237 lines
15 KiB
C
237 lines
15 KiB
C
/**************************************************************************//**
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* @file acmp_reg.h
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* @version V1.00
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* @brief ACMP register definition header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __ACMP_REG_H__
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#define __ACMP_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/**
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@addtogroup REGISTER Control Register
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@{
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*/
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/**
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@addtogroup ACMP Analog Comparator Controller (ACMP)
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Memory Mapped Structure for ACMP Controller
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@{
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*/
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typedef struct
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{
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/**
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* @var ACMP_T::CTL
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* Offset: 0x00~0x04 Analog Comparator 0/1 Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |ACMPEN |Comparator Enable Bit
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* | | |0 = Comparator x Disabled.
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* | | |1 = Comparator x Enabled.
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* |[1] |ACMPIE |Comparator Interrupt Enable Bit
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* | | |0 = Comparator x interrupt Disabled.
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* | | |1 = Comparator x interrupt Enabled
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* | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
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* |[3] |ACMPOINV |Comparator Output Inverse
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* | | |0 = Comparator x output inverse Disabled.
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* | | |1 = Comparator x output inverse Enabled.
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* |[5:4] |NEGSEL |Comparator Negative Input Selection
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* | | |00 = ACMPx_N pin.
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* | | |01 = Internal comparator reference voltage (CRV).
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* | | |10 = Band-gap voltage.
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* | | |11 = DAC output.
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* |[7:6] |POSSEL |Comparator Positive Input Selection
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* | | |00 = Input from ACMPx_P0.
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* | | |01 = Input from ACMPx_P1.
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* | | |10 = Input from ACMPx_P2.
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* | | |11 = Input from ACMPx_P3.
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* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
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* | | |ACMPIFx will be set to 1 when comparator output edge condition is detected.
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* | | |00 = Rising edge or falling edge.
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* | | |01 = Rising edge.
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* | | |10 = Falling edge.
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* | | |11 = Reserved.
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* |[12] |OUTSEL |Comparator Output Select
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* | | |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output.
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* | | |1 = Comparator x output to ACMPx_O pin is from filter output.
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* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
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* | | |000 = Filter function is Disabled.
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* | | |001 = ACMPx output is sampled 1 consecutive PCLK.
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* | | |010 = ACMPx output is sampled 2 consecutive PCLKs.
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* | | |011 = ACMPx output is sampled 4 consecutive PCLKs.
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* | | |100 = ACMPx output is sampled 8 consecutive PCLKs.
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* | | |101 = ACMPx output is sampled 16 consecutive PCLKs.
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* | | |110 = ACMPx output is sampled 32 consecutive PCLKs.
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* | | |111 = ACMPx output is sampled 64 consecutive PCLKs.
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* |[16] |WKEN |Power-down Wake-up Enable Bit
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* | | |0 = Wake-up function Disabled.
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* | | |1 = Wake-up function Enabled.
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* |[17] |WLATEN |Window Latch Mode Enable Bit
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* | | |0 = Window Latch Mode Disabled.
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* | | |1 = Window Latch Mode Enabled.
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* |[18] |WCMPSEL |Window Compare Mode Selection
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* | | |0 = Window Compare Mode Disabled.
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* | | |1 = Window Compare Mode is Selected.
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* |[25:24] |HYSSEL |Hysteresis Mode Selection
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* | | |00 = Hysteresis is 0mV.
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* | | |01 = Hysteresis is 10mV.
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* | | |10 = Hysteresis is 20mV.
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* | | |11 = Hysteresis is 30mV.
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* |[29:28] |MODESEL |Propagation Delay Mode Selection
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* | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
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* | | |01 = Max propagation delay is 2uS, operation current is 3uA.
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* | | |10 = Max propagation delay is 600nS, operation current is 10uA.
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* | | |11 = Max propagation delay is 200nS, operation current is 75uA.
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* @var ACMP_T::STATUS
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* Offset: 0x08 Analog Comparator Status Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
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* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output.
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* | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
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* | | |Note: Write 1 to clear this bit to 0.
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* |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
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* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
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* | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
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* | | |Note: Write 1 to clear this bit to 0.
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* |[4] |ACMPO0 |Comparator 0 Output
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* | | |Synchronized to the PCLK to allow reading by software.
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* | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
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* |[5] |ACMPO1 |Comparator 1 Output
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* | | |Synchronized to the PCLK to allow reading by software.
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* | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
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* |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
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* | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
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* | | |0 = No power-down wake-up occurred.
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* | | |1 = Power-down wake-up occurred.
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* | | |Note: Write 1 to clear this bit to 0.
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* |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
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* | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
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* | | |0 = No power-down wake-up occurred.
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* | | |1 = Power-down wake-up occurred.
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* | | |Note: Write 1 to clear this bit to 0.
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* |[12] |ACMPS0 |Comparator 0 Status
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* | | |Synchronized to the PCLK to allow reading by software.
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* | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
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* |[13] |ACMPS1 |Comparator 1 Status
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* | | |Synchronized to the PCLK to allow reading by software
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* | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
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* |[16] |ACMPWO |Comparator Window Output
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* | | |This bit shows the output status of window compare mode
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* | | |0 = The positive input voltage is outside the window.
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* | | |1 = The positive input voltage is in the window.
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* @var ACMP_T::VREF
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* Offset: 0x0C Analog Comparator Reference Voltage Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[3:0] |CRVCTL |Comparator Reference Voltage Setting
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* | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
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* |[6] |CRVSSEL |CRV Source Voltage Selection
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* | | |0 = AVDD is selected as CRV source voltage.
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* | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
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*/
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__IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */
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__IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
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__IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
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} ACMP_T;
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/**
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@addtogroup ACMP_CONST ACMP Bit Field Definition
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Constant Definitions for ACMP Controller
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@{ */
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#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
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#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
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#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
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#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
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#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
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#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
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#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
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#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
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#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
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#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
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#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
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#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
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#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
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#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
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#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
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#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
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#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
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#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
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#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */
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#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */
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#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */
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#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */
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#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */
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#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */
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#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */
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#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */
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#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
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#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
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#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
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#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
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#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
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#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
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#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
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#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
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#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
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#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
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#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
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#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
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#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
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#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
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#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
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#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
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#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
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#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
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#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
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#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
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#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
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#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
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/** @} ACMP_CONST */
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/** @} end of ACMP register group */
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/** @} end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif /* __ACMP_REG_H__ */
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