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594 lines
47 KiB
C
594 lines
47 KiB
C
/**************************************************************************//**
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* @file qspi_reg.h
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* @version V1.00
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* @brief QSPI register definition header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __QSPI_REG_H__
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#define __QSPI_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/**
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@addtogroup REGISTER Control Register
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@{
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*/
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/**
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@addtogroup QSPI Quad Serial Peripheral Interface Controller (QSPI)
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Memory Mapped Structure for QSPI Controller
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@{
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*/
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typedef struct
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{
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/**
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* @var QSPI_T::CTL
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* Offset: 0x00 QSPI Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |QSPIEN |QSPI Transfer Control Enable Bit
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* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
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* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
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* | | |0 = Transfer control Disabled.
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* | | |1 = Transfer control Enabled.
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* | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the QSPIEN (QSPIx_CTL[0]) and confirm the QSPIENSTS (QSPIx_STATUS[15]) is 0.
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* |[1] |RXNEG |Receive on Negative Edge
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* | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock.
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* | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock.
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* |[2] |TXNEG |Transmit on Negative Edge
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* | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.
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* | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
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* |[3] |CLKPOL |Clock Polarity
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* | | |0 = QSPI bus clock is idle low.
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* | | |1 = QSPI bus clock is idle high.
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* |[7:4] |SUSPITV |Suspend Interval (Master Only)
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* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
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* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
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* | | |The default value is 0x3
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* | | |The period of the suspend interval is obtained according to the following equation.
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* | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle
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* | | |Example:
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* | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle.
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* | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle.
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* | | |.....
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* | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle.
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* | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.
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* |[12:8] |DWIDTH |Data Width
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* | | |This field specifies how many bits can be transmitted / received in one transaction
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* | | |The minimum bit length is 8 bits and can up to 32 bits.
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* | | |DWIDTH = 0x08 .... 8 bits.
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* | | |DWIDTH = 0x09 .... 9 bits.
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* | | |.....
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* | | |DWIDTH = 0x1F .... 31 bits.
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* | | |DWIDTH = 0x00 .... 32 bits.
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* |[13] |LSB |Send LSB First
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* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
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* | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).
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* |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit
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* | | |This bit is used to select full-duplex or half-duplex for QSPI transfer
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* | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
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* | | |0 = QSPI operates in full-duplex transfer.
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* | | |1 = QSPI operates in half-duplex transfer.
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* |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
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* | | |This bit field is only available in Master mode
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* | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.
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* | | |0 = Receive-only mode Disabled.
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* | | |1 = Receive-only mode Enabled.
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* |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in QSPI0)
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* | | |0 = 2-Bit Transfer mode Disabled.
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* | | |1 = 2-Bit Transfer mode Enabled.
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* | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
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* | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
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* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
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* | | |0 = QSPI unit transfer interrupt Disabled.
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* | | |1 = QSPI unit transfer interrupt Enabled.
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* |[18] |SLAVE |Slave Mode Control
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* | | |0 = Master mode.
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* | | |1 = Slave mode.
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* |[19] |REORDER |Byte Reorder Function Enable Bit
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* | | |0 = Byte Reorder function Disabled.
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* | | |1 = Byte Reorder function Enabled
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* | | |A byte suspend interval will be inserted among each byte
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* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
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* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
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* |[20] |DATDIR |Data Port Direction Control
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* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
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* | | |0 = QSPI data is input direction.
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* | | |1 = QSPI data is output direction.
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* |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in QSPI0)
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* | | |0 = Dual I/O mode Disabled.
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* | | |1 = Dual I/O mode Enabled.
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* |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in QSPI0)
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* | | |0 = Quad I/O mode Disabled.
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* | | |1 = Quad I/O mode Enabled.
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* @var QSPI_T::CLKDIV
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* Offset: 0x04 QSPI Clock Divider Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[8:0] |DIVIDER |Clock Divider
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* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master
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* | | |The frequency is obtained according to the following equation.
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* | | |where
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* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
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* @var QSPI_T::SSCTL
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* Offset: 0x08 QSPI Slave Select Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |SS |Slave Selection Control (Master Only)
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* | | |If AUTOSS bit is cleared to 0,
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* | | |0 = set the QSPIx_SS line to inactive state.
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* | | |1 = set the QSPIx_SS line to active state.
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* | | |If the AUTOSS bit is set to 1,
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* | | |0 = Keep the QSPIx_SS line at inactive state.
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* | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
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* | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).
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* |[2] |SSACTPOL |Slave Selection Active Polarity
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* | | |This bit defines the active polarity of slave selection signal (QSPIx_SS).
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* | | |0 = The slave selection signal QSPIx_SS is active low.
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* | | |1 = The slave selection signal QSPIx_SS is active high.
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* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
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* | | |0 = Automatic slave selection function Disabled
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* | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]).
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* | | |1 = Automatic slave selection function Enabled.
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* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in QSPI0)
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* | | |Slave 3-wire mode is only available in QSPI0
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* | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins.
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* | | |0 = 4-wire bi-direction interface.
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* | | |1 = 3-wire bi-direction interface.
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* |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0)
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* | | |0 = Slave mode time-out interrupt Disabled.
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* | | |1 = Slave mode time-out interrupt Enabled.
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* |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in QSPI0)
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* | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
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* | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
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* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
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* | | |0 = Slave mode bit count error interrupt Disabled.
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* | | |1 = Slave mode bit count error interrupt Enabled.
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* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
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* | | |0 = Slave mode TX under run interrupt Disabled.
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* | | |1 = Slave mode TX under run interrupt Enabled.
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* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
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* | | |0 = Slave select active interrupt Disabled.
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* | | |1 = Slave select active interrupt Enabled.
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* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
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* | | |0 = Slave select inactive interrupt Disabled.
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* | | |1 = Slave select inactive interrupt Enabled.
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* |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in QSPI0)
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* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
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* | | |The clock source of the time-out counter is Slave peripheral clock
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* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
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* @var QSPI_T::PDMACTL
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* Offset: 0x0C QSPI PDMA Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
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* | | |0 = Transmit PDMA function Disabled.
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* | | |1 = Transmit PDMA function Enabled.
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* | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
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* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
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* |[1] |RXPDMAEN |Receive PDMA Enable Bit
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* | | |0 = Receive PDMA function Disabled.
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* | | |1 = Receive PDMA function Enabled.
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* |[2] |PDMARST |PDMA Reset
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* | | |0 = No effect.
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* | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.
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* @var QSPI_T::FIFOCTL
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* Offset: 0x10 QSPI FIFO Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |RXRST |Receive Reset
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* | | |0 = No effect.
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* | | |1 = Reset receive FIFO pointer and receive circuit
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* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
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* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
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* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
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* |[1] |TXRST |Transmit Reset
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* | | |0 = No effect.
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* | | |1 = Reset transmit FIFO pointer and transmit circuit
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* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
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* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
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* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
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* | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
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* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
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* | | |0 = RX FIFO threshold interrupt Disabled.
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* | | |1 = RX FIFO threshold interrupt Enabled.
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* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
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* | | |0 = TX FIFO threshold interrupt Disabled.
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* | | |1 = TX FIFO threshold interrupt Enabled.
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* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
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* | | |0 = Receive time-out interrupt Disabled.
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* | | |1 = Receive time-out interrupt Enabled.
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* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
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* | | |0 = Receive FIFO overrun interrupt Disabled.
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* | | |1 = Receive FIFO overrun interrupt Enabled.
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* |[6] |TXUFPOL |TX Underflow Data Polarity
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* | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode.
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* | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode.
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* | | |Note:
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* | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
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* | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
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* | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
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* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
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* | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1
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* | | |This bit is used to enable the TX underflow interrupt.
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* | | |0 = Slave TX underflow interrupt Disabled.
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* | | |1 = Slave TX underflow interrupt Enabled.
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* |[8] |RXFBCLR |Receive FIFO Buffer Clear
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* | | |0 = No effect.
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* | | |1 = Clear receive FIFO pointer
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* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
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* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
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* | | |Note: The RX shift register will not be cleared.
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* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
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* | | |0 = No effect.
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* | | |1 = Clear transmit FIFO pointer
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* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
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* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
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* | | |Note: The TX shift register will not be cleared.
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* |[26:24] |RXTH |Receive FIFO Threshold
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* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
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* |[30:28] |TXTH |Transmit FIFO Threshold
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* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
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* @var QSPI_T::STATUS
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* Offset: 0x14 QSPI Status Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |BUSY |Busy Status (Read Only)
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* | | |0 = QSPI controller is in idle state.
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* | | |1 = QSPI controller is in busy state.
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* | | |The following listing are the bus busy conditions:
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* | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0.
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* | | |b
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* | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
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* | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1.
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* | | |d
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* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active.
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* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
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* |[1] |UNITIF |Unit Transfer Interrupt Flag
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* | | |0 = No transaction has been finished since this bit was cleared to 0.
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* | | |1 = QSPI controller has finished one unit transfer.
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* | | |Note: This bit will be cleared by writing 1 to it.
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* |[2] |SSACTIF |Slave Select Active Interrupt Flag
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* | | |0 = Slave select active interrupt was cleared or not occurred.
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* | | |1 = Slave select active interrupt event occurred.
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* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
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* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
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* | | |0 = Slave select inactive interrupt was cleared or not occurred.
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* | | |1 = Slave select inactive interrupt event occurred.
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* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
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* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
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* | | |0 = The slave select line status is 0.
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* | | |1 = The slave select line status is 1.
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* | | |Note: This bit is only available in Slave mode
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* | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
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* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in QSPI0)
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* | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started
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* | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
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* | | |0 = Slave time-out is not active.
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* | | |1 = Slave time-out is active.
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* | | |Note: This bit will be cleared by writing 1 to it.
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* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
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* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
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* | | |0 = No Slave mode bit count error event.
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* | | |1 = Slave mode bit count error event occurs.
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* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
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* | | |This bit will be cleared by writing 1 to it.
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* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
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* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
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* | | |0 = No Slave TX under run event.
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* | | |1 = Slave TX under run event occurs.
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* | | |Note: This bit will be cleared by writing 1 to it.
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* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
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* | | |0 = Receive FIFO buffer is not empty.
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* | | |1 = Receive FIFO buffer is empty.
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* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
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* | | |0 = Receive FIFO buffer is not full.
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* | | |1 = Receive FIFO buffer is full.
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* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
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* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
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* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
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* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
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* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
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* | | |0 = No FIFO is overrun.
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* | | |1 = Receive FIFO is overrun.
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* | | |Note: This bit will be cleared by writing 1 to it.
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* |[12] |RXTOIF |Receive Time-out Interrupt Flag
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* | | |0 = No receive FIFO time-out event.
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* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode
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* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
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* | | |Note: This bit will be cleared by writing 1 to it.
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* |[15] |QSPIENSTS |QSPI Enable Status (Read Only)
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* | | |0 = The QSPI controller is disabled.
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* | | |1 = The QSPI controller is enabled.
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* | | |Note: The QSPI peripheral clock is asynchronous with the system clock
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* | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
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* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
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* | | |0 = Transmit FIFO buffer is not empty.
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* | | |1 = Transmit FIFO buffer is empty.
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* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
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* | | |0 = Transmit FIFO buffer is not full.
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* | | |1 = Transmit FIFO buffer is full.
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* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
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* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
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* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
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* |[19] |TXUFIF |TX Underflow Interrupt Flag
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* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
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* | | |0 = No effect.
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* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
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* | | |Note 1: This bit will be cleared by writing 1 to it.
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* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
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* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
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* | | |0 = The reset function of TXRST or RXRST is done.
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* | | |1 = Doing the reset function of TXRST or RXRST.
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* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
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* | | |User can check the status of this bit to monitor the reset function is doing or done.
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* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
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* | | |This bit field indicates the valid data count of receive FIFO buffer.
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* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
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* | | |This bit field indicates the valid data count of transmit FIFO buffer.
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* @var QSPI_T::TX
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* Offset: 0x20 QSPI Data Transmit Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |TX |Data Transmit Register
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* | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
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* | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.
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* | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
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* | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer.
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* | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid
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* | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
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* @var QSPI_T::RX
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* Offset: 0x30 QSPI Data Receive Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |RX |Data Receive Register
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* | | |There are 4-level FIFO buffers in this controller
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* | | |The data receive register holds the data received from QSPI data input pin
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* | | |This is a read only register.
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*/
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__IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */
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__IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */
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__IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */
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__IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */
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__IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */
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__IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE0[2];
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/// @endcond //HIDDEN_SYMBOLS
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__O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE1[3];
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/// @endcond //HIDDEN_SYMBOLS
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__I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */
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} QSPI_T;
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/**
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@addtogroup QSPI_CONST QSPI Bit Field Definition
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Constant Definitions for QSPI Controller
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@{ */
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#define QSPI_CTL_QSPIEN_Pos (0) /*!< QSPI_T::CTL: QSPIEN Position */
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#define QSPI_CTL_QSPIEN_Msk (0x1ul << QSPI_CTL_QSPIEN_Pos) /*!< QSPI_T::CTL: QSPIEN Mask */
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#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */
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#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */
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#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */
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#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */
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#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */
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#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */
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#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */
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#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */
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#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */
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#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */
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#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */
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#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */
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#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */
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#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */
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#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */
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#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */
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#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */
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#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */
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#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */
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#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */
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#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */
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#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */
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#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */
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#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */
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#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */
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#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */
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#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */
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#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */
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#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */
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#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */
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#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */
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#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */
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#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */
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#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */
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#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */
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#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */
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#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */
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#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */
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#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */
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#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */
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#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */
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#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */
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#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */
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#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */
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#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */
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#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */
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#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */
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#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */
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#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */
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#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */
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#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */
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#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */
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#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */
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#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */
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#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */
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#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */
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|
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#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */
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#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */
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#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */
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#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */
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#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */
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#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */
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#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */
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#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */
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#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */
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#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */
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#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */
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#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */
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#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */
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#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */
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#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */
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#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */
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#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */
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#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */
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#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */
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#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */
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#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */
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#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */
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#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */
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#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */
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#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */
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#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */
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#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */
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#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */
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#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */
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#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */
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#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */
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#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */
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#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */
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#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */
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#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */
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#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */
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#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */
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#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */
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#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */
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#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */
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#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */
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#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */
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#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */
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#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */
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#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */
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#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */
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#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */
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#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */
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#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */
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#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */
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#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */
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#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */
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#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */
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#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */
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#define QSPI_STATUS_QSPIENSTS_Pos (15) /*!< QSPI_T::STATUS: QSPIENSTS Position */
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#define QSPI_STATUS_QSPIENSTS_Msk (0x1ul << QSPI_STATUS_QSPIENSTS_Pos) /*!< QSPI_T::STATUS: QSPIENSTS Mask */
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#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */
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#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */
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#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */
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#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */
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#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */
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#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */
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#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */
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#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */
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#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */
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#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */
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#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */
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#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */
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#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */
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#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */
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#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */
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#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */
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#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */
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#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */
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/** @} QSPI_CONST */
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/** @} end of QSPI register group */
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/** @} end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif /* __QSPI_REG_H__ */
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