Build updated MainCode image (matches Mac OS ROM 9.6.1+)
This commit is contained in:
Elliot Nunn
parent
283a0c5ba8
commit
1c43f478a3
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@ -22,8 +22,8 @@ BackLightDir = {DriverDir}BackLight:
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#include {SonyDir}Sony.make
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#include {SerialDir}Serial.make
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#include {SerialDMADir}SerialDMA.make
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##include {SerialDir}Serial.make
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##include {SerialDMADir}SerialDMA.make
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#include {NewAgeDir}NewAge.make
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@ -674,7 +674,7 @@ btQType EQU 21 ; B*Tree Manager
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; Device Control Entry Definition
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;dCtlEntrySize used to be only 40 bytes!
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dCtlEntrySize EQU $34 ; length of a DCE [52 bytes]
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dCtlEntrySize EQU $38 ; length of a DCE [52 bytes]
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dCtlDriver EQU 0 ; driver [handle]
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dCtlFlags EQU 4 ; flags [word]
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dCtlQueue EQU 6 ; queue header
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@ -53,7 +53,7 @@ resetCmd EQU $00 ; Command for Bus Reset
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kbdAddr EQU $02 ; keyboard type device
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mouseAddr EQU $03 ; mouse type device
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numFDBAdr EQU 16 ; number of avaiblae FDB address
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moveTime EQU 50 ; number of times to move device
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moveTime EQU 10 ; number of times to move device
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IF IopADB THEN
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@ -90,6 +90,8 @@ denom ds.w 1 ; Private: fraction of the errors to use next time
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spread ds.w 1 ; Private: Number of samples to spread errors over
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newData ds.b 1 ; Private: set when deltas are new
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ds.b 1 ; align
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ds.b 4 ; new
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CrsrDevSize EQU *
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ENDR
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@ -231,41 +231,110 @@ DockingGlobals EQU $1FF8 ; pointer to docking globals <H12>
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;_______________________________________________________________________
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; Processor Info Record
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;
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; Used to pass Processor information from the NanoKernel to user mode
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; software.
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; Configuration Info Record
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; Used to pass Configuration information from the Boot Program to the
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; NanoKernel for data structure and address mapping initialization.
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;_______________________________________________________________________
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ProcessorInfoPtr equ $5FFFEFD8 ; logical address of ProcessorInfo record
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ProcessorInfoVer equ $5FFFEFDC ; version number of ProcessorInfo record
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ProcessorInfoLen equ $5FFFEFDE ; length of ProcessorInfo record
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NKConfigurationInfo record 0,increment
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ROMByteCheckSums ds.l 8 ; 000 ; ROM Checksums - one word for each of 8 byte lanes
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ROMCheckSum64 ds.l 2 ; 020 ; ROM Checksum - 64 bit sum of doublewords
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ProcessorInfo record 0,increment
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ProcessorVersionReg ds.l 1 ; contents of the PVR special purpose register
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CpuClockRateHz ds.l 1 ; CPU Clock frequency
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BusClockRateHz ds.l 1 ; Bus Clock frequency
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DecClockRateHz ds.l 1 ; Decrementer Clock frequency
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PageSize ds.l 1 ; number of bytes in a memory page
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DataCacheTotalSize ds.l 1 ; number of bytes in the Data Cache
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InstCacheTotalSize ds.l 1 ; number of bytes in the Instruction Cache
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CoherencyBlockSize ds.w 1 ; number of bytes in a Coherency Block
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ReservationGranuleSize ds.w 1 ; number of bytes in a Reservation Granule
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CombinedCaches ds.w 1 ; 1 <- combined or no cache, 0 <- split cache
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InstCacheLineSize ds.w 1 ; number of bytes in a Line of the Instruction Cache
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DataCacheLineSize ds.w 1 ; number of bytes in a Line of the Data Cache
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DataCacheBlockSizeTouch ds.w 1 ; number of bytes in a Block for DCBT DCBTST
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InstCacheBlockSize ds.w 1 ; number of bytes in a Block of the Instruction Cache
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DataCacheBlockSize ds.w 1 ; number of bytes in a Block of the Data Cache
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InstCacheAssociativity ds.w 1 ; Associativity of the Instruction Cache
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DataCacheAssociativity ds.w 1 ; Associativity of the Data Cache
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ROMImageBaseOffset ds.l 1 ; 028 ; Offset of Base of total ROM image
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ROMImageSize ds.l 1 ; 02c ; Number of bytes in ROM image
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ROMImageVersion ds.l 1 ; 030 ; ROM Version number for entire ROM
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TransCacheTotalSize ds.w 1 ; number of entries in the Translation Cache
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TransCacheAssociativity ds.w 1 ; Associativity of the Translation Cache
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align 32 ; pad to nice cache block alignment
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Size equ *-ProcessorInfo
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Mac68KROMOffset ds.l 1 ; 034 ; Offset of base of Macintosh 68K ROM
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Mac68KROMSize ds.l 1 ; 038 ; Number of bytes in Macintosh 68K ROM
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ExceptionTableOffset ds.l 1 ; 03c ; Offset of base of PowerPC Exception Table Code
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ExceptionTableSize ds.l 1 ; 040 ; Number of bytes in PowerPC Exception Table Code
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HWInitCodeOffset ds.l 1 ; 044 ; Offset of base of Hardware Init Code (field moved!)
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HWInitCodeSize ds.l 1 ; 048 ; Number of bytes in Hardware Init Code
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KernelCodeOffset ds.l 1 ; 04c ; Offset of base of NanoKernel Code
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KernelCodeSize ds.l 1 ; 050 ; Number of bytes in NanoKernel Code
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EmulatorCodeOffset ds.l 1 ; 054 ; Offset of base of Emulator Code
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EmulatorCodeSize ds.l 1 ; 058 ; Number of bytes in Emulator Code
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OpcodeTableOffset ds.l 1 ; 05c ; Offset of base of Opcode Table
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OpcodeTableSize ds.l 1 ; 060 ; Number of bytes in Opcode Table
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BootstrapVersion ds.b 16 ; 064 ; Bootstrap loader version info
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BootVersionOffset ds.l 1 ; 074 ; offset within EmulatorData of BootstrapVersion
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ECBOffset ds.l 1 ; 078 ; offset within EmulatorData of ECB
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IplValueOffset ds.l 1 ; 07c ; offset within EmulatorData of IplValue
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EmulatorEntryOffset ds.l 1 ; 080 ; offset within Emulator Code of entry point
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KernelTrapTableOffset ds.l 1 ; 084 ; offset within Emulator Code of KernelTrapTable
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TestIntMaskInit ds.l 1 ; 088 ; initial value for test interrupt mask
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ClearIntMaskInit ds.l 1 ; 08c ; initial value for clear interrupt mask
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PostIntMaskInit ds.l 1 ; 090 ; initial value for post interrupt mask
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LA_InterruptCtl ds.l 1 ; 094 ; logical address of Interrupt Control I/O page
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InterruptHandlerKind ds.b 1 ; 098 ; kind of handler to use
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ds.b 3 ; 099 ; filler
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LA_InfoRecord ds.l 1 ; 09c ; logical address of InfoRecord page
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LA_KernelData ds.l 1 ; 0a0 ; logical address of KernelData page
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LA_EmulatorData ds.l 1 ; 0a4 ; logical address of EmulatorData page
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LA_DispatchTable ds.l 1 ; 0a8 ; logical address of Dispatch Table
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LA_EmulatorCode ds.l 1 ; 0ac ; logical address of Emulator Code
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MacLowMemInitOffset ds.l 1 ; 0b0 ; offset to list of LowMem addr/data values
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PageAttributeInit ds.l 1 ; 0b4 ; default WIMG/PP settings for PTE creation
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PageMapInitSize ds.l 1 ; 0b8 ; size of page mapping info
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PageMapInitOffset ds.l 1 ; 0bc ; offset to page mapping info (from base of ConfigInfo)
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PageMapIRPOffset ds.l 1 ; 0c0 ; offset of InfoRecord map info (from base of PageMap)
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PageMapKDPOffset ds.l 1 ; 0c4 ; offset of KernelData map info (from base of PageMap)
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PageMapEDPOffset ds.l 1 ; 0c8 ; offset of EmulatorData map info (from base of PageMap)
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SegMaps
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SegMap32SupInit ds.l 32 ; 0cc ; 32 bit mode Segment Map Supervisor space
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SegMap32UsrInit ds.l 32 ; 14c ; 32 bit mode Segment Map User space
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SegMap32CPUInit ds.l 32 ; 1cc ; 32 bit mode Segment Map CPU space
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SegMap32OvlInit ds.l 32 ; 24c ; 32 bit mode Segment Map Overlay mode
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BATRangeInit ds.l 32 ; 2cc ; BAT mapping ranges
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BatMap32SupInit ds.l 1 ; 34c ; 32 bit mode BAT Map Supervisor space
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BatMap32UsrInit ds.l 1 ; 350 ; 32 bit mode BAT Map User space
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BatMap32CPUInit ds.l 1 ; 354 ; 32 bit mode BAT Map CPU space
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BatMap32OvlInit ds.l 1 ; 358 ; 32 bit mode BAT Map Overlay mode
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SharedMemoryAddr ds.l 1 ; 35c ; physical address of Mac/Smurf shared message mem
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PA_RelocatedLowMemInit ds.l 1 ; 360 ; physical address of RelocatedLowMem
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OpenFWBundleOffset ds.l 1 ; 364 ; Offset of base of OpenFirmware PEF Bundle
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OpenFWBundleSize ds.l 1 ; 368 ; Number of bytes in OpenFirmware PEF Bundle
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LA_OpenFirmware ds.l 1 ; 36c ; logical address of Open Firmware
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PA_OpenFirmware ds.l 1 ; 370 ; physical address of Open Firmware
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LA_HardwarePriv ds.l 1 ; 374 ; logical address of HardwarePriv callback
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; Used to stop here, plus 8 bytes for cache block alignment (0x380 bytes).
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; Now there be more!
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Debug ds.w 1 ; 378 ; > 256 required for screen log
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DebugThreshold equ 257
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org $388
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DebugFlags ds.l 1 ; 388 ; bit 1<< 1 required for screen log
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NanodbgrFlagShift equ 0
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NanodbgrFlagBit equ 31 - NanodbgrFlagShift
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LogFlagShift equ 1
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LogFlagBit equ 31 - LogFlagShift
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org $100
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Size equ *
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endr
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;_______________________________________________________________________
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; System Info Record
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;
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@ -273,70 +342,112 @@ Size equ *-ProcessorInfo
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; software.
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;_______________________________________________________________________
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NKSystemInfoPtr equ $5FFFEFF0 ; logical address of NKSystemInfo record
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NKSystemInfoVer equ $5FFFEFF4 ; version number of NKSystemInfo record
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NKSystemInfoLen equ $5FFFEFF6 ; length of NKSystemInfo record
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NKSystemInfoPtr equ $68FFEFF0 ; logical address of NKSystemInfo record
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NKSystemInfoVer equ $68FFEFF4 ; version number of NKSystemInfo record
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NKSystemInfoLen equ $68FFEFF6 ; length of NKSystemInfo record
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NKSystemInfo record 0,increment
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PhysicalMemorySize ds.l 1 ; Number of bytes in Physical RAM
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UsableMemorySize ds.l 1 ; Number of bytes in Usable RAM
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LogicalMemorySize ds.l 1 ; Number of bytes in Logical RAM
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HashTableSize ds.l 1 ; Number of bytes in Memory Hash Table
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PhysicalMemorySize ds.l 1 ; 000, irp+dc0 ; Number of bytes in Physical RAM
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UsableMemorySize ds.l 1 ; 004, irp+dc4 ; Number of bytes in Usable RAM
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LogicalMemorySize ds.l 1 ; 008, irp+dc8 ; Number of bytes in Logical RAM
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HashTableSize ds.l 1 ; 00c, irp+dcc ; Number of bytes in Memory Hash Table
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L2DataCacheTotalSize ds.l 1 ; number of bytes in the L2 Data Cache
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L2InstCacheTotalSize ds.l 1 ; number of bytes in the L2 Instruction Cache
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L2CombinedCaches ds.w 1 ; 1 <- combined or no cache, 0 <- split cache
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L2InstCacheBlockSize ds.w 1 ; number of bytes in a Block of the L2 Instruction Cache
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L2DataCacheBlockSize ds.w 1 ; number of bytes in a Block of the L2 Data Cache
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L2InstCacheAssociativity ds.w 1 ; Associativity of the L2 Instruction Cache
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L2DataCacheAssociativity ds.w 1 ; Associativity of the L2 Data Cache
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ds.b 2 ; unused
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L2DataCacheTotalSize ds.l 1 ; 010, irp+dd0 ; number of bytes in the L2 Data Cache
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L2InstCacheTotalSize ds.l 1 ; 014, irp+dd4 ; number of bytes in the L2 Instruction Cache
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L2CombinedCaches ds.w 1 ; 018, irp+dd8 ; 1 <- combined or no cache, 0 <- split cache
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L2InstCacheBlockSize ds.w 1 ; 01a, irp+dda ; number of bytes in a Block of the L2 Instruction Cache
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L2DataCacheBlockSize ds.w 1 ; 01c, irp+ddc ; number of bytes in a Block of the L2 Data Cache
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L2InstCacheAssociativity ds.w 1 ; 01e, irp+dde ; Associativity of the L2 Instruction Cache
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L2DataCacheAssociativity ds.w 1 ; 020, irp+de0 ; Associativity of the L2 Data Cache
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ds.b 2 ; 022, irp+de2 ; unused
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ds.b 2 ; unused
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FlashManufacturerCode ds.b 1 ; Flash ROM Manufacturer code
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FlashDeviceCode ds.b 1 ; Flash ROM Device code
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FlashStart ds.l 1 ; Starting address of Flash ROM
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FlashSize ds.l 1 ; Number of bytes in Flash ROM
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ds.b 2 ; 024, irp+de4 ; unused
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FlashManufacturerCode ds.b 1 ; 026, irp+de6 ; Flash ROM Manufacturer code
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FlashDeviceCode ds.b 1 ; 027, irp+de7 ; Flash ROM Device code
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FlashStart ds.l 1 ; 028, irp+de8 ; Starting address of Flash ROM
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FlashSize ds.l 1 ; 02c, irp+dec ; Number of bytes in Flash ROM
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align 16
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Bank0Start ds.l 1 ; Starting address of RAM bank 0
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Bank0Size ds.l 1 ; Number of bytes in RAM bank 0
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Bank1Start ds.l 1 ; Starting address of RAM bank 1
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Bank1Size ds.l 1 ; Number of bytes in RAM bank 1
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Bank2Start ds.l 1 ; Starting address of RAM bank 2
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Bank2Size ds.l 1 ; Number of bytes in RAM bank 2
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Bank3Start ds.l 1 ; Starting address of RAM bank 3
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Bank3Size ds.l 1 ; Number of bytes in RAM bank 3
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Bank4Start ds.l 1 ; Starting address of RAM bank 4
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Bank4Size ds.l 1 ; Number of bytes in RAM bank 4
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Bank5Start ds.l 1 ; Starting address of RAM bank 5
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Bank5Size ds.l 1 ; Number of bytes in RAM bank 5
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Bank6Start ds.l 1 ; Starting address of RAM bank 6
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Bank6Size ds.l 1 ; Number of bytes in RAM bank 6
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Bank7Start ds.l 1 ; Starting address of RAM bank 7
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Bank7Size ds.l 1 ; Number of bytes in RAM bank 7
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Bank8Start ds.l 1 ; Starting address of RAM bank 8
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Bank8Size ds.l 1 ; Number of bytes in RAM bank 8
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Bank9Start ds.l 1 ; Starting address of RAM bank 9
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Bank9Size ds.l 1 ; Number of bytes in RAM bank 9
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Bank10Start ds.l 1 ; Starting address of RAM bank 10
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Bank10Size ds.l 1 ; Number of bytes in RAM bank 10
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Bank11Start ds.l 1 ; Starting address of RAM bank 11
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Bank11Size ds.l 1 ; Number of bytes in RAM bank 11
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Bank12Start ds.l 1 ; Starting address of RAM bank 12
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Bank12Size ds.l 1 ; Number of bytes in RAM bank 12
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Bank13Start ds.l 1 ; Starting address of RAM bank 13
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Bank13Size ds.l 1 ; Number of bytes in RAM bank 13
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Bank14Start ds.l 1 ; Starting address of RAM bank 14
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Bank14Size ds.l 1 ; Number of bytes in RAM bank 14
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Bank15Start ds.l 1 ; Starting address of RAM bank 15
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Bank15Size ds.l 1 ; Number of bytes in RAM bank 15
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align 32 ; pad to nice cache block alignment
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MaxBanks equ 16 ; 16 banks, 0É15
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Size equ *-SystemInfo
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Bank0Start ds.l 1 ; 030, irp+df0 ; Starting address of RAM bank 0
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Bank0Size ds.l 1 ; 034, irp+df4 ; Number of bytes in RAM bank 0
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Bank1Start ds.l 1 ; 038, irp+df8 ; Starting address of RAM bank 1
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Bank1Size ds.l 1 ; 03c, irp+dfc ; Number of bytes in RAM bank 1
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Bank2Start ds.l 1 ; 040, irp+e00 ; Starting address of RAM bank 2
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Bank2Size ds.l 1 ; 044, irp+e04 ; Number of bytes in RAM bank 2
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Bank3Start ds.l 1 ; 048, irp+e08 ; Starting address of RAM bank 3
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Bank3Size ds.l 1 ; 04c, irp+e0c ; Number of bytes in RAM bank 3
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Bank4Start ds.l 1 ; 050, irp+e10 ; Starting address of RAM bank 4
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Bank4Size ds.l 1 ; 054, irp+e14 ; Number of bytes in RAM bank 4
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Bank5Start ds.l 1 ; 058, irp+e18 ; Starting address of RAM bank 5
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Bank5Size ds.l 1 ; 05c, irp+e1c ; Number of bytes in RAM bank 5
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Bank6Start ds.l 1 ; 060, irp+e20 ; Starting address of RAM bank 6
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Bank6Size ds.l 1 ; 064, irp+e24 ; Number of bytes in RAM bank 6
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Bank7Start ds.l 1 ; 068, irp+e28 ; Starting address of RAM bank 7
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Bank7Size ds.l 1 ; 06c, irp+e2c ; Number of bytes in RAM bank 7
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Bank8Start ds.l 1 ; 070, irp+e30 ; Starting address of RAM bank 8
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Bank8Size ds.l 1 ; 074, irp+e34 ; Number of bytes in RAM bank 8
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Bank9Start ds.l 1 ; 078, irp+e38 ; Starting address of RAM bank 9
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Bank9Size ds.l 1 ; 07c, irp+e3c ; Number of bytes in RAM bank 9
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Bank10Start ds.l 1 ; 080, irp+e40 ; Starting address of RAM bank 10
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Bank10Size ds.l 1 ; 084, irp+e44 ; Number of bytes in RAM bank 10
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Bank11Start ds.l 1 ; 088, irp+e48 ; Starting address of RAM bank 11
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Bank11Size ds.l 1 ; 08c, irp+e4c ; Number of bytes in RAM bank 11
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Bank12Start ds.l 1 ; 090, irp+e50 ; Starting address of RAM bank 12
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Bank12Size ds.l 1 ; 094, irp+e54 ; Number of bytes in RAM bank 12
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Bank13Start ds.l 1 ; 098, irp+e58 ; Starting address of RAM bank 13
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Bank13Size ds.l 1 ; 09c, irp+e5c ; Number of bytes in RAM bank 13
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Bank14Start ds.l 1 ; 0a0, irp+e60 ; Starting address of RAM bank 14
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Bank14Size ds.l 1 ; 0a4, irp+e64 ; Number of bytes in RAM bank 14
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Bank15Start ds.l 1 ; 0a8, irp+e68 ; Starting address of RAM bank 15
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Bank15Size ds.l 1 ; 0ac, irp+e6c ; Number of bytes in RAM bank 15
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Bank16Start ds.l 1 ; 0b0, irp+e70 ; Starting address of RAM bank 16
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Bank16Size ds.l 1 ; 0b4, irp+e74 ; Number of bytes in RAM bank 16
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Bank17Start ds.l 1 ; 0b8, irp+e78 ; Starting address of RAM bank 17
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Bank17Size ds.l 1 ; 0bc, irp+e7c ; Number of bytes in RAM bank 17
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Bank18Start ds.l 1 ; 0c0, irp+e80 ; Starting address of RAM bank 18
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Bank18Size ds.l 1 ; 0c4, irp+e84 ; Number of bytes in RAM bank 18
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Bank19Start ds.l 1 ; 0c8, irp+e88 ; Starting address of RAM bank 19
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Bank19Size ds.l 1 ; 0cc, irp+e8c ; Number of bytes in RAM bank 19
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Bank20Start ds.l 1 ; 0d0, irp+e90 ; Starting address of RAM bank 20
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Bank20Size ds.l 1 ; 0d4, irp+e94 ; Number of bytes in RAM bank 20
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Bank21Start ds.l 1 ; 0d8, irp+e98 ; Starting address of RAM bank 21
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Bank21Size ds.l 1 ; 0dc, irp+e9c ; Number of bytes in RAM bank 21
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Bank22Start ds.l 1 ; 0e0, irp+ea0 ; Starting address of RAM bank 22
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Bank22Size ds.l 1 ; 0e4, irp+ea4 ; Number of bytes in RAM bank 22
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Bank23Start ds.l 1 ; 0e8, irp+ea8 ; Starting address of RAM bank 23
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Bank23Size ds.l 1 ; 0ec, irp+eac ; Number of bytes in RAM bank 23
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Bank24Start ds.l 1 ; 0f0, irp+eb0 ; Starting address of RAM bank 24
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Bank24Size ds.l 1 ; 0f4, irp+eb4 ; Number of bytes in RAM bank 24
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Bank25Start ds.l 1 ; 0f8, irp+eb8 ; Starting address of RAM bank 25
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Bank25Size ds.l 1 ; 0fc, irp+ebc ; Number of bytes in RAM bank 25
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EndOfBanks
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MaxBanks equ 26 ; Pads out to old struct len (cache block), more to come...
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; Interrupt Support Data
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IntCntrBaseAddr ds.l 1 ; 100, irp+ec0 ; Interrupt Controller Base Address (variable is used since this is a PCI Dev and address is relocatable)
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IntPendingReg ds.l 2 ; 104, irp+ec4 ; Data of current interrupts pending register
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; These fields were added to report information about tightly-coupled L2 caches.
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; The inline L2 information should be used in situations where there is a CPU
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; card L2 cache that can coexist with a motherboard L2.
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InlineL2DSize ds.l 1 ; 10c, irp+ecc ; Size of in-line L2 Dcache
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InlineL2ISize ds.l 1 ; 110, irp+ed0 ; Size of in-line L2 Icache
|
||||
InlineL2Combined ds.w 1 ; 114, irp+ed4 ; 1 <- combined or no cache, 0 <- split cache
|
||||
InlineL2IBlockSize ds.w 1 ; 116, irp+ed6 ; Block size of in-line I L2 cache
|
||||
InlineL2DBlockSize ds.w 1 ; 118, irp+ed8 ; Block size of in-line D L2 cache
|
||||
InlineL2IAssoc ds.w 1 ; 11a, irp+eda ; Associativity of L2 I
|
||||
InlineL2DAssoc ds.w 1 ; 11c, irp+edc ; Associativity of L2 D
|
||||
ds.w 1 ; 11e, irp+ede ; pad
|
||||
|
||||
; More Interrupt Support Data
|
||||
IntsCompleted ds.l 2 ; 120, irp+ee0 ; completed interrupts
|
||||
|
||||
ds.b $18
|
||||
Size equ *
|
||||
endr
|
||||
|
||||
|
||||
|
||||
;_______________________________________________________________________
|
||||
; Diagnostic Info Record
|
||||
;
|
||||
|
|
@ -344,19 +455,52 @@ Size equ *-SystemInfo
|
|||
; the NanoKernel, and from the NanoKernel to user mode software.
|
||||
;_______________________________________________________________________
|
||||
|
||||
nkDiagInfoPtr equ $5FFFEFE8 ; logical address of DiagnosticInfo record
|
||||
nkDiagInfoVer equ $5FFFEFEC ; version number of DiagnosticInfo record
|
||||
nkDiagInfoLen equ $5FFFEFEE ; length of DiagnosticInfo record
|
||||
NKDiagInfoPtr equ $68FFEFE8 ; logical address of DiagnosticInfo record
|
||||
NKDiagInfoVer equ $68FFEFEC ; version number of DiagnosticInfo record
|
||||
NKDiagInfoLen equ $68FFEFEE ; length of DiagnosticInfo record
|
||||
|
||||
nkDiagInfo record 0,increment
|
||||
ds.b 236 ; it WILL all fit in 256 bytes
|
||||
DiagPOSTResult2 ds.l 1 ; POST results
|
||||
DiagPOSTResult1 ds.l 1 ; POST results
|
||||
DiagEmoRestart ds.l 1 ; Burn in restart flag
|
||||
DiagWarmStartHigh ds.l 1 ; First long of native warm start (WLSC) <SM44>
|
||||
DiagWarmStartLow ds.l 1 ; Second long of native warm start (SamB) <SM44>
|
||||
align 32 ; pad to nice cache block alignment
|
||||
Size equ *-nkDiagInfo
|
||||
NKDiagInfo record 0,increment
|
||||
BankMBFailOffset ds.l 1 ; 000 ; Mother Board RAM failure code
|
||||
BankAFailOffset ds.l 1 ; 004 ; Bank A RAM failure code
|
||||
BankBFailOffset ds.l 1 ; 008 ; Bank B RAM failure code
|
||||
BankCFailOffset ds.l 1 ; 00c ; Bank C RAM failure code
|
||||
|
||||
BankDFailOffset ds.l 1 ; 010 ; Bank D RAM failure code
|
||||
BankEFailOffset ds.l 1 ; 014 ; Bank E RAM failure code
|
||||
BankFFailOffset ds.l 1 ; 018 ; Bank F RAM failure code
|
||||
BankGFailOffset ds.l 1 ; 01c ; Bank G RAM failure code
|
||||
|
||||
BankHFailOffset ds.l 1 ; 020 ; Bank H RAM failure code
|
||||
CacheFailOffset ds.l 1 ; 024 ; cache failure code
|
||||
LongBootParamOffset ds.l 1 ; 028 ; on longBoot this is where the params will be
|
||||
POSTTraceOffset ds.l 1 ; 02c ; this tells us what route the POST took
|
||||
|
||||
POSTOldWarmOffset ds.l 1 ; 030 ; logged address of old warmstart flag
|
||||
POSTOldLongOffset ds.l 1 ; 034 ; logged address of old long boot flag
|
||||
POSTOldGlobbOffset ds.l 1 ; 038 ; logged address of old Diagnostic Info Record
|
||||
POSTOldParamOffset ds.l 1 ; 03c ; the params from the old diag globb
|
||||
|
||||
POSTStartRTCUOffset ds.l 1 ; 040 ; PPC Real Time Clock Upper at start of POST
|
||||
POSTStartRTCLOffset ds.l 1 ; 044 ; PPC Real Time Clock Lower at start of POST
|
||||
POSTEndRTCUOffset ds.l 1 ; 048 ; PPC Real Time Clock Upper at end of POST
|
||||
POSTEndRTCLOffset ds.l 1 ; 04c ; PPC Real Time Clock Lower at end of POST
|
||||
|
||||
POSTTestTypeOffset ds.l 1 ; 050 ; when long RAM tests fail test type which failed is put here
|
||||
POSTError2Offset ds.l 1 ; 054 ; result codes from tests
|
||||
POSTError3Offset ds.l 1 ; 058 ; result codes from tests
|
||||
POSTError4Offset ds.l 1 ; 05c ; result codes from tests
|
||||
|
||||
RegistersStore ds.b 140 ; 060 ; store all 60x registers here, still fit into 256 bytes size.
|
||||
|
||||
; Everything BEFORE here is new (hence the funny-sized register store)
|
||||
|
||||
DiagPOSTResult2 ds.l 1 ; 0ec ; POST results
|
||||
DiagPOSTResult1 ds.l 1 ; 0f0 ; POST results
|
||||
DiagLongBootSig ds.l 1 ; 0f4 ; Burn in restart flag
|
||||
DiagWarmStartHigh ds.l 1 ; 0f8 ; First long of native warm start (WLSC) <SM44>
|
||||
DiagWarmStartLow ds.l 1 ; 0fc ; Second long of native warm start (SamB) <SM44>
|
||||
|
||||
Size equ *
|
||||
endr
|
||||
|
||||
|
||||
|
|
@ -368,30 +512,278 @@ Size equ *-nkDiagInfo
|
|||
; software.
|
||||
;_______________________________________________________________________
|
||||
|
||||
nkNanoKernelInfoPtr equ $5FFFEFE0 ; logical address of NanoKernelInfo record
|
||||
nkNanoKernelInfoVer equ $5FFFEFE4 ; version number of NanoKernelInfo record
|
||||
nkNanoKernelInfoLen equ $5FFFEFE6 ; length of NanoKernelInfo record
|
||||
NKNanoKernelInfoPtr equ $68FFEFE0 ; logical address of NanoKernelInfo record
|
||||
NKNanoKernelInfoVer equ $68FFEFE4 ; version number of NanoKernelInfo record
|
||||
NKNanoKernelInfoLen equ $68FFEFE6 ; length of NanoKernelInfo record
|
||||
|
||||
nkNanoKernelInfo record 0,increment
|
||||
ExceptionCauseCounts ds.l 32 ; counters per exception cause
|
||||
NanoKernelCallCounts ds.l 16 ; counters per NanoKernel call
|
||||
ExternalIntCount ds.l 1 ; count of External Interrupts
|
||||
MisalignmentCount ds.l 1 ; count of Misalignment Interrupts
|
||||
FPUReloadCount ds.l 1 ; count of FPU reloads on demand
|
||||
DecrementerIntCount ds.l 1 ; count of Decrementer Interrupts
|
||||
QuietWriteCount ds.l 1 ; count of Writes to Quiet Read-Only memory
|
||||
HashTableCreateCount ds.l 1 ; count of Hash Table Entry creations
|
||||
HashTableDeleteCount ds.l 1 ; count of Hash Table Entry deletions
|
||||
HashTableOverflowCount ds.l 1 ; count of Hash Table Entry overflows
|
||||
EmulatedUnimpInstCount ds.l 1 ; count of Emulated unimplemented instructions
|
||||
NCBPtrCacheMissCount ds.l 1 ; count of NCB Pointer cache misses
|
||||
ExceptionPropagateCount ds.l 1 ; count of Exceptions propagated to system
|
||||
ExceptionForcedCount ds.l 1 ; count of Exceptions forced to system
|
||||
align 8 ; align for 64 bit time base counters
|
||||
SysContextCpuTime ds.l 2 ; CPU Time used by System Context
|
||||
AltContextCpuTime ds.l 2 ; CPU Time used by Alternate Context
|
||||
align 32 ; pad to nice cache block alignment
|
||||
Size equ *-nkNanoKernelInfo
|
||||
NKNanoKernelInfo record 0,increment
|
||||
ExceptionCauseCounts ds.l 32 ; 000, kdp+dc0 ; counters per exception cause
|
||||
NanoKernelCallCounts ds.l 16 ; 080, kdp+e40 ; counters per NanoKernel call
|
||||
ExternalIntCount ds.l 1 ; 0c0, kdp+e80 ; count of External Interrupts
|
||||
MisalignmentCount ds.l 1 ; 0c4, kdp+e84 ; count of Misalignment Interrupts
|
||||
FPUReloadCount ds.l 1 ; 0c8, kdp+e88 ; count of FPU reloads on demand
|
||||
DecrementerIntCount ds.l 1 ; 0cc, kdp+e8c ; count of Decrementer Interrupts
|
||||
QuietWriteCount ds.l 1 ; 0d0, kdp+e90 ; count of Writes to Quiet Read-Only memory
|
||||
HashTableCreateCount ds.l 1 ; 0d4, kdp+e94 ; count of Hash Table Entry creations
|
||||
HashTableDeleteCount ds.l 1 ; 0d8, kdp+e98 ; count of Hash Table Entry deletions
|
||||
HashTableOverflowCount ds.l 1 ; 0dc, kdp+e9c ; count of Hash Table Entry overflows
|
||||
EmulatedUnimpInstCount ds.l 1 ; 0e0, kdp+ea0 ; count of Emulated unimplemented instructions
|
||||
NCBPtrCacheMissCount ds.l 1 ; 0e4, kdp+ea4 ; count of NCB Pointer cache misses
|
||||
ExceptionPropagateCount ds.l 1 ; 0e8, kdp+ea8 ; count of Exceptions propagated to system
|
||||
ExceptionForcedCount ds.l 1 ; 0ec, kdp+eac ; count of Exceptions forced to system
|
||||
SysContextCpuTime ds.l 2 ; 0f0, kdp+eb0 ; CPU Time used by System Context
|
||||
AltContextCpuTime ds.l 2 ; 0f8, kdp+eb4 ; CPU Time used by Alternate Context
|
||||
|
||||
; This stuff is new (starts at 0x100)
|
||||
|
||||
blueProcessID ds.l 1 ; 100, kdp+ec0 ; ID of the blue process.
|
||||
blueTaskID ds.l 1 ; 104, kdp+ec4 ; ID of the blue task.
|
||||
pageQueueID ds.l 1 ; 108, kdp+ec8 ; ID of the page fault queue.
|
||||
TaskCount ds.l 1 ; 10c, kdp+ecc ; Number of tasks.
|
||||
FreePoolExtendCount ds.l 1 ; 110, kdp+ed0 ; Number of pages given to the nanokernel.
|
||||
|
||||
;rsrv1 ds.l 3 ; 114, kdp+ed4 ; reserved???
|
||||
|
||||
; My additions
|
||||
|
||||
org $11c
|
||||
ConfigFlags ds.l 1 ; 11c, kdp+edc ; includes ScreenConsole ... TODO put flag equs here
|
||||
NanodbgrFlagShift equ 1
|
||||
NanodbgrFlagBit equ 31 - NanodbgrFlagShift
|
||||
LogFlagShift equ 3
|
||||
LogFlagBit equ 31 - LogFlagShift
|
||||
; bit 31 always set on replacement, bit 27 set on replacement with ROM 2.7f3 or later
|
||||
|
||||
org $128
|
||||
VMDispatchCountTblPtr ds.l 1 ; 128, kdp+ee8
|
||||
ds.l 1
|
||||
ds.l 1
|
||||
MPDispatchCountTblPtr ds.l 1 ; 134, kdp+ef4 ; ???????
|
||||
AddrSpcSetCtr ds.l 1 ; 138, kdp+ef8 ; incremented by SetAddrSpcRegisters
|
||||
IDCtr ds.l 1 ; 13c, kdp+efc
|
||||
|
||||
ds.b $20
|
||||
Size equ *
|
||||
endr
|
||||
|
||||
|
||||
|
||||
;_______________________________________________________________________
|
||||
; Processor Info Record
|
||||
;
|
||||
; Used to pass Processor information from the NanoKernel to user mode
|
||||
; software.
|
||||
;_______________________________________________________________________
|
||||
|
||||
ProcessorInfoPtr equ $68FFEFD8 ; logical address of ProcessorInfo record
|
||||
ProcessorInfoVer equ $68FFEFDC ; version number of ProcessorInfo record
|
||||
ProcessorInfoLen equ $68FFEFDE ; length of ProcessorInfo record
|
||||
|
||||
ProcessorInfo record 0,increment
|
||||
ProcessorVersionReg ds.l 1 ; 000, kdp+f20 ; contents of the PVR special purpose register
|
||||
CpuClockRateHz ds.l 1 ; 004, kdp+f24 ; CPU Clock frequency
|
||||
BusClockRateHz ds.l 1 ; 008, kdp+f28 ; Bus Clock frequency
|
||||
DecClockRateHz ds.l 1 ; 00c, kdp+f2c ; Decrementer Clock frequency
|
||||
|
||||
Ovr
|
||||
PageSize ds.l 1 ; 010, kdp+f30 ; number of bytes in a memory page
|
||||
DataCacheTotalSize ds.l 1 ; 014, kdp+f34 ; number of bytes in the Data Cache
|
||||
InstCacheTotalSize ds.l 1 ; 018, kdp+f38 ; number of bytes in the Instruction Cache
|
||||
CoherencyBlockSize ds.w 1 ; 01c, kdp+f3c ; number of bytes in a Coherency Block
|
||||
ReservationGranuleSize ds.w 1 ; 01e, kdp+f3e ; number of bytes in a Reservation Granule
|
||||
CombinedCaches ds.w 1 ; 020, kdp+f40 ; 1 <- combined or no cache, 0 <- split cache
|
||||
InstCacheLineSize ds.w 1 ; 022, kdp+f42 ; number of bytes in a Line of the Instruction Cache
|
||||
DataCacheLineSize ds.w 1 ; 024, kdp+f44 ; number of bytes in a Line of the Data Cache
|
||||
DataCacheBlockSizeTouch ds.w 1 ; 026, kdp+f46 ; number of bytes in a Block for DCBT DCBTST
|
||||
InstCacheBlockSize ds.w 1 ; 028, kdp+f48 ; number of bytes in a Block of the Instruction Cache
|
||||
DataCacheBlockSize ds.w 1 ; 02a, kdp+f4a ; number of bytes in a Block of the Data Cache
|
||||
InstCacheAssociativity ds.w 1 ; 02c, kdp+f4c ; Associativity of the Instruction Cache
|
||||
DataCacheAssociativity ds.w 1 ; 02e, kdp+f4e ; Associativity of the Data Cache
|
||||
|
||||
TransCacheTotalSize ds.w 1 ; 030, kdp+f50 ; number of entries in the Translation Cache
|
||||
TransCacheAssociativity ds.w 1 ; 032, kdp+f52 ; Associativity of the Translation Cache
|
||||
OvrEnd
|
||||
|
||||
; These fields were added to report information about back-side L2 caches
|
||||
|
||||
ProcessorL2DSize ds.l 1 ; 034, kdp+f54 ; Size of back-side L2 Dcache
|
||||
ProcessorL2ISize ds.l 1 ; 038, kdp+f58 ; Size of back-side L2 Icache
|
||||
ProcessorL2Combined ds.w 1 ; 03c, kdp+f5c ; 1 <- combined or no cache, 0 <- split cache
|
||||
ProcessorL2IBlockSize ds.w 1 ; 03e, kdp+f5e ; Block size of back-side I L2 cache
|
||||
ProcessorL2DBlockSize ds.w 1 ; 040, kdp+f60 ; Block size of back-side D L2 cache
|
||||
ProcessorL2IAssoc ds.w 1 ; 042, kdp+f62 ; Associativity of L2 I
|
||||
ProcessorL2DAssoc ds.w 1 ; 044, kdp+f64 ; Associativity of L2 D
|
||||
|
||||
filler1 ds.w 1 ; 046, kdp+f66 ; align to long
|
||||
|
||||
; ProcessorFlags - Definitions for the processor flags field. These are bit positions,
|
||||
; as in 1 << hasVMX, and not masks.
|
||||
hasL2CR equ 0
|
||||
hasPLRUL1 equ 1
|
||||
hasTAU equ 2
|
||||
hasVMX equ 3
|
||||
unknownFlag equ 4
|
||||
hasExtraBATs equ 5
|
||||
ProcessorFlags ds.l 1 ; 048, kdp+f68 ; flags to specify processor features
|
||||
|
||||
align 5 ; pad to nice cache block alignment
|
||||
|
||||
org $05e
|
||||
SetToZero ds.w 1 ; 05e, kdp+f7e ; by same code that sets below
|
||||
CpuClockRateHzCopy ds.l 1 ; 060, kdp+f80 ; copies by Init.s
|
||||
BusClockRateHzCopy ds.l 1 ; 064, kdp+f84 ; copies by Init.s
|
||||
DecClockRateHzCopy ds.l 1 ; 068, kdp+f88 ; copies by Init.s
|
||||
|
||||
ds.b $34
|
||||
Size equ *
|
||||
endr
|
||||
|
||||
|
||||
|
||||
;_______________________________________________________________________
|
||||
; Hardware Info Record
|
||||
;
|
||||
; Used to pass hardware information from the NanoKernel to user mode
|
||||
; software.
|
||||
;_______________________________________________________________________
|
||||
|
||||
NKHWInfoPtr equ $68FFEFD0 ; logical address of HWInfo record
|
||||
NKHWInfoVer equ $68FFEFD4 ; version number of HWInfo record
|
||||
NKHWInfoLen equ $68FFEFD6 ; length of HWInfo record
|
||||
|
||||
NKHWInfo record 0,increment
|
||||
MacROM_Base ds.l 1 ; 000, irp+f00 ; base address (physical) of Mac ROM
|
||||
DeviceTreeBase ds.l 1 ; 004, irp+f04 ; base address of the copied device tree properties
|
||||
UniversalInfoTableBase ds.l 1 ; 008, irp+f08 ; base address of the Universal Info Table
|
||||
ConfigInfoTableBase ds.l 1 ; 00c, irp+f0c ; base address of the Config Info Table
|
||||
VectorLookupTable ds.l 1 ; 010, irp+f10 ; base address of the interrupt vector lookup table (short *)
|
||||
VectorMaskTable ds.l 1 ; 014, irp+f14 ; base address of the interrupt vector mask table (long *)
|
||||
|
||||
OpenPICBaseAddr ds.l 1 ; 018, irp+f18 ; OpenPIC base address
|
||||
|
||||
ISAMaster8259 ds.l 1 ; 01c, irp+f1c ; ISA Master 8259 ports (char *)
|
||||
ISASlave8259 ds.l 1 ; 020, irp+f20 ; ISA Slave 8259 ports (char *)
|
||||
InterruptAck8259 ds.l 1 ; 024, irp+f24 ; address to read to ack 8259 interrupt (long *)
|
||||
|
||||
; interrupt pending bits (actively changing)
|
||||
|
||||
PendingInts ds.l 2 ; 028, irp+f28 ; 64 bits of pending interrupts
|
||||
|
||||
; some Mac I/O device base addresses
|
||||
|
||||
ADB_Base ds.l 1 ; 030, irp+f30 ; base address of ADB
|
||||
SCSI_DMA_Base ds.l 1 ; 034, irp+f34 ; base address of SCSI DMA registers
|
||||
|
||||
; RTAS related stuff
|
||||
|
||||
RTAS_PrivDataArea ds.l 1 ; 038, irp+f38 ; RTAS private data area
|
||||
MacOS_NVRAM_Offset ds.l 1 ; 03c, irp+f3c ; offset into nvram to MacOS data
|
||||
|
||||
RTAS_NVRAM_Fetch ds.l 1 ; 040, irp+f40 ; token for RTAS NVRAM fetch
|
||||
RTAS_NVRAM_Store ds.l 1 ; 044, irp+f44 ; token for RTAS NVRAM store
|
||||
RTAS_Get_Clock ds.l 1 ; 048, irp+f48 ; token for RTAS clock get
|
||||
RTAS_Set_Clock ds.l 1 ; 04c, irp+f4c ; token for RTAS clock set
|
||||
RTAS_Restart ds.l 1 ; 050, irp+f50 ; token for RTAS Restart
|
||||
RTAS_Shutdown ds.l 1 ; 054, irp+f54 ; token for RTAS Shutdown
|
||||
RTAS_Restart_At ds.l 1 ; 058, irp+f58 ; token for RTAS system startup at specified time
|
||||
RTAS_EventScan ds.l 1 ; 05c, irp+f5c ; token for RTAS event scan
|
||||
RTAS_Check_Exception ds.l 1 ; 060, irp+f60 ; token for RTAS check exception
|
||||
RTAS_Read_PCI_Config ds.l 1 ; 064, irp+f64 ; token for RTAS read PCI config
|
||||
RTAS_Write_PCI_Config ds.l 1 ; 068, irp+f68 ; token for RTAS write PCI config
|
||||
|
||||
; SIO interrupt source numbers for the MPIC
|
||||
|
||||
SIOIntVect ds.w 1 ; 06c, irp+f6c ; SIO (8259 cascade vector) vector number
|
||||
SIOIntBit ds.w 1 ; 06e, irp+f6e ; SIO (8259 cascade vector) bit number
|
||||
|
||||
Signature ds.l 1 ; 070, irp+f70 ; signature for this record ('Hnfo')
|
||||
|
||||
; more interrupt source numbers
|
||||
|
||||
SpuriousIntVect ds.w 1 ; 074, irp+f74 ; spurious vector number
|
||||
|
||||
CPU_ID ds.w 1 ; 076, irp+f76 ; the ID of this CPU (universal-tables-related)
|
||||
|
||||
SCCAIntVect ds.w 1 ; 078, irp+f78 ; SCC A (non-DMA) vector number
|
||||
SCCBIntVect ds.w 1 ; 07a, irp+f7a ; SCC B (non-DMA) vector number
|
||||
SCSIIntVect ds.w 1 ; 07c, irp+f7c ; SCSI vector number
|
||||
SCSIDMAIntVect ds.w 1 ; 07e, irp+f7e ; SCSI DMA vector number
|
||||
VIAIntVect ds.w 1 ; 080, irp+f80 ; VIA vector number
|
||||
VIAIntBit ds.w 1 ; 082, irp+f82 ; VIA bit number
|
||||
ADBIntVect ds.w 1 ; 084, irp+f84 ; vector number
|
||||
NMIIntVect ds.w 1 ; 086, irp+f86 ; NMI vector number
|
||||
NMIIntBit ds.w 1 ; 088, irp+f88 ; NMI bit number
|
||||
|
||||
; current (actively changing) interrupt handling variables
|
||||
|
||||
ISAPendingInt ds.w 1 ; 08a, irp+f8a ; currently pending ISA/8259 interrupt
|
||||
CompletedInts ds.b 8 ; 08c, irp+f8c ; completed interrupts
|
||||
|
||||
nkHWInfoFlagSlowMESH equ 1 ; set if fast MESH doesn't work on this box
|
||||
nkHWInfoFlagAsynchMESH equ 2 ; set if Synchronous MESH doesn't work on this box
|
||||
nkHWInfoFlagNoCopySWTLB equ 4 ; set if the software TLB walk code for 603 should NOT be copied
|
||||
HardwareInfoFlags ds.l 1 ; 094, irp+f94 ; 32 bits of flags (see enum above)
|
||||
|
||||
RTAS_Get_PowerOn_Time ds.l 1 ; 098, irp+f98 ; token for RTAS getting time for system startup
|
||||
|
||||
ds.b $24
|
||||
Size equ *
|
||||
endr
|
||||
|
||||
|
||||
|
||||
;_______________________________________________________________________
|
||||
; Processor State Record
|
||||
;
|
||||
; Used to save the state of the processor across sleep.
|
||||
;_______________________________________________________________________
|
||||
|
||||
NKProcessorStatePtr equ $68FFEFC8 ; logical address of ProcessorState record
|
||||
NKProcessorStateVer equ $68FFEFCC ; version number of ProcessorState record
|
||||
NKProcessorStateLen equ $68FFEFCE ; length of ProcessorState record
|
||||
|
||||
NKProcessorState record 0,increment
|
||||
saveDBAT0u ds.l 1 ; 000 ; place to store DBAT0U
|
||||
saveDBAT0l ds.l 1 ; 004 ; place to store DBAT0L
|
||||
saveDBAT1u ds.l 1 ; 008 ; place to store DBAT1U
|
||||
saveDBAT1l ds.l 1 ; 00c ; place to store DBAT1L
|
||||
saveDBAT2u ds.l 1 ; 010 ; place to store DBAT2U
|
||||
saveDBAT2l ds.l 1 ; 014 ; place to store DBAT2L
|
||||
saveDBAT3u ds.l 1 ; 018 ; place to store DBAT3U
|
||||
saveDBAT3l ds.l 1 ; 01c ; place to store DBAT3L
|
||||
|
||||
saveIBAT0u ds.l 1 ; 020 ; place to store IBAT0U
|
||||
saveIBAT0l ds.l 1 ; 024 ; place to store IBAT0L
|
||||
saveIBAT1u ds.l 1 ; 028 ; place to store IBAT1U
|
||||
saveIBAT1l ds.l 1 ; 02c ; place to store IBAT1L
|
||||
saveIBAT2u ds.l 1 ; 030 ; place to store IBAT2U
|
||||
saveIBAT2l ds.l 1 ; 034 ; place to store IBAT2L
|
||||
saveIBAT3u ds.l 1 ; 038 ; place to store IBAT3U
|
||||
saveIBAT3l ds.l 1 ; 03c ; place to store IBAT3L
|
||||
|
||||
saveSPRG0 ds.l 1 ; 040 ; place to store SPRG0
|
||||
saveSPRG1 ds.l 1 ; 044 ; place to store SPRG1
|
||||
saveSPRG2 ds.l 1 ; 048 ; place to store SPRG2
|
||||
saveSPRG3 ds.l 1 ; 04c ; place to store SPRG3
|
||||
|
||||
saveL2CR ds.l 1 ; 050 ; place to store Arthur's L2CR
|
||||
|
||||
saveSRR0 ds.l 1 ; 054 ; place to store SRR0
|
||||
saveSRR1 ds.l 1 ; 058 ; place to store SRR1
|
||||
saveTBU ds.l 1 ; 05c ; place to store TBU
|
||||
saveTBL ds.l 1 ; 060 ; place to store TBL
|
||||
saveHID0 ds.l 1 ; 064 ; place to store HID0
|
||||
saveDEC ds.l 1 ; 068 ; place to store DEC
|
||||
saveMSR ds.l 1 ; 06c ; place to store MSR
|
||||
saveSDR1 ds.l 1 ; 070 ; place to store SDR1
|
||||
|
||||
; saveKernelDataPtr needs to always be right after saveReturnAddr
|
||||
; because of how the code works. DO NOT CHANGE THIS ORDERING!
|
||||
|
||||
saveReturnAddr ds.l 1 ; 074 ; place to store the addr to jump to.
|
||||
saveKernelDataPtr ds.l 1 ; 078 ; place to store the KernelDataPtr
|
||||
saveContextPtr ds.l 1 ; 07c ; place to store the ContextPtr
|
||||
Size equ *
|
||||
endr
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ kPreventFileFromBeingClosedMask equ 16
|
|||
kAllOverrideAttributesMask equ kOverrideNextMapMask + \
|
||||
kDontCountOrIndexDuplicatesMask + \
|
||||
kTwoDeepMask + \
|
||||
kPreventFileFromBeingClosedMask
|
||||
kPreventFileFromBeingClosedMask + 32 + 64 + 128
|
||||
kAllButOverrideAttributesMask equ 255 - kAllOverrideAttributesMask
|
||||
|
||||
selectMakeOverrideMap equ 4
|
||||
|
|
|
|||
|
|
@ -436,11 +436,13 @@ emExpansionBusGlobals ds.l 1 ; Pointer to Expansion Bus Manager Globals
|
|||
|
||||
jSWModemSoundVector ds.l 1 ; Vector to control routine for software modem sound
|
||||
|
||||
ds.b 270
|
||||
|
||||
; NOTE: When adding new fields here, be sure to update the high-level language header files as well
|
||||
; (currently {CInternal}ExpandMemPriv.h is the one)
|
||||
; Be sure to update the Reality sources when you change this file (and the version number)
|
||||
|
||||
emCurVersion EQU $0133 ; version
|
||||
emCurVersion EQU $016b ; version
|
||||
|
||||
emRecSize equ * ; size for this version
|
||||
size equ *
|
||||
|
|
|
|||
|
|
@ -118,13 +118,13 @@ InitVec&TVec proc export ; initialize the vector table vector
|
|||
|
||||
Endif
|
||||
|
||||
; fill in the unused "holes" with the address of UNIMPLEMENTED
|
||||
; fill in the unused "holes" with the address of BADTRAP
|
||||
|
||||
If (&thisCVect - &lastCVect) > 4 Then
|
||||
|
||||
import UNIMPLEMENTED
|
||||
import BADTRAP
|
||||
|
||||
dcb.l (&thisCVect - &lastCVect - 4)/4 ,UNIMPLEMENTED-BASEOFROM+ROMBASE
|
||||
dcb.l (&thisCVect - &lastCVect - 4)/4 ,BADTRAP-BASEOFROM+ROMBASE
|
||||
|
||||
Endif
|
||||
|
||||
|
|
|
|||
|
|
@ -109,6 +109,7 @@ ContinueComp ds.l 1 ; vector to power message continue procedure <SM5>
|
|||
deferredPDM ds.l 1 ; pointer to PDM deferred task to post alert <SM5>
|
||||
prevPollStack ds.l 1 ; keep address of any other poll stack <SM6>
|
||||
SpareComp3 ds.l 1 ; spare vector #3 <SM5>
|
||||
ds.b $178-$64 ; new
|
||||
EgretGlobSize EQU *
|
||||
ENDR
|
||||
|
||||
|
|
@ -273,7 +274,8 @@ EnDisPDM equ $21 ; Enable/Disable PowerDown Message <T2>
|
|||
RdWrIIC equ $22 ; Read or Write IIC (I sqared C) <SM3>[rbm]<3>
|
||||
WakeUpMode equ $23 ; Enable/Disable WakeUpMode <P1>
|
||||
TimerTickle equ $24 ; ShutDown Timer Tickle <P1>
|
||||
MaxPseudoCmd equ TimerTickle ; largest possible pseudo command number <P1>
|
||||
; more commands apparently added
|
||||
MaxPseudoCmd equ $2A ; largest possible pseudo command number <P1>
|
||||
|
||||
;
|
||||
;__________________________________________________________________________________________________
|
||||
|
|
|
|||
|
|
@ -285,7 +285,7 @@
|
|||
Exit 1
|
||||
End
|
||||
|
||||
"{Sources}Tools:Make" -w {MOpts} {Targets} -f "{MakeFile}" > "{MakeOut}" || Exit
|
||||
Make -w {MOpts} {Targets} -f "{MakeFile}" > "{MakeOut}" || Exit
|
||||
|
||||
If {EchoCmds}
|
||||
Set Echo 1
|
||||
|
|
|
|||
|
|
@ -13,6 +13,12 @@
|
|||
#
|
||||
# Change History (most recent first):
|
||||
#
|
||||
# 1/29/17 HQX Add conditionals for "Custer" (Mirrored Drive Door G4 ROM v10.2.1)
|
||||
# resources, change TNTPlus to hasPCI.
|
||||
# 1/9/17 HQX Add Classic flag
|
||||
# 12/28/16 HQX Finally realise how this works. Patch to emulate the missing
|
||||
# "ParseFeatures" command. Added NewWorld and TNTPlus flags.
|
||||
#
|
||||
# <SM25> 12/13/93 PN Roll in KAOs and Horror changes to support Malcom and AJ
|
||||
# machines
|
||||
# <SM24> 11/10/93 fau Update from SuperMunggio <SMG2-3>.
|
||||
|
|
@ -64,7 +70,28 @@
|
|||
#
|
||||
#
|
||||
|
||||
Set AvailableFeatures "hasROMGibbly ¶
|
||||
Set cdg5Features "¶
|
||||
Vanilla ¶
|
||||
LatestHack ¶
|
||||
hasPCI ¶
|
||||
BlueBox ¶
|
||||
NewWorld ¶
|
||||
CusterBacklightParcel ¶
|
||||
CusterUSBShimKeyboard ¶
|
||||
cdg5HappyMac ¶
|
||||
NKDebugShim ¶
|
||||
NKShowLog ¶
|
||||
ExtraNKLogging ¶
|
||||
DebugAlways ¶
|
||||
SkipTbxiValidation ¶
|
||||
TbxiPatchG4Version ¶
|
||||
TbxiDisableAppleKiwi ¶
|
||||
Wedge ¶
|
||||
"
|
||||
|
||||
Set AvailableFeatures "{cdg5Features} ¶
|
||||
hasBCScreen ¶
|
||||
hasROMGibbly ¶
|
||||
hasManEject ¶
|
||||
hasCacheTypeCPU ¶
|
||||
forPDMProto ¶
|
||||
|
|
@ -197,12 +224,25 @@ Set AvailableFeatures "hasROMGibbly
|
|||
useROMFonts "
|
||||
|
||||
|
||||
If "` ParseFeatures -a "{AvailableFeatures}" -f ": ROM {1}" `" =~ /': ROM '(Å)¨1/
|
||||
Set Defines "{¨1}"
|
||||
Else
|
||||
Exit 1
|
||||
End
|
||||
|
||||
|
||||
# # ParseFeatures is lost to the ages...
|
||||
# If "` ParseFeatures -a "{AvailableFeatures}" -f ": ROM {1}" `" =~ /': ROM '(Å)¨1/
|
||||
# Set Defines "{¨1}"
|
||||
# Else
|
||||
# Exit 1
|
||||
# End
|
||||
|
||||
# Set Defines "-d "
|
||||
|
||||
# This block of code replaces it...
|
||||
For Feature in {AvailableFeatures}
|
||||
Set Defines "{Defines} -d {Feature}=`Evaluate " {1} " =~ /Å {Feature} Å/`"
|
||||
End
|
||||
|
||||
# Ugh!
|
||||
Set Defines "`Echo {Defines} | StreamEdit -e '¥,° Replace /=1/ "=TRUE" -c °' -e '¥,° Replace /=0/ "=FALSE" -c °'`"
|
||||
|
||||
For Override in {2}
|
||||
|
||||
If "{Override}" =~ /(Å)¨1=(Å)¨2/
|
||||
|
|
@ -214,9 +254,9 @@ Set AvailableFeatures "hasROMGibbly
|
|||
End
|
||||
|
||||
If {Value} =~ /true/
|
||||
Set Value TRUE
|
||||
Set Value 1 #TRUE # to allow overrides to work right!
|
||||
Else If {Value} =~ /false/
|
||||
Set Value FALSE
|
||||
Set Value 0 #FALSE
|
||||
End
|
||||
|
||||
If "{Defines}" =~ /(Å)¨3{Name}=[Â ¶t]+(Å)¨4/
|
||||
|
|
|
|||
|
|
@ -54,30 +54,23 @@ MainCodeLibs =
|
|||
"{MiscDir}GoNativeROMLib.o" ¶
|
||||
"{LibDir}SlotMgr.lib" ¶
|
||||
"{LibDir}SCSI.lib" ¶
|
||||
"{LibDir}SCSI4pt3.lib" ¶
|
||||
"{LibDir}HFS.lib" ¶
|
||||
"{LibDir}PPC.lib" ¶
|
||||
"{LibDir}ADBMgr.lib" ¶
|
||||
"{LibDir}TimeMgr.lib" ¶
|
||||
"{LibDir}Toolbox.lib" ¶
|
||||
"{LibDir}CommToolboxPatch.Lib" ¶
|
||||
"{LibDir}MemoryMgr.lib" ¶
|
||||
"{LibDir}AliasMgr.lib" ¶
|
||||
"{LibDir}ComponentMgr.lib" ¶
|
||||
"{LibDir}DataAccessMgr.lib" ¶
|
||||
"{LibDir}EditionMgr.lib" ¶
|
||||
"{LibDir}ExpansionBusMgr.lib" ¶
|
||||
"{LibDir}HelpMgr.lib" ¶
|
||||
"{LibDir}SoundMgr.lib" ¶
|
||||
"{LibDir}Gestalt.lib" ¶
|
||||
"{LibDir}IconUtils.lib" ¶
|
||||
"{LibDir}NotificationMgr.lib" ¶
|
||||
"{LibDir}PictUtilities.lib" ¶
|
||||
"{LibDir}ToolboxEventMgr.lib" ¶
|
||||
"{LibDir}ControlMgr.lib" ¶
|
||||
"{LibDir}DisplayMgr.lib" ¶
|
||||
"{LibDir}WindowMgr.lib" ¶
|
||||
"{LibDir}MenuMgr.lib" ¶
|
||||
"{LibDir}ATAMgr.lib" ¶
|
||||
"{ObjDir}DeviceMgr.a.o" ¶
|
||||
# ¶
|
||||
# DispatchHelper and DialogMgr.lib need to be colocated ¶
|
||||
# ¶
|
||||
|
|
@ -89,15 +82,8 @@ MainCodeLibs =
|
|||
"{LibDir}ResourceMgr.lib" ¶
|
||||
"{LibDir}ScriptMgr.lib" ¶
|
||||
"{LibDir}CQD.lib" ¶
|
||||
"{LibDir}TextServicesMgr.lib" ¶
|
||||
"{LibDir}FontMgr.lib" ¶
|
||||
"{LibDir}RomInterface.Lib" ¶
|
||||
"{LibDir}RomStandardLib.lib" ¶
|
||||
"{LibDir}StartTest.lib" ¶
|
||||
"{LibDir}VideoDriver.lib" ¶
|
||||
"{ObjDir}WallyWorld.a.o" ¶
|
||||
"{ObjDir}FPEmulation.a.o" ¶
|
||||
"{LibDir}Beep.lib" ¶
|
||||
"{LibDir}Lastly.lib" ¶
|
||||
# ¶
|
||||
# Keep DispTable at end ¶
|
||||
# ¶
|
||||
|
|
@ -118,7 +104,7 @@ MainCodeLibs =
|
|||
#
|
||||
# Vectorization
|
||||
#
|
||||
"{LibDir}MainCode.Lib" Ä {MainCodeLibs} "{ObjDir}VectorTablePatch.a.o"
|
||||
"{LibDir}MainCode.Lib" Ä {MainCodeLibs} "{ObjDir}VectorTablePatch.a.o" "{ToolDir}Vectorize"
|
||||
"{ToolDir}Vectorize" -w -v "{ObjDir}VectorTablePatch.a.o" -log "{TextDir}MainCode.Sym" {StdVOpts} -o "{Targ}" {MainCodeLibs}
|
||||
|
||||
"{ObjDir}VectorTablePatch.a.o" Ä "{Sources}Make:VectorTable.a" "{IntAIncludes}VectorTablePatch.a"
|
||||
|
|
|
|||
|
|
@ -162,26 +162,21 @@ IntAIncludes = {Sources}Internal:Asm:
|
|||
IntCIncludes = {Sources}Internal:C:
|
||||
IntPInterfaces = {Sources}Internal:Pascal:
|
||||
IntRIncludes = {Sources}Internal:Rez:
|
||||
Libraries = {Sources}Libs:Libraries:
|
||||
CLibraries = {Sources}Libs:CLibraries:
|
||||
PLibraries = {Sources}Libs:PLibraries:
|
||||
|
||||
|
||||
MAOpts = -d TRUE=1 -d FALSE=0 -d Alignment=8 -d CPU=20 -d ROMRelease=$D4C1 -wb -d SubRelease=3 -blksize 62
|
||||
MCOpts = -d TRUE=1 -d FALSE=0 -d Alignment=8 -d CPU=20 -d ROMRelease=$D4C1 -b3 -mbg full -mc68020 -blksize 62 -opt full
|
||||
MAOpts = -d TRUE=1 -d FALSE=0 -d Alignment=8 -d CPU=20 -d ROMRelease=$45F6 -wb -d SubRelease=1 -blksize 62
|
||||
MCOpts = -d TRUE=1 -d FALSE=0 -d Alignment=8 -d CPU=20 -d ROMRelease=$45F6 -b3 -mbg full -mc68020 -blksize 62 -opt full
|
||||
MPOpts = -mbg full -mc68020
|
||||
|
||||
RomBase = $40800000
|
||||
RomBase = $FFC00000
|
||||
|
||||
Features = hasRISCV0ResMgrPatches ¶
|
||||
hasDoubleByte ¶
|
||||
hasAMIC ¶
|
||||
SupportNativeComponents ¶
|
||||
Script_Char_Extra ¶
|
||||
hasPenFraction ¶
|
||||
hasFullKerning ¶
|
||||
hasGlyphState ¶
|
||||
hasNewHeapMgr ¶
|
||||
hasPDMMaceEnet ¶
|
||||
hasAppleTalkInROM ¶
|
||||
hasMixedMode ¶
|
||||
|
|
@ -189,9 +184,7 @@ Features = hasRISCV0ResMgrPatches
|
|||
hasSCSIDiskModeFeature ¶
|
||||
hasSysSevenResources ¶
|
||||
hasDataAccessPACK ¶
|
||||
hasYMCA ¶
|
||||
hasCPUIDRegister ¶
|
||||
hasHMC ¶
|
||||
has2MegROMOrMore ¶
|
||||
hasVideoIn ¶
|
||||
hasAsyncSCSI ¶
|
||||
|
|
@ -208,7 +201,6 @@ Features = hasRISCV0ResMgrPatches
|
|||
forLocalizability ¶
|
||||
has040MMU ¶
|
||||
hasADBKeyLayouts ¶
|
||||
hasASC ¶
|
||||
hasAliasMgr ¶
|
||||
hasApple2Fonts ¶
|
||||
hasAppleEventMgr ¶
|
||||
|
|
@ -216,49 +208,25 @@ Features = hasRISCV0ResMgrPatches
|
|||
hasBattery ¶
|
||||
hasCommToolbox ¶
|
||||
hasCQD ¶
|
||||
hasDAFB ¶
|
||||
hasDJMEMC ¶
|
||||
hasDataAccessMgr ¶
|
||||
hasDisplayMgr ¶
|
||||
hasDisplayMgrWindows ¶
|
||||
hasEDisk ¶
|
||||
hasEclipseVIA2 ¶
|
||||
hasEditionMgr ¶
|
||||
hasEgret ¶
|
||||
hasExtendedCharacterSet ¶
|
||||
hasFMC ¶
|
||||
hasGDU ¶
|
||||
hasGlue ¶
|
||||
hasGrandCentral ¶
|
||||
hasIdle ¶
|
||||
hasIopScc ¶
|
||||
hasIopSwim ¶
|
||||
hasJaws ¶
|
||||
hasMDU ¶
|
||||
hasMMU ¶
|
||||
hasMSC ¶
|
||||
hasMac2VIA2 ¶
|
||||
hasNetBoot ¶
|
||||
hasNiagra ¶
|
||||
hasOrwell ¶
|
||||
hasOss ¶
|
||||
hasPratt ¶
|
||||
hasProtectedPRAM ¶
|
||||
hasSCSI96 ¶
|
||||
hasSWIM2 ¶
|
||||
hasSwim3 ¶
|
||||
hasSlotMgr ¶
|
||||
hasSonora ¶
|
||||
hasSplineFonts ¶
|
||||
hasVDAC ¶
|
||||
hasVIAClock ¶
|
||||
hasVISA2 ¶
|
||||
hasVISADecoder ¶
|
||||
hasWaimeaVIA2 ¶
|
||||
isUniversal ¶
|
||||
hasPwrControls ¶
|
||||
hasPwrMgrClock ¶
|
||||
hasRBV ¶
|
||||
hasSplineFonts ¶
|
||||
hasVIAClock ¶
|
||||
hasWaimeaVIA2 ¶
|
||||
|
|
@ -267,6 +235,8 @@ Features = hasRISCV0ResMgrPatches
|
|||
onHafMac ¶
|
||||
onMac32 ¶
|
||||
onNuMac ¶
|
||||
hasBCScreen ¶
|
||||
hasMMU ¶
|
||||
ForROM
|
||||
|
||||
|
||||
|
|
@ -340,9 +310,6 @@ FeatureSet
|
|||
Set CIncludes "{CIncludes}"
|
||||
Set PInterfaces "{PInterfaces}"
|
||||
Set RIncludes "{RIncludes}"
|
||||
Set Libraries "{Libraries}"
|
||||
Set CLibraries "{CLibraries}"
|
||||
Set PLibraries "{PLibraries}"
|
||||
Set StdAOpts "{MAOpts} {FeatureSet} -i {IntAIncludes} {AOpts} -i {ObjDir}"
|
||||
Set StdCOpts "{MCOpts} {FeatureSet} -i {IntCIncludes} {COpts}"
|
||||
Set StdCPOpts "{MCPOpts} {FeatureSet} -i {IntCIncludes} {COpts}"
|
||||
|
|
@ -381,10 +348,10 @@ Clean
|
|||
|
||||
#include {ToolSrcDir}Tools.make
|
||||
|
||||
#include {MakeDir}MainCode.make
|
||||
|
||||
#include {DeclDir}DeclData.make
|
||||
|
||||
#include {DriverDir}Drivers.make
|
||||
|
||||
#include {ResourceDir}Resources.make
|
||||
#include {MakeDir}MainCode.make
|
||||
|
||||
##include {DeclDir}DeclData.make
|
||||
|
||||
##include {ResourceDir}Resources.make
|
||||
|
|
|
|||
1644
Make/VectorTable.a
1644
Make/VectorTable.a
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
|
@ -182,7 +182,7 @@ Debugging equ 0 ; disable debugging checks
|
|||
|
||||
;______________________________________________________________________
|
||||
;
|
||||
; Routine: CountADBs
|
||||
; Routine: CountADBs 2b380
|
||||
; Arguments: None
|
||||
; Output: D0.W Number of ADB entries
|
||||
; Function: This routine counts the number of entries in the ADB
|
||||
|
|
@ -210,7 +210,7 @@ FirstCount
|
|||
|
||||
;______________________________________________________________________
|
||||
;
|
||||
; Routine: GetIndADB
|
||||
; Routine: GetIndADB 2b39a
|
||||
; Arguments: DO.W Index from 1 to the value returned by CountADBs
|
||||
; A0 Pointer to buffer in which DeviceType, OrigAddr,
|
||||
; ServiceAddr, DataAddr are returned (10 bytes)
|
||||
|
|
@ -245,7 +245,7 @@ LoadBuf MOVE.B FDBDevTy(A1), (A0)+ ; Return DeviceType
|
|||
Title 'KbdADB - ADB Manager - GetADBInfo / SetADBInfo / FindFDBInfo'
|
||||
;______________________________________________________________________
|
||||
;
|
||||
; Routine: GetADBInfo
|
||||
; Routine: GetADBInfo 2b3c6
|
||||
; Arguments: DO.B ADBAddr
|
||||
; A0 Pointer to buffer in which DeviceType, OrigAddr,
|
||||
; ServiceAddr, DataAddr are returned (10 bytes)
|
||||
|
|
@ -261,7 +261,7 @@ GetADBInfoTrap
|
|||
|
||||
;______________________________________________________________________
|
||||
;
|
||||
; Routine: SetADBInfo
|
||||
; Routine: SetADBInfo 2b3cc
|
||||
; Arguments: DO.B ADBAddr
|
||||
; A0 Pointer to buffer containing ServiceAddr and
|
||||
; DataAddr (8 bytes)
|
||||
|
|
@ -282,7 +282,7 @@ DoneSet RTS
|
|||
|
||||
;______________________________________________________________________
|
||||
;
|
||||
; Routine: FindFDBInfo
|
||||
; Routine: FindFDBInfo 2b3da
|
||||
; Arguments: DO.B FDBAddr
|
||||
; Output: D0.L 0 if found, -1 if not
|
||||
; A1 Real address of FDB record if found.
|
||||
|
|
@ -317,7 +317,7 @@ DoneFind
|
|||
Title 'KbdADB - ADB Manager - ADBOp'
|
||||
;_______________________________________________________________________
|
||||
;
|
||||
; Routine: ADBOp
|
||||
; Routine: ADBOp 2b3fc
|
||||
; Inputs: A0.L - pointer to ADBOpBlock paramater block
|
||||
; D0.B - ADB command/address byte to send
|
||||
;
|
||||
|
|
@ -379,7 +379,7 @@ ADBOpTrap ; a0-a1/d1-d2 saved by OsTrap dispatch
|
|||
Title 'KbdADB - ADB Manager - RunADBRequest'
|
||||
;_______________________________________________________________________
|
||||
;
|
||||
; Routine: RunADBRequest
|
||||
; Routine: RunADBRequest 2b44c
|
||||
; Inputs: A3 - pointer to ADBBase
|
||||
;
|
||||
; Outputs: D2 - length of transmit buffer data
|
||||
|
|
@ -424,7 +424,7 @@ RunADBRequest
|
|||
Title 'KbdADB - ADB Manager - ExplicitRequestDone'
|
||||
;_______________________________________________________________________
|
||||
;
|
||||
; Routine: ExplicitRequestDone
|
||||
; Routine: ExplicitRequestDone 2b47e
|
||||
; Inputs: D2 - length of receive buffer data
|
||||
; D3 - command byte / SRQ flag (bit 31)
|
||||
; A2 - pointer to buffer containing receive data
|
||||
|
|
@ -482,7 +482,7 @@ ExplicitRequestDone
|
|||
Title 'KbdADB - ADB Manager - ImplicitRequestDone'
|
||||
;_______________________________________________________________________
|
||||
;
|
||||
; Routine: ImplicitRequestDone
|
||||
; Routine: ImplicitRequestDone 2b4b4
|
||||
; Inputs: D2 - length of receive buffer data
|
||||
; D3 - command byte / SRQ flag (bit 31)
|
||||
; A2 - pointer to buffer containing receive data
|
||||
|
|
@ -524,7 +524,7 @@ ImplicitRequestDone
|
|||
Title 'KbdADB - ADB Manager - RequestDone'
|
||||
;_______________________________________________________________________
|
||||
;
|
||||
; Routine: RequestDone
|
||||
; Routine: RequestDone 2b4d4
|
||||
; Inputs: D2 - length of receive buffer data
|
||||
; D3 - command byte / SRQ flag (bit 31)
|
||||
; A0 - pointer to buffer to pass to completion routine
|
||||
|
|
@ -559,37 +559,74 @@ RequestDone move.l a0,-(sp) ; copy buffer address to A0 save area on stack
|
|||
|
||||
TestFor SupportsIdle
|
||||
BEQ.S @notsupported
|
||||
_IdleUpdate ; this is activity, stay at full speed
|
||||
|
||||
MoveA.L (PmgrBase), A1
|
||||
CmpI.L #sleepConst, PmgrRec.SleepSaveFlag(A1)
|
||||
BEQ.B @definitelyNot
|
||||
BTst.B #$2, $129(A1)
|
||||
BEQ.B @nearEnd
|
||||
@definitelyNot
|
||||
|
||||
Move.L (A7), D3
|
||||
Move.B D3, D0
|
||||
LsR.B #$4, D0
|
||||
Bsr FindFDBInfo
|
||||
Move.B $1(A1), D0
|
||||
MoveA.L $4(A7), A1
|
||||
Move.L (A1), D3
|
||||
CmpI.B #$2, D0
|
||||
BNE.B @noTesting
|
||||
BTst.L #$17, D3
|
||||
BNE.B @idleDone
|
||||
Bra.B @nearEnd
|
||||
@noTesting
|
||||
MoveA.L (PmgrBase), A1
|
||||
CmpI.L #sleepConst, PmgrRec.SleepSaveFlag(A1)
|
||||
BEQ.B @idleDone
|
||||
CmpI.B #$3, D0
|
||||
BNE.B @idleDone
|
||||
@nearEnd
|
||||
Move.L D0, -(A7)
|
||||
Move.L #$10001, D0
|
||||
_PowerDispatch
|
||||
Move.L (A7)+, D0
|
||||
@idleDone
|
||||
@notsupported
|
||||
|
||||
movem.l (sp)+,d0/a0/a1/a2 ; setup cmd, buffer, handler, data
|
||||
; (13).start
|
||||
TestFor SupportsIdle
|
||||
beq.s @continue
|
||||
move.l d0,-(sp) ; save d0 temporarily on the stack <t10> ag
|
||||
move.l #((UsrActivity<<16)|\ ; set for user activity <K2>
|
||||
(IdleUpdateDisp<<0)),d0 ; idle update selector <K2>
|
||||
_PowerDispatch ; call power manager
|
||||
move.l (sp)+,d0 ; restore d0 <t10> ag
|
||||
@continue
|
||||
move.l a1,d1 ; test to see if handler address is valid
|
||||
beq.s @noHandler ; if not, don't call it
|
||||
|
||||
BTST #fDBInit,FDBFlag(A3) ; is ADB initialization in progress?
|
||||
BNE.S @JustDoIt ; -> yes, calling the handler now is allowed
|
||||
|
||||
MOVE.L D0,D2
|
||||
AND #$F,D2
|
||||
CMP.B #$C,D2
|
||||
BNE @justDoIt
|
||||
|
||||
; jump thru the ProductInfo table to check if a keyswitch is in the secure position <H4>
|
||||
|
||||
MOVEA.L UnivInfoPtr,A1 ; point to the ProductInfo table <H4>
|
||||
ADDA.L ProductInfo.ADBDebugUtilPtr(A1),A1 ; and get the address of its ADB table <H4>
|
||||
MOVE.L 4*adbKeySwSecure(A1),D2 ; get the offset to the keyswitch code <H4>
|
||||
BEQ.S @JustDoIt ; -> no keyswitch check, so just call the handler <H4>
|
||||
BEQ.S @MaybeDoIt ; -> no keyswitch check, so just call the handler <H4>
|
||||
MOVEM.L D0/D1/A0/A2,-(SP) ; <H4>
|
||||
ADDA.L D2,A1 ; calculate the routine's address <H4>
|
||||
JSR (A1) ; and call it <H4>
|
||||
MOVEM.L (SP)+,D0/D1/A0/A2 ; <H4>
|
||||
BEQ.S @noHandler ; -> the keyswitch is secure, so don't call the handler
|
||||
|
||||
@MaybeDoIt BTST.B #3,$240A
|
||||
BEQ.S @JustDoIt
|
||||
|
||||
MOVE.L PmgrBase,A1
|
||||
CMP.L #sleepConst,PmgrRec.SleepSaveFlag(A1)
|
||||
BEQ.S @noHandler
|
||||
|
||||
BTST.B #2,PmgrRec.PmgrFlags2(A1)
|
||||
BNE.B @noHandler
|
||||
|
||||
@JustDoIt MOVEA.L D1,A1 ; get the handler's address <H4>
|
||||
jsr (a1) ; call the handler
|
||||
|
||||
|
|
@ -602,7 +639,7 @@ RequestDone move.l a0,-(sp) ; copy buffer address to A0 save area on stack
|
|||
Title 'KbdADB - ADB Manager - Initialization'
|
||||
;______________________________________________________________________
|
||||
;
|
||||
; ADBReInit - ReInitialize the Front Desk Bus
|
||||
; ADBReInit 2b5aa - ReInitialize the Front Desk Bus
|
||||
;
|
||||
;______________________________________________________________________
|
||||
|
||||
|
|
@ -638,7 +675,7 @@ iLocalData EQU iDeviceTy
|
|||
|
||||
;______________________________________________________________________
|
||||
;
|
||||
; ADBProc - this routine lives in the JADBProc vector and is called
|
||||
; ADBProc 2b5d0 - this routine lives in the JADBProc vector and is called
|
||||
; by ADBReInit before and after initialization
|
||||
;
|
||||
;______________________________________________________________________
|
||||
|
|
@ -695,6 +732,7 @@ ADBProc
|
|||
;______________________________________________________________________
|
||||
|
||||
PostInit ; <SM3> rb
|
||||
; 2b610
|
||||
WITH ExpandMemRec,KybdDriverData ; <SM3> rb
|
||||
|
||||
_CountADBs ; Get the number of ADB devices
|
||||
|
|
@ -728,14 +766,14 @@ PostInit ; <SM3> rb
|
|||
ENDWITH ; <SM3> rb
|
||||
;______________________________________________________________________
|
||||
;
|
||||
; InitADBDrvr - this routine bring in all appropriate 'ADBS' resources and
|
||||
; InitADBDrvr 2b64c - this routine bring in all appropriate 'ADBS' resources and
|
||||
; execute the initialization routines.
|
||||
;
|
||||
;______________________________________________________________________
|
||||
|
||||
InitADBDrvr _CountADBs ; get the number of valid ADB entries
|
||||
Move D0,D3 ; save it in D3
|
||||
BEQ.S DoneSrv ; If none, nothing to do
|
||||
BEQ DoneSrv ; If none, nothing to do
|
||||
MoveQ #1,D4 ; start at first entry
|
||||
Link A6,#iLocalData ; reserve stack frame
|
||||
FSrvLoop
|
||||
|
|
@ -759,9 +797,7 @@ FSrvLoop
|
|||
_DetachResource ; detach it
|
||||
|
||||
Move.L D1,A0 ; put handle in A0
|
||||
Move.L (A0),D0 ; dereference handle
|
||||
_StripAddress ; make it a 24-bit address
|
||||
Move.L D0,A0 ; put it in A0
|
||||
Move.L (A0),A0 ; dereference handle
|
||||
Move.B iADBAddr(A6),D0 ; put ADB Address in D0
|
||||
Move.B iDeviceTy(A6),D1 ; put device type in D1
|
||||
JSR (A0) ; execute the service routine
|
||||
|
|
@ -777,7 +813,7 @@ DoneSrv
|
|||
|
||||
;_______________________________________________________________________
|
||||
;
|
||||
; InitADB - Initialize state variables
|
||||
; InitADB 2b69c - Initialize state variables
|
||||
;
|
||||
;_______________________________________________________________________
|
||||
|
||||
|
|
@ -796,6 +832,50 @@ InitADB MOVE.L #FDBDSize,D0 ; get local data area length
|
|||
LEA FDBTask,A0 ; setup the FDB VBL task
|
||||
MOVE.L A0,JKybdTask ; lomem vector
|
||||
|
||||
BTst.B #$2, ($2408)
|
||||
BEQ.B @dontHitExpandMem
|
||||
import IOPR_ADB
|
||||
Lea.L IOPR_ADB, A0
|
||||
Move.L A0, ([ExpandMem],$294)
|
||||
@dontHitExpandMem
|
||||
|
||||
Move.L UnivROMFlags, D0
|
||||
|
||||
AndI.L #$E, D0
|
||||
BEQ.B @escape
|
||||
|
||||
CmpI.L #$A, D0
|
||||
BEQ.B @escape
|
||||
|
||||
CmpI.L #$C, D0
|
||||
BEQ.B @second
|
||||
|
||||
CmpI.L #$8, D0
|
||||
BEQ.B @fourth
|
||||
|
||||
CmpI.L #$2, D0
|
||||
BNE.B @third
|
||||
|
||||
@first Lea.L ($FFFDB592).L, A0
|
||||
Lea.L @first(A0.L), A0
|
||||
Bra.B @done
|
||||
|
||||
@second Lea.L ($FFFDB5A2).L, A0
|
||||
Lea.L @second(A0.L), A0
|
||||
Bra.B @done
|
||||
|
||||
@third Lea.L ($FFFDB5CE).L, A0
|
||||
Lea.L @third(A0.L), A0
|
||||
Bra.B @done
|
||||
|
||||
@fourth Lea.L ($FFFDB5DE).L, A0
|
||||
Lea.L @fourth(A0.L), A0
|
||||
|
||||
@done MoveA.L (UnivInfoPtr), A1
|
||||
SubA.L A1, A0
|
||||
Move.L A0, $48(A1)
|
||||
@escape
|
||||
|
||||
; jump thru the ProductInfo table to call the hardware-dependent initialization code
|
||||
|
||||
MOVEA.L UnivInfoPtr,A0 ; point to the ProductInfo table <H4>
|
||||
|
|
@ -838,7 +918,7 @@ ReInit ori.w #HiIntMask,sr ; mask out interrupts
|
|||
|
||||
;_______________________________________________________________________
|
||||
;
|
||||
; InitDevT - Initialize the Device Table
|
||||
; InitDevT 2b7a0 - Initialize the Device Table
|
||||
;
|
||||
; NOTE: everything after BusReset below is part of an ADB completion
|
||||
; routine, and thus is run at interrupt level 1. No calls
|
||||
|
|
@ -853,17 +933,19 @@ InitDevT bsr BusReset ; reset all devices on the bus
|
|||
@PollNext move.b d0,InitAddr(a3) ; save device address
|
||||
bsr TalkR3 ; issue a Talk R3 command (asynchronously)
|
||||
move.b InitAddr(a3),d0 ; restore poll address
|
||||
tst.b (a0)+ ; test reply length, see if device returned data
|
||||
tst.b (a0) ; test reply length, see if device returned data
|
||||
beq.s @NoDevice ; no, nothing to install
|
||||
|
||||
; there is a response from the device in the address, so update the
|
||||
; device table according to the device
|
||||
|
||||
@whoaGoBack
|
||||
moveq.l #0,d1 ; zero extend for indexing
|
||||
move.b DevTOffset(a3),d1 ; get offset to devicetable
|
||||
move.b 1(a0),FDBDevTy(a3,d1.w) ; copy device handler ID into table
|
||||
move.b 2(a0),FDBDevTy(a3,d1.w) ; copy device handler ID into table
|
||||
move.b d0,FDBOAddr(a3,d1.w); save device address
|
||||
move.b d0,FDBAddr(a3,d1.w) ; save device address
|
||||
move.b d0,FDBOAddr(a3,d1.w); save device address
|
||||
|
||||
cmpi.b #KbdAddr,d0 ; is it a keyboard type device?
|
||||
bne.s @notKbd ; no, branch
|
||||
|
|
@ -878,10 +960,29 @@ InitDevT bsr BusReset ; reset all devices on the bus
|
|||
move.w HasDev(a3),d2 ; get value in HasDev
|
||||
bset.l d0,d2 ; remember which address has device
|
||||
move.w d2,HasDev(A3) ; save it
|
||||
Bra @skipNewNoDeviceCode
|
||||
@NoDevice
|
||||
|
||||
BTst.B #$2, ($2408)
|
||||
BEQ.B @skipNewNoDeviceCode
|
||||
|
||||
Tst.L ([$2B6],$29C)
|
||||