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537 lines
15 KiB
Plaintext
537 lines
15 KiB
Plaintext
;
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; File: KernelEx.a
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;
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; Contains: Routines to force exception status in the FPU for
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; exceptional cases detected or reported within the
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; transcendental functions
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;
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; Originally Written by: Motorola Inc.
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; Adapted to Apple/MPW: Jon Okada
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;
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; Copyright: © 1990, 1991 by Apple Computer, Inc., all rights reserved.
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;
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; This file is used in these builds: Mac32
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;
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; Change History (most recent first):
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;
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; <3> 6/24/91 BG Modified "src_nan" to not quiet signaling NaN input
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; when SNaN exception is enabled. Modified "t_resdnrm" to set UNFL, AUNFL, INEX2, and AINEX
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; in USER_FPSR(a6) when rounding precision is narrower
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; than extended. Modified "t_unfl" and "t_resdnrm" to normalize unnormalized
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; results and produce zeros with zero exponent.
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; <2> 3/30/91 BG Rolling in Jon Okada's latest changes.
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; <1> 12/14/90 BG First checked into TERROR/BBS.
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; kernelex.a
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; Based upon Motorola file 'kernel_ex.sa'
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; CHANGE LOG:
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; 04 Jan 91 JPO Deleted constant "huge" (not referenced).
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; 28 May 91 JPO Modified "src_nan" to not quiet signaling NaN input
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; when SNaN exception is enabled.
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; 14 Jun 91 JPO Modified "t_resdnrm" to set UNFL, AUNFL, INEX2, and AINEX
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; in USER_FPSR(a6) when rounding precision is narrower
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; than extended.
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; 17 Jun 91 JPO Modified "t_unfl" and "t_resdnrm" to normalize unnormalized
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; results and produce zeros with zero exponent.
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;
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*
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* kernel_ex.sa 3.1 12/10/90
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*
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* This file contains routines to force exception status in the
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* fpu for exceptional cases detected or reported within the
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* transcendental functions. Typically, the t_xx routine will
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* set the appropriate bits in the USER_FPSR word on the stack.
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* The bits are tested in gen_except.sa to determine if an exceptional
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* situation needs to be created on return from the FPSP.
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*
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* Copyright (C) Motorola, Inc. 1990
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* All Rights Reserved
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*
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* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
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* The copyright notice above does not evidence any
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* actual or intended publication of such source code.
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* KERNEL_EX IDNT 2,1 Motorola 040 Floating Point Software Package
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mns_inf dc.l $ffff0000,$00000000,$00000000
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pls_inf dc.l $7fff0000,$00000000,$00000000
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nan dc.l $7fff0000,$ffffffff,$ffffffff
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;huge dc.l $7ffe0000,$ffffffff,$ffffffff ; deleted <1/4/91, JPO>
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*
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* DZ exception
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*
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*
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* if dz trap disabled
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* store properly signed inf (use sign of etemp) into fp0
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* set FPSR exception status dz bit, condition code
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* inf bit, and accrued dz bit
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* return
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* frestore the frame into the machine (done by unimp_hd)
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*
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* else dz trap enabled
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* set exception status bit & accrued bits in FPSR
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* set flag to disable sto_res from corrupting fp register
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* return
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* frestore the frame into the machine (done by unimp_hd)
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*
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* t_dz2 is used by monadic functions such as flogn (from do_func).
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* t_dz is used by monadic functions such as satanh (from the
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* transcendental function).
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*
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t_dz2:
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bset.b #neg_bit,FPSR_CC(a6) ;set neg bit in FPSR
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fmove.l #0,FPSR ;clr status bits (Z set)
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btst.b #dz_bit,FPCR_ENABLE(a6) ;test FPCR for dz exc enabled
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bne.b dz_ena_end
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bra.b m_inf ;flogx always returns -inf
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t_dz:
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fmove.l #0,FPSR ;clr status bits (Z set)
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btst.b #dz_bit,FPCR_ENABLE(a6) ;test FPCR for dz exc enabled
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bne.b dz_ena
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*
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* dz disabled
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*
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btst.b #sign_bit,ETEMP_EX(a6) ;check sign for neg or pos
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beq.b p_inf ;branch if pos sign
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m_inf:
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fmovem.x mns_inf,fp0 ;load -inf
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bset.b #neg_bit,FPSR_CC(a6) ;set neg bit in FPSR
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bra.b set_fpsr
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p_inf:
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fmovem.x pls_inf,fp0 ;load +inf
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set_fpsr:
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or.l #dzinf_mask,USER_FPSR(a6) ;set I,DZ,ADZ
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rts
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*
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* dz enabled
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*
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dz_ena:
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btst.b #sign_bit,ETEMP_EX(a6) ;check sign for neg or pos
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beq.b dz_ena_end
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bset.b #neg_bit,FPSR_CC(a6) ;set neg bit in FPSR
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dz_ena_end:
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or.l #dzinf_mask,USER_FPSR(a6) ;set I,DZ,ADZ
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st.b STORE_FLG(a6)
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rts
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*
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* OPERR exception
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*
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* if (operr trap disabled)
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* set FPSR exception status operr bit, condition code
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* nan bit; Store default NAN into fp0
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* frestore the frame into the machine (done by unimp_hd)
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*
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* else (operr trap enabled)
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* set FPSR exception status operr bit, accrued operr bit
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* set flag to disable sto_res from corrupting fp register
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* frestore the frame into the machine (done by unimp_hd)
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*
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t_operr:
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or.l #opnan_mask,USER_FPSR(a6) ;set NaN, OPERR, AIOP
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btst.b #operr_bit,FPCR_ENABLE(a6) ;test FPCR for operr enabled
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bne.b op_ena
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fmovem.x nan,fp0 ;load default nan
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rts
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op_ena:
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st.b STORE_FLG(a6) ;do not corrupt destination
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rts
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*
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* t_unfl --- UNFL exception
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*
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* This entry point is used by all routines requiring unfl, inex2,
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* aunfl, and ainex to be set on exit.
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*
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* On entry, a0 points to the exceptional operand. The final exceptional
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* operand is built in FP_SCR1 and only the sign from the original operand
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* is used.
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*
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t_unfl:
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clr.l FP_SCR1(a6) ;set exceptional operand to zero
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clr.l FP_SCR1+4(a6)
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clr.l FP_SCR1+8(a6)
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tst.b (a0) ;extract sign from caller's exop
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bpl.b unfl_signok
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bset #sign_bit,FP_SCR1(a6)
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unfl_signok:
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lea.l FP_SCR1(a6),a0
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or.l #unfinx_mask,USER_FPSR(a6)
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* ;set UNFL, INEX2, AUNFL, AINEX
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unfl_con:
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btst.b #unfl_bit,FPCR_ENABLE(a6)
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beq.b unfl_dis
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unfl_ena:
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bfclr STAG(a6){5:3} ;clear wbtm66,wbtm1,wbtm0
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bset.b #wbtemp15_bit,WB_BYTE(a6) ;set wbtemp15
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bset.b #sticky_bit,STICKY(a6) ;set sticky bit
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bclr.b #E1,E_BYTE(a6)
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unfl_dis:
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bfextu FPCR_MODE(a6){0:2},d0 ;get round precision
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bclr.b #sign_bit,LOCAL_EX(a0)
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sne LOCAL_SGN(a0) ;convert to internal ext format
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bsr unf_sub ;returns IEEE result at a0
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* ;and sets FPSR_CC accordingly
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bfclr LOCAL_SGN(a0){0:8} ;convert back to IEEE ext format
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beq.b unfl_fin
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bset.b #sign_bit,LOCAL_EX(a0)
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bset.b #sign_bit,FP_SCR1(a6) ;set sign bit of exc operand
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; If result is unnormalized, normalize it here. If result is zero with nonzero <T3> thru next <T3>
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; exponent, zero exponent here. Only possible values at this point are zero,
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; extended denorm, or extended unnormal (due to single/double denorm). <6/17/91, JPO>
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unfl_fin:
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move.w LOCAL_EX(a0),d1 ; isolate exponent <6/17/91, JPO>
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andi.w #$7fff,d1 ; <6/17/91, JPO>
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beq.b @2 ; zero exponent means all OK <6/17/91, JPO>
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tst.l LOCAL_HI(a0) ; test high mantissa <6/17/91, JPO>
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bmi.b @2 ; normal <6/17/91, JPO>
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bne.b @1 ; unnormalized <6/17/91, JPO>
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tst.l LOCAL_LO(a0) ; test low mantissa <6/17/91, JPO>
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bne.b @1 ; unnormalized <6/17/91, JPO>
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bfclr LOCAL_EX(a0){1:15} ; zero result. zero exponent <6/17/91, JPO>
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bra.b @2
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@1: ; label ADDED <6/17/91, JPO>
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bsr nrm_set ; normalize unnormal <6/17/91, JPO>
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@2: ; label added <6/17/91, JPO> <T3>
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fmovem.x (a0),fp0 ;store result in fp0
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rts
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*
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* t_ovfl2 --- OVFL exception (without inex2 returned)
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*
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* This entry is used by scale to force catastrophic overflow. The
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* ovfl, aovfl, and ainex bits are set, but not the inex2 bit.
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*
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t_ovfl2:
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or.l #ovfl_inx_mask,USER_FPSR(a6)
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move.l ETEMP(a6),FP_SCR1(a6)
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move.l ETEMP_HI(a6),FP_SCR1+4(a6)
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move.l ETEMP_LO(a6),FP_SCR1+8(a6)
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*
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* Check for single or double round precision. If single, check if
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* the lower 40 bits of ETEMP are zero; if not, set inex2. If double,
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* check if the lower 21 bits are zero; if not, set inex2.
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*
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move.b FPCR_MODE(a6),d0
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andi.b #$c0,d0
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beq.b t_work ;if extended, finish ovfl processing
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cmpi.b #$40,d0 ;test for single
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bne.b t_dbl
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t_sgl:
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tst.b ETEMP_LO(a6)
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bne.b t_setinx2
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move.l ETEMP_HI(a6),d0
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andi.l #$ff,d0 ;look at only lower 8 bits
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bne.b t_setinx2
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bra.b t_work
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t_dbl:
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move.l ETEMP_LO(a6),d0
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andi.l #$7ff,d0 ;look at only lower 11 bits
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beq.b t_work
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t_setinx2:
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or.l #inex2_mask,USER_FPSR(a6)
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bra.b t_work
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*
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* t_ovfl --- OVFL exception
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*
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*** Note: the exc operand is returned in ETEMP.
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*
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t_ovfl:
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or.l #ovfinx_mask,USER_FPSR(a6)
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t_work:
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btst.b #ovfl_bit,FPCR_ENABLE(a6) ;test FPCR for ovfl enabled
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beq.b ovf_dis
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ovf_ena:
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clr.l FP_SCR1(a6) ;set exceptional operand
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clr.l FP_SCR1+4(a6)
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clr.l FP_SCR1+8(a6)
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bfclr STAG(a6){5:3} ;clear wbtm66,wbtm1,wbtm0
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bclr.b #wbtemp15_bit,WB_BYTE(a6) ;clear wbtemp15
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bset.b #sticky_bit,STICKY(a6) ;set sticky bit
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bclr.b #E1,E_BYTE(a6)
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* ;fall through to disabled case
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* For disabled overflow call 'ovf_r_k'. This routine loads the
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* correct result based on the rounding precision, destination
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* format, rounding mode and sign.
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*
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ovf_dis:
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bsr ovf_r_k ;returns unsigned ETEMP_EX
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* ;and sets FPSR_CC accordingly.
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bfclr ETEMP_SGN(a6){0:8} ;fix sign
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beq.b ovf_pos
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bset.b #sign_bit,ETEMP_EX(a6)
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bset.b #sign_bit,FP_SCR1(a6) ;set exceptional operand sign
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ovf_pos:
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fmovem.x ETEMP(a6),fp0 ;move the result to fp0
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rts
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*
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* INEX2 exception
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*
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* The inex2 and ainex bits are set.
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*
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t_inx2:
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or.l #inx2a_mask,USER_FPSR(a6) ;set INEX2, AINEX
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rts
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*
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* Force Inex2
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*
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* This routine is called by the transcendental routines to force
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* the inex2 exception bits set in the FPSR. If the underflow bit
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* is set, but the underflow trap was not taken, the aunfl bit in
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* the FPSR must be set.
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*
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t_frcinx:
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or.l #inx2a_mask,USER_FPSR(a6) ;set INEX2, AINEX
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btst.b #unfl_bit,FPSR_EXCEPT(a6) ;test for unfl bit set
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beq.b no_uacc1 ;if clear, do not set aunfl
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bset.b #aunfl_bit,FPSR_AEXCEPT(a6)
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no_uacc1:
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rts
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*
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* DST_NAN
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*
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* Determine if the destination nan is signalling or non-signalling,
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* and set the FPSR bits accordingly. See the MC68040 User's Manual
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* section 3.2.2.5 NOT-A-NUMBERS.
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*
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dst_nan:
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btst.b #sign_bit,FPTEMP_EX(a6) ;test sign of nan
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beq.b dst_pos ;if clr, it was positive
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bset.b #neg_bit,FPSR_CC(a6) ;set N bit
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dst_pos:
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btst.b #signan_bit,FPTEMP_HI(a6) ;check if signalling
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beq.b dst_snan ;branch if signalling
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fmove.l d1,fpcr ;restore user's rmode/prec
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fmove.x FPTEMP(a6),fp0 ;return the non-signalling nan
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*
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* Check the source nan. If it is signalling, snan will be reported.
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*
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move.b STAG(a6),d0
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andi.b #$e0,d0
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cmpi.b #$60,d0
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bne.b no_snan
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btst.b #signan_bit,ETEMP_HI(a6) ;check if signalling
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bne.b no_snan
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or.l #snaniop_mask,USER_FPSR(a6) ;set NAN, SNAN, AIOP
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no_snan:
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rts
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dst_snan:
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btst.b #snan_bit,FPCR_ENABLE(a6) ;check if trap enabled
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beq.b dst_dis ;branch if disabled
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or.b #nan_tag,DTAG(a6) ;set up dtag for nan
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st.b STORE_FLG(a6) ;do not store a result
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or.l #snaniop_mask,USER_FPSR(a6) ;set NAN, SNAN, AIOP
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rts
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dst_dis:
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bset.b #signan_bit,FPTEMP_HI(a6) ;set SNAN bit in sop
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fmove.l d1,fpcr ;restore user's rmode/prec
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fmove.x FPTEMP(a6),fp0 ;load non-sign. nan
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or.l #snaniop_mask,USER_FPSR(a6) ;set NAN, SNAN, AIOP
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rts
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*
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* SRC_NAN
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*
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* Determine if the source nan is signalling or non-signalling,
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* and set the FPSR bits accordingly. See the MC68040 User's Manual
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* section 3.2.2.5 NOT-A-NUMBERS.
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*
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src_nan:
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btst.b #sign_bit,ETEMP_EX(a6) ;test sign of nan
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beq.b src_pos ;if clr, it was positive
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bset.b #neg_bit,FPSR_CC(a6) ;set N bit
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src_pos:
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btst.b #signan_bit,ETEMP_HI(a6) ;check if signalling
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beq.b src_snan ;branch if signalling
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fmove.l d1,fpcr ;restore user's rmode/prec
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fmove.x ETEMP(a6),fp0 ;return the non-signalling nan
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rts
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src_snan:
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btst.b #snan_bit,FPCR_ENABLE(a6) ;check if trap enabled
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beq.b src_dis ;branch if disabled
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; bset.b #signan_bit,ETEMP_HI(a6) ;set SNAN bit in sop - DELETED <5/28/91, JPO> <T3>
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; or.b #norm_tag,DTAG(a6) ;set up dtag for norm - DELETED <5/28/91, JPO> <T3>
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or.b #nan_tag,STAG(a6) ;set up stag for nan
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st.b STORE_FLG(a6) ;do not store a result
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or.l #snaniop_mask,USER_FPSR(a6) ;set NAN, SNAN, AIOP
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rts
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src_dis:
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bset.b #signan_bit,ETEMP_HI(a6) ;set SNAN bit in sop
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fmove.l d1,fpcr ;restore user's rmode/prec
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fmove.x ETEMP(a6),fp0 ;load non-sign. nan
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or.l #snaniop_mask,USER_FPSR(a6) ;set NAN, SNAN, AIOP
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rts
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*
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* For all functions that have a denormalized input and that f(x)=x,
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* this is the entry point
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*
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t_extdnrm:
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or.l #unfinx_mask,USER_FPSR(a6)
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* ;set UNFL, INEX2, AUNFL, AINEX
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bra.b xdnrm_con
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*
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* Entry point for scale with extended denorm. The function does
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* not set inex2, aunfl, or ainex.
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*
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t_resdnrm:
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or.l #unfl_mask,USER_FPSR(a6)
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xdnrm_con:
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btst.b #unfl_bit,FPCR_ENABLE(a6)
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beq.b xdnrm_dis
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*
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* If exceptions are enabled, the additional task of setting up WBTEMP
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* is needed so that when the underflow exception handler is entered,
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* the user perceives no difference between what the 040 provides vs.
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* what the FPSP provides.
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*
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xdnrm_ena:
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move.l a0,-(a7)
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move.l LOCAL_EX(a0),FP_SCR1(a6)
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move.l LOCAL_HI(a0),FP_SCR1+4(a6)
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move.l LOCAL_LO(a0),FP_SCR1+8(a6)
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lea FP_SCR1(a6),a0
|
|
|
|
bclr.b #sign_bit,LOCAL_EX(a0)
|
|
sne LOCAL_SGN(a0) ;convert to internal ext format
|
|
tst.w LOCAL_EX(a0) ;check if input is denorm
|
|
beq.b xdnrm_dn ;if so, skip nrm_set
|
|
bsr nrm_set ;normalize the result (exponent
|
|
* ;will be negative
|
|
xdnrm_dn:
|
|
bclr.b #sign_bit,LOCAL_EX(a0) ;take off false sign
|
|
bfclr LOCAL_SGN(a0){0:8} ;change back to IEEE ext format
|
|
beq.b xdep
|
|
bset.b #sign_bit,LOCAL_EX(a0)
|
|
xdep:
|
|
bfclr STAG(a6){5:3} ;clear wbtm66,wbtm1,wbtm0
|
|
bset.b #wbtemp15_bit,WB_BYTE(a6) ;set wbtemp15
|
|
bclr.b #sticky_bit,STICKY(a6) ;clear sticky bit
|
|
bclr.b #E1,E_BYTE(a6)
|
|
move.l (a7)+,a0
|
|
xdnrm_dis:
|
|
bfextu FPCR_MODE(a6){0:2},d0 ;get round precision
|
|
bne.b not_ext ;if not round extended, store
|
|
* ;IEEE defaults
|
|
is_ext:
|
|
btst.b #sign_bit,LOCAL_EX(a0)
|
|
beq.b xdnrm_store
|
|
|
|
bset.b #neg_bit,FPSR_CC(a6) ;set N bit in FPSR_CC
|
|
|
|
bra.b xdnrm_store
|
|
|
|
not_ext:
|
|
or.l #unfinx_mask,USER_FPSR(a6) ; set UNFL, AUNFL, INEX2, AINEX <6/14/91, JPO> <T3>
|
|
bclr.b #sign_bit,LOCAL_EX(a0)
|
|
sne LOCAL_SGN(a0) ;convert to internal ext format
|
|
bsr unf_sub ;returns IEEE result pointed by
|
|
* ;a0; sets FPSR_CC accordingly
|
|
bfclr LOCAL_SGN(a0){0:8} ;convert back to IEEE ext format
|
|
beq.b xdnrm_store
|
|
bset.b #sign_bit,LOCAL_EX(a0)
|
|
xdnrm_store:
|
|
bra unfl_fin ; continue above <6/17/91, JPO> <T3>
|
|
; fmovem.x (a0),fp0 ;store result in fp0 - DELETED <6/17/91, JPO> <T3>
|
|
; rts ; DELETED <6/17/91, JPO> <T3>
|
|
|
|
*
|
|
* This subroutine is used for dyadic operations that use an extended
|
|
* denorm within the kernel. The approach used is to capture the frame,
|
|
* fix/restore.
|
|
*
|
|
|
|
t_avoid_unsupp:
|
|
link a2,#-LOCAL_SIZE ;so that a2 fpsp.h negative
|
|
* ;offsets may be used
|
|
fsave -(a7)
|
|
tst.b 1(a7) ;check if idle, exit if so
|
|
beq.b idle_end
|
|
btst.b #E1,E_BYTE(a2) ;check for an E1 exception if
|
|
* ;enabled, there is an unsupp
|
|
beq.b end_avun ;else, exit
|
|
btst.b #7,DTAG(a2) ;check for denorm destination
|
|
beq.b src_den ;else, must be a source denorm
|
|
*
|
|
* handle destination denorm
|
|
*
|
|
lea FPTEMP(a2),a0
|
|
btst.b #sign_bit,LOCAL_EX(a0)
|
|
sne LOCAL_SGN(a0) ;convert to internal ext format
|
|
bclr.b #7,DTAG(a2) ;set DTAG to norm
|
|
bsr nrm_set ;normalize result, exponent
|
|
* ;will become negative
|
|
bclr.b #sign_bit,LOCAL_EX(a0) ;get rid of fake sign
|
|
bfclr LOCAL_SGN(a0){0:8} ;convert back to IEEE ext format
|
|
beq.b ck_src_den ;check if source is also denorm
|
|
bset.b #sign_bit,LOCAL_EX(a0)
|
|
ck_src_den:
|
|
btst.b #7,STAG(a2)
|
|
beq.b end_avun
|
|
src_den:
|
|
lea ETEMP(a2),a0
|
|
btst.b #sign_bit,LOCAL_EX(a0)
|
|
sne LOCAL_SGN(a0) ;convert to internal ext format
|
|
bclr.b #7,STAG(a2) ;set STAG to norm
|
|
bsr nrm_set ;normalize result, exponent
|
|
* ;will become negative
|
|
bclr.b #sign_bit,LOCAL_EX(a0) ;get rid of fake sign
|
|
bfclr LOCAL_SGN(a0){0:8} ;convert back to IEEE ext format
|
|
beq.b den_com
|
|
bset.b #sign_bit,LOCAL_EX(a0)
|
|
den_com:
|
|
move.b #$fe,CU_SAVEPC(a2) ;set continue frame
|
|
clr.w NMNEXC(a2) ;clear NMNEXC
|
|
bclr.b #E1,E_BYTE(a2)
|
|
* fmove.l FPSR,FPSR_SHADOW(a2)
|
|
* bset.b #SFLAG,E_BYTE(a2)
|
|
* bset.b #XFLAG,T_BYTE(a2)
|
|
end_avun:
|
|
frestore (a7)+
|
|
unlk a2
|
|
rts
|
|
idle_end:
|
|
add.l #4,a7
|
|
unlk a2
|
|
rts
|
|
|
|
|