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337 lines
12 KiB
Plaintext
337 lines
12 KiB
Plaintext
;
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; File: MaceEqu.a
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;
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; Contains: Equates for accessing the Ethernet Media Access
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; Controller (MACE)
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;
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; Written by: Mark A. Law
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;
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; Copyright: © 1991-1993 by Apple Computer, Inc. All rights reserved.
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;
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; This file is used in these builds: Mac32
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;
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; Change History (most recent first):
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;
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; <SM6> 6/14/93 kc Roll in Ludwig.
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; <LW4> 5/1/93 mal #1082434 Added records for new GetMem & FreeMem rtns.
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; <LW3> 3/21/93 mal Versioned record for MACE 'ecfg' rsrc.
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; <LW2> 1/27/93 mal Added MACEecfg rsrc support.
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; <SM5> 12/4/92 mal Removed OFLO bit from recv pkt status.
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; <SM4> 11/19/92 mal Added equ for yet another bit AMD didn't tell us about.
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; <SM3> 10/30/92 mal MaceInitParms record change.
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; <SM2> 10/13/92 mal -changed status thats passed to RecvRtn to lw
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; <1> 10/6/92 GDW New location for ROMLink tool.
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; <SM2> 6/22/92 mal Changes to support PSC2's (EVT2) Ethernet DMA receive model.
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; <P4> 4/30/92 mal Expanded MaceInitParms record.
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; <P3> 4/27/92 mal Added MaceInit parameters record.
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; <P2> 3/23/92 mal Added MACE MAC config reg bit defines
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;
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; ---------------------------------------------------------
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; MACE Registers
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; ---------------------------------------------------------
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MACERegBase EQU $50F1C000 ; Mace Reg Base on Cyclone
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MACERegs RECORD 0
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MACE_RX_FIFO DS.W 1 ;RD RXData -Read Status first
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ORG *+$e
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MACE_XMIT_FIFO DS.W 1 ;TX TXData
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ORG *+$e
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MACE_TX_FRM_CNTRL DS.B 1 ;RD/WR 01=Retry,XMTFCS,AUTOPAD
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ORG *+$f
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MACE_TX_FRM_STAT DS.B 1 ;RD
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ORG *+$f
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MACE_TX_RETRY_CNT DS.B 1 ;RD
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ORG *+$f
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MACE_RX_FRM_CNTRL DS.B 1 ;RD/WR 00 = Not_AutoStripPad
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ORG *+$f
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MACE_RX_FRM_STAT DS.B 1 ;RD Read 4x to get RX Status of packet
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ORG *+$f
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MACE_FIFO_FRM_CNT DS.B 1 ;RD Number of frames in FIFO
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ORG *+$f
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MACE_INT DS.B 1 ;RD_1 Interupt Source bits
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ORG *+$f
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MACE_INT_MSK DS.B 1 ;RD/WR Interupt Enables
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ORG *+$f
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MACE_POLL DS.B 1 ;RD Yet another status location
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ORG *+$f
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MACE_BIU_CNFG DS.B 1 ;RD/WR 20 = normal mode 01 = Soft Reset
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ORG *+$f
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MACE_FIFO_CNFG DS.B 1
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ORG *+$f
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MACE_MAC_CNFG DS.B 1 ;Enables
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ORG *+$f
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MACE_PLS_CNFG DS.B 1 ;RD/WR 0=Normal Mode
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ORG *+$f
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MACE_PHY_CNFG DS.B 1 ;RD/WR Reserved,Dude.
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ORG *+$f
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MACE_CHIP_ID_LOW DS.B 1 ;RD Just Reads ID
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ORG *+$f
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MACE_CHIP_ID_HIGH DS.B 1 ;RD Just Reads ID
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ORG *+$f
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MACE_ADDR_CNFG DS.B 1 ;RD/WR 04=Phy_Addr, 02=Log_Addr
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ORG *+$1f
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MACE_LOG_ADDR DS.B 1 ;Load with 6 Zeros
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ORG *+$f
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MACE_PHY_ADDR DS.B 1 ;Load with Address
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ORG *+$2f
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MACE_MISSED_PKT_CNT DS.B 1 ;RD
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ORG *+$4f
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MACE_USER_TEST_REG DS.B 1 ;
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ENDR
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;
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; MACE Interrupt Reg. & Int. Reg. Mask Bit defines
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; MACE Int. Reg - Read/Clear; MACE Int. Mask Reg. - Read/Write
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;
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BABL EQU 6 ; Babble, Xmit timeout error
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CERR EQU 5 ; Signal Quality Error (SQE), xmit
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RCVCO EQU 4 ; Receive Collision Cnt Overflow
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MPCO EQU 2 ; Missed Pkt Cnt Overflow
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RCVINT EQU 1 ; Rcv int
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XMTINT EQU 0 ; Xmit int
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; mask to disable all MACE ints
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MaceIntMask EQU (1<<BABL)+(1<<CERR)+(1<<RCVCO)+(1<<MPCO)+(1<<RCVINT)+(1<<XMTINT)
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OurIntsMask EQU (1<<RCVINT) ; ignore recv ints
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;
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; MACE Transmit Frame Status Reg. Bit defines
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; Note: ONE and MORE are swapped prior to CURIO B0 MACE
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;
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XMTSV EQU 7 ; transmit status field valid when 1
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UFLO EQU 6 ; underflow - xmit fifo
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LCOL EQU 5 ; late collision
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MORE EQU 4 ; more than 1 retry needed to xmit
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ONE EQU 3 ; exactly 1 retry needed to xmit
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DEFER EQU 2 ; transmission defered at least once
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LCAR EQU 1 ; loss of carrier
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RTRY EQU 0 ; retry
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;
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; MACE Transmit Frame Control Reg. Bit defines (byte)
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;
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DRTRY EQU 7 ; disable retry
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DXMTFCS EQU 3 ; disable xmit fcs
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APADXMT EQU 0 ; enable xmt autopad
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; -forces generation of fcs
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;
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; MACE Receive Frame Control Reg. Bit defines (byte)
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;
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ASTRIPRCV EQU 0 ; enable rcv autopad stripping
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; -forces stripping of fcs
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;
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; MACE Receive Status Reg. Bit defines (long)
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;
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; Receive Message Byte Count (byte0)
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; Bits 7-0 : Recv Message Byte Count bits 7-0
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; Receive Status (byte1)
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; Bits 3-0 : Recv Message Byte Count bits 11-8
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; Bits 7-4 : Recv Message Status bits
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RcvOFLO EQU 7 ; receive fifo overflow
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RcvCLSN EQU 6 ; late collision during recv
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RcvFRAM EQU 5 ; frame error, non-integer # of bytes
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RcvFCS EQU 4 ; frame check sequence error
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; Receive Runt Packet Count (byte2)
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; -number of runts recv'd since last successfully recv'd pkt
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; -maxs at 255
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; Receive Collision Count (byte3)
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; -number of collisions since last successfully recv'd pkt
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; -maxs at 255
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;
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; MACE Bus Interface Unit Reg. Bit defines (byte)
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;
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BSWAP EQU 7 ; byte swap mode, 0-Intel, 1-Motorola
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; Transmit start point Bits 5-4
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XMSTP EQU 4 ; bit shift offset
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MACERESET EQU 0 ; software reset
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; Transmit start point equates
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; -controls when preamble xmit starts
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XMTS4 EQU $00 ; start when 4 bytes in FIFO
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XMTS16 EQU $10 ; start when 16 bytes in FIFO
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XMTS64 EQU $20 ; start when 64 bytes in FIFO
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XMTS112 EQU $30 ; start when 112 bytes in FIFO
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;
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; MACE FIFO Configuration Reg. Bit defines (byte)
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; -fifo water mark changes ignored until fw reset bit set
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; Transmit FIFO water mark Bits 7-6
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XMTFW EQU 6 ; bit shift offset
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; Receive FIFO water mark Bits 5-4
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RCVFW EQU 4 ; bit shift offset
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XMTFWR EQU 3 ; xmit fifo water mark reset
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RCVFWR EQU 2 ; recv fifo water mark reset
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XMTBRST EQU 1 ; xmit burst
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RCVBRST EQU 0 ; recv burst
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; FIFO watermark equates
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RFW16 EQU $00 ; 16 byte recv FIFO watermark
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RFW32 EQU $10 ; 32 byte recv FIFO watermark
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RFW64 EQU $20 ; 64 byte recv FIFO watermark
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TFW16 EQU $00 ; 16 byte xmit FIFO watermark
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TFW32 EQU $40 ; 32 byte xmit FIFO watermark
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TFW64 EQU $80 ; 64 byte xmit FIFO watermark
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;
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; MACE MAC Configuration Reg. Bit defines (byte)
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;
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PROMISC EQU 7 ; promiscuous mode, recv all valid frames
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DXMT2PD EQU 6 ; disable xmit 2-part deferral algorithm
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EMBA EQU 5 ; enable modified back-off algorithm
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ENXMT EQU 1 ; enable xmit
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ENRCV EQU 0 ; enable recv
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;
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; MACE Physical Layer Signaling Reg. Bit defines (byte)
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;
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XMTSEL EQU 3 ; xmit mode select
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; Port Select Bits 2-1
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PORTSEL EQU 1 ; bit shift offset
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ENSTS EQU 0 ; enable optional I/O function status
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;
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; MACE Internal Address Configuration Reg. Bit defines (byte)
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;
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ADDRCHG EQU 7 ; address change enable
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PHYADDR EQU 2 ; physical address select
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LOGADDR EQU 1 ; logical address select
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;
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; MACE User Test Reg. Bit defines (byte)
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;
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;¥¥¥¥¥ WARNING: DO NOT EVER SET BIT 7 or you'll fry the MACE!!!! ¥¥¥¥¥
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; Bit 6 (disable) is set during MACE init to disallow an erroneous and/or
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; malicious setting of RTRE.
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RTRE EQU 7 ; reserved test register enable
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RTRD EQU 6 ; reserved test register disable
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;¥¥¥¥¥
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RPA EQU 5 ; runt packet accept
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FCOLL EQU 4 ; force a collision, use with loopback
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RCVFCSE EQU 3 ; receive fcs enable, use with loopback
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; Loopback control Bits 2-1, %XX0 ¥¥¥ NOT FOR BIT SHIFTS!
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NOLPB EQU %000 ; disable loopback mode
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EXTLPB EQU %010 ; external loopback mode
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INTLPB EQU %100 ; internal loopback, no MENDEC
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MENDECLPB EQU %110 ; internal loopback, with MENDEC
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;
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; Misc. equates
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;
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MondoPkt EQU 2000 ; Value > max pkt, used for Recv DMA cnt
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CntRegMask EQU $0001ffff ; Ignore upper 15 bits
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nobuff EQU -2 ; no xmit buffer available
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;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ Network Statistics
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NetStats RECORD 0 ; network management stats.
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TxOK DS.L 1 ; frames transmitted OK
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sCollFrame DS.L 1 ; single collision frames
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mCollFrame DS.L 1 ; multiple collision frames
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CollFrame DS.L 1 ; collision frames
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DefTx DS.L 1 ; deferred transmissions
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LateColl DS.L 1 ; late collisions
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ExcessColl DS.L 1 ; excessive collisions
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ExcessDef DS.L 1 ; excessive defferals
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InMACTxErr DS.L 1 ; internal MAC transmit errors
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RxOK DS.L 1 ; frames received OK
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MultiRxOK DS.L 1 ; multicast frames recd OK
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BroadRxOK DS.L 1 ; broadcast frames recd OK
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FCSerr DS.L 1 ; frame check sequence errors
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FAerr DS.L 1 ; frame alignment errors
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MPerr DS.L 1 ; missed packet errors
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Size EQU *
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ENDR
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;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ General Equates
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TalliesPerSec EQU 5000000 ; number of timer ticks/second
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TxMaxRetries EQU 4 ; max attempts to retry aborted xmits
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Max_Tx_Packets EQU 16 ; maximum # of chained Tx packets
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Min_Pkt_Size EQU 60 ; minimum packet size
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Min_Rx_Buffs EQU 2 ; minimum # of recv descriptors/buffers
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Max_Pkt_Size EQU 1518 ; maximum packet size (inc. CRC)
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EOL_Bit EQU 0 ; end-of-link bit
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;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ For GetMemory call
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GetMem RECORD 0
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memsize DS.l 1 ; requested size
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memoptions DS.l 1 ; requested options
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memhndl DS.l 1 ; handle to memory mgr block
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memhndla DS.l 1 ; handle to 4 or 8k aligned memory
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memhndlasz DS.l 1 ; ptr to 4 or 8k aligned memory size
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GetMemSz EQU *
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ENDR
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Locked EQU 0 ; want locked memory
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Contig EQU 1 ; want contiguous memory
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CacheOff EQU 2 ; want non-cacheable memory
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;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ For FreeMemory call
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FreeMem RECORD 0
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memoptions DS.l 1 ; requested options
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memptr DS.l 1 ; ptr to memory mgr block
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memptra DS.l 1 ; ptr to 4 or 8k aligned memory
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memptrasz DS.l 1 ; 4 or 8k aligned memory size
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FreeMemSz EQU *
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ENDR
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;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ Initialization Parameters
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MACEInitParms RECORD 0
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RecvRtn DS.l 1 ; address of Ethernet receive routine
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RecvPrms DS.l 1 ; parms to pass @ receive
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XmitRtn DS.l 1 ; address of Ethernet xmit complete routine
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XmitPrms DS.l 1 ; parms to pass @ xmit complete
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MACECfgPtr DS.l 1 ; ptr to MACE config record
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Dot3NetStats DS.l 1 ; ptr to 802.3 statistics array
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LAPMIBNetStats DS.l 1 ; ptr to LAP MIB statistics array
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EnetAddr DS.l 1 ; ptr to ethernet address
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FastMoveRtn DS.l 1 ; ->proc to move memory FAST
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IPSize EQU *
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ENDR
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;¥¥¥¥ Parms passed to .ENET "RecvRtn"
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RcvParms RECORD {A6Link}
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Size EQU * ; no local vars
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A6Link DS.l 2 ; saved A6 and return addr
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Parm DS.l 1 ; parm passed to MaceInit
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Buff DS.l 1 ; ptr to Mace's buffer containing pkt
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Pkt DS.l 1 ; ptr to packet data
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Len DS.w 1 ; pkt length
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Stat DS.l 1 ; pkt status
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; Stat definition:
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; Byte 0: Receive Runt Packet Count (Bits 31-24)
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; -number of runts recv'd since last successfully recv'd pkt
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; -maxs at 255
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; Byte 1: Receive Collision Count (Bits 23-16)
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; -number of collisions since last successfully recv'd pkt
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; -maxs at 255
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; Byte 2-3: Receive Status (Bits 15-0)
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; Bits 15-7,3-0 : reserved, read as 0's
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; Bits 6-4 : Recv Message Status bits
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; RcvCLSN EQU 6 ; late collision during recv
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; RcvFRAM EQU 5 ; frame error, non-integer # of bytes
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; RcvFCS EQU 4 ; frame check sequence error
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ParmsSz EQU * - Parm ; len of passed parms
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ENDR
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Configrsrc EQU 'ecfg' ; rsrc type for MACE config data rsrc
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; Mace Configuration Record
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MACECfg RECORD 0 ; Config values from config rsrc
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MACECfgVers DS.w 1 ; record version
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MACEBase DS.l 1 ; Base address of MACE
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EnetPROM DS.l 1 ; base address of Address Prom
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XmitFrmCtl DS.b 1 ; MACE transmit frame control register value
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RecvFrmCtl DS.b 1 ; MACE receive frame control register value
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FIFOCfgCtl DS.b 1 ; MACE xmit/recv fifo config control register value
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MACCfgCtl DS.b 1 ; MACE MAC config control register value
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; The following are optional values; ignored if zero
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EnetAddr DS.b 6 ; Alternate Ethernet Address, overrides Address PROM
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XmitBuffs DS.w 1 ; Alternate number of transmit buffers
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RecvBuffs DS.w 1 ; Alternate number of receive buffers
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RecvChains DS.w 1 ; Alternate number of receive "chains"
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CfgSize EQU *
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ENDR
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