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619 lines
23 KiB
C
619 lines
23 KiB
C
/*
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File: InitItt.c
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Contains: routines that initializes Cousin Itt
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Entry points:
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Written by: Paul Wolf
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Copyright: © 1992-1994 by Apple Computer, Inc., all rights reserved.
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Change History (most recent first):
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<SM40> 2/2/94 DCB My last change broke the INIT...
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<SM39> 2/2/94 DCB Removed call INITSCSIBOOT and moved it into StartInit.a where it
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gets called after Slot Interrupts and ADB are initialized.
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<SM38> 2/1/94 chp Remove some redundant initializations of fields in the TNT HDA
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descriptor.
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<SM37> 2/1/94 DCB Set the using601Emulator field in the hardware description field
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if we are running on a 601.
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<SM36> 1/29/94 DCB Added code to initialize SIMg->otherSIMg which is used on dual
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bus machines with one interrupt source.
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<ML3> 1/5/94 pdw Converted SCSIGlobals usage to new format.
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<SM34> 12/19/93 DCB Only check for non-universal if we are being built as an INIT.
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<SM33> 12/19/93 DCB Un-Patch the Deferred Task Manager if patchIIciROM.a has
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installed the evil QuickMail patch which can cause the stack to
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grow in an unbounded fashion. Also don't install on
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non-universal ROMs (Duh).
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<SM32> 11/22/93 pdw Rolling in from <MCxx>.
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<SM31> 11/21/93 pdw Removed reinitialization of interrupt function fields for second
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bus.
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<SM30> 11/19/93 chp Support new IRQ primitive vector initialization. Move TNT
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external SCSI to SCSI96_2 and support internal SCSI as SCSI96_1,
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which is a 53CF96.
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<SMG4> 9/29/93 chp Fill in more vital statistics for TNT.
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<SMG3> 9/22/93 chp Add support and vital information for TNT SCSI initialization.
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<SM28> 10/29/93 DCB <MC> roll-in.
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<MC6> 10/28/93 pdw Cleaned up forPDMProto stuff a little bit more.
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<SM27> 10/14/93 pdw <MC> roll-in.
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<MC5> 10/12/93 pdw Added support for Synchronous data transfers, rewrote State
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Machine, message handling etc.
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<MC4> 9/26/93 pdw Got rid of ReplaceGestalt call.
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<MC3> 9/16/93 pdw Added setting of HBAisFast for ColdFusion's FC96 bus and
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clearing of it (for default) for all second buses. Fixes the
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initialization of Curio as an FC96 bug (which made boot SLOW).
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<MC2> 9/13/93 pdw Roll-in from SuperMario.
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<SM26> 9/13/93 pdw Changed the risky slash pattern.
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<SM25> 9/12/93 pdw Added support for reregistration of buses for plugging in new
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replacement SIMs (i.e. from an Init on an IttFull ROM).
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<SM24> 8/23/93 DCB Went back to checking for djMEMC since the TestFor works now.
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<SM23> 8/20/93 DCB Fixing initialization problems for Wombats and possibly other
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(?) 040/c96 machines. Need to unblock interrupts before
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returning if we don't install. Also default to Wombat for now if
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we don't know what we are - I'll fix this soon I promise.
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<SM22> 8/13/93 pdw Got rid of all that fake-gestalt stuff. Went to local cpu var
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based on decoder types.
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<SM21> 7/28/93 pdw Fixing Quadra ISR vector problem: Adding init of intIRQbitNum to
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3 into default values init area.
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<SM20> 7/20/93 pdw Fixed up some Cold Fusion problems with IRQ bit numbers and some
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Quadra 9x0 problems with not initing the second DAFB.
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<SM19> 7/2/93 IH Reality Update: Change Gestalt call to use
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SelectorFunctionProcPtr.
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<SM18> 6/29/93 pdw Massive checkins: Change asynchronicity mechanism to CallMachine
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stack switching mechanism. Adding support for Cold Fusion.
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Rearranging HW/SW Init code. Some code optimizations.
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<SM17> 5/30/93 PW Fixed "doesn't run without Gibbly" bug by only dereferencing
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HALg0 and HALg1 when they are both valid.
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<SM16> 5/29/93 PW Nothing really.
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<SM15> 5/25/93 DCB Rollin from Ludwig. (The next item below)
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<LW8> 5/21/93 PW Adding PRAM selectable Initiator ID stuff.
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<SM14> 5/5/93 PW Making changes to get this to work in ROM on PDM EVT2.
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<SM13> 5/5/93 PW Converted names to meanies-friendly names. Updated with latest
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from Ludwig stuff.
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<SM12> 4/8/93 DCB Added Initialization code for Wombat class machines.
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<SM11> 3/29/93 PW Changed PDM's characteristic to hasDMA=true.
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<LW7> 4/30/93 DCB Blocking interrupts around installation to prevent VBLs etc from
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stepping on us.
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<LW5> 4/14/93 DCB Added AppleSim function to prevent installation of SIMs if they
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are already there.
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<LW4> 3/26/93 PW Changed the names of some of the hw desc fields
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(dreqNeedsSwapMMU, dmaType etc). Slight rearrangement into
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default, special case.
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<LW3> 2/17/93 PW Began adding dual-interrupt support for Quadras.
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<SM10> 3/22/93 PW Removing DMA support for PDM because DMA reads kills DMA writes
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on all other channels.
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<SM9> 3/20/93 PW Rolled back the fixed changes for <SM7>. Mostly for dual-bus
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support for Quadras and lots of little PDM things.
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<SM8> 3/17/93 DCB Rolled out Changes for <SM7> which broke the build.
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<SM7> 3/16/93 PW Began adding dual-interrupt support for Quadras. Rearranged for
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easier universalization.
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<SM6> 1/31/93 PW Update from the latest of Ludwig. Also changes required for PDM
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(will update Ludwig with these as needed myself).
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<LW2> 1/27/93 PW Starting to rewrite for Universalizing this blasted file.
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<SM5> 11/20/92 DCB Added Gestalt scsiSelector
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<SM4> 8/24/92 PN Take out CycloneboxEVT1 stuff
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<SM3> 7/28/92 PW Got rid of unused variable warning.
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<SM2> 7/28/92 PW Removed blocking of interrupts because of a VM habit of
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rejecting LockMemory if ints are nonzero. NOT the final
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solution.
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<SM1> 7/24/92 PW New Today.
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*/
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#include <SysEqu.h>
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#include <Memory.h>
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#include <SCSIStandard.h>
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#include <GestaltEqu.h>
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#include <GestaltPrivateEqu.h>
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#include <Start.h>
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#include <SCSI.h>
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#include <Slots.h>
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#include <GrandCentralPriv.h>
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#ifndef SCSI2Base
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#define SCSI2Base 0x1FF0 /*[GLOBAL VAR] (long) base address for 2nd SCSI chip read*/
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#endif
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#include "SCSIDebug.h"
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#include "ACAM.h"
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#include "XPT.h"
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#include "SIMCore.h"
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#include "BootItt.h"
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#include "HALc96.h"
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#include "SCSIGlue.h"
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#include "XPTPriv.h" //!!! We need to move the SCSIGlobals struct to XPT.h!
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#include "SIMCorePriv.h"
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pascal OSErr IttGestalt( OSType scsiSelector,long * response ); // <SM5>
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Boolean AppleSIMS( void );
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extern short BlockInterrupts(void);
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extern void UnblockInterrupts( short oldSR);
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/*********************************************************************************
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InitItt - initialize Cousin Itt
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See, the way it works is this.
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¥ InitItt initializes the XPT by calling InitXpt
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¥ InitItt initializes the HAL HW by calling Init53c9xHW
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¥ InitItt initializes the HAL SW by calling Init53c9xSW
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¥ The HAL actually has to register itself with SIMCore
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it calls SIMRegisterHAL
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¥ SIMCore must register the new HBA with the XPT
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it calls SCSIRegisterBus
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¥ The XPT allocates all of the statics for both HAL and SIMCore
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The XPT returns to the SIM
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¥ The SIM sets up its statics and returns to the HAL
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¥ The HAL sets up its statics and it's done and returns to InitItt
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¥ InitItt does the same for each HBA it knows about (i.e. motherboard buses)
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¥ InitItt calls NewGestalt to announce our arrival
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*********************************************************************************/
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long
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InitItt()
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{
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long err;
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HBADesc_53c9x * hwDescPtr;
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//SelectorFunctionProcPtr oldGestalt;
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HALc96Globals * halg0;
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HALc96Globals * halg1;
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SIMglobals * simg0;
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SIMglobals * simg1;
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XPTglobals * xptg;
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ushort oldSR;
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Boolean reregister;
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enum {kPDM, kCyclone, kRealQuadra, kWombat, kTNT} cpu;
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long gstlt;
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#if forPDMProto
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Boolean onPDM_EVT1;
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#endif
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#if forIttInit
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// Don't install on non-universal machines
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// Should I check for Gestalt being implemented?
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if( Gestalt('hdwr', &gstlt) )
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return(-1);
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if( (gstlt & (1 << gestaltHasUniversalROM)) == 0 )
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return(-1);
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#endif
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if ( ! TestFor_SCSI96_1Exists()) // At least one 53c96?
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return (-1); // no- exit w/err
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oldSR = BlockInterrupts(); //-> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> ->
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if ( TestFor_HMCDecoder() ) {
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cpu = kPDM;
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#if forPDMProto
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if (*(char *)0xcb3 == 0x44)
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onPDM_EVT1 = true;
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else
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onPDM_EVT1 = false;
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#endif
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}
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else if ( TestFor_PSCExists()) {
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cpu = kCyclone;
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}
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else if ( TestFor_OrwellExists()) {
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cpu = kRealQuadra;
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}
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else if ( TestFor_djMEMCExists()) {
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cpu = kWombat;
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}
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else if ( TestFor_GrandCentralExists()) {
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cpu = kTNT;
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}
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else {
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UnblockInterrupts( oldSR); //<- <- <- <- <- <-
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return (-1);
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}
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if (err = InitXPT()) { // always need to init the XPT first
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IfDebugStr("\pInitXPT failed");
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UnblockInterrupts( oldSR); //<- <- <- <- <- <-
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return (-1);
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}
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#if forIttInit
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// First we need to fix a bug in the deferred task manager. The System 7
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// link patch "fixes" a QuickMail server bug by adding code to reduce interrupts
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// everytime we attempt do dispatch tasks - even if if the DTQueue is busy and
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// we aren't going to do anything this go-round. If an interrupt is pending at
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// this point it is happens even though we haven't RTE'd from the interrupt we
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// were just completing. If this happens back to back to ... then we fill up the
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// stack with interrupt stack frames until we collide with the heap.
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// SuperMario ROMs do not do this so I assume CE fixed their bug long ago. Since
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// the "fix" for them makes it impossible for me to use the Deferred Task Manager
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// I am stuffing the original ROM vector back in so it won't lower interupts prior
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// to doing the RTE.
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#define jDisptch 0x6e4 // Low mem vector for deferred task manager
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{
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ushort *instr;
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instr = *(ushort **)jDisptch;
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// Check to see if the patch is installed
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if( instr[0] == 0x4eb9 && // jsr 4080a1ee (_DTInstall + 1e)
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instr[1] == 0x4080 &&
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instr[2] == 0xa1ee &&
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instr[3] == 0x027c && // andi.w #f8ff, sr
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instr[4] == 0xf8ff &&
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instr[5] == 0x4e75 ) // rts
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{
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// Stuff the old vector back in. This address is correct for
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// all IIci based ROMs. Note that if this isn't a IIci based
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// ROM then the above patch wouldn't call 0x4080a1ee.
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*(ulong *)jDisptch = 0x4080a1ee;
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}
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// else leave it alone
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}
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#endif
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reregister = AppleSIMS(); // if our SIMs are already there, do a REregister instead
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hwDescPtr = (HBADesc_53c9x *) NewPtrSysClear( sizeof(HBADesc_53c9x)); //&&&& NewPtrSysClear
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if (hwDescPtr==0) {
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IfDebugStr("\pCanÕt allocate hwDesc");
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UnblockInterrupts( oldSR); //<- <- <- <- <- <-
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return (-1);
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}
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//ÉÉÉÉÉÉ Prep for Initializing First Bus ÉÉÉÉÉÉ
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//--- Default Values (except addresses)
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hwDescPtr-> baseRegAddr = *(Ptr *)SCSIBase; // base addr of c9x registers (offset of $10 between regs
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hwDescPtr-> pdmaAddr = hwDescPtr->baseRegAddr+0x100; // addr of Pseudo-dma access
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hwDescPtr-> pdmaNonSerlzdAddr = hwDescPtr->pdmaAddr; // default to no non-serialized space
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hwDescPtr-> jvClearSCSIIRQ = ClearVIASCSIIRQ;
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hwDescPtr-> jvEnableSCSIIRQ = EnableVIASCSIIRQ;
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hwDescPtr-> jvDisableSCSIIRQ = DisableVIASCSIIRQ;
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hwDescPtr-> jvTestSCSIIE = TestVIASCSIIE;
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hwDescPtr-> HBAisFast = false; // set if c9x part capable of Fast Synchronous (10MB/S)
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hwDescPtr-> HBAisDiff = false; // set if c9x part capable of differential
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hwDescPtr-> intOSNumberSCSI = 0; // OS registration number for the SCSI interrupt
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hwDescPtr-> intSensSCSI = LEVEL; // EDGE vs LEVEL vs STICKYBIT sensitive int
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hwDescPtr-> intOSNumberDMA = 0; // OS registration number for the DMA interrupt
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hwDescPtr-> intTypeDMA = SHARED_VIA; // type of interrupt control (shared VIA bit, etc.)
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hwDescPtr-> intSensDMA = LEVEL; // EDGE vs LEVEL vs STICKYBIT sensitive int
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hwDescPtr-> intDREQbitNum = 0; //
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hwDescPtr-> intIRQbitNum = 3; // IRQ = bit 3
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hwDescPtr-> enableIRQvalue = (1<<3)+0x80;
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hwDescPtr-> disableIRQvalue = (1<<3);
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hwDescPtr-> testIRQenableValue = (1<<3);
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hwDescPtr-> clearIRQvalue = (1<<3)+0x80;
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hwDescPtr-> dreqNeedsSwapMMU = false; // set if dreq status bit is in DAFB register
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hwDescPtr-> HBAhasDMA = false; // set if true DMA available
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hwDescPtr-> HBAhasPseudoDMA = true; // set if Pseudo-DMA available
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hwDescPtr-> HBAhasHskPseudoDMA = true; // set if handshaked pseudo-DMA available
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hwDescPtr-> intTypeSCSI = INDEPENDENT_VIA; // type of interrupt control (shared VIA bit, etc.)
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hwDescPtr-> dmaType = dmaTypeNone; // type of DMA controller
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hwDescPtr-> usesThreshold8 = false; // doesn't use threshold 8 mode
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if( Gestalt('cput',&gstlt) == noErr && gstlt == gestaltCPU601 )
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hwDescPtr-> using601Emulator = true; // running emulated
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else
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hwDescPtr-> using601Emulator = false; // running native 68K
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//--- Fields specific to different CPUs
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switch (cpu) {
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case kPDM:
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hwDescPtr-> dreqAddr = (Ptr)0x50F26003;
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hwDescPtr-> intEnableSCSIAddr = (Ptr)0x50f26013;
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hwDescPtr-> intFlagSCSIAddr = (Ptr)0x50f26003;
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hwDescPtr-> HBAhasDMA = true;
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hwDescPtr-> HBAhasPseudoDMA = true;
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hwDescPtr-> HBAhasHskPseudoDMA = true;
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hwDescPtr-> intTypeSCSI = INDEPENDENT_VIA;
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hwDescPtr-> dmaType = dmaTypeAMIC;
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hwDescPtr-> dmaAlignmentSize = 8;
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hwDescPtr-> usesThreshold8 = true;
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#if forPDMProto
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if (onPDM_EVT1) {
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hwDescPtr-> HBAhasPseudoDMA = true; // pseudo-DMA is supported on old AMIC
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hwDescPtr-> HBAhasHskPseudoDMA = false; // but, handshaked pseudo-DMA isn't
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hwDescPtr-> HBAhasDMA = true; // true DMA available kinda
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}
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#endif
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if ( TestFor_SCSI96_2Exists()) { // if 2 buses, this is the FC96 NOT the Curio
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hwDescPtr-> dmaCntrlAddr = (Ptr)0x50F32009;
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hwDescPtr-> dmaBaseAddr = (Ptr)0x50F32004;
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hwDescPtr-> HBAisFast = true;
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hwDescPtr-> intIRQbitNum = 6; // IRQ = bit 6
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hwDescPtr-> enableIRQvalue = (1<<6)+0x80;
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hwDescPtr-> disableIRQvalue = (1<<6);
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hwDescPtr-> testIRQenableValue = (1<<6);
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hwDescPtr-> clearIRQvalue = (1<<6)+0x80;
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hwDescPtr-> intDREQbitNum = 2; // DRQ = bit 2
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}
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else { // if just 1 bus, this is the Curio - MAKE SURE 2nd VERSION CHANGES !
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hwDescPtr-> dmaCntrlAddr = (Ptr)0x50F32008;
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hwDescPtr-> dmaBaseAddr = (Ptr)0x50F32000;
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hwDescPtr-> intIRQbitNum = 3; // IRQ = bit 3
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hwDescPtr-> enableIRQvalue = (1<<3)+0x80;
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hwDescPtr-> disableIRQvalue = (1<<3);
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hwDescPtr-> testIRQenableValue = (1<<3);
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hwDescPtr-> clearIRQvalue = (1<<3)+0x80;
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hwDescPtr-> intDREQbitNum = 0; // DRQ = bit 0
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}
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break;
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case kRealQuadra:
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// Pseudo-dma non-serialized access (non-decoded in HW, different page table entry)
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hwDescPtr-> pdmaNonSerlzdAddr = hwDescPtr->pdmaAddr+0x40000;
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hwDescPtr-> dafbAddr = (Ptr)0xF9800024; // addr of dafb register to init
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hwDescPtr-> dreqAddr = hwDescPtr->dafbAddr + 2; // addr of dafb register with DREQ bit
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hwDescPtr-> intEnableSCSIAddr = (Ptr)0x50f03c13;
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hwDescPtr-> intFlagSCSIAddr = (Ptr)0x50f03a03;
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hwDescPtr-> intSensSCSI = EDGE;
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hwDescPtr-> dreqNeedsSwapMMU = true;
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hwDescPtr-> intDREQbitNum = 1;
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hwDescPtr-> needsDAFBinit = true; // Quadras need their DAFB inited
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hwDescPtr-> HBAhasDMA = false;
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hwDescPtr-> HBAhasPseudoDMA = true;
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hwDescPtr-> HBAhasHskPseudoDMA = true;
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if ( TestFor_SCSI96_2Exists())
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hwDescPtr-> intTypeSCSI = SHARED_VIA; // if 2 buses, this is a shared via bit for int
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else
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hwDescPtr-> intTypeSCSI = INDEPENDENT_VIA; // if 1 bus, this is an independent bit in via
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break;
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case kWombat:
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hwDescPtr-> dreqAddr = (Ptr)0x50f03a00;
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hwDescPtr-> intEnableSCSIAddr = (Ptr)0x50f03c13;
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hwDescPtr-> intFlagSCSIAddr = (Ptr)0x50f03a03;
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hwDescPtr-> intSensSCSI = EDGE;
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hwDescPtr-> dmaType = pdmaTypeBIOS;
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break;
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case kCyclone:
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hwDescPtr-> pdmaAddr = (Ptr)0;
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hwDescPtr-> pdmaNonSerlzdAddr = (Ptr)0;
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hwDescPtr-> dreqAddr = (Ptr)0x50f03a00;
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hwDescPtr-> intEnableSCSIAddr = (Ptr)0x50f03c00;
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hwDescPtr-> intFlagSCSIAddr = (Ptr)0x50f03a00;
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hwDescPtr-> HBAhasDMA = true;
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hwDescPtr-> HBAhasPseudoDMA = false;
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hwDescPtr-> HBAhasHskPseudoDMA = false;
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hwDescPtr-> intTypeSCSI = INDEPENDENT_VIA;
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hwDescPtr-> dmaType = dmaTypePSC;
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hwDescPtr-> dmaAlignmentSize = 16;
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break;
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case kTNT:
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// SCSI96_1 is by convention the internal bus (53CF96)
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// This bus is known in the Grand Central literature as SCSI1.
|
|
hwDescPtr-> pdmaAddr = (Ptr)0x5FFF8001; // ainÕt no such thing
|
|
hwDescPtr-> pdmaNonSerlzdAddr = (Ptr)0x5FFF8001; // ainÕt no such thing
|
|
hwDescPtr-> dreqAddr = (Ptr)0xF301A000; // in Generic Board Register (Proto2)
|
|
hwDescPtr-> intEnableSCSIAddr = (Ptr)0xF3000024; // 32-bit access only!
|
|
hwDescPtr-> intFlagSCSIAddr = (Ptr)0xF300002C; // 32-bit access only!
|
|
hwDescPtr-> dmaCntrlAddr = (Ptr)0xF3008A00; // 32-bit access only!
|
|
hwDescPtr-> jvClearSCSIIRQ = ClearGCSCSI1IRQ;
|
|
hwDescPtr-> jvEnableSCSIIRQ = EnableGCSCSI1IRQ;
|
|
hwDescPtr-> jvDisableSCSIIRQ = DisableGCSCSI1IRQ;
|
|
hwDescPtr-> jvTestSCSIIE = TestGCSCSI1IE;
|
|
hwDescPtr-> HBAisFast = true;
|
|
hwDescPtr-> HBAhasDMA = true; // got the old DB-DMA thing
|
|
hwDescPtr-> HBAhasPseudoDMA = false;
|
|
hwDescPtr-> HBAhasHskPseudoDMA = false;
|
|
hwDescPtr-> intIRQbitNum = gcifDevSCSI1;
|
|
hwDescPtr-> intDREQbitNum = 7;
|
|
hwDescPtr-> intOSNumberSCSI = gcifDevSCSI1;
|
|
hwDescPtr-> intTypeSCSI = GRAND_CENTRAL;
|
|
hwDescPtr-> intOSNumberDMA = gcifDmaSCSI1;
|
|
hwDescPtr-> intTypeDMA = GRAND_CENTRAL;
|
|
hwDescPtr-> dmaType = dmaTypeGC; // type of DMA controller
|
|
hwDescPtr-> dmaAlignmentSize = 1; // no alignment restrictions
|
|
|
|
break;
|
|
}
|
|
|
|
|
|
//ÉÉÉÉÉÉ Do Initialization of first bus ÉÉÉÉÉÉ
|
|
|
|
ReadInitiatorID(hwDescPtr); // read Initiator ID into hwDesc
|
|
if (err = Init53c9xHW(hwDescPtr)) { // will want to see if TERROR already did this init
|
|
IfDebugStr("\pInit53c9xHW 1 failed");
|
|
UnblockInterrupts( oldSR); //<- <- <- <- <- <-
|
|
return (-1);
|
|
}
|
|
|
|
if (reregister)
|
|
halg0 = (HALc96Globals *)ReInitHAL(hwDescPtr, 0); // re-init the HAL at bus #0
|
|
else
|
|
halg0 = (HALc96Globals *)Init53c9xSW(hwDescPtr); // init the HAL
|
|
|
|
if (halg0 == 0) {
|
|
IfDebugStr("\pInit53c9xSW 1 failed");
|
|
UnblockInterrupts( oldSR); //<- <- <- <- <- <-
|
|
return (-1);
|
|
}
|
|
|
|
SCSIGlobals->numBEHs = 0;
|
|
SCSIGlobals->berr_halg0 = (Ptr)halg0;
|
|
|
|
|
|
|
|
//ÉÉÉÉÉÉ Prep for Initializing external HBA for Dual-Bus Machines ÉÉÉÉÉÉ
|
|
|
|
if ( TestFor_SCSI96_2Exists())
|
|
{
|
|
hwDescPtr-> baseRegAddr = *(Ptr *)SCSI2Base; // base addr of c9x registers (offset of $10 between regs
|
|
hwDescPtr-> pdmaAddr = hwDescPtr->baseRegAddr+0x100; // addr of Pseudo-dma access
|
|
hwDescPtr-> pdmaNonSerlzdAddr = hwDescPtr->pdmaAddr; // default to no-nonserialized access
|
|
hwDescPtr-> HBAisFast = false;
|
|
|
|
switch (cpu) {
|
|
case kPDM: // if 2 buses, this is the Curio NOT the FC96
|
|
hwDescPtr-> dmaCntrlAddr = (Ptr)0x50F32008;
|
|
hwDescPtr-> dmaBaseAddr = (Ptr)0x50F32000;
|
|
hwDescPtr-> intIRQbitNum = 3; // IRQ = bit 3
|
|
hwDescPtr-> enableIRQvalue = (1<<3)+0x80;
|
|
hwDescPtr-> disableIRQvalue = (1<<3);
|
|
hwDescPtr-> testIRQenableValue = (1<<3);
|
|
hwDescPtr-> clearIRQvalue = (1<<3)+0x80;
|
|
hwDescPtr-> intDREQbitNum = 0; // DRQ = bit 0
|
|
|
|
break;
|
|
|
|
case kRealQuadra: // Quadra 9x0
|
|
hwDescPtr-> pdmaNonSerlzdAddr = hwDescPtr->pdmaAddr+0x40000;
|
|
hwDescPtr-> dafbAddr = (Ptr)0xF9800028; // addr of dafb register to init
|
|
hwDescPtr-> dreqAddr = hwDescPtr->dafbAddr + 2; // addr of dafb register with DREQ bit
|
|
hwDescPtr-> intTypeSCSI = SHARED_VIA;
|
|
|
|
break;
|
|
|
|
case kTNT:
|
|
// SCSI96_2 is by convention the external bus (CURIO 53C94 cell)
|
|
// This bus is known in the Grand Central literature as SCSI0.
|
|
hwDescPtr-> pdmaAddr = (Ptr)0x5FFF8001; // ainÕt no such thing
|
|
hwDescPtr-> pdmaNonSerlzdAddr = (Ptr)0x5FFF8001; // ainÕt no such thing
|
|
hwDescPtr-> dreqAddr = (Ptr)0xF301A000; // in Generic Board Register (Proto2)
|
|
hwDescPtr-> intEnableSCSIAddr = (Ptr)0xF3000024; // 32-bit access only!
|
|
hwDescPtr-> intFlagSCSIAddr = (Ptr)0xF300002C; // 32-bit access only!
|
|
hwDescPtr-> dmaCntrlAddr = (Ptr)0xF3008000; // 32-bit access only!
|
|
hwDescPtr-> jvClearSCSIIRQ = ClearGCSCSI0IRQ;
|
|
hwDescPtr-> jvEnableSCSIIRQ = EnableGCSCSI0IRQ;
|
|
hwDescPtr-> jvDisableSCSIIRQ = DisableGCSCSI0IRQ;
|
|
hwDescPtr-> jvTestSCSIIE = TestGCSCSI1IE;
|
|
hwDescPtr-> HBAhasDMA = true; // got the old DB-DMA thing
|
|
hwDescPtr-> HBAhasPseudoDMA = false;
|
|
hwDescPtr-> HBAhasHskPseudoDMA = false;
|
|
hwDescPtr-> intIRQbitNum = gcifDevSCSI0;
|
|
hwDescPtr-> intDREQbitNum = 6;
|
|
hwDescPtr-> intOSNumberSCSI = gcifDevSCSI0;
|
|
hwDescPtr-> intTypeSCSI = GRAND_CENTRAL;
|
|
hwDescPtr-> intOSNumberDMA = gcifDmaSCSI0;
|
|
hwDescPtr-> intTypeDMA = GRAND_CENTRAL;
|
|
hwDescPtr-> dmaType = dmaTypeGC; // type of DMA controller
|
|
hwDescPtr-> dmaAlignmentSize = 1; // no alignment restrictions
|
|
|
|
break;
|
|
}
|
|
|
|
|
|
//ÉÉÉÉÉÉ Do Initialization of second bus ÉÉÉÉÉÉ
|
|
|
|
ReadInitiatorID(hwDescPtr); // read Initiator ID into hwDesc
|
|
if (err = Init53c9xHW(hwDescPtr)) { // will want to see if TERROR already did this init
|
|
IfDebugStr("\pInit53c9xHW 2 failed");
|
|
UnblockInterrupts( oldSR); //<- <- <- <- <- <-
|
|
return (-1);
|
|
}
|
|
|
|
if (reregister)
|
|
halg1 = (HALc96Globals *)ReInitHAL(hwDescPtr, 1); // re-init the HAL at bus #1
|
|
else
|
|
halg1 = (HALc96Globals *)Init53c9xSW(hwDescPtr); // init the HAL
|
|
|
|
if (halg1 == 0) {
|
|
IfDebugStr("\pInit53c9xSW 2 failed");
|
|
UnblockInterrupts( oldSR); //<- <- <- <- <- <-
|
|
return (-1);
|
|
}
|
|
|
|
SCSIGlobals->berr_halg1 = (Ptr) halg1;
|
|
|
|
halg0->otherHALg = (void *)halg1;
|
|
halg1->otherHALg = (void *)halg0;
|
|
|
|
xptg = GetXPTg(); // From the SCSIGlobals
|
|
|
|
|
|
// Just like the HAL the SIM needs to know about the other bus
|
|
simg0 = (SIMglobals *)(((xptg->BusInfoPtr[0])->initInfo).SIMstaticPtr);
|
|
simg1 = (SIMglobals *)(((xptg->BusInfoPtr[1])->initInfo).SIMstaticPtr);
|
|
|
|
simg0->otherSIMg = (Ptr)simg1;
|
|
simg1->otherSIMg = (Ptr)simg0;
|
|
|
|
|
|
}
|
|
|
|
UnblockInterrupts( oldSR); //<- <- <- <- <- <- <- <- <- <- <- <- <- <- <- <- <- <- <- <-
|
|
|
|
if( NewGestalt(gestaltSCSI,IttGestalt) ) {
|
|
// if there is already one there, we need to get the old values and change only
|
|
// those feature bits that change because of this new (apparently) RAM resident Itt code
|
|
// then we need to replaceGestalt it. ** But for now, nothing changes **
|
|
//ReplaceGestalt(gestaltSCSI,IttGestalt,&oldGestalt );
|
|
}
|
|
#if forIttInit
|
|
INITSCSIBOOT();
|
|
#endif
|
|
|
|
return (0);
|
|
}
|
|
|
|
|
|
|
|
/*********************************************************************************
|
|
IttGestalt -
|
|
*********************************************************************************/
|
|
|
|
pascal OSErr
|
|
IttGestalt(
|
|
OSType scsiSelector,
|
|
long * response )
|
|
{
|
|
#pragma unused(scsiSelector);
|
|
|
|
*(ulong *)response = 1<<gestaltAsyncSCSI;
|
|
|
|
#if ForROM
|
|
#if !forIttInit
|
|
*(ulong *)response |= (1<<gestaltAsyncSCSIINROM) + (1<<gestaltSCSISlotBoot);
|
|
#endif
|
|
#endif
|
|
return(0);
|
|
}
|
|
|
|
|
|
/*********************************************************************************
|
|
AppleSIMS -
|
|
*********************************************************************************/
|
|
|
|
Boolean
|
|
AppleSIMS( void )
|
|
{
|
|
SCSIBusInquiryPB scPB;
|
|
|
|
Clear((char *)&scPB,sizeof(scPB));
|
|
scPB.scsiFunctionCode = SCSIBusInquiry;
|
|
scPB.scsiPBLength = sizeof(SCSIBusInquiryPB);
|
|
scPB.scsiCompletion = nil;
|
|
if (SCSIAction( (SCSI_PB *) &scPB )) // Get info for the internal (first) bus
|
|
return(false);
|
|
|
|
if( *(long *)&scPB.scsiSIMVendor == 'Appl' &&
|
|
*(long *)&scPB.scsiSIMVendor[4] == 'e Co' &&
|
|
*(long *)&scPB.scsiSIMVendor[8] == 'mput' )
|
|
return(true);
|
|
else
|
|
return(false);
|
|
}
|
|
|