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updates to match current fellow cpu code

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This commit is contained in:
Kelvin Sherlock 2014-12-04 16:09:18 -05:00
parent ff52cae4e9
commit abe8b9236b
14 changed files with 483 additions and 528 deletions
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105
cpu/CpuIntegration.c
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@ -1,4 +1,4 @@
/* @(#) $Id: CpuIntegration.c,v 1.10 2013/01/08 19:17:33 peschau Exp $ */ /* @(#) $Id: CpuIntegration.c,v 1.10 2013-01-08 19:17:33 peschau Exp $ */
/*=========================================================================*/ /*=========================================================================*/
/* Fellow */ /* Fellow */
/* Initialization of 68000 core */ /* Initialization of 68000 core */
@ -29,15 +29,12 @@
#include "CpuModule.h" #include "CpuModule.h"
#include "CpuIntegration.h" #include "CpuIntegration.h"
#include "CpuModule_Internal.h" #include "CpuModule_Internal.h"
//#include "bus.h" #include "bus.h"
//#include "fileops.h" #include "fileops.h"
#include "interrupt.h"
jmp_buf cpu_integration_exception_buffer; jmp_buf cpu_integration_exception_buffer;
ULO cpu_integration_chip_interrupt_number;
/* custom chip intreq bit-number to irq-level */
static ULO cpu_integration_int_to_level[16] = {1,1,1,2, 3,3,3,4, 4,4,4,5, 5,6,6,7};
static ULO cpu_integration_irq_source;
/* Cycles spent by chips (Blitter) as a result of an instruction */ /* Cycles spent by chips (Blitter) as a result of an instruction */
static ULO cpu_integration_chip_cycles; static ULO cpu_integration_chip_cycles;
@ -75,7 +72,7 @@ static ULO cpuIntegrationGetSpeedMultiplier(void)
return cpu_integration_speed_multiplier; return cpu_integration_speed_multiplier;
} }
static void cpuIntegrationCalculateMultiplier(void) void cpuIntegrationCalculateMultiplier(void)
{ {
ULO multiplier = 12; ULO multiplier = 12;
@ -144,65 +141,25 @@ ULO cpuIntegrationGetChipSlowdown(void)
return cpu_integration_chip_slowdown; return cpu_integration_chip_slowdown;
} }
ULO cpuIntegrationGetChipIrqToIntLevel(ULO chip_irq) void cpuIntegrationSetChipInterruptNumber(ULO chip_interrupt_number)
{ {
return cpu_integration_int_to_level[chip_irq]; cpu_integration_chip_interrupt_number = chip_interrupt_number;
} }
void cpuIntegrationSetIrqSource(ULO irq_source) ULO cpuIntegrationGetChipInterruptNumber(void)
{ {
cpu_integration_irq_source = irq_source; return cpu_integration_chip_interrupt_number;
} }
ULO cpuIntegrationGetIrqSource(void) // A wrapper for cpuSetIrqLevel that restarts the
// scheduling of cpu events if the cpu was stoppped
void cpuIntegrationSetIrqLevel(ULO new_interrupt_level, ULO chip_interrupt_number)
{ {
return cpu_integration_irq_source; if (cpuSetIrqLevel(new_interrupt_level))
}
/*=====================================================
Checking for waiting interrupts
=====================================================*/
static BOOLE cpuIntegrationCheckPendingInterruptsFunc(void)
{
ULO current_cpu_level = (cpuGetSR() >> 8) & 7;
BOOLE chip_irqs_enabled = !!(intena & 0x4000);
if (chip_irqs_enabled)
{ {
LON highest_chip_irq; cpuEvent.cycle = busGetCycle();
ULO chip_irqs = intreq & intena;
if (chip_irqs == 0) return FALSE;
for (highest_chip_irq = 13; highest_chip_irq >= 0; highest_chip_irq--)
{
if (chip_irqs & (1 << highest_chip_irq))
{
// Found a chip-irq that is both flagged and enabled.
ULO highest_chip_level = cpuIntegrationGetChipIrqToIntLevel(highest_chip_irq);
if (highest_chip_level > current_cpu_level)
{
cpuSetIrqLevel(highest_chip_level);
cpuSetIrqAddress(memoryReadLong(cpuGetVbr() + 0x60 + highest_chip_level*4));
cpuIntegrationSetIrqSource(highest_chip_irq);
if (cpuGetStop())
{
cpuSetStop(FALSE);
cpuEvent.cycle = bus.cycle;
}
return TRUE;
}
}
}
} }
return FALSE; cpuIntegrationSetChipInterruptNumber(chip_interrupt_number);
}
void cpuIntegrationCheckPendingInterrupts(void)
{
cpuCheckPendingInterrupts();
} }
/*=========================================*/ /*=========================================*/
@ -244,7 +201,7 @@ void cpuInstructionLogOpen(void)
void cpuIntegrationPrintBusCycle(void) void cpuIntegrationPrintBusCycle(void)
{ {
fprintf(CPUINSTRUCTIONLOG, "%d:%.5d ", bus.frame_no, bus.cycle); fprintf(CPUINSTRUCTIONLOG, "%I64u:%.5u ", bus.frame_no, bus.cycle);
} }
void cpuIntegrationInstructionLogging(void) void cpuIntegrationInstructionLogging(void)
@ -293,37 +250,13 @@ void cpuIntegrationExceptionLogging(STR *description, ULO original_pc, UWO opcod
fprintf(CPUINSTRUCTIONLOG, "%s for opcode %.4X at PC %.8X from PC %.8X\n", description, opcode, original_pc, cpuGetPC()); fprintf(CPUINSTRUCTIONLOG, "%s for opcode %.4X at PC %.8X from PC %.8X\n", description, opcode, original_pc, cpuGetPC());
} }
STR *cpuIntegrationGetInterruptName(ULO chip_irq_no)
{
switch (chip_irq_no)
{
case 0: return "TBE: Output buffer of the serial port is empty.";
case 1: return "DSKBLK: Disk DMA transfer ended.";
case 2: return "SOFT: Software interrupt.";
case 3: return "PORTS: From CIA-A or expansion port.";
case 4: return "COPER: Copper interrupt.";
case 5: return "VERTB: Start of vertical blank.";
case 6: return "BLIT: Blitter done.";
case 7: return "AUD0: Audio data on channel 0.";
case 8: return "AUD1: Audio data on channel 1.";
case 9: return "AUD2: Audio data on channel 2.";
case 10: return "AUD3: Audio data on channel 3.";
case 11: return "RBF: Input buffer of the serial port full.";
case 12: return "DSKSYN: Disk sync value recognized.";
case 13: return "EXTER: From CIA-B or expansion port.";
case 14: return "INTEN: BUG! Not an interrupt.";
case 15: return "NMI: BUG! Not an interrupt.";
}
return "Illegal interrupt source!";
}
void cpuIntegrationInterruptLogging(ULO level, ULO vector_address) void cpuIntegrationInterruptLogging(ULO level, ULO vector_address)
{ {
if (cpu_disable_instruction_log) return; if (cpu_disable_instruction_log) return;
cpuInstructionLogOpen(); cpuInstructionLogOpen();
cpuIntegrationPrintBusCycle(); cpuIntegrationPrintBusCycle();
fprintf(CPUINSTRUCTIONLOG, "Irq %d to %.6X (%s)\n", level, vector_address, cpuIntegrationGetInterruptName(cpuIntegrationGetIrqSource())); fprintf(CPUINSTRUCTIONLOG, "Irq %u to %.6X (%s)\n", level, vector_address, interruptGetInterruptName(cpuIntegrationGetChipInterruptNumber()));
} }
#endif #endif
@ -396,7 +329,7 @@ void cpuIntegrationSetDefaultConfig(void)
cpuIntegrationSetChipSlowdown(1); cpuIntegrationSetChipSlowdown(1);
cpuIntegrationSetSpeed(4); cpuIntegrationSetSpeed(4);
cpuSetCheckPendingInterruptsFunc(cpuIntegrationCheckPendingInterruptsFunc); cpuSetCheckPendingInterruptsFunc(interruptRaisePending);
cpuSetMidInstructionExceptionFunc(cpuIntegrationMidInstructionExceptionFunc); cpuSetMidInstructionExceptionFunc(cpuIntegrationMidInstructionExceptionFunc);
cpuSetResetExceptionFunc(cpuIntegrationResetExceptionFunc); cpuSetResetExceptionFunc(cpuIntegrationResetExceptionFunc);

4
cpu/CpuModule.c
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@ -1,4 +1,4 @@
/* @(#) $Id: CpuModule.c,v 1.7 2012/08/12 16:51:02 peschau Exp $ */ /* @(#) $Id: CpuModule.c,v 1.7 2012-08-12 16:51:02 peschau Exp $ */
/*=========================================================================*/ /*=========================================================================*/
/* Fellow */ /* Fellow */
/* Initialization of 68000 core */ /* Initialization of 68000 core */
@ -48,7 +48,7 @@ void cpuClearEverything(void)
cpuSetSfc(0); cpuSetSfc(0);
cpuSetDfc(0); cpuSetDfc(0);
cpuSetIrqLevel(0); cpuSetIrqLevel(0);
cpuSetIrqAddress(0); cpuSetRaiseInterrupt(FALSE);
cpuSetStop(FALSE); cpuSetStop(FALSE);
cpuSetInstructionTime(0); cpuSetInstructionTime(0);
cpuSetOriginalPC(0); cpuSetOriginalPC(0);

4
cpu/CpuModule.h
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@ -18,7 +18,7 @@ extern void cpuSetFLineExceptionFunc(cpuLineExceptionFunc func);
typedef BOOLE (*cpuCheckPendingInterruptsFunc)(void); typedef BOOLE (*cpuCheckPendingInterruptsFunc)(void);
extern void cpuSetCheckPendingInterruptsFunc(cpuCheckPendingInterruptsFunc func); extern void cpuSetCheckPendingInterruptsFunc(cpuCheckPendingInterruptsFunc func);
extern void cpuCheckPendingInterrupts(void); extern void cpuCheckPendingInterrupts(void);
extern void cpuSetUpInterrupt(void); void cpuSetUpInterrupt(ULO new_interrupt_level);
extern void cpuInitializeFromNewPC(ULO new_pc); extern void cpuInitializeFromNewPC(ULO new_pc);
@ -77,7 +77,7 @@ extern ULO cpuGetInitialSP(void);
extern ULO cpuGetInstructionTime(void); extern ULO cpuGetInstructionTime(void);
extern void cpuSetIrqLevel(ULO irq_level); extern BOOLE cpuSetIrqLevel(ULO new_interrupt_level);
extern ULO cpuGetIrqLevel(void); extern ULO cpuGetIrqLevel(void);
extern void cpuSetIrqAddress(ULO irq_address); extern void cpuSetIrqAddress(ULO irq_address);

88
cpu/CpuModule_Disassembler.c
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@ -150,7 +150,7 @@ static ULO cpuDis05(ULO regno, ULO pcp, STR *sdata, STR *soperands)
ULO disp = memoryReadWord(pcp); ULO disp = memoryReadWord(pcp);
cpuDisWordAppend(disp, sdata); cpuDisWordAppend(disp, sdata);
sprintf(cpuDisEoS(soperands), "$%.4X(A%1d)", disp, regno); sprintf(cpuDisEoS(soperands), "$%.4X(A%1u)", disp, regno);
return pcp + 2; return pcp + 2;
} }
@ -168,22 +168,22 @@ static ULO cpuDis06Brief(ULO regno, ULO pcp, ULO ext, BOOLE is_pc_indirect, STR
{ {
if (!is_pc_indirect) if (!is_pc_indirect)
{ {
sprintf(cpuDisEoS(soperands), "$%.2X(A%1d,%c%1d.%c)", offset, regno, indexregtype, indexregno, indexsize); sprintf(cpuDisEoS(soperands), "$%.2X(A%1u,%c%1u.%c)", offset, regno, indexregtype, indexregno, indexsize);
} }
else else
{ {
sprintf(cpuDisEoS(soperands), "$%.2X(PC,%c%1d.%c)", offset, indexregtype, indexregno, indexsize); sprintf(cpuDisEoS(soperands), "$%.2X(PC,%c%1u.%c)", offset, indexregtype, indexregno, indexsize);
} }
} }
else else
{ {
if (!is_pc_indirect) if (!is_pc_indirect)
{ {
sprintf(cpuDisEoS(soperands), "$%.2X(A%1d,%c%1d.%c%s)", offset, regno, indexregtype, indexregno, indexsize, scale[scalefactor]); sprintf(cpuDisEoS(soperands), "$%.2X(A%1u,%c%1u.%c%s)", offset, regno, indexregtype, indexregno, indexsize, scale[scalefactor]);
} }
else else
{ {
sprintf(cpuDisEoS(soperands), "$%.2X(PC,%c%1d.%c%s)", offset, indexregtype, indexregno, indexsize, scale[scalefactor]); sprintf(cpuDisEoS(soperands), "$%.2X(PC,%c%1u.%c%s)", offset, indexregtype, indexregno, indexsize, scale[scalefactor]);
} }
} }
return pcp; return pcp;
@ -250,7 +250,7 @@ static ULO cpuDis06Extended(ULO regno, ULO pcp, ULO ext, BOOLE is_pc_indirect, S
} }
else else
{ {
sprintf(baseregstr, "A%d", regno); sprintf(baseregstr, "A%u", regno);
} }
} }
@ -262,7 +262,7 @@ static ULO cpuDis06Extended(ULO regno, ULO pcp, ULO ext, BOOLE is_pc_indirect, S
} }
else else
{ /* Index included */ { /* Index included */
sprintf(indexstr, "%c%d.%c%s", indexregtype, indexregno, indexsize, scale[scalefactor]); sprintf(indexstr, "%c%u.%c%s", indexregtype, indexregno, indexsize, scale[scalefactor]);
} }
/* Base displacement */ /* Base displacement */
@ -373,11 +373,9 @@ static ULO cpuDis71(ULO pcp, STR *sdata, STR *soperands)
static ULO cpuDis72(ULO pcp, STR *sdata, STR *soperands) static ULO cpuDis72(ULO pcp, STR *sdata, STR *soperands)
{ {
ULO disp = memoryReadWord(pcp); ULO disp = memoryReadWord(pcp);
ULO ea = pcp + disp;
if (disp & 0x8000) ea += 0xffff0000;
cpuDisWordAppend(disp, sdata); cpuDisWordAppend(disp, sdata);
sprintf(cpuDisEoS(soperands), "$%.4X ; $%.4X(PC)", ea, disp); sprintf(cpuDisEoS(soperands), "$%.4X(PC)", disp);
return pcp + 2; return pcp + 2;
} }
@ -563,7 +561,7 @@ static ULO cpuDisArith4(ULO prc, UWO opc, ULO nr, STR *sdata, STR *sinstruction,
imm = 8; imm = 8;
} }
sprintf(sinstruction, "%sQ.%c", cpu_dis_anr[nr], cpuDisSizeChar(size)); sprintf(sinstruction, "%sQ.%c", cpu_dis_anr[nr], cpuDisSizeChar(size));
sprintf(soperands, "#$%.1d,", imm); sprintf(soperands, "#$%.1u,", imm);
return cpuDisAdrMode(eamode, eareg, prc + 2, size, sdata, soperands); return cpuDisAdrMode(eamode, eareg, prc + 2, size, sdata, soperands);
} }
@ -619,12 +617,12 @@ static ULO cpuDisShift(ULO prc, UWO opc, ULO nr, STR *sdata, STR *sinstruction,
dreg = 8; dreg = 8;
} }
sprintf(sinstruction, "%s%c.%c", cpu_dis_shnr[nr], rl, sc); sprintf(sinstruction, "%s%c.%c", cpu_dis_shnr[nr], rl, sc);
sprintf(soperands, "#$%1X,D%1d", dreg, eareg); sprintf(soperands, "#$%1X,D%1u", dreg, eareg);
} }
else else
{ {
sprintf(sinstruction, "%s%c.%c", cpu_dis_shnr[nr], rl, sc); sprintf(sinstruction, "%s%c.%c", cpu_dis_shnr[nr], rl, sc);
sprintf(soperands, "D%1d,D%1d", dreg, eareg); sprintf(soperands, "D%1u,D%1u", dreg, eareg);
} }
prc += 2; prc += 2;
} }
@ -815,7 +813,7 @@ static ULO cpuDisDBcc(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sope
adr = (offset > 32767) ? (prc + offset - 65536) : (prc + offset); adr = (offset > 32767) ? (prc + offset - 65536) : (prc + offset);
cpuDisWordAppend(offset, sdata); cpuDisWordAppend(offset, sdata);
sprintf(sinstruction, "DB%s", (bratype == 0) ? "T" : ((bratype == 1) ? "F" : cpu_dis_btab[bratype])); sprintf(sinstruction, "DB%s", (bratype == 0) ? "T" : ((bratype == 1) ? "F" : cpu_dis_btab[bratype]));
sprintf(soperands, "D%1d,$%6.6X", cpuDisGetSourceRegister(opc), adr); sprintf(soperands, "D%1u,$%6.6X", cpuDisGetSourceRegister(opc), adr);
return prc + 2; return prc + 2;
} }
@ -851,7 +849,7 @@ static ULO cpuDisExg(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soper
static ULO cpuDisExt(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) static ULO cpuDisExt(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands)
{ {
sprintf(sinstruction, "EXT.%c", (cpuDisGetBit(opc, 6) == 0) ? 'W' : 'L'); sprintf(sinstruction, "EXT.%c", (cpuDisGetBit(opc, 6) == 0) ? 'W' : 'L');
sprintf(soperands, "D%d", cpuDisGetSourceRegister(opc)); sprintf(soperands, "D%u", cpuDisGetSourceRegister(opc));
return prc + 2; return prc + 2;
} }
@ -876,7 +874,7 @@ static ULO cpuDisLink(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sope
cpuDisWordAppend(imm, sdata); cpuDisWordAppend(imm, sdata);
sprintf(sinstruction, "LINK"); sprintf(sinstruction, "LINK");
sprintf(soperands, "A%1d,#$%.4X", cpuDisGetSourceRegister(opc), imm); sprintf(soperands, "A%1u,#$%.4X", cpuDisGetSourceRegister(opc), imm);
return prc + 4; return prc + 4;
} }
@ -1025,11 +1023,11 @@ static ULO cpuDisMovep(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sop
sprintf(sinstruction, "MOVEP.%c", sizech); sprintf(sinstruction, "MOVEP.%c", sizech);
if (to_mem) if (to_mem)
{ {
sprintf(soperands, "D%1d,$%.4X(A%d)", dataregno, disp, adrregno); sprintf(soperands, "D%1u,$%.4X(A%1u)", dataregno, disp, adrregno);
} }
else else
{ {
sprintf(soperands, "$%.4X(A%1d),D%1d,", disp, adrregno, dataregno); sprintf(soperands, "$%.4X(A%1u),D%1u", disp, adrregno, dataregno);
} }
return prc + 4; return prc + 4;
} }
@ -1037,7 +1035,7 @@ static ULO cpuDisMovep(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sop
static ULO cpuDisMoveq(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) static ULO cpuDisMoveq(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands)
{ {
sprintf(sinstruction, "MOVEQ.L"); sprintf(sinstruction, "MOVEQ.L");
sprintf(soperands, "#$%8.8X,D%d", cpuDisGetLowByteSignExtend(opc), cpuDisGetDestinationRegister(opc)); sprintf(soperands, "#$%8.8X,D%u", cpuDisGetLowByteSignExtend(opc), cpuDisGetDestinationRegister(opc));
return prc + 2; return prc + 2;
} }
@ -1224,31 +1222,31 @@ static ULO cpuDisBf(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sopera
sprintf(sinstruction, "BF%s", cpu_dis_bftxt[n]); sprintf(sinstruction, "BF%s", cpu_dis_bftxt[n]);
if (n == 7) if (n == 7)
{ {
sprintf(stmp, "D%d,", (ext >> 12) & 7); sprintf(stmp, "D%u,", (ext >> 12) & 7);
strcat(soperands, stmp); strcat(soperands, stmp);
} }
prc = cpuDisAdrMode(eamode, eareg, prc + 4, 16, sdata, soperands); prc = cpuDisAdrMode(eamode, eareg, prc + 4, 16, sdata, soperands);
if (ext & 0x800) if (ext & 0x800)
{ {
sprintf(stmp, "{D%d:", offset & 7); sprintf(stmp, "{D%u:", offset & 7);
} }
else else
{ {
sprintf(stmp, "{%d:", offset); sprintf(stmp, "{%u:", offset);
} }
strcat(soperands, stmp); strcat(soperands, stmp);
if (ext & 0x20) if (ext & 0x20)
{ {
sprintf(stmp, "D%d}", width & 7); sprintf(stmp, "D%u}", width & 7);
} }
else else
{ {
sprintf(stmp, "%d}", width); sprintf(stmp, "%u}", width);
} }
strcat(soperands, stmp); strcat(soperands, stmp);
if ((n == 1) || (n == 3) || (n == 7)) if ((n == 1) || (n == 3) || (n == 7))
{ {
sprintf(stmp, ",D%d", (ext >> 12) & 7); sprintf(stmp, ",D%u", (ext >> 12) & 7);
strcat(soperands, stmp); strcat(soperands, stmp);
} }
return prc; return prc;
@ -1268,7 +1266,7 @@ static ULO cpuDisCas(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soper
sprintf(sinstruction, "CAS2.%c", cpuDisSizeChar(size)); sprintf(sinstruction, "CAS2.%c", cpuDisSizeChar(size));
sprintf(soperands, sprintf(soperands,
"D%d:D%d,D%d:D%d,(%s%d):(%s%d)", "D%u:D%u,D%u:D%u,(%s%u):(%s%u)",
ext & 7, ext & 7,
ext2 & 7, ext2 & 7,
(ext >> 6) & 7, (ext >> 6) & 7,
@ -1282,7 +1280,7 @@ static ULO cpuDisCas(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soper
else else
{ {
sprintf(sinstruction, "CAS.%c", cpuDisSizeChar(size)); sprintf(sinstruction, "CAS.%c", cpuDisSizeChar(size));
sprintf(soperands, "D%d,D%d,", ext & 7, (ext >> 6) & 7); sprintf(soperands, "D%u,D%u,", ext & 7, (ext >> 6) & 7);
prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, size, sdata, soperands); prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, size, sdata, soperands);
} }
return prc; return prc;
@ -1308,7 +1306,7 @@ static ULO cpuDisChk2(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sope
cpuDisWordAppend(ext, sdata); cpuDisWordAppend(ext, sdata);
sprintf(sinstruction, "%s.%c", (ext & 0x800) ? "CHK2" : "CMP2", cpuDisSizeChar(size)); sprintf(sinstruction, "%s.%c", (ext & 0x800) ? "CHK2" : "CMP2", cpuDisSizeChar(size));
prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, size, sdata, soperands); prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, size, sdata, soperands);
sprintf(stmp, ",%s%d", (ext & 0x8000) ? "A" : "D", (ext>>12) & 7); sprintf(stmp, ",%s%u", (ext & 0x8000) ? "A" : "D", (ext>>12) & 7);
strcat(soperands, stmp); strcat(soperands, stmp);
return prc; return prc;
} }
@ -1328,11 +1326,11 @@ static ULO cpuDisDivl(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sope
prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, 32, sdata, soperands); prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, 32, sdata, soperands);
if (ext & 0x400) if (ext & 0x400)
{ {
sprintf(stmp, ",D%d:D%d", dr, dq); sprintf(stmp, ",D%u:D%u", dr, dq);
} }
else else
{ {
sprintf(stmp, ",D%d", dq); sprintf(stmp, ",D%u", dq);
} }
strcat(soperands, stmp); strcat(soperands, stmp);
return prc; return prc;
@ -1341,7 +1339,7 @@ static ULO cpuDisDivl(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sope
static ULO cpuDisExtb(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) static ULO cpuDisExtb(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands)
{ {
sprintf(sinstruction, "EXTB.L"); sprintf(sinstruction, "EXTB.L");
sprintf(soperands, "D%d", cpuDisGetSourceRegister(opc)); sprintf(soperands, "D%u", cpuDisGetSourceRegister(opc));
return prc + 2; return prc + 2;
} }
@ -1350,7 +1348,7 @@ static ULO cpuDisLinkl(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sop
ULO disp = memoryReadLong(prc + 2); ULO disp = memoryReadLong(prc + 2);
cpuDisLongAppend(disp, sdata); cpuDisLongAppend(disp, sdata);
sprintf(sinstruction, "LINK.L"); sprintf(sinstruction, "LINK.L");
sprintf(soperands, "A%d, #$%.8X", cpuDisGetSourceRegister(opc), disp); sprintf(soperands, "A%u, #$%.8X", cpuDisGetSourceRegister(opc), disp);
return prc + 6; return prc + 6;
} }
@ -1372,7 +1370,7 @@ static ULO cpuDisMovec(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sop
sprintf(sinstruction, "MOVEC.L"); sprintf(sinstruction, "MOVEC.L");
if (opc & 1) if (opc & 1)
{ /* To control register */ { /* To control register */
sprintf(stmp, "%s%d,", (extw & 0x8000) ? "A" : "D", (extw>>12) & 7); sprintf(stmp, "%s%u,", (extw & 0x8000) ? "A" : "D", (extw>>12) & 7);
strcat(soperands, stmp); strcat(soperands, stmp);
} }
creg = extw & 0xfff; creg = extw & 0xfff;
@ -1410,7 +1408,7 @@ static ULO cpuDisMovec(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sop
} }
if (!(opc & 1)) if (!(opc & 1))
{ /* From control register */ { /* From control register */
sprintf(stmp, ",%s%d", (extw & 0x8000) ? "A":"D", (extw >> 12) & 7); sprintf(stmp, ",%s%u", (extw & 0x8000) ? "A":"D", (extw >> 12) & 7);
strcat(soperands, stmp); strcat(soperands, stmp);
} }
return prc + 4; return prc + 4;
@ -1427,13 +1425,13 @@ static ULO cpuDisMoves(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sop
sprintf(sinstruction, "MOVES.%c", cpuDisSizeChar(size)); sprintf(sinstruction, "MOVES.%c", cpuDisSizeChar(size));
if (ext & 0x800) if (ext & 0x800)
{ {
sprintf(stmp, "%s%d,", (ext & 0x8000) ? "A" : "D", (ext >> 12) & 7); sprintf(stmp, "%s%u,", (ext & 0x8000) ? "A" : "D", (ext >> 12) & 7);
strcat(soperands, stmp); strcat(soperands, stmp);
} }
prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, size, sdata, soperands); prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, size, sdata, soperands);
if (!(ext & 0x800)) if (!(ext & 0x800))
{ {
sprintf(stmp, ",%s%d", (ext & 0x8000) ? "A" : "D", (ext >> 12) & 7); sprintf(stmp, ",%s%u", (ext & 0x8000) ? "A" : "D", (ext >> 12) & 7);
strcat(soperands, stmp); strcat(soperands, stmp);
} }
return prc; return prc;
@ -1454,11 +1452,11 @@ static ULO cpuDisMull(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sope
prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, 32, sdata, soperands); prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, 32, sdata, soperands);
if (ext & 0x400) if (ext & 0x400)
{ {
sprintf(stmp, ",D%d:D%d", dh, dl); sprintf(stmp, ",D%u:D%u", dh, dl);
} }
else else
{ {
sprintf(stmp, ",D%d", dl); sprintf(stmp, ",D%u", dl);
} }
strcat(soperands, stmp); strcat(soperands, stmp);
return prc; return prc;
@ -1491,12 +1489,12 @@ static void cpuDisPflush030PrintFc(STR *soperands, ULO fcode)
else if (fcode == 1) strcat(soperands, "DFC,"); else if (fcode == 1) strcat(soperands, "DFC,");
else if ((fcode & 0x18) == 8) else if ((fcode & 0x18) == 8)
{ {
sprintf(stmp, "D%d,", fcode & 7); sprintf(stmp, "D%u,", fcode & 7);
strcat(soperands, stmp); strcat(soperands, stmp);
} }
else if ((fcode & 0x18) == 0x10) else if ((fcode & 0x18) == 0x10)
{ {
sprintf(stmp, "#%d,", fcode & 7); sprintf(stmp, "#%u,", fcode & 7);
strcat(soperands, stmp); strcat(soperands, stmp);
} }
} }
@ -1566,11 +1564,11 @@ static ULO cpuDisPflush040(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR
{ {
case 0: case 0:
sprintf(sinstruction, "PFLUSHN"); sprintf(sinstruction, "PFLUSHN");
sprintf(soperands, "(A%d)", reg); sprintf(soperands, "(A%u)", reg);
break; break;
case 1: case 1:
sprintf(sinstruction, "PFLUSH"); sprintf(sinstruction, "PFLUSH");
sprintf(soperands, "(A%d)", reg); sprintf(soperands, "(A%u)", reg);
break; break;
case 2: case 2:
sprintf(sinstruction, "PFLUSHAN"); sprintf(sinstruction, "PFLUSHAN");
@ -1590,7 +1588,7 @@ static ULO cpuDisPtest040(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *
ULO rw = cpuDisGetBit(opc, 5); ULO rw = cpuDisGetBit(opc, 5);
sprintf(sinstruction, "PTEST%c", (rw) ? 'R' : 'W'); sprintf(sinstruction, "PTEST%c", (rw) ? 'R' : 'W');
sprintf(soperands, "(A%d)", reg); sprintf(soperands, "(A%u)", reg);
return prc + 2; return prc + 2;
} }
@ -1652,14 +1650,14 @@ static ULO cpuDisCallm(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *sop
ULO eareg = cpuDisGetSourceRegister(opc); ULO eareg = cpuDisGetSourceRegister(opc);
ULO ext = memoryReadWord(prc + 2); ULO ext = memoryReadWord(prc + 2);
cpuDisWordAppend(ext, sdata); cpuDisWordAppend(ext, sdata);
sprintf(soperands, "#%d,", ext & 0xff); sprintf(soperands, "#%u,", ext & 0xff);
return cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, 16, sdata, soperands); return cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, 16, sdata, soperands);
} }
static ULO cpuDisRtm(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) static ULO cpuDisRtm(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands)
{ {
sprintf(sinstruction, "RTM"); sprintf(sinstruction, "RTM");
sprintf(soperands, "%c%d", (opc & 8) ? 'A':'D', cpuDisGetSourceRegister(opc)); sprintf(soperands, "%c%u", (opc & 8) ? 'A':'D', cpuDisGetSourceRegister(opc));
return prc + 2; return prc + 2;
} }

2
cpu/CpuModule_EffectiveAddress.c
View File

@ -1,4 +1,4 @@
/* @(#) $Id: CpuModule_EffectiveAddress.c,v 1.3 2012/07/15 22:20:35 peschau Exp $ */ /* @(#) $Id: CpuModule_EffectiveAddress.c,v 1.3 2012-07-15 22:20:35 peschau Exp $ */
/*=========================================================================*/ /*=========================================================================*/
/* Fellow */ /* Fellow */
/* CPU 68k effective address calculation functions */ /* CPU 68k effective address calculation functions */

46
cpu/CpuModule_Exceptions.c
View File

@ -1,4 +1,4 @@
/* @(#) $Id: CpuModule_Exceptions.c,v 1.5 2012/08/12 16:51:02 peschau Exp $ */ /* @(#) $Id: CpuModule_Exceptions.c,v 1.5 2012-08-12 16:51:02 peschau Exp $ */
/*=========================================================================*/ /*=========================================================================*/
/* Fellow */ /* Fellow */
/* CPU 68k exception handling functions */ /* CPU 68k exception handling functions */
@ -94,26 +94,54 @@ static STR *cpuGetExceptionName(ULO vector_offset)
Sets up an exception Sets up an exception
===============================================*/ ===============================================*/
void cpuExceptionFail(BOOLE executejmp)
{
// Avoid endless loop that will crash the emulator.
// The (odd) address error exception vector contained an odd address.
cpuCallResetExceptionFunc();
cpuHardReset();
cpuSetInstructionTime(132);
if (executejmp)
{
cpuCallMidInstructionExceptionFunc(); // Supposed to be doing setjmp/longjmp back to machine emulator code
}
}
void cpuThrowException(ULO vector_offset, ULO pc, BOOLE executejmp) void cpuThrowException(ULO vector_offset, ULO pc, BOOLE executejmp)
{ {
ULO vector_address; ULO vector_address;
BOOLE is_address_error_on_sub_020 = (cpuGetModelMajor() < 2 && vector_offset == 0xc);
BOOLE stack_is_even = !(cpuGetAReg(7) & 1);
BOOLE vbr_is_even = !(cpuGetVbr() & 1);
if ((is_address_error_on_sub_020 && !stack_is_even) || !vbr_is_even)
{
cpuExceptionFail(executejmp);
return;
}
#ifdef CPU_INSTRUCTION_LOGGING #ifdef CPU_INSTRUCTION_LOGGING
cpuCallExceptionLoggingFunc(cpuGetExceptionName(vector_offset), cpuGetOriginalPC(), cpuGetCurrentOpcode()); cpuCallExceptionLoggingFunc(cpuGetExceptionName(vector_offset), cpuGetOriginalPC(), cpuGetCurrentOpcode());
#endif #endif
cpuActivateSSP(); cpuActivateSSP();
stack_is_even = !(cpuGetAReg(7) & 1);
if (is_address_error_on_sub_020 && !stack_is_even)
{
cpuExceptionFail(executejmp);
return;
}
cpuStackFrameGenerate((UWO) vector_offset, pc); cpuStackFrameGenerate((UWO) vector_offset, pc);
// read a memory position // read a memory position
vector_address = memoryReadLong(cpuGetVbr() + vector_offset); vector_address = memoryReadLong(cpuGetVbr() + vector_offset);
if (cpuGetModelMajor() < 2 && vector_address & 0x1 && vector_offset == 0xc) if (is_address_error_on_sub_020 && vector_address & 1)
{ {
// Avoid endless loop that will crash the emulator. cpuExceptionFail(executejmp);
// The (odd) address error exception vector contained an odd address. return;
cpuCallResetExceptionFunc();
cpuHardReset();
cpuSetInstructionTime(132);
} }
else else
{ {
@ -192,7 +220,7 @@ void cpuThrowTraceException(void)
void cpuThrowAddressErrorException(void) void cpuThrowAddressErrorException(void)
{ {
cpuThrowException(0xc, cpuGetPC(), TRUE); cpuThrowException(0xc, cpuGetPC() - 2, TRUE);
} }
/*=================*/ /*=================*/

2
cpu/CpuModule_Flags.c
View File

@ -1,4 +1,4 @@
/* @(#) $Id: CpuModule_Flags.c,v 1.3 2011/07/18 17:22:55 peschau Exp $ */ /* @(#) $Id: CpuModule_Flags.c,v 1.3 2011-07-18 17:22:55 peschau Exp $ */
/*=========================================================================*/ /*=========================================================================*/
/* Fellow */ /* Fellow */
/* 68000 flag and condition code handling */ /* 68000 flag and condition code handling */

691
cpu/CpuModule_Instructions.c
View File

File diff suppressed because it is too large Load Diff

5
cpu/CpuModule_Internal.h
View File

@ -51,7 +51,7 @@ extern void cpuSetCaar(ULO caar);
extern ULO cpuGetCaar(void); extern ULO cpuGetCaar(void);
extern void cpuSetSR(ULO sr); extern void cpuSetSR(ULO sr);
extern ULO cpuGetSR(void); extern ULO cpuGetSR(void);
extern void cpuSetIrqLevel(ULO irq_level); extern BOOLE cpuSetIrqLevel(ULO new_interrupt_level);
extern ULO cpuGetIrqLevel(void); extern ULO cpuGetIrqLevel(void);
extern void cpuSetIrqAddress(ULO irq_address); extern void cpuSetIrqAddress(ULO irq_address);
extern ULO cpuGetIrqAddress(void); extern ULO cpuGetIrqAddress(void);
@ -167,10 +167,11 @@ extern void cpuCallInterruptLoggingFunc(ULO level, ULO vector_address);
#endif #endif
// Interrupt // Interrupt
extern void cpuCallCheckPendingInterruptsFunc(void);
extern ULO cpuActivateSSP(void); extern ULO cpuActivateSSP(void);
extern void cpuSetRaiseInterrupt(BOOLE raise_irq); extern void cpuSetRaiseInterrupt(BOOLE raise_irq);
extern BOOLE cpuGetRaiseInterrupt(void); extern BOOLE cpuGetRaiseInterrupt(void);
extern void cpuSetRaiseInterruptLevel(ULO raise_irq_level);
extern ULO cpuGetRaiseInterruptLevel(void);
// Exceptions // Exceptions
extern void cpuThrowPrivilegeViolationException(void); extern void cpuThrowPrivilegeViolationException(void);

19
cpu/CpuModule_InternalState.c
View File

@ -1,4 +1,4 @@
/* @(#) $Id: CpuModule_InternalState.c,v 1.9 2012/08/12 16:51:02 peschau Exp $ */ /* @(#) $Id: CpuModule_InternalState.c,v 1.9 2012-08-12 16:51:02 peschau Exp $ */
/*=========================================================================*/ /*=========================================================================*/
/* Fellow */ /* Fellow */
/* 68000 internal state */ /* 68000 internal state */
@ -43,8 +43,7 @@ static ULO cpu_caar;
/* Irq management */ /* Irq management */
static BOOLE cpu_raise_irq; static BOOLE cpu_raise_irq;
static ULO cpu_irq_level; static ULO cpu_raise_irq_level;
static ULO cpu_irq_address;
/* Reset values */ /* Reset values */
static ULO cpu_initial_pc; static ULO cpu_initial_pc;
@ -186,12 +185,6 @@ ULO cpuGetCaar(void) {return cpu_caar;}
void cpuSetSR(ULO sr) {cpu_sr = sr;} void cpuSetSR(ULO sr) {cpu_sr = sr;}
ULO cpuGetSR(void) {return cpu_sr;} ULO cpuGetSR(void) {return cpu_sr;}
void cpuSetIrqLevel(ULO irq_level) {cpu_irq_level = irq_level;}
ULO cpuGetIrqLevel(void) {return cpu_irq_level;}
void cpuSetIrqAddress(ULO irq_address) {cpu_irq_address = irq_address;}
ULO cpuGetIrqAddress(void) {return cpu_irq_address;}
void cpuSetInstructionTime(ULO cycles) {cpu_instruction_time = cycles;} void cpuSetInstructionTime(ULO cycles) {cpu_instruction_time = cycles;}
ULO cpuGetInstructionTime(void) {return cpu_instruction_time;} ULO cpuGetInstructionTime(void) {return cpu_instruction_time;}
@ -207,6 +200,10 @@ UWO cpuGetCurrentOpcode(void) {return cpu_current_opcode;}
void cpuSetRaiseInterrupt(BOOLE raise_irq) {cpu_raise_irq = raise_irq;} void cpuSetRaiseInterrupt(BOOLE raise_irq) {cpu_raise_irq = raise_irq;}
BOOLE cpuGetRaiseInterrupt(void) {return cpu_raise_irq;} BOOLE cpuGetRaiseInterrupt(void) {return cpu_raise_irq;}
void cpuSetRaiseInterruptLevel(ULO raise_irq_level) {cpu_raise_irq_level = raise_irq_level;}
ULO cpuGetRaiseInterruptLevel(void) {return cpu_raise_irq_level;}
ULO cpuGetIrqLevel(void) {return (cpu_sr & 0x0700) >> 8;}
void cpuSetInitialPC(ULO pc) {cpu_initial_pc = pc;} void cpuSetInitialPC(ULO pc) {cpu_initial_pc = pc;}
ULO cpuGetInitialPC(void) {return cpu_initial_pc;} ULO cpuGetInitialPC(void) {return cpu_initial_pc;}
@ -352,8 +349,6 @@ void cpuSaveState(FILE *F)
fwrite(&cpu_vbr, sizeof(cpu_vbr), 1, F); fwrite(&cpu_vbr, sizeof(cpu_vbr), 1, F);
fwrite(&cpu_cacr, sizeof(cpu_cacr), 1, F); fwrite(&cpu_cacr, sizeof(cpu_cacr), 1, F);
fwrite(&cpu_caar, sizeof(cpu_caar), 1, F); fwrite(&cpu_caar, sizeof(cpu_caar), 1, F);
fwrite(&cpu_irq_level, sizeof(cpu_irq_level), 1, F);
fwrite(&cpu_irq_address, sizeof(cpu_irq_address), 1, F);
fwrite(&cpu_initial_pc, sizeof(cpu_initial_pc), 1, F); fwrite(&cpu_initial_pc, sizeof(cpu_initial_pc), 1, F);
fwrite(&cpu_initial_sp, sizeof(cpu_initial_sp), 1, F); fwrite(&cpu_initial_sp, sizeof(cpu_initial_sp), 1, F);
} }
@ -382,8 +377,6 @@ void cpuLoadState(FILE *F)
fread(&cpu_vbr, sizeof(cpu_vbr), 1, F); fread(&cpu_vbr, sizeof(cpu_vbr), 1, F);
fread(&cpu_cacr, sizeof(cpu_cacr), 1, F); fread(&cpu_cacr, sizeof(cpu_cacr), 1, F);
fread(&cpu_caar, sizeof(cpu_caar), 1, F); fread(&cpu_caar, sizeof(cpu_caar), 1, F);
fread(&cpu_irq_level, sizeof(cpu_irq_level), 1, F);
fread(&cpu_irq_address, sizeof(cpu_irq_address), 1, F);
fread(&cpu_initial_pc, sizeof(cpu_initial_pc), 1, F); fread(&cpu_initial_pc, sizeof(cpu_initial_pc), 1, F);
fread(&cpu_initial_sp, sizeof(cpu_initial_sp), 1, F); fread(&cpu_initial_sp, sizeof(cpu_initial_sp), 1, F);
cpuSetModel(cpu_model_major, cpu_model_minor); // Recalculates stack frames etc. cpuSetModel(cpu_model_major, cpu_model_minor); // Recalculates stack frames etc.

40
cpu/CpuModule_Interrupts.c
View File

@ -1,4 +1,4 @@
/* @(#) $Id: CpuModule_Interrupts.c,v 1.5 2012/08/12 16:51:02 peschau Exp $ */ /* @(#) $Id: CpuModule_Interrupts.c,v 1.5 2012-08-12 16:51:02 peschau Exp $ */
/*=========================================================================*/ /*=========================================================================*/
/* Fellow */ /* Fellow */
/* 68000 interrupt handling */ /* 68000 interrupt handling */
@ -31,15 +31,10 @@
/* Function for checking pending interrupts */ /* Function for checking pending interrupts */
cpuCheckPendingInterruptsFunc cpu_check_pending_interrupts_func; cpuCheckPendingInterruptsFunc cpu_check_pending_interrupts_func;
void cpuCallCheckPendingInterruptsFunc(void)
{
if (cpuGetRaiseInterrupt()) return;
cpuSetRaiseInterrupt(cpu_check_pending_interrupts_func());
}
void cpuCheckPendingInterrupts(void) void cpuCheckPendingInterrupts(void)
{ {
cpuCallCheckPendingInterruptsFunc(); if (cpuGetRaiseInterrupt()) return;
if (cpu_check_pending_interrupts_func) cpu_check_pending_interrupts_func();
} }
void cpuSetCheckPendingInterruptsFunc(cpuCheckPendingInterruptsFunc func) void cpuSetCheckPendingInterruptsFunc(cpuCheckPendingInterruptsFunc func)
@ -70,24 +65,41 @@ ULO cpuActivateSSP(void)
return currentSP; return currentSP;
} }
// Retrns TRUE if the CPU is in the stopped state,
// this allows our scheduling queue to start
// scheduling CPU events again.
BOOLE cpuSetIrqLevel(ULO new_interrupt_level)
{
cpuSetRaiseInterrupt(TRUE);
cpuSetRaiseInterruptLevel(new_interrupt_level);
if (cpuGetStop())
{
cpuSetStop(FALSE);
return TRUE;
}
return FALSE;
}
/*============================================================ /*============================================================
Transfers control to an interrupt routine Transfers control to an interrupt routine
============================================================*/ ============================================================*/
// Returns TRUE if the cpu was stopped void cpuSetUpInterrupt(ULO new_interrupt_level)
void cpuSetUpInterrupt(void)
{ {
UWO vector_offset = (UWO) (0x60 + cpuGetIrqLevel()*4); UWO vector_offset = (UWO) (0x60 + new_interrupt_level*4);
ULO vector_address = memoryReadLong(cpuGetVbr() + vector_offset);
cpuActivateSSP(); // Switch to using ssp or msp. Loads a7 and preserves usp if we came from user-mode. cpuActivateSSP(); // Switch to using ssp or msp. Loads a7 and preserves usp if we came from user-mode.
cpuStackFrameGenerate(vector_offset, cpuGetPC()); // This will end up on msp if master is enabled, or on the ssp/isp if not. cpuStackFrameGenerate(vector_offset, cpuGetPC()); // This will end up on msp if master is enabled, or on the ssp/isp if not.
cpuSetSR(cpuGetSR() & 0x38ff); // Clear interrupt level cpuSetSR(cpuGetSR() & 0x38ff); // Clear interrupt level
cpuSetSR(cpuGetSR() | 0x2000); // Set supervisor mode cpuSetSR(cpuGetSR() | 0x2000); // Set supervisor mode
cpuSetSR(cpuGetSR() | (UWO)(cpuGetIrqLevel() << 8)); // Set interrupt level cpuSetSR(cpuGetSR() | (UWO)(new_interrupt_level << 8)); // Set interrupt level
#ifdef CPU_INSTRUCTION_LOGGING #ifdef CPU_INSTRUCTION_LOGGING
cpuCallInterruptLoggingFunc(cpuGetIrqLevel(), cpuGetIrqAddress()); cpuCallInterruptLoggingFunc(new_interrupt_level, vector_address);
#endif #endif
if (cpuGetModelMajor() >= 2 && cpuGetModelMajor() < 6) if (cpuGetModelMajor() >= 2 && cpuGetModelMajor() < 6)
@ -101,7 +113,7 @@ void cpuSetUpInterrupt(void)
cpuSetSR(cpuGetSR() & 0xefff); // Clear master bit cpuSetSR(cpuGetSR() & 0xefff); // Clear master bit
} }
} }
cpuInitializeFromNewPC(cpuGetIrqAddress()); cpuInitializeFromNewPC(vector_address);
cpuSetStop(FALSE); cpuSetStop(FALSE);
cpuSetRaiseInterrupt(FALSE); cpuSetRaiseInterrupt(FALSE);
} }

2
cpu/CpuModule_Logging.c
View File

@ -1,4 +1,4 @@
/* @(#) $Id: CpuModule_Logging.c,v 1.3 2012/08/12 16:51:02 peschau Exp $ */ /* @(#) $Id: CpuModule_Logging.c,v 1.3 2012-08-12 16:51:02 peschau Exp $ */
/*=========================================================================*/ /*=========================================================================*/
/* Fellow */ /* Fellow */
/* CPU 68k logging functions */ /* CPU 68k logging functions */

2
cpu/CpuModule_StackFrameGen.c
View File

@ -1,4 +1,4 @@
/* @(#) $Id: CpuModule_StackFrameGen.c,v 1.3 2011/07/18 17:22:55 peschau Exp $ */ /* @(#) $Id: CpuModule_StackFrameGen.c,v 1.3 2011-07-18 17:22:55 peschau Exp $ */
/*=========================================================================*/ /*=========================================================================*/
/* Fellow */ /* Fellow */
/* 68000 stack frame generation */ /* 68000 stack frame generation */

1
cpu/defs.h
View File

@ -4,6 +4,7 @@
#include <stdint.h> #include <stdint.h>
#include <stdio.h> #include <stdio.h>
#include <string.h> #include <string.h>
#include <stdbool.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {