diff --git a/cpu/CpuIntegration.c b/cpu/CpuIntegration.c new file mode 100644 index 0000000..5c8a53d --- /dev/null +++ b/cpu/CpuIntegration.c @@ -0,0 +1,458 @@ +/* @(#) $Id: CpuIntegration.c,v 1.10 2013/01/08 19:17:33 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* Initialization of 68000 core */ +/* Integrates the 68k emulation with custom chips */ +/* */ +/* Author: Petter Schau */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ + +#include "defs.h" +#include "fellow.h" +#include "fmem.h" +#include "CpuModule.h" +#include "CpuIntegration.h" +#include "CpuModule_Internal.h" +#include "bus.h" +#include "fileops.h" + + +jmp_buf cpu_integration_exception_buffer; + +/* custom chip intreq bit-number to irq-level */ +static ULO cpu_integration_int_to_level[16] = {1,1,1,2, 3,3,3,4, 4,4,4,5, 5,6,6,7}; +static ULO cpu_integration_irq_source; + +/* Cycles spent by chips (Blitter) as a result of an instruction */ +static ULO cpu_integration_chip_cycles; +static ULO cpu_integration_chip_slowdown; + +/*===========================================================================*/ +/* CPU properties */ +/*===========================================================================*/ + +ULO cpu_integration_speed; // The speed as expressed in the fellow configuration settings +ULO cpu_integration_speed_multiplier; // The cycle multiplier used to adjust the cpu-speed, calculated from cpu_integration_speed +cpu_integration_models cpu_integration_model; // The cpu model as expressed in the fellow configuration settings + +/*===========================================================================*/ +/* CPU properties */ +/*===========================================================================*/ + +void cpuIntegrationSetSpeed(ULO speed) +{ + cpu_integration_speed = speed; +} + +ULO cpuIntegrationGetSpeed(void) +{ + return cpu_integration_speed; +} + +static void cpuIntegrationSetSpeedMultiplier(ULO multiplier) +{ + cpu_integration_speed_multiplier = multiplier; +} + +static ULO cpuIntegrationGetSpeedMultiplier(void) +{ + return cpu_integration_speed_multiplier; +} + +static void cpuIntegrationCalculateMultiplier(void) +{ + ULO multiplier = 12; + + switch (cpuGetModelMajor()) + { + case 0: + multiplier = 12; + break; + case 1: + multiplier = 12; + break; + case 2: + multiplier = 11; + break; + case 3: + multiplier = 11; + break; + } + + if (cpuIntegrationGetSpeed() >= 8) cpuIntegrationSetSpeedMultiplier(multiplier); + else if (cpuIntegrationGetSpeed() >= 4) cpuIntegrationSetSpeedMultiplier(multiplier - 1); + else if (cpuIntegrationGetSpeed() >= 2) cpuIntegrationSetSpeedMultiplier(multiplier - 2); + else if (cpuIntegrationGetSpeed() >= 1) cpuIntegrationSetSpeedMultiplier(multiplier - 3); + else cpuIntegrationSetSpeedMultiplier(multiplier - 4); +} + +BOOLE cpuIntegrationSetModel(cpu_integration_models model) +{ + BOOLE needreset = (cpu_integration_model != model); + cpu_integration_model = model; + + switch (cpu_integration_model) + { + case M68000: cpuSetModel(0, 0); break; + case M68010: cpuSetModel(1, 0); break; + case M68020: cpuSetModel(2, 0); break; + case M68030: cpuSetModel(3, 0); break; + case M68EC20: cpuSetModel(2, 1); break; + case M68EC30: cpuSetModel(3, 1); break; + } + return needreset; +} + +cpu_integration_models cpuIntegrationGetModel(void) +{ + return cpu_integration_model; +} + +void cpuIntegrationSetChipCycles(ULO chip_cycles) +{ + cpu_integration_chip_cycles = chip_cycles; +} + +ULO cpuIntegrationGetChipCycles(void) +{ + return cpu_integration_chip_cycles; +} + +void cpuIntegrationSetChipSlowdown(ULO chip_slowdown) +{ + cpu_integration_chip_slowdown = chip_slowdown; +} + +ULO cpuIntegrationGetChipSlowdown(void) +{ + return cpu_integration_chip_slowdown; +} + +ULO cpuIntegrationGetChipIrqToIntLevel(ULO chip_irq) +{ + return cpu_integration_int_to_level[chip_irq]; +} + +void cpuIntegrationSetIrqSource(ULO irq_source) +{ + cpu_integration_irq_source = irq_source; +} + +ULO cpuIntegrationGetIrqSource(void) +{ + return cpu_integration_irq_source; +} + +/*===================================================== + Checking for waiting interrupts + =====================================================*/ + +static BOOLE cpuIntegrationCheckPendingInterruptsFunc(void) +{ + ULO current_cpu_level = (cpuGetSR() >> 8) & 7; + BOOLE chip_irqs_enabled = !!(intena & 0x4000); + + if (chip_irqs_enabled) + { + LON highest_chip_irq; + ULO chip_irqs = intreq & intena; + + if (chip_irqs == 0) return FALSE; + + for (highest_chip_irq = 13; highest_chip_irq >= 0; highest_chip_irq--) + { + if (chip_irqs & (1 << highest_chip_irq)) + { + // Found a chip-irq that is both flagged and enabled. + ULO highest_chip_level = cpuIntegrationGetChipIrqToIntLevel(highest_chip_irq); + if (highest_chip_level > current_cpu_level) + { + cpuSetIrqLevel(highest_chip_level); + cpuSetIrqAddress(memoryReadLong(cpuGetVbr() + 0x60 + highest_chip_level*4)); + cpuIntegrationSetIrqSource(highest_chip_irq); + + if (cpuGetStop()) + { + cpuSetStop(FALSE); + cpuEvent.cycle = bus.cycle; + } + return TRUE; + } + } + } + } + return FALSE; +} + +void cpuIntegrationCheckPendingInterrupts(void) +{ + cpuCheckPendingInterrupts(); +} + +/*=========================================*/ +/* Exception mid-instruction exit function */ +/*=========================================*/ + +void cpuIntegrationMidInstructionExceptionFunc(void) +{ + longjmp(cpu_integration_exception_buffer, -1); +} + +/*===================================================*/ +/* Handles reset exception event from the cpu-module */ +/*===================================================*/ + +void cpuIntegrationResetExceptionFunc(void) +{ + fellowSoftReset(); +} + +/*=========*/ +/* Logging */ +/*=========*/ + +#ifdef CPU_INSTRUCTION_LOGGING + +FILE *CPUINSTRUCTIONLOG; +int cpu_disable_instruction_log = TRUE; + +void cpuInstructionLogOpen(void) +{ + if (CPUINSTRUCTIONLOG == NULL) + { + char filename[MAX_PATH]; + fileopsGetGenericFileName(filename, "WinFellow", "cpuinstructions.log"); + CPUINSTRUCTIONLOG = fopen(filename, "w"); + } +} + +void cpuIntegrationPrintBusCycle(void) +{ + fprintf(CPUINSTRUCTIONLOG, "%d:%.5d ", bus.frame_no, bus.cycle); +} + +void cpuIntegrationInstructionLogging(void) +{ + char saddress[256], sdata[256], sinstruction[256], soperands[256]; + + if (cpu_disable_instruction_log) return; + cpuInstructionLogOpen(); + /* + fprintf(CPUINSTRUCTIONLOG, + "D0:%.8X D1:%.8X D2:%.8X D3:%.8X D4:%.8X D5:%.8X D6:%.8X D7:%.8X\n", + cpuGetDReg(0), + cpuGetDReg(1), + cpuGetDReg(2), + cpuGetDReg(3), + cpuGetDReg(4), + cpuGetDReg(5), + cpuGetDReg(6), + cpuGetDReg(7)); + + fprintf(CPUINSTRUCTIONLOG, + "A0:%.8X A1:%.8X A2:%.8X A3:%.8X A4:%.8X A5:%.8X A6:%.8X A7:%.8X\n", + cpuGetAReg(0), + cpuGetAReg(1), + cpuGetAReg(2), + cpuGetAReg(3), + cpuGetAReg(4), + cpuGetAReg(5), + cpuGetAReg(6), + cpuGetAReg(7)); + */ + saddress[0] = '\0'; + sdata[0] = '\0'; + sinstruction[0] = '\0'; + soperands[0] = '\0'; + cpuDisOpcode(cpuGetPC(), saddress, sdata, sinstruction, soperands); + fprintf(CPUINSTRUCTIONLOG, "SSP:%.6X USP:%.6X SP:%.4X %s %s\t%s\t%s\n", cpuGetSspDirect(), cpuGetUspDirect(), cpuGetSR(), saddress, sdata, sinstruction, soperands); +} + +void cpuIntegrationExceptionLogging(STR *description, ULO original_pc, UWO opcode) +{ + if (cpu_disable_instruction_log) return; + cpuInstructionLogOpen(); + + cpuIntegrationPrintBusCycle(); + fprintf(CPUINSTRUCTIONLOG, "%s for opcode %.4X at PC %.8X from PC %.8X\n", description, opcode, original_pc, cpuGetPC()); +} + +STR *cpuIntegrationGetInterruptName(ULO chip_irq_no) +{ + switch (chip_irq_no) + { + case 0: return "TBE: Output buffer of the serial port is empty."; + case 1: return "DSKBLK: Disk DMA transfer ended."; + case 2: return "SOFT: Software interrupt."; + case 3: return "PORTS: From CIA-A or expansion port."; + case 4: return "COPER: Copper interrupt."; + case 5: return "VERTB: Start of vertical blank."; + case 6: return "BLIT: Blitter done."; + case 7: return "AUD0: Audio data on channel 0."; + case 8: return "AUD1: Audio data on channel 1."; + case 9: return "AUD2: Audio data on channel 2."; + case 10: return "AUD3: Audio data on channel 3."; + case 11: return "RBF: Input buffer of the serial port full."; + case 12: return "DSKSYN: Disk sync value recognized."; + case 13: return "EXTER: From CIA-B or expansion port."; + case 14: return "INTEN: BUG! Not an interrupt."; + case 15: return "NMI: BUG! Not an interrupt."; + } + return "Illegal interrupt source!"; +} + +void cpuIntegrationInterruptLogging(ULO level, ULO vector_address) +{ + if (cpu_disable_instruction_log) return; + cpuInstructionLogOpen(); + + cpuIntegrationPrintBusCycle(); + fprintf(CPUINSTRUCTIONLOG, "Irq %d to %.6X (%s)\n", level, vector_address, cpuIntegrationGetInterruptName(cpuIntegrationGetIrqSource())); +} + +#endif + +void cpuIntegrationExecuteInstructionEventHandler68000Fast(void) +{ + ULO cycles; + cycles = cpuExecuteInstruction(); + + if (cpuGetStop()) + { + cpuEvent.cycle = BUS_CYCLE_DISABLE; + } + else + { + cpuEvent.cycle += ((cycles*cpuIntegrationGetChipSlowdown())>>1) + cpuIntegrationGetChipCycles(); + } + cpuIntegrationSetChipCycles(0); +} + +void cpuIntegrationExecuteInstructionEventHandler68000General(void) +{ + ULO cycles = 0; + ULO time_used = 0; + + do + { + cycles = cpuExecuteInstruction(); + cycles = cycles*cpuIntegrationGetChipSlowdown(); // Compensate for blitter time + time_used += (cpuIntegrationGetChipCycles()<<12) + (cycles<>12); + } + cpuIntegrationSetChipCycles(0); +} + +void cpuIntegrationExecuteInstructionEventHandler68020(void) +{ + ULO time_used = 0; + do + { + cpuExecuteInstruction(); + time_used += (cpuIntegrationGetChipCycles()<<12) + (4<>12); + } + cpuIntegrationSetChipCycles(0); +} + +void cpuIntegrationSetDefaultConfig(void) +{ + cpuIntegrationSetModel(M68000); + cpuIntegrationSetChipCycles(0); + cpuIntegrationSetChipSlowdown(1); + cpuIntegrationSetSpeed(4); + + cpuSetCheckPendingInterruptsFunc(cpuIntegrationCheckPendingInterruptsFunc); + cpuSetMidInstructionExceptionFunc(cpuIntegrationMidInstructionExceptionFunc); + cpuSetResetExceptionFunc(cpuIntegrationResetExceptionFunc); + +#ifdef CPU_INSTRUCTION_LOGGING + cpuSetInstructionLoggingFunc(cpuIntegrationInstructionLogging); + cpuSetExceptionLoggingFunc(cpuIntegrationExceptionLogging); + cpuSetInterruptLoggingFunc(cpuIntegrationInterruptLogging); +#endif +} + +/*=========================*/ +/* Fellow lifecycle events */ +/*=========================*/ + +void cpuIntegrationSaveState(FILE *F) +{ + cpuSaveState(F); + + fwrite(&cpu_integration_chip_slowdown, sizeof(cpu_integration_chip_slowdown), 1, F); + // Everything else is configuration options which will be set when the associated config-file is loaded. +} + +void cpuIntegrationLoadState(FILE *F) +{ + cpuLoadState(F); + + fread(&cpu_integration_chip_slowdown, sizeof(cpu_integration_chip_slowdown), 1, F); + // Everything else is configuration options which will be set when the associated config-file is loaded. +} + +void cpuIntegrationEmulationStart(void) +{ + cpuIntegrationCalculateMultiplier(); +} + +void cpuIntegrationEmulationStop(void) +{ +} + +void cpuIntegrationHardReset(void) +{ + cpuIntegrationSetChipCycles(0); + cpuIntegrationSetChipSlowdown(1); + cpuSetInitialPC(memoryInitialPC()); + cpuSetInitialSP(memoryInitialSP()); + cpuHardReset(); +} + +void cpuIntegrationStartup(void) +{ + cpuStartup(); + cpuIntegrationSetDefaultConfig(); + cpuCreateMulTimeTables(); +} + +void cpuIntegrationShutdown(void) +{ + cpuProfileWrite(); +} diff --git a/cpu/CpuIntegration.h b/cpu/CpuIntegration.h new file mode 100644 index 0000000..d4a51c5 --- /dev/null +++ b/cpu/CpuIntegration.h @@ -0,0 +1,44 @@ +#ifndef CpuIntegration_H +#define CpuIntegration_H + +typedef enum { + M68000 = 0, + M68010 = 1, + M68020 = 2, + M68030 = 3, + M68EC30 = 4, + M68EC20 = 9 +} cpu_integration_models; + +extern void cpuIntegrationSetUpInterruptEventHandler(void); +extern void cpuIntegrationExecuteInstructionEventHandler68000Fast(void); +extern void cpuIntegrationExecuteInstructionEventHandler68000General(void); +extern void cpuIntegrationExecuteInstructionEventHandler68020(void); +extern void cpuIntegrationCheckPendingInterrupts(void); +extern ULO cpuIntegrationDisOpcode(ULO disasm_pc, STR *saddress, STR *sdata, STR *sinstruction, STR *soperands); + +extern BOOLE cpuIntegrationSetModel(cpu_integration_models model); +extern cpu_integration_models cpuIntegrationGetModel(void); +extern ULO cpuIntegrationGetModelMajor(void); +extern ULO cpuIntegrationGetPC(void); + +extern ULO cpuIntegrationGetInstructionTime(void); +extern void cpuIntegrationSetSpeed(ULO speed); +extern ULO cpuIntegrationGetSpeed(void); +extern void cpuIntegrationSetChipCycles(ULO chip_cycles); +extern ULO cpuIntegrationGetChipCycles(void); +extern void cpuIntegrationSetChipSlowdown(ULO chip_slowdown); +extern ULO cpuIntegrationGetChipSlowdown(void); + +extern jmp_buf cpu_integration_exception_buffer; + +// Fellow limecycle events +extern void cpuIntegrationSaveState(FILE *F); +extern void cpuIntegrationLoadState(FILE *F); +extern void cpuIntegrationEmulationStart(void); +extern void cpuIntegrationEmulationStop(void); +extern void cpuIntegrationHardReset(void); +extern void cpuIntegrationStartup(void); +extern void cpuIntegrationShutdown(void); + +#endif diff --git a/cpu/CpuModule.c b/cpu/CpuModule.c new file mode 100644 index 0000000..db33e59 --- /dev/null +++ b/cpu/CpuModule.c @@ -0,0 +1,80 @@ +/* @(#) $Id: CpuModule.c,v 1.7 2012/08/12 16:51:02 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* Initialization of 68000 core */ +/* */ +/* Author: Petter Schau */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ + +#include "defs.h" +#include "CpuModule.h" +#include "fellow.h" +#include "fmem.h" +#include "CpuModule_Internal.h" + +void cpuClearEverything(void) +{ + ULO i,j; + + for (j = 0; j < 2; j++) + for (i = 0; i < 8; i++) + cpuSetReg(j, i, 0); + + cpuSetUspDirect(0); + cpuSetSspDirect(0); + cpuSetMspDirect(0); + cpuSetPC(0); + cpuClearPrefetch(); + cpuSetVbr(0); + cpuSetSR(0); + cpuSetCacr(0); + cpuSetCaar(0); + cpuSetSfc(0); + cpuSetDfc(0); + cpuSetIrqLevel(0); + cpuSetIrqAddress(0); + cpuSetStop(FALSE); + cpuSetInstructionTime(0); + cpuSetOriginalPC(0); + cpuSetInitialPC(0); + cpuSetInitialSP(0); + cpuSetModel(0, 0); // Also sets model-mask + cpuSetCheckPendingInterruptsFunc(NULL); + +#ifdef CPU_INSTRUCTION_LOGGING + cpuSetCurrentOpcode(0); + cpuSetInstructionLoggingFunc(NULL); + cpuSetExceptionLoggingFunc(NULL); + cpuSetInterruptLoggingFunc(NULL); +#endif + + cpuSetMidInstructionExceptionFunc(NULL); + cpuSetResetExceptionFunc(NULL); +} + +void cpuHardReset(void) +{ + cpuThrowResetException(); + cpuSetRaiseInterrupt(FALSE); +} + +void cpuStartup(void) +{ + cpuClearEverything(); +} diff --git a/cpu/CpuModule.h b/cpu/CpuModule.h new file mode 100644 index 0000000..3b04da8 --- /dev/null +++ b/cpu/CpuModule.h @@ -0,0 +1,93 @@ +#ifndef CpuModule_H +#define CpuModule_H + +// This header file defines the internal interfaces of the CPU module. + +#define CPU_INSTRUCTION_LOGGING + +// Function to check if there are any external interrupt sources wanting to issue interrupts +typedef BOOLE (*cpuCheckPendingInterruptsFunc)(void); +extern void cpuSetCheckPendingInterruptsFunc(cpuCheckPendingInterruptsFunc func); +extern void cpuCheckPendingInterrupts(void); +extern void cpuSetUpInterrupt(void); +extern void cpuInitializeFromNewPC(ULO new_pc); + +// Logging interface +#ifdef CPU_INSTRUCTION_LOGGING + +typedef void (*cpuInstructionLoggingFunc)(void); +extern void cpuSetInstructionLoggingFunc(cpuInstructionLoggingFunc func); +typedef void (*cpuExceptionLoggingFunc)(STR *description, ULO original_pc, UWO opcode); +extern void cpuSetExceptionLoggingFunc(cpuExceptionLoggingFunc func); +typedef void (*cpuInterruptLoggingFunc)(ULO level, ULO vector_address); +extern void cpuSetInterruptLoggingFunc(cpuInterruptLoggingFunc func); + +#endif + +// CPU register and control properties +extern void cpuSetPC(ULO pc); +extern ULO cpuGetPC(void); + +extern void cpuSetReg(ULO da, ULO i, ULO value); +extern ULO cpuGetReg(ULO da, ULO i); + +extern void cpuSetDReg(ULO i, ULO value); +extern ULO cpuGetDReg(ULO i); + +extern void cpuSetAReg(ULO i, ULO value); +extern ULO cpuGetAReg(ULO i); + +extern void cpuSetSR(ULO sr); +extern ULO cpuGetSR(void); + +extern void cpuSetUspDirect(ULO usp); +extern ULO cpuGetUspDirect(void); +extern ULO cpuGetUspAutoMap(void); + +extern void cpuSetMspDirect(ULO msp); +extern ULO cpuGetMspDirect(void); + +extern void cpuSetSspDirect(ULO ssp); +extern ULO cpuGetSspDirect(void); +extern ULO cpuGetSspAutoMap(void); + +extern ULO cpuGetVbr(void); + +extern void cpuSetStop(BOOLE stop); +extern BOOLE cpuGetStop(void); + +extern void cpuSetInitialPC(ULO pc); +extern ULO cpuGetInitialPC(void); + +extern void cpuSetInitialSP(ULO sp); +extern ULO cpuGetInitialSP(void); + +extern ULO cpuGetInstructionTime(void); + +extern void cpuSetIrqLevel(ULO irq_level); +extern ULO cpuGetIrqLevel(void); + +extern void cpuSetIrqAddress(ULO irq_address); +extern ULO cpuGetIrqAddress(void); + +extern ULO cpuExecuteInstruction(void); +extern ULO cpuDisOpcode(ULO disasm_pc, STR *saddress, STR *sdata, STR *sinstruction, STR *soperands); + +extern void cpuSaveState(FILE *F); +extern void cpuLoadState(FILE *F); +extern void cpuHardReset(void); +extern void cpuStartup(void); + +typedef void (*cpuMidInstructionExceptionFunc)(void); +extern void cpuSetMidInstructionExceptionFunc(cpuMidInstructionExceptionFunc func); +extern void cpuThrowAddressErrorException(void); + +typedef void (*cpuResetExceptionFunc)(void); +extern void cpuSetResetExceptionFunc(cpuResetExceptionFunc func); + +// Configuration settings +extern void cpuSetModel(ULO major, ULO minor); +extern ULO cpuGetModelMajor(void); +extern ULO cpuGetModelMinor(void); + +#endif \ No newline at end of file diff --git a/cpu/CpuModule_Code.h b/cpu/CpuModule_Code.h new file mode 100644 index 0000000..c5ce164 --- /dev/null +++ b/cpu/CpuModule_Code.h @@ -0,0 +1,12233 @@ +#ifndef CPUMODULE_CODE_H +#define CPUMODULE_CODE_H + +static void ADD_D000(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void ADD_D010(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADD_D018(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADD_D020(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(10); +} +static void ADD_D028(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void ADD_D030(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void ADD_D038(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void ADD_D039(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void ADD_D03A(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void ADD_D03B(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void ADD_D03C(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADD_D040(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void ADD_D048(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void ADD_D050(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADD_D058(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADD_D060(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(10); +} +static void ADD_D068(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void ADD_D070(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void ADD_D078(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void ADD_D079(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void ADD_D07A(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void ADD_D07B(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void ADD_D07C(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADD_D080(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADD_D088(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADD_D090(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void ADD_D098(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void ADD_D0A0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void ADD_D0A8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void ADD_D0B0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void ADD_D0B8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void ADD_D0B9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(22); +} +static void ADD_D0BA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void ADD_D0BB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void ADD_D0BC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void ADD_D110(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void ADD_D118(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void ADD_D120(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void ADD_D128(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADD_D130(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void ADD_D138(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADD_D139(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADD_D150(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void ADD_D158(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void ADD_D160(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void ADD_D168(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADD_D170(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void ADD_D178(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADD_D179(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADD_D190(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADD_D198(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADD_D1A0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void ADD_D1A8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void ADD_D1B0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void ADD_D1B8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void ADD_D1B9(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ADDA_D0C0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)cpuGetDRegWord(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADDA_D0C8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)cpuGetARegWord(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADDA_D0D0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA02(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void ADDA_D0D8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void ADDA_D0E0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void ADDA_D0E8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA05(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void ADDA_D0F0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA06(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void ADDA_D0F8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA70()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void ADDA_D0F9(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA71()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void ADDA_D0FA(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA72()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void ADDA_D0FB(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA73()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void ADDA_D0FC(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)cpuGetNextWord(); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void ADDA_D1C0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADDA_D1C8(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADDA_D1D0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void ADDA_D1D8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void ADDA_D1E0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void ADDA_D1E8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void ADDA_D1F0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void ADDA_D1F8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void ADDA_D1F9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(22); +} +static void ADDA_D1FA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void ADDA_D1FB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void ADDA_D1FC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void ADDI_0600(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void ADDI_0610(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADDI_0618(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADDI_0620(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void ADDI_0628(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADDI_0630(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(22); +} +static void ADDI_0638(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADDI_0639(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(24); +} +static void ADDI_0640(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void ADDI_0650(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADDI_0658(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADDI_0660(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void ADDI_0668(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADDI_0670(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(22); +} +static void ADDI_0678(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADDI_0679(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(24); +} +static void ADDI_0680(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(16); +} +static void ADDI_0690(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ADDI_0698(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ADDI_06A0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(30); +} +static void ADDI_06A8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void ADDI_06B0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(34); +} +static void ADDI_06B8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void ADDI_06B9(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(36); +} +static void ADDQ_5000(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuAddB(dst, src); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void ADDQ_5010(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void ADDQ_5018(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void ADDQ_5020(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void ADDQ_5028(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADDQ_5030(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void ADDQ_5038(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADDQ_5039(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuAddB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADDQ_5040(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuAddW(dst, src); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void ADDQ_5050(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void ADDQ_5058(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void ADDQ_5060(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void ADDQ_5068(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADDQ_5070(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void ADDQ_5078(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ADDQ_5079(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuAddW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADDQ_5080(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuAddL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void ADDQ_5090(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADDQ_5098(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void ADDQ_50A0(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void ADDQ_50A8(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void ADDQ_50B0(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void ADDQ_50B8(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void ADDQ_50B9(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuAddL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ADDQ_5048(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dst = cpuGetAReg(opc_data[0]); + dst = cpuAddaW(dst, src); + cpuSetAReg(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void ADDQ_5088(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dst = cpuGetAReg(opc_data[0]); + dst = cpuAddaL(dst, src); + cpuSetAReg(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void AND_C000(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void AND_C010(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void AND_C018(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void AND_C020(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(10); +} +static void AND_C028(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void AND_C030(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void AND_C038(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void AND_C039(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void AND_C03A(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void AND_C03B(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void AND_C03C(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void AND_C040(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void AND_C050(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void AND_C058(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void AND_C060(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(10); +} +static void AND_C068(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void AND_C070(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void AND_C078(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void AND_C079(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void AND_C07A(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void AND_C07B(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void AND_C07C(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void AND_C080(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void AND_C090(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void AND_C098(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void AND_C0A0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void AND_C0A8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void AND_C0B0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void AND_C0B8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void AND_C0B9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(22); +} +static void AND_C0BA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void AND_C0BB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void AND_C0BC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void AND_C110(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void AND_C118(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void AND_C120(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void AND_C128(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void AND_C130(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void AND_C138(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void AND_C139(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void AND_C150(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void AND_C158(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void AND_C160(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void AND_C168(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void AND_C170(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void AND_C178(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void AND_C179(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void AND_C190(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void AND_C198(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void AND_C1A0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void AND_C1A8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void AND_C1B0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void AND_C1B8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void AND_C1B9(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ANDI_0200(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuAndB(dst, src); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void ANDI_0210(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ANDI_0218(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ANDI_0220(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void ANDI_0228(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void ANDI_0230(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(22); +} +static void ANDI_0238(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void ANDI_0239(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuAndB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(24); +} +static void ANDI_0240(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuAndW(dst, src); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void ANDI_0250(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ANDI_0258(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ANDI_0260(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void ANDI_0268(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void ANDI_0270(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(22); +} +static void ANDI_0278(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void ANDI_0279(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuAndW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(24); +} +static void ANDI_0280(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuAndL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(14); +} +static void ANDI_0290(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ANDI_0298(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ANDI_02A0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(30); +} +static void ANDI_02A8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void ANDI_02B0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(34); +} +static void ANDI_02B8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void ANDI_02B9(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuAndL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(36); +} +static void ANDI_023C(ULO*opc_data) +{ + cpuAndCcrB(); + cpuSetInstructionTime(20); +} +static void ANDI_027C(ULO*opc_data) +{ + cpuAndSrW(); + cpuSetInstructionTime(20); +} +static void EOR_B100(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuEorB(dst, src); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void EOR_B110(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(8); +} +static void EOR_B118(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(8); +} +static void EOR_B120(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(10); +} +static void EOR_B128(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void EOR_B130(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void EOR_B138(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void EOR_B139(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void EOR_B140(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuEorW(dst, src); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void EOR_B150(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(8); +} +static void EOR_B158(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(8); +} +static void EOR_B160(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(10); +} +static void EOR_B168(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void EOR_B170(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void EOR_B178(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void EOR_B179(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void EOR_B180(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuEorL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void EOR_B190(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(16); +} +static void EOR_B198(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(16); +} +static void EOR_B1A0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(18); +} +static void EOR_B1A8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void EOR_B1B0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void EOR_B1B8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void EOR_B1B9(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void EORI_0A00(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuEorB(dst, src); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void EORI_0A10(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void EORI_0A18(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void EORI_0A20(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void EORI_0A28(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void EORI_0A30(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(22); +} +static void EORI_0A38(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void EORI_0A39(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuEorB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(24); +} +static void EORI_0A40(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuEorW(dst, src); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void EORI_0A50(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void EORI_0A58(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void EORI_0A60(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void EORI_0A68(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void EORI_0A70(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(22); +} +static void EORI_0A78(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void EORI_0A79(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuEorW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(24); +} +static void EORI_0A80(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuEorL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(16); +} +static void EORI_0A90(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void EORI_0A98(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void EORI_0AA0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(30); +} +static void EORI_0AA8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void EORI_0AB0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(34); +} +static void EORI_0AB8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void EORI_0AB9(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuEorL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(36); +} +static void EORI_0A3C(ULO*opc_data) +{ + cpuEorCcrB(); + cpuSetInstructionTime(20); +} +static void EORI_0A7C(ULO*opc_data) +{ + cpuEorSrW(); + cpuSetInstructionTime(20); +} +static void OR_8000(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void OR_8010(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void OR_8018(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void OR_8020(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(10); +} +static void OR_8028(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void OR_8030(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void OR_8038(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void OR_8039(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void OR_803A(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void OR_803B(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void OR_803C(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void OR_8040(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void OR_8050(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void OR_8058(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void OR_8060(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(10); +} +static void OR_8068(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void OR_8070(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void OR_8078(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void OR_8079(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void OR_807A(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void OR_807B(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void OR_807C(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void OR_8080(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void OR_8090(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void OR_8098(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void OR_80A0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void OR_80A8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void OR_80B0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void OR_80B8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void OR_80B9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(22); +} +static void OR_80BA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void OR_80BB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void OR_80BC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void OR_8110(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void OR_8118(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void OR_8120(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void OR_8128(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void OR_8130(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void OR_8138(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void OR_8139(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void OR_8150(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void OR_8158(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void OR_8160(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void OR_8168(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void OR_8170(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void OR_8178(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void OR_8179(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void OR_8190(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void OR_8198(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void OR_81A0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void OR_81A8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void OR_81B0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void OR_81B8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void OR_81B9(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ORI_0000(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuOrB(dst, src); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void ORI_0010(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ORI_0018(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void ORI_0020(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void ORI_0028(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void ORI_0030(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(22); +} +static void ORI_0038(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void ORI_0039(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuOrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(24); +} +static void ORI_0040(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuOrW(dst, src); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void ORI_0050(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ORI_0058(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void ORI_0060(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void ORI_0068(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void ORI_0070(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(22); +} +static void ORI_0078(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void ORI_0079(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuOrW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(24); +} +static void ORI_0080(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuOrL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(16); +} +static void ORI_0090(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ORI_0098(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void ORI_00A0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(30); +} +static void ORI_00A8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void ORI_00B0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(34); +} +static void ORI_00B8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void ORI_00B9(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuOrL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(36); +} +static void ORI_003C(ULO*opc_data) +{ + cpuOrCcrB(); + cpuSetInstructionTime(20); +} +static void ORI_007C(ULO*opc_data) +{ + cpuOrSrW(); + cpuSetInstructionTime(20); +} +static void SUB_9000(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void SUB_9010(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUB_9018(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUB_9020(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(10); +} +static void SUB_9028(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void SUB_9030(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void SUB_9038(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void SUB_9039(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void SUB_903A(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void SUB_903B(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void SUB_903C(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUB_9040(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void SUB_9048(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void SUB_9050(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUB_9058(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUB_9060(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(10); +} +static void SUB_9068(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void SUB_9070(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void SUB_9078(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void SUB_9079(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void SUB_907A(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void SUB_907B(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void SUB_907C(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUB_9080(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUB_9088(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUB_9090(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void SUB_9098(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void SUB_90A0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void SUB_90A8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void SUB_90B0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void SUB_90B8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void SUB_90B9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(22); +} +static void SUB_90BA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void SUB_90BB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void SUB_90BC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void SUB_9110(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void SUB_9118(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void SUB_9120(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void SUB_9128(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUB_9130(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void SUB_9138(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUB_9139(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUB_9150(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void SUB_9158(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void SUB_9160(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void SUB_9168(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUB_9170(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void SUB_9178(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUB_9179(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[1]); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUB_9190(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUB_9198(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUB_91A0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void SUB_91A8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void SUB_91B0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void SUB_91B8(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void SUB_91B9(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void SUBA_90C0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)cpuGetDRegWord(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUBA_90C8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)cpuGetARegWord(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUBA_90D0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA02(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void SUBA_90D8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void SUBA_90E0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void SUBA_90E8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA05(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void SUBA_90F0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA06(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void SUBA_90F8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA70()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void SUBA_90F9(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA71()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void SUBA_90FA(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA72()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void SUBA_90FB(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA73()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void SUBA_90FC(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)cpuGetNextWord(); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(12); +} +static void SUBA_91C0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUBA_91C8(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUBA_91D0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void SUBA_91D8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(14); +} +static void SUBA_91E0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void SUBA_91E8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void SUBA_91F0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void SUBA_91F8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void SUBA_91F9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(22); +} +static void SUBA_91FA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(18); +} +static void SUBA_91FB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(20); +} +static void SUBA_91FC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetAReg(opc_data[1]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[1], dst); + cpuSetInstructionTime(16); +} +static void SUBI_0400(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void SUBI_0410(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUBI_0418(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUBI_0420(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void SUBI_0428(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUBI_0430(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(22); +} +static void SUBI_0438(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUBI_0439(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(24); +} +static void SUBI_0440(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void SUBI_0450(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUBI_0458(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUBI_0460(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void SUBI_0468(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUBI_0470(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(22); +} +static void SUBI_0478(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUBI_0479(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(24); +} +static void SUBI_0480(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(16); +} +static void SUBI_0490(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void SUBI_0498(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void SUBI_04A0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(30); +} +static void SUBI_04A8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void SUBI_04B0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(34); +} +static void SUBI_04B8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(32); +} +static void SUBI_04B9(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(36); +} +static void SUBQ_5100(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuSubB(dst, src); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void SUBQ_5110(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void SUBQ_5118(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void SUBQ_5120(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void SUBQ_5128(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUBQ_5130(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void SUBQ_5138(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUBQ_5139(ULO*opc_data) +{ + UBY src = (UBY)opc_data[1]; + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuSubB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUBQ_5140(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuSubW(dst, src); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void SUBQ_5150(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void SUBQ_5158(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void SUBQ_5160(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void SUBQ_5168(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUBQ_5170(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void SUBQ_5178(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void SUBQ_5179(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuSubW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUBQ_5180(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuSubL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void SUBQ_5190(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUBQ_5198(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void SUBQ_51A0(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void SUBQ_51A8(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void SUBQ_51B0(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void SUBQ_51B8(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void SUBQ_51B9(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuSubL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void SUBQ_5148(ULO*opc_data) +{ + UWO src = (UWO)opc_data[1]; + ULO dst = cpuGetAReg(opc_data[0]); + dst = cpuSubaW(dst, src); + cpuSetAReg(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void SUBQ_5188(ULO*opc_data) +{ + ULO src = opc_data[1]; + ULO dst = cpuGetAReg(opc_data[0]); + dst = cpuSubaL(dst, src); + cpuSetAReg(opc_data[0], dst); + cpuSetInstructionTime(8); +} +static void CHK_4180(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(10); +} +static void CHK_4190(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(14); +} +static void CHK_4198(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(14); +} +static void CHK_41A0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(16); +} +static void CHK_41A8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(18); +} +static void CHK_41B0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(20); +} +static void CHK_41B8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(18); +} +static void CHK_41B9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(22); +} +static void CHK_41BA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(18); +} +static void CHK_41BB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(20); +} +static void CHK_41BC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuChkW(dst, src); + cpuSetInstructionTime(14); +} +static void CHK_4100(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(10); +} +static void CHK_4110(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(18); +} +static void CHK_4118(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(18); +} +static void CHK_4120(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(20); +} +static void CHK_4128(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(22); +} +static void CHK_4130(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(24); +} +static void CHK_4138(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(22); +} +static void CHK_4139(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(26); +} +static void CHK_413A(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(22); +} +static void CHK_413B(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(24); +} +static void CHK_413C(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[1]); + cpuChkL(dst, src); + cpuSetInstructionTime(18); +} +static void CMP_B000(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(4); +} +static void CMP_B010(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(8); +} +static void CMP_B018(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(8); +} +static void CMP_B020(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(10); +} +static void CMP_B028(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(12); +} +static void CMP_B030(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(14); +} +static void CMP_B038(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(12); +} +static void CMP_B039(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(16); +} +static void CMP_B03A(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(12); +} +static void CMP_B03B(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(14); +} +static void CMP_B03C(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[1]); + cpuCmpB(dst, src); + cpuSetInstructionTime(8); +} +static void CMP_B040(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(4); +} +static void CMP_B048(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(4); +} +static void CMP_B050(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(8); +} +static void CMP_B058(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(8); +} +static void CMP_B060(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(10); +} +static void CMP_B068(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(12); +} +static void CMP_B070(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(14); +} +static void CMP_B078(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(12); +} +static void CMP_B079(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(16); +} +static void CMP_B07A(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(12); +} +static void CMP_B07B(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(14); +} +static void CMP_B07C(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[1]); + cpuCmpW(dst, src); + cpuSetInstructionTime(8); +} +static void CMP_B080(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(6); +} +static void CMP_B088(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(6); +} +static void CMP_B090(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMP_B098(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMP_B0A0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(16); +} +static void CMP_B0A8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(18); +} +static void CMP_B0B0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(20); +} +static void CMP_B0B8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(18); +} +static void CMP_B0B9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(22); +} +static void CMP_B0BA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(18); +} +static void CMP_B0BB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(20); +} +static void CMP_B0BC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMPA_B0C0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)cpuGetDRegWord(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(6); +} +static void CMPA_B0C8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)cpuGetARegWord(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(6); +} +static void CMPA_B0D0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA02(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(10); +} +static void CMPA_B0D8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(10); +} +static void CMPA_B0E0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(12); +} +static void CMPA_B0E8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA05(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMPA_B0F0(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA06(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(16); +} +static void CMPA_B0F8(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA70()); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMPA_B0F9(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA71()); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(18); +} +static void CMPA_B0FA(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA72()); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMPA_B0FB(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)memoryReadWord(cpuEA73()); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(16); +} +static void CMPA_B0FC(ULO*opc_data) +{ + ULO src = (ULO)(LON)(WOR)cpuGetNextWord(); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(10); +} +static void CMPA_B1C0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(6); +} +static void CMPA_B1C8(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(6); +} +static void CMPA_B1D0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMPA_B1D8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMPA_B1E0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(16); +} +static void CMPA_B1E8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(18); +} +static void CMPA_B1F0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(20); +} +static void CMPA_B1F8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(18); +} +static void CMPA_B1F9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(22); +} +static void CMPA_B1FA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(18); +} +static void CMPA_B1FB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(20); +} +static void CMPA_B1FC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetAReg(opc_data[1]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMPI_0C00(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + UBY dst = cpuGetDRegByte(opc_data[0]); + cpuCmpB(dst, src); + cpuSetInstructionTime(8); +} +static void CMPI_0C10(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuCmpB(dst, src); + cpuSetInstructionTime(12); +} +static void CMPI_0C18(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + cpuCmpB(dst, src); + cpuSetInstructionTime(12); +} +static void CMPI_0C20(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + cpuCmpB(dst, src); + cpuSetInstructionTime(14); +} +static void CMPI_0C28(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuCmpB(dst, src); + cpuSetInstructionTime(16); +} +static void CMPI_0C30(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuCmpB(dst, src); + cpuSetInstructionTime(18); +} +static void CMPI_0C38(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + cpuCmpB(dst, src); + cpuSetInstructionTime(16); +} +static void CMPI_0C39(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + cpuCmpB(dst, src); + cpuSetInstructionTime(20); +} +static void CMPI_0C40(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[0]); + cpuCmpW(dst, src); + cpuSetInstructionTime(8); +} +static void CMPI_0C50(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + cpuCmpW(dst, src); + cpuSetInstructionTime(12); +} +static void CMPI_0C58(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + cpuCmpW(dst, src); + cpuSetInstructionTime(12); +} +static void CMPI_0C60(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + cpuCmpW(dst, src); + cpuSetInstructionTime(14); +} +static void CMPI_0C68(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + cpuCmpW(dst, src); + cpuSetInstructionTime(16); +} +static void CMPI_0C70(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + cpuCmpW(dst, src); + cpuSetInstructionTime(18); +} +static void CMPI_0C78(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + cpuCmpW(dst, src); + cpuSetInstructionTime(16); +} +static void CMPI_0C79(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + cpuCmpW(dst, src); + cpuSetInstructionTime(20); +} +static void CMPI_0C80(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dst = cpuGetDReg(opc_data[0]); + cpuCmpL(dst, src); + cpuSetInstructionTime(14); +} +static void CMPI_0C90(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + cpuCmpL(dst, src); + cpuSetInstructionTime(20); +} +static void CMPI_0C98(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + cpuCmpL(dst, src); + cpuSetInstructionTime(20); +} +static void CMPI_0CA0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + cpuCmpL(dst, src); + cpuSetInstructionTime(22); +} +static void CMPI_0CA8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + cpuCmpL(dst, src); + cpuSetInstructionTime(24); +} +static void CMPI_0CB0(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + cpuCmpL(dst, src); + cpuSetInstructionTime(26); +} +static void CMPI_0CB8(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + cpuCmpL(dst, src); + cpuSetInstructionTime(24); +} +static void CMPI_0CB9(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + cpuCmpL(dst, src); + cpuSetInstructionTime(28); +} +static void CMPI_0C3A(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA72(); + UBY dst = memoryReadByte(dstea); + cpuCmpB(dst, src); + cpuSetInstructionTime(16); +} +static void CMPI_0C3B(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA73(); + UBY dst = memoryReadByte(dstea); + cpuCmpB(dst, src); + cpuSetInstructionTime(18); +} +static void CMPI_0C7A(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA72(); + UWO dst = memoryReadWord(dstea); + cpuCmpW(dst, src); + cpuSetInstructionTime(16); +} +static void CMPI_0C7B(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA73(); + UWO dst = memoryReadWord(dstea); + cpuCmpW(dst, src); + cpuSetInstructionTime(18); +} +static void CMPI_0CBA(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA72(); + ULO dst = memoryReadLong(dstea); + cpuCmpL(dst, src); + cpuSetInstructionTime(24); +} +static void CMPI_0CBB(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA73(); + ULO dst = memoryReadLong(dstea); + cpuCmpL(dst, src); + cpuSetInstructionTime(26); +} +static void BCHG_0150(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(10); +} +static void BCHG_0158(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(10); +} +static void BCHG_0160(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BCHG_0168(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void BCHG_0170(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BCHG_0178(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void BCHG_0179(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void BCHG_0140(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuBchgL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(10 + ((src >= 16) ? 2 : 0)); +} +static void BCHG_0850(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BCHG_0858(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BCHG_0860(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void BCHG_0868(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BCHG_0870(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void BCHG_0878(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BCHG_0879(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuBchgB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void BCHG_0840(ULO*opc_data) +{ + ULO src = (ULO)cpuGetNextWord(); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuBchgL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(12); +} +static void BCLR_0190(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BCLR_0198(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BCLR_01A0(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void BCLR_01A8(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BCLR_01B0(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void BCLR_01B8(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BCLR_01B9(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void BCLR_0180(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuBclrL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(12 + ((src >= 16) ? 2 : 0)); +} +static void BCLR_0890(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BCLR_0898(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BCLR_08A0(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void BCLR_08A8(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BCLR_08B0(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void BCLR_08B8(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BCLR_08B9(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuBclrB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void BCLR_0880(ULO*opc_data) +{ + ULO src = (ULO)cpuGetNextWord(); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuBclrL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(12); +} +static void BSET_01D0(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(10); +} +static void BSET_01D8(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(10); +} +static void BSET_01E0(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BSET_01E8(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void BSET_01F0(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BSET_01F8(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void BSET_01F9(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void BSET_01C0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuBsetL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(10 + ((src >= 16) ? 2 : 0)); +} +static void BSET_08D0(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BSET_08D8(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void BSET_08E0(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void BSET_08E8(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BSET_08F0(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void BSET_08F8(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void BSET_08F9(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuBsetB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void BSET_08C0(ULO*opc_data) +{ + ULO src = (ULO)cpuGetNextWord(); + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuBsetL(dst, src); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(12); +} +static void BTST_0110(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(10); +} +static void BTST_0118(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(10); +} +static void BTST_0120(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(12); +} +static void BTST_0128(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(14); +} +static void BTST_0130(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(16); +} +static void BTST_0138(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(14); +} +static void BTST_0139(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(18); +} +static void BTST_013A(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA72(); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(14); +} +static void BTST_013B(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + ULO dstea = cpuEA73(); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(16); +} +static void BTST_013C(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[1]); + UBY dst = (UBY)cpuGetNextWord(); + cpuBtstB(dst, src); + cpuSetInstructionTime(10); +} +static void BTST_0100(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[1]); + ULO dst = cpuGetDReg(opc_data[0]); + cpuBtstL(dst, src); + cpuSetInstructionTime(10); +} +static void BTST_0810(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(8); +} +static void BTST_0818(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(8); +} +static void BTST_0820(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(10); +} +static void BTST_0828(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(12); +} +static void BTST_0830(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(14); +} +static void BTST_0838(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(12); +} +static void BTST_0839(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(16); +} +static void BTST_083A(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA72(); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(12); +} +static void BTST_083B(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA73(); + UBY dst = memoryReadByte(dstea); + cpuBtstB(dst, src); + cpuSetInstructionTime(14); +} +static void BTST_0800(ULO*opc_data) +{ + ULO src = (ULO)cpuGetNextWord(); + ULO dst = cpuGetDReg(opc_data[0]); + cpuBtstL(dst, src); + cpuSetInstructionTime(8); +} +static void LEA_41D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + cpuSetAReg(opc_data[1], dstea); + cpuSetInstructionTime(4); +} +static void LEA_41E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + cpuSetAReg(opc_data[1], dstea); + cpuSetInstructionTime(8); +} +static void LEA_41F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + cpuSetAReg(opc_data[1], dstea); + cpuSetInstructionTime(12); +} +static void LEA_41F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + cpuSetAReg(opc_data[1], dstea); + cpuSetInstructionTime(8); +} +static void LEA_41F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + cpuSetAReg(opc_data[1], dstea); + cpuSetInstructionTime(12); +} +static void LEA_41FA(ULO*opc_data) +{ + ULO dstea = cpuEA72(); + cpuSetAReg(opc_data[1], dstea); + cpuSetInstructionTime(8); +} +static void LEA_41FB(ULO*opc_data) +{ + ULO dstea = cpuEA73(); + cpuSetAReg(opc_data[1], dstea); + cpuSetInstructionTime(12); +} +static void MULS_C1C0(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 0); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1D0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 4); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1D8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 4); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1E0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 6); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1E8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 8); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1F0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 10); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1F8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 8); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1F9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 12); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1FA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 8); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1FB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 10); + cpuSetDReg(opc_data[1], res); +} +static void MULS_C1FC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMulsW(dst, src, 4); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0C0(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 0); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0D0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 4); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0D8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 4); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0E0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 6); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0E8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 8); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0F0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 10); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0F8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 8); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0F9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 12); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0FA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 8); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0FB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 10); + cpuSetDReg(opc_data[1], res); +} +static void MULU_C0FC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + UWO dst = cpuGetDRegWord(opc_data[1]); + ULO res = cpuMuluW(dst, src, 4); + cpuSetDReg(opc_data[1], res); +} +static void DIVS_81C0(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81D0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81D8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81E0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81E8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81F0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81F8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81F9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81FA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81FB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVS_81FC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivsW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C40(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = cpuGetDReg(opc_data[0]); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C50(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C58(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C60(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C68(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C70(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C78(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA70()); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C79(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA71()); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C7A(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA72()); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C7B(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA73()); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVL_4C7C(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = cpuGetNextLong(); + cpuDivL(src, ext); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80C0(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80D0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80D8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80E0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80E8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80F0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80F8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80F9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80FA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80FB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void DIVU_80FC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dst = cpuGetDReg(opc_data[1]); + ULO res = cpuDivuW(dst, src); + cpuSetDReg(opc_data[1], res); + cpuSetInstructionTime(opc_data[2]); +} +static void MOVEM_48A0(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + cpuMovemwPre(regs, opc_data[0]); +} +static void MOVEM_48E0(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + cpuMovemlPre(regs, opc_data[0]); +} +static void MOVEM_4C98(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + cpuMovemwPost(regs, opc_data[0]); +} +static void MOVEM_4CD8(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + cpuMovemlPost(regs, opc_data[0]); +} +static void MOVEM_4890(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuMovemwR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_48A8(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuMovemwR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_48B0(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuMovemwR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_48B8(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuMovemwR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_48B9(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuMovemwR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_48D0(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuMovemlR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_48E8(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuMovemlR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_48F0(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuMovemlR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_48F8(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuMovemlR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_48F9(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuMovemlR2Ea(regs, dstea, opc_data[1]); +} +static void MOVEM_4C90(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuMovemwEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CA8(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuMovemwEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CB0(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuMovemwEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CB8(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuMovemwEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CB9(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuMovemwEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CBA(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuMovemwEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CBB(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuMovemwEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CD0(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuMovemlEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CE8(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuMovemlEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CF0(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuMovemlEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CF8(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuMovemlEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CF9(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuMovemlEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CFA(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuMovemlEa2R(regs, dstea, opc_data[1]); +} +static void MOVEM_4CFB(ULO*opc_data) +{ + UWO regs = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuMovemlEa2R(regs, dstea, opc_data[1]); +} +static void CLR_4200(ULO*opc_data) +{ + UBY dst = 0; + cpuClr(); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void CLR_4210(ULO*opc_data) +{ + UBY dst = 0; + ULO dstea = cpuEA02(opc_data[0]); + cpuClr(); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void CLR_4218(ULO*opc_data) +{ + UBY dst = 0; + ULO dstea = cpuEA03(opc_data[0], 1); + cpuClr(); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void CLR_4220(ULO*opc_data) +{ + UBY dst = 0; + ULO dstea = cpuEA04(opc_data[0], 1); + cpuClr(); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void CLR_4228(ULO*opc_data) +{ + UBY dst = 0; + ULO dstea = cpuEA05(opc_data[0]); + cpuClr(); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void CLR_4230(ULO*opc_data) +{ + UBY dst = 0; + ULO dstea = cpuEA06(opc_data[0]); + cpuClr(); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void CLR_4238(ULO*opc_data) +{ + UBY dst = 0; + ULO dstea = cpuEA70(); + cpuClr(); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void CLR_4239(ULO*opc_data) +{ + UBY dst = 0; + ULO dstea = cpuEA71(); + cpuClr(); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void CLR_4240(ULO*opc_data) +{ + UWO dst = 0; + cpuClr(); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void CLR_4250(ULO*opc_data) +{ + UWO dst = 0; + ULO dstea = cpuEA02(opc_data[0]); + cpuClr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void CLR_4258(ULO*opc_data) +{ + UWO dst = 0; + ULO dstea = cpuEA03(opc_data[0], 2); + cpuClr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void CLR_4260(ULO*opc_data) +{ + UWO dst = 0; + ULO dstea = cpuEA04(opc_data[0], 2); + cpuClr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void CLR_4268(ULO*opc_data) +{ + UWO dst = 0; + ULO dstea = cpuEA05(opc_data[0]); + cpuClr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void CLR_4270(ULO*opc_data) +{ + UWO dst = 0; + ULO dstea = cpuEA06(opc_data[0]); + cpuClr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void CLR_4278(ULO*opc_data) +{ + UWO dst = 0; + ULO dstea = cpuEA70(); + cpuClr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void CLR_4279(ULO*opc_data) +{ + UWO dst = 0; + ULO dstea = cpuEA71(); + cpuClr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void CLR_4280(ULO*opc_data) +{ + ULO dst = 0; + cpuClr(); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(6); +} +static void CLR_4290(ULO*opc_data) +{ + ULO dst = 0; + ULO dstea = cpuEA02(opc_data[0]); + cpuClr(); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void CLR_4298(ULO*opc_data) +{ + ULO dst = 0; + ULO dstea = cpuEA03(opc_data[0], 4); + cpuClr(); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void CLR_42A0(ULO*opc_data) +{ + ULO dst = 0; + ULO dstea = cpuEA04(opc_data[0], 4); + cpuClr(); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void CLR_42A8(ULO*opc_data) +{ + ULO dst = 0; + ULO dstea = cpuEA05(opc_data[0]); + cpuClr(); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void CLR_42B0(ULO*opc_data) +{ + ULO dst = 0; + ULO dstea = cpuEA06(opc_data[0]); + cpuClr(); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void CLR_42B8(ULO*opc_data) +{ + ULO dst = 0; + ULO dstea = cpuEA70(); + cpuClr(); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void CLR_42B9(ULO*opc_data) +{ + ULO dst = 0; + ULO dstea = cpuEA71(); + cpuClr(); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void BFCHG_EAD0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuBfChgEa(dstea, ext); +} +static void BFCHG_EAE8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuBfChgEa(dstea, ext); +} +static void BFCHG_EAF0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuBfChgEa(dstea, ext); +} +static void BFCHG_EAF8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuBfChgEa(dstea, ext); +} +static void BFCHG_EAF9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuBfChgEa(dstea, ext); +} +static void BFCLR_ECD0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuBfClrEa(dstea, ext); +} +static void BFCLR_ECE8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuBfClrEa(dstea, ext); +} +static void BFCLR_ECF0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuBfClrEa(dstea, ext); +} +static void BFCLR_ECF8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuBfClrEa(dstea, ext); +} +static void BFCLR_ECF9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuBfClrEa(dstea, ext); +} +static void BFEXTS_EBD0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuBfExtsEa(dstea, ext); +} +static void BFEXTS_EBE8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuBfExtsEa(dstea, ext); +} +static void BFEXTS_EBF0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuBfExtsEa(dstea, ext); +} +static void BFEXTS_EBF8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuBfExtsEa(dstea, ext); +} +static void BFEXTS_EBF9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuBfExtsEa(dstea, ext); +} +static void BFEXTS_EBFA(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuBfExtsEa(dstea, ext); +} +static void BFEXTS_EBFB(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuBfExtsEa(dstea, ext); +} +static void BFEXTU_E9D0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuBfExtuEa(dstea, ext); +} +static void BFEXTU_E9E8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuBfExtuEa(dstea, ext); +} +static void BFEXTU_E9F0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuBfExtuEa(dstea, ext); +} +static void BFEXTU_E9F8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuBfExtuEa(dstea, ext); +} +static void BFEXTU_E9F9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuBfExtuEa(dstea, ext); +} +static void BFEXTU_E9FA(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuBfExtuEa(dstea, ext); +} +static void BFEXTU_E9FB(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuBfExtuEa(dstea, ext); +} +static void BFFFO_EDD0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuBfFfoEa(dstea, ext); +} +static void BFFFO_EDE8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuBfFfoEa(dstea, ext); +} +static void BFFFO_EDF0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuBfFfoEa(dstea, ext); +} +static void BFFFO_EDF8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuBfFfoEa(dstea, ext); +} +static void BFFFO_EDF9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuBfFfoEa(dstea, ext); +} +static void BFFFO_EDFA(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuBfFfoEa(dstea, ext); +} +static void BFFFO_EDFB(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuBfFfoEa(dstea, ext); +} +static void BFINS_EFD0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuBfInsEa(dstea, ext); +} +static void BFINS_EFE8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuBfInsEa(dstea, ext); +} +static void BFINS_EFF0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuBfInsEa(dstea, ext); +} +static void BFINS_EFF8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuBfInsEa(dstea, ext); +} +static void BFINS_EFF9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuBfInsEa(dstea, ext); +} +static void BFSET_EED0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuBfSetEa(dstea, ext); +} +static void BFSET_EEE8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuBfSetEa(dstea, ext); +} +static void BFSET_EEF0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuBfSetEa(dstea, ext); +} +static void BFSET_EEF8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuBfSetEa(dstea, ext); +} +static void BFSET_EEF9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuBfSetEa(dstea, ext); +} +static void BFTST_E8D0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuBfTstEa(dstea, ext); +} +static void BFTST_E8E8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuBfTstEa(dstea, ext); +} +static void BFTST_E8F0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuBfTstEa(dstea, ext); +} +static void BFTST_E8F8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuBfTstEa(dstea, ext); +} +static void BFTST_E8F9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuBfTstEa(dstea, ext); +} +static void BFTST_E8FA(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuBfTstEa(dstea, ext); +} +static void BFTST_E8FB(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuBfTstEa(dstea, ext); +} +static void BFCHG_EAC0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + cpuBfChgReg(opc_data[1], ext); +} +static void BFCLR_ECC0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + cpuBfClrReg(opc_data[1], ext); +} +static void BFEXTS_EBC0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + cpuBfExtsReg(opc_data[1], ext); +} +static void BFEXTU_E9C0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + cpuBfExtuReg(opc_data[1], ext); +} +static void BFFFO_EDC0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + cpuBfFfoReg(opc_data[1], ext); +} +static void BFINS_EFC0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + cpuBfInsReg(opc_data[1], ext); +} +static void BFSET_EEC0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + cpuBfSetReg(opc_data[1], ext); +} +static void BFTST_E8C0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + cpuBfTstReg(opc_data[1], ext); +} +static void MULL_4C00(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = cpuGetDReg(opc_data[0]); + cpuMulL(src, ext); +} +static void MULL_4C10(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + cpuMulL(src, ext); +} +static void MULL_4C18(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + cpuMulL(src, ext); +} +static void MULL_4C20(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + cpuMulL(src, ext); +} +static void MULL_4C28(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + cpuMulL(src, ext); +} +static void MULL_4C30(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + cpuMulL(src, ext); +} +static void MULL_4C38(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA70()); + cpuMulL(src, ext); +} +static void MULL_4C39(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA71()); + cpuMulL(src, ext); +} +static void MULL_4C3A(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA72()); + cpuMulL(src, ext); +} +static void MULL_4C3B(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA73()); + cpuMulL(src, ext); +} +static void MULL_4C3C(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = cpuGetNextLong(); + cpuMulL(src, ext); +} +static void MOVES_0E10(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + cpuMoveSB(src, ext); +} +static void MOVES_0E18(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + cpuMoveSB(src, ext); +} +static void MOVES_0E20(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + cpuMoveSB(src, ext); +} +static void MOVES_0E28(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + cpuMoveSB(src, ext); +} +static void MOVES_0E30(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + cpuMoveSB(src, ext); +} +static void MOVES_0E38(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UBY src = memoryReadByte(cpuEA70()); + cpuMoveSB(src, ext); +} +static void MOVES_0E39(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UBY src = memoryReadByte(cpuEA71()); + cpuMoveSB(src, ext); +} +static void MOVES_0E50(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + cpuMoveSW(src, ext); +} +static void MOVES_0E58(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + cpuMoveSW(src, ext); +} +static void MOVES_0E60(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + cpuMoveSW(src, ext); +} +static void MOVES_0E68(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + cpuMoveSW(src, ext); +} +static void MOVES_0E70(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + cpuMoveSW(src, ext); +} +static void MOVES_0E78(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UWO src = memoryReadWord(cpuEA70()); + cpuMoveSW(src, ext); +} +static void MOVES_0E79(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + UWO src = memoryReadWord(cpuEA71()); + cpuMoveSW(src, ext); +} +static void MOVES_0E90(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + cpuMoveSL(src, ext); +} +static void MOVES_0E98(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + cpuMoveSL(src, ext); +} +static void MOVES_0EA0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + cpuMoveSL(src, ext); +} +static void MOVES_0EA8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + cpuMoveSL(src, ext); +} +static void MOVES_0EB0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + cpuMoveSL(src, ext); +} +static void MOVES_0EB8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA70()); + cpuMoveSL(src, ext); +} +static void MOVES_0EB9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO src = memoryReadLong(cpuEA71()); + cpuMoveSL(src, ext); +} +static void NBCD_4800(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuNbcdB(dst); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(6); +} +static void NBCD_4810(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNbcdB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void NBCD_4818(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuNbcdB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void NBCD_4820(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuNbcdB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void NBCD_4828(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNbcdB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void NBCD_4830(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNbcdB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void NBCD_4838(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuNbcdB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void NBCD_4839(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuNbcdB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void NEG_4400(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuNegB(dst); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void NEG_4410(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNegB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void NEG_4418(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuNegB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void NEG_4420(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuNegB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void NEG_4428(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNegB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void NEG_4430(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNegB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void NEG_4438(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuNegB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void NEG_4439(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuNegB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void NEG_4440(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuNegW(dst); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void NEG_4450(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuNegW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void NEG_4458(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuNegW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void NEG_4460(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuNegW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void NEG_4468(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuNegW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void NEG_4470(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuNegW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void NEG_4478(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuNegW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void NEG_4479(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuNegW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void NEG_4480(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuNegL(dst); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(6); +} +static void NEG_4490(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuNegL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void NEG_4498(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuNegL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void NEG_44A0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuNegL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void NEG_44A8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuNegL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void NEG_44B0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuNegL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void NEG_44B8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuNegL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void NEG_44B9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuNegL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void NEGX_4000(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuNegxB(dst); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void NEGX_4010(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNegxB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void NEGX_4018(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuNegxB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void NEGX_4020(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuNegxB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void NEGX_4028(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNegxB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void NEGX_4030(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNegxB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void NEGX_4038(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuNegxB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void NEGX_4039(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuNegxB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void NEGX_4040(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuNegxW(dst); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void NEGX_4050(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuNegxW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void NEGX_4058(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuNegxW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void NEGX_4060(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuNegxW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void NEGX_4068(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuNegxW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void NEGX_4070(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuNegxW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void NEGX_4078(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuNegxW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void NEGX_4079(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuNegxW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void NEGX_4080(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuNegxL(dst); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(6); +} +static void NEGX_4090(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuNegxL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void NEGX_4098(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuNegxL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void NEGX_40A0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuNegxL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void NEGX_40A8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuNegxL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void NEGX_40B0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuNegxL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void NEGX_40B8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuNegxL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void NEGX_40B9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuNegxL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void NOT_4600(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuNotB(dst); + cpuSetDRegByte(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void NOT_4610(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNotB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void NOT_4618(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuNotB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void NOT_4620(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuNotB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void NOT_4628(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNotB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void NOT_4630(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuNotB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void NOT_4638(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuNotB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void NOT_4639(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuNotB(dst); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void NOT_4640(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuNotW(dst); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(4); +} +static void NOT_4650(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuNotW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void NOT_4658(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuNotW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void NOT_4660(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuNotW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void NOT_4668(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuNotW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void NOT_4670(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuNotW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void NOT_4678(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuNotW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void NOT_4679(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuNotW(dst); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void NOT_4680(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuNotL(dst); + cpuSetDReg(opc_data[0], dst); + cpuSetInstructionTime(6); +} +static void NOT_4690(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuNotL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void NOT_4698(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuNotL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(20); +} +static void NOT_46A0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuNotL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(22); +} +static void NOT_46A8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuNotL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void NOT_46B0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + dst = cpuNotL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(26); +} +static void NOT_46B8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + dst = cpuNotL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(24); +} +static void NOT_46B9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + dst = cpuNotL(dst); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(28); +} +static void TAS_4AC0(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuTas(dst); + cpuSetDRegByte(opc_data[0], dst); +} +static void TAS_4AD0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuTas(dst); + memoryWriteByte(dst, dstea); +} +static void TAS_4AD8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuTas(dst); + memoryWriteByte(dst, dstea); +} +static void TAS_4AE0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuTas(dst); + memoryWriteByte(dst, dstea); +} +static void TAS_4AE8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuTas(dst); + memoryWriteByte(dst, dstea); +} +static void TAS_4AF0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + dst = cpuTas(dst); + memoryWriteByte(dst, dstea); +} +static void TAS_4AF8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + dst = cpuTas(dst); + memoryWriteByte(dst, dstea); +} +static void TAS_4AF9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + dst = cpuTas(dst); + memoryWriteByte(dst, dstea); +} +static void TST_4A00(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + cpuTestB(dst); + cpuSetInstructionTime(4); +} +static void TST_4A10(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuTestB(dst); + cpuSetInstructionTime(8); +} +static void TST_4A18(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + cpuTestB(dst); + cpuSetInstructionTime(8); +} +static void TST_4A20(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = memoryReadByte(dstea); + cpuTestB(dst); + cpuSetInstructionTime(10); +} +static void TST_4A28(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuTestB(dst); + cpuSetInstructionTime(12); +} +static void TST_4A30(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = memoryReadByte(dstea); + cpuTestB(dst); + cpuSetInstructionTime(14); +} +static void TST_4A38(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UBY dst = memoryReadByte(dstea); + cpuTestB(dst); + cpuSetInstructionTime(12); +} +static void TST_4A39(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UBY dst = memoryReadByte(dstea); + cpuTestB(dst); + cpuSetInstructionTime(16); +} +static void TST_4A40(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + cpuTestW(dst); + cpuSetInstructionTime(4); +} +static void TST_4A50(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + cpuTestW(dst); + cpuSetInstructionTime(8); +} +static void TST_4A58(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + cpuTestW(dst); + cpuSetInstructionTime(8); +} +static void TST_4A60(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + cpuTestW(dst); + cpuSetInstructionTime(10); +} +static void TST_4A68(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + cpuTestW(dst); + cpuSetInstructionTime(12); +} +static void TST_4A70(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + cpuTestW(dst); + cpuSetInstructionTime(14); +} +static void TST_4A78(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + cpuTestW(dst); + cpuSetInstructionTime(12); +} +static void TST_4A79(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + cpuTestW(dst); + cpuSetInstructionTime(16); +} +static void TST_4A80(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + cpuTestL(dst); + cpuSetInstructionTime(4); +} +static void TST_4A90(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + ULO dst = memoryReadLong(dstea); + cpuTestL(dst); + cpuSetInstructionTime(12); +} +static void TST_4A98(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + cpuTestL(dst); + cpuSetInstructionTime(12); +} +static void TST_4AA0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 4); + ULO dst = memoryReadLong(dstea); + cpuTestL(dst); + cpuSetInstructionTime(14); +} +static void TST_4AA8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + ULO dst = memoryReadLong(dstea); + cpuTestL(dst); + cpuSetInstructionTime(16); +} +static void TST_4AB0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + ULO dst = memoryReadLong(dstea); + cpuTestL(dst); + cpuSetInstructionTime(18); +} +static void TST_4AB8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + ULO dst = memoryReadLong(dstea); + cpuTestL(dst); + cpuSetInstructionTime(16); +} +static void TST_4AB9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + ULO dst = memoryReadLong(dstea); + cpuTestL(dst); + cpuSetInstructionTime(20); +} +static void TST_4A3A(ULO*opc_data) +{ + ULO dstea = cpuEA72(); + UBY dst = memoryReadByte(dstea); + cpuTestB(dst); + cpuSetInstructionTime(12); +} +static void TST_4A3B(ULO*opc_data) +{ + ULO dstea = cpuEA73(); + UBY dst = memoryReadByte(dstea); + cpuTestB(dst); + cpuSetInstructionTime(14); +} +static void TST_4A3C(ULO*opc_data) +{ + UBY dst = (UBY)cpuGetNextWord(); + cpuTestB(dst); + cpuSetInstructionTime(8); +} +static void TST_4A48(ULO*opc_data) +{ + UWO dst = (UWO)cpuGetAReg(opc_data[0]); + cpuTestW(dst); + cpuSetInstructionTime(4); +} +static void TST_4A7A(ULO*opc_data) +{ + ULO dstea = cpuEA72(); + UWO dst = memoryReadWord(dstea); + cpuTestW(dst); + cpuSetInstructionTime(12); +} +static void TST_4A7B(ULO*opc_data) +{ + ULO dstea = cpuEA73(); + UWO dst = memoryReadWord(dstea); + cpuTestW(dst); + cpuSetInstructionTime(14); +} +static void TST_4A7C(ULO*opc_data) +{ + UWO dst = cpuGetNextWord(); + cpuTestW(dst); + cpuSetInstructionTime(8); +} +static void TST_4A88(ULO*opc_data) +{ + ULO dst = cpuGetAReg(opc_data[0]); + cpuTestL(dst); + cpuSetInstructionTime(4); +} +static void TST_4ABA(ULO*opc_data) +{ + ULO dstea = cpuEA72(); + ULO dst = memoryReadLong(dstea); + cpuTestL(dst); + cpuSetInstructionTime(16); +} +static void TST_4ABB(ULO*opc_data) +{ + ULO dstea = cpuEA73(); + ULO dst = memoryReadLong(dstea); + cpuTestL(dst); + cpuSetInstructionTime(18); +} +static void TST_4ABC(ULO*opc_data) +{ + ULO dst = cpuGetNextLong(); + cpuTestL(dst); + cpuSetInstructionTime(12); +} +static void PEA_4850(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + cpuPeaL(dstea); + cpuSetInstructionTime(8); +} +static void PEA_4868(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + cpuPeaL(dstea); + cpuSetInstructionTime(10); +} +static void PEA_4870(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + cpuPeaL(dstea); + cpuSetInstructionTime(14); +} +static void PEA_4878(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + cpuPeaL(dstea); + cpuSetInstructionTime(10); +} +static void PEA_4879(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + cpuPeaL(dstea); + cpuSetInstructionTime(12); +} +static void PEA_487A(ULO*opc_data) +{ + ULO dstea = cpuEA72(); + cpuPeaL(dstea); + cpuSetInstructionTime(10); +} +static void PEA_487B(ULO*opc_data) +{ + ULO dstea = cpuEA73(); + cpuPeaL(dstea); + cpuSetInstructionTime(14); +} +static void JMP_4ED0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + cpuJmp(dstea); + cpuSetInstructionTime(8); +} +static void JMP_4EE8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + cpuJmp(dstea); + cpuSetInstructionTime(10); +} +static void JMP_4EF0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + cpuJmp(dstea); + cpuSetInstructionTime(14); +} +static void JMP_4EF8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + cpuJmp(dstea); + cpuSetInstructionTime(10); +} +static void JMP_4EF9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + cpuJmp(dstea); + cpuSetInstructionTime(12); +} +static void JMP_4EFA(ULO*opc_data) +{ + ULO dstea = cpuEA72(); + cpuJmp(dstea); + cpuSetInstructionTime(10); +} +static void JMP_4EFB(ULO*opc_data) +{ + ULO dstea = cpuEA73(); + cpuJmp(dstea); + cpuSetInstructionTime(14); +} +static void JSR_4E90(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + cpuJsr(dstea); + cpuSetInstructionTime(16); +} +static void JSR_4EA8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + cpuJsr(dstea); + cpuSetInstructionTime(18); +} +static void JSR_4EB0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + cpuJsr(dstea); + cpuSetInstructionTime(22); +} +static void JSR_4EB8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + cpuJsr(dstea); + cpuSetInstructionTime(18); +} +static void JSR_4EB9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + cpuJsr(dstea); + cpuSetInstructionTime(20); +} +static void JSR_4EBA(ULO*opc_data) +{ + ULO dstea = cpuEA72(); + cpuJsr(dstea); + cpuSetInstructionTime(18); +} +static void JSR_4EBB(ULO*opc_data) +{ + ULO dstea = cpuEA73(); + cpuJsr(dstea); + cpuSetInstructionTime(22); +} +static void MOVETOSR_46C0(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + cpuMoveToSr(src); + cpuSetInstructionTime(12); +} +static void MOVETOSR_46D0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + cpuMoveToSr(src); + cpuSetInstructionTime(16); +} +static void MOVETOSR_46D8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + cpuMoveToSr(src); + cpuSetInstructionTime(16); +} +static void MOVETOSR_46E0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + cpuMoveToSr(src); + cpuSetInstructionTime(18); +} +static void MOVETOSR_46E8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + cpuMoveToSr(src); + cpuSetInstructionTime(20); +} +static void MOVETOSR_46F0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + cpuMoveToSr(src); + cpuSetInstructionTime(22); +} +static void MOVETOSR_46F8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + cpuMoveToSr(src); + cpuSetInstructionTime(20); +} +static void MOVETOSR_46F9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + cpuMoveToSr(src); + cpuSetInstructionTime(24); +} +static void MOVETOSR_46FA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + cpuMoveToSr(src); + cpuSetInstructionTime(20); +} +static void MOVETOSR_46FB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + cpuMoveToSr(src); + cpuSetInstructionTime(22); +} +static void MOVETOSR_46FC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + cpuMoveToSr(src); + cpuSetInstructionTime(16); +} +static void MOVETOCCR_44C0(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + cpuMoveToCcr(src); + cpuSetInstructionTime(12); +} +static void MOVETOCCR_44D0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + cpuMoveToCcr(src); + cpuSetInstructionTime(16); +} +static void MOVETOCCR_44D8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + cpuMoveToCcr(src); + cpuSetInstructionTime(16); +} +static void MOVETOCCR_44E0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + cpuMoveToCcr(src); + cpuSetInstructionTime(18); +} +static void MOVETOCCR_44E8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + cpuMoveToCcr(src); + cpuSetInstructionTime(20); +} +static void MOVETOCCR_44F0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + cpuMoveToCcr(src); + cpuSetInstructionTime(22); +} +static void MOVETOCCR_44F8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + cpuMoveToCcr(src); + cpuSetInstructionTime(20); +} +static void MOVETOCCR_44F9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + cpuMoveToCcr(src); + cpuSetInstructionTime(24); +} +static void MOVETOCCR_44FA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + cpuMoveToCcr(src); + cpuSetInstructionTime(20); +} +static void MOVETOCCR_44FB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + cpuMoveToCcr(src); + cpuSetInstructionTime(22); +} +static void MOVETOCCR_44FC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + cpuMoveToCcr(src); + cpuSetInstructionTime(16); +} +static void SCC_50C0(ULO*opc_data) +{ + UBY dst = cpuScc(opc_data[1]); + cpuSetDRegByte(opc_data[0], dst); + if (dst == 0) + { + cpuSetInstructionTime(4); + } + else + { + cpuSetInstructionTime(6); + } +} +static void SCC_50D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UBY dst = cpuScc(opc_data[1]); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void SCC_50D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 1); + UBY dst = cpuScc(opc_data[1]); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(12); +} +static void SCC_50E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 1); + UBY dst = cpuScc(opc_data[1]); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(14); +} +static void SCC_50E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UBY dst = cpuScc(opc_data[1]); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void SCC_50F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UBY dst = cpuScc(opc_data[1]); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void SCC_50F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UBY dst = cpuScc(opc_data[1]); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(16); +} +static void SCC_50F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UBY dst = cpuScc(opc_data[1]); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(20); +} +static void MOVEFROMCCR_42C0(ULO*opc_data) +{ + UWO dst = cpuMoveFromCcr(); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(6); +} +static void MOVEFROMCCR_42D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = cpuMoveFromCcr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void MOVEFROMCCR_42D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = cpuMoveFromCcr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void MOVEFROMCCR_42E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = cpuMoveFromCcr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void MOVEFROMCCR_42E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = cpuMoveFromCcr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void MOVEFROMCCR_42F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = cpuMoveFromCcr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void MOVEFROMCCR_42F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = cpuMoveFromCcr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void MOVEFROMCCR_42F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = cpuMoveFromCcr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void MOVEFROMSR_40C0(ULO*opc_data) +{ + UWO dst = cpuMoveFromSr(); + cpuSetDRegWord(opc_data[0], dst); + cpuSetInstructionTime(6); +} +static void MOVEFROMSR_40D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = cpuMoveFromSr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void MOVEFROMSR_40D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = cpuMoveFromSr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(12); +} +static void MOVEFROMSR_40E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = cpuMoveFromSr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(14); +} +static void MOVEFROMSR_40E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = cpuMoveFromSr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void MOVEFROMSR_40F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = cpuMoveFromSr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void MOVEFROMSR_40F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = cpuMoveFromSr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(16); +} +static void MOVEFROMSR_40F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = cpuMoveFromSr(); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(20); +} +static void CAS_0AD0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuCasB(dstea, ext); +} +static void CAS_0AD8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 1); + cpuCasB(dstea, ext); +} +static void CAS_0AE0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 1); + cpuCasB(dstea, ext); +} +static void CAS_0AE8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuCasB(dstea, ext); +} +static void CAS_0AF0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuCasB(dstea, ext); +} +static void CAS_0AF8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuCasB(dstea, ext); +} +static void CAS_0AF9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuCasB(dstea, ext); +} +static void CAS_0CD0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuCasW(dstea, ext); +} +static void CAS_0CD8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 2); + cpuCasW(dstea, ext); +} +static void CAS_0CE0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 2); + cpuCasW(dstea, ext); +} +static void CAS_0CE8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuCasW(dstea, ext); +} +static void CAS_0CF0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuCasW(dstea, ext); +} +static void CAS_0CF8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuCasW(dstea, ext); +} +static void CAS_0CF9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuCasW(dstea, ext); +} +static void CAS_0ED0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuCasL(dstea, ext); +} +static void CAS_0ED8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[0], 4); + cpuCasL(dstea, ext); +} +static void CAS_0EE0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[0], 4); + cpuCasL(dstea, ext); +} +static void CAS_0EE8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuCasL(dstea, ext); +} +static void CAS_0EF0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuCasL(dstea, ext); +} +static void CAS_0EF8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuCasL(dstea, ext); +} +static void CAS_0EF9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuCasL(dstea, ext); +} +static void CHKCMP2_00D0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuChkCmp2B(dstea, ext); +} +static void CHKCMP2_00E8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuChkCmp2B(dstea, ext); +} +static void CHKCMP2_00F0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuChkCmp2B(dstea, ext); +} +static void CHKCMP2_00F8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuChkCmp2B(dstea, ext); +} +static void CHKCMP2_00F9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuChkCmp2B(dstea, ext); +} +static void CHKCMP2_00FA(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuChkCmp2B(dstea, ext); +} +static void CHKCMP2_00FB(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuChkCmp2B(dstea, ext); +} +static void CHKCMP2_02D0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuChkCmp2W(dstea, ext); +} +static void CHKCMP2_02E8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuChkCmp2W(dstea, ext); +} +static void CHKCMP2_02F0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuChkCmp2W(dstea, ext); +} +static void CHKCMP2_02F8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuChkCmp2W(dstea, ext); +} +static void CHKCMP2_02F9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuChkCmp2W(dstea, ext); +} +static void CHKCMP2_02FA(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuChkCmp2W(dstea, ext); +} +static void CHKCMP2_02FB(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuChkCmp2W(dstea, ext); +} +static void CHKCMP2_04D0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuChkCmp2L(dstea, ext); +} +static void CHKCMP2_04E8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuChkCmp2L(dstea, ext); +} +static void CHKCMP2_04F0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuChkCmp2L(dstea, ext); +} +static void CHKCMP2_04F8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuChkCmp2L(dstea, ext); +} +static void CHKCMP2_04F9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuChkCmp2L(dstea, ext); +} +static void CHKCMP2_04FA(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuChkCmp2L(dstea, ext); +} +static void CHKCMP2_04FB(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuChkCmp2L(dstea, ext); +} +static void CALLM_06D0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuCallm(dstea, ext); +} +static void CALLM_06E8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuCallm(dstea, ext); +} +static void CALLM_06F0(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuCallm(dstea, ext); +} +static void CALLM_06F8(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuCallm(dstea, ext); +} +static void CALLM_06F9(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuCallm(dstea, ext); +} +static void CALLM_06FA(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA72(); + cpuCallm(dstea, ext); +} +static void CALLM_06FB(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA73(); + cpuCallm(dstea, ext); +} +static void PFLUSH030_F010(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[0]); + cpuPflush030(dstea, ext); +} +static void PFLUSH030_F028(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[0]); + cpuPflush030(dstea, ext); +} +static void PFLUSH030_F030(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[0]); + cpuPflush030(dstea, ext); +} +static void PFLUSH030_F038(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuPflush030(dstea, ext); +} +static void PFLUSH030_F039(ULO*opc_data) +{ + UWO ext = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuPflush030(dstea, ext); +} +static void MOVEQ_7000(ULO*opc_data) +{ + cpuSetDReg(opc_data[0], opc_data[1]); + cpuSetFlagsAbs((UWO)opc_data[2]); + cpuSetInstructionTime(4); +} +static void MOVE_1000(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(4); +} +static void MOVE_1008(ULO*opc_data) +{ + UBY src = cpuGetARegByte(opc_data[0]); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(4); +} +static void MOVE_1010(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(8); +} +static void MOVE_1018(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(8); +} +static void MOVE_1020(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(10); +} +static void MOVE_1028(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVE_1030(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(14); +} +static void MOVE_1038(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVE_1039(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(16); +} +static void MOVE_103A(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVE_103B(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(14); +} +static void MOVE_103C(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + cpuMoveB(src); + cpuSetDRegByte(opc_data[1], src); + cpuSetInstructionTime(8); +} +static void MOVE_1080(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_1088(ULO*opc_data) +{ + UBY src = cpuGetARegByte(opc_data[0]); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_1090(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_1098(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_10A0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_10A8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_10B0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_10B8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_10B9(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_10BA(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_10BB(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_10BC(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_10C0(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_10C8(ULO*opc_data) +{ + UBY src = cpuGetARegByte(opc_data[0]); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_10D0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_10D8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_10E0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_10E8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_10F0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_10F8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_10F9(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_10FA(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_10FB(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_10FC(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_1100(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_1108(ULO*opc_data) +{ + UBY src = cpuGetARegByte(opc_data[0]); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_1110(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_1118(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_1120(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_1128(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_1130(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_1138(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_1139(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_113A(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_113B(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_113C(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[1], 1); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_1140(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_1148(ULO*opc_data) +{ + UBY src = cpuGetARegByte(opc_data[0]); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_1150(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_1158(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_1160(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_1168(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_1170(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_1178(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_1179(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_117A(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_117B(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_117C(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_1180(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_1188(ULO*opc_data) +{ + UBY src = cpuGetARegByte(opc_data[0]); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_1190(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_1198(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_11A0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_11A8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_11B0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_11B8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_11B9(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_11BA(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_11BB(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_11BC(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_11C0(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_11C8(ULO*opc_data) +{ + UBY src = cpuGetARegByte(opc_data[0]); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_11D0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_11D8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_11E0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_11E8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_11F0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_11F8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_11F9(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_11FA(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_11FB(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_11FC(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_13C0(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_13C8(ULO*opc_data) +{ + UBY src = cpuGetARegByte(opc_data[0]); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_13D0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA02(opc_data[0])); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_13D8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA03(opc_data[0],1)); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_13E0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_13E8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA05(opc_data[0])); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_13F0(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA06(opc_data[0])); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_13F8(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA70()); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_13F9(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA71()); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_13FA(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA72()); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_13FB(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA73()); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_13FC(ULO*opc_data) +{ + UBY src = (UBY)cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuMoveB(src); + memoryWriteByte(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_3000(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(4); +} +static void MOVE_3008(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(4); +} +static void MOVE_3010(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(8); +} +static void MOVE_3018(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(8); +} +static void MOVE_3020(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(10); +} +static void MOVE_3028(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVE_3030(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(14); +} +static void MOVE_3038(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVE_3039(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(16); +} +static void MOVE_303A(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVE_303B(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(14); +} +static void MOVE_303C(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + cpuMoveW(src); + cpuSetDRegWord(opc_data[1], src); + cpuSetInstructionTime(8); +} +static void MOVE_3080(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_3088(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_3090(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_3098(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_30A0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_30A8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_30B0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_30B8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_30B9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_30BA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_30BB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_30BC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_30C0(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_30C8(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_30D0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_30D8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_30E0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_30E8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_30F0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_30F8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_30F9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_30FA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_30FB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_30FC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA03(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_3100(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_3108(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(8); +} +static void MOVE_3110(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_3118(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_3120(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_3128(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_3130(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_3138(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_3139(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_313A(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_313B(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_313C(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA04(opc_data[1], 2); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_3140(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_3148(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_3150(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_3158(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_3160(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_3168(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_3170(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_3178(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_3179(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_317A(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_317B(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_317C(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_3180(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_3188(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(14); +} +static void MOVE_3190(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_3198(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_31A0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_31A8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_31B0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_31B8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_31B9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_31BA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_31BB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_31BC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_31C0(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_31C8(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_31D0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_31D8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_31E0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_31E8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_31F0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_31F8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_31F9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_31FA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_31FB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_31FC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA70(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_33C0(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_33C8(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_33D0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_33D8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_33E0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_33E8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_33F0(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_33F8(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_33F9(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_33FA(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_33FB(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_33FC(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + ULO dstea = cpuEA71(); + cpuMoveW(src); + memoryWriteWord(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_2000(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(4); +} +static void MOVE_2008(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(4); +} +static void MOVE_2010(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVE_2018(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVE_2020(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(14); +} +static void MOVE_2028(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(16); +} +static void MOVE_2030(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(18); +} +static void MOVE_2038(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(16); +} +static void MOVE_2039(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(20); +} +static void MOVE_203A(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(16); +} +static void MOVE_203B(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(18); +} +static void MOVE_203C(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + cpuMoveL(src); + cpuSetDReg(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVE_2080(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_2088(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_2090(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_2098(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_20A0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_20A8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_20B0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_20B8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_20B9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_20BA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_20BB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_20BC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA02(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_20C0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_20C8(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_20D0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_20D8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_20E0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_20E8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_20F0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_20F8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_20F9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_20FA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_20FB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_20FC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA03(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_2100(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_2108(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(12); +} +static void MOVE_2110(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_2118(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_2120(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(22); +} +static void MOVE_2128(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_2130(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_2138(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_2139(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_213A(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_213B(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_213C(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA04(opc_data[1], 4); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_2140(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_2148(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_2150(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_2158(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_2160(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_2168(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_2170(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(30); +} +static void MOVE_2178(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_2179(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(32); +} +static void MOVE_217A(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_217B(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(30); +} +static void MOVE_217C(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA05(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_2180(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_2188(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(18); +} +static void MOVE_2190(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_2198(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_21A0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_21A8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(30); +} +static void MOVE_21B0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(32); +} +static void MOVE_21B8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(30); +} +static void MOVE_21B9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(34); +} +static void MOVE_21BA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(30); +} +static void MOVE_21BB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(32); +} +static void MOVE_21BC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA06(opc_data[1]); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_21C0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_21C8(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(16); +} +static void MOVE_21D0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_21D8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_21E0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(26); +} +static void MOVE_21E8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_21F0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(30); +} +static void MOVE_21F8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_21F9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(32); +} +static void MOVE_21FA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_21FB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(30); +} +static void MOVE_21FC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA70(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(24); +} +static void MOVE_23C0(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_23C8(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(20); +} +static void MOVE_23D0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_23D8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVE_23E0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(30); +} +static void MOVE_23E8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(32); +} +static void MOVE_23F0(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(34); +} +static void MOVE_23F8(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(32); +} +static void MOVE_23F9(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(36); +} +static void MOVE_23FA(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(32); +} +static void MOVE_23FB(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(34); +} +static void MOVE_23FC(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + ULO dstea = cpuEA71(); + cpuMoveL(src); + memoryWriteLong(src, dstea); + cpuSetInstructionTime(28); +} +static void MOVEA_3040(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(4); +} +static void MOVEA_3048(ULO*opc_data) +{ + UWO src = cpuGetARegWord(opc_data[0]); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(4); +} +static void MOVEA_3050(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA02(opc_data[0])); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(8); +} +static void MOVEA_3058(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA03(opc_data[0],2)); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(8); +} +static void MOVEA_3060(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(10); +} +static void MOVEA_3068(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA05(opc_data[0])); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(12); +} +static void MOVEA_3070(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA06(opc_data[0])); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(14); +} +static void MOVEA_3078(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA70()); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(12); +} +static void MOVEA_3079(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA71()); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(16); +} +static void MOVEA_307A(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA72()); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(12); +} +static void MOVEA_307B(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA73()); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(14); +} +static void MOVEA_307C(ULO*opc_data) +{ + UWO src = cpuGetNextWord(); + cpuSetAReg(opc_data[1], (ULO)(LON)(WOR)src); + cpuSetInstructionTime(8); +} +static void MOVEA_2040(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(4); +} +static void MOVEA_2048(ULO*opc_data) +{ + ULO src = cpuGetAReg(opc_data[0]); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(4); +} +static void MOVEA_2050(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA02(opc_data[0])); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVEA_2058(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA03(opc_data[0],4)); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void MOVEA_2060(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(14); +} +static void MOVEA_2068(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA05(opc_data[0])); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(16); +} +static void MOVEA_2070(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA06(opc_data[0])); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(18); +} +static void MOVEA_2078(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA70()); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(16); +} +static void MOVEA_2079(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA71()); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(20); +} +static void MOVEA_207A(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA72()); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(16); +} +static void MOVEA_207B(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA73()); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(18); +} +static void MOVEA_207C(ULO*opc_data) +{ + ULO src = cpuGetNextLong(); + cpuSetAReg(opc_data[1], src); + cpuSetInstructionTime(12); +} +static void BCCB_6200(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode2(), opc_data[1]); +} +static void BCCB_6300(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode3(), opc_data[1]); +} +static void BCCB_6400(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode4(), opc_data[1]); +} +static void BCCB_6500(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode5(), opc_data[1]); +} +static void BCCB_6600(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode6(), opc_data[1]); +} +static void BCCB_6700(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode7(), opc_data[1]); +} +static void BCCB_6800(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode8(), opc_data[1]); +} +static void BCCB_6900(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode9(), opc_data[1]); +} +static void BCCB_6A00(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode10(), opc_data[1]); +} +static void BCCB_6B00(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode11(), opc_data[1]); +} +static void BCCB_6C00(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode12(), opc_data[1]); +} +static void BCCB_6D00(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode13(), opc_data[1]); +} +static void BCCB_6E00(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode14(), opc_data[1]); +} +static void BCCB_6F00(ULO*opc_data) +{ + cpuBccB(cpuCalculateConditionCode15(), opc_data[1]); +} +static void BCCW_6200(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode2()); +} +static void BCCW_6300(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode3()); +} +static void BCCW_6400(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode4()); +} +static void BCCW_6500(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode5()); +} +static void BCCW_6600(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode6()); +} +static void BCCW_6700(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode7()); +} +static void BCCW_6800(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode8()); +} +static void BCCW_6900(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode9()); +} +static void BCCW_6A00(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode10()); +} +static void BCCW_6B00(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode11()); +} +static void BCCW_6C00(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode12()); +} +static void BCCW_6D00(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode13()); +} +static void BCCW_6E00(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode14()); +} +static void BCCW_6F00(ULO*opc_data) +{ + cpuBccW(cpuCalculateConditionCode15()); +} +static void BCCL_62FF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode2()); +} +static void BCCL_63FF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode3()); +} +static void BCCL_64FF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode4()); +} +static void BCCL_65FF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode5()); +} +static void BCCL_66FF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode6()); +} +static void BCCL_67FF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode7()); +} +static void BCCL_68FF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode8()); +} +static void BCCL_69FF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode9()); +} +static void BCCL_6AFF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode10()); +} +static void BCCL_6BFF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode11()); +} +static void BCCL_6CFF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode12()); +} +static void BCCL_6DFF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode13()); +} +static void BCCL_6EFF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode14()); +} +static void BCCL_6FFF(ULO*opc_data) +{ + cpuBccL(cpuCalculateConditionCode15()); +} +static void BKPT_4848(ULO*opc_data) +{ + cpuBkpt(opc_data[0]); +} +static void EXG_C140(ULO*opc_data) +{ + cpuExgDD(opc_data[0], opc_data[1]); +} +static void EXG_C148(ULO*opc_data) +{ + cpuExgAA(opc_data[0], opc_data[1]); +} +static void EXG_C188(ULO*opc_data) +{ + cpuExgDA(opc_data[0], opc_data[1]); +} +static void EXT_4880(ULO*opc_data) +{ + cpuExtW(opc_data[0]); +} +static void EXT_48C0(ULO*opc_data) +{ + cpuExtL(opc_data[0]); +} +static void EXT_49C0(ULO*opc_data) +{ + cpuExtBL(opc_data[0]); +} +static void SWAP_4840(ULO*opc_data) +{ + cpuSwap(opc_data[0]); +} +static void LINK_4E50(ULO*opc_data) +{ + cpuLinkW(opc_data[0]); +} +static void LINK_4808(ULO*opc_data) +{ + cpuLinkL(opc_data[0]); +} +static void UNLK_4E58(ULO*opc_data) +{ + cpuUnlk(opc_data[0]); +} +static void BRAB_6000(ULO*opc_data) +{ + cpuBraB(opc_data[1]); +} +static void BRAW_6000(ULO*opc_data) +{ + cpuBraW(); +} +static void BRAL_60FF(ULO*opc_data) +{ + cpuBraL(); +} +static void BSRB_6100(ULO*opc_data) +{ + cpuBsrB(opc_data[1]); +} +static void BSRW_6100(ULO*opc_data) +{ + cpuBsrW(); +} +static void BSRL_61FF(ULO*opc_data) +{ + cpuBsrL(); +} +static void DBCC_50C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode0(), opc_data[1]); +} +static void DBCC_51C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode1(), opc_data[1]); +} +static void DBCC_52C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode2(), opc_data[1]); +} +static void DBCC_53C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode3(), opc_data[1]); +} +static void DBCC_54C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode4(), opc_data[1]); +} +static void DBCC_55C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode5(), opc_data[1]); +} +static void DBCC_56C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode6(), opc_data[1]); +} +static void DBCC_57C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode7(), opc_data[1]); +} +static void DBCC_58C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode8(), opc_data[1]); +} +static void DBCC_59C8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode9(), opc_data[1]); +} +static void DBCC_5AC8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode10(), opc_data[1]); +} +static void DBCC_5BC8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode11(), opc_data[1]); +} +static void DBCC_5CC8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode12(), opc_data[1]); +} +static void DBCC_5DC8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode13(), opc_data[1]); +} +static void DBCC_5EC8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode14(), opc_data[1]); +} +static void DBCC_5FC8(ULO*opc_data) +{ + cpuDbcc(cpuCalculateConditionCode15(), opc_data[1]); +} +static void TRAPCC_50FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode0()); +} +static void TRAPCC_51FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode1()); +} +static void TRAPCC_52FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode2()); +} +static void TRAPCC_53FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode3()); +} +static void TRAPCC_54FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode4()); +} +static void TRAPCC_55FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode5()); +} +static void TRAPCC_56FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode6()); +} +static void TRAPCC_57FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode7()); +} +static void TRAPCC_58FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode8()); +} +static void TRAPCC_59FC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode9()); +} +static void TRAPCC_5AFC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode10()); +} +static void TRAPCC_5BFC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode11()); +} +static void TRAPCC_5CFC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode12()); +} +static void TRAPCC_5DFC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode13()); +} +static void TRAPCC_5EFC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode14()); +} +static void TRAPCC_5FFC(ULO*opc_data) +{ + cpuTrapcc(cpuCalculateConditionCode15()); +} +static void TRAPCC_50FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode0()); +} +static void TRAPCC_51FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode1()); +} +static void TRAPCC_52FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode2()); +} +static void TRAPCC_53FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode3()); +} +static void TRAPCC_54FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode4()); +} +static void TRAPCC_55FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode5()); +} +static void TRAPCC_56FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode6()); +} +static void TRAPCC_57FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode7()); +} +static void TRAPCC_58FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode8()); +} +static void TRAPCC_59FA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode9()); +} +static void TRAPCC_5AFA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode10()); +} +static void TRAPCC_5BFA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode11()); +} +static void TRAPCC_5CFA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode12()); +} +static void TRAPCC_5DFA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode13()); +} +static void TRAPCC_5EFA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode14()); +} +static void TRAPCC_5FFA(ULO*opc_data) +{ + cpuTrapccW(cpuCalculateConditionCode15()); +} +static void TRAPCC_50FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode0()); +} +static void TRAPCC_51FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode1()); +} +static void TRAPCC_52FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode2()); +} +static void TRAPCC_53FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode3()); +} +static void TRAPCC_54FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode4()); +} +static void TRAPCC_55FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode5()); +} +static void TRAPCC_56FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode6()); +} +static void TRAPCC_57FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode7()); +} +static void TRAPCC_58FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode8()); +} +static void TRAPCC_59FB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode9()); +} +static void TRAPCC_5AFB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode10()); +} +static void TRAPCC_5BFB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode11()); +} +static void TRAPCC_5CFB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode12()); +} +static void TRAPCC_5DFB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode13()); +} +static void TRAPCC_5EFB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode14()); +} +static void TRAPCC_5FFB(ULO*opc_data) +{ + cpuTrapccL(cpuCalculateConditionCode15()); +} +static void RTD_4E74(ULO*opc_data) +{ + cpuRtd(); +} +static void RTE_4E73(ULO*opc_data) +{ + cpuRte(); +} +static void RTS_4E75(ULO*opc_data) +{ + cpuRts(); +} +static void RTR_4E77(ULO*opc_data) +{ + cpuRtr(); +} +static void NOP_4E71(ULO*opc_data) +{ + cpuNop(); +} +static void MOVEC_4E7A(ULO*opc_data) +{ + cpuMoveCFrom(); +} +static void MOVEC_4E7B(ULO*opc_data) +{ + cpuMoveCTo(); +} +static void CAS2_0CFC(ULO*opc_data) +{ + cpuCas2W(); +} +static void CAS2_0EFC(ULO*opc_data) +{ + cpuCas2L(); +} +static void TRAP_4E40(ULO*opc_data) +{ + cpuTrap(opc_data[0]); +} +static void TRAPV_4E76(ULO*opc_data) +{ + cpuTrapv(); +} +static void STOP_4E72(ULO*opc_data) +{ + cpuStop(cpuGetNextWord()); +} +static void RESET_4E70(ULO*opc_data) +{ + cpuReset(); +} +static void MOVEUSP_4E60(ULO*opc_data) +{ + cpuMoveToUsp(opc_data[0]); +} +static void MOVEUSP_4E68(ULO*opc_data) +{ + cpuMoveFromUsp(opc_data[0]); +} +static void CMPM_B108(ULO*opc_data) +{ + cpuCmpMB(opc_data[0], opc_data[1]); +} +static void CMPM_B148(ULO*opc_data) +{ + cpuCmpMW(opc_data[0], opc_data[1]); +} +static void CMPM_B188(ULO*opc_data) +{ + cpuCmpML(opc_data[0], opc_data[1]); +} +static void RTM_06C0(ULO*opc_data) +{ + cpuRtm(opc_data[0], opc_data[1]); +} +static void PFLUSH040_F500(ULO*opc_data) +{ + cpuPflush040(opc_data[0], opc_data[1]); +} +static void PTEST040_F548(ULO*opc_data) +{ + cpuPtest040(opc_data[0], opc_data[1]); +} +static void ADDX_D100(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAddXB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void ADDX_D140(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuAddXW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void ADDX_D180(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuAddXL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void ADDX_D108(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA04(opc_data[1], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAddXB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void ADDX_D148(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dstea = cpuEA04(opc_data[1], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAddXW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void ADDX_D188(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dstea = cpuEA04(opc_data[1], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuAddXL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(30); +} +static void SUBX_9100(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSubXB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void SUBX_9140(ULO*opc_data) +{ + UWO src = cpuGetDRegWord(opc_data[0]); + UWO dst = cpuGetDRegWord(opc_data[1]); + dst = cpuSubXW(dst, src); + cpuSetDRegWord(opc_data[1], dst); + cpuSetInstructionTime(4); +} +static void SUBX_9180(ULO*opc_data) +{ + ULO src = cpuGetDReg(opc_data[0]); + ULO dst = cpuGetDReg(opc_data[1]); + dst = cpuSubXL(dst, src); + cpuSetDReg(opc_data[1], dst); + cpuSetInstructionTime(8); +} +static void SUBX_9108(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA04(opc_data[1], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuSubXB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void SUBX_9148(ULO*opc_data) +{ + UWO src = memoryReadWord(cpuEA04(opc_data[0],2)); + ULO dstea = cpuEA04(opc_data[1], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuSubXW(dst, src); + memoryWriteWord(dst, dstea); + cpuSetInstructionTime(18); +} +static void SUBX_9188(ULO*opc_data) +{ + ULO src = memoryReadLong(cpuEA04(opc_data[0],4)); + ULO dstea = cpuEA04(opc_data[1], 4); + ULO dst = memoryReadLong(dstea); + dst = cpuSubXL(dst, src); + memoryWriteLong(dst, dstea); + cpuSetInstructionTime(30); +} +static void ABCD_C100(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuAbcdB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(6); +} +static void ABCD_C108(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA04(opc_data[1], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuAbcdB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void SBCD_8100(ULO*opc_data) +{ + UBY src = cpuGetDRegByte(opc_data[0]); + UBY dst = cpuGetDRegByte(opc_data[1]); + dst = cpuSbcdB(dst, src); + cpuSetDRegByte(opc_data[1], dst); + cpuSetInstructionTime(6); +} +static void SBCD_8108(ULO*opc_data) +{ + UBY src = memoryReadByte(cpuEA04(opc_data[0],1)); + ULO dstea = cpuEA04(opc_data[1], 1); + UBY dst = memoryReadByte(dstea); + dst = cpuSbcdB(dst, src); + memoryWriteByte(dst, dstea); + cpuSetInstructionTime(18); +} +static void LSL_E108(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuLslB(dst, opc_data[1], opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void LSL_E148(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuLslW(dst, opc_data[1], opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void LSL_E188(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuLslL(dst, opc_data[1], opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void LSL_E128(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuLslB(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void LSL_E168(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuLslW(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void LSL_E1A8(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuLslL(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void LSL_E3D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuLslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSL_E3D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuLslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSL_E3E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuLslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSL_E3E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuLslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSL_E3F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuLslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSL_E3F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuLslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSL_E3F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuLslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSR_E008(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuLsrB(dst, opc_data[1], opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void LSR_E048(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuLsrW(dst, opc_data[1], opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void LSR_E088(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuLsrL(dst, opc_data[1], opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void LSR_E028(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuLsrB(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void LSR_E068(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuLsrW(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void LSR_E0A8(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuLsrL(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void LSR_E2D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuLsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSR_E2D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuLsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSR_E2E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuLsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSR_E2E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuLsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSR_E2F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuLsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSR_E2F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuLsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void LSR_E2F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuLsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASL_E100(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuAslB(dst, opc_data[1], opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ASL_E140(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuAslW(dst, opc_data[1], opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ASL_E180(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuAslL(dst, opc_data[1], opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ASL_E120(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuAslB(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ASL_E160(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuAslW(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ASL_E1A0(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuAslL(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ASL_E1D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASL_E1D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASL_E1E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASL_E1E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASL_E1F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASL_E1F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuAslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASL_E1F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuAslW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASR_E000(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuAsrB(dst, opc_data[1], opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ASR_E040(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuAsrW(dst, opc_data[1], opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ASR_E080(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuAsrL(dst, opc_data[1], opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ASR_E020(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuAsrB(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ASR_E060(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuAsrW(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ASR_E0A0(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuAsrL(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ASR_E0D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASR_E0D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASR_E0E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuAsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASR_E0E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASR_E0F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuAsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASR_E0F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuAsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ASR_E0F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuAsrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROL_E118(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuRolB(dst, opc_data[1], opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ROL_E158(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuRolW(dst, opc_data[1], opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ROL_E198(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuRolL(dst, opc_data[1], opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ROL_E138(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuRolB(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ROL_E178(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuRolW(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ROL_E1B8(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuRolL(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ROL_E7D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRolW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROL_E7D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuRolW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROL_E7E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuRolW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROL_E7E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRolW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROL_E7F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRolW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROL_E7F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuRolW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROL_E7F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuRolW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROR_E018(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuRorB(dst, opc_data[1], opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ROR_E058(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuRorW(dst, opc_data[1], opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ROR_E098(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuRorL(dst, opc_data[1], opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ROR_E038(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuRorB(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ROR_E078(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuRorW(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ROR_E0B8(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuRorL(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ROR_E6D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRorW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROR_E6D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuRorW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROR_E6E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuRorW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROR_E6E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRorW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROR_E6F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRorW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROR_E6F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuRorW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROR_E6F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuRorW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXL_E110(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuRoxlB(dst, opc_data[1], opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ROXL_E150(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuRoxlW(dst, opc_data[1], opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ROXL_E190(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuRoxlL(dst, opc_data[1], opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ROXL_E130(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuRoxlB(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ROXL_E170(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuRoxlW(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ROXL_E1B0(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuRoxlL(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ROXL_E5D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxlW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXL_E5D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxlW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXL_E5E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxlW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXL_E5E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxlW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXL_E5F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxlW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXL_E5F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxlW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXL_E5F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxlW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXR_E010(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuRoxrB(dst, opc_data[1], opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ROXR_E050(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuRoxrW(dst, opc_data[1], opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ROXR_E090(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuRoxrL(dst, opc_data[1], opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ROXR_E030(ULO*opc_data) +{ + UBY dst = cpuGetDRegByte(opc_data[0]); + dst = cpuRoxrB(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegByte(opc_data[0], dst); +} +static void ROXR_E070(ULO*opc_data) +{ + UWO dst = cpuGetDRegWord(opc_data[0]); + dst = cpuRoxrW(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDRegWord(opc_data[0], dst); +} +static void ROXR_E0B0(ULO*opc_data) +{ + ULO dst = cpuGetDReg(opc_data[0]); + dst = cpuRoxrL(dst, cpuGetDReg(opc_data[1]), opc_data[2]); + cpuSetDReg(opc_data[0], dst); +} +static void ROXR_E4D0(ULO*opc_data) +{ + ULO dstea = cpuEA02(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXR_E4D8(ULO*opc_data) +{ + ULO dstea = cpuEA03(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXR_E4E0(ULO*opc_data) +{ + ULO dstea = cpuEA04(opc_data[0], 2); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXR_E4E8(ULO*opc_data) +{ + ULO dstea = cpuEA05(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXR_E4F0(ULO*opc_data) +{ + ULO dstea = cpuEA06(opc_data[0]); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXR_E4F8(ULO*opc_data) +{ + ULO dstea = cpuEA70(); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void ROXR_E4F9(ULO*opc_data) +{ + ULO dstea = cpuEA71(); + UWO dst = memoryReadWord(dstea); + dst = cpuRoxrW(dst, 1, opc_data[2]); + memoryWriteWord(dst, dstea); +} +static void MOVEP_0188(ULO*opc_data) +{ + cpuMovepWEa(opc_data[1], opc_data[0]); +} +static void MOVEP_01C8(ULO*opc_data) +{ + cpuMovepLEa(opc_data[1], opc_data[0]); +} +static void MOVEP_0108(ULO*opc_data) +{ + cpuMovepWReg(opc_data[1], opc_data[0]); +} +static void MOVEP_0148(ULO*opc_data) +{ + cpuMovepLReg(opc_data[1], opc_data[0]); +} +static void PACK_8140(ULO*opc_data) +{ + cpuPackReg(opc_data[1], opc_data[0]); +} +static void PACK_8148(ULO*opc_data) +{ + cpuPackEa(opc_data[1], opc_data[0]); +} +static void UNPK_8180(ULO*opc_data) +{ + cpuUnpkReg(opc_data[1], opc_data[0]); +} +static void UNPK_8188(ULO*opc_data) +{ + cpuUnpkEa(opc_data[1], opc_data[0]); +} +#endif diff --git a/cpu/CpuModule_Data.h b/cpu/CpuModule_Data.h new file mode 100644 index 0000000..c84c0ff --- /dev/null +++ b/cpu/CpuModule_Data.h @@ -0,0 +1,69648 @@ +#ifndef CPUMODULE_DATA_H +#define CPUMODULE_DATA_H + +typedef void (*cpuInstructionFunction)(ULO*); +typedef struct cpu_data_struct +{ + cpuInstructionFunction instruction_func; + ULO data[3]; +} cpuOpcodeData; + +cpuOpcodeData cpu_opcode_data[65536] = { +{ORI_0000,{0U,0U,0U}}, +{ORI_0000,{1U,0U,0U}}, +{ORI_0000,{2U,0U,0U}}, +{ORI_0000,{3U,0U,0U}}, +{ORI_0000,{4U,0U,0U}}, +{ORI_0000,{5U,0U,0U}}, +{ORI_0000,{6U,0U,0U}}, +{ORI_0000,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ORI_0010,{0U,0U,0U}}, +{ORI_0010,{1U,0U,0U}}, +{ORI_0010,{2U,0U,0U}}, +{ORI_0010,{3U,0U,0U}}, +{ORI_0010,{4U,0U,0U}}, +{ORI_0010,{5U,0U,0U}}, +{ORI_0010,{6U,0U,0U}}, +{ORI_0010,{7U,0U,0U}}, +{ORI_0018,{0U,0U,0U}}, +{ORI_0018,{1U,0U,0U}}, +{ORI_0018,{2U,0U,0U}}, +{ORI_0018,{3U,0U,0U}}, +{ORI_0018,{4U,0U,0U}}, +{ORI_0018,{5U,0U,0U}}, +{ORI_0018,{6U,0U,0U}}, +{ORI_0018,{7U,0U,0U}}, +{ORI_0020,{0U,0U,0U}}, +{ORI_0020,{1U,0U,0U}}, +{ORI_0020,{2U,0U,0U}}, +{ORI_0020,{3U,0U,0U}}, +{ORI_0020,{4U,0U,0U}}, +{ORI_0020,{5U,0U,0U}}, +{ORI_0020,{6U,0U,0U}}, +{ORI_0020,{7U,0U,0U}}, +{ORI_0028,{0U,0U,0U}}, +{ORI_0028,{1U,0U,0U}}, +{ORI_0028,{2U,0U,0U}}, +{ORI_0028,{3U,0U,0U}}, +{ORI_0028,{4U,0U,0U}}, +{ORI_0028,{5U,0U,0U}}, +{ORI_0028,{6U,0U,0U}}, +{ORI_0028,{7U,0U,0U}}, +{ORI_0030,{0U,0U,0U}}, +{ORI_0030,{1U,0U,0U}}, +{ORI_0030,{2U,0U,0U}}, +{ORI_0030,{3U,0U,0U}}, +{ORI_0030,{4U,0U,0U}}, +{ORI_0030,{5U,0U,0U}}, +{ORI_0030,{6U,0U,0U}}, +{ORI_0030,{7U,0U,0U}}, +{ORI_0038,{0U,0U,0U}}, +{ORI_0039,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ORI_003C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ORI_0040,{0U,0U,0U}}, +{ORI_0040,{1U,0U,0U}}, +{ORI_0040,{2U,0U,0U}}, +{ORI_0040,{3U,0U,0U}}, +{ORI_0040,{4U,0U,0U}}, +{ORI_0040,{5U,0U,0U}}, +{ORI_0040,{6U,0U,0U}}, +{ORI_0040,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ORI_0050,{0U,0U,0U}}, +{ORI_0050,{1U,0U,0U}}, +{ORI_0050,{2U,0U,0U}}, +{ORI_0050,{3U,0U,0U}}, +{ORI_0050,{4U,0U,0U}}, +{ORI_0050,{5U,0U,0U}}, +{ORI_0050,{6U,0U,0U}}, +{ORI_0050,{7U,0U,0U}}, +{ORI_0058,{0U,0U,0U}}, +{ORI_0058,{1U,0U,0U}}, +{ORI_0058,{2U,0U,0U}}, +{ORI_0058,{3U,0U,0U}}, +{ORI_0058,{4U,0U,0U}}, +{ORI_0058,{5U,0U,0U}}, +{ORI_0058,{6U,0U,0U}}, +{ORI_0058,{7U,0U,0U}}, +{ORI_0060,{0U,0U,0U}}, +{ORI_0060,{1U,0U,0U}}, +{ORI_0060,{2U,0U,0U}}, +{ORI_0060,{3U,0U,0U}}, +{ORI_0060,{4U,0U,0U}}, +{ORI_0060,{5U,0U,0U}}, +{ORI_0060,{6U,0U,0U}}, +{ORI_0060,{7U,0U,0U}}, +{ORI_0068,{0U,0U,0U}}, +{ORI_0068,{1U,0U,0U}}, +{ORI_0068,{2U,0U,0U}}, +{ORI_0068,{3U,0U,0U}}, +{ORI_0068,{4U,0U,0U}}, +{ORI_0068,{5U,0U,0U}}, +{ORI_0068,{6U,0U,0U}}, +{ORI_0068,{7U,0U,0U}}, +{ORI_0070,{0U,0U,0U}}, +{ORI_0070,{1U,0U,0U}}, +{ORI_0070,{2U,0U,0U}}, +{ORI_0070,{3U,0U,0U}}, +{ORI_0070,{4U,0U,0U}}, +{ORI_0070,{5U,0U,0U}}, +{ORI_0070,{6U,0U,0U}}, +{ORI_0070,{7U,0U,0U}}, +{ORI_0078,{0U,0U,0U}}, +{ORI_0079,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ORI_007C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ORI_0080,{0U,0U,0U}}, +{ORI_0080,{1U,0U,0U}}, +{ORI_0080,{2U,0U,0U}}, +{ORI_0080,{3U,0U,0U}}, +{ORI_0080,{4U,0U,0U}}, +{ORI_0080,{5U,0U,0U}}, +{ORI_0080,{6U,0U,0U}}, +{ORI_0080,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ORI_0090,{0U,0U,0U}}, +{ORI_0090,{1U,0U,0U}}, +{ORI_0090,{2U,0U,0U}}, +{ORI_0090,{3U,0U,0U}}, +{ORI_0090,{4U,0U,0U}}, +{ORI_0090,{5U,0U,0U}}, +{ORI_0090,{6U,0U,0U}}, +{ORI_0090,{7U,0U,0U}}, +{ORI_0098,{0U,0U,0U}}, +{ORI_0098,{1U,0U,0U}}, +{ORI_0098,{2U,0U,0U}}, +{ORI_0098,{3U,0U,0U}}, +{ORI_0098,{4U,0U,0U}}, +{ORI_0098,{5U,0U,0U}}, +{ORI_0098,{6U,0U,0U}}, +{ORI_0098,{7U,0U,0U}}, +{ORI_00A0,{0U,0U,0U}}, +{ORI_00A0,{1U,0U,0U}}, +{ORI_00A0,{2U,0U,0U}}, +{ORI_00A0,{3U,0U,0U}}, +{ORI_00A0,{4U,0U,0U}}, +{ORI_00A0,{5U,0U,0U}}, +{ORI_00A0,{6U,0U,0U}}, +{ORI_00A0,{7U,0U,0U}}, +{ORI_00A8,{0U,0U,0U}}, +{ORI_00A8,{1U,0U,0U}}, +{ORI_00A8,{2U,0U,0U}}, +{ORI_00A8,{3U,0U,0U}}, +{ORI_00A8,{4U,0U,0U}}, +{ORI_00A8,{5U,0U,0U}}, +{ORI_00A8,{6U,0U,0U}}, +{ORI_00A8,{7U,0U,0U}}, +{ORI_00B0,{0U,0U,0U}}, +{ORI_00B0,{1U,0U,0U}}, +{ORI_00B0,{2U,0U,0U}}, +{ORI_00B0,{3U,0U,0U}}, +{ORI_00B0,{4U,0U,0U}}, +{ORI_00B0,{5U,0U,0U}}, +{ORI_00B0,{6U,0U,0U}}, +{ORI_00B0,{7U,0U,0U}}, +{ORI_00B8,{0U,0U,0U}}, +{ORI_00B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHKCMP2_00D0,{0U,0U,0U}}, +{CHKCMP2_00D0,{1U,0U,0U}}, +{CHKCMP2_00D0,{2U,0U,0U}}, +{CHKCMP2_00D0,{3U,0U,0U}}, +{CHKCMP2_00D0,{4U,0U,0U}}, +{CHKCMP2_00D0,{5U,0U,0U}}, +{CHKCMP2_00D0,{6U,0U,0U}}, +{CHKCMP2_00D0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHKCMP2_00E8,{0U,0U,0U}}, +{CHKCMP2_00E8,{1U,0U,0U}}, +{CHKCMP2_00E8,{2U,0U,0U}}, +{CHKCMP2_00E8,{3U,0U,0U}}, +{CHKCMP2_00E8,{4U,0U,0U}}, +{CHKCMP2_00E8,{5U,0U,0U}}, +{CHKCMP2_00E8,{6U,0U,0U}}, +{CHKCMP2_00E8,{7U,0U,0U}}, +{CHKCMP2_00F0,{0U,0U,0U}}, +{CHKCMP2_00F0,{1U,0U,0U}}, +{CHKCMP2_00F0,{2U,0U,0U}}, +{CHKCMP2_00F0,{3U,0U,0U}}, +{CHKCMP2_00F0,{4U,0U,0U}}, +{CHKCMP2_00F0,{5U,0U,0U}}, +{CHKCMP2_00F0,{6U,0U,0U}}, +{CHKCMP2_00F0,{7U,0U,0U}}, +{CHKCMP2_00F8,{0U,0U,0U}}, +{CHKCMP2_00F9,{0U,0U,0U}}, +{CHKCMP2_00FA,{0U,0U,0U}}, +{CHKCMP2_00FB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0100,{0U,0U,0U}}, +{BTST_0100,{1U,0U,0U}}, +{BTST_0100,{2U,0U,0U}}, +{BTST_0100,{3U,0U,0U}}, +{BTST_0100,{4U,0U,0U}}, +{BTST_0100,{5U,0U,0U}}, +{BTST_0100,{6U,0U,0U}}, +{BTST_0100,{7U,0U,0U}}, +{MOVEP_0108,{0U,0U,0U}}, +{MOVEP_0108,{0U,1U,0U}}, +{MOVEP_0108,{0U,2U,0U}}, +{MOVEP_0108,{0U,3U,0U}}, +{MOVEP_0108,{0U,4U,0U}}, +{MOVEP_0108,{0U,5U,0U}}, +{MOVEP_0108,{0U,6U,0U}}, +{MOVEP_0108,{0U,7U,0U}}, +{BTST_0110,{0U,0U,0U}}, +{BTST_0110,{1U,0U,0U}}, +{BTST_0110,{2U,0U,0U}}, +{BTST_0110,{3U,0U,0U}}, +{BTST_0110,{4U,0U,0U}}, +{BTST_0110,{5U,0U,0U}}, +{BTST_0110,{6U,0U,0U}}, +{BTST_0110,{7U,0U,0U}}, +{BTST_0118,{0U,0U,0U}}, +{BTST_0118,{1U,0U,0U}}, +{BTST_0118,{2U,0U,0U}}, +{BTST_0118,{3U,0U,0U}}, +{BTST_0118,{4U,0U,0U}}, +{BTST_0118,{5U,0U,0U}}, +{BTST_0118,{6U,0U,0U}}, +{BTST_0118,{7U,0U,0U}}, +{BTST_0120,{0U,0U,0U}}, +{BTST_0120,{1U,0U,0U}}, +{BTST_0120,{2U,0U,0U}}, +{BTST_0120,{3U,0U,0U}}, +{BTST_0120,{4U,0U,0U}}, +{BTST_0120,{5U,0U,0U}}, +{BTST_0120,{6U,0U,0U}}, +{BTST_0120,{7U,0U,0U}}, +{BTST_0128,{0U,0U,0U}}, +{BTST_0128,{1U,0U,0U}}, +{BTST_0128,{2U,0U,0U}}, +{BTST_0128,{3U,0U,0U}}, +{BTST_0128,{4U,0U,0U}}, +{BTST_0128,{5U,0U,0U}}, +{BTST_0128,{6U,0U,0U}}, +{BTST_0128,{7U,0U,0U}}, +{BTST_0130,{0U,0U,0U}}, +{BTST_0130,{1U,0U,0U}}, +{BTST_0130,{2U,0U,0U}}, +{BTST_0130,{3U,0U,0U}}, +{BTST_0130,{4U,0U,0U}}, +{BTST_0130,{5U,0U,0U}}, +{BTST_0130,{6U,0U,0U}}, +{BTST_0130,{7U,0U,0U}}, +{BTST_0138,{0U,0U,0U}}, +{BTST_0139,{0U,0U,0U}}, +{BTST_013A,{0U,0U,0U}}, +{BTST_013B,{0U,0U,0U}}, +{BTST_013C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0140,{0U,0U,0U}}, +{BCHG_0140,{1U,0U,0U}}, +{BCHG_0140,{2U,0U,0U}}, +{BCHG_0140,{3U,0U,0U}}, +{BCHG_0140,{4U,0U,0U}}, +{BCHG_0140,{5U,0U,0U}}, +{BCHG_0140,{6U,0U,0U}}, +{BCHG_0140,{7U,0U,0U}}, +{MOVEP_0148,{0U,0U,0U}}, +{MOVEP_0148,{0U,1U,0U}}, +{MOVEP_0148,{0U,2U,0U}}, +{MOVEP_0148,{0U,3U,0U}}, +{MOVEP_0148,{0U,4U,0U}}, +{MOVEP_0148,{0U,5U,0U}}, +{MOVEP_0148,{0U,6U,0U}}, +{MOVEP_0148,{0U,7U,0U}}, +{BCHG_0150,{0U,0U,0U}}, +{BCHG_0150,{1U,0U,0U}}, +{BCHG_0150,{2U,0U,0U}}, +{BCHG_0150,{3U,0U,0U}}, +{BCHG_0150,{4U,0U,0U}}, +{BCHG_0150,{5U,0U,0U}}, +{BCHG_0150,{6U,0U,0U}}, +{BCHG_0150,{7U,0U,0U}}, +{BCHG_0158,{0U,0U,0U}}, +{BCHG_0158,{1U,0U,0U}}, +{BCHG_0158,{2U,0U,0U}}, +{BCHG_0158,{3U,0U,0U}}, +{BCHG_0158,{4U,0U,0U}}, +{BCHG_0158,{5U,0U,0U}}, +{BCHG_0158,{6U,0U,0U}}, +{BCHG_0158,{7U,0U,0U}}, +{BCHG_0160,{0U,0U,0U}}, +{BCHG_0160,{1U,0U,0U}}, +{BCHG_0160,{2U,0U,0U}}, +{BCHG_0160,{3U,0U,0U}}, +{BCHG_0160,{4U,0U,0U}}, +{BCHG_0160,{5U,0U,0U}}, +{BCHG_0160,{6U,0U,0U}}, +{BCHG_0160,{7U,0U,0U}}, +{BCHG_0168,{0U,0U,0U}}, +{BCHG_0168,{1U,0U,0U}}, +{BCHG_0168,{2U,0U,0U}}, +{BCHG_0168,{3U,0U,0U}}, +{BCHG_0168,{4U,0U,0U}}, +{BCHG_0168,{5U,0U,0U}}, +{BCHG_0168,{6U,0U,0U}}, +{BCHG_0168,{7U,0U,0U}}, +{BCHG_0170,{0U,0U,0U}}, +{BCHG_0170,{1U,0U,0U}}, +{BCHG_0170,{2U,0U,0U}}, +{BCHG_0170,{3U,0U,0U}}, +{BCHG_0170,{4U,0U,0U}}, +{BCHG_0170,{5U,0U,0U}}, +{BCHG_0170,{6U,0U,0U}}, +{BCHG_0170,{7U,0U,0U}}, +{BCHG_0178,{0U,0U,0U}}, +{BCHG_0179,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0180,{0U,0U,0U}}, +{BCLR_0180,{1U,0U,0U}}, +{BCLR_0180,{2U,0U,0U}}, +{BCLR_0180,{3U,0U,0U}}, +{BCLR_0180,{4U,0U,0U}}, +{BCLR_0180,{5U,0U,0U}}, +{BCLR_0180,{6U,0U,0U}}, +{BCLR_0180,{7U,0U,0U}}, +{MOVEP_0188,{0U,0U,0U}}, +{MOVEP_0188,{0U,1U,0U}}, +{MOVEP_0188,{0U,2U,0U}}, +{MOVEP_0188,{0U,3U,0U}}, +{MOVEP_0188,{0U,4U,0U}}, +{MOVEP_0188,{0U,5U,0U}}, +{MOVEP_0188,{0U,6U,0U}}, +{MOVEP_0188,{0U,7U,0U}}, +{BCLR_0190,{0U,0U,0U}}, +{BCLR_0190,{1U,0U,0U}}, +{BCLR_0190,{2U,0U,0U}}, +{BCLR_0190,{3U,0U,0U}}, +{BCLR_0190,{4U,0U,0U}}, +{BCLR_0190,{5U,0U,0U}}, +{BCLR_0190,{6U,0U,0U}}, +{BCLR_0190,{7U,0U,0U}}, +{BCLR_0198,{0U,0U,0U}}, +{BCLR_0198,{1U,0U,0U}}, +{BCLR_0198,{2U,0U,0U}}, +{BCLR_0198,{3U,0U,0U}}, +{BCLR_0198,{4U,0U,0U}}, +{BCLR_0198,{5U,0U,0U}}, +{BCLR_0198,{6U,0U,0U}}, +{BCLR_0198,{7U,0U,0U}}, +{BCLR_01A0,{0U,0U,0U}}, +{BCLR_01A0,{1U,0U,0U}}, +{BCLR_01A0,{2U,0U,0U}}, +{BCLR_01A0,{3U,0U,0U}}, +{BCLR_01A0,{4U,0U,0U}}, +{BCLR_01A0,{5U,0U,0U}}, +{BCLR_01A0,{6U,0U,0U}}, +{BCLR_01A0,{7U,0U,0U}}, +{BCLR_01A8,{0U,0U,0U}}, +{BCLR_01A8,{1U,0U,0U}}, +{BCLR_01A8,{2U,0U,0U}}, +{BCLR_01A8,{3U,0U,0U}}, +{BCLR_01A8,{4U,0U,0U}}, +{BCLR_01A8,{5U,0U,0U}}, +{BCLR_01A8,{6U,0U,0U}}, +{BCLR_01A8,{7U,0U,0U}}, +{BCLR_01B0,{0U,0U,0U}}, +{BCLR_01B0,{1U,0U,0U}}, +{BCLR_01B0,{2U,0U,0U}}, +{BCLR_01B0,{3U,0U,0U}}, +{BCLR_01B0,{4U,0U,0U}}, +{BCLR_01B0,{5U,0U,0U}}, +{BCLR_01B0,{6U,0U,0U}}, +{BCLR_01B0,{7U,0U,0U}}, +{BCLR_01B8,{0U,0U,0U}}, +{BCLR_01B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_01C0,{0U,0U,0U}}, +{BSET_01C0,{1U,0U,0U}}, +{BSET_01C0,{2U,0U,0U}}, +{BSET_01C0,{3U,0U,0U}}, +{BSET_01C0,{4U,0U,0U}}, +{BSET_01C0,{5U,0U,0U}}, +{BSET_01C0,{6U,0U,0U}}, +{BSET_01C0,{7U,0U,0U}}, +{MOVEP_01C8,{0U,0U,0U}}, +{MOVEP_01C8,{0U,1U,0U}}, +{MOVEP_01C8,{0U,2U,0U}}, +{MOVEP_01C8,{0U,3U,0U}}, +{MOVEP_01C8,{0U,4U,0U}}, +{MOVEP_01C8,{0U,5U,0U}}, +{MOVEP_01C8,{0U,6U,0U}}, +{MOVEP_01C8,{0U,7U,0U}}, +{BSET_01D0,{0U,0U,0U}}, +{BSET_01D0,{1U,0U,0U}}, +{BSET_01D0,{2U,0U,0U}}, +{BSET_01D0,{3U,0U,0U}}, +{BSET_01D0,{4U,0U,0U}}, +{BSET_01D0,{5U,0U,0U}}, +{BSET_01D0,{6U,0U,0U}}, +{BSET_01D0,{7U,0U,0U}}, +{BSET_01D8,{0U,0U,0U}}, +{BSET_01D8,{1U,0U,0U}}, +{BSET_01D8,{2U,0U,0U}}, +{BSET_01D8,{3U,0U,0U}}, +{BSET_01D8,{4U,0U,0U}}, +{BSET_01D8,{5U,0U,0U}}, +{BSET_01D8,{6U,0U,0U}}, +{BSET_01D8,{7U,0U,0U}}, +{BSET_01E0,{0U,0U,0U}}, +{BSET_01E0,{1U,0U,0U}}, +{BSET_01E0,{2U,0U,0U}}, +{BSET_01E0,{3U,0U,0U}}, +{BSET_01E0,{4U,0U,0U}}, +{BSET_01E0,{5U,0U,0U}}, +{BSET_01E0,{6U,0U,0U}}, +{BSET_01E0,{7U,0U,0U}}, +{BSET_01E8,{0U,0U,0U}}, +{BSET_01E8,{1U,0U,0U}}, +{BSET_01E8,{2U,0U,0U}}, +{BSET_01E8,{3U,0U,0U}}, +{BSET_01E8,{4U,0U,0U}}, +{BSET_01E8,{5U,0U,0U}}, +{BSET_01E8,{6U,0U,0U}}, +{BSET_01E8,{7U,0U,0U}}, +{BSET_01F0,{0U,0U,0U}}, +{BSET_01F0,{1U,0U,0U}}, +{BSET_01F0,{2U,0U,0U}}, +{BSET_01F0,{3U,0U,0U}}, +{BSET_01F0,{4U,0U,0U}}, +{BSET_01F0,{5U,0U,0U}}, +{BSET_01F0,{6U,0U,0U}}, +{BSET_01F0,{7U,0U,0U}}, +{BSET_01F8,{0U,0U,0U}}, +{BSET_01F9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ANDI_0200,{0U,0U,0U}}, +{ANDI_0200,{1U,0U,0U}}, +{ANDI_0200,{2U,0U,0U}}, +{ANDI_0200,{3U,0U,0U}}, +{ANDI_0200,{4U,0U,0U}}, +{ANDI_0200,{5U,0U,0U}}, +{ANDI_0200,{6U,0U,0U}}, +{ANDI_0200,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ANDI_0210,{0U,0U,0U}}, +{ANDI_0210,{1U,0U,0U}}, +{ANDI_0210,{2U,0U,0U}}, +{ANDI_0210,{3U,0U,0U}}, +{ANDI_0210,{4U,0U,0U}}, +{ANDI_0210,{5U,0U,0U}}, +{ANDI_0210,{6U,0U,0U}}, +{ANDI_0210,{7U,0U,0U}}, +{ANDI_0218,{0U,0U,0U}}, +{ANDI_0218,{1U,0U,0U}}, +{ANDI_0218,{2U,0U,0U}}, +{ANDI_0218,{3U,0U,0U}}, +{ANDI_0218,{4U,0U,0U}}, +{ANDI_0218,{5U,0U,0U}}, +{ANDI_0218,{6U,0U,0U}}, +{ANDI_0218,{7U,0U,0U}}, +{ANDI_0220,{0U,0U,0U}}, +{ANDI_0220,{1U,0U,0U}}, +{ANDI_0220,{2U,0U,0U}}, +{ANDI_0220,{3U,0U,0U}}, +{ANDI_0220,{4U,0U,0U}}, +{ANDI_0220,{5U,0U,0U}}, +{ANDI_0220,{6U,0U,0U}}, +{ANDI_0220,{7U,0U,0U}}, +{ANDI_0228,{0U,0U,0U}}, +{ANDI_0228,{1U,0U,0U}}, +{ANDI_0228,{2U,0U,0U}}, +{ANDI_0228,{3U,0U,0U}}, +{ANDI_0228,{4U,0U,0U}}, +{ANDI_0228,{5U,0U,0U}}, +{ANDI_0228,{6U,0U,0U}}, +{ANDI_0228,{7U,0U,0U}}, +{ANDI_0230,{0U,0U,0U}}, +{ANDI_0230,{1U,0U,0U}}, +{ANDI_0230,{2U,0U,0U}}, +{ANDI_0230,{3U,0U,0U}}, +{ANDI_0230,{4U,0U,0U}}, +{ANDI_0230,{5U,0U,0U}}, +{ANDI_0230,{6U,0U,0U}}, +{ANDI_0230,{7U,0U,0U}}, +{ANDI_0238,{0U,0U,0U}}, +{ANDI_0239,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ANDI_023C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ANDI_0240,{0U,0U,0U}}, +{ANDI_0240,{1U,0U,0U}}, +{ANDI_0240,{2U,0U,0U}}, +{ANDI_0240,{3U,0U,0U}}, +{ANDI_0240,{4U,0U,0U}}, +{ANDI_0240,{5U,0U,0U}}, +{ANDI_0240,{6U,0U,0U}}, +{ANDI_0240,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ANDI_0250,{0U,0U,0U}}, +{ANDI_0250,{1U,0U,0U}}, +{ANDI_0250,{2U,0U,0U}}, +{ANDI_0250,{3U,0U,0U}}, +{ANDI_0250,{4U,0U,0U}}, +{ANDI_0250,{5U,0U,0U}}, +{ANDI_0250,{6U,0U,0U}}, +{ANDI_0250,{7U,0U,0U}}, +{ANDI_0258,{0U,0U,0U}}, +{ANDI_0258,{1U,0U,0U}}, +{ANDI_0258,{2U,0U,0U}}, +{ANDI_0258,{3U,0U,0U}}, +{ANDI_0258,{4U,0U,0U}}, +{ANDI_0258,{5U,0U,0U}}, +{ANDI_0258,{6U,0U,0U}}, +{ANDI_0258,{7U,0U,0U}}, +{ANDI_0260,{0U,0U,0U}}, +{ANDI_0260,{1U,0U,0U}}, +{ANDI_0260,{2U,0U,0U}}, +{ANDI_0260,{3U,0U,0U}}, +{ANDI_0260,{4U,0U,0U}}, +{ANDI_0260,{5U,0U,0U}}, +{ANDI_0260,{6U,0U,0U}}, +{ANDI_0260,{7U,0U,0U}}, +{ANDI_0268,{0U,0U,0U}}, +{ANDI_0268,{1U,0U,0U}}, +{ANDI_0268,{2U,0U,0U}}, +{ANDI_0268,{3U,0U,0U}}, +{ANDI_0268,{4U,0U,0U}}, +{ANDI_0268,{5U,0U,0U}}, +{ANDI_0268,{6U,0U,0U}}, +{ANDI_0268,{7U,0U,0U}}, +{ANDI_0270,{0U,0U,0U}}, +{ANDI_0270,{1U,0U,0U}}, +{ANDI_0270,{2U,0U,0U}}, +{ANDI_0270,{3U,0U,0U}}, +{ANDI_0270,{4U,0U,0U}}, +{ANDI_0270,{5U,0U,0U}}, +{ANDI_0270,{6U,0U,0U}}, +{ANDI_0270,{7U,0U,0U}}, +{ANDI_0278,{0U,0U,0U}}, +{ANDI_0279,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ANDI_027C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ANDI_0280,{0U,0U,0U}}, +{ANDI_0280,{1U,0U,0U}}, +{ANDI_0280,{2U,0U,0U}}, +{ANDI_0280,{3U,0U,0U}}, +{ANDI_0280,{4U,0U,0U}}, +{ANDI_0280,{5U,0U,0U}}, +{ANDI_0280,{6U,0U,0U}}, +{ANDI_0280,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ANDI_0290,{0U,0U,0U}}, +{ANDI_0290,{1U,0U,0U}}, +{ANDI_0290,{2U,0U,0U}}, +{ANDI_0290,{3U,0U,0U}}, +{ANDI_0290,{4U,0U,0U}}, +{ANDI_0290,{5U,0U,0U}}, +{ANDI_0290,{6U,0U,0U}}, +{ANDI_0290,{7U,0U,0U}}, +{ANDI_0298,{0U,0U,0U}}, +{ANDI_0298,{1U,0U,0U}}, +{ANDI_0298,{2U,0U,0U}}, +{ANDI_0298,{3U,0U,0U}}, +{ANDI_0298,{4U,0U,0U}}, +{ANDI_0298,{5U,0U,0U}}, +{ANDI_0298,{6U,0U,0U}}, +{ANDI_0298,{7U,0U,0U}}, +{ANDI_02A0,{0U,0U,0U}}, +{ANDI_02A0,{1U,0U,0U}}, +{ANDI_02A0,{2U,0U,0U}}, +{ANDI_02A0,{3U,0U,0U}}, +{ANDI_02A0,{4U,0U,0U}}, +{ANDI_02A0,{5U,0U,0U}}, +{ANDI_02A0,{6U,0U,0U}}, +{ANDI_02A0,{7U,0U,0U}}, +{ANDI_02A8,{0U,0U,0U}}, +{ANDI_02A8,{1U,0U,0U}}, +{ANDI_02A8,{2U,0U,0U}}, +{ANDI_02A8,{3U,0U,0U}}, +{ANDI_02A8,{4U,0U,0U}}, +{ANDI_02A8,{5U,0U,0U}}, +{ANDI_02A8,{6U,0U,0U}}, +{ANDI_02A8,{7U,0U,0U}}, +{ANDI_02B0,{0U,0U,0U}}, +{ANDI_02B0,{1U,0U,0U}}, +{ANDI_02B0,{2U,0U,0U}}, +{ANDI_02B0,{3U,0U,0U}}, +{ANDI_02B0,{4U,0U,0U}}, +{ANDI_02B0,{5U,0U,0U}}, +{ANDI_02B0,{6U,0U,0U}}, +{ANDI_02B0,{7U,0U,0U}}, +{ANDI_02B8,{0U,0U,0U}}, +{ANDI_02B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHKCMP2_02D0,{0U,0U,0U}}, +{CHKCMP2_02D0,{1U,0U,0U}}, +{CHKCMP2_02D0,{2U,0U,0U}}, +{CHKCMP2_02D0,{3U,0U,0U}}, +{CHKCMP2_02D0,{4U,0U,0U}}, +{CHKCMP2_02D0,{5U,0U,0U}}, +{CHKCMP2_02D0,{6U,0U,0U}}, +{CHKCMP2_02D0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHKCMP2_02E8,{0U,0U,0U}}, +{CHKCMP2_02E8,{1U,0U,0U}}, +{CHKCMP2_02E8,{2U,0U,0U}}, +{CHKCMP2_02E8,{3U,0U,0U}}, +{CHKCMP2_02E8,{4U,0U,0U}}, +{CHKCMP2_02E8,{5U,0U,0U}}, +{CHKCMP2_02E8,{6U,0U,0U}}, +{CHKCMP2_02E8,{7U,0U,0U}}, +{CHKCMP2_02F0,{0U,0U,0U}}, +{CHKCMP2_02F0,{1U,0U,0U}}, +{CHKCMP2_02F0,{2U,0U,0U}}, +{CHKCMP2_02F0,{3U,0U,0U}}, +{CHKCMP2_02F0,{4U,0U,0U}}, +{CHKCMP2_02F0,{5U,0U,0U}}, +{CHKCMP2_02F0,{6U,0U,0U}}, +{CHKCMP2_02F0,{7U,0U,0U}}, +{CHKCMP2_02F8,{0U,0U,0U}}, +{CHKCMP2_02F9,{0U,0U,0U}}, +{CHKCMP2_02FA,{0U,0U,0U}}, +{CHKCMP2_02FB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0100,{0U,1U,0U}}, +{BTST_0100,{1U,1U,0U}}, +{BTST_0100,{2U,1U,0U}}, +{BTST_0100,{3U,1U,0U}}, +{BTST_0100,{4U,1U,0U}}, +{BTST_0100,{5U,1U,0U}}, +{BTST_0100,{6U,1U,0U}}, +{BTST_0100,{7U,1U,0U}}, +{MOVEP_0108,{1U,0U,0U}}, +{MOVEP_0108,{1U,1U,0U}}, +{MOVEP_0108,{1U,2U,0U}}, +{MOVEP_0108,{1U,3U,0U}}, +{MOVEP_0108,{1U,4U,0U}}, +{MOVEP_0108,{1U,5U,0U}}, +{MOVEP_0108,{1U,6U,0U}}, +{MOVEP_0108,{1U,7U,0U}}, +{BTST_0110,{0U,1U,0U}}, +{BTST_0110,{1U,1U,0U}}, +{BTST_0110,{2U,1U,0U}}, +{BTST_0110,{3U,1U,0U}}, +{BTST_0110,{4U,1U,0U}}, +{BTST_0110,{5U,1U,0U}}, +{BTST_0110,{6U,1U,0U}}, +{BTST_0110,{7U,1U,0U}}, +{BTST_0118,{0U,1U,0U}}, +{BTST_0118,{1U,1U,0U}}, +{BTST_0118,{2U,1U,0U}}, +{BTST_0118,{3U,1U,0U}}, +{BTST_0118,{4U,1U,0U}}, +{BTST_0118,{5U,1U,0U}}, +{BTST_0118,{6U,1U,0U}}, +{BTST_0118,{7U,1U,0U}}, +{BTST_0120,{0U,1U,0U}}, +{BTST_0120,{1U,1U,0U}}, +{BTST_0120,{2U,1U,0U}}, +{BTST_0120,{3U,1U,0U}}, +{BTST_0120,{4U,1U,0U}}, +{BTST_0120,{5U,1U,0U}}, +{BTST_0120,{6U,1U,0U}}, +{BTST_0120,{7U,1U,0U}}, +{BTST_0128,{0U,1U,0U}}, +{BTST_0128,{1U,1U,0U}}, +{BTST_0128,{2U,1U,0U}}, +{BTST_0128,{3U,1U,0U}}, +{BTST_0128,{4U,1U,0U}}, +{BTST_0128,{5U,1U,0U}}, +{BTST_0128,{6U,1U,0U}}, +{BTST_0128,{7U,1U,0U}}, +{BTST_0130,{0U,1U,0U}}, +{BTST_0130,{1U,1U,0U}}, +{BTST_0130,{2U,1U,0U}}, +{BTST_0130,{3U,1U,0U}}, +{BTST_0130,{4U,1U,0U}}, +{BTST_0130,{5U,1U,0U}}, +{BTST_0130,{6U,1U,0U}}, +{BTST_0130,{7U,1U,0U}}, +{BTST_0138,{0U,1U,0U}}, +{BTST_0139,{0U,1U,0U}}, +{BTST_013A,{0U,1U,0U}}, +{BTST_013B,{0U,1U,0U}}, +{BTST_013C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0140,{0U,1U,0U}}, +{BCHG_0140,{1U,1U,0U}}, +{BCHG_0140,{2U,1U,0U}}, +{BCHG_0140,{3U,1U,0U}}, +{BCHG_0140,{4U,1U,0U}}, +{BCHG_0140,{5U,1U,0U}}, +{BCHG_0140,{6U,1U,0U}}, +{BCHG_0140,{7U,1U,0U}}, +{MOVEP_0148,{1U,0U,0U}}, +{MOVEP_0148,{1U,1U,0U}}, +{MOVEP_0148,{1U,2U,0U}}, +{MOVEP_0148,{1U,3U,0U}}, +{MOVEP_0148,{1U,4U,0U}}, +{MOVEP_0148,{1U,5U,0U}}, +{MOVEP_0148,{1U,6U,0U}}, +{MOVEP_0148,{1U,7U,0U}}, +{BCHG_0150,{0U,1U,0U}}, +{BCHG_0150,{1U,1U,0U}}, +{BCHG_0150,{2U,1U,0U}}, +{BCHG_0150,{3U,1U,0U}}, +{BCHG_0150,{4U,1U,0U}}, +{BCHG_0150,{5U,1U,0U}}, +{BCHG_0150,{6U,1U,0U}}, +{BCHG_0150,{7U,1U,0U}}, +{BCHG_0158,{0U,1U,0U}}, +{BCHG_0158,{1U,1U,0U}}, +{BCHG_0158,{2U,1U,0U}}, +{BCHG_0158,{3U,1U,0U}}, +{BCHG_0158,{4U,1U,0U}}, +{BCHG_0158,{5U,1U,0U}}, +{BCHG_0158,{6U,1U,0U}}, +{BCHG_0158,{7U,1U,0U}}, +{BCHG_0160,{0U,1U,0U}}, +{BCHG_0160,{1U,1U,0U}}, +{BCHG_0160,{2U,1U,0U}}, +{BCHG_0160,{3U,1U,0U}}, +{BCHG_0160,{4U,1U,0U}}, +{BCHG_0160,{5U,1U,0U}}, +{BCHG_0160,{6U,1U,0U}}, +{BCHG_0160,{7U,1U,0U}}, +{BCHG_0168,{0U,1U,0U}}, +{BCHG_0168,{1U,1U,0U}}, +{BCHG_0168,{2U,1U,0U}}, +{BCHG_0168,{3U,1U,0U}}, +{BCHG_0168,{4U,1U,0U}}, +{BCHG_0168,{5U,1U,0U}}, +{BCHG_0168,{6U,1U,0U}}, +{BCHG_0168,{7U,1U,0U}}, +{BCHG_0170,{0U,1U,0U}}, +{BCHG_0170,{1U,1U,0U}}, +{BCHG_0170,{2U,1U,0U}}, +{BCHG_0170,{3U,1U,0U}}, +{BCHG_0170,{4U,1U,0U}}, +{BCHG_0170,{5U,1U,0U}}, +{BCHG_0170,{6U,1U,0U}}, +{BCHG_0170,{7U,1U,0U}}, +{BCHG_0178,{0U,1U,0U}}, +{BCHG_0179,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0180,{0U,1U,0U}}, +{BCLR_0180,{1U,1U,0U}}, +{BCLR_0180,{2U,1U,0U}}, +{BCLR_0180,{3U,1U,0U}}, +{BCLR_0180,{4U,1U,0U}}, +{BCLR_0180,{5U,1U,0U}}, +{BCLR_0180,{6U,1U,0U}}, +{BCLR_0180,{7U,1U,0U}}, +{MOVEP_0188,{1U,0U,0U}}, +{MOVEP_0188,{1U,1U,0U}}, +{MOVEP_0188,{1U,2U,0U}}, +{MOVEP_0188,{1U,3U,0U}}, +{MOVEP_0188,{1U,4U,0U}}, +{MOVEP_0188,{1U,5U,0U}}, +{MOVEP_0188,{1U,6U,0U}}, +{MOVEP_0188,{1U,7U,0U}}, +{BCLR_0190,{0U,1U,0U}}, +{BCLR_0190,{1U,1U,0U}}, +{BCLR_0190,{2U,1U,0U}}, +{BCLR_0190,{3U,1U,0U}}, +{BCLR_0190,{4U,1U,0U}}, +{BCLR_0190,{5U,1U,0U}}, +{BCLR_0190,{6U,1U,0U}}, +{BCLR_0190,{7U,1U,0U}}, +{BCLR_0198,{0U,1U,0U}}, +{BCLR_0198,{1U,1U,0U}}, +{BCLR_0198,{2U,1U,0U}}, +{BCLR_0198,{3U,1U,0U}}, +{BCLR_0198,{4U,1U,0U}}, +{BCLR_0198,{5U,1U,0U}}, +{BCLR_0198,{6U,1U,0U}}, +{BCLR_0198,{7U,1U,0U}}, +{BCLR_01A0,{0U,1U,0U}}, +{BCLR_01A0,{1U,1U,0U}}, +{BCLR_01A0,{2U,1U,0U}}, +{BCLR_01A0,{3U,1U,0U}}, +{BCLR_01A0,{4U,1U,0U}}, +{BCLR_01A0,{5U,1U,0U}}, +{BCLR_01A0,{6U,1U,0U}}, +{BCLR_01A0,{7U,1U,0U}}, +{BCLR_01A8,{0U,1U,0U}}, +{BCLR_01A8,{1U,1U,0U}}, +{BCLR_01A8,{2U,1U,0U}}, +{BCLR_01A8,{3U,1U,0U}}, +{BCLR_01A8,{4U,1U,0U}}, +{BCLR_01A8,{5U,1U,0U}}, +{BCLR_01A8,{6U,1U,0U}}, +{BCLR_01A8,{7U,1U,0U}}, +{BCLR_01B0,{0U,1U,0U}}, +{BCLR_01B0,{1U,1U,0U}}, +{BCLR_01B0,{2U,1U,0U}}, +{BCLR_01B0,{3U,1U,0U}}, +{BCLR_01B0,{4U,1U,0U}}, +{BCLR_01B0,{5U,1U,0U}}, +{BCLR_01B0,{6U,1U,0U}}, +{BCLR_01B0,{7U,1U,0U}}, +{BCLR_01B8,{0U,1U,0U}}, +{BCLR_01B9,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_01C0,{0U,1U,0U}}, +{BSET_01C0,{1U,1U,0U}}, +{BSET_01C0,{2U,1U,0U}}, +{BSET_01C0,{3U,1U,0U}}, +{BSET_01C0,{4U,1U,0U}}, +{BSET_01C0,{5U,1U,0U}}, +{BSET_01C0,{6U,1U,0U}}, +{BSET_01C0,{7U,1U,0U}}, +{MOVEP_01C8,{1U,0U,0U}}, +{MOVEP_01C8,{1U,1U,0U}}, +{MOVEP_01C8,{1U,2U,0U}}, +{MOVEP_01C8,{1U,3U,0U}}, +{MOVEP_01C8,{1U,4U,0U}}, +{MOVEP_01C8,{1U,5U,0U}}, +{MOVEP_01C8,{1U,6U,0U}}, +{MOVEP_01C8,{1U,7U,0U}}, +{BSET_01D0,{0U,1U,0U}}, +{BSET_01D0,{1U,1U,0U}}, +{BSET_01D0,{2U,1U,0U}}, +{BSET_01D0,{3U,1U,0U}}, +{BSET_01D0,{4U,1U,0U}}, +{BSET_01D0,{5U,1U,0U}}, +{BSET_01D0,{6U,1U,0U}}, +{BSET_01D0,{7U,1U,0U}}, +{BSET_01D8,{0U,1U,0U}}, +{BSET_01D8,{1U,1U,0U}}, +{BSET_01D8,{2U,1U,0U}}, +{BSET_01D8,{3U,1U,0U}}, +{BSET_01D8,{4U,1U,0U}}, +{BSET_01D8,{5U,1U,0U}}, +{BSET_01D8,{6U,1U,0U}}, +{BSET_01D8,{7U,1U,0U}}, +{BSET_01E0,{0U,1U,0U}}, +{BSET_01E0,{1U,1U,0U}}, +{BSET_01E0,{2U,1U,0U}}, +{BSET_01E0,{3U,1U,0U}}, +{BSET_01E0,{4U,1U,0U}}, +{BSET_01E0,{5U,1U,0U}}, +{BSET_01E0,{6U,1U,0U}}, +{BSET_01E0,{7U,1U,0U}}, +{BSET_01E8,{0U,1U,0U}}, +{BSET_01E8,{1U,1U,0U}}, +{BSET_01E8,{2U,1U,0U}}, +{BSET_01E8,{3U,1U,0U}}, +{BSET_01E8,{4U,1U,0U}}, +{BSET_01E8,{5U,1U,0U}}, +{BSET_01E8,{6U,1U,0U}}, +{BSET_01E8,{7U,1U,0U}}, +{BSET_01F0,{0U,1U,0U}}, +{BSET_01F0,{1U,1U,0U}}, +{BSET_01F0,{2U,1U,0U}}, +{BSET_01F0,{3U,1U,0U}}, +{BSET_01F0,{4U,1U,0U}}, +{BSET_01F0,{5U,1U,0U}}, +{BSET_01F0,{6U,1U,0U}}, +{BSET_01F0,{7U,1U,0U}}, +{BSET_01F8,{0U,1U,0U}}, +{BSET_01F9,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBI_0400,{0U,0U,0U}}, +{SUBI_0400,{1U,0U,0U}}, +{SUBI_0400,{2U,0U,0U}}, +{SUBI_0400,{3U,0U,0U}}, +{SUBI_0400,{4U,0U,0U}}, +{SUBI_0400,{5U,0U,0U}}, +{SUBI_0400,{6U,0U,0U}}, +{SUBI_0400,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBI_0410,{0U,0U,0U}}, +{SUBI_0410,{1U,0U,0U}}, +{SUBI_0410,{2U,0U,0U}}, +{SUBI_0410,{3U,0U,0U}}, +{SUBI_0410,{4U,0U,0U}}, +{SUBI_0410,{5U,0U,0U}}, +{SUBI_0410,{6U,0U,0U}}, +{SUBI_0410,{7U,0U,0U}}, +{SUBI_0418,{0U,0U,0U}}, +{SUBI_0418,{1U,0U,0U}}, +{SUBI_0418,{2U,0U,0U}}, +{SUBI_0418,{3U,0U,0U}}, +{SUBI_0418,{4U,0U,0U}}, +{SUBI_0418,{5U,0U,0U}}, +{SUBI_0418,{6U,0U,0U}}, +{SUBI_0418,{7U,0U,0U}}, +{SUBI_0420,{0U,0U,0U}}, +{SUBI_0420,{1U,0U,0U}}, +{SUBI_0420,{2U,0U,0U}}, +{SUBI_0420,{3U,0U,0U}}, +{SUBI_0420,{4U,0U,0U}}, +{SUBI_0420,{5U,0U,0U}}, +{SUBI_0420,{6U,0U,0U}}, +{SUBI_0420,{7U,0U,0U}}, +{SUBI_0428,{0U,0U,0U}}, +{SUBI_0428,{1U,0U,0U}}, +{SUBI_0428,{2U,0U,0U}}, +{SUBI_0428,{3U,0U,0U}}, +{SUBI_0428,{4U,0U,0U}}, +{SUBI_0428,{5U,0U,0U}}, +{SUBI_0428,{6U,0U,0U}}, +{SUBI_0428,{7U,0U,0U}}, +{SUBI_0430,{0U,0U,0U}}, +{SUBI_0430,{1U,0U,0U}}, +{SUBI_0430,{2U,0U,0U}}, +{SUBI_0430,{3U,0U,0U}}, +{SUBI_0430,{4U,0U,0U}}, +{SUBI_0430,{5U,0U,0U}}, +{SUBI_0430,{6U,0U,0U}}, +{SUBI_0430,{7U,0U,0U}}, +{SUBI_0438,{0U,0U,0U}}, +{SUBI_0439,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBI_0440,{0U,0U,0U}}, +{SUBI_0440,{1U,0U,0U}}, +{SUBI_0440,{2U,0U,0U}}, +{SUBI_0440,{3U,0U,0U}}, +{SUBI_0440,{4U,0U,0U}}, +{SUBI_0440,{5U,0U,0U}}, +{SUBI_0440,{6U,0U,0U}}, +{SUBI_0440,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBI_0450,{0U,0U,0U}}, +{SUBI_0450,{1U,0U,0U}}, +{SUBI_0450,{2U,0U,0U}}, +{SUBI_0450,{3U,0U,0U}}, +{SUBI_0450,{4U,0U,0U}}, +{SUBI_0450,{5U,0U,0U}}, +{SUBI_0450,{6U,0U,0U}}, +{SUBI_0450,{7U,0U,0U}}, +{SUBI_0458,{0U,0U,0U}}, +{SUBI_0458,{1U,0U,0U}}, +{SUBI_0458,{2U,0U,0U}}, +{SUBI_0458,{3U,0U,0U}}, +{SUBI_0458,{4U,0U,0U}}, +{SUBI_0458,{5U,0U,0U}}, +{SUBI_0458,{6U,0U,0U}}, +{SUBI_0458,{7U,0U,0U}}, +{SUBI_0460,{0U,0U,0U}}, +{SUBI_0460,{1U,0U,0U}}, +{SUBI_0460,{2U,0U,0U}}, +{SUBI_0460,{3U,0U,0U}}, +{SUBI_0460,{4U,0U,0U}}, +{SUBI_0460,{5U,0U,0U}}, +{SUBI_0460,{6U,0U,0U}}, +{SUBI_0460,{7U,0U,0U}}, +{SUBI_0468,{0U,0U,0U}}, +{SUBI_0468,{1U,0U,0U}}, +{SUBI_0468,{2U,0U,0U}}, +{SUBI_0468,{3U,0U,0U}}, +{SUBI_0468,{4U,0U,0U}}, +{SUBI_0468,{5U,0U,0U}}, +{SUBI_0468,{6U,0U,0U}}, +{SUBI_0468,{7U,0U,0U}}, +{SUBI_0470,{0U,0U,0U}}, +{SUBI_0470,{1U,0U,0U}}, +{SUBI_0470,{2U,0U,0U}}, +{SUBI_0470,{3U,0U,0U}}, +{SUBI_0470,{4U,0U,0U}}, +{SUBI_0470,{5U,0U,0U}}, +{SUBI_0470,{6U,0U,0U}}, +{SUBI_0470,{7U,0U,0U}}, +{SUBI_0478,{0U,0U,0U}}, +{SUBI_0479,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBI_0480,{0U,0U,0U}}, +{SUBI_0480,{1U,0U,0U}}, +{SUBI_0480,{2U,0U,0U}}, +{SUBI_0480,{3U,0U,0U}}, +{SUBI_0480,{4U,0U,0U}}, +{SUBI_0480,{5U,0U,0U}}, +{SUBI_0480,{6U,0U,0U}}, +{SUBI_0480,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBI_0490,{0U,0U,0U}}, +{SUBI_0490,{1U,0U,0U}}, +{SUBI_0490,{2U,0U,0U}}, +{SUBI_0490,{3U,0U,0U}}, +{SUBI_0490,{4U,0U,0U}}, +{SUBI_0490,{5U,0U,0U}}, +{SUBI_0490,{6U,0U,0U}}, +{SUBI_0490,{7U,0U,0U}}, +{SUBI_0498,{0U,0U,0U}}, +{SUBI_0498,{1U,0U,0U}}, +{SUBI_0498,{2U,0U,0U}}, +{SUBI_0498,{3U,0U,0U}}, +{SUBI_0498,{4U,0U,0U}}, +{SUBI_0498,{5U,0U,0U}}, +{SUBI_0498,{6U,0U,0U}}, +{SUBI_0498,{7U,0U,0U}}, +{SUBI_04A0,{0U,0U,0U}}, +{SUBI_04A0,{1U,0U,0U}}, +{SUBI_04A0,{2U,0U,0U}}, +{SUBI_04A0,{3U,0U,0U}}, +{SUBI_04A0,{4U,0U,0U}}, +{SUBI_04A0,{5U,0U,0U}}, +{SUBI_04A0,{6U,0U,0U}}, +{SUBI_04A0,{7U,0U,0U}}, +{SUBI_04A8,{0U,0U,0U}}, +{SUBI_04A8,{1U,0U,0U}}, +{SUBI_04A8,{2U,0U,0U}}, +{SUBI_04A8,{3U,0U,0U}}, +{SUBI_04A8,{4U,0U,0U}}, +{SUBI_04A8,{5U,0U,0U}}, +{SUBI_04A8,{6U,0U,0U}}, +{SUBI_04A8,{7U,0U,0U}}, +{SUBI_04B0,{0U,0U,0U}}, +{SUBI_04B0,{1U,0U,0U}}, +{SUBI_04B0,{2U,0U,0U}}, +{SUBI_04B0,{3U,0U,0U}}, +{SUBI_04B0,{4U,0U,0U}}, +{SUBI_04B0,{5U,0U,0U}}, +{SUBI_04B0,{6U,0U,0U}}, +{SUBI_04B0,{7U,0U,0U}}, +{SUBI_04B8,{0U,0U,0U}}, +{SUBI_04B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHKCMP2_04D0,{0U,0U,0U}}, +{CHKCMP2_04D0,{1U,0U,0U}}, +{CHKCMP2_04D0,{2U,0U,0U}}, +{CHKCMP2_04D0,{3U,0U,0U}}, +{CHKCMP2_04D0,{4U,0U,0U}}, +{CHKCMP2_04D0,{5U,0U,0U}}, +{CHKCMP2_04D0,{6U,0U,0U}}, +{CHKCMP2_04D0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHKCMP2_04E8,{0U,0U,0U}}, +{CHKCMP2_04E8,{1U,0U,0U}}, +{CHKCMP2_04E8,{2U,0U,0U}}, +{CHKCMP2_04E8,{3U,0U,0U}}, +{CHKCMP2_04E8,{4U,0U,0U}}, +{CHKCMP2_04E8,{5U,0U,0U}}, +{CHKCMP2_04E8,{6U,0U,0U}}, +{CHKCMP2_04E8,{7U,0U,0U}}, +{CHKCMP2_04F0,{0U,0U,0U}}, +{CHKCMP2_04F0,{1U,0U,0U}}, +{CHKCMP2_04F0,{2U,0U,0U}}, +{CHKCMP2_04F0,{3U,0U,0U}}, +{CHKCMP2_04F0,{4U,0U,0U}}, +{CHKCMP2_04F0,{5U,0U,0U}}, +{CHKCMP2_04F0,{6U,0U,0U}}, +{CHKCMP2_04F0,{7U,0U,0U}}, +{CHKCMP2_04F8,{0U,0U,0U}}, +{CHKCMP2_04F9,{0U,0U,0U}}, +{CHKCMP2_04FA,{0U,0U,0U}}, +{CHKCMP2_04FB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0100,{0U,2U,0U}}, +{BTST_0100,{1U,2U,0U}}, +{BTST_0100,{2U,2U,0U}}, +{BTST_0100,{3U,2U,0U}}, +{BTST_0100,{4U,2U,0U}}, +{BTST_0100,{5U,2U,0U}}, +{BTST_0100,{6U,2U,0U}}, +{BTST_0100,{7U,2U,0U}}, +{MOVEP_0108,{2U,0U,0U}}, +{MOVEP_0108,{2U,1U,0U}}, +{MOVEP_0108,{2U,2U,0U}}, +{MOVEP_0108,{2U,3U,0U}}, +{MOVEP_0108,{2U,4U,0U}}, +{MOVEP_0108,{2U,5U,0U}}, +{MOVEP_0108,{2U,6U,0U}}, +{MOVEP_0108,{2U,7U,0U}}, +{BTST_0110,{0U,2U,0U}}, +{BTST_0110,{1U,2U,0U}}, +{BTST_0110,{2U,2U,0U}}, +{BTST_0110,{3U,2U,0U}}, +{BTST_0110,{4U,2U,0U}}, +{BTST_0110,{5U,2U,0U}}, +{BTST_0110,{6U,2U,0U}}, +{BTST_0110,{7U,2U,0U}}, +{BTST_0118,{0U,2U,0U}}, +{BTST_0118,{1U,2U,0U}}, +{BTST_0118,{2U,2U,0U}}, +{BTST_0118,{3U,2U,0U}}, +{BTST_0118,{4U,2U,0U}}, +{BTST_0118,{5U,2U,0U}}, +{BTST_0118,{6U,2U,0U}}, +{BTST_0118,{7U,2U,0U}}, +{BTST_0120,{0U,2U,0U}}, +{BTST_0120,{1U,2U,0U}}, +{BTST_0120,{2U,2U,0U}}, +{BTST_0120,{3U,2U,0U}}, +{BTST_0120,{4U,2U,0U}}, +{BTST_0120,{5U,2U,0U}}, +{BTST_0120,{6U,2U,0U}}, +{BTST_0120,{7U,2U,0U}}, +{BTST_0128,{0U,2U,0U}}, +{BTST_0128,{1U,2U,0U}}, +{BTST_0128,{2U,2U,0U}}, +{BTST_0128,{3U,2U,0U}}, +{BTST_0128,{4U,2U,0U}}, +{BTST_0128,{5U,2U,0U}}, +{BTST_0128,{6U,2U,0U}}, +{BTST_0128,{7U,2U,0U}}, +{BTST_0130,{0U,2U,0U}}, +{BTST_0130,{1U,2U,0U}}, +{BTST_0130,{2U,2U,0U}}, +{BTST_0130,{3U,2U,0U}}, +{BTST_0130,{4U,2U,0U}}, +{BTST_0130,{5U,2U,0U}}, +{BTST_0130,{6U,2U,0U}}, +{BTST_0130,{7U,2U,0U}}, +{BTST_0138,{0U,2U,0U}}, +{BTST_0139,{0U,2U,0U}}, +{BTST_013A,{0U,2U,0U}}, +{BTST_013B,{0U,2U,0U}}, +{BTST_013C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0140,{0U,2U,0U}}, +{BCHG_0140,{1U,2U,0U}}, +{BCHG_0140,{2U,2U,0U}}, +{BCHG_0140,{3U,2U,0U}}, +{BCHG_0140,{4U,2U,0U}}, +{BCHG_0140,{5U,2U,0U}}, +{BCHG_0140,{6U,2U,0U}}, +{BCHG_0140,{7U,2U,0U}}, +{MOVEP_0148,{2U,0U,0U}}, +{MOVEP_0148,{2U,1U,0U}}, +{MOVEP_0148,{2U,2U,0U}}, +{MOVEP_0148,{2U,3U,0U}}, +{MOVEP_0148,{2U,4U,0U}}, +{MOVEP_0148,{2U,5U,0U}}, +{MOVEP_0148,{2U,6U,0U}}, +{MOVEP_0148,{2U,7U,0U}}, +{BCHG_0150,{0U,2U,0U}}, +{BCHG_0150,{1U,2U,0U}}, +{BCHG_0150,{2U,2U,0U}}, +{BCHG_0150,{3U,2U,0U}}, +{BCHG_0150,{4U,2U,0U}}, +{BCHG_0150,{5U,2U,0U}}, +{BCHG_0150,{6U,2U,0U}}, +{BCHG_0150,{7U,2U,0U}}, +{BCHG_0158,{0U,2U,0U}}, +{BCHG_0158,{1U,2U,0U}}, +{BCHG_0158,{2U,2U,0U}}, +{BCHG_0158,{3U,2U,0U}}, +{BCHG_0158,{4U,2U,0U}}, +{BCHG_0158,{5U,2U,0U}}, +{BCHG_0158,{6U,2U,0U}}, +{BCHG_0158,{7U,2U,0U}}, +{BCHG_0160,{0U,2U,0U}}, +{BCHG_0160,{1U,2U,0U}}, +{BCHG_0160,{2U,2U,0U}}, +{BCHG_0160,{3U,2U,0U}}, +{BCHG_0160,{4U,2U,0U}}, +{BCHG_0160,{5U,2U,0U}}, +{BCHG_0160,{6U,2U,0U}}, +{BCHG_0160,{7U,2U,0U}}, +{BCHG_0168,{0U,2U,0U}}, +{BCHG_0168,{1U,2U,0U}}, +{BCHG_0168,{2U,2U,0U}}, +{BCHG_0168,{3U,2U,0U}}, +{BCHG_0168,{4U,2U,0U}}, +{BCHG_0168,{5U,2U,0U}}, +{BCHG_0168,{6U,2U,0U}}, +{BCHG_0168,{7U,2U,0U}}, +{BCHG_0170,{0U,2U,0U}}, +{BCHG_0170,{1U,2U,0U}}, +{BCHG_0170,{2U,2U,0U}}, +{BCHG_0170,{3U,2U,0U}}, +{BCHG_0170,{4U,2U,0U}}, +{BCHG_0170,{5U,2U,0U}}, +{BCHG_0170,{6U,2U,0U}}, +{BCHG_0170,{7U,2U,0U}}, +{BCHG_0178,{0U,2U,0U}}, +{BCHG_0179,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0180,{0U,2U,0U}}, +{BCLR_0180,{1U,2U,0U}}, +{BCLR_0180,{2U,2U,0U}}, +{BCLR_0180,{3U,2U,0U}}, +{BCLR_0180,{4U,2U,0U}}, +{BCLR_0180,{5U,2U,0U}}, +{BCLR_0180,{6U,2U,0U}}, +{BCLR_0180,{7U,2U,0U}}, +{MOVEP_0188,{2U,0U,0U}}, +{MOVEP_0188,{2U,1U,0U}}, +{MOVEP_0188,{2U,2U,0U}}, +{MOVEP_0188,{2U,3U,0U}}, +{MOVEP_0188,{2U,4U,0U}}, +{MOVEP_0188,{2U,5U,0U}}, +{MOVEP_0188,{2U,6U,0U}}, +{MOVEP_0188,{2U,7U,0U}}, +{BCLR_0190,{0U,2U,0U}}, +{BCLR_0190,{1U,2U,0U}}, +{BCLR_0190,{2U,2U,0U}}, +{BCLR_0190,{3U,2U,0U}}, +{BCLR_0190,{4U,2U,0U}}, +{BCLR_0190,{5U,2U,0U}}, +{BCLR_0190,{6U,2U,0U}}, +{BCLR_0190,{7U,2U,0U}}, +{BCLR_0198,{0U,2U,0U}}, +{BCLR_0198,{1U,2U,0U}}, +{BCLR_0198,{2U,2U,0U}}, +{BCLR_0198,{3U,2U,0U}}, +{BCLR_0198,{4U,2U,0U}}, +{BCLR_0198,{5U,2U,0U}}, +{BCLR_0198,{6U,2U,0U}}, +{BCLR_0198,{7U,2U,0U}}, +{BCLR_01A0,{0U,2U,0U}}, +{BCLR_01A0,{1U,2U,0U}}, +{BCLR_01A0,{2U,2U,0U}}, +{BCLR_01A0,{3U,2U,0U}}, +{BCLR_01A0,{4U,2U,0U}}, +{BCLR_01A0,{5U,2U,0U}}, +{BCLR_01A0,{6U,2U,0U}}, +{BCLR_01A0,{7U,2U,0U}}, +{BCLR_01A8,{0U,2U,0U}}, +{BCLR_01A8,{1U,2U,0U}}, +{BCLR_01A8,{2U,2U,0U}}, +{BCLR_01A8,{3U,2U,0U}}, +{BCLR_01A8,{4U,2U,0U}}, +{BCLR_01A8,{5U,2U,0U}}, +{BCLR_01A8,{6U,2U,0U}}, +{BCLR_01A8,{7U,2U,0U}}, +{BCLR_01B0,{0U,2U,0U}}, +{BCLR_01B0,{1U,2U,0U}}, +{BCLR_01B0,{2U,2U,0U}}, +{BCLR_01B0,{3U,2U,0U}}, +{BCLR_01B0,{4U,2U,0U}}, +{BCLR_01B0,{5U,2U,0U}}, +{BCLR_01B0,{6U,2U,0U}}, +{BCLR_01B0,{7U,2U,0U}}, +{BCLR_01B8,{0U,2U,0U}}, +{BCLR_01B9,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_01C0,{0U,2U,0U}}, +{BSET_01C0,{1U,2U,0U}}, +{BSET_01C0,{2U,2U,0U}}, +{BSET_01C0,{3U,2U,0U}}, +{BSET_01C0,{4U,2U,0U}}, +{BSET_01C0,{5U,2U,0U}}, +{BSET_01C0,{6U,2U,0U}}, +{BSET_01C0,{7U,2U,0U}}, +{MOVEP_01C8,{2U,0U,0U}}, +{MOVEP_01C8,{2U,1U,0U}}, +{MOVEP_01C8,{2U,2U,0U}}, +{MOVEP_01C8,{2U,3U,0U}}, +{MOVEP_01C8,{2U,4U,0U}}, +{MOVEP_01C8,{2U,5U,0U}}, +{MOVEP_01C8,{2U,6U,0U}}, +{MOVEP_01C8,{2U,7U,0U}}, +{BSET_01D0,{0U,2U,0U}}, +{BSET_01D0,{1U,2U,0U}}, +{BSET_01D0,{2U,2U,0U}}, +{BSET_01D0,{3U,2U,0U}}, +{BSET_01D0,{4U,2U,0U}}, +{BSET_01D0,{5U,2U,0U}}, +{BSET_01D0,{6U,2U,0U}}, +{BSET_01D0,{7U,2U,0U}}, +{BSET_01D8,{0U,2U,0U}}, +{BSET_01D8,{1U,2U,0U}}, +{BSET_01D8,{2U,2U,0U}}, +{BSET_01D8,{3U,2U,0U}}, +{BSET_01D8,{4U,2U,0U}}, +{BSET_01D8,{5U,2U,0U}}, +{BSET_01D8,{6U,2U,0U}}, +{BSET_01D8,{7U,2U,0U}}, +{BSET_01E0,{0U,2U,0U}}, +{BSET_01E0,{1U,2U,0U}}, +{BSET_01E0,{2U,2U,0U}}, +{BSET_01E0,{3U,2U,0U}}, +{BSET_01E0,{4U,2U,0U}}, +{BSET_01E0,{5U,2U,0U}}, +{BSET_01E0,{6U,2U,0U}}, +{BSET_01E0,{7U,2U,0U}}, +{BSET_01E8,{0U,2U,0U}}, +{BSET_01E8,{1U,2U,0U}}, +{BSET_01E8,{2U,2U,0U}}, +{BSET_01E8,{3U,2U,0U}}, +{BSET_01E8,{4U,2U,0U}}, +{BSET_01E8,{5U,2U,0U}}, +{BSET_01E8,{6U,2U,0U}}, +{BSET_01E8,{7U,2U,0U}}, +{BSET_01F0,{0U,2U,0U}}, +{BSET_01F0,{1U,2U,0U}}, +{BSET_01F0,{2U,2U,0U}}, +{BSET_01F0,{3U,2U,0U}}, +{BSET_01F0,{4U,2U,0U}}, +{BSET_01F0,{5U,2U,0U}}, +{BSET_01F0,{6U,2U,0U}}, +{BSET_01F0,{7U,2U,0U}}, +{BSET_01F8,{0U,2U,0U}}, +{BSET_01F9,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDI_0600,{0U,0U,0U}}, +{ADDI_0600,{1U,0U,0U}}, +{ADDI_0600,{2U,0U,0U}}, +{ADDI_0600,{3U,0U,0U}}, +{ADDI_0600,{4U,0U,0U}}, +{ADDI_0600,{5U,0U,0U}}, +{ADDI_0600,{6U,0U,0U}}, +{ADDI_0600,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDI_0610,{0U,0U,0U}}, +{ADDI_0610,{1U,0U,0U}}, +{ADDI_0610,{2U,0U,0U}}, +{ADDI_0610,{3U,0U,0U}}, +{ADDI_0610,{4U,0U,0U}}, +{ADDI_0610,{5U,0U,0U}}, +{ADDI_0610,{6U,0U,0U}}, +{ADDI_0610,{7U,0U,0U}}, +{ADDI_0618,{0U,0U,0U}}, +{ADDI_0618,{1U,0U,0U}}, +{ADDI_0618,{2U,0U,0U}}, +{ADDI_0618,{3U,0U,0U}}, +{ADDI_0618,{4U,0U,0U}}, +{ADDI_0618,{5U,0U,0U}}, +{ADDI_0618,{6U,0U,0U}}, +{ADDI_0618,{7U,0U,0U}}, +{ADDI_0620,{0U,0U,0U}}, +{ADDI_0620,{1U,0U,0U}}, +{ADDI_0620,{2U,0U,0U}}, +{ADDI_0620,{3U,0U,0U}}, +{ADDI_0620,{4U,0U,0U}}, +{ADDI_0620,{5U,0U,0U}}, +{ADDI_0620,{6U,0U,0U}}, +{ADDI_0620,{7U,0U,0U}}, +{ADDI_0628,{0U,0U,0U}}, +{ADDI_0628,{1U,0U,0U}}, +{ADDI_0628,{2U,0U,0U}}, +{ADDI_0628,{3U,0U,0U}}, +{ADDI_0628,{4U,0U,0U}}, +{ADDI_0628,{5U,0U,0U}}, +{ADDI_0628,{6U,0U,0U}}, +{ADDI_0628,{7U,0U,0U}}, +{ADDI_0630,{0U,0U,0U}}, +{ADDI_0630,{1U,0U,0U}}, +{ADDI_0630,{2U,0U,0U}}, +{ADDI_0630,{3U,0U,0U}}, +{ADDI_0630,{4U,0U,0U}}, +{ADDI_0630,{5U,0U,0U}}, +{ADDI_0630,{6U,0U,0U}}, +{ADDI_0630,{7U,0U,0U}}, +{ADDI_0638,{0U,0U,0U}}, +{ADDI_0639,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDI_0640,{0U,0U,0U}}, +{ADDI_0640,{1U,0U,0U}}, +{ADDI_0640,{2U,0U,0U}}, +{ADDI_0640,{3U,0U,0U}}, +{ADDI_0640,{4U,0U,0U}}, +{ADDI_0640,{5U,0U,0U}}, +{ADDI_0640,{6U,0U,0U}}, +{ADDI_0640,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDI_0650,{0U,0U,0U}}, +{ADDI_0650,{1U,0U,0U}}, +{ADDI_0650,{2U,0U,0U}}, +{ADDI_0650,{3U,0U,0U}}, +{ADDI_0650,{4U,0U,0U}}, +{ADDI_0650,{5U,0U,0U}}, +{ADDI_0650,{6U,0U,0U}}, +{ADDI_0650,{7U,0U,0U}}, +{ADDI_0658,{0U,0U,0U}}, +{ADDI_0658,{1U,0U,0U}}, +{ADDI_0658,{2U,0U,0U}}, +{ADDI_0658,{3U,0U,0U}}, +{ADDI_0658,{4U,0U,0U}}, +{ADDI_0658,{5U,0U,0U}}, +{ADDI_0658,{6U,0U,0U}}, +{ADDI_0658,{7U,0U,0U}}, +{ADDI_0660,{0U,0U,0U}}, +{ADDI_0660,{1U,0U,0U}}, +{ADDI_0660,{2U,0U,0U}}, +{ADDI_0660,{3U,0U,0U}}, +{ADDI_0660,{4U,0U,0U}}, +{ADDI_0660,{5U,0U,0U}}, +{ADDI_0660,{6U,0U,0U}}, +{ADDI_0660,{7U,0U,0U}}, +{ADDI_0668,{0U,0U,0U}}, +{ADDI_0668,{1U,0U,0U}}, +{ADDI_0668,{2U,0U,0U}}, +{ADDI_0668,{3U,0U,0U}}, +{ADDI_0668,{4U,0U,0U}}, +{ADDI_0668,{5U,0U,0U}}, +{ADDI_0668,{6U,0U,0U}}, +{ADDI_0668,{7U,0U,0U}}, +{ADDI_0670,{0U,0U,0U}}, +{ADDI_0670,{1U,0U,0U}}, +{ADDI_0670,{2U,0U,0U}}, +{ADDI_0670,{3U,0U,0U}}, +{ADDI_0670,{4U,0U,0U}}, +{ADDI_0670,{5U,0U,0U}}, +{ADDI_0670,{6U,0U,0U}}, +{ADDI_0670,{7U,0U,0U}}, +{ADDI_0678,{0U,0U,0U}}, +{ADDI_0679,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDI_0680,{0U,0U,0U}}, +{ADDI_0680,{1U,0U,0U}}, +{ADDI_0680,{2U,0U,0U}}, +{ADDI_0680,{3U,0U,0U}}, +{ADDI_0680,{4U,0U,0U}}, +{ADDI_0680,{5U,0U,0U}}, +{ADDI_0680,{6U,0U,0U}}, +{ADDI_0680,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDI_0690,{0U,0U,0U}}, +{ADDI_0690,{1U,0U,0U}}, +{ADDI_0690,{2U,0U,0U}}, +{ADDI_0690,{3U,0U,0U}}, +{ADDI_0690,{4U,0U,0U}}, +{ADDI_0690,{5U,0U,0U}}, +{ADDI_0690,{6U,0U,0U}}, +{ADDI_0690,{7U,0U,0U}}, +{ADDI_0698,{0U,0U,0U}}, +{ADDI_0698,{1U,0U,0U}}, +{ADDI_0698,{2U,0U,0U}}, +{ADDI_0698,{3U,0U,0U}}, +{ADDI_0698,{4U,0U,0U}}, +{ADDI_0698,{5U,0U,0U}}, +{ADDI_0698,{6U,0U,0U}}, +{ADDI_0698,{7U,0U,0U}}, +{ADDI_06A0,{0U,0U,0U}}, +{ADDI_06A0,{1U,0U,0U}}, +{ADDI_06A0,{2U,0U,0U}}, +{ADDI_06A0,{3U,0U,0U}}, +{ADDI_06A0,{4U,0U,0U}}, +{ADDI_06A0,{5U,0U,0U}}, +{ADDI_06A0,{6U,0U,0U}}, +{ADDI_06A0,{7U,0U,0U}}, +{ADDI_06A8,{0U,0U,0U}}, +{ADDI_06A8,{1U,0U,0U}}, +{ADDI_06A8,{2U,0U,0U}}, +{ADDI_06A8,{3U,0U,0U}}, +{ADDI_06A8,{4U,0U,0U}}, +{ADDI_06A8,{5U,0U,0U}}, +{ADDI_06A8,{6U,0U,0U}}, +{ADDI_06A8,{7U,0U,0U}}, +{ADDI_06B0,{0U,0U,0U}}, +{ADDI_06B0,{1U,0U,0U}}, +{ADDI_06B0,{2U,0U,0U}}, +{ADDI_06B0,{3U,0U,0U}}, +{ADDI_06B0,{4U,0U,0U}}, +{ADDI_06B0,{5U,0U,0U}}, +{ADDI_06B0,{6U,0U,0U}}, +{ADDI_06B0,{7U,0U,0U}}, +{ADDI_06B8,{0U,0U,0U}}, +{ADDI_06B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{RTM_06C0,{0U,0U,0U}}, +{RTM_06C0,{0U,1U,0U}}, +{RTM_06C0,{0U,2U,0U}}, +{RTM_06C0,{0U,3U,0U}}, +{RTM_06C0,{0U,4U,0U}}, +{RTM_06C0,{0U,5U,0U}}, +{RTM_06C0,{0U,6U,0U}}, +{RTM_06C0,{0U,7U,0U}}, +{RTM_06C0,{1U,0U,0U}}, +{RTM_06C0,{1U,1U,0U}}, +{RTM_06C0,{1U,2U,0U}}, +{RTM_06C0,{1U,3U,0U}}, +{RTM_06C0,{1U,4U,0U}}, +{RTM_06C0,{1U,5U,0U}}, +{RTM_06C0,{1U,6U,0U}}, +{RTM_06C0,{1U,7U,0U}}, +{CALLM_06D0,{0U,0U,0U}}, +{CALLM_06D0,{1U,0U,0U}}, +{CALLM_06D0,{2U,0U,0U}}, +{CALLM_06D0,{3U,0U,0U}}, +{CALLM_06D0,{4U,0U,0U}}, +{CALLM_06D0,{5U,0U,0U}}, +{CALLM_06D0,{6U,0U,0U}}, +{CALLM_06D0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CALLM_06E8,{0U,0U,0U}}, +{CALLM_06E8,{1U,0U,0U}}, +{CALLM_06E8,{2U,0U,0U}}, +{CALLM_06E8,{3U,0U,0U}}, +{CALLM_06E8,{4U,0U,0U}}, +{CALLM_06E8,{5U,0U,0U}}, +{CALLM_06E8,{6U,0U,0U}}, +{CALLM_06E8,{7U,0U,0U}}, +{CALLM_06F0,{0U,0U,0U}}, +{CALLM_06F0,{1U,0U,0U}}, +{CALLM_06F0,{2U,0U,0U}}, +{CALLM_06F0,{3U,0U,0U}}, +{CALLM_06F0,{4U,0U,0U}}, +{CALLM_06F0,{5U,0U,0U}}, +{CALLM_06F0,{6U,0U,0U}}, +{CALLM_06F0,{7U,0U,0U}}, +{CALLM_06F8,{0U,0U,0U}}, +{CALLM_06F9,{0U,0U,0U}}, +{CALLM_06FA,{0U,0U,0U}}, +{CALLM_06FB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0100,{0U,3U,0U}}, +{BTST_0100,{1U,3U,0U}}, +{BTST_0100,{2U,3U,0U}}, +{BTST_0100,{3U,3U,0U}}, +{BTST_0100,{4U,3U,0U}}, +{BTST_0100,{5U,3U,0U}}, +{BTST_0100,{6U,3U,0U}}, +{BTST_0100,{7U,3U,0U}}, +{MOVEP_0108,{3U,0U,0U}}, +{MOVEP_0108,{3U,1U,0U}}, +{MOVEP_0108,{3U,2U,0U}}, +{MOVEP_0108,{3U,3U,0U}}, +{MOVEP_0108,{3U,4U,0U}}, +{MOVEP_0108,{3U,5U,0U}}, +{MOVEP_0108,{3U,6U,0U}}, +{MOVEP_0108,{3U,7U,0U}}, +{BTST_0110,{0U,3U,0U}}, +{BTST_0110,{1U,3U,0U}}, +{BTST_0110,{2U,3U,0U}}, +{BTST_0110,{3U,3U,0U}}, +{BTST_0110,{4U,3U,0U}}, +{BTST_0110,{5U,3U,0U}}, +{BTST_0110,{6U,3U,0U}}, +{BTST_0110,{7U,3U,0U}}, +{BTST_0118,{0U,3U,0U}}, +{BTST_0118,{1U,3U,0U}}, +{BTST_0118,{2U,3U,0U}}, +{BTST_0118,{3U,3U,0U}}, +{BTST_0118,{4U,3U,0U}}, +{BTST_0118,{5U,3U,0U}}, +{BTST_0118,{6U,3U,0U}}, +{BTST_0118,{7U,3U,0U}}, +{BTST_0120,{0U,3U,0U}}, +{BTST_0120,{1U,3U,0U}}, +{BTST_0120,{2U,3U,0U}}, +{BTST_0120,{3U,3U,0U}}, +{BTST_0120,{4U,3U,0U}}, +{BTST_0120,{5U,3U,0U}}, +{BTST_0120,{6U,3U,0U}}, +{BTST_0120,{7U,3U,0U}}, +{BTST_0128,{0U,3U,0U}}, +{BTST_0128,{1U,3U,0U}}, +{BTST_0128,{2U,3U,0U}}, +{BTST_0128,{3U,3U,0U}}, +{BTST_0128,{4U,3U,0U}}, +{BTST_0128,{5U,3U,0U}}, +{BTST_0128,{6U,3U,0U}}, +{BTST_0128,{7U,3U,0U}}, +{BTST_0130,{0U,3U,0U}}, +{BTST_0130,{1U,3U,0U}}, +{BTST_0130,{2U,3U,0U}}, +{BTST_0130,{3U,3U,0U}}, +{BTST_0130,{4U,3U,0U}}, +{BTST_0130,{5U,3U,0U}}, +{BTST_0130,{6U,3U,0U}}, +{BTST_0130,{7U,3U,0U}}, +{BTST_0138,{0U,3U,0U}}, +{BTST_0139,{0U,3U,0U}}, +{BTST_013A,{0U,3U,0U}}, +{BTST_013B,{0U,3U,0U}}, +{BTST_013C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0140,{0U,3U,0U}}, +{BCHG_0140,{1U,3U,0U}}, +{BCHG_0140,{2U,3U,0U}}, +{BCHG_0140,{3U,3U,0U}}, +{BCHG_0140,{4U,3U,0U}}, +{BCHG_0140,{5U,3U,0U}}, +{BCHG_0140,{6U,3U,0U}}, +{BCHG_0140,{7U,3U,0U}}, +{MOVEP_0148,{3U,0U,0U}}, +{MOVEP_0148,{3U,1U,0U}}, +{MOVEP_0148,{3U,2U,0U}}, +{MOVEP_0148,{3U,3U,0U}}, +{MOVEP_0148,{3U,4U,0U}}, +{MOVEP_0148,{3U,5U,0U}}, +{MOVEP_0148,{3U,6U,0U}}, +{MOVEP_0148,{3U,7U,0U}}, +{BCHG_0150,{0U,3U,0U}}, +{BCHG_0150,{1U,3U,0U}}, +{BCHG_0150,{2U,3U,0U}}, +{BCHG_0150,{3U,3U,0U}}, +{BCHG_0150,{4U,3U,0U}}, +{BCHG_0150,{5U,3U,0U}}, +{BCHG_0150,{6U,3U,0U}}, +{BCHG_0150,{7U,3U,0U}}, +{BCHG_0158,{0U,3U,0U}}, +{BCHG_0158,{1U,3U,0U}}, +{BCHG_0158,{2U,3U,0U}}, +{BCHG_0158,{3U,3U,0U}}, +{BCHG_0158,{4U,3U,0U}}, +{BCHG_0158,{5U,3U,0U}}, +{BCHG_0158,{6U,3U,0U}}, +{BCHG_0158,{7U,3U,0U}}, +{BCHG_0160,{0U,3U,0U}}, +{BCHG_0160,{1U,3U,0U}}, +{BCHG_0160,{2U,3U,0U}}, +{BCHG_0160,{3U,3U,0U}}, +{BCHG_0160,{4U,3U,0U}}, +{BCHG_0160,{5U,3U,0U}}, +{BCHG_0160,{6U,3U,0U}}, +{BCHG_0160,{7U,3U,0U}}, +{BCHG_0168,{0U,3U,0U}}, +{BCHG_0168,{1U,3U,0U}}, +{BCHG_0168,{2U,3U,0U}}, +{BCHG_0168,{3U,3U,0U}}, +{BCHG_0168,{4U,3U,0U}}, +{BCHG_0168,{5U,3U,0U}}, +{BCHG_0168,{6U,3U,0U}}, +{BCHG_0168,{7U,3U,0U}}, +{BCHG_0170,{0U,3U,0U}}, +{BCHG_0170,{1U,3U,0U}}, +{BCHG_0170,{2U,3U,0U}}, +{BCHG_0170,{3U,3U,0U}}, +{BCHG_0170,{4U,3U,0U}}, +{BCHG_0170,{5U,3U,0U}}, +{BCHG_0170,{6U,3U,0U}}, +{BCHG_0170,{7U,3U,0U}}, +{BCHG_0178,{0U,3U,0U}}, +{BCHG_0179,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0180,{0U,3U,0U}}, +{BCLR_0180,{1U,3U,0U}}, +{BCLR_0180,{2U,3U,0U}}, +{BCLR_0180,{3U,3U,0U}}, +{BCLR_0180,{4U,3U,0U}}, +{BCLR_0180,{5U,3U,0U}}, +{BCLR_0180,{6U,3U,0U}}, +{BCLR_0180,{7U,3U,0U}}, +{MOVEP_0188,{3U,0U,0U}}, +{MOVEP_0188,{3U,1U,0U}}, +{MOVEP_0188,{3U,2U,0U}}, +{MOVEP_0188,{3U,3U,0U}}, +{MOVEP_0188,{3U,4U,0U}}, +{MOVEP_0188,{3U,5U,0U}}, +{MOVEP_0188,{3U,6U,0U}}, +{MOVEP_0188,{3U,7U,0U}}, +{BCLR_0190,{0U,3U,0U}}, +{BCLR_0190,{1U,3U,0U}}, +{BCLR_0190,{2U,3U,0U}}, +{BCLR_0190,{3U,3U,0U}}, +{BCLR_0190,{4U,3U,0U}}, +{BCLR_0190,{5U,3U,0U}}, +{BCLR_0190,{6U,3U,0U}}, +{BCLR_0190,{7U,3U,0U}}, +{BCLR_0198,{0U,3U,0U}}, +{BCLR_0198,{1U,3U,0U}}, +{BCLR_0198,{2U,3U,0U}}, +{BCLR_0198,{3U,3U,0U}}, +{BCLR_0198,{4U,3U,0U}}, +{BCLR_0198,{5U,3U,0U}}, +{BCLR_0198,{6U,3U,0U}}, +{BCLR_0198,{7U,3U,0U}}, +{BCLR_01A0,{0U,3U,0U}}, +{BCLR_01A0,{1U,3U,0U}}, +{BCLR_01A0,{2U,3U,0U}}, +{BCLR_01A0,{3U,3U,0U}}, +{BCLR_01A0,{4U,3U,0U}}, +{BCLR_01A0,{5U,3U,0U}}, +{BCLR_01A0,{6U,3U,0U}}, +{BCLR_01A0,{7U,3U,0U}}, +{BCLR_01A8,{0U,3U,0U}}, +{BCLR_01A8,{1U,3U,0U}}, +{BCLR_01A8,{2U,3U,0U}}, +{BCLR_01A8,{3U,3U,0U}}, +{BCLR_01A8,{4U,3U,0U}}, +{BCLR_01A8,{5U,3U,0U}}, +{BCLR_01A8,{6U,3U,0U}}, +{BCLR_01A8,{7U,3U,0U}}, +{BCLR_01B0,{0U,3U,0U}}, +{BCLR_01B0,{1U,3U,0U}}, +{BCLR_01B0,{2U,3U,0U}}, +{BCLR_01B0,{3U,3U,0U}}, +{BCLR_01B0,{4U,3U,0U}}, +{BCLR_01B0,{5U,3U,0U}}, +{BCLR_01B0,{6U,3U,0U}}, +{BCLR_01B0,{7U,3U,0U}}, +{BCLR_01B8,{0U,3U,0U}}, +{BCLR_01B9,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_01C0,{0U,3U,0U}}, +{BSET_01C0,{1U,3U,0U}}, +{BSET_01C0,{2U,3U,0U}}, +{BSET_01C0,{3U,3U,0U}}, +{BSET_01C0,{4U,3U,0U}}, +{BSET_01C0,{5U,3U,0U}}, +{BSET_01C0,{6U,3U,0U}}, +{BSET_01C0,{7U,3U,0U}}, +{MOVEP_01C8,{3U,0U,0U}}, +{MOVEP_01C8,{3U,1U,0U}}, +{MOVEP_01C8,{3U,2U,0U}}, +{MOVEP_01C8,{3U,3U,0U}}, +{MOVEP_01C8,{3U,4U,0U}}, +{MOVEP_01C8,{3U,5U,0U}}, +{MOVEP_01C8,{3U,6U,0U}}, +{MOVEP_01C8,{3U,7U,0U}}, +{BSET_01D0,{0U,3U,0U}}, +{BSET_01D0,{1U,3U,0U}}, +{BSET_01D0,{2U,3U,0U}}, +{BSET_01D0,{3U,3U,0U}}, +{BSET_01D0,{4U,3U,0U}}, +{BSET_01D0,{5U,3U,0U}}, +{BSET_01D0,{6U,3U,0U}}, +{BSET_01D0,{7U,3U,0U}}, +{BSET_01D8,{0U,3U,0U}}, +{BSET_01D8,{1U,3U,0U}}, +{BSET_01D8,{2U,3U,0U}}, +{BSET_01D8,{3U,3U,0U}}, +{BSET_01D8,{4U,3U,0U}}, +{BSET_01D8,{5U,3U,0U}}, +{BSET_01D8,{6U,3U,0U}}, +{BSET_01D8,{7U,3U,0U}}, +{BSET_01E0,{0U,3U,0U}}, +{BSET_01E0,{1U,3U,0U}}, +{BSET_01E0,{2U,3U,0U}}, +{BSET_01E0,{3U,3U,0U}}, +{BSET_01E0,{4U,3U,0U}}, +{BSET_01E0,{5U,3U,0U}}, +{BSET_01E0,{6U,3U,0U}}, +{BSET_01E0,{7U,3U,0U}}, +{BSET_01E8,{0U,3U,0U}}, +{BSET_01E8,{1U,3U,0U}}, +{BSET_01E8,{2U,3U,0U}}, +{BSET_01E8,{3U,3U,0U}}, +{BSET_01E8,{4U,3U,0U}}, +{BSET_01E8,{5U,3U,0U}}, +{BSET_01E8,{6U,3U,0U}}, +{BSET_01E8,{7U,3U,0U}}, +{BSET_01F0,{0U,3U,0U}}, +{BSET_01F0,{1U,3U,0U}}, +{BSET_01F0,{2U,3U,0U}}, +{BSET_01F0,{3U,3U,0U}}, +{BSET_01F0,{4U,3U,0U}}, +{BSET_01F0,{5U,3U,0U}}, +{BSET_01F0,{6U,3U,0U}}, +{BSET_01F0,{7U,3U,0U}}, +{BSET_01F8,{0U,3U,0U}}, +{BSET_01F9,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0800,{0U,0U,0U}}, +{BTST_0800,{1U,0U,0U}}, +{BTST_0800,{2U,0U,0U}}, +{BTST_0800,{3U,0U,0U}}, +{BTST_0800,{4U,0U,0U}}, +{BTST_0800,{5U,0U,0U}}, +{BTST_0800,{6U,0U,0U}}, +{BTST_0800,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0810,{0U,0U,0U}}, +{BTST_0810,{1U,0U,0U}}, +{BTST_0810,{2U,0U,0U}}, +{BTST_0810,{3U,0U,0U}}, +{BTST_0810,{4U,0U,0U}}, +{BTST_0810,{5U,0U,0U}}, +{BTST_0810,{6U,0U,0U}}, +{BTST_0810,{7U,0U,0U}}, +{BTST_0818,{0U,0U,0U}}, +{BTST_0818,{1U,0U,0U}}, +{BTST_0818,{2U,0U,0U}}, +{BTST_0818,{3U,0U,0U}}, +{BTST_0818,{4U,0U,0U}}, +{BTST_0818,{5U,0U,0U}}, +{BTST_0818,{6U,0U,0U}}, +{BTST_0818,{7U,0U,0U}}, +{BTST_0820,{0U,0U,0U}}, +{BTST_0820,{1U,0U,0U}}, +{BTST_0820,{2U,0U,0U}}, +{BTST_0820,{3U,0U,0U}}, +{BTST_0820,{4U,0U,0U}}, +{BTST_0820,{5U,0U,0U}}, +{BTST_0820,{6U,0U,0U}}, +{BTST_0820,{7U,0U,0U}}, +{BTST_0828,{0U,0U,0U}}, +{BTST_0828,{1U,0U,0U}}, +{BTST_0828,{2U,0U,0U}}, +{BTST_0828,{3U,0U,0U}}, +{BTST_0828,{4U,0U,0U}}, +{BTST_0828,{5U,0U,0U}}, +{BTST_0828,{6U,0U,0U}}, +{BTST_0828,{7U,0U,0U}}, +{BTST_0830,{0U,0U,0U}}, +{BTST_0830,{1U,0U,0U}}, +{BTST_0830,{2U,0U,0U}}, +{BTST_0830,{3U,0U,0U}}, +{BTST_0830,{4U,0U,0U}}, +{BTST_0830,{5U,0U,0U}}, +{BTST_0830,{6U,0U,0U}}, +{BTST_0830,{7U,0U,0U}}, +{BTST_0838,{0U,0U,0U}}, +{BTST_0839,{0U,0U,0U}}, +{BTST_083A,{0U,0U,0U}}, +{BTST_083B,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0840,{0U,0U,0U}}, +{BCHG_0840,{1U,0U,0U}}, +{BCHG_0840,{2U,0U,0U}}, +{BCHG_0840,{3U,0U,0U}}, +{BCHG_0840,{4U,0U,0U}}, +{BCHG_0840,{5U,0U,0U}}, +{BCHG_0840,{6U,0U,0U}}, +{BCHG_0840,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0850,{0U,0U,0U}}, +{BCHG_0850,{1U,0U,0U}}, +{BCHG_0850,{2U,0U,0U}}, +{BCHG_0850,{3U,0U,0U}}, +{BCHG_0850,{4U,0U,0U}}, +{BCHG_0850,{5U,0U,0U}}, +{BCHG_0850,{6U,0U,0U}}, +{BCHG_0850,{7U,0U,0U}}, +{BCHG_0858,{0U,0U,0U}}, +{BCHG_0858,{1U,0U,0U}}, +{BCHG_0858,{2U,0U,0U}}, +{BCHG_0858,{3U,0U,0U}}, +{BCHG_0858,{4U,0U,0U}}, +{BCHG_0858,{5U,0U,0U}}, +{BCHG_0858,{6U,0U,0U}}, +{BCHG_0858,{7U,0U,0U}}, +{BCHG_0860,{0U,0U,0U}}, +{BCHG_0860,{1U,0U,0U}}, +{BCHG_0860,{2U,0U,0U}}, +{BCHG_0860,{3U,0U,0U}}, +{BCHG_0860,{4U,0U,0U}}, +{BCHG_0860,{5U,0U,0U}}, +{BCHG_0860,{6U,0U,0U}}, +{BCHG_0860,{7U,0U,0U}}, +{BCHG_0868,{0U,0U,0U}}, +{BCHG_0868,{1U,0U,0U}}, +{BCHG_0868,{2U,0U,0U}}, +{BCHG_0868,{3U,0U,0U}}, +{BCHG_0868,{4U,0U,0U}}, +{BCHG_0868,{5U,0U,0U}}, +{BCHG_0868,{6U,0U,0U}}, +{BCHG_0868,{7U,0U,0U}}, +{BCHG_0870,{0U,0U,0U}}, +{BCHG_0870,{1U,0U,0U}}, +{BCHG_0870,{2U,0U,0U}}, +{BCHG_0870,{3U,0U,0U}}, +{BCHG_0870,{4U,0U,0U}}, +{BCHG_0870,{5U,0U,0U}}, +{BCHG_0870,{6U,0U,0U}}, +{BCHG_0870,{7U,0U,0U}}, +{BCHG_0878,{0U,0U,0U}}, +{BCHG_0879,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0880,{0U,0U,0U}}, +{BCLR_0880,{1U,0U,0U}}, +{BCLR_0880,{2U,0U,0U}}, +{BCLR_0880,{3U,0U,0U}}, +{BCLR_0880,{4U,0U,0U}}, +{BCLR_0880,{5U,0U,0U}}, +{BCLR_0880,{6U,0U,0U}}, +{BCLR_0880,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0890,{0U,0U,0U}}, +{BCLR_0890,{1U,0U,0U}}, +{BCLR_0890,{2U,0U,0U}}, +{BCLR_0890,{3U,0U,0U}}, +{BCLR_0890,{4U,0U,0U}}, +{BCLR_0890,{5U,0U,0U}}, +{BCLR_0890,{6U,0U,0U}}, +{BCLR_0890,{7U,0U,0U}}, +{BCLR_0898,{0U,0U,0U}}, +{BCLR_0898,{1U,0U,0U}}, +{BCLR_0898,{2U,0U,0U}}, +{BCLR_0898,{3U,0U,0U}}, +{BCLR_0898,{4U,0U,0U}}, +{BCLR_0898,{5U,0U,0U}}, +{BCLR_0898,{6U,0U,0U}}, +{BCLR_0898,{7U,0U,0U}}, +{BCLR_08A0,{0U,0U,0U}}, +{BCLR_08A0,{1U,0U,0U}}, +{BCLR_08A0,{2U,0U,0U}}, +{BCLR_08A0,{3U,0U,0U}}, +{BCLR_08A0,{4U,0U,0U}}, +{BCLR_08A0,{5U,0U,0U}}, +{BCLR_08A0,{6U,0U,0U}}, +{BCLR_08A0,{7U,0U,0U}}, +{BCLR_08A8,{0U,0U,0U}}, +{BCLR_08A8,{1U,0U,0U}}, +{BCLR_08A8,{2U,0U,0U}}, +{BCLR_08A8,{3U,0U,0U}}, +{BCLR_08A8,{4U,0U,0U}}, +{BCLR_08A8,{5U,0U,0U}}, +{BCLR_08A8,{6U,0U,0U}}, +{BCLR_08A8,{7U,0U,0U}}, +{BCLR_08B0,{0U,0U,0U}}, +{BCLR_08B0,{1U,0U,0U}}, +{BCLR_08B0,{2U,0U,0U}}, +{BCLR_08B0,{3U,0U,0U}}, +{BCLR_08B0,{4U,0U,0U}}, +{BCLR_08B0,{5U,0U,0U}}, +{BCLR_08B0,{6U,0U,0U}}, +{BCLR_08B0,{7U,0U,0U}}, +{BCLR_08B8,{0U,0U,0U}}, +{BCLR_08B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_08C0,{0U,0U,0U}}, +{BSET_08C0,{1U,0U,0U}}, +{BSET_08C0,{2U,0U,0U}}, +{BSET_08C0,{3U,0U,0U}}, +{BSET_08C0,{4U,0U,0U}}, +{BSET_08C0,{5U,0U,0U}}, +{BSET_08C0,{6U,0U,0U}}, +{BSET_08C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_08D0,{0U,0U,0U}}, +{BSET_08D0,{1U,0U,0U}}, +{BSET_08D0,{2U,0U,0U}}, +{BSET_08D0,{3U,0U,0U}}, +{BSET_08D0,{4U,0U,0U}}, +{BSET_08D0,{5U,0U,0U}}, +{BSET_08D0,{6U,0U,0U}}, +{BSET_08D0,{7U,0U,0U}}, +{BSET_08D8,{0U,0U,0U}}, +{BSET_08D8,{1U,0U,0U}}, +{BSET_08D8,{2U,0U,0U}}, +{BSET_08D8,{3U,0U,0U}}, +{BSET_08D8,{4U,0U,0U}}, +{BSET_08D8,{5U,0U,0U}}, +{BSET_08D8,{6U,0U,0U}}, +{BSET_08D8,{7U,0U,0U}}, +{BSET_08E0,{0U,0U,0U}}, +{BSET_08E0,{1U,0U,0U}}, +{BSET_08E0,{2U,0U,0U}}, +{BSET_08E0,{3U,0U,0U}}, +{BSET_08E0,{4U,0U,0U}}, +{BSET_08E0,{5U,0U,0U}}, +{BSET_08E0,{6U,0U,0U}}, +{BSET_08E0,{7U,0U,0U}}, +{BSET_08E8,{0U,0U,0U}}, +{BSET_08E8,{1U,0U,0U}}, +{BSET_08E8,{2U,0U,0U}}, +{BSET_08E8,{3U,0U,0U}}, +{BSET_08E8,{4U,0U,0U}}, +{BSET_08E8,{5U,0U,0U}}, +{BSET_08E8,{6U,0U,0U}}, +{BSET_08E8,{7U,0U,0U}}, +{BSET_08F0,{0U,0U,0U}}, +{BSET_08F0,{1U,0U,0U}}, +{BSET_08F0,{2U,0U,0U}}, +{BSET_08F0,{3U,0U,0U}}, +{BSET_08F0,{4U,0U,0U}}, +{BSET_08F0,{5U,0U,0U}}, +{BSET_08F0,{6U,0U,0U}}, +{BSET_08F0,{7U,0U,0U}}, +{BSET_08F8,{0U,0U,0U}}, +{BSET_08F9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0100,{0U,4U,0U}}, +{BTST_0100,{1U,4U,0U}}, +{BTST_0100,{2U,4U,0U}}, +{BTST_0100,{3U,4U,0U}}, +{BTST_0100,{4U,4U,0U}}, +{BTST_0100,{5U,4U,0U}}, +{BTST_0100,{6U,4U,0U}}, +{BTST_0100,{7U,4U,0U}}, +{MOVEP_0108,{4U,0U,0U}}, +{MOVEP_0108,{4U,1U,0U}}, +{MOVEP_0108,{4U,2U,0U}}, +{MOVEP_0108,{4U,3U,0U}}, +{MOVEP_0108,{4U,4U,0U}}, +{MOVEP_0108,{4U,5U,0U}}, +{MOVEP_0108,{4U,6U,0U}}, +{MOVEP_0108,{4U,7U,0U}}, +{BTST_0110,{0U,4U,0U}}, +{BTST_0110,{1U,4U,0U}}, +{BTST_0110,{2U,4U,0U}}, +{BTST_0110,{3U,4U,0U}}, +{BTST_0110,{4U,4U,0U}}, +{BTST_0110,{5U,4U,0U}}, +{BTST_0110,{6U,4U,0U}}, +{BTST_0110,{7U,4U,0U}}, +{BTST_0118,{0U,4U,0U}}, +{BTST_0118,{1U,4U,0U}}, +{BTST_0118,{2U,4U,0U}}, +{BTST_0118,{3U,4U,0U}}, +{BTST_0118,{4U,4U,0U}}, +{BTST_0118,{5U,4U,0U}}, +{BTST_0118,{6U,4U,0U}}, +{BTST_0118,{7U,4U,0U}}, +{BTST_0120,{0U,4U,0U}}, +{BTST_0120,{1U,4U,0U}}, +{BTST_0120,{2U,4U,0U}}, +{BTST_0120,{3U,4U,0U}}, +{BTST_0120,{4U,4U,0U}}, +{BTST_0120,{5U,4U,0U}}, +{BTST_0120,{6U,4U,0U}}, +{BTST_0120,{7U,4U,0U}}, +{BTST_0128,{0U,4U,0U}}, +{BTST_0128,{1U,4U,0U}}, +{BTST_0128,{2U,4U,0U}}, +{BTST_0128,{3U,4U,0U}}, +{BTST_0128,{4U,4U,0U}}, +{BTST_0128,{5U,4U,0U}}, +{BTST_0128,{6U,4U,0U}}, +{BTST_0128,{7U,4U,0U}}, +{BTST_0130,{0U,4U,0U}}, +{BTST_0130,{1U,4U,0U}}, +{BTST_0130,{2U,4U,0U}}, +{BTST_0130,{3U,4U,0U}}, +{BTST_0130,{4U,4U,0U}}, +{BTST_0130,{5U,4U,0U}}, +{BTST_0130,{6U,4U,0U}}, +{BTST_0130,{7U,4U,0U}}, +{BTST_0138,{0U,4U,0U}}, +{BTST_0139,{0U,4U,0U}}, +{BTST_013A,{0U,4U,0U}}, +{BTST_013B,{0U,4U,0U}}, +{BTST_013C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0140,{0U,4U,0U}}, +{BCHG_0140,{1U,4U,0U}}, +{BCHG_0140,{2U,4U,0U}}, +{BCHG_0140,{3U,4U,0U}}, +{BCHG_0140,{4U,4U,0U}}, +{BCHG_0140,{5U,4U,0U}}, +{BCHG_0140,{6U,4U,0U}}, +{BCHG_0140,{7U,4U,0U}}, +{MOVEP_0148,{4U,0U,0U}}, +{MOVEP_0148,{4U,1U,0U}}, +{MOVEP_0148,{4U,2U,0U}}, +{MOVEP_0148,{4U,3U,0U}}, +{MOVEP_0148,{4U,4U,0U}}, +{MOVEP_0148,{4U,5U,0U}}, +{MOVEP_0148,{4U,6U,0U}}, +{MOVEP_0148,{4U,7U,0U}}, +{BCHG_0150,{0U,4U,0U}}, +{BCHG_0150,{1U,4U,0U}}, +{BCHG_0150,{2U,4U,0U}}, +{BCHG_0150,{3U,4U,0U}}, +{BCHG_0150,{4U,4U,0U}}, +{BCHG_0150,{5U,4U,0U}}, +{BCHG_0150,{6U,4U,0U}}, +{BCHG_0150,{7U,4U,0U}}, +{BCHG_0158,{0U,4U,0U}}, +{BCHG_0158,{1U,4U,0U}}, +{BCHG_0158,{2U,4U,0U}}, +{BCHG_0158,{3U,4U,0U}}, +{BCHG_0158,{4U,4U,0U}}, +{BCHG_0158,{5U,4U,0U}}, +{BCHG_0158,{6U,4U,0U}}, +{BCHG_0158,{7U,4U,0U}}, +{BCHG_0160,{0U,4U,0U}}, +{BCHG_0160,{1U,4U,0U}}, +{BCHG_0160,{2U,4U,0U}}, +{BCHG_0160,{3U,4U,0U}}, +{BCHG_0160,{4U,4U,0U}}, +{BCHG_0160,{5U,4U,0U}}, +{BCHG_0160,{6U,4U,0U}}, +{BCHG_0160,{7U,4U,0U}}, +{BCHG_0168,{0U,4U,0U}}, +{BCHG_0168,{1U,4U,0U}}, +{BCHG_0168,{2U,4U,0U}}, +{BCHG_0168,{3U,4U,0U}}, +{BCHG_0168,{4U,4U,0U}}, +{BCHG_0168,{5U,4U,0U}}, +{BCHG_0168,{6U,4U,0U}}, +{BCHG_0168,{7U,4U,0U}}, +{BCHG_0170,{0U,4U,0U}}, +{BCHG_0170,{1U,4U,0U}}, +{BCHG_0170,{2U,4U,0U}}, +{BCHG_0170,{3U,4U,0U}}, +{BCHG_0170,{4U,4U,0U}}, +{BCHG_0170,{5U,4U,0U}}, +{BCHG_0170,{6U,4U,0U}}, +{BCHG_0170,{7U,4U,0U}}, +{BCHG_0178,{0U,4U,0U}}, +{BCHG_0179,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0180,{0U,4U,0U}}, +{BCLR_0180,{1U,4U,0U}}, +{BCLR_0180,{2U,4U,0U}}, +{BCLR_0180,{3U,4U,0U}}, +{BCLR_0180,{4U,4U,0U}}, +{BCLR_0180,{5U,4U,0U}}, +{BCLR_0180,{6U,4U,0U}}, +{BCLR_0180,{7U,4U,0U}}, +{MOVEP_0188,{4U,0U,0U}}, +{MOVEP_0188,{4U,1U,0U}}, +{MOVEP_0188,{4U,2U,0U}}, +{MOVEP_0188,{4U,3U,0U}}, +{MOVEP_0188,{4U,4U,0U}}, +{MOVEP_0188,{4U,5U,0U}}, +{MOVEP_0188,{4U,6U,0U}}, +{MOVEP_0188,{4U,7U,0U}}, +{BCLR_0190,{0U,4U,0U}}, +{BCLR_0190,{1U,4U,0U}}, +{BCLR_0190,{2U,4U,0U}}, +{BCLR_0190,{3U,4U,0U}}, +{BCLR_0190,{4U,4U,0U}}, +{BCLR_0190,{5U,4U,0U}}, +{BCLR_0190,{6U,4U,0U}}, +{BCLR_0190,{7U,4U,0U}}, +{BCLR_0198,{0U,4U,0U}}, +{BCLR_0198,{1U,4U,0U}}, +{BCLR_0198,{2U,4U,0U}}, +{BCLR_0198,{3U,4U,0U}}, +{BCLR_0198,{4U,4U,0U}}, +{BCLR_0198,{5U,4U,0U}}, +{BCLR_0198,{6U,4U,0U}}, +{BCLR_0198,{7U,4U,0U}}, +{BCLR_01A0,{0U,4U,0U}}, +{BCLR_01A0,{1U,4U,0U}}, +{BCLR_01A0,{2U,4U,0U}}, +{BCLR_01A0,{3U,4U,0U}}, +{BCLR_01A0,{4U,4U,0U}}, +{BCLR_01A0,{5U,4U,0U}}, +{BCLR_01A0,{6U,4U,0U}}, +{BCLR_01A0,{7U,4U,0U}}, +{BCLR_01A8,{0U,4U,0U}}, +{BCLR_01A8,{1U,4U,0U}}, +{BCLR_01A8,{2U,4U,0U}}, +{BCLR_01A8,{3U,4U,0U}}, +{BCLR_01A8,{4U,4U,0U}}, +{BCLR_01A8,{5U,4U,0U}}, +{BCLR_01A8,{6U,4U,0U}}, +{BCLR_01A8,{7U,4U,0U}}, +{BCLR_01B0,{0U,4U,0U}}, +{BCLR_01B0,{1U,4U,0U}}, +{BCLR_01B0,{2U,4U,0U}}, +{BCLR_01B0,{3U,4U,0U}}, +{BCLR_01B0,{4U,4U,0U}}, +{BCLR_01B0,{5U,4U,0U}}, +{BCLR_01B0,{6U,4U,0U}}, +{BCLR_01B0,{7U,4U,0U}}, +{BCLR_01B8,{0U,4U,0U}}, +{BCLR_01B9,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_01C0,{0U,4U,0U}}, +{BSET_01C0,{1U,4U,0U}}, +{BSET_01C0,{2U,4U,0U}}, +{BSET_01C0,{3U,4U,0U}}, +{BSET_01C0,{4U,4U,0U}}, +{BSET_01C0,{5U,4U,0U}}, +{BSET_01C0,{6U,4U,0U}}, +{BSET_01C0,{7U,4U,0U}}, +{MOVEP_01C8,{4U,0U,0U}}, +{MOVEP_01C8,{4U,1U,0U}}, +{MOVEP_01C8,{4U,2U,0U}}, +{MOVEP_01C8,{4U,3U,0U}}, +{MOVEP_01C8,{4U,4U,0U}}, +{MOVEP_01C8,{4U,5U,0U}}, +{MOVEP_01C8,{4U,6U,0U}}, +{MOVEP_01C8,{4U,7U,0U}}, +{BSET_01D0,{0U,4U,0U}}, +{BSET_01D0,{1U,4U,0U}}, +{BSET_01D0,{2U,4U,0U}}, +{BSET_01D0,{3U,4U,0U}}, +{BSET_01D0,{4U,4U,0U}}, +{BSET_01D0,{5U,4U,0U}}, +{BSET_01D0,{6U,4U,0U}}, +{BSET_01D0,{7U,4U,0U}}, +{BSET_01D8,{0U,4U,0U}}, +{BSET_01D8,{1U,4U,0U}}, +{BSET_01D8,{2U,4U,0U}}, +{BSET_01D8,{3U,4U,0U}}, +{BSET_01D8,{4U,4U,0U}}, +{BSET_01D8,{5U,4U,0U}}, +{BSET_01D8,{6U,4U,0U}}, +{BSET_01D8,{7U,4U,0U}}, +{BSET_01E0,{0U,4U,0U}}, +{BSET_01E0,{1U,4U,0U}}, +{BSET_01E0,{2U,4U,0U}}, +{BSET_01E0,{3U,4U,0U}}, +{BSET_01E0,{4U,4U,0U}}, +{BSET_01E0,{5U,4U,0U}}, +{BSET_01E0,{6U,4U,0U}}, +{BSET_01E0,{7U,4U,0U}}, +{BSET_01E8,{0U,4U,0U}}, +{BSET_01E8,{1U,4U,0U}}, +{BSET_01E8,{2U,4U,0U}}, +{BSET_01E8,{3U,4U,0U}}, +{BSET_01E8,{4U,4U,0U}}, +{BSET_01E8,{5U,4U,0U}}, +{BSET_01E8,{6U,4U,0U}}, +{BSET_01E8,{7U,4U,0U}}, +{BSET_01F0,{0U,4U,0U}}, +{BSET_01F0,{1U,4U,0U}}, +{BSET_01F0,{2U,4U,0U}}, +{BSET_01F0,{3U,4U,0U}}, +{BSET_01F0,{4U,4U,0U}}, +{BSET_01F0,{5U,4U,0U}}, +{BSET_01F0,{6U,4U,0U}}, +{BSET_01F0,{7U,4U,0U}}, +{BSET_01F8,{0U,4U,0U}}, +{BSET_01F9,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EORI_0A00,{0U,0U,0U}}, +{EORI_0A00,{1U,0U,0U}}, +{EORI_0A00,{2U,0U,0U}}, +{EORI_0A00,{3U,0U,0U}}, +{EORI_0A00,{4U,0U,0U}}, +{EORI_0A00,{5U,0U,0U}}, +{EORI_0A00,{6U,0U,0U}}, +{EORI_0A00,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EORI_0A10,{0U,0U,0U}}, +{EORI_0A10,{1U,0U,0U}}, +{EORI_0A10,{2U,0U,0U}}, +{EORI_0A10,{3U,0U,0U}}, +{EORI_0A10,{4U,0U,0U}}, +{EORI_0A10,{5U,0U,0U}}, +{EORI_0A10,{6U,0U,0U}}, +{EORI_0A10,{7U,0U,0U}}, +{EORI_0A18,{0U,0U,0U}}, +{EORI_0A18,{1U,0U,0U}}, +{EORI_0A18,{2U,0U,0U}}, +{EORI_0A18,{3U,0U,0U}}, +{EORI_0A18,{4U,0U,0U}}, +{EORI_0A18,{5U,0U,0U}}, +{EORI_0A18,{6U,0U,0U}}, +{EORI_0A18,{7U,0U,0U}}, +{EORI_0A20,{0U,0U,0U}}, +{EORI_0A20,{1U,0U,0U}}, +{EORI_0A20,{2U,0U,0U}}, +{EORI_0A20,{3U,0U,0U}}, +{EORI_0A20,{4U,0U,0U}}, +{EORI_0A20,{5U,0U,0U}}, +{EORI_0A20,{6U,0U,0U}}, +{EORI_0A20,{7U,0U,0U}}, +{EORI_0A28,{0U,0U,0U}}, +{EORI_0A28,{1U,0U,0U}}, +{EORI_0A28,{2U,0U,0U}}, +{EORI_0A28,{3U,0U,0U}}, +{EORI_0A28,{4U,0U,0U}}, +{EORI_0A28,{5U,0U,0U}}, +{EORI_0A28,{6U,0U,0U}}, +{EORI_0A28,{7U,0U,0U}}, +{EORI_0A30,{0U,0U,0U}}, +{EORI_0A30,{1U,0U,0U}}, +{EORI_0A30,{2U,0U,0U}}, +{EORI_0A30,{3U,0U,0U}}, +{EORI_0A30,{4U,0U,0U}}, +{EORI_0A30,{5U,0U,0U}}, +{EORI_0A30,{6U,0U,0U}}, +{EORI_0A30,{7U,0U,0U}}, +{EORI_0A38,{0U,0U,0U}}, +{EORI_0A39,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EORI_0A3C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EORI_0A40,{0U,0U,0U}}, +{EORI_0A40,{1U,0U,0U}}, +{EORI_0A40,{2U,0U,0U}}, +{EORI_0A40,{3U,0U,0U}}, +{EORI_0A40,{4U,0U,0U}}, +{EORI_0A40,{5U,0U,0U}}, +{EORI_0A40,{6U,0U,0U}}, +{EORI_0A40,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EORI_0A50,{0U,0U,0U}}, +{EORI_0A50,{1U,0U,0U}}, +{EORI_0A50,{2U,0U,0U}}, +{EORI_0A50,{3U,0U,0U}}, +{EORI_0A50,{4U,0U,0U}}, +{EORI_0A50,{5U,0U,0U}}, +{EORI_0A50,{6U,0U,0U}}, +{EORI_0A50,{7U,0U,0U}}, +{EORI_0A58,{0U,0U,0U}}, +{EORI_0A58,{1U,0U,0U}}, +{EORI_0A58,{2U,0U,0U}}, +{EORI_0A58,{3U,0U,0U}}, +{EORI_0A58,{4U,0U,0U}}, +{EORI_0A58,{5U,0U,0U}}, +{EORI_0A58,{6U,0U,0U}}, +{EORI_0A58,{7U,0U,0U}}, +{EORI_0A60,{0U,0U,0U}}, +{EORI_0A60,{1U,0U,0U}}, +{EORI_0A60,{2U,0U,0U}}, +{EORI_0A60,{3U,0U,0U}}, +{EORI_0A60,{4U,0U,0U}}, +{EORI_0A60,{5U,0U,0U}}, +{EORI_0A60,{6U,0U,0U}}, +{EORI_0A60,{7U,0U,0U}}, +{EORI_0A68,{0U,0U,0U}}, +{EORI_0A68,{1U,0U,0U}}, +{EORI_0A68,{2U,0U,0U}}, +{EORI_0A68,{3U,0U,0U}}, +{EORI_0A68,{4U,0U,0U}}, +{EORI_0A68,{5U,0U,0U}}, +{EORI_0A68,{6U,0U,0U}}, +{EORI_0A68,{7U,0U,0U}}, +{EORI_0A70,{0U,0U,0U}}, +{EORI_0A70,{1U,0U,0U}}, +{EORI_0A70,{2U,0U,0U}}, +{EORI_0A70,{3U,0U,0U}}, +{EORI_0A70,{4U,0U,0U}}, +{EORI_0A70,{5U,0U,0U}}, +{EORI_0A70,{6U,0U,0U}}, +{EORI_0A70,{7U,0U,0U}}, +{EORI_0A78,{0U,0U,0U}}, +{EORI_0A79,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EORI_0A7C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EORI_0A80,{0U,0U,0U}}, +{EORI_0A80,{1U,0U,0U}}, +{EORI_0A80,{2U,0U,0U}}, +{EORI_0A80,{3U,0U,0U}}, +{EORI_0A80,{4U,0U,0U}}, +{EORI_0A80,{5U,0U,0U}}, +{EORI_0A80,{6U,0U,0U}}, +{EORI_0A80,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EORI_0A90,{0U,0U,0U}}, +{EORI_0A90,{1U,0U,0U}}, +{EORI_0A90,{2U,0U,0U}}, +{EORI_0A90,{3U,0U,0U}}, +{EORI_0A90,{4U,0U,0U}}, +{EORI_0A90,{5U,0U,0U}}, +{EORI_0A90,{6U,0U,0U}}, +{EORI_0A90,{7U,0U,0U}}, +{EORI_0A98,{0U,0U,0U}}, +{EORI_0A98,{1U,0U,0U}}, +{EORI_0A98,{2U,0U,0U}}, +{EORI_0A98,{3U,0U,0U}}, +{EORI_0A98,{4U,0U,0U}}, +{EORI_0A98,{5U,0U,0U}}, +{EORI_0A98,{6U,0U,0U}}, +{EORI_0A98,{7U,0U,0U}}, +{EORI_0AA0,{0U,0U,0U}}, +{EORI_0AA0,{1U,0U,0U}}, +{EORI_0AA0,{2U,0U,0U}}, +{EORI_0AA0,{3U,0U,0U}}, +{EORI_0AA0,{4U,0U,0U}}, +{EORI_0AA0,{5U,0U,0U}}, +{EORI_0AA0,{6U,0U,0U}}, +{EORI_0AA0,{7U,0U,0U}}, +{EORI_0AA8,{0U,0U,0U}}, +{EORI_0AA8,{1U,0U,0U}}, +{EORI_0AA8,{2U,0U,0U}}, +{EORI_0AA8,{3U,0U,0U}}, +{EORI_0AA8,{4U,0U,0U}}, +{EORI_0AA8,{5U,0U,0U}}, +{EORI_0AA8,{6U,0U,0U}}, +{EORI_0AA8,{7U,0U,0U}}, +{EORI_0AB0,{0U,0U,0U}}, +{EORI_0AB0,{1U,0U,0U}}, +{EORI_0AB0,{2U,0U,0U}}, +{EORI_0AB0,{3U,0U,0U}}, +{EORI_0AB0,{4U,0U,0U}}, +{EORI_0AB0,{5U,0U,0U}}, +{EORI_0AB0,{6U,0U,0U}}, +{EORI_0AB0,{7U,0U,0U}}, +{EORI_0AB8,{0U,0U,0U}}, +{EORI_0AB9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CAS_0AD0,{0U,0U,0U}}, +{CAS_0AD0,{1U,0U,0U}}, +{CAS_0AD0,{2U,0U,0U}}, +{CAS_0AD0,{3U,0U,0U}}, +{CAS_0AD0,{4U,0U,0U}}, +{CAS_0AD0,{5U,0U,0U}}, +{CAS_0AD0,{6U,0U,0U}}, +{CAS_0AD0,{7U,0U,0U}}, +{CAS_0AD8,{0U,0U,0U}}, +{CAS_0AD8,{1U,0U,0U}}, +{CAS_0AD8,{2U,0U,0U}}, +{CAS_0AD8,{3U,0U,0U}}, +{CAS_0AD8,{4U,0U,0U}}, +{CAS_0AD8,{5U,0U,0U}}, +{CAS_0AD8,{6U,0U,0U}}, +{CAS_0AD8,{7U,0U,0U}}, +{CAS_0AE0,{0U,0U,0U}}, +{CAS_0AE0,{1U,0U,0U}}, +{CAS_0AE0,{2U,0U,0U}}, +{CAS_0AE0,{3U,0U,0U}}, +{CAS_0AE0,{4U,0U,0U}}, +{CAS_0AE0,{5U,0U,0U}}, +{CAS_0AE0,{6U,0U,0U}}, +{CAS_0AE0,{7U,0U,0U}}, +{CAS_0AE8,{0U,0U,0U}}, +{CAS_0AE8,{1U,0U,0U}}, +{CAS_0AE8,{2U,0U,0U}}, +{CAS_0AE8,{3U,0U,0U}}, +{CAS_0AE8,{4U,0U,0U}}, +{CAS_0AE8,{5U,0U,0U}}, +{CAS_0AE8,{6U,0U,0U}}, +{CAS_0AE8,{7U,0U,0U}}, +{CAS_0AF0,{0U,0U,0U}}, +{CAS_0AF0,{1U,0U,0U}}, +{CAS_0AF0,{2U,0U,0U}}, +{CAS_0AF0,{3U,0U,0U}}, +{CAS_0AF0,{4U,0U,0U}}, +{CAS_0AF0,{5U,0U,0U}}, +{CAS_0AF0,{6U,0U,0U}}, +{CAS_0AF0,{7U,0U,0U}}, +{CAS_0AF8,{0U,0U,0U}}, +{CAS_0AF9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0100,{0U,5U,0U}}, +{BTST_0100,{1U,5U,0U}}, +{BTST_0100,{2U,5U,0U}}, +{BTST_0100,{3U,5U,0U}}, +{BTST_0100,{4U,5U,0U}}, +{BTST_0100,{5U,5U,0U}}, +{BTST_0100,{6U,5U,0U}}, +{BTST_0100,{7U,5U,0U}}, +{MOVEP_0108,{5U,0U,0U}}, +{MOVEP_0108,{5U,1U,0U}}, +{MOVEP_0108,{5U,2U,0U}}, +{MOVEP_0108,{5U,3U,0U}}, +{MOVEP_0108,{5U,4U,0U}}, +{MOVEP_0108,{5U,5U,0U}}, +{MOVEP_0108,{5U,6U,0U}}, +{MOVEP_0108,{5U,7U,0U}}, +{BTST_0110,{0U,5U,0U}}, +{BTST_0110,{1U,5U,0U}}, +{BTST_0110,{2U,5U,0U}}, +{BTST_0110,{3U,5U,0U}}, +{BTST_0110,{4U,5U,0U}}, +{BTST_0110,{5U,5U,0U}}, +{BTST_0110,{6U,5U,0U}}, +{BTST_0110,{7U,5U,0U}}, +{BTST_0118,{0U,5U,0U}}, +{BTST_0118,{1U,5U,0U}}, +{BTST_0118,{2U,5U,0U}}, +{BTST_0118,{3U,5U,0U}}, +{BTST_0118,{4U,5U,0U}}, +{BTST_0118,{5U,5U,0U}}, +{BTST_0118,{6U,5U,0U}}, +{BTST_0118,{7U,5U,0U}}, +{BTST_0120,{0U,5U,0U}}, +{BTST_0120,{1U,5U,0U}}, +{BTST_0120,{2U,5U,0U}}, +{BTST_0120,{3U,5U,0U}}, +{BTST_0120,{4U,5U,0U}}, +{BTST_0120,{5U,5U,0U}}, +{BTST_0120,{6U,5U,0U}}, +{BTST_0120,{7U,5U,0U}}, +{BTST_0128,{0U,5U,0U}}, +{BTST_0128,{1U,5U,0U}}, +{BTST_0128,{2U,5U,0U}}, +{BTST_0128,{3U,5U,0U}}, +{BTST_0128,{4U,5U,0U}}, +{BTST_0128,{5U,5U,0U}}, +{BTST_0128,{6U,5U,0U}}, +{BTST_0128,{7U,5U,0U}}, +{BTST_0130,{0U,5U,0U}}, +{BTST_0130,{1U,5U,0U}}, +{BTST_0130,{2U,5U,0U}}, +{BTST_0130,{3U,5U,0U}}, +{BTST_0130,{4U,5U,0U}}, +{BTST_0130,{5U,5U,0U}}, +{BTST_0130,{6U,5U,0U}}, +{BTST_0130,{7U,5U,0U}}, +{BTST_0138,{0U,5U,0U}}, +{BTST_0139,{0U,5U,0U}}, +{BTST_013A,{0U,5U,0U}}, +{BTST_013B,{0U,5U,0U}}, +{BTST_013C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0140,{0U,5U,0U}}, +{BCHG_0140,{1U,5U,0U}}, +{BCHG_0140,{2U,5U,0U}}, +{BCHG_0140,{3U,5U,0U}}, +{BCHG_0140,{4U,5U,0U}}, +{BCHG_0140,{5U,5U,0U}}, +{BCHG_0140,{6U,5U,0U}}, +{BCHG_0140,{7U,5U,0U}}, +{MOVEP_0148,{5U,0U,0U}}, +{MOVEP_0148,{5U,1U,0U}}, +{MOVEP_0148,{5U,2U,0U}}, +{MOVEP_0148,{5U,3U,0U}}, +{MOVEP_0148,{5U,4U,0U}}, +{MOVEP_0148,{5U,5U,0U}}, +{MOVEP_0148,{5U,6U,0U}}, +{MOVEP_0148,{5U,7U,0U}}, +{BCHG_0150,{0U,5U,0U}}, +{BCHG_0150,{1U,5U,0U}}, +{BCHG_0150,{2U,5U,0U}}, +{BCHG_0150,{3U,5U,0U}}, +{BCHG_0150,{4U,5U,0U}}, +{BCHG_0150,{5U,5U,0U}}, +{BCHG_0150,{6U,5U,0U}}, +{BCHG_0150,{7U,5U,0U}}, +{BCHG_0158,{0U,5U,0U}}, +{BCHG_0158,{1U,5U,0U}}, +{BCHG_0158,{2U,5U,0U}}, +{BCHG_0158,{3U,5U,0U}}, +{BCHG_0158,{4U,5U,0U}}, +{BCHG_0158,{5U,5U,0U}}, +{BCHG_0158,{6U,5U,0U}}, +{BCHG_0158,{7U,5U,0U}}, +{BCHG_0160,{0U,5U,0U}}, +{BCHG_0160,{1U,5U,0U}}, +{BCHG_0160,{2U,5U,0U}}, +{BCHG_0160,{3U,5U,0U}}, +{BCHG_0160,{4U,5U,0U}}, +{BCHG_0160,{5U,5U,0U}}, +{BCHG_0160,{6U,5U,0U}}, +{BCHG_0160,{7U,5U,0U}}, +{BCHG_0168,{0U,5U,0U}}, +{BCHG_0168,{1U,5U,0U}}, +{BCHG_0168,{2U,5U,0U}}, +{BCHG_0168,{3U,5U,0U}}, +{BCHG_0168,{4U,5U,0U}}, +{BCHG_0168,{5U,5U,0U}}, +{BCHG_0168,{6U,5U,0U}}, +{BCHG_0168,{7U,5U,0U}}, +{BCHG_0170,{0U,5U,0U}}, +{BCHG_0170,{1U,5U,0U}}, +{BCHG_0170,{2U,5U,0U}}, +{BCHG_0170,{3U,5U,0U}}, +{BCHG_0170,{4U,5U,0U}}, +{BCHG_0170,{5U,5U,0U}}, +{BCHG_0170,{6U,5U,0U}}, +{BCHG_0170,{7U,5U,0U}}, +{BCHG_0178,{0U,5U,0U}}, +{BCHG_0179,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0180,{0U,5U,0U}}, +{BCLR_0180,{1U,5U,0U}}, +{BCLR_0180,{2U,5U,0U}}, +{BCLR_0180,{3U,5U,0U}}, +{BCLR_0180,{4U,5U,0U}}, +{BCLR_0180,{5U,5U,0U}}, +{BCLR_0180,{6U,5U,0U}}, +{BCLR_0180,{7U,5U,0U}}, +{MOVEP_0188,{5U,0U,0U}}, +{MOVEP_0188,{5U,1U,0U}}, +{MOVEP_0188,{5U,2U,0U}}, +{MOVEP_0188,{5U,3U,0U}}, +{MOVEP_0188,{5U,4U,0U}}, +{MOVEP_0188,{5U,5U,0U}}, +{MOVEP_0188,{5U,6U,0U}}, +{MOVEP_0188,{5U,7U,0U}}, +{BCLR_0190,{0U,5U,0U}}, +{BCLR_0190,{1U,5U,0U}}, +{BCLR_0190,{2U,5U,0U}}, +{BCLR_0190,{3U,5U,0U}}, +{BCLR_0190,{4U,5U,0U}}, +{BCLR_0190,{5U,5U,0U}}, +{BCLR_0190,{6U,5U,0U}}, +{BCLR_0190,{7U,5U,0U}}, +{BCLR_0198,{0U,5U,0U}}, +{BCLR_0198,{1U,5U,0U}}, +{BCLR_0198,{2U,5U,0U}}, +{BCLR_0198,{3U,5U,0U}}, +{BCLR_0198,{4U,5U,0U}}, +{BCLR_0198,{5U,5U,0U}}, +{BCLR_0198,{6U,5U,0U}}, +{BCLR_0198,{7U,5U,0U}}, +{BCLR_01A0,{0U,5U,0U}}, +{BCLR_01A0,{1U,5U,0U}}, +{BCLR_01A0,{2U,5U,0U}}, +{BCLR_01A0,{3U,5U,0U}}, +{BCLR_01A0,{4U,5U,0U}}, +{BCLR_01A0,{5U,5U,0U}}, +{BCLR_01A0,{6U,5U,0U}}, +{BCLR_01A0,{7U,5U,0U}}, +{BCLR_01A8,{0U,5U,0U}}, +{BCLR_01A8,{1U,5U,0U}}, +{BCLR_01A8,{2U,5U,0U}}, +{BCLR_01A8,{3U,5U,0U}}, +{BCLR_01A8,{4U,5U,0U}}, +{BCLR_01A8,{5U,5U,0U}}, +{BCLR_01A8,{6U,5U,0U}}, +{BCLR_01A8,{7U,5U,0U}}, +{BCLR_01B0,{0U,5U,0U}}, +{BCLR_01B0,{1U,5U,0U}}, +{BCLR_01B0,{2U,5U,0U}}, +{BCLR_01B0,{3U,5U,0U}}, +{BCLR_01B0,{4U,5U,0U}}, +{BCLR_01B0,{5U,5U,0U}}, +{BCLR_01B0,{6U,5U,0U}}, +{BCLR_01B0,{7U,5U,0U}}, +{BCLR_01B8,{0U,5U,0U}}, +{BCLR_01B9,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_01C0,{0U,5U,0U}}, +{BSET_01C0,{1U,5U,0U}}, +{BSET_01C0,{2U,5U,0U}}, +{BSET_01C0,{3U,5U,0U}}, +{BSET_01C0,{4U,5U,0U}}, +{BSET_01C0,{5U,5U,0U}}, +{BSET_01C0,{6U,5U,0U}}, +{BSET_01C0,{7U,5U,0U}}, +{MOVEP_01C8,{5U,0U,0U}}, +{MOVEP_01C8,{5U,1U,0U}}, +{MOVEP_01C8,{5U,2U,0U}}, +{MOVEP_01C8,{5U,3U,0U}}, +{MOVEP_01C8,{5U,4U,0U}}, +{MOVEP_01C8,{5U,5U,0U}}, +{MOVEP_01C8,{5U,6U,0U}}, +{MOVEP_01C8,{5U,7U,0U}}, +{BSET_01D0,{0U,5U,0U}}, +{BSET_01D0,{1U,5U,0U}}, +{BSET_01D0,{2U,5U,0U}}, +{BSET_01D0,{3U,5U,0U}}, +{BSET_01D0,{4U,5U,0U}}, +{BSET_01D0,{5U,5U,0U}}, +{BSET_01D0,{6U,5U,0U}}, +{BSET_01D0,{7U,5U,0U}}, +{BSET_01D8,{0U,5U,0U}}, +{BSET_01D8,{1U,5U,0U}}, +{BSET_01D8,{2U,5U,0U}}, +{BSET_01D8,{3U,5U,0U}}, +{BSET_01D8,{4U,5U,0U}}, +{BSET_01D8,{5U,5U,0U}}, +{BSET_01D8,{6U,5U,0U}}, +{BSET_01D8,{7U,5U,0U}}, +{BSET_01E0,{0U,5U,0U}}, +{BSET_01E0,{1U,5U,0U}}, +{BSET_01E0,{2U,5U,0U}}, +{BSET_01E0,{3U,5U,0U}}, +{BSET_01E0,{4U,5U,0U}}, +{BSET_01E0,{5U,5U,0U}}, +{BSET_01E0,{6U,5U,0U}}, +{BSET_01E0,{7U,5U,0U}}, +{BSET_01E8,{0U,5U,0U}}, +{BSET_01E8,{1U,5U,0U}}, +{BSET_01E8,{2U,5U,0U}}, +{BSET_01E8,{3U,5U,0U}}, +{BSET_01E8,{4U,5U,0U}}, +{BSET_01E8,{5U,5U,0U}}, +{BSET_01E8,{6U,5U,0U}}, +{BSET_01E8,{7U,5U,0U}}, +{BSET_01F0,{0U,5U,0U}}, +{BSET_01F0,{1U,5U,0U}}, +{BSET_01F0,{2U,5U,0U}}, +{BSET_01F0,{3U,5U,0U}}, +{BSET_01F0,{4U,5U,0U}}, +{BSET_01F0,{5U,5U,0U}}, +{BSET_01F0,{6U,5U,0U}}, +{BSET_01F0,{7U,5U,0U}}, +{BSET_01F8,{0U,5U,0U}}, +{BSET_01F9,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPI_0C00,{0U,0U,0U}}, +{CMPI_0C00,{1U,0U,0U}}, +{CMPI_0C00,{2U,0U,0U}}, +{CMPI_0C00,{3U,0U,0U}}, +{CMPI_0C00,{4U,0U,0U}}, +{CMPI_0C00,{5U,0U,0U}}, +{CMPI_0C00,{6U,0U,0U}}, +{CMPI_0C00,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPI_0C10,{0U,0U,0U}}, +{CMPI_0C10,{1U,0U,0U}}, +{CMPI_0C10,{2U,0U,0U}}, +{CMPI_0C10,{3U,0U,0U}}, +{CMPI_0C10,{4U,0U,0U}}, +{CMPI_0C10,{5U,0U,0U}}, +{CMPI_0C10,{6U,0U,0U}}, +{CMPI_0C10,{7U,0U,0U}}, +{CMPI_0C18,{0U,0U,0U}}, +{CMPI_0C18,{1U,0U,0U}}, +{CMPI_0C18,{2U,0U,0U}}, +{CMPI_0C18,{3U,0U,0U}}, +{CMPI_0C18,{4U,0U,0U}}, +{CMPI_0C18,{5U,0U,0U}}, +{CMPI_0C18,{6U,0U,0U}}, +{CMPI_0C18,{7U,0U,0U}}, +{CMPI_0C20,{0U,0U,0U}}, +{CMPI_0C20,{1U,0U,0U}}, +{CMPI_0C20,{2U,0U,0U}}, +{CMPI_0C20,{3U,0U,0U}}, +{CMPI_0C20,{4U,0U,0U}}, +{CMPI_0C20,{5U,0U,0U}}, +{CMPI_0C20,{6U,0U,0U}}, +{CMPI_0C20,{7U,0U,0U}}, +{CMPI_0C28,{0U,0U,0U}}, +{CMPI_0C28,{1U,0U,0U}}, +{CMPI_0C28,{2U,0U,0U}}, +{CMPI_0C28,{3U,0U,0U}}, +{CMPI_0C28,{4U,0U,0U}}, +{CMPI_0C28,{5U,0U,0U}}, +{CMPI_0C28,{6U,0U,0U}}, +{CMPI_0C28,{7U,0U,0U}}, +{CMPI_0C30,{0U,0U,0U}}, +{CMPI_0C30,{1U,0U,0U}}, +{CMPI_0C30,{2U,0U,0U}}, +{CMPI_0C30,{3U,0U,0U}}, +{CMPI_0C30,{4U,0U,0U}}, +{CMPI_0C30,{5U,0U,0U}}, +{CMPI_0C30,{6U,0U,0U}}, +{CMPI_0C30,{7U,0U,0U}}, +{CMPI_0C38,{0U,0U,0U}}, +{CMPI_0C39,{0U,0U,0U}}, +{CMPI_0C3A,{0U,0U,0U}}, +{CMPI_0C3B,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPI_0C40,{0U,0U,0U}}, +{CMPI_0C40,{1U,0U,0U}}, +{CMPI_0C40,{2U,0U,0U}}, +{CMPI_0C40,{3U,0U,0U}}, +{CMPI_0C40,{4U,0U,0U}}, +{CMPI_0C40,{5U,0U,0U}}, +{CMPI_0C40,{6U,0U,0U}}, +{CMPI_0C40,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPI_0C50,{0U,0U,0U}}, +{CMPI_0C50,{1U,0U,0U}}, +{CMPI_0C50,{2U,0U,0U}}, +{CMPI_0C50,{3U,0U,0U}}, +{CMPI_0C50,{4U,0U,0U}}, +{CMPI_0C50,{5U,0U,0U}}, +{CMPI_0C50,{6U,0U,0U}}, +{CMPI_0C50,{7U,0U,0U}}, +{CMPI_0C58,{0U,0U,0U}}, +{CMPI_0C58,{1U,0U,0U}}, +{CMPI_0C58,{2U,0U,0U}}, +{CMPI_0C58,{3U,0U,0U}}, +{CMPI_0C58,{4U,0U,0U}}, +{CMPI_0C58,{5U,0U,0U}}, +{CMPI_0C58,{6U,0U,0U}}, +{CMPI_0C58,{7U,0U,0U}}, +{CMPI_0C60,{0U,0U,0U}}, +{CMPI_0C60,{1U,0U,0U}}, +{CMPI_0C60,{2U,0U,0U}}, +{CMPI_0C60,{3U,0U,0U}}, +{CMPI_0C60,{4U,0U,0U}}, +{CMPI_0C60,{5U,0U,0U}}, +{CMPI_0C60,{6U,0U,0U}}, +{CMPI_0C60,{7U,0U,0U}}, +{CMPI_0C68,{0U,0U,0U}}, +{CMPI_0C68,{1U,0U,0U}}, +{CMPI_0C68,{2U,0U,0U}}, +{CMPI_0C68,{3U,0U,0U}}, +{CMPI_0C68,{4U,0U,0U}}, +{CMPI_0C68,{5U,0U,0U}}, +{CMPI_0C68,{6U,0U,0U}}, +{CMPI_0C68,{7U,0U,0U}}, +{CMPI_0C70,{0U,0U,0U}}, +{CMPI_0C70,{1U,0U,0U}}, +{CMPI_0C70,{2U,0U,0U}}, +{CMPI_0C70,{3U,0U,0U}}, +{CMPI_0C70,{4U,0U,0U}}, +{CMPI_0C70,{5U,0U,0U}}, +{CMPI_0C70,{6U,0U,0U}}, +{CMPI_0C70,{7U,0U,0U}}, +{CMPI_0C78,{0U,0U,0U}}, +{CMPI_0C79,{0U,0U,0U}}, +{CMPI_0C7A,{0U,0U,0U}}, +{CMPI_0C7B,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPI_0C80,{0U,0U,0U}}, +{CMPI_0C80,{1U,0U,0U}}, +{CMPI_0C80,{2U,0U,0U}}, +{CMPI_0C80,{3U,0U,0U}}, +{CMPI_0C80,{4U,0U,0U}}, +{CMPI_0C80,{5U,0U,0U}}, +{CMPI_0C80,{6U,0U,0U}}, +{CMPI_0C80,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPI_0C90,{0U,0U,0U}}, +{CMPI_0C90,{1U,0U,0U}}, +{CMPI_0C90,{2U,0U,0U}}, +{CMPI_0C90,{3U,0U,0U}}, +{CMPI_0C90,{4U,0U,0U}}, +{CMPI_0C90,{5U,0U,0U}}, +{CMPI_0C90,{6U,0U,0U}}, +{CMPI_0C90,{7U,0U,0U}}, +{CMPI_0C98,{0U,0U,0U}}, +{CMPI_0C98,{1U,0U,0U}}, +{CMPI_0C98,{2U,0U,0U}}, +{CMPI_0C98,{3U,0U,0U}}, +{CMPI_0C98,{4U,0U,0U}}, +{CMPI_0C98,{5U,0U,0U}}, +{CMPI_0C98,{6U,0U,0U}}, +{CMPI_0C98,{7U,0U,0U}}, +{CMPI_0CA0,{0U,0U,0U}}, +{CMPI_0CA0,{1U,0U,0U}}, +{CMPI_0CA0,{2U,0U,0U}}, +{CMPI_0CA0,{3U,0U,0U}}, +{CMPI_0CA0,{4U,0U,0U}}, +{CMPI_0CA0,{5U,0U,0U}}, +{CMPI_0CA0,{6U,0U,0U}}, +{CMPI_0CA0,{7U,0U,0U}}, +{CMPI_0CA8,{0U,0U,0U}}, +{CMPI_0CA8,{1U,0U,0U}}, +{CMPI_0CA8,{2U,0U,0U}}, +{CMPI_0CA8,{3U,0U,0U}}, +{CMPI_0CA8,{4U,0U,0U}}, +{CMPI_0CA8,{5U,0U,0U}}, +{CMPI_0CA8,{6U,0U,0U}}, +{CMPI_0CA8,{7U,0U,0U}}, +{CMPI_0CB0,{0U,0U,0U}}, +{CMPI_0CB0,{1U,0U,0U}}, +{CMPI_0CB0,{2U,0U,0U}}, +{CMPI_0CB0,{3U,0U,0U}}, +{CMPI_0CB0,{4U,0U,0U}}, +{CMPI_0CB0,{5U,0U,0U}}, +{CMPI_0CB0,{6U,0U,0U}}, +{CMPI_0CB0,{7U,0U,0U}}, +{CMPI_0CB8,{0U,0U,0U}}, +{CMPI_0CB9,{0U,0U,0U}}, +{CMPI_0CBA,{0U,0U,0U}}, +{CMPI_0CBB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CAS_0CD0,{0U,0U,0U}}, +{CAS_0CD0,{1U,0U,0U}}, +{CAS_0CD0,{2U,0U,0U}}, +{CAS_0CD0,{3U,0U,0U}}, +{CAS_0CD0,{4U,0U,0U}}, +{CAS_0CD0,{5U,0U,0U}}, +{CAS_0CD0,{6U,0U,0U}}, +{CAS_0CD0,{7U,0U,0U}}, +{CAS_0CD8,{0U,0U,0U}}, +{CAS_0CD8,{1U,0U,0U}}, +{CAS_0CD8,{2U,0U,0U}}, +{CAS_0CD8,{3U,0U,0U}}, +{CAS_0CD8,{4U,0U,0U}}, +{CAS_0CD8,{5U,0U,0U}}, +{CAS_0CD8,{6U,0U,0U}}, +{CAS_0CD8,{7U,0U,0U}}, +{CAS_0CE0,{0U,0U,0U}}, +{CAS_0CE0,{1U,0U,0U}}, +{CAS_0CE0,{2U,0U,0U}}, +{CAS_0CE0,{3U,0U,0U}}, +{CAS_0CE0,{4U,0U,0U}}, +{CAS_0CE0,{5U,0U,0U}}, +{CAS_0CE0,{6U,0U,0U}}, +{CAS_0CE0,{7U,0U,0U}}, +{CAS_0CE8,{0U,0U,0U}}, +{CAS_0CE8,{1U,0U,0U}}, +{CAS_0CE8,{2U,0U,0U}}, +{CAS_0CE8,{3U,0U,0U}}, +{CAS_0CE8,{4U,0U,0U}}, +{CAS_0CE8,{5U,0U,0U}}, +{CAS_0CE8,{6U,0U,0U}}, +{CAS_0CE8,{7U,0U,0U}}, +{CAS_0CF0,{0U,0U,0U}}, +{CAS_0CF0,{1U,0U,0U}}, +{CAS_0CF0,{2U,0U,0U}}, +{CAS_0CF0,{3U,0U,0U}}, +{CAS_0CF0,{4U,0U,0U}}, +{CAS_0CF0,{5U,0U,0U}}, +{CAS_0CF0,{6U,0U,0U}}, +{CAS_0CF0,{7U,0U,0U}}, +{CAS_0CF8,{0U,0U,0U}}, +{CAS_0CF9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CAS2_0CFC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0100,{0U,6U,0U}}, +{BTST_0100,{1U,6U,0U}}, +{BTST_0100,{2U,6U,0U}}, +{BTST_0100,{3U,6U,0U}}, +{BTST_0100,{4U,6U,0U}}, +{BTST_0100,{5U,6U,0U}}, +{BTST_0100,{6U,6U,0U}}, +{BTST_0100,{7U,6U,0U}}, +{MOVEP_0108,{6U,0U,0U}}, +{MOVEP_0108,{6U,1U,0U}}, +{MOVEP_0108,{6U,2U,0U}}, +{MOVEP_0108,{6U,3U,0U}}, +{MOVEP_0108,{6U,4U,0U}}, +{MOVEP_0108,{6U,5U,0U}}, +{MOVEP_0108,{6U,6U,0U}}, +{MOVEP_0108,{6U,7U,0U}}, +{BTST_0110,{0U,6U,0U}}, +{BTST_0110,{1U,6U,0U}}, +{BTST_0110,{2U,6U,0U}}, +{BTST_0110,{3U,6U,0U}}, +{BTST_0110,{4U,6U,0U}}, +{BTST_0110,{5U,6U,0U}}, +{BTST_0110,{6U,6U,0U}}, +{BTST_0110,{7U,6U,0U}}, +{BTST_0118,{0U,6U,0U}}, +{BTST_0118,{1U,6U,0U}}, +{BTST_0118,{2U,6U,0U}}, +{BTST_0118,{3U,6U,0U}}, +{BTST_0118,{4U,6U,0U}}, +{BTST_0118,{5U,6U,0U}}, +{BTST_0118,{6U,6U,0U}}, +{BTST_0118,{7U,6U,0U}}, +{BTST_0120,{0U,6U,0U}}, +{BTST_0120,{1U,6U,0U}}, +{BTST_0120,{2U,6U,0U}}, +{BTST_0120,{3U,6U,0U}}, +{BTST_0120,{4U,6U,0U}}, +{BTST_0120,{5U,6U,0U}}, +{BTST_0120,{6U,6U,0U}}, +{BTST_0120,{7U,6U,0U}}, +{BTST_0128,{0U,6U,0U}}, +{BTST_0128,{1U,6U,0U}}, +{BTST_0128,{2U,6U,0U}}, +{BTST_0128,{3U,6U,0U}}, +{BTST_0128,{4U,6U,0U}}, +{BTST_0128,{5U,6U,0U}}, +{BTST_0128,{6U,6U,0U}}, +{BTST_0128,{7U,6U,0U}}, +{BTST_0130,{0U,6U,0U}}, +{BTST_0130,{1U,6U,0U}}, +{BTST_0130,{2U,6U,0U}}, +{BTST_0130,{3U,6U,0U}}, +{BTST_0130,{4U,6U,0U}}, +{BTST_0130,{5U,6U,0U}}, +{BTST_0130,{6U,6U,0U}}, +{BTST_0130,{7U,6U,0U}}, +{BTST_0138,{0U,6U,0U}}, +{BTST_0139,{0U,6U,0U}}, +{BTST_013A,{0U,6U,0U}}, +{BTST_013B,{0U,6U,0U}}, +{BTST_013C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0140,{0U,6U,0U}}, +{BCHG_0140,{1U,6U,0U}}, +{BCHG_0140,{2U,6U,0U}}, +{BCHG_0140,{3U,6U,0U}}, +{BCHG_0140,{4U,6U,0U}}, +{BCHG_0140,{5U,6U,0U}}, +{BCHG_0140,{6U,6U,0U}}, +{BCHG_0140,{7U,6U,0U}}, +{MOVEP_0148,{6U,0U,0U}}, +{MOVEP_0148,{6U,1U,0U}}, +{MOVEP_0148,{6U,2U,0U}}, +{MOVEP_0148,{6U,3U,0U}}, +{MOVEP_0148,{6U,4U,0U}}, +{MOVEP_0148,{6U,5U,0U}}, +{MOVEP_0148,{6U,6U,0U}}, +{MOVEP_0148,{6U,7U,0U}}, +{BCHG_0150,{0U,6U,0U}}, +{BCHG_0150,{1U,6U,0U}}, +{BCHG_0150,{2U,6U,0U}}, +{BCHG_0150,{3U,6U,0U}}, +{BCHG_0150,{4U,6U,0U}}, +{BCHG_0150,{5U,6U,0U}}, +{BCHG_0150,{6U,6U,0U}}, +{BCHG_0150,{7U,6U,0U}}, +{BCHG_0158,{0U,6U,0U}}, +{BCHG_0158,{1U,6U,0U}}, +{BCHG_0158,{2U,6U,0U}}, +{BCHG_0158,{3U,6U,0U}}, +{BCHG_0158,{4U,6U,0U}}, +{BCHG_0158,{5U,6U,0U}}, +{BCHG_0158,{6U,6U,0U}}, +{BCHG_0158,{7U,6U,0U}}, +{BCHG_0160,{0U,6U,0U}}, +{BCHG_0160,{1U,6U,0U}}, +{BCHG_0160,{2U,6U,0U}}, +{BCHG_0160,{3U,6U,0U}}, +{BCHG_0160,{4U,6U,0U}}, +{BCHG_0160,{5U,6U,0U}}, +{BCHG_0160,{6U,6U,0U}}, +{BCHG_0160,{7U,6U,0U}}, +{BCHG_0168,{0U,6U,0U}}, +{BCHG_0168,{1U,6U,0U}}, +{BCHG_0168,{2U,6U,0U}}, +{BCHG_0168,{3U,6U,0U}}, +{BCHG_0168,{4U,6U,0U}}, +{BCHG_0168,{5U,6U,0U}}, +{BCHG_0168,{6U,6U,0U}}, +{BCHG_0168,{7U,6U,0U}}, +{BCHG_0170,{0U,6U,0U}}, +{BCHG_0170,{1U,6U,0U}}, +{BCHG_0170,{2U,6U,0U}}, +{BCHG_0170,{3U,6U,0U}}, +{BCHG_0170,{4U,6U,0U}}, +{BCHG_0170,{5U,6U,0U}}, +{BCHG_0170,{6U,6U,0U}}, +{BCHG_0170,{7U,6U,0U}}, +{BCHG_0178,{0U,6U,0U}}, +{BCHG_0179,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0180,{0U,6U,0U}}, +{BCLR_0180,{1U,6U,0U}}, +{BCLR_0180,{2U,6U,0U}}, +{BCLR_0180,{3U,6U,0U}}, +{BCLR_0180,{4U,6U,0U}}, +{BCLR_0180,{5U,6U,0U}}, +{BCLR_0180,{6U,6U,0U}}, +{BCLR_0180,{7U,6U,0U}}, +{MOVEP_0188,{6U,0U,0U}}, +{MOVEP_0188,{6U,1U,0U}}, +{MOVEP_0188,{6U,2U,0U}}, +{MOVEP_0188,{6U,3U,0U}}, +{MOVEP_0188,{6U,4U,0U}}, +{MOVEP_0188,{6U,5U,0U}}, +{MOVEP_0188,{6U,6U,0U}}, +{MOVEP_0188,{6U,7U,0U}}, +{BCLR_0190,{0U,6U,0U}}, +{BCLR_0190,{1U,6U,0U}}, +{BCLR_0190,{2U,6U,0U}}, +{BCLR_0190,{3U,6U,0U}}, +{BCLR_0190,{4U,6U,0U}}, +{BCLR_0190,{5U,6U,0U}}, +{BCLR_0190,{6U,6U,0U}}, +{BCLR_0190,{7U,6U,0U}}, +{BCLR_0198,{0U,6U,0U}}, +{BCLR_0198,{1U,6U,0U}}, +{BCLR_0198,{2U,6U,0U}}, +{BCLR_0198,{3U,6U,0U}}, +{BCLR_0198,{4U,6U,0U}}, +{BCLR_0198,{5U,6U,0U}}, +{BCLR_0198,{6U,6U,0U}}, +{BCLR_0198,{7U,6U,0U}}, +{BCLR_01A0,{0U,6U,0U}}, +{BCLR_01A0,{1U,6U,0U}}, +{BCLR_01A0,{2U,6U,0U}}, +{BCLR_01A0,{3U,6U,0U}}, +{BCLR_01A0,{4U,6U,0U}}, +{BCLR_01A0,{5U,6U,0U}}, +{BCLR_01A0,{6U,6U,0U}}, +{BCLR_01A0,{7U,6U,0U}}, +{BCLR_01A8,{0U,6U,0U}}, +{BCLR_01A8,{1U,6U,0U}}, +{BCLR_01A8,{2U,6U,0U}}, +{BCLR_01A8,{3U,6U,0U}}, +{BCLR_01A8,{4U,6U,0U}}, +{BCLR_01A8,{5U,6U,0U}}, +{BCLR_01A8,{6U,6U,0U}}, +{BCLR_01A8,{7U,6U,0U}}, +{BCLR_01B0,{0U,6U,0U}}, +{BCLR_01B0,{1U,6U,0U}}, +{BCLR_01B0,{2U,6U,0U}}, +{BCLR_01B0,{3U,6U,0U}}, +{BCLR_01B0,{4U,6U,0U}}, +{BCLR_01B0,{5U,6U,0U}}, +{BCLR_01B0,{6U,6U,0U}}, +{BCLR_01B0,{7U,6U,0U}}, +{BCLR_01B8,{0U,6U,0U}}, +{BCLR_01B9,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_01C0,{0U,6U,0U}}, +{BSET_01C0,{1U,6U,0U}}, +{BSET_01C0,{2U,6U,0U}}, +{BSET_01C0,{3U,6U,0U}}, +{BSET_01C0,{4U,6U,0U}}, +{BSET_01C0,{5U,6U,0U}}, +{BSET_01C0,{6U,6U,0U}}, +{BSET_01C0,{7U,6U,0U}}, +{MOVEP_01C8,{6U,0U,0U}}, +{MOVEP_01C8,{6U,1U,0U}}, +{MOVEP_01C8,{6U,2U,0U}}, +{MOVEP_01C8,{6U,3U,0U}}, +{MOVEP_01C8,{6U,4U,0U}}, +{MOVEP_01C8,{6U,5U,0U}}, +{MOVEP_01C8,{6U,6U,0U}}, +{MOVEP_01C8,{6U,7U,0U}}, +{BSET_01D0,{0U,6U,0U}}, +{BSET_01D0,{1U,6U,0U}}, +{BSET_01D0,{2U,6U,0U}}, +{BSET_01D0,{3U,6U,0U}}, +{BSET_01D0,{4U,6U,0U}}, +{BSET_01D0,{5U,6U,0U}}, +{BSET_01D0,{6U,6U,0U}}, +{BSET_01D0,{7U,6U,0U}}, +{BSET_01D8,{0U,6U,0U}}, +{BSET_01D8,{1U,6U,0U}}, +{BSET_01D8,{2U,6U,0U}}, +{BSET_01D8,{3U,6U,0U}}, +{BSET_01D8,{4U,6U,0U}}, +{BSET_01D8,{5U,6U,0U}}, +{BSET_01D8,{6U,6U,0U}}, +{BSET_01D8,{7U,6U,0U}}, +{BSET_01E0,{0U,6U,0U}}, +{BSET_01E0,{1U,6U,0U}}, +{BSET_01E0,{2U,6U,0U}}, +{BSET_01E0,{3U,6U,0U}}, +{BSET_01E0,{4U,6U,0U}}, +{BSET_01E0,{5U,6U,0U}}, +{BSET_01E0,{6U,6U,0U}}, +{BSET_01E0,{7U,6U,0U}}, +{BSET_01E8,{0U,6U,0U}}, +{BSET_01E8,{1U,6U,0U}}, +{BSET_01E8,{2U,6U,0U}}, +{BSET_01E8,{3U,6U,0U}}, +{BSET_01E8,{4U,6U,0U}}, +{BSET_01E8,{5U,6U,0U}}, +{BSET_01E8,{6U,6U,0U}}, +{BSET_01E8,{7U,6U,0U}}, +{BSET_01F0,{0U,6U,0U}}, +{BSET_01F0,{1U,6U,0U}}, +{BSET_01F0,{2U,6U,0U}}, +{BSET_01F0,{3U,6U,0U}}, +{BSET_01F0,{4U,6U,0U}}, +{BSET_01F0,{5U,6U,0U}}, +{BSET_01F0,{6U,6U,0U}}, +{BSET_01F0,{7U,6U,0U}}, +{BSET_01F8,{0U,6U,0U}}, +{BSET_01F9,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVES_0E10,{0U,0U,0U}}, +{MOVES_0E10,{1U,0U,0U}}, +{MOVES_0E10,{2U,0U,0U}}, +{MOVES_0E10,{3U,0U,0U}}, +{MOVES_0E10,{4U,0U,0U}}, +{MOVES_0E10,{5U,0U,0U}}, +{MOVES_0E10,{6U,0U,0U}}, +{MOVES_0E10,{7U,0U,0U}}, +{MOVES_0E18,{0U,0U,0U}}, +{MOVES_0E18,{1U,0U,0U}}, +{MOVES_0E18,{2U,0U,0U}}, +{MOVES_0E18,{3U,0U,0U}}, +{MOVES_0E18,{4U,0U,0U}}, +{MOVES_0E18,{5U,0U,0U}}, +{MOVES_0E18,{6U,0U,0U}}, +{MOVES_0E18,{7U,0U,0U}}, +{MOVES_0E20,{0U,0U,0U}}, +{MOVES_0E20,{1U,0U,0U}}, +{MOVES_0E20,{2U,0U,0U}}, +{MOVES_0E20,{3U,0U,0U}}, +{MOVES_0E20,{4U,0U,0U}}, +{MOVES_0E20,{5U,0U,0U}}, +{MOVES_0E20,{6U,0U,0U}}, +{MOVES_0E20,{7U,0U,0U}}, +{MOVES_0E28,{0U,0U,0U}}, +{MOVES_0E28,{1U,0U,0U}}, +{MOVES_0E28,{2U,0U,0U}}, +{MOVES_0E28,{3U,0U,0U}}, +{MOVES_0E28,{4U,0U,0U}}, +{MOVES_0E28,{5U,0U,0U}}, +{MOVES_0E28,{6U,0U,0U}}, +{MOVES_0E28,{7U,0U,0U}}, +{MOVES_0E30,{0U,0U,0U}}, +{MOVES_0E30,{1U,0U,0U}}, +{MOVES_0E30,{2U,0U,0U}}, +{MOVES_0E30,{3U,0U,0U}}, +{MOVES_0E30,{4U,0U,0U}}, +{MOVES_0E30,{5U,0U,0U}}, +{MOVES_0E30,{6U,0U,0U}}, +{MOVES_0E30,{7U,0U,0U}}, +{MOVES_0E38,{0U,0U,0U}}, +{MOVES_0E39,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVES_0E50,{0U,0U,0U}}, +{MOVES_0E50,{1U,0U,0U}}, +{MOVES_0E50,{2U,0U,0U}}, +{MOVES_0E50,{3U,0U,0U}}, +{MOVES_0E50,{4U,0U,0U}}, +{MOVES_0E50,{5U,0U,0U}}, +{MOVES_0E50,{6U,0U,0U}}, +{MOVES_0E50,{7U,0U,0U}}, +{MOVES_0E58,{0U,0U,0U}}, +{MOVES_0E58,{1U,0U,0U}}, +{MOVES_0E58,{2U,0U,0U}}, +{MOVES_0E58,{3U,0U,0U}}, +{MOVES_0E58,{4U,0U,0U}}, +{MOVES_0E58,{5U,0U,0U}}, +{MOVES_0E58,{6U,0U,0U}}, +{MOVES_0E58,{7U,0U,0U}}, +{MOVES_0E60,{0U,0U,0U}}, +{MOVES_0E60,{1U,0U,0U}}, +{MOVES_0E60,{2U,0U,0U}}, +{MOVES_0E60,{3U,0U,0U}}, +{MOVES_0E60,{4U,0U,0U}}, +{MOVES_0E60,{5U,0U,0U}}, +{MOVES_0E60,{6U,0U,0U}}, +{MOVES_0E60,{7U,0U,0U}}, +{MOVES_0E68,{0U,0U,0U}}, +{MOVES_0E68,{1U,0U,0U}}, +{MOVES_0E68,{2U,0U,0U}}, +{MOVES_0E68,{3U,0U,0U}}, +{MOVES_0E68,{4U,0U,0U}}, +{MOVES_0E68,{5U,0U,0U}}, +{MOVES_0E68,{6U,0U,0U}}, +{MOVES_0E68,{7U,0U,0U}}, +{MOVES_0E70,{0U,0U,0U}}, +{MOVES_0E70,{1U,0U,0U}}, +{MOVES_0E70,{2U,0U,0U}}, +{MOVES_0E70,{3U,0U,0U}}, +{MOVES_0E70,{4U,0U,0U}}, +{MOVES_0E70,{5U,0U,0U}}, +{MOVES_0E70,{6U,0U,0U}}, +{MOVES_0E70,{7U,0U,0U}}, +{MOVES_0E78,{0U,0U,0U}}, +{MOVES_0E79,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVES_0E90,{0U,0U,0U}}, +{MOVES_0E90,{1U,0U,0U}}, +{MOVES_0E90,{2U,0U,0U}}, +{MOVES_0E90,{3U,0U,0U}}, +{MOVES_0E90,{4U,0U,0U}}, +{MOVES_0E90,{5U,0U,0U}}, +{MOVES_0E90,{6U,0U,0U}}, +{MOVES_0E90,{7U,0U,0U}}, +{MOVES_0E98,{0U,0U,0U}}, +{MOVES_0E98,{1U,0U,0U}}, +{MOVES_0E98,{2U,0U,0U}}, +{MOVES_0E98,{3U,0U,0U}}, +{MOVES_0E98,{4U,0U,0U}}, +{MOVES_0E98,{5U,0U,0U}}, +{MOVES_0E98,{6U,0U,0U}}, +{MOVES_0E98,{7U,0U,0U}}, +{MOVES_0EA0,{0U,0U,0U}}, +{MOVES_0EA0,{1U,0U,0U}}, +{MOVES_0EA0,{2U,0U,0U}}, +{MOVES_0EA0,{3U,0U,0U}}, +{MOVES_0EA0,{4U,0U,0U}}, +{MOVES_0EA0,{5U,0U,0U}}, +{MOVES_0EA0,{6U,0U,0U}}, +{MOVES_0EA0,{7U,0U,0U}}, +{MOVES_0EA8,{0U,0U,0U}}, +{MOVES_0EA8,{1U,0U,0U}}, +{MOVES_0EA8,{2U,0U,0U}}, +{MOVES_0EA8,{3U,0U,0U}}, +{MOVES_0EA8,{4U,0U,0U}}, +{MOVES_0EA8,{5U,0U,0U}}, +{MOVES_0EA8,{6U,0U,0U}}, +{MOVES_0EA8,{7U,0U,0U}}, +{MOVES_0EB0,{0U,0U,0U}}, +{MOVES_0EB0,{1U,0U,0U}}, +{MOVES_0EB0,{2U,0U,0U}}, +{MOVES_0EB0,{3U,0U,0U}}, +{MOVES_0EB0,{4U,0U,0U}}, +{MOVES_0EB0,{5U,0U,0U}}, +{MOVES_0EB0,{6U,0U,0U}}, +{MOVES_0EB0,{7U,0U,0U}}, +{MOVES_0EB8,{0U,0U,0U}}, +{MOVES_0EB9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CAS_0ED0,{0U,0U,0U}}, +{CAS_0ED0,{1U,0U,0U}}, +{CAS_0ED0,{2U,0U,0U}}, +{CAS_0ED0,{3U,0U,0U}}, +{CAS_0ED0,{4U,0U,0U}}, +{CAS_0ED0,{5U,0U,0U}}, +{CAS_0ED0,{6U,0U,0U}}, +{CAS_0ED0,{7U,0U,0U}}, +{CAS_0ED8,{0U,0U,0U}}, +{CAS_0ED8,{1U,0U,0U}}, +{CAS_0ED8,{2U,0U,0U}}, +{CAS_0ED8,{3U,0U,0U}}, +{CAS_0ED8,{4U,0U,0U}}, +{CAS_0ED8,{5U,0U,0U}}, +{CAS_0ED8,{6U,0U,0U}}, +{CAS_0ED8,{7U,0U,0U}}, +{CAS_0EE0,{0U,0U,0U}}, +{CAS_0EE0,{1U,0U,0U}}, +{CAS_0EE0,{2U,0U,0U}}, +{CAS_0EE0,{3U,0U,0U}}, +{CAS_0EE0,{4U,0U,0U}}, +{CAS_0EE0,{5U,0U,0U}}, +{CAS_0EE0,{6U,0U,0U}}, +{CAS_0EE0,{7U,0U,0U}}, +{CAS_0EE8,{0U,0U,0U}}, +{CAS_0EE8,{1U,0U,0U}}, +{CAS_0EE8,{2U,0U,0U}}, +{CAS_0EE8,{3U,0U,0U}}, +{CAS_0EE8,{4U,0U,0U}}, +{CAS_0EE8,{5U,0U,0U}}, +{CAS_0EE8,{6U,0U,0U}}, +{CAS_0EE8,{7U,0U,0U}}, +{CAS_0EF0,{0U,0U,0U}}, +{CAS_0EF0,{1U,0U,0U}}, +{CAS_0EF0,{2U,0U,0U}}, +{CAS_0EF0,{3U,0U,0U}}, +{CAS_0EF0,{4U,0U,0U}}, +{CAS_0EF0,{5U,0U,0U}}, +{CAS_0EF0,{6U,0U,0U}}, +{CAS_0EF0,{7U,0U,0U}}, +{CAS_0EF8,{0U,0U,0U}}, +{CAS_0EF9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CAS2_0EFC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BTST_0100,{0U,7U,0U}}, +{BTST_0100,{1U,7U,0U}}, +{BTST_0100,{2U,7U,0U}}, +{BTST_0100,{3U,7U,0U}}, +{BTST_0100,{4U,7U,0U}}, +{BTST_0100,{5U,7U,0U}}, +{BTST_0100,{6U,7U,0U}}, +{BTST_0100,{7U,7U,0U}}, +{MOVEP_0108,{7U,0U,0U}}, +{MOVEP_0108,{7U,1U,0U}}, +{MOVEP_0108,{7U,2U,0U}}, +{MOVEP_0108,{7U,3U,0U}}, +{MOVEP_0108,{7U,4U,0U}}, +{MOVEP_0108,{7U,5U,0U}}, +{MOVEP_0108,{7U,6U,0U}}, +{MOVEP_0108,{7U,7U,0U}}, +{BTST_0110,{0U,7U,0U}}, +{BTST_0110,{1U,7U,0U}}, +{BTST_0110,{2U,7U,0U}}, +{BTST_0110,{3U,7U,0U}}, +{BTST_0110,{4U,7U,0U}}, +{BTST_0110,{5U,7U,0U}}, +{BTST_0110,{6U,7U,0U}}, +{BTST_0110,{7U,7U,0U}}, +{BTST_0118,{0U,7U,0U}}, +{BTST_0118,{1U,7U,0U}}, +{BTST_0118,{2U,7U,0U}}, +{BTST_0118,{3U,7U,0U}}, +{BTST_0118,{4U,7U,0U}}, +{BTST_0118,{5U,7U,0U}}, +{BTST_0118,{6U,7U,0U}}, +{BTST_0118,{7U,7U,0U}}, +{BTST_0120,{0U,7U,0U}}, +{BTST_0120,{1U,7U,0U}}, +{BTST_0120,{2U,7U,0U}}, +{BTST_0120,{3U,7U,0U}}, +{BTST_0120,{4U,7U,0U}}, +{BTST_0120,{5U,7U,0U}}, +{BTST_0120,{6U,7U,0U}}, +{BTST_0120,{7U,7U,0U}}, +{BTST_0128,{0U,7U,0U}}, +{BTST_0128,{1U,7U,0U}}, +{BTST_0128,{2U,7U,0U}}, +{BTST_0128,{3U,7U,0U}}, +{BTST_0128,{4U,7U,0U}}, +{BTST_0128,{5U,7U,0U}}, +{BTST_0128,{6U,7U,0U}}, +{BTST_0128,{7U,7U,0U}}, +{BTST_0130,{0U,7U,0U}}, +{BTST_0130,{1U,7U,0U}}, +{BTST_0130,{2U,7U,0U}}, +{BTST_0130,{3U,7U,0U}}, +{BTST_0130,{4U,7U,0U}}, +{BTST_0130,{5U,7U,0U}}, +{BTST_0130,{6U,7U,0U}}, +{BTST_0130,{7U,7U,0U}}, +{BTST_0138,{0U,7U,0U}}, +{BTST_0139,{0U,7U,0U}}, +{BTST_013A,{0U,7U,0U}}, +{BTST_013B,{0U,7U,0U}}, +{BTST_013C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCHG_0140,{0U,7U,0U}}, +{BCHG_0140,{1U,7U,0U}}, +{BCHG_0140,{2U,7U,0U}}, +{BCHG_0140,{3U,7U,0U}}, +{BCHG_0140,{4U,7U,0U}}, +{BCHG_0140,{5U,7U,0U}}, +{BCHG_0140,{6U,7U,0U}}, +{BCHG_0140,{7U,7U,0U}}, +{MOVEP_0148,{7U,0U,0U}}, +{MOVEP_0148,{7U,1U,0U}}, +{MOVEP_0148,{7U,2U,0U}}, +{MOVEP_0148,{7U,3U,0U}}, +{MOVEP_0148,{7U,4U,0U}}, +{MOVEP_0148,{7U,5U,0U}}, +{MOVEP_0148,{7U,6U,0U}}, +{MOVEP_0148,{7U,7U,0U}}, +{BCHG_0150,{0U,7U,0U}}, +{BCHG_0150,{1U,7U,0U}}, +{BCHG_0150,{2U,7U,0U}}, +{BCHG_0150,{3U,7U,0U}}, +{BCHG_0150,{4U,7U,0U}}, +{BCHG_0150,{5U,7U,0U}}, +{BCHG_0150,{6U,7U,0U}}, +{BCHG_0150,{7U,7U,0U}}, +{BCHG_0158,{0U,7U,0U}}, +{BCHG_0158,{1U,7U,0U}}, +{BCHG_0158,{2U,7U,0U}}, +{BCHG_0158,{3U,7U,0U}}, +{BCHG_0158,{4U,7U,0U}}, +{BCHG_0158,{5U,7U,0U}}, +{BCHG_0158,{6U,7U,0U}}, +{BCHG_0158,{7U,7U,0U}}, +{BCHG_0160,{0U,7U,0U}}, +{BCHG_0160,{1U,7U,0U}}, +{BCHG_0160,{2U,7U,0U}}, +{BCHG_0160,{3U,7U,0U}}, +{BCHG_0160,{4U,7U,0U}}, +{BCHG_0160,{5U,7U,0U}}, +{BCHG_0160,{6U,7U,0U}}, +{BCHG_0160,{7U,7U,0U}}, +{BCHG_0168,{0U,7U,0U}}, +{BCHG_0168,{1U,7U,0U}}, +{BCHG_0168,{2U,7U,0U}}, +{BCHG_0168,{3U,7U,0U}}, +{BCHG_0168,{4U,7U,0U}}, +{BCHG_0168,{5U,7U,0U}}, +{BCHG_0168,{6U,7U,0U}}, +{BCHG_0168,{7U,7U,0U}}, +{BCHG_0170,{0U,7U,0U}}, +{BCHG_0170,{1U,7U,0U}}, +{BCHG_0170,{2U,7U,0U}}, +{BCHG_0170,{3U,7U,0U}}, +{BCHG_0170,{4U,7U,0U}}, +{BCHG_0170,{5U,7U,0U}}, +{BCHG_0170,{6U,7U,0U}}, +{BCHG_0170,{7U,7U,0U}}, +{BCHG_0178,{0U,7U,0U}}, +{BCHG_0179,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BCLR_0180,{0U,7U,0U}}, +{BCLR_0180,{1U,7U,0U}}, +{BCLR_0180,{2U,7U,0U}}, +{BCLR_0180,{3U,7U,0U}}, +{BCLR_0180,{4U,7U,0U}}, +{BCLR_0180,{5U,7U,0U}}, +{BCLR_0180,{6U,7U,0U}}, +{BCLR_0180,{7U,7U,0U}}, +{MOVEP_0188,{7U,0U,0U}}, +{MOVEP_0188,{7U,1U,0U}}, +{MOVEP_0188,{7U,2U,0U}}, +{MOVEP_0188,{7U,3U,0U}}, +{MOVEP_0188,{7U,4U,0U}}, +{MOVEP_0188,{7U,5U,0U}}, +{MOVEP_0188,{7U,6U,0U}}, +{MOVEP_0188,{7U,7U,0U}}, +{BCLR_0190,{0U,7U,0U}}, +{BCLR_0190,{1U,7U,0U}}, +{BCLR_0190,{2U,7U,0U}}, +{BCLR_0190,{3U,7U,0U}}, +{BCLR_0190,{4U,7U,0U}}, +{BCLR_0190,{5U,7U,0U}}, +{BCLR_0190,{6U,7U,0U}}, +{BCLR_0190,{7U,7U,0U}}, +{BCLR_0198,{0U,7U,0U}}, +{BCLR_0198,{1U,7U,0U}}, +{BCLR_0198,{2U,7U,0U}}, +{BCLR_0198,{3U,7U,0U}}, +{BCLR_0198,{4U,7U,0U}}, +{BCLR_0198,{5U,7U,0U}}, +{BCLR_0198,{6U,7U,0U}}, +{BCLR_0198,{7U,7U,0U}}, +{BCLR_01A0,{0U,7U,0U}}, +{BCLR_01A0,{1U,7U,0U}}, +{BCLR_01A0,{2U,7U,0U}}, +{BCLR_01A0,{3U,7U,0U}}, +{BCLR_01A0,{4U,7U,0U}}, +{BCLR_01A0,{5U,7U,0U}}, +{BCLR_01A0,{6U,7U,0U}}, +{BCLR_01A0,{7U,7U,0U}}, +{BCLR_01A8,{0U,7U,0U}}, +{BCLR_01A8,{1U,7U,0U}}, +{BCLR_01A8,{2U,7U,0U}}, +{BCLR_01A8,{3U,7U,0U}}, +{BCLR_01A8,{4U,7U,0U}}, +{BCLR_01A8,{5U,7U,0U}}, +{BCLR_01A8,{6U,7U,0U}}, +{BCLR_01A8,{7U,7U,0U}}, +{BCLR_01B0,{0U,7U,0U}}, +{BCLR_01B0,{1U,7U,0U}}, +{BCLR_01B0,{2U,7U,0U}}, +{BCLR_01B0,{3U,7U,0U}}, +{BCLR_01B0,{4U,7U,0U}}, +{BCLR_01B0,{5U,7U,0U}}, +{BCLR_01B0,{6U,7U,0U}}, +{BCLR_01B0,{7U,7U,0U}}, +{BCLR_01B8,{0U,7U,0U}}, +{BCLR_01B9,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BSET_01C0,{0U,7U,0U}}, +{BSET_01C0,{1U,7U,0U}}, +{BSET_01C0,{2U,7U,0U}}, +{BSET_01C0,{3U,7U,0U}}, +{BSET_01C0,{4U,7U,0U}}, +{BSET_01C0,{5U,7U,0U}}, +{BSET_01C0,{6U,7U,0U}}, +{BSET_01C0,{7U,7U,0U}}, +{MOVEP_01C8,{7U,0U,0U}}, +{MOVEP_01C8,{7U,1U,0U}}, +{MOVEP_01C8,{7U,2U,0U}}, +{MOVEP_01C8,{7U,3U,0U}}, +{MOVEP_01C8,{7U,4U,0U}}, +{MOVEP_01C8,{7U,5U,0U}}, +{MOVEP_01C8,{7U,6U,0U}}, +{MOVEP_01C8,{7U,7U,0U}}, +{BSET_01D0,{0U,7U,0U}}, +{BSET_01D0,{1U,7U,0U}}, +{BSET_01D0,{2U,7U,0U}}, +{BSET_01D0,{3U,7U,0U}}, +{BSET_01D0,{4U,7U,0U}}, +{BSET_01D0,{5U,7U,0U}}, +{BSET_01D0,{6U,7U,0U}}, +{BSET_01D0,{7U,7U,0U}}, +{BSET_01D8,{0U,7U,0U}}, +{BSET_01D8,{1U,7U,0U}}, +{BSET_01D8,{2U,7U,0U}}, +{BSET_01D8,{3U,7U,0U}}, +{BSET_01D8,{4U,7U,0U}}, +{BSET_01D8,{5U,7U,0U}}, +{BSET_01D8,{6U,7U,0U}}, +{BSET_01D8,{7U,7U,0U}}, +{BSET_01E0,{0U,7U,0U}}, +{BSET_01E0,{1U,7U,0U}}, +{BSET_01E0,{2U,7U,0U}}, +{BSET_01E0,{3U,7U,0U}}, +{BSET_01E0,{4U,7U,0U}}, +{BSET_01E0,{5U,7U,0U}}, +{BSET_01E0,{6U,7U,0U}}, +{BSET_01E0,{7U,7U,0U}}, +{BSET_01E8,{0U,7U,0U}}, +{BSET_01E8,{1U,7U,0U}}, +{BSET_01E8,{2U,7U,0U}}, +{BSET_01E8,{3U,7U,0U}}, +{BSET_01E8,{4U,7U,0U}}, +{BSET_01E8,{5U,7U,0U}}, +{BSET_01E8,{6U,7U,0U}}, +{BSET_01E8,{7U,7U,0U}}, +{BSET_01F0,{0U,7U,0U}}, +{BSET_01F0,{1U,7U,0U}}, +{BSET_01F0,{2U,7U,0U}}, +{BSET_01F0,{3U,7U,0U}}, +{BSET_01F0,{4U,7U,0U}}, +{BSET_01F0,{5U,7U,0U}}, +{BSET_01F0,{6U,7U,0U}}, +{BSET_01F0,{7U,7U,0U}}, +{BSET_01F8,{0U,7U,0U}}, +{BSET_01F9,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1000,{0U,0U,0U}}, +{MOVE_1000,{1U,0U,0U}}, +{MOVE_1000,{2U,0U,0U}}, +{MOVE_1000,{3U,0U,0U}}, +{MOVE_1000,{4U,0U,0U}}, +{MOVE_1000,{5U,0U,0U}}, +{MOVE_1000,{6U,0U,0U}}, +{MOVE_1000,{7U,0U,0U}}, +{MOVE_1008,{0U,0U,0U}}, +{MOVE_1008,{1U,0U,0U}}, +{MOVE_1008,{2U,0U,0U}}, +{MOVE_1008,{3U,0U,0U}}, +{MOVE_1008,{4U,0U,0U}}, +{MOVE_1008,{5U,0U,0U}}, +{MOVE_1008,{6U,0U,0U}}, +{MOVE_1008,{7U,0U,0U}}, +{MOVE_1010,{0U,0U,0U}}, +{MOVE_1010,{1U,0U,0U}}, +{MOVE_1010,{2U,0U,0U}}, +{MOVE_1010,{3U,0U,0U}}, +{MOVE_1010,{4U,0U,0U}}, +{MOVE_1010,{5U,0U,0U}}, +{MOVE_1010,{6U,0U,0U}}, +{MOVE_1010,{7U,0U,0U}}, +{MOVE_1018,{0U,0U,0U}}, +{MOVE_1018,{1U,0U,0U}}, +{MOVE_1018,{2U,0U,0U}}, +{MOVE_1018,{3U,0U,0U}}, +{MOVE_1018,{4U,0U,0U}}, +{MOVE_1018,{5U,0U,0U}}, +{MOVE_1018,{6U,0U,0U}}, +{MOVE_1018,{7U,0U,0U}}, +{MOVE_1020,{0U,0U,0U}}, +{MOVE_1020,{1U,0U,0U}}, +{MOVE_1020,{2U,0U,0U}}, +{MOVE_1020,{3U,0U,0U}}, +{MOVE_1020,{4U,0U,0U}}, +{MOVE_1020,{5U,0U,0U}}, +{MOVE_1020,{6U,0U,0U}}, +{MOVE_1020,{7U,0U,0U}}, +{MOVE_1028,{0U,0U,0U}}, +{MOVE_1028,{1U,0U,0U}}, +{MOVE_1028,{2U,0U,0U}}, +{MOVE_1028,{3U,0U,0U}}, +{MOVE_1028,{4U,0U,0U}}, +{MOVE_1028,{5U,0U,0U}}, +{MOVE_1028,{6U,0U,0U}}, +{MOVE_1028,{7U,0U,0U}}, +{MOVE_1030,{0U,0U,0U}}, +{MOVE_1030,{1U,0U,0U}}, +{MOVE_1030,{2U,0U,0U}}, +{MOVE_1030,{3U,0U,0U}}, +{MOVE_1030,{4U,0U,0U}}, +{MOVE_1030,{5U,0U,0U}}, +{MOVE_1030,{6U,0U,0U}}, +{MOVE_1030,{7U,0U,0U}}, +{MOVE_1038,{0U,0U,0U}}, +{MOVE_1039,{0U,0U,0U}}, +{MOVE_103A,{0U,0U,0U}}, +{MOVE_103B,{0U,0U,0U}}, +{MOVE_103C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1080,{0U,0U,0U}}, +{MOVE_1080,{1U,0U,0U}}, +{MOVE_1080,{2U,0U,0U}}, +{MOVE_1080,{3U,0U,0U}}, +{MOVE_1080,{4U,0U,0U}}, +{MOVE_1080,{5U,0U,0U}}, +{MOVE_1080,{6U,0U,0U}}, +{MOVE_1080,{7U,0U,0U}}, +{MOVE_1088,{0U,0U,0U}}, +{MOVE_1088,{1U,0U,0U}}, +{MOVE_1088,{2U,0U,0U}}, +{MOVE_1088,{3U,0U,0U}}, +{MOVE_1088,{4U,0U,0U}}, +{MOVE_1088,{5U,0U,0U}}, +{MOVE_1088,{6U,0U,0U}}, +{MOVE_1088,{7U,0U,0U}}, +{MOVE_1090,{0U,0U,0U}}, +{MOVE_1090,{1U,0U,0U}}, +{MOVE_1090,{2U,0U,0U}}, +{MOVE_1090,{3U,0U,0U}}, +{MOVE_1090,{4U,0U,0U}}, +{MOVE_1090,{5U,0U,0U}}, +{MOVE_1090,{6U,0U,0U}}, +{MOVE_1090,{7U,0U,0U}}, +{MOVE_1098,{0U,0U,0U}}, +{MOVE_1098,{1U,0U,0U}}, +{MOVE_1098,{2U,0U,0U}}, +{MOVE_1098,{3U,0U,0U}}, +{MOVE_1098,{4U,0U,0U}}, +{MOVE_1098,{5U,0U,0U}}, +{MOVE_1098,{6U,0U,0U}}, +{MOVE_1098,{7U,0U,0U}}, +{MOVE_10A0,{0U,0U,0U}}, +{MOVE_10A0,{1U,0U,0U}}, +{MOVE_10A0,{2U,0U,0U}}, +{MOVE_10A0,{3U,0U,0U}}, +{MOVE_10A0,{4U,0U,0U}}, +{MOVE_10A0,{5U,0U,0U}}, +{MOVE_10A0,{6U,0U,0U}}, +{MOVE_10A0,{7U,0U,0U}}, +{MOVE_10A8,{0U,0U,0U}}, +{MOVE_10A8,{1U,0U,0U}}, +{MOVE_10A8,{2U,0U,0U}}, +{MOVE_10A8,{3U,0U,0U}}, +{MOVE_10A8,{4U,0U,0U}}, +{MOVE_10A8,{5U,0U,0U}}, +{MOVE_10A8,{6U,0U,0U}}, +{MOVE_10A8,{7U,0U,0U}}, +{MOVE_10B0,{0U,0U,0U}}, +{MOVE_10B0,{1U,0U,0U}}, +{MOVE_10B0,{2U,0U,0U}}, +{MOVE_10B0,{3U,0U,0U}}, +{MOVE_10B0,{4U,0U,0U}}, +{MOVE_10B0,{5U,0U,0U}}, +{MOVE_10B0,{6U,0U,0U}}, +{MOVE_10B0,{7U,0U,0U}}, +{MOVE_10B8,{0U,0U,0U}}, +{MOVE_10B9,{0U,0U,0U}}, +{MOVE_10BA,{0U,0U,0U}}, +{MOVE_10BB,{0U,0U,0U}}, +{MOVE_10BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_10C0,{0U,0U,0U}}, +{MOVE_10C0,{1U,0U,0U}}, +{MOVE_10C0,{2U,0U,0U}}, +{MOVE_10C0,{3U,0U,0U}}, +{MOVE_10C0,{4U,0U,0U}}, +{MOVE_10C0,{5U,0U,0U}}, +{MOVE_10C0,{6U,0U,0U}}, +{MOVE_10C0,{7U,0U,0U}}, +{MOVE_10C8,{0U,0U,0U}}, +{MOVE_10C8,{1U,0U,0U}}, +{MOVE_10C8,{2U,0U,0U}}, +{MOVE_10C8,{3U,0U,0U}}, +{MOVE_10C8,{4U,0U,0U}}, +{MOVE_10C8,{5U,0U,0U}}, +{MOVE_10C8,{6U,0U,0U}}, +{MOVE_10C8,{7U,0U,0U}}, +{MOVE_10D0,{0U,0U,0U}}, +{MOVE_10D0,{1U,0U,0U}}, +{MOVE_10D0,{2U,0U,0U}}, +{MOVE_10D0,{3U,0U,0U}}, +{MOVE_10D0,{4U,0U,0U}}, +{MOVE_10D0,{5U,0U,0U}}, +{MOVE_10D0,{6U,0U,0U}}, +{MOVE_10D0,{7U,0U,0U}}, +{MOVE_10D8,{0U,0U,0U}}, +{MOVE_10D8,{1U,0U,0U}}, +{MOVE_10D8,{2U,0U,0U}}, +{MOVE_10D8,{3U,0U,0U}}, +{MOVE_10D8,{4U,0U,0U}}, +{MOVE_10D8,{5U,0U,0U}}, +{MOVE_10D8,{6U,0U,0U}}, +{MOVE_10D8,{7U,0U,0U}}, +{MOVE_10E0,{0U,0U,0U}}, +{MOVE_10E0,{1U,0U,0U}}, +{MOVE_10E0,{2U,0U,0U}}, +{MOVE_10E0,{3U,0U,0U}}, +{MOVE_10E0,{4U,0U,0U}}, +{MOVE_10E0,{5U,0U,0U}}, +{MOVE_10E0,{6U,0U,0U}}, +{MOVE_10E0,{7U,0U,0U}}, +{MOVE_10E8,{0U,0U,0U}}, +{MOVE_10E8,{1U,0U,0U}}, +{MOVE_10E8,{2U,0U,0U}}, +{MOVE_10E8,{3U,0U,0U}}, +{MOVE_10E8,{4U,0U,0U}}, +{MOVE_10E8,{5U,0U,0U}}, +{MOVE_10E8,{6U,0U,0U}}, +{MOVE_10E8,{7U,0U,0U}}, +{MOVE_10F0,{0U,0U,0U}}, +{MOVE_10F0,{1U,0U,0U}}, +{MOVE_10F0,{2U,0U,0U}}, +{MOVE_10F0,{3U,0U,0U}}, +{MOVE_10F0,{4U,0U,0U}}, +{MOVE_10F0,{5U,0U,0U}}, +{MOVE_10F0,{6U,0U,0U}}, +{MOVE_10F0,{7U,0U,0U}}, +{MOVE_10F8,{0U,0U,0U}}, +{MOVE_10F9,{0U,0U,0U}}, +{MOVE_10FA,{0U,0U,0U}}, +{MOVE_10FB,{0U,0U,0U}}, +{MOVE_10FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1100,{0U,0U,0U}}, +{MOVE_1100,{1U,0U,0U}}, +{MOVE_1100,{2U,0U,0U}}, +{MOVE_1100,{3U,0U,0U}}, +{MOVE_1100,{4U,0U,0U}}, +{MOVE_1100,{5U,0U,0U}}, +{MOVE_1100,{6U,0U,0U}}, +{MOVE_1100,{7U,0U,0U}}, +{MOVE_1108,{0U,0U,0U}}, +{MOVE_1108,{1U,0U,0U}}, +{MOVE_1108,{2U,0U,0U}}, +{MOVE_1108,{3U,0U,0U}}, +{MOVE_1108,{4U,0U,0U}}, +{MOVE_1108,{5U,0U,0U}}, +{MOVE_1108,{6U,0U,0U}}, +{MOVE_1108,{7U,0U,0U}}, +{MOVE_1110,{0U,0U,0U}}, +{MOVE_1110,{1U,0U,0U}}, +{MOVE_1110,{2U,0U,0U}}, +{MOVE_1110,{3U,0U,0U}}, +{MOVE_1110,{4U,0U,0U}}, +{MOVE_1110,{5U,0U,0U}}, +{MOVE_1110,{6U,0U,0U}}, +{MOVE_1110,{7U,0U,0U}}, +{MOVE_1118,{0U,0U,0U}}, +{MOVE_1118,{1U,0U,0U}}, +{MOVE_1118,{2U,0U,0U}}, +{MOVE_1118,{3U,0U,0U}}, +{MOVE_1118,{4U,0U,0U}}, +{MOVE_1118,{5U,0U,0U}}, +{MOVE_1118,{6U,0U,0U}}, +{MOVE_1118,{7U,0U,0U}}, +{MOVE_1120,{0U,0U,0U}}, +{MOVE_1120,{1U,0U,0U}}, +{MOVE_1120,{2U,0U,0U}}, +{MOVE_1120,{3U,0U,0U}}, +{MOVE_1120,{4U,0U,0U}}, +{MOVE_1120,{5U,0U,0U}}, +{MOVE_1120,{6U,0U,0U}}, +{MOVE_1120,{7U,0U,0U}}, +{MOVE_1128,{0U,0U,0U}}, +{MOVE_1128,{1U,0U,0U}}, +{MOVE_1128,{2U,0U,0U}}, +{MOVE_1128,{3U,0U,0U}}, +{MOVE_1128,{4U,0U,0U}}, +{MOVE_1128,{5U,0U,0U}}, +{MOVE_1128,{6U,0U,0U}}, +{MOVE_1128,{7U,0U,0U}}, +{MOVE_1130,{0U,0U,0U}}, +{MOVE_1130,{1U,0U,0U}}, +{MOVE_1130,{2U,0U,0U}}, +{MOVE_1130,{3U,0U,0U}}, +{MOVE_1130,{4U,0U,0U}}, +{MOVE_1130,{5U,0U,0U}}, +{MOVE_1130,{6U,0U,0U}}, +{MOVE_1130,{7U,0U,0U}}, +{MOVE_1138,{0U,0U,0U}}, +{MOVE_1139,{0U,0U,0U}}, +{MOVE_113A,{0U,0U,0U}}, +{MOVE_113B,{0U,0U,0U}}, +{MOVE_113C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1140,{0U,0U,0U}}, +{MOVE_1140,{1U,0U,0U}}, +{MOVE_1140,{2U,0U,0U}}, +{MOVE_1140,{3U,0U,0U}}, +{MOVE_1140,{4U,0U,0U}}, +{MOVE_1140,{5U,0U,0U}}, +{MOVE_1140,{6U,0U,0U}}, +{MOVE_1140,{7U,0U,0U}}, +{MOVE_1148,{0U,0U,0U}}, +{MOVE_1148,{1U,0U,0U}}, +{MOVE_1148,{2U,0U,0U}}, +{MOVE_1148,{3U,0U,0U}}, +{MOVE_1148,{4U,0U,0U}}, +{MOVE_1148,{5U,0U,0U}}, +{MOVE_1148,{6U,0U,0U}}, +{MOVE_1148,{7U,0U,0U}}, +{MOVE_1150,{0U,0U,0U}}, +{MOVE_1150,{1U,0U,0U}}, +{MOVE_1150,{2U,0U,0U}}, +{MOVE_1150,{3U,0U,0U}}, +{MOVE_1150,{4U,0U,0U}}, +{MOVE_1150,{5U,0U,0U}}, +{MOVE_1150,{6U,0U,0U}}, +{MOVE_1150,{7U,0U,0U}}, +{MOVE_1158,{0U,0U,0U}}, +{MOVE_1158,{1U,0U,0U}}, +{MOVE_1158,{2U,0U,0U}}, +{MOVE_1158,{3U,0U,0U}}, +{MOVE_1158,{4U,0U,0U}}, +{MOVE_1158,{5U,0U,0U}}, +{MOVE_1158,{6U,0U,0U}}, +{MOVE_1158,{7U,0U,0U}}, +{MOVE_1160,{0U,0U,0U}}, +{MOVE_1160,{1U,0U,0U}}, +{MOVE_1160,{2U,0U,0U}}, +{MOVE_1160,{3U,0U,0U}}, +{MOVE_1160,{4U,0U,0U}}, +{MOVE_1160,{5U,0U,0U}}, +{MOVE_1160,{6U,0U,0U}}, +{MOVE_1160,{7U,0U,0U}}, +{MOVE_1168,{0U,0U,0U}}, +{MOVE_1168,{1U,0U,0U}}, +{MOVE_1168,{2U,0U,0U}}, +{MOVE_1168,{3U,0U,0U}}, +{MOVE_1168,{4U,0U,0U}}, +{MOVE_1168,{5U,0U,0U}}, +{MOVE_1168,{6U,0U,0U}}, +{MOVE_1168,{7U,0U,0U}}, +{MOVE_1170,{0U,0U,0U}}, +{MOVE_1170,{1U,0U,0U}}, +{MOVE_1170,{2U,0U,0U}}, +{MOVE_1170,{3U,0U,0U}}, +{MOVE_1170,{4U,0U,0U}}, +{MOVE_1170,{5U,0U,0U}}, +{MOVE_1170,{6U,0U,0U}}, +{MOVE_1170,{7U,0U,0U}}, +{MOVE_1178,{0U,0U,0U}}, +{MOVE_1179,{0U,0U,0U}}, +{MOVE_117A,{0U,0U,0U}}, +{MOVE_117B,{0U,0U,0U}}, +{MOVE_117C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1180,{0U,0U,0U}}, +{MOVE_1180,{1U,0U,0U}}, +{MOVE_1180,{2U,0U,0U}}, +{MOVE_1180,{3U,0U,0U}}, +{MOVE_1180,{4U,0U,0U}}, +{MOVE_1180,{5U,0U,0U}}, +{MOVE_1180,{6U,0U,0U}}, +{MOVE_1180,{7U,0U,0U}}, +{MOVE_1188,{0U,0U,0U}}, +{MOVE_1188,{1U,0U,0U}}, +{MOVE_1188,{2U,0U,0U}}, +{MOVE_1188,{3U,0U,0U}}, +{MOVE_1188,{4U,0U,0U}}, +{MOVE_1188,{5U,0U,0U}}, +{MOVE_1188,{6U,0U,0U}}, +{MOVE_1188,{7U,0U,0U}}, +{MOVE_1190,{0U,0U,0U}}, +{MOVE_1190,{1U,0U,0U}}, +{MOVE_1190,{2U,0U,0U}}, +{MOVE_1190,{3U,0U,0U}}, +{MOVE_1190,{4U,0U,0U}}, +{MOVE_1190,{5U,0U,0U}}, +{MOVE_1190,{6U,0U,0U}}, +{MOVE_1190,{7U,0U,0U}}, +{MOVE_1198,{0U,0U,0U}}, +{MOVE_1198,{1U,0U,0U}}, +{MOVE_1198,{2U,0U,0U}}, +{MOVE_1198,{3U,0U,0U}}, +{MOVE_1198,{4U,0U,0U}}, +{MOVE_1198,{5U,0U,0U}}, +{MOVE_1198,{6U,0U,0U}}, +{MOVE_1198,{7U,0U,0U}}, +{MOVE_11A0,{0U,0U,0U}}, +{MOVE_11A0,{1U,0U,0U}}, +{MOVE_11A0,{2U,0U,0U}}, +{MOVE_11A0,{3U,0U,0U}}, +{MOVE_11A0,{4U,0U,0U}}, +{MOVE_11A0,{5U,0U,0U}}, +{MOVE_11A0,{6U,0U,0U}}, +{MOVE_11A0,{7U,0U,0U}}, +{MOVE_11A8,{0U,0U,0U}}, +{MOVE_11A8,{1U,0U,0U}}, +{MOVE_11A8,{2U,0U,0U}}, +{MOVE_11A8,{3U,0U,0U}}, +{MOVE_11A8,{4U,0U,0U}}, +{MOVE_11A8,{5U,0U,0U}}, +{MOVE_11A8,{6U,0U,0U}}, +{MOVE_11A8,{7U,0U,0U}}, +{MOVE_11B0,{0U,0U,0U}}, +{MOVE_11B0,{1U,0U,0U}}, +{MOVE_11B0,{2U,0U,0U}}, +{MOVE_11B0,{3U,0U,0U}}, +{MOVE_11B0,{4U,0U,0U}}, +{MOVE_11B0,{5U,0U,0U}}, +{MOVE_11B0,{6U,0U,0U}}, +{MOVE_11B0,{7U,0U,0U}}, +{MOVE_11B8,{0U,0U,0U}}, +{MOVE_11B9,{0U,0U,0U}}, +{MOVE_11BA,{0U,0U,0U}}, +{MOVE_11BB,{0U,0U,0U}}, +{MOVE_11BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_11C0,{0U,0U,0U}}, +{MOVE_11C0,{1U,0U,0U}}, +{MOVE_11C0,{2U,0U,0U}}, +{MOVE_11C0,{3U,0U,0U}}, +{MOVE_11C0,{4U,0U,0U}}, +{MOVE_11C0,{5U,0U,0U}}, +{MOVE_11C0,{6U,0U,0U}}, +{MOVE_11C0,{7U,0U,0U}}, +{MOVE_11C8,{0U,0U,0U}}, +{MOVE_11C8,{1U,0U,0U}}, +{MOVE_11C8,{2U,0U,0U}}, +{MOVE_11C8,{3U,0U,0U}}, +{MOVE_11C8,{4U,0U,0U}}, +{MOVE_11C8,{5U,0U,0U}}, +{MOVE_11C8,{6U,0U,0U}}, +{MOVE_11C8,{7U,0U,0U}}, +{MOVE_11D0,{0U,0U,0U}}, +{MOVE_11D0,{1U,0U,0U}}, +{MOVE_11D0,{2U,0U,0U}}, +{MOVE_11D0,{3U,0U,0U}}, +{MOVE_11D0,{4U,0U,0U}}, +{MOVE_11D0,{5U,0U,0U}}, +{MOVE_11D0,{6U,0U,0U}}, +{MOVE_11D0,{7U,0U,0U}}, +{MOVE_11D8,{0U,0U,0U}}, +{MOVE_11D8,{1U,0U,0U}}, +{MOVE_11D8,{2U,0U,0U}}, +{MOVE_11D8,{3U,0U,0U}}, +{MOVE_11D8,{4U,0U,0U}}, +{MOVE_11D8,{5U,0U,0U}}, +{MOVE_11D8,{6U,0U,0U}}, +{MOVE_11D8,{7U,0U,0U}}, +{MOVE_11E0,{0U,0U,0U}}, +{MOVE_11E0,{1U,0U,0U}}, +{MOVE_11E0,{2U,0U,0U}}, +{MOVE_11E0,{3U,0U,0U}}, +{MOVE_11E0,{4U,0U,0U}}, +{MOVE_11E0,{5U,0U,0U}}, +{MOVE_11E0,{6U,0U,0U}}, +{MOVE_11E0,{7U,0U,0U}}, +{MOVE_11E8,{0U,0U,0U}}, +{MOVE_11E8,{1U,0U,0U}}, +{MOVE_11E8,{2U,0U,0U}}, +{MOVE_11E8,{3U,0U,0U}}, +{MOVE_11E8,{4U,0U,0U}}, +{MOVE_11E8,{5U,0U,0U}}, +{MOVE_11E8,{6U,0U,0U}}, +{MOVE_11E8,{7U,0U,0U}}, +{MOVE_11F0,{0U,0U,0U}}, +{MOVE_11F0,{1U,0U,0U}}, +{MOVE_11F0,{2U,0U,0U}}, +{MOVE_11F0,{3U,0U,0U}}, +{MOVE_11F0,{4U,0U,0U}}, +{MOVE_11F0,{5U,0U,0U}}, +{MOVE_11F0,{6U,0U,0U}}, +{MOVE_11F0,{7U,0U,0U}}, +{MOVE_11F8,{0U,0U,0U}}, +{MOVE_11F9,{0U,0U,0U}}, +{MOVE_11FA,{0U,0U,0U}}, +{MOVE_11FB,{0U,0U,0U}}, +{MOVE_11FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1000,{0U,1U,0U}}, +{MOVE_1000,{1U,1U,0U}}, +{MOVE_1000,{2U,1U,0U}}, +{MOVE_1000,{3U,1U,0U}}, +{MOVE_1000,{4U,1U,0U}}, +{MOVE_1000,{5U,1U,0U}}, +{MOVE_1000,{6U,1U,0U}}, +{MOVE_1000,{7U,1U,0U}}, +{MOVE_1008,{0U,1U,0U}}, +{MOVE_1008,{1U,1U,0U}}, +{MOVE_1008,{2U,1U,0U}}, +{MOVE_1008,{3U,1U,0U}}, +{MOVE_1008,{4U,1U,0U}}, +{MOVE_1008,{5U,1U,0U}}, +{MOVE_1008,{6U,1U,0U}}, +{MOVE_1008,{7U,1U,0U}}, +{MOVE_1010,{0U,1U,0U}}, +{MOVE_1010,{1U,1U,0U}}, +{MOVE_1010,{2U,1U,0U}}, +{MOVE_1010,{3U,1U,0U}}, +{MOVE_1010,{4U,1U,0U}}, +{MOVE_1010,{5U,1U,0U}}, +{MOVE_1010,{6U,1U,0U}}, +{MOVE_1010,{7U,1U,0U}}, +{MOVE_1018,{0U,1U,0U}}, +{MOVE_1018,{1U,1U,0U}}, +{MOVE_1018,{2U,1U,0U}}, +{MOVE_1018,{3U,1U,0U}}, +{MOVE_1018,{4U,1U,0U}}, +{MOVE_1018,{5U,1U,0U}}, +{MOVE_1018,{6U,1U,0U}}, +{MOVE_1018,{7U,1U,0U}}, +{MOVE_1020,{0U,1U,0U}}, +{MOVE_1020,{1U,1U,0U}}, +{MOVE_1020,{2U,1U,0U}}, +{MOVE_1020,{3U,1U,0U}}, +{MOVE_1020,{4U,1U,0U}}, +{MOVE_1020,{5U,1U,0U}}, +{MOVE_1020,{6U,1U,0U}}, +{MOVE_1020,{7U,1U,0U}}, +{MOVE_1028,{0U,1U,0U}}, +{MOVE_1028,{1U,1U,0U}}, +{MOVE_1028,{2U,1U,0U}}, +{MOVE_1028,{3U,1U,0U}}, +{MOVE_1028,{4U,1U,0U}}, +{MOVE_1028,{5U,1U,0U}}, +{MOVE_1028,{6U,1U,0U}}, +{MOVE_1028,{7U,1U,0U}}, +{MOVE_1030,{0U,1U,0U}}, +{MOVE_1030,{1U,1U,0U}}, +{MOVE_1030,{2U,1U,0U}}, +{MOVE_1030,{3U,1U,0U}}, +{MOVE_1030,{4U,1U,0U}}, +{MOVE_1030,{5U,1U,0U}}, +{MOVE_1030,{6U,1U,0U}}, +{MOVE_1030,{7U,1U,0U}}, +{MOVE_1038,{0U,1U,0U}}, +{MOVE_1039,{0U,1U,0U}}, +{MOVE_103A,{0U,1U,0U}}, +{MOVE_103B,{0U,1U,0U}}, +{MOVE_103C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1080,{0U,1U,0U}}, +{MOVE_1080,{1U,1U,0U}}, +{MOVE_1080,{2U,1U,0U}}, +{MOVE_1080,{3U,1U,0U}}, +{MOVE_1080,{4U,1U,0U}}, +{MOVE_1080,{5U,1U,0U}}, +{MOVE_1080,{6U,1U,0U}}, +{MOVE_1080,{7U,1U,0U}}, +{MOVE_1088,{0U,1U,0U}}, +{MOVE_1088,{1U,1U,0U}}, +{MOVE_1088,{2U,1U,0U}}, +{MOVE_1088,{3U,1U,0U}}, +{MOVE_1088,{4U,1U,0U}}, +{MOVE_1088,{5U,1U,0U}}, +{MOVE_1088,{6U,1U,0U}}, +{MOVE_1088,{7U,1U,0U}}, +{MOVE_1090,{0U,1U,0U}}, +{MOVE_1090,{1U,1U,0U}}, +{MOVE_1090,{2U,1U,0U}}, +{MOVE_1090,{3U,1U,0U}}, +{MOVE_1090,{4U,1U,0U}}, +{MOVE_1090,{5U,1U,0U}}, +{MOVE_1090,{6U,1U,0U}}, +{MOVE_1090,{7U,1U,0U}}, +{MOVE_1098,{0U,1U,0U}}, +{MOVE_1098,{1U,1U,0U}}, +{MOVE_1098,{2U,1U,0U}}, +{MOVE_1098,{3U,1U,0U}}, +{MOVE_1098,{4U,1U,0U}}, +{MOVE_1098,{5U,1U,0U}}, +{MOVE_1098,{6U,1U,0U}}, +{MOVE_1098,{7U,1U,0U}}, +{MOVE_10A0,{0U,1U,0U}}, +{MOVE_10A0,{1U,1U,0U}}, +{MOVE_10A0,{2U,1U,0U}}, +{MOVE_10A0,{3U,1U,0U}}, +{MOVE_10A0,{4U,1U,0U}}, +{MOVE_10A0,{5U,1U,0U}}, +{MOVE_10A0,{6U,1U,0U}}, +{MOVE_10A0,{7U,1U,0U}}, +{MOVE_10A8,{0U,1U,0U}}, +{MOVE_10A8,{1U,1U,0U}}, +{MOVE_10A8,{2U,1U,0U}}, +{MOVE_10A8,{3U,1U,0U}}, +{MOVE_10A8,{4U,1U,0U}}, +{MOVE_10A8,{5U,1U,0U}}, +{MOVE_10A8,{6U,1U,0U}}, +{MOVE_10A8,{7U,1U,0U}}, +{MOVE_10B0,{0U,1U,0U}}, +{MOVE_10B0,{1U,1U,0U}}, +{MOVE_10B0,{2U,1U,0U}}, +{MOVE_10B0,{3U,1U,0U}}, +{MOVE_10B0,{4U,1U,0U}}, +{MOVE_10B0,{5U,1U,0U}}, +{MOVE_10B0,{6U,1U,0U}}, +{MOVE_10B0,{7U,1U,0U}}, +{MOVE_10B8,{0U,1U,0U}}, +{MOVE_10B9,{0U,1U,0U}}, +{MOVE_10BA,{0U,1U,0U}}, +{MOVE_10BB,{0U,1U,0U}}, +{MOVE_10BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_10C0,{0U,1U,0U}}, +{MOVE_10C0,{1U,1U,0U}}, +{MOVE_10C0,{2U,1U,0U}}, +{MOVE_10C0,{3U,1U,0U}}, +{MOVE_10C0,{4U,1U,0U}}, +{MOVE_10C0,{5U,1U,0U}}, +{MOVE_10C0,{6U,1U,0U}}, +{MOVE_10C0,{7U,1U,0U}}, +{MOVE_10C8,{0U,1U,0U}}, +{MOVE_10C8,{1U,1U,0U}}, +{MOVE_10C8,{2U,1U,0U}}, +{MOVE_10C8,{3U,1U,0U}}, +{MOVE_10C8,{4U,1U,0U}}, +{MOVE_10C8,{5U,1U,0U}}, +{MOVE_10C8,{6U,1U,0U}}, +{MOVE_10C8,{7U,1U,0U}}, +{MOVE_10D0,{0U,1U,0U}}, +{MOVE_10D0,{1U,1U,0U}}, +{MOVE_10D0,{2U,1U,0U}}, +{MOVE_10D0,{3U,1U,0U}}, +{MOVE_10D0,{4U,1U,0U}}, +{MOVE_10D0,{5U,1U,0U}}, +{MOVE_10D0,{6U,1U,0U}}, +{MOVE_10D0,{7U,1U,0U}}, +{MOVE_10D8,{0U,1U,0U}}, +{MOVE_10D8,{1U,1U,0U}}, +{MOVE_10D8,{2U,1U,0U}}, +{MOVE_10D8,{3U,1U,0U}}, +{MOVE_10D8,{4U,1U,0U}}, +{MOVE_10D8,{5U,1U,0U}}, +{MOVE_10D8,{6U,1U,0U}}, +{MOVE_10D8,{7U,1U,0U}}, +{MOVE_10E0,{0U,1U,0U}}, +{MOVE_10E0,{1U,1U,0U}}, +{MOVE_10E0,{2U,1U,0U}}, +{MOVE_10E0,{3U,1U,0U}}, +{MOVE_10E0,{4U,1U,0U}}, +{MOVE_10E0,{5U,1U,0U}}, +{MOVE_10E0,{6U,1U,0U}}, +{MOVE_10E0,{7U,1U,0U}}, +{MOVE_10E8,{0U,1U,0U}}, +{MOVE_10E8,{1U,1U,0U}}, +{MOVE_10E8,{2U,1U,0U}}, +{MOVE_10E8,{3U,1U,0U}}, +{MOVE_10E8,{4U,1U,0U}}, +{MOVE_10E8,{5U,1U,0U}}, +{MOVE_10E8,{6U,1U,0U}}, +{MOVE_10E8,{7U,1U,0U}}, +{MOVE_10F0,{0U,1U,0U}}, +{MOVE_10F0,{1U,1U,0U}}, +{MOVE_10F0,{2U,1U,0U}}, +{MOVE_10F0,{3U,1U,0U}}, +{MOVE_10F0,{4U,1U,0U}}, +{MOVE_10F0,{5U,1U,0U}}, +{MOVE_10F0,{6U,1U,0U}}, +{MOVE_10F0,{7U,1U,0U}}, +{MOVE_10F8,{0U,1U,0U}}, +{MOVE_10F9,{0U,1U,0U}}, +{MOVE_10FA,{0U,1U,0U}}, +{MOVE_10FB,{0U,1U,0U}}, +{MOVE_10FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1100,{0U,1U,0U}}, +{MOVE_1100,{1U,1U,0U}}, +{MOVE_1100,{2U,1U,0U}}, +{MOVE_1100,{3U,1U,0U}}, +{MOVE_1100,{4U,1U,0U}}, +{MOVE_1100,{5U,1U,0U}}, +{MOVE_1100,{6U,1U,0U}}, +{MOVE_1100,{7U,1U,0U}}, +{MOVE_1108,{0U,1U,0U}}, +{MOVE_1108,{1U,1U,0U}}, +{MOVE_1108,{2U,1U,0U}}, +{MOVE_1108,{3U,1U,0U}}, +{MOVE_1108,{4U,1U,0U}}, +{MOVE_1108,{5U,1U,0U}}, +{MOVE_1108,{6U,1U,0U}}, +{MOVE_1108,{7U,1U,0U}}, +{MOVE_1110,{0U,1U,0U}}, +{MOVE_1110,{1U,1U,0U}}, +{MOVE_1110,{2U,1U,0U}}, +{MOVE_1110,{3U,1U,0U}}, +{MOVE_1110,{4U,1U,0U}}, +{MOVE_1110,{5U,1U,0U}}, +{MOVE_1110,{6U,1U,0U}}, +{MOVE_1110,{7U,1U,0U}}, +{MOVE_1118,{0U,1U,0U}}, +{MOVE_1118,{1U,1U,0U}}, +{MOVE_1118,{2U,1U,0U}}, +{MOVE_1118,{3U,1U,0U}}, +{MOVE_1118,{4U,1U,0U}}, +{MOVE_1118,{5U,1U,0U}}, +{MOVE_1118,{6U,1U,0U}}, +{MOVE_1118,{7U,1U,0U}}, +{MOVE_1120,{0U,1U,0U}}, +{MOVE_1120,{1U,1U,0U}}, +{MOVE_1120,{2U,1U,0U}}, +{MOVE_1120,{3U,1U,0U}}, +{MOVE_1120,{4U,1U,0U}}, +{MOVE_1120,{5U,1U,0U}}, +{MOVE_1120,{6U,1U,0U}}, +{MOVE_1120,{7U,1U,0U}}, +{MOVE_1128,{0U,1U,0U}}, +{MOVE_1128,{1U,1U,0U}}, +{MOVE_1128,{2U,1U,0U}}, +{MOVE_1128,{3U,1U,0U}}, +{MOVE_1128,{4U,1U,0U}}, +{MOVE_1128,{5U,1U,0U}}, +{MOVE_1128,{6U,1U,0U}}, +{MOVE_1128,{7U,1U,0U}}, +{MOVE_1130,{0U,1U,0U}}, +{MOVE_1130,{1U,1U,0U}}, +{MOVE_1130,{2U,1U,0U}}, +{MOVE_1130,{3U,1U,0U}}, +{MOVE_1130,{4U,1U,0U}}, +{MOVE_1130,{5U,1U,0U}}, +{MOVE_1130,{6U,1U,0U}}, +{MOVE_1130,{7U,1U,0U}}, +{MOVE_1138,{0U,1U,0U}}, +{MOVE_1139,{0U,1U,0U}}, +{MOVE_113A,{0U,1U,0U}}, +{MOVE_113B,{0U,1U,0U}}, +{MOVE_113C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1140,{0U,1U,0U}}, +{MOVE_1140,{1U,1U,0U}}, +{MOVE_1140,{2U,1U,0U}}, +{MOVE_1140,{3U,1U,0U}}, +{MOVE_1140,{4U,1U,0U}}, +{MOVE_1140,{5U,1U,0U}}, +{MOVE_1140,{6U,1U,0U}}, +{MOVE_1140,{7U,1U,0U}}, +{MOVE_1148,{0U,1U,0U}}, +{MOVE_1148,{1U,1U,0U}}, +{MOVE_1148,{2U,1U,0U}}, +{MOVE_1148,{3U,1U,0U}}, +{MOVE_1148,{4U,1U,0U}}, +{MOVE_1148,{5U,1U,0U}}, +{MOVE_1148,{6U,1U,0U}}, +{MOVE_1148,{7U,1U,0U}}, +{MOVE_1150,{0U,1U,0U}}, +{MOVE_1150,{1U,1U,0U}}, +{MOVE_1150,{2U,1U,0U}}, +{MOVE_1150,{3U,1U,0U}}, +{MOVE_1150,{4U,1U,0U}}, +{MOVE_1150,{5U,1U,0U}}, +{MOVE_1150,{6U,1U,0U}}, +{MOVE_1150,{7U,1U,0U}}, +{MOVE_1158,{0U,1U,0U}}, +{MOVE_1158,{1U,1U,0U}}, +{MOVE_1158,{2U,1U,0U}}, +{MOVE_1158,{3U,1U,0U}}, +{MOVE_1158,{4U,1U,0U}}, +{MOVE_1158,{5U,1U,0U}}, +{MOVE_1158,{6U,1U,0U}}, +{MOVE_1158,{7U,1U,0U}}, +{MOVE_1160,{0U,1U,0U}}, +{MOVE_1160,{1U,1U,0U}}, +{MOVE_1160,{2U,1U,0U}}, +{MOVE_1160,{3U,1U,0U}}, +{MOVE_1160,{4U,1U,0U}}, +{MOVE_1160,{5U,1U,0U}}, +{MOVE_1160,{6U,1U,0U}}, +{MOVE_1160,{7U,1U,0U}}, +{MOVE_1168,{0U,1U,0U}}, +{MOVE_1168,{1U,1U,0U}}, +{MOVE_1168,{2U,1U,0U}}, +{MOVE_1168,{3U,1U,0U}}, +{MOVE_1168,{4U,1U,0U}}, +{MOVE_1168,{5U,1U,0U}}, +{MOVE_1168,{6U,1U,0U}}, +{MOVE_1168,{7U,1U,0U}}, +{MOVE_1170,{0U,1U,0U}}, +{MOVE_1170,{1U,1U,0U}}, +{MOVE_1170,{2U,1U,0U}}, +{MOVE_1170,{3U,1U,0U}}, +{MOVE_1170,{4U,1U,0U}}, +{MOVE_1170,{5U,1U,0U}}, +{MOVE_1170,{6U,1U,0U}}, +{MOVE_1170,{7U,1U,0U}}, +{MOVE_1178,{0U,1U,0U}}, +{MOVE_1179,{0U,1U,0U}}, +{MOVE_117A,{0U,1U,0U}}, +{MOVE_117B,{0U,1U,0U}}, +{MOVE_117C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1180,{0U,1U,0U}}, +{MOVE_1180,{1U,1U,0U}}, +{MOVE_1180,{2U,1U,0U}}, +{MOVE_1180,{3U,1U,0U}}, +{MOVE_1180,{4U,1U,0U}}, +{MOVE_1180,{5U,1U,0U}}, +{MOVE_1180,{6U,1U,0U}}, +{MOVE_1180,{7U,1U,0U}}, +{MOVE_1188,{0U,1U,0U}}, +{MOVE_1188,{1U,1U,0U}}, +{MOVE_1188,{2U,1U,0U}}, +{MOVE_1188,{3U,1U,0U}}, +{MOVE_1188,{4U,1U,0U}}, +{MOVE_1188,{5U,1U,0U}}, +{MOVE_1188,{6U,1U,0U}}, +{MOVE_1188,{7U,1U,0U}}, +{MOVE_1190,{0U,1U,0U}}, +{MOVE_1190,{1U,1U,0U}}, +{MOVE_1190,{2U,1U,0U}}, +{MOVE_1190,{3U,1U,0U}}, +{MOVE_1190,{4U,1U,0U}}, +{MOVE_1190,{5U,1U,0U}}, +{MOVE_1190,{6U,1U,0U}}, +{MOVE_1190,{7U,1U,0U}}, +{MOVE_1198,{0U,1U,0U}}, +{MOVE_1198,{1U,1U,0U}}, +{MOVE_1198,{2U,1U,0U}}, +{MOVE_1198,{3U,1U,0U}}, +{MOVE_1198,{4U,1U,0U}}, +{MOVE_1198,{5U,1U,0U}}, +{MOVE_1198,{6U,1U,0U}}, +{MOVE_1198,{7U,1U,0U}}, +{MOVE_11A0,{0U,1U,0U}}, +{MOVE_11A0,{1U,1U,0U}}, +{MOVE_11A0,{2U,1U,0U}}, +{MOVE_11A0,{3U,1U,0U}}, +{MOVE_11A0,{4U,1U,0U}}, +{MOVE_11A0,{5U,1U,0U}}, +{MOVE_11A0,{6U,1U,0U}}, +{MOVE_11A0,{7U,1U,0U}}, +{MOVE_11A8,{0U,1U,0U}}, +{MOVE_11A8,{1U,1U,0U}}, +{MOVE_11A8,{2U,1U,0U}}, +{MOVE_11A8,{3U,1U,0U}}, +{MOVE_11A8,{4U,1U,0U}}, +{MOVE_11A8,{5U,1U,0U}}, +{MOVE_11A8,{6U,1U,0U}}, +{MOVE_11A8,{7U,1U,0U}}, +{MOVE_11B0,{0U,1U,0U}}, +{MOVE_11B0,{1U,1U,0U}}, +{MOVE_11B0,{2U,1U,0U}}, +{MOVE_11B0,{3U,1U,0U}}, +{MOVE_11B0,{4U,1U,0U}}, +{MOVE_11B0,{5U,1U,0U}}, +{MOVE_11B0,{6U,1U,0U}}, +{MOVE_11B0,{7U,1U,0U}}, +{MOVE_11B8,{0U,1U,0U}}, +{MOVE_11B9,{0U,1U,0U}}, +{MOVE_11BA,{0U,1U,0U}}, +{MOVE_11BB,{0U,1U,0U}}, +{MOVE_11BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_13C0,{0U,0U,0U}}, +{MOVE_13C0,{1U,0U,0U}}, +{MOVE_13C0,{2U,0U,0U}}, +{MOVE_13C0,{3U,0U,0U}}, +{MOVE_13C0,{4U,0U,0U}}, +{MOVE_13C0,{5U,0U,0U}}, +{MOVE_13C0,{6U,0U,0U}}, +{MOVE_13C0,{7U,0U,0U}}, +{MOVE_13C8,{0U,0U,0U}}, +{MOVE_13C8,{1U,0U,0U}}, +{MOVE_13C8,{2U,0U,0U}}, +{MOVE_13C8,{3U,0U,0U}}, +{MOVE_13C8,{4U,0U,0U}}, +{MOVE_13C8,{5U,0U,0U}}, +{MOVE_13C8,{6U,0U,0U}}, +{MOVE_13C8,{7U,0U,0U}}, +{MOVE_13D0,{0U,0U,0U}}, +{MOVE_13D0,{1U,0U,0U}}, +{MOVE_13D0,{2U,0U,0U}}, +{MOVE_13D0,{3U,0U,0U}}, +{MOVE_13D0,{4U,0U,0U}}, +{MOVE_13D0,{5U,0U,0U}}, +{MOVE_13D0,{6U,0U,0U}}, +{MOVE_13D0,{7U,0U,0U}}, +{MOVE_13D8,{0U,0U,0U}}, +{MOVE_13D8,{1U,0U,0U}}, +{MOVE_13D8,{2U,0U,0U}}, +{MOVE_13D8,{3U,0U,0U}}, +{MOVE_13D8,{4U,0U,0U}}, +{MOVE_13D8,{5U,0U,0U}}, +{MOVE_13D8,{6U,0U,0U}}, +{MOVE_13D8,{7U,0U,0U}}, +{MOVE_13E0,{0U,0U,0U}}, +{MOVE_13E0,{1U,0U,0U}}, +{MOVE_13E0,{2U,0U,0U}}, +{MOVE_13E0,{3U,0U,0U}}, +{MOVE_13E0,{4U,0U,0U}}, +{MOVE_13E0,{5U,0U,0U}}, +{MOVE_13E0,{6U,0U,0U}}, +{MOVE_13E0,{7U,0U,0U}}, +{MOVE_13E8,{0U,0U,0U}}, +{MOVE_13E8,{1U,0U,0U}}, +{MOVE_13E8,{2U,0U,0U}}, +{MOVE_13E8,{3U,0U,0U}}, +{MOVE_13E8,{4U,0U,0U}}, +{MOVE_13E8,{5U,0U,0U}}, +{MOVE_13E8,{6U,0U,0U}}, +{MOVE_13E8,{7U,0U,0U}}, +{MOVE_13F0,{0U,0U,0U}}, +{MOVE_13F0,{1U,0U,0U}}, +{MOVE_13F0,{2U,0U,0U}}, +{MOVE_13F0,{3U,0U,0U}}, +{MOVE_13F0,{4U,0U,0U}}, +{MOVE_13F0,{5U,0U,0U}}, +{MOVE_13F0,{6U,0U,0U}}, +{MOVE_13F0,{7U,0U,0U}}, +{MOVE_13F8,{0U,0U,0U}}, +{MOVE_13F9,{0U,0U,0U}}, +{MOVE_13FA,{0U,0U,0U}}, +{MOVE_13FB,{0U,0U,0U}}, +{MOVE_13FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1000,{0U,2U,0U}}, +{MOVE_1000,{1U,2U,0U}}, +{MOVE_1000,{2U,2U,0U}}, +{MOVE_1000,{3U,2U,0U}}, +{MOVE_1000,{4U,2U,0U}}, +{MOVE_1000,{5U,2U,0U}}, +{MOVE_1000,{6U,2U,0U}}, +{MOVE_1000,{7U,2U,0U}}, +{MOVE_1008,{0U,2U,0U}}, +{MOVE_1008,{1U,2U,0U}}, +{MOVE_1008,{2U,2U,0U}}, +{MOVE_1008,{3U,2U,0U}}, +{MOVE_1008,{4U,2U,0U}}, +{MOVE_1008,{5U,2U,0U}}, +{MOVE_1008,{6U,2U,0U}}, +{MOVE_1008,{7U,2U,0U}}, +{MOVE_1010,{0U,2U,0U}}, +{MOVE_1010,{1U,2U,0U}}, +{MOVE_1010,{2U,2U,0U}}, +{MOVE_1010,{3U,2U,0U}}, +{MOVE_1010,{4U,2U,0U}}, +{MOVE_1010,{5U,2U,0U}}, +{MOVE_1010,{6U,2U,0U}}, +{MOVE_1010,{7U,2U,0U}}, +{MOVE_1018,{0U,2U,0U}}, +{MOVE_1018,{1U,2U,0U}}, +{MOVE_1018,{2U,2U,0U}}, +{MOVE_1018,{3U,2U,0U}}, +{MOVE_1018,{4U,2U,0U}}, +{MOVE_1018,{5U,2U,0U}}, +{MOVE_1018,{6U,2U,0U}}, +{MOVE_1018,{7U,2U,0U}}, +{MOVE_1020,{0U,2U,0U}}, +{MOVE_1020,{1U,2U,0U}}, +{MOVE_1020,{2U,2U,0U}}, +{MOVE_1020,{3U,2U,0U}}, +{MOVE_1020,{4U,2U,0U}}, +{MOVE_1020,{5U,2U,0U}}, +{MOVE_1020,{6U,2U,0U}}, +{MOVE_1020,{7U,2U,0U}}, +{MOVE_1028,{0U,2U,0U}}, +{MOVE_1028,{1U,2U,0U}}, +{MOVE_1028,{2U,2U,0U}}, +{MOVE_1028,{3U,2U,0U}}, +{MOVE_1028,{4U,2U,0U}}, +{MOVE_1028,{5U,2U,0U}}, +{MOVE_1028,{6U,2U,0U}}, +{MOVE_1028,{7U,2U,0U}}, +{MOVE_1030,{0U,2U,0U}}, +{MOVE_1030,{1U,2U,0U}}, +{MOVE_1030,{2U,2U,0U}}, +{MOVE_1030,{3U,2U,0U}}, +{MOVE_1030,{4U,2U,0U}}, +{MOVE_1030,{5U,2U,0U}}, +{MOVE_1030,{6U,2U,0U}}, +{MOVE_1030,{7U,2U,0U}}, +{MOVE_1038,{0U,2U,0U}}, +{MOVE_1039,{0U,2U,0U}}, +{MOVE_103A,{0U,2U,0U}}, +{MOVE_103B,{0U,2U,0U}}, +{MOVE_103C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1080,{0U,2U,0U}}, +{MOVE_1080,{1U,2U,0U}}, +{MOVE_1080,{2U,2U,0U}}, +{MOVE_1080,{3U,2U,0U}}, +{MOVE_1080,{4U,2U,0U}}, +{MOVE_1080,{5U,2U,0U}}, +{MOVE_1080,{6U,2U,0U}}, +{MOVE_1080,{7U,2U,0U}}, +{MOVE_1088,{0U,2U,0U}}, +{MOVE_1088,{1U,2U,0U}}, +{MOVE_1088,{2U,2U,0U}}, +{MOVE_1088,{3U,2U,0U}}, +{MOVE_1088,{4U,2U,0U}}, +{MOVE_1088,{5U,2U,0U}}, +{MOVE_1088,{6U,2U,0U}}, +{MOVE_1088,{7U,2U,0U}}, +{MOVE_1090,{0U,2U,0U}}, +{MOVE_1090,{1U,2U,0U}}, +{MOVE_1090,{2U,2U,0U}}, +{MOVE_1090,{3U,2U,0U}}, +{MOVE_1090,{4U,2U,0U}}, +{MOVE_1090,{5U,2U,0U}}, +{MOVE_1090,{6U,2U,0U}}, +{MOVE_1090,{7U,2U,0U}}, +{MOVE_1098,{0U,2U,0U}}, +{MOVE_1098,{1U,2U,0U}}, +{MOVE_1098,{2U,2U,0U}}, +{MOVE_1098,{3U,2U,0U}}, +{MOVE_1098,{4U,2U,0U}}, +{MOVE_1098,{5U,2U,0U}}, +{MOVE_1098,{6U,2U,0U}}, +{MOVE_1098,{7U,2U,0U}}, +{MOVE_10A0,{0U,2U,0U}}, +{MOVE_10A0,{1U,2U,0U}}, +{MOVE_10A0,{2U,2U,0U}}, +{MOVE_10A0,{3U,2U,0U}}, +{MOVE_10A0,{4U,2U,0U}}, +{MOVE_10A0,{5U,2U,0U}}, +{MOVE_10A0,{6U,2U,0U}}, +{MOVE_10A0,{7U,2U,0U}}, +{MOVE_10A8,{0U,2U,0U}}, +{MOVE_10A8,{1U,2U,0U}}, +{MOVE_10A8,{2U,2U,0U}}, +{MOVE_10A8,{3U,2U,0U}}, +{MOVE_10A8,{4U,2U,0U}}, +{MOVE_10A8,{5U,2U,0U}}, +{MOVE_10A8,{6U,2U,0U}}, +{MOVE_10A8,{7U,2U,0U}}, +{MOVE_10B0,{0U,2U,0U}}, +{MOVE_10B0,{1U,2U,0U}}, +{MOVE_10B0,{2U,2U,0U}}, +{MOVE_10B0,{3U,2U,0U}}, +{MOVE_10B0,{4U,2U,0U}}, +{MOVE_10B0,{5U,2U,0U}}, +{MOVE_10B0,{6U,2U,0U}}, +{MOVE_10B0,{7U,2U,0U}}, +{MOVE_10B8,{0U,2U,0U}}, +{MOVE_10B9,{0U,2U,0U}}, +{MOVE_10BA,{0U,2U,0U}}, +{MOVE_10BB,{0U,2U,0U}}, +{MOVE_10BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_10C0,{0U,2U,0U}}, +{MOVE_10C0,{1U,2U,0U}}, +{MOVE_10C0,{2U,2U,0U}}, +{MOVE_10C0,{3U,2U,0U}}, +{MOVE_10C0,{4U,2U,0U}}, +{MOVE_10C0,{5U,2U,0U}}, +{MOVE_10C0,{6U,2U,0U}}, +{MOVE_10C0,{7U,2U,0U}}, +{MOVE_10C8,{0U,2U,0U}}, +{MOVE_10C8,{1U,2U,0U}}, +{MOVE_10C8,{2U,2U,0U}}, +{MOVE_10C8,{3U,2U,0U}}, +{MOVE_10C8,{4U,2U,0U}}, +{MOVE_10C8,{5U,2U,0U}}, +{MOVE_10C8,{6U,2U,0U}}, +{MOVE_10C8,{7U,2U,0U}}, +{MOVE_10D0,{0U,2U,0U}}, +{MOVE_10D0,{1U,2U,0U}}, +{MOVE_10D0,{2U,2U,0U}}, +{MOVE_10D0,{3U,2U,0U}}, +{MOVE_10D0,{4U,2U,0U}}, +{MOVE_10D0,{5U,2U,0U}}, +{MOVE_10D0,{6U,2U,0U}}, +{MOVE_10D0,{7U,2U,0U}}, +{MOVE_10D8,{0U,2U,0U}}, +{MOVE_10D8,{1U,2U,0U}}, +{MOVE_10D8,{2U,2U,0U}}, +{MOVE_10D8,{3U,2U,0U}}, +{MOVE_10D8,{4U,2U,0U}}, +{MOVE_10D8,{5U,2U,0U}}, +{MOVE_10D8,{6U,2U,0U}}, +{MOVE_10D8,{7U,2U,0U}}, +{MOVE_10E0,{0U,2U,0U}}, +{MOVE_10E0,{1U,2U,0U}}, +{MOVE_10E0,{2U,2U,0U}}, +{MOVE_10E0,{3U,2U,0U}}, +{MOVE_10E0,{4U,2U,0U}}, +{MOVE_10E0,{5U,2U,0U}}, +{MOVE_10E0,{6U,2U,0U}}, +{MOVE_10E0,{7U,2U,0U}}, +{MOVE_10E8,{0U,2U,0U}}, +{MOVE_10E8,{1U,2U,0U}}, +{MOVE_10E8,{2U,2U,0U}}, +{MOVE_10E8,{3U,2U,0U}}, +{MOVE_10E8,{4U,2U,0U}}, +{MOVE_10E8,{5U,2U,0U}}, +{MOVE_10E8,{6U,2U,0U}}, +{MOVE_10E8,{7U,2U,0U}}, +{MOVE_10F0,{0U,2U,0U}}, +{MOVE_10F0,{1U,2U,0U}}, +{MOVE_10F0,{2U,2U,0U}}, +{MOVE_10F0,{3U,2U,0U}}, +{MOVE_10F0,{4U,2U,0U}}, +{MOVE_10F0,{5U,2U,0U}}, +{MOVE_10F0,{6U,2U,0U}}, +{MOVE_10F0,{7U,2U,0U}}, +{MOVE_10F8,{0U,2U,0U}}, +{MOVE_10F9,{0U,2U,0U}}, +{MOVE_10FA,{0U,2U,0U}}, +{MOVE_10FB,{0U,2U,0U}}, +{MOVE_10FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1100,{0U,2U,0U}}, +{MOVE_1100,{1U,2U,0U}}, +{MOVE_1100,{2U,2U,0U}}, +{MOVE_1100,{3U,2U,0U}}, +{MOVE_1100,{4U,2U,0U}}, +{MOVE_1100,{5U,2U,0U}}, +{MOVE_1100,{6U,2U,0U}}, +{MOVE_1100,{7U,2U,0U}}, +{MOVE_1108,{0U,2U,0U}}, +{MOVE_1108,{1U,2U,0U}}, +{MOVE_1108,{2U,2U,0U}}, +{MOVE_1108,{3U,2U,0U}}, +{MOVE_1108,{4U,2U,0U}}, +{MOVE_1108,{5U,2U,0U}}, +{MOVE_1108,{6U,2U,0U}}, +{MOVE_1108,{7U,2U,0U}}, +{MOVE_1110,{0U,2U,0U}}, +{MOVE_1110,{1U,2U,0U}}, +{MOVE_1110,{2U,2U,0U}}, +{MOVE_1110,{3U,2U,0U}}, +{MOVE_1110,{4U,2U,0U}}, +{MOVE_1110,{5U,2U,0U}}, +{MOVE_1110,{6U,2U,0U}}, +{MOVE_1110,{7U,2U,0U}}, +{MOVE_1118,{0U,2U,0U}}, +{MOVE_1118,{1U,2U,0U}}, +{MOVE_1118,{2U,2U,0U}}, +{MOVE_1118,{3U,2U,0U}}, +{MOVE_1118,{4U,2U,0U}}, +{MOVE_1118,{5U,2U,0U}}, +{MOVE_1118,{6U,2U,0U}}, +{MOVE_1118,{7U,2U,0U}}, +{MOVE_1120,{0U,2U,0U}}, +{MOVE_1120,{1U,2U,0U}}, +{MOVE_1120,{2U,2U,0U}}, +{MOVE_1120,{3U,2U,0U}}, +{MOVE_1120,{4U,2U,0U}}, +{MOVE_1120,{5U,2U,0U}}, +{MOVE_1120,{6U,2U,0U}}, +{MOVE_1120,{7U,2U,0U}}, +{MOVE_1128,{0U,2U,0U}}, +{MOVE_1128,{1U,2U,0U}}, +{MOVE_1128,{2U,2U,0U}}, +{MOVE_1128,{3U,2U,0U}}, +{MOVE_1128,{4U,2U,0U}}, +{MOVE_1128,{5U,2U,0U}}, +{MOVE_1128,{6U,2U,0U}}, +{MOVE_1128,{7U,2U,0U}}, +{MOVE_1130,{0U,2U,0U}}, +{MOVE_1130,{1U,2U,0U}}, +{MOVE_1130,{2U,2U,0U}}, +{MOVE_1130,{3U,2U,0U}}, +{MOVE_1130,{4U,2U,0U}}, +{MOVE_1130,{5U,2U,0U}}, +{MOVE_1130,{6U,2U,0U}}, +{MOVE_1130,{7U,2U,0U}}, +{MOVE_1138,{0U,2U,0U}}, +{MOVE_1139,{0U,2U,0U}}, +{MOVE_113A,{0U,2U,0U}}, +{MOVE_113B,{0U,2U,0U}}, +{MOVE_113C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1140,{0U,2U,0U}}, +{MOVE_1140,{1U,2U,0U}}, +{MOVE_1140,{2U,2U,0U}}, +{MOVE_1140,{3U,2U,0U}}, +{MOVE_1140,{4U,2U,0U}}, +{MOVE_1140,{5U,2U,0U}}, +{MOVE_1140,{6U,2U,0U}}, +{MOVE_1140,{7U,2U,0U}}, +{MOVE_1148,{0U,2U,0U}}, +{MOVE_1148,{1U,2U,0U}}, +{MOVE_1148,{2U,2U,0U}}, +{MOVE_1148,{3U,2U,0U}}, +{MOVE_1148,{4U,2U,0U}}, +{MOVE_1148,{5U,2U,0U}}, +{MOVE_1148,{6U,2U,0U}}, +{MOVE_1148,{7U,2U,0U}}, +{MOVE_1150,{0U,2U,0U}}, +{MOVE_1150,{1U,2U,0U}}, +{MOVE_1150,{2U,2U,0U}}, +{MOVE_1150,{3U,2U,0U}}, +{MOVE_1150,{4U,2U,0U}}, +{MOVE_1150,{5U,2U,0U}}, +{MOVE_1150,{6U,2U,0U}}, +{MOVE_1150,{7U,2U,0U}}, +{MOVE_1158,{0U,2U,0U}}, +{MOVE_1158,{1U,2U,0U}}, +{MOVE_1158,{2U,2U,0U}}, +{MOVE_1158,{3U,2U,0U}}, +{MOVE_1158,{4U,2U,0U}}, +{MOVE_1158,{5U,2U,0U}}, +{MOVE_1158,{6U,2U,0U}}, +{MOVE_1158,{7U,2U,0U}}, +{MOVE_1160,{0U,2U,0U}}, +{MOVE_1160,{1U,2U,0U}}, +{MOVE_1160,{2U,2U,0U}}, +{MOVE_1160,{3U,2U,0U}}, +{MOVE_1160,{4U,2U,0U}}, +{MOVE_1160,{5U,2U,0U}}, +{MOVE_1160,{6U,2U,0U}}, +{MOVE_1160,{7U,2U,0U}}, +{MOVE_1168,{0U,2U,0U}}, +{MOVE_1168,{1U,2U,0U}}, +{MOVE_1168,{2U,2U,0U}}, +{MOVE_1168,{3U,2U,0U}}, +{MOVE_1168,{4U,2U,0U}}, +{MOVE_1168,{5U,2U,0U}}, +{MOVE_1168,{6U,2U,0U}}, +{MOVE_1168,{7U,2U,0U}}, +{MOVE_1170,{0U,2U,0U}}, +{MOVE_1170,{1U,2U,0U}}, +{MOVE_1170,{2U,2U,0U}}, +{MOVE_1170,{3U,2U,0U}}, +{MOVE_1170,{4U,2U,0U}}, +{MOVE_1170,{5U,2U,0U}}, +{MOVE_1170,{6U,2U,0U}}, +{MOVE_1170,{7U,2U,0U}}, +{MOVE_1178,{0U,2U,0U}}, +{MOVE_1179,{0U,2U,0U}}, +{MOVE_117A,{0U,2U,0U}}, +{MOVE_117B,{0U,2U,0U}}, +{MOVE_117C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1180,{0U,2U,0U}}, +{MOVE_1180,{1U,2U,0U}}, +{MOVE_1180,{2U,2U,0U}}, +{MOVE_1180,{3U,2U,0U}}, +{MOVE_1180,{4U,2U,0U}}, +{MOVE_1180,{5U,2U,0U}}, +{MOVE_1180,{6U,2U,0U}}, +{MOVE_1180,{7U,2U,0U}}, +{MOVE_1188,{0U,2U,0U}}, +{MOVE_1188,{1U,2U,0U}}, +{MOVE_1188,{2U,2U,0U}}, +{MOVE_1188,{3U,2U,0U}}, +{MOVE_1188,{4U,2U,0U}}, +{MOVE_1188,{5U,2U,0U}}, +{MOVE_1188,{6U,2U,0U}}, +{MOVE_1188,{7U,2U,0U}}, +{MOVE_1190,{0U,2U,0U}}, +{MOVE_1190,{1U,2U,0U}}, +{MOVE_1190,{2U,2U,0U}}, +{MOVE_1190,{3U,2U,0U}}, +{MOVE_1190,{4U,2U,0U}}, +{MOVE_1190,{5U,2U,0U}}, +{MOVE_1190,{6U,2U,0U}}, +{MOVE_1190,{7U,2U,0U}}, +{MOVE_1198,{0U,2U,0U}}, +{MOVE_1198,{1U,2U,0U}}, +{MOVE_1198,{2U,2U,0U}}, +{MOVE_1198,{3U,2U,0U}}, +{MOVE_1198,{4U,2U,0U}}, +{MOVE_1198,{5U,2U,0U}}, +{MOVE_1198,{6U,2U,0U}}, +{MOVE_1198,{7U,2U,0U}}, +{MOVE_11A0,{0U,2U,0U}}, +{MOVE_11A0,{1U,2U,0U}}, +{MOVE_11A0,{2U,2U,0U}}, +{MOVE_11A0,{3U,2U,0U}}, +{MOVE_11A0,{4U,2U,0U}}, +{MOVE_11A0,{5U,2U,0U}}, +{MOVE_11A0,{6U,2U,0U}}, +{MOVE_11A0,{7U,2U,0U}}, +{MOVE_11A8,{0U,2U,0U}}, +{MOVE_11A8,{1U,2U,0U}}, +{MOVE_11A8,{2U,2U,0U}}, +{MOVE_11A8,{3U,2U,0U}}, +{MOVE_11A8,{4U,2U,0U}}, +{MOVE_11A8,{5U,2U,0U}}, +{MOVE_11A8,{6U,2U,0U}}, +{MOVE_11A8,{7U,2U,0U}}, +{MOVE_11B0,{0U,2U,0U}}, +{MOVE_11B0,{1U,2U,0U}}, +{MOVE_11B0,{2U,2U,0U}}, +{MOVE_11B0,{3U,2U,0U}}, +{MOVE_11B0,{4U,2U,0U}}, +{MOVE_11B0,{5U,2U,0U}}, +{MOVE_11B0,{6U,2U,0U}}, +{MOVE_11B0,{7U,2U,0U}}, +{MOVE_11B8,{0U,2U,0U}}, +{MOVE_11B9,{0U,2U,0U}}, +{MOVE_11BA,{0U,2U,0U}}, +{MOVE_11BB,{0U,2U,0U}}, +{MOVE_11BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1000,{0U,3U,0U}}, +{MOVE_1000,{1U,3U,0U}}, +{MOVE_1000,{2U,3U,0U}}, +{MOVE_1000,{3U,3U,0U}}, +{MOVE_1000,{4U,3U,0U}}, +{MOVE_1000,{5U,3U,0U}}, +{MOVE_1000,{6U,3U,0U}}, +{MOVE_1000,{7U,3U,0U}}, +{MOVE_1008,{0U,3U,0U}}, +{MOVE_1008,{1U,3U,0U}}, +{MOVE_1008,{2U,3U,0U}}, +{MOVE_1008,{3U,3U,0U}}, +{MOVE_1008,{4U,3U,0U}}, +{MOVE_1008,{5U,3U,0U}}, +{MOVE_1008,{6U,3U,0U}}, +{MOVE_1008,{7U,3U,0U}}, +{MOVE_1010,{0U,3U,0U}}, +{MOVE_1010,{1U,3U,0U}}, +{MOVE_1010,{2U,3U,0U}}, +{MOVE_1010,{3U,3U,0U}}, +{MOVE_1010,{4U,3U,0U}}, +{MOVE_1010,{5U,3U,0U}}, +{MOVE_1010,{6U,3U,0U}}, +{MOVE_1010,{7U,3U,0U}}, +{MOVE_1018,{0U,3U,0U}}, +{MOVE_1018,{1U,3U,0U}}, +{MOVE_1018,{2U,3U,0U}}, +{MOVE_1018,{3U,3U,0U}}, +{MOVE_1018,{4U,3U,0U}}, +{MOVE_1018,{5U,3U,0U}}, +{MOVE_1018,{6U,3U,0U}}, +{MOVE_1018,{7U,3U,0U}}, +{MOVE_1020,{0U,3U,0U}}, +{MOVE_1020,{1U,3U,0U}}, +{MOVE_1020,{2U,3U,0U}}, +{MOVE_1020,{3U,3U,0U}}, +{MOVE_1020,{4U,3U,0U}}, +{MOVE_1020,{5U,3U,0U}}, +{MOVE_1020,{6U,3U,0U}}, +{MOVE_1020,{7U,3U,0U}}, +{MOVE_1028,{0U,3U,0U}}, +{MOVE_1028,{1U,3U,0U}}, +{MOVE_1028,{2U,3U,0U}}, +{MOVE_1028,{3U,3U,0U}}, +{MOVE_1028,{4U,3U,0U}}, +{MOVE_1028,{5U,3U,0U}}, +{MOVE_1028,{6U,3U,0U}}, +{MOVE_1028,{7U,3U,0U}}, +{MOVE_1030,{0U,3U,0U}}, +{MOVE_1030,{1U,3U,0U}}, +{MOVE_1030,{2U,3U,0U}}, +{MOVE_1030,{3U,3U,0U}}, +{MOVE_1030,{4U,3U,0U}}, +{MOVE_1030,{5U,3U,0U}}, +{MOVE_1030,{6U,3U,0U}}, +{MOVE_1030,{7U,3U,0U}}, +{MOVE_1038,{0U,3U,0U}}, +{MOVE_1039,{0U,3U,0U}}, +{MOVE_103A,{0U,3U,0U}}, +{MOVE_103B,{0U,3U,0U}}, +{MOVE_103C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1080,{0U,3U,0U}}, +{MOVE_1080,{1U,3U,0U}}, +{MOVE_1080,{2U,3U,0U}}, +{MOVE_1080,{3U,3U,0U}}, +{MOVE_1080,{4U,3U,0U}}, +{MOVE_1080,{5U,3U,0U}}, +{MOVE_1080,{6U,3U,0U}}, +{MOVE_1080,{7U,3U,0U}}, +{MOVE_1088,{0U,3U,0U}}, +{MOVE_1088,{1U,3U,0U}}, +{MOVE_1088,{2U,3U,0U}}, +{MOVE_1088,{3U,3U,0U}}, +{MOVE_1088,{4U,3U,0U}}, +{MOVE_1088,{5U,3U,0U}}, +{MOVE_1088,{6U,3U,0U}}, +{MOVE_1088,{7U,3U,0U}}, +{MOVE_1090,{0U,3U,0U}}, +{MOVE_1090,{1U,3U,0U}}, +{MOVE_1090,{2U,3U,0U}}, +{MOVE_1090,{3U,3U,0U}}, +{MOVE_1090,{4U,3U,0U}}, +{MOVE_1090,{5U,3U,0U}}, +{MOVE_1090,{6U,3U,0U}}, +{MOVE_1090,{7U,3U,0U}}, +{MOVE_1098,{0U,3U,0U}}, +{MOVE_1098,{1U,3U,0U}}, +{MOVE_1098,{2U,3U,0U}}, +{MOVE_1098,{3U,3U,0U}}, +{MOVE_1098,{4U,3U,0U}}, +{MOVE_1098,{5U,3U,0U}}, +{MOVE_1098,{6U,3U,0U}}, +{MOVE_1098,{7U,3U,0U}}, +{MOVE_10A0,{0U,3U,0U}}, +{MOVE_10A0,{1U,3U,0U}}, +{MOVE_10A0,{2U,3U,0U}}, +{MOVE_10A0,{3U,3U,0U}}, +{MOVE_10A0,{4U,3U,0U}}, +{MOVE_10A0,{5U,3U,0U}}, +{MOVE_10A0,{6U,3U,0U}}, +{MOVE_10A0,{7U,3U,0U}}, +{MOVE_10A8,{0U,3U,0U}}, +{MOVE_10A8,{1U,3U,0U}}, +{MOVE_10A8,{2U,3U,0U}}, +{MOVE_10A8,{3U,3U,0U}}, +{MOVE_10A8,{4U,3U,0U}}, +{MOVE_10A8,{5U,3U,0U}}, +{MOVE_10A8,{6U,3U,0U}}, +{MOVE_10A8,{7U,3U,0U}}, +{MOVE_10B0,{0U,3U,0U}}, +{MOVE_10B0,{1U,3U,0U}}, +{MOVE_10B0,{2U,3U,0U}}, +{MOVE_10B0,{3U,3U,0U}}, +{MOVE_10B0,{4U,3U,0U}}, +{MOVE_10B0,{5U,3U,0U}}, +{MOVE_10B0,{6U,3U,0U}}, +{MOVE_10B0,{7U,3U,0U}}, +{MOVE_10B8,{0U,3U,0U}}, +{MOVE_10B9,{0U,3U,0U}}, +{MOVE_10BA,{0U,3U,0U}}, +{MOVE_10BB,{0U,3U,0U}}, +{MOVE_10BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_10C0,{0U,3U,0U}}, +{MOVE_10C0,{1U,3U,0U}}, +{MOVE_10C0,{2U,3U,0U}}, +{MOVE_10C0,{3U,3U,0U}}, +{MOVE_10C0,{4U,3U,0U}}, +{MOVE_10C0,{5U,3U,0U}}, +{MOVE_10C0,{6U,3U,0U}}, +{MOVE_10C0,{7U,3U,0U}}, +{MOVE_10C8,{0U,3U,0U}}, +{MOVE_10C8,{1U,3U,0U}}, +{MOVE_10C8,{2U,3U,0U}}, +{MOVE_10C8,{3U,3U,0U}}, +{MOVE_10C8,{4U,3U,0U}}, +{MOVE_10C8,{5U,3U,0U}}, +{MOVE_10C8,{6U,3U,0U}}, +{MOVE_10C8,{7U,3U,0U}}, +{MOVE_10D0,{0U,3U,0U}}, +{MOVE_10D0,{1U,3U,0U}}, +{MOVE_10D0,{2U,3U,0U}}, +{MOVE_10D0,{3U,3U,0U}}, +{MOVE_10D0,{4U,3U,0U}}, +{MOVE_10D0,{5U,3U,0U}}, +{MOVE_10D0,{6U,3U,0U}}, +{MOVE_10D0,{7U,3U,0U}}, +{MOVE_10D8,{0U,3U,0U}}, +{MOVE_10D8,{1U,3U,0U}}, +{MOVE_10D8,{2U,3U,0U}}, +{MOVE_10D8,{3U,3U,0U}}, +{MOVE_10D8,{4U,3U,0U}}, +{MOVE_10D8,{5U,3U,0U}}, +{MOVE_10D8,{6U,3U,0U}}, +{MOVE_10D8,{7U,3U,0U}}, +{MOVE_10E0,{0U,3U,0U}}, +{MOVE_10E0,{1U,3U,0U}}, +{MOVE_10E0,{2U,3U,0U}}, +{MOVE_10E0,{3U,3U,0U}}, +{MOVE_10E0,{4U,3U,0U}}, +{MOVE_10E0,{5U,3U,0U}}, +{MOVE_10E0,{6U,3U,0U}}, +{MOVE_10E0,{7U,3U,0U}}, +{MOVE_10E8,{0U,3U,0U}}, +{MOVE_10E8,{1U,3U,0U}}, +{MOVE_10E8,{2U,3U,0U}}, +{MOVE_10E8,{3U,3U,0U}}, +{MOVE_10E8,{4U,3U,0U}}, +{MOVE_10E8,{5U,3U,0U}}, +{MOVE_10E8,{6U,3U,0U}}, +{MOVE_10E8,{7U,3U,0U}}, +{MOVE_10F0,{0U,3U,0U}}, +{MOVE_10F0,{1U,3U,0U}}, +{MOVE_10F0,{2U,3U,0U}}, +{MOVE_10F0,{3U,3U,0U}}, +{MOVE_10F0,{4U,3U,0U}}, +{MOVE_10F0,{5U,3U,0U}}, +{MOVE_10F0,{6U,3U,0U}}, +{MOVE_10F0,{7U,3U,0U}}, +{MOVE_10F8,{0U,3U,0U}}, +{MOVE_10F9,{0U,3U,0U}}, +{MOVE_10FA,{0U,3U,0U}}, +{MOVE_10FB,{0U,3U,0U}}, +{MOVE_10FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1100,{0U,3U,0U}}, +{MOVE_1100,{1U,3U,0U}}, +{MOVE_1100,{2U,3U,0U}}, +{MOVE_1100,{3U,3U,0U}}, +{MOVE_1100,{4U,3U,0U}}, +{MOVE_1100,{5U,3U,0U}}, +{MOVE_1100,{6U,3U,0U}}, +{MOVE_1100,{7U,3U,0U}}, +{MOVE_1108,{0U,3U,0U}}, +{MOVE_1108,{1U,3U,0U}}, +{MOVE_1108,{2U,3U,0U}}, +{MOVE_1108,{3U,3U,0U}}, +{MOVE_1108,{4U,3U,0U}}, +{MOVE_1108,{5U,3U,0U}}, +{MOVE_1108,{6U,3U,0U}}, +{MOVE_1108,{7U,3U,0U}}, +{MOVE_1110,{0U,3U,0U}}, +{MOVE_1110,{1U,3U,0U}}, +{MOVE_1110,{2U,3U,0U}}, +{MOVE_1110,{3U,3U,0U}}, +{MOVE_1110,{4U,3U,0U}}, +{MOVE_1110,{5U,3U,0U}}, +{MOVE_1110,{6U,3U,0U}}, +{MOVE_1110,{7U,3U,0U}}, +{MOVE_1118,{0U,3U,0U}}, +{MOVE_1118,{1U,3U,0U}}, +{MOVE_1118,{2U,3U,0U}}, +{MOVE_1118,{3U,3U,0U}}, +{MOVE_1118,{4U,3U,0U}}, +{MOVE_1118,{5U,3U,0U}}, +{MOVE_1118,{6U,3U,0U}}, +{MOVE_1118,{7U,3U,0U}}, +{MOVE_1120,{0U,3U,0U}}, +{MOVE_1120,{1U,3U,0U}}, +{MOVE_1120,{2U,3U,0U}}, +{MOVE_1120,{3U,3U,0U}}, +{MOVE_1120,{4U,3U,0U}}, +{MOVE_1120,{5U,3U,0U}}, +{MOVE_1120,{6U,3U,0U}}, +{MOVE_1120,{7U,3U,0U}}, +{MOVE_1128,{0U,3U,0U}}, +{MOVE_1128,{1U,3U,0U}}, +{MOVE_1128,{2U,3U,0U}}, +{MOVE_1128,{3U,3U,0U}}, +{MOVE_1128,{4U,3U,0U}}, +{MOVE_1128,{5U,3U,0U}}, +{MOVE_1128,{6U,3U,0U}}, +{MOVE_1128,{7U,3U,0U}}, +{MOVE_1130,{0U,3U,0U}}, +{MOVE_1130,{1U,3U,0U}}, +{MOVE_1130,{2U,3U,0U}}, +{MOVE_1130,{3U,3U,0U}}, +{MOVE_1130,{4U,3U,0U}}, +{MOVE_1130,{5U,3U,0U}}, +{MOVE_1130,{6U,3U,0U}}, +{MOVE_1130,{7U,3U,0U}}, +{MOVE_1138,{0U,3U,0U}}, +{MOVE_1139,{0U,3U,0U}}, +{MOVE_113A,{0U,3U,0U}}, +{MOVE_113B,{0U,3U,0U}}, +{MOVE_113C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1140,{0U,3U,0U}}, +{MOVE_1140,{1U,3U,0U}}, +{MOVE_1140,{2U,3U,0U}}, +{MOVE_1140,{3U,3U,0U}}, +{MOVE_1140,{4U,3U,0U}}, +{MOVE_1140,{5U,3U,0U}}, +{MOVE_1140,{6U,3U,0U}}, +{MOVE_1140,{7U,3U,0U}}, +{MOVE_1148,{0U,3U,0U}}, +{MOVE_1148,{1U,3U,0U}}, +{MOVE_1148,{2U,3U,0U}}, +{MOVE_1148,{3U,3U,0U}}, +{MOVE_1148,{4U,3U,0U}}, +{MOVE_1148,{5U,3U,0U}}, +{MOVE_1148,{6U,3U,0U}}, +{MOVE_1148,{7U,3U,0U}}, +{MOVE_1150,{0U,3U,0U}}, +{MOVE_1150,{1U,3U,0U}}, +{MOVE_1150,{2U,3U,0U}}, +{MOVE_1150,{3U,3U,0U}}, +{MOVE_1150,{4U,3U,0U}}, +{MOVE_1150,{5U,3U,0U}}, +{MOVE_1150,{6U,3U,0U}}, +{MOVE_1150,{7U,3U,0U}}, +{MOVE_1158,{0U,3U,0U}}, +{MOVE_1158,{1U,3U,0U}}, +{MOVE_1158,{2U,3U,0U}}, +{MOVE_1158,{3U,3U,0U}}, +{MOVE_1158,{4U,3U,0U}}, +{MOVE_1158,{5U,3U,0U}}, +{MOVE_1158,{6U,3U,0U}}, +{MOVE_1158,{7U,3U,0U}}, +{MOVE_1160,{0U,3U,0U}}, +{MOVE_1160,{1U,3U,0U}}, +{MOVE_1160,{2U,3U,0U}}, +{MOVE_1160,{3U,3U,0U}}, +{MOVE_1160,{4U,3U,0U}}, +{MOVE_1160,{5U,3U,0U}}, +{MOVE_1160,{6U,3U,0U}}, +{MOVE_1160,{7U,3U,0U}}, +{MOVE_1168,{0U,3U,0U}}, +{MOVE_1168,{1U,3U,0U}}, +{MOVE_1168,{2U,3U,0U}}, +{MOVE_1168,{3U,3U,0U}}, +{MOVE_1168,{4U,3U,0U}}, +{MOVE_1168,{5U,3U,0U}}, +{MOVE_1168,{6U,3U,0U}}, +{MOVE_1168,{7U,3U,0U}}, +{MOVE_1170,{0U,3U,0U}}, +{MOVE_1170,{1U,3U,0U}}, +{MOVE_1170,{2U,3U,0U}}, +{MOVE_1170,{3U,3U,0U}}, +{MOVE_1170,{4U,3U,0U}}, +{MOVE_1170,{5U,3U,0U}}, +{MOVE_1170,{6U,3U,0U}}, +{MOVE_1170,{7U,3U,0U}}, +{MOVE_1178,{0U,3U,0U}}, +{MOVE_1179,{0U,3U,0U}}, +{MOVE_117A,{0U,3U,0U}}, +{MOVE_117B,{0U,3U,0U}}, +{MOVE_117C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1180,{0U,3U,0U}}, +{MOVE_1180,{1U,3U,0U}}, +{MOVE_1180,{2U,3U,0U}}, +{MOVE_1180,{3U,3U,0U}}, +{MOVE_1180,{4U,3U,0U}}, +{MOVE_1180,{5U,3U,0U}}, +{MOVE_1180,{6U,3U,0U}}, +{MOVE_1180,{7U,3U,0U}}, +{MOVE_1188,{0U,3U,0U}}, +{MOVE_1188,{1U,3U,0U}}, +{MOVE_1188,{2U,3U,0U}}, +{MOVE_1188,{3U,3U,0U}}, +{MOVE_1188,{4U,3U,0U}}, +{MOVE_1188,{5U,3U,0U}}, +{MOVE_1188,{6U,3U,0U}}, +{MOVE_1188,{7U,3U,0U}}, +{MOVE_1190,{0U,3U,0U}}, +{MOVE_1190,{1U,3U,0U}}, +{MOVE_1190,{2U,3U,0U}}, +{MOVE_1190,{3U,3U,0U}}, +{MOVE_1190,{4U,3U,0U}}, +{MOVE_1190,{5U,3U,0U}}, +{MOVE_1190,{6U,3U,0U}}, +{MOVE_1190,{7U,3U,0U}}, +{MOVE_1198,{0U,3U,0U}}, +{MOVE_1198,{1U,3U,0U}}, +{MOVE_1198,{2U,3U,0U}}, +{MOVE_1198,{3U,3U,0U}}, +{MOVE_1198,{4U,3U,0U}}, +{MOVE_1198,{5U,3U,0U}}, +{MOVE_1198,{6U,3U,0U}}, +{MOVE_1198,{7U,3U,0U}}, +{MOVE_11A0,{0U,3U,0U}}, +{MOVE_11A0,{1U,3U,0U}}, +{MOVE_11A0,{2U,3U,0U}}, +{MOVE_11A0,{3U,3U,0U}}, +{MOVE_11A0,{4U,3U,0U}}, +{MOVE_11A0,{5U,3U,0U}}, +{MOVE_11A0,{6U,3U,0U}}, +{MOVE_11A0,{7U,3U,0U}}, +{MOVE_11A8,{0U,3U,0U}}, +{MOVE_11A8,{1U,3U,0U}}, +{MOVE_11A8,{2U,3U,0U}}, +{MOVE_11A8,{3U,3U,0U}}, +{MOVE_11A8,{4U,3U,0U}}, +{MOVE_11A8,{5U,3U,0U}}, +{MOVE_11A8,{6U,3U,0U}}, +{MOVE_11A8,{7U,3U,0U}}, +{MOVE_11B0,{0U,3U,0U}}, +{MOVE_11B0,{1U,3U,0U}}, +{MOVE_11B0,{2U,3U,0U}}, +{MOVE_11B0,{3U,3U,0U}}, +{MOVE_11B0,{4U,3U,0U}}, +{MOVE_11B0,{5U,3U,0U}}, +{MOVE_11B0,{6U,3U,0U}}, +{MOVE_11B0,{7U,3U,0U}}, +{MOVE_11B8,{0U,3U,0U}}, +{MOVE_11B9,{0U,3U,0U}}, +{MOVE_11BA,{0U,3U,0U}}, +{MOVE_11BB,{0U,3U,0U}}, +{MOVE_11BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1000,{0U,4U,0U}}, +{MOVE_1000,{1U,4U,0U}}, +{MOVE_1000,{2U,4U,0U}}, +{MOVE_1000,{3U,4U,0U}}, +{MOVE_1000,{4U,4U,0U}}, +{MOVE_1000,{5U,4U,0U}}, +{MOVE_1000,{6U,4U,0U}}, +{MOVE_1000,{7U,4U,0U}}, +{MOVE_1008,{0U,4U,0U}}, +{MOVE_1008,{1U,4U,0U}}, +{MOVE_1008,{2U,4U,0U}}, +{MOVE_1008,{3U,4U,0U}}, +{MOVE_1008,{4U,4U,0U}}, +{MOVE_1008,{5U,4U,0U}}, +{MOVE_1008,{6U,4U,0U}}, +{MOVE_1008,{7U,4U,0U}}, +{MOVE_1010,{0U,4U,0U}}, +{MOVE_1010,{1U,4U,0U}}, +{MOVE_1010,{2U,4U,0U}}, +{MOVE_1010,{3U,4U,0U}}, +{MOVE_1010,{4U,4U,0U}}, +{MOVE_1010,{5U,4U,0U}}, +{MOVE_1010,{6U,4U,0U}}, +{MOVE_1010,{7U,4U,0U}}, +{MOVE_1018,{0U,4U,0U}}, +{MOVE_1018,{1U,4U,0U}}, +{MOVE_1018,{2U,4U,0U}}, +{MOVE_1018,{3U,4U,0U}}, +{MOVE_1018,{4U,4U,0U}}, +{MOVE_1018,{5U,4U,0U}}, +{MOVE_1018,{6U,4U,0U}}, +{MOVE_1018,{7U,4U,0U}}, +{MOVE_1020,{0U,4U,0U}}, +{MOVE_1020,{1U,4U,0U}}, +{MOVE_1020,{2U,4U,0U}}, +{MOVE_1020,{3U,4U,0U}}, +{MOVE_1020,{4U,4U,0U}}, +{MOVE_1020,{5U,4U,0U}}, +{MOVE_1020,{6U,4U,0U}}, +{MOVE_1020,{7U,4U,0U}}, +{MOVE_1028,{0U,4U,0U}}, +{MOVE_1028,{1U,4U,0U}}, +{MOVE_1028,{2U,4U,0U}}, +{MOVE_1028,{3U,4U,0U}}, +{MOVE_1028,{4U,4U,0U}}, +{MOVE_1028,{5U,4U,0U}}, +{MOVE_1028,{6U,4U,0U}}, +{MOVE_1028,{7U,4U,0U}}, +{MOVE_1030,{0U,4U,0U}}, +{MOVE_1030,{1U,4U,0U}}, +{MOVE_1030,{2U,4U,0U}}, +{MOVE_1030,{3U,4U,0U}}, +{MOVE_1030,{4U,4U,0U}}, +{MOVE_1030,{5U,4U,0U}}, +{MOVE_1030,{6U,4U,0U}}, +{MOVE_1030,{7U,4U,0U}}, +{MOVE_1038,{0U,4U,0U}}, +{MOVE_1039,{0U,4U,0U}}, +{MOVE_103A,{0U,4U,0U}}, +{MOVE_103B,{0U,4U,0U}}, +{MOVE_103C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1080,{0U,4U,0U}}, +{MOVE_1080,{1U,4U,0U}}, +{MOVE_1080,{2U,4U,0U}}, +{MOVE_1080,{3U,4U,0U}}, +{MOVE_1080,{4U,4U,0U}}, +{MOVE_1080,{5U,4U,0U}}, +{MOVE_1080,{6U,4U,0U}}, +{MOVE_1080,{7U,4U,0U}}, +{MOVE_1088,{0U,4U,0U}}, +{MOVE_1088,{1U,4U,0U}}, +{MOVE_1088,{2U,4U,0U}}, +{MOVE_1088,{3U,4U,0U}}, +{MOVE_1088,{4U,4U,0U}}, +{MOVE_1088,{5U,4U,0U}}, +{MOVE_1088,{6U,4U,0U}}, +{MOVE_1088,{7U,4U,0U}}, +{MOVE_1090,{0U,4U,0U}}, +{MOVE_1090,{1U,4U,0U}}, +{MOVE_1090,{2U,4U,0U}}, +{MOVE_1090,{3U,4U,0U}}, +{MOVE_1090,{4U,4U,0U}}, +{MOVE_1090,{5U,4U,0U}}, +{MOVE_1090,{6U,4U,0U}}, +{MOVE_1090,{7U,4U,0U}}, +{MOVE_1098,{0U,4U,0U}}, +{MOVE_1098,{1U,4U,0U}}, +{MOVE_1098,{2U,4U,0U}}, +{MOVE_1098,{3U,4U,0U}}, +{MOVE_1098,{4U,4U,0U}}, +{MOVE_1098,{5U,4U,0U}}, +{MOVE_1098,{6U,4U,0U}}, +{MOVE_1098,{7U,4U,0U}}, +{MOVE_10A0,{0U,4U,0U}}, +{MOVE_10A0,{1U,4U,0U}}, +{MOVE_10A0,{2U,4U,0U}}, +{MOVE_10A0,{3U,4U,0U}}, +{MOVE_10A0,{4U,4U,0U}}, +{MOVE_10A0,{5U,4U,0U}}, +{MOVE_10A0,{6U,4U,0U}}, +{MOVE_10A0,{7U,4U,0U}}, +{MOVE_10A8,{0U,4U,0U}}, +{MOVE_10A8,{1U,4U,0U}}, +{MOVE_10A8,{2U,4U,0U}}, +{MOVE_10A8,{3U,4U,0U}}, +{MOVE_10A8,{4U,4U,0U}}, +{MOVE_10A8,{5U,4U,0U}}, +{MOVE_10A8,{6U,4U,0U}}, +{MOVE_10A8,{7U,4U,0U}}, +{MOVE_10B0,{0U,4U,0U}}, +{MOVE_10B0,{1U,4U,0U}}, +{MOVE_10B0,{2U,4U,0U}}, +{MOVE_10B0,{3U,4U,0U}}, +{MOVE_10B0,{4U,4U,0U}}, +{MOVE_10B0,{5U,4U,0U}}, +{MOVE_10B0,{6U,4U,0U}}, +{MOVE_10B0,{7U,4U,0U}}, +{MOVE_10B8,{0U,4U,0U}}, +{MOVE_10B9,{0U,4U,0U}}, +{MOVE_10BA,{0U,4U,0U}}, +{MOVE_10BB,{0U,4U,0U}}, +{MOVE_10BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_10C0,{0U,4U,0U}}, +{MOVE_10C0,{1U,4U,0U}}, +{MOVE_10C0,{2U,4U,0U}}, +{MOVE_10C0,{3U,4U,0U}}, +{MOVE_10C0,{4U,4U,0U}}, +{MOVE_10C0,{5U,4U,0U}}, +{MOVE_10C0,{6U,4U,0U}}, +{MOVE_10C0,{7U,4U,0U}}, +{MOVE_10C8,{0U,4U,0U}}, +{MOVE_10C8,{1U,4U,0U}}, +{MOVE_10C8,{2U,4U,0U}}, +{MOVE_10C8,{3U,4U,0U}}, +{MOVE_10C8,{4U,4U,0U}}, +{MOVE_10C8,{5U,4U,0U}}, +{MOVE_10C8,{6U,4U,0U}}, +{MOVE_10C8,{7U,4U,0U}}, +{MOVE_10D0,{0U,4U,0U}}, +{MOVE_10D0,{1U,4U,0U}}, +{MOVE_10D0,{2U,4U,0U}}, +{MOVE_10D0,{3U,4U,0U}}, +{MOVE_10D0,{4U,4U,0U}}, +{MOVE_10D0,{5U,4U,0U}}, +{MOVE_10D0,{6U,4U,0U}}, +{MOVE_10D0,{7U,4U,0U}}, +{MOVE_10D8,{0U,4U,0U}}, +{MOVE_10D8,{1U,4U,0U}}, +{MOVE_10D8,{2U,4U,0U}}, +{MOVE_10D8,{3U,4U,0U}}, +{MOVE_10D8,{4U,4U,0U}}, +{MOVE_10D8,{5U,4U,0U}}, +{MOVE_10D8,{6U,4U,0U}}, +{MOVE_10D8,{7U,4U,0U}}, +{MOVE_10E0,{0U,4U,0U}}, +{MOVE_10E0,{1U,4U,0U}}, +{MOVE_10E0,{2U,4U,0U}}, +{MOVE_10E0,{3U,4U,0U}}, +{MOVE_10E0,{4U,4U,0U}}, +{MOVE_10E0,{5U,4U,0U}}, +{MOVE_10E0,{6U,4U,0U}}, +{MOVE_10E0,{7U,4U,0U}}, +{MOVE_10E8,{0U,4U,0U}}, +{MOVE_10E8,{1U,4U,0U}}, +{MOVE_10E8,{2U,4U,0U}}, +{MOVE_10E8,{3U,4U,0U}}, +{MOVE_10E8,{4U,4U,0U}}, +{MOVE_10E8,{5U,4U,0U}}, +{MOVE_10E8,{6U,4U,0U}}, +{MOVE_10E8,{7U,4U,0U}}, +{MOVE_10F0,{0U,4U,0U}}, +{MOVE_10F0,{1U,4U,0U}}, +{MOVE_10F0,{2U,4U,0U}}, +{MOVE_10F0,{3U,4U,0U}}, +{MOVE_10F0,{4U,4U,0U}}, +{MOVE_10F0,{5U,4U,0U}}, +{MOVE_10F0,{6U,4U,0U}}, +{MOVE_10F0,{7U,4U,0U}}, +{MOVE_10F8,{0U,4U,0U}}, +{MOVE_10F9,{0U,4U,0U}}, +{MOVE_10FA,{0U,4U,0U}}, +{MOVE_10FB,{0U,4U,0U}}, +{MOVE_10FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1100,{0U,4U,0U}}, +{MOVE_1100,{1U,4U,0U}}, +{MOVE_1100,{2U,4U,0U}}, +{MOVE_1100,{3U,4U,0U}}, +{MOVE_1100,{4U,4U,0U}}, +{MOVE_1100,{5U,4U,0U}}, +{MOVE_1100,{6U,4U,0U}}, +{MOVE_1100,{7U,4U,0U}}, +{MOVE_1108,{0U,4U,0U}}, +{MOVE_1108,{1U,4U,0U}}, +{MOVE_1108,{2U,4U,0U}}, +{MOVE_1108,{3U,4U,0U}}, +{MOVE_1108,{4U,4U,0U}}, +{MOVE_1108,{5U,4U,0U}}, +{MOVE_1108,{6U,4U,0U}}, +{MOVE_1108,{7U,4U,0U}}, +{MOVE_1110,{0U,4U,0U}}, +{MOVE_1110,{1U,4U,0U}}, +{MOVE_1110,{2U,4U,0U}}, +{MOVE_1110,{3U,4U,0U}}, +{MOVE_1110,{4U,4U,0U}}, +{MOVE_1110,{5U,4U,0U}}, +{MOVE_1110,{6U,4U,0U}}, +{MOVE_1110,{7U,4U,0U}}, +{MOVE_1118,{0U,4U,0U}}, +{MOVE_1118,{1U,4U,0U}}, +{MOVE_1118,{2U,4U,0U}}, +{MOVE_1118,{3U,4U,0U}}, +{MOVE_1118,{4U,4U,0U}}, +{MOVE_1118,{5U,4U,0U}}, +{MOVE_1118,{6U,4U,0U}}, +{MOVE_1118,{7U,4U,0U}}, +{MOVE_1120,{0U,4U,0U}}, +{MOVE_1120,{1U,4U,0U}}, +{MOVE_1120,{2U,4U,0U}}, +{MOVE_1120,{3U,4U,0U}}, +{MOVE_1120,{4U,4U,0U}}, +{MOVE_1120,{5U,4U,0U}}, +{MOVE_1120,{6U,4U,0U}}, +{MOVE_1120,{7U,4U,0U}}, +{MOVE_1128,{0U,4U,0U}}, +{MOVE_1128,{1U,4U,0U}}, +{MOVE_1128,{2U,4U,0U}}, +{MOVE_1128,{3U,4U,0U}}, +{MOVE_1128,{4U,4U,0U}}, +{MOVE_1128,{5U,4U,0U}}, +{MOVE_1128,{6U,4U,0U}}, +{MOVE_1128,{7U,4U,0U}}, +{MOVE_1130,{0U,4U,0U}}, +{MOVE_1130,{1U,4U,0U}}, +{MOVE_1130,{2U,4U,0U}}, +{MOVE_1130,{3U,4U,0U}}, +{MOVE_1130,{4U,4U,0U}}, +{MOVE_1130,{5U,4U,0U}}, +{MOVE_1130,{6U,4U,0U}}, +{MOVE_1130,{7U,4U,0U}}, +{MOVE_1138,{0U,4U,0U}}, +{MOVE_1139,{0U,4U,0U}}, +{MOVE_113A,{0U,4U,0U}}, +{MOVE_113B,{0U,4U,0U}}, +{MOVE_113C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1140,{0U,4U,0U}}, +{MOVE_1140,{1U,4U,0U}}, +{MOVE_1140,{2U,4U,0U}}, +{MOVE_1140,{3U,4U,0U}}, +{MOVE_1140,{4U,4U,0U}}, +{MOVE_1140,{5U,4U,0U}}, +{MOVE_1140,{6U,4U,0U}}, +{MOVE_1140,{7U,4U,0U}}, +{MOVE_1148,{0U,4U,0U}}, +{MOVE_1148,{1U,4U,0U}}, +{MOVE_1148,{2U,4U,0U}}, +{MOVE_1148,{3U,4U,0U}}, +{MOVE_1148,{4U,4U,0U}}, +{MOVE_1148,{5U,4U,0U}}, +{MOVE_1148,{6U,4U,0U}}, +{MOVE_1148,{7U,4U,0U}}, +{MOVE_1150,{0U,4U,0U}}, +{MOVE_1150,{1U,4U,0U}}, +{MOVE_1150,{2U,4U,0U}}, +{MOVE_1150,{3U,4U,0U}}, +{MOVE_1150,{4U,4U,0U}}, +{MOVE_1150,{5U,4U,0U}}, +{MOVE_1150,{6U,4U,0U}}, +{MOVE_1150,{7U,4U,0U}}, +{MOVE_1158,{0U,4U,0U}}, +{MOVE_1158,{1U,4U,0U}}, +{MOVE_1158,{2U,4U,0U}}, +{MOVE_1158,{3U,4U,0U}}, +{MOVE_1158,{4U,4U,0U}}, +{MOVE_1158,{5U,4U,0U}}, +{MOVE_1158,{6U,4U,0U}}, +{MOVE_1158,{7U,4U,0U}}, +{MOVE_1160,{0U,4U,0U}}, +{MOVE_1160,{1U,4U,0U}}, +{MOVE_1160,{2U,4U,0U}}, +{MOVE_1160,{3U,4U,0U}}, +{MOVE_1160,{4U,4U,0U}}, +{MOVE_1160,{5U,4U,0U}}, +{MOVE_1160,{6U,4U,0U}}, +{MOVE_1160,{7U,4U,0U}}, +{MOVE_1168,{0U,4U,0U}}, +{MOVE_1168,{1U,4U,0U}}, +{MOVE_1168,{2U,4U,0U}}, +{MOVE_1168,{3U,4U,0U}}, +{MOVE_1168,{4U,4U,0U}}, +{MOVE_1168,{5U,4U,0U}}, +{MOVE_1168,{6U,4U,0U}}, +{MOVE_1168,{7U,4U,0U}}, +{MOVE_1170,{0U,4U,0U}}, +{MOVE_1170,{1U,4U,0U}}, +{MOVE_1170,{2U,4U,0U}}, +{MOVE_1170,{3U,4U,0U}}, +{MOVE_1170,{4U,4U,0U}}, +{MOVE_1170,{5U,4U,0U}}, +{MOVE_1170,{6U,4U,0U}}, +{MOVE_1170,{7U,4U,0U}}, +{MOVE_1178,{0U,4U,0U}}, +{MOVE_1179,{0U,4U,0U}}, +{MOVE_117A,{0U,4U,0U}}, +{MOVE_117B,{0U,4U,0U}}, +{MOVE_117C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1180,{0U,4U,0U}}, +{MOVE_1180,{1U,4U,0U}}, +{MOVE_1180,{2U,4U,0U}}, +{MOVE_1180,{3U,4U,0U}}, +{MOVE_1180,{4U,4U,0U}}, +{MOVE_1180,{5U,4U,0U}}, +{MOVE_1180,{6U,4U,0U}}, +{MOVE_1180,{7U,4U,0U}}, +{MOVE_1188,{0U,4U,0U}}, +{MOVE_1188,{1U,4U,0U}}, +{MOVE_1188,{2U,4U,0U}}, +{MOVE_1188,{3U,4U,0U}}, +{MOVE_1188,{4U,4U,0U}}, +{MOVE_1188,{5U,4U,0U}}, +{MOVE_1188,{6U,4U,0U}}, +{MOVE_1188,{7U,4U,0U}}, +{MOVE_1190,{0U,4U,0U}}, +{MOVE_1190,{1U,4U,0U}}, +{MOVE_1190,{2U,4U,0U}}, +{MOVE_1190,{3U,4U,0U}}, +{MOVE_1190,{4U,4U,0U}}, +{MOVE_1190,{5U,4U,0U}}, +{MOVE_1190,{6U,4U,0U}}, +{MOVE_1190,{7U,4U,0U}}, +{MOVE_1198,{0U,4U,0U}}, +{MOVE_1198,{1U,4U,0U}}, +{MOVE_1198,{2U,4U,0U}}, +{MOVE_1198,{3U,4U,0U}}, +{MOVE_1198,{4U,4U,0U}}, +{MOVE_1198,{5U,4U,0U}}, +{MOVE_1198,{6U,4U,0U}}, +{MOVE_1198,{7U,4U,0U}}, +{MOVE_11A0,{0U,4U,0U}}, +{MOVE_11A0,{1U,4U,0U}}, +{MOVE_11A0,{2U,4U,0U}}, +{MOVE_11A0,{3U,4U,0U}}, +{MOVE_11A0,{4U,4U,0U}}, +{MOVE_11A0,{5U,4U,0U}}, +{MOVE_11A0,{6U,4U,0U}}, +{MOVE_11A0,{7U,4U,0U}}, +{MOVE_11A8,{0U,4U,0U}}, +{MOVE_11A8,{1U,4U,0U}}, +{MOVE_11A8,{2U,4U,0U}}, +{MOVE_11A8,{3U,4U,0U}}, +{MOVE_11A8,{4U,4U,0U}}, +{MOVE_11A8,{5U,4U,0U}}, +{MOVE_11A8,{6U,4U,0U}}, +{MOVE_11A8,{7U,4U,0U}}, +{MOVE_11B0,{0U,4U,0U}}, +{MOVE_11B0,{1U,4U,0U}}, +{MOVE_11B0,{2U,4U,0U}}, +{MOVE_11B0,{3U,4U,0U}}, +{MOVE_11B0,{4U,4U,0U}}, +{MOVE_11B0,{5U,4U,0U}}, +{MOVE_11B0,{6U,4U,0U}}, +{MOVE_11B0,{7U,4U,0U}}, +{MOVE_11B8,{0U,4U,0U}}, +{MOVE_11B9,{0U,4U,0U}}, +{MOVE_11BA,{0U,4U,0U}}, +{MOVE_11BB,{0U,4U,0U}}, +{MOVE_11BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1000,{0U,5U,0U}}, +{MOVE_1000,{1U,5U,0U}}, +{MOVE_1000,{2U,5U,0U}}, +{MOVE_1000,{3U,5U,0U}}, +{MOVE_1000,{4U,5U,0U}}, +{MOVE_1000,{5U,5U,0U}}, +{MOVE_1000,{6U,5U,0U}}, +{MOVE_1000,{7U,5U,0U}}, +{MOVE_1008,{0U,5U,0U}}, +{MOVE_1008,{1U,5U,0U}}, +{MOVE_1008,{2U,5U,0U}}, +{MOVE_1008,{3U,5U,0U}}, +{MOVE_1008,{4U,5U,0U}}, +{MOVE_1008,{5U,5U,0U}}, +{MOVE_1008,{6U,5U,0U}}, +{MOVE_1008,{7U,5U,0U}}, +{MOVE_1010,{0U,5U,0U}}, +{MOVE_1010,{1U,5U,0U}}, +{MOVE_1010,{2U,5U,0U}}, +{MOVE_1010,{3U,5U,0U}}, +{MOVE_1010,{4U,5U,0U}}, +{MOVE_1010,{5U,5U,0U}}, +{MOVE_1010,{6U,5U,0U}}, +{MOVE_1010,{7U,5U,0U}}, +{MOVE_1018,{0U,5U,0U}}, +{MOVE_1018,{1U,5U,0U}}, +{MOVE_1018,{2U,5U,0U}}, +{MOVE_1018,{3U,5U,0U}}, +{MOVE_1018,{4U,5U,0U}}, +{MOVE_1018,{5U,5U,0U}}, +{MOVE_1018,{6U,5U,0U}}, +{MOVE_1018,{7U,5U,0U}}, +{MOVE_1020,{0U,5U,0U}}, +{MOVE_1020,{1U,5U,0U}}, +{MOVE_1020,{2U,5U,0U}}, +{MOVE_1020,{3U,5U,0U}}, +{MOVE_1020,{4U,5U,0U}}, +{MOVE_1020,{5U,5U,0U}}, +{MOVE_1020,{6U,5U,0U}}, +{MOVE_1020,{7U,5U,0U}}, +{MOVE_1028,{0U,5U,0U}}, +{MOVE_1028,{1U,5U,0U}}, +{MOVE_1028,{2U,5U,0U}}, +{MOVE_1028,{3U,5U,0U}}, +{MOVE_1028,{4U,5U,0U}}, +{MOVE_1028,{5U,5U,0U}}, +{MOVE_1028,{6U,5U,0U}}, +{MOVE_1028,{7U,5U,0U}}, +{MOVE_1030,{0U,5U,0U}}, +{MOVE_1030,{1U,5U,0U}}, +{MOVE_1030,{2U,5U,0U}}, +{MOVE_1030,{3U,5U,0U}}, +{MOVE_1030,{4U,5U,0U}}, +{MOVE_1030,{5U,5U,0U}}, +{MOVE_1030,{6U,5U,0U}}, +{MOVE_1030,{7U,5U,0U}}, +{MOVE_1038,{0U,5U,0U}}, +{MOVE_1039,{0U,5U,0U}}, +{MOVE_103A,{0U,5U,0U}}, +{MOVE_103B,{0U,5U,0U}}, +{MOVE_103C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1080,{0U,5U,0U}}, +{MOVE_1080,{1U,5U,0U}}, +{MOVE_1080,{2U,5U,0U}}, +{MOVE_1080,{3U,5U,0U}}, +{MOVE_1080,{4U,5U,0U}}, +{MOVE_1080,{5U,5U,0U}}, +{MOVE_1080,{6U,5U,0U}}, +{MOVE_1080,{7U,5U,0U}}, +{MOVE_1088,{0U,5U,0U}}, +{MOVE_1088,{1U,5U,0U}}, +{MOVE_1088,{2U,5U,0U}}, +{MOVE_1088,{3U,5U,0U}}, +{MOVE_1088,{4U,5U,0U}}, +{MOVE_1088,{5U,5U,0U}}, +{MOVE_1088,{6U,5U,0U}}, +{MOVE_1088,{7U,5U,0U}}, +{MOVE_1090,{0U,5U,0U}}, +{MOVE_1090,{1U,5U,0U}}, +{MOVE_1090,{2U,5U,0U}}, +{MOVE_1090,{3U,5U,0U}}, +{MOVE_1090,{4U,5U,0U}}, +{MOVE_1090,{5U,5U,0U}}, +{MOVE_1090,{6U,5U,0U}}, +{MOVE_1090,{7U,5U,0U}}, +{MOVE_1098,{0U,5U,0U}}, +{MOVE_1098,{1U,5U,0U}}, +{MOVE_1098,{2U,5U,0U}}, +{MOVE_1098,{3U,5U,0U}}, +{MOVE_1098,{4U,5U,0U}}, +{MOVE_1098,{5U,5U,0U}}, +{MOVE_1098,{6U,5U,0U}}, +{MOVE_1098,{7U,5U,0U}}, +{MOVE_10A0,{0U,5U,0U}}, +{MOVE_10A0,{1U,5U,0U}}, +{MOVE_10A0,{2U,5U,0U}}, +{MOVE_10A0,{3U,5U,0U}}, +{MOVE_10A0,{4U,5U,0U}}, +{MOVE_10A0,{5U,5U,0U}}, +{MOVE_10A0,{6U,5U,0U}}, +{MOVE_10A0,{7U,5U,0U}}, +{MOVE_10A8,{0U,5U,0U}}, +{MOVE_10A8,{1U,5U,0U}}, +{MOVE_10A8,{2U,5U,0U}}, +{MOVE_10A8,{3U,5U,0U}}, +{MOVE_10A8,{4U,5U,0U}}, +{MOVE_10A8,{5U,5U,0U}}, +{MOVE_10A8,{6U,5U,0U}}, +{MOVE_10A8,{7U,5U,0U}}, +{MOVE_10B0,{0U,5U,0U}}, +{MOVE_10B0,{1U,5U,0U}}, +{MOVE_10B0,{2U,5U,0U}}, +{MOVE_10B0,{3U,5U,0U}}, +{MOVE_10B0,{4U,5U,0U}}, +{MOVE_10B0,{5U,5U,0U}}, +{MOVE_10B0,{6U,5U,0U}}, +{MOVE_10B0,{7U,5U,0U}}, +{MOVE_10B8,{0U,5U,0U}}, +{MOVE_10B9,{0U,5U,0U}}, +{MOVE_10BA,{0U,5U,0U}}, +{MOVE_10BB,{0U,5U,0U}}, +{MOVE_10BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_10C0,{0U,5U,0U}}, +{MOVE_10C0,{1U,5U,0U}}, +{MOVE_10C0,{2U,5U,0U}}, +{MOVE_10C0,{3U,5U,0U}}, +{MOVE_10C0,{4U,5U,0U}}, +{MOVE_10C0,{5U,5U,0U}}, +{MOVE_10C0,{6U,5U,0U}}, +{MOVE_10C0,{7U,5U,0U}}, +{MOVE_10C8,{0U,5U,0U}}, +{MOVE_10C8,{1U,5U,0U}}, +{MOVE_10C8,{2U,5U,0U}}, +{MOVE_10C8,{3U,5U,0U}}, +{MOVE_10C8,{4U,5U,0U}}, +{MOVE_10C8,{5U,5U,0U}}, +{MOVE_10C8,{6U,5U,0U}}, +{MOVE_10C8,{7U,5U,0U}}, +{MOVE_10D0,{0U,5U,0U}}, +{MOVE_10D0,{1U,5U,0U}}, +{MOVE_10D0,{2U,5U,0U}}, +{MOVE_10D0,{3U,5U,0U}}, +{MOVE_10D0,{4U,5U,0U}}, +{MOVE_10D0,{5U,5U,0U}}, +{MOVE_10D0,{6U,5U,0U}}, +{MOVE_10D0,{7U,5U,0U}}, +{MOVE_10D8,{0U,5U,0U}}, +{MOVE_10D8,{1U,5U,0U}}, +{MOVE_10D8,{2U,5U,0U}}, +{MOVE_10D8,{3U,5U,0U}}, +{MOVE_10D8,{4U,5U,0U}}, +{MOVE_10D8,{5U,5U,0U}}, +{MOVE_10D8,{6U,5U,0U}}, +{MOVE_10D8,{7U,5U,0U}}, +{MOVE_10E0,{0U,5U,0U}}, +{MOVE_10E0,{1U,5U,0U}}, +{MOVE_10E0,{2U,5U,0U}}, +{MOVE_10E0,{3U,5U,0U}}, +{MOVE_10E0,{4U,5U,0U}}, +{MOVE_10E0,{5U,5U,0U}}, +{MOVE_10E0,{6U,5U,0U}}, +{MOVE_10E0,{7U,5U,0U}}, +{MOVE_10E8,{0U,5U,0U}}, +{MOVE_10E8,{1U,5U,0U}}, +{MOVE_10E8,{2U,5U,0U}}, +{MOVE_10E8,{3U,5U,0U}}, +{MOVE_10E8,{4U,5U,0U}}, +{MOVE_10E8,{5U,5U,0U}}, +{MOVE_10E8,{6U,5U,0U}}, +{MOVE_10E8,{7U,5U,0U}}, +{MOVE_10F0,{0U,5U,0U}}, +{MOVE_10F0,{1U,5U,0U}}, +{MOVE_10F0,{2U,5U,0U}}, +{MOVE_10F0,{3U,5U,0U}}, +{MOVE_10F0,{4U,5U,0U}}, +{MOVE_10F0,{5U,5U,0U}}, +{MOVE_10F0,{6U,5U,0U}}, +{MOVE_10F0,{7U,5U,0U}}, +{MOVE_10F8,{0U,5U,0U}}, +{MOVE_10F9,{0U,5U,0U}}, +{MOVE_10FA,{0U,5U,0U}}, +{MOVE_10FB,{0U,5U,0U}}, +{MOVE_10FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1100,{0U,5U,0U}}, +{MOVE_1100,{1U,5U,0U}}, +{MOVE_1100,{2U,5U,0U}}, +{MOVE_1100,{3U,5U,0U}}, +{MOVE_1100,{4U,5U,0U}}, +{MOVE_1100,{5U,5U,0U}}, +{MOVE_1100,{6U,5U,0U}}, +{MOVE_1100,{7U,5U,0U}}, +{MOVE_1108,{0U,5U,0U}}, +{MOVE_1108,{1U,5U,0U}}, +{MOVE_1108,{2U,5U,0U}}, +{MOVE_1108,{3U,5U,0U}}, +{MOVE_1108,{4U,5U,0U}}, +{MOVE_1108,{5U,5U,0U}}, +{MOVE_1108,{6U,5U,0U}}, +{MOVE_1108,{7U,5U,0U}}, +{MOVE_1110,{0U,5U,0U}}, +{MOVE_1110,{1U,5U,0U}}, +{MOVE_1110,{2U,5U,0U}}, +{MOVE_1110,{3U,5U,0U}}, +{MOVE_1110,{4U,5U,0U}}, +{MOVE_1110,{5U,5U,0U}}, +{MOVE_1110,{6U,5U,0U}}, +{MOVE_1110,{7U,5U,0U}}, +{MOVE_1118,{0U,5U,0U}}, +{MOVE_1118,{1U,5U,0U}}, +{MOVE_1118,{2U,5U,0U}}, +{MOVE_1118,{3U,5U,0U}}, +{MOVE_1118,{4U,5U,0U}}, +{MOVE_1118,{5U,5U,0U}}, +{MOVE_1118,{6U,5U,0U}}, +{MOVE_1118,{7U,5U,0U}}, +{MOVE_1120,{0U,5U,0U}}, +{MOVE_1120,{1U,5U,0U}}, +{MOVE_1120,{2U,5U,0U}}, +{MOVE_1120,{3U,5U,0U}}, +{MOVE_1120,{4U,5U,0U}}, +{MOVE_1120,{5U,5U,0U}}, +{MOVE_1120,{6U,5U,0U}}, +{MOVE_1120,{7U,5U,0U}}, +{MOVE_1128,{0U,5U,0U}}, +{MOVE_1128,{1U,5U,0U}}, +{MOVE_1128,{2U,5U,0U}}, +{MOVE_1128,{3U,5U,0U}}, +{MOVE_1128,{4U,5U,0U}}, +{MOVE_1128,{5U,5U,0U}}, +{MOVE_1128,{6U,5U,0U}}, +{MOVE_1128,{7U,5U,0U}}, +{MOVE_1130,{0U,5U,0U}}, +{MOVE_1130,{1U,5U,0U}}, +{MOVE_1130,{2U,5U,0U}}, +{MOVE_1130,{3U,5U,0U}}, +{MOVE_1130,{4U,5U,0U}}, +{MOVE_1130,{5U,5U,0U}}, +{MOVE_1130,{6U,5U,0U}}, +{MOVE_1130,{7U,5U,0U}}, +{MOVE_1138,{0U,5U,0U}}, +{MOVE_1139,{0U,5U,0U}}, +{MOVE_113A,{0U,5U,0U}}, +{MOVE_113B,{0U,5U,0U}}, +{MOVE_113C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1140,{0U,5U,0U}}, +{MOVE_1140,{1U,5U,0U}}, +{MOVE_1140,{2U,5U,0U}}, +{MOVE_1140,{3U,5U,0U}}, +{MOVE_1140,{4U,5U,0U}}, +{MOVE_1140,{5U,5U,0U}}, +{MOVE_1140,{6U,5U,0U}}, +{MOVE_1140,{7U,5U,0U}}, +{MOVE_1148,{0U,5U,0U}}, +{MOVE_1148,{1U,5U,0U}}, +{MOVE_1148,{2U,5U,0U}}, +{MOVE_1148,{3U,5U,0U}}, +{MOVE_1148,{4U,5U,0U}}, +{MOVE_1148,{5U,5U,0U}}, +{MOVE_1148,{6U,5U,0U}}, +{MOVE_1148,{7U,5U,0U}}, +{MOVE_1150,{0U,5U,0U}}, +{MOVE_1150,{1U,5U,0U}}, +{MOVE_1150,{2U,5U,0U}}, +{MOVE_1150,{3U,5U,0U}}, +{MOVE_1150,{4U,5U,0U}}, +{MOVE_1150,{5U,5U,0U}}, +{MOVE_1150,{6U,5U,0U}}, +{MOVE_1150,{7U,5U,0U}}, +{MOVE_1158,{0U,5U,0U}}, +{MOVE_1158,{1U,5U,0U}}, +{MOVE_1158,{2U,5U,0U}}, +{MOVE_1158,{3U,5U,0U}}, +{MOVE_1158,{4U,5U,0U}}, +{MOVE_1158,{5U,5U,0U}}, +{MOVE_1158,{6U,5U,0U}}, +{MOVE_1158,{7U,5U,0U}}, +{MOVE_1160,{0U,5U,0U}}, +{MOVE_1160,{1U,5U,0U}}, +{MOVE_1160,{2U,5U,0U}}, +{MOVE_1160,{3U,5U,0U}}, +{MOVE_1160,{4U,5U,0U}}, +{MOVE_1160,{5U,5U,0U}}, +{MOVE_1160,{6U,5U,0U}}, +{MOVE_1160,{7U,5U,0U}}, +{MOVE_1168,{0U,5U,0U}}, +{MOVE_1168,{1U,5U,0U}}, +{MOVE_1168,{2U,5U,0U}}, +{MOVE_1168,{3U,5U,0U}}, +{MOVE_1168,{4U,5U,0U}}, +{MOVE_1168,{5U,5U,0U}}, +{MOVE_1168,{6U,5U,0U}}, +{MOVE_1168,{7U,5U,0U}}, +{MOVE_1170,{0U,5U,0U}}, +{MOVE_1170,{1U,5U,0U}}, +{MOVE_1170,{2U,5U,0U}}, +{MOVE_1170,{3U,5U,0U}}, +{MOVE_1170,{4U,5U,0U}}, +{MOVE_1170,{5U,5U,0U}}, +{MOVE_1170,{6U,5U,0U}}, +{MOVE_1170,{7U,5U,0U}}, +{MOVE_1178,{0U,5U,0U}}, +{MOVE_1179,{0U,5U,0U}}, +{MOVE_117A,{0U,5U,0U}}, +{MOVE_117B,{0U,5U,0U}}, +{MOVE_117C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1180,{0U,5U,0U}}, +{MOVE_1180,{1U,5U,0U}}, +{MOVE_1180,{2U,5U,0U}}, +{MOVE_1180,{3U,5U,0U}}, +{MOVE_1180,{4U,5U,0U}}, +{MOVE_1180,{5U,5U,0U}}, +{MOVE_1180,{6U,5U,0U}}, +{MOVE_1180,{7U,5U,0U}}, +{MOVE_1188,{0U,5U,0U}}, +{MOVE_1188,{1U,5U,0U}}, +{MOVE_1188,{2U,5U,0U}}, +{MOVE_1188,{3U,5U,0U}}, +{MOVE_1188,{4U,5U,0U}}, +{MOVE_1188,{5U,5U,0U}}, +{MOVE_1188,{6U,5U,0U}}, +{MOVE_1188,{7U,5U,0U}}, +{MOVE_1190,{0U,5U,0U}}, +{MOVE_1190,{1U,5U,0U}}, +{MOVE_1190,{2U,5U,0U}}, +{MOVE_1190,{3U,5U,0U}}, +{MOVE_1190,{4U,5U,0U}}, +{MOVE_1190,{5U,5U,0U}}, +{MOVE_1190,{6U,5U,0U}}, +{MOVE_1190,{7U,5U,0U}}, +{MOVE_1198,{0U,5U,0U}}, +{MOVE_1198,{1U,5U,0U}}, +{MOVE_1198,{2U,5U,0U}}, +{MOVE_1198,{3U,5U,0U}}, +{MOVE_1198,{4U,5U,0U}}, +{MOVE_1198,{5U,5U,0U}}, +{MOVE_1198,{6U,5U,0U}}, +{MOVE_1198,{7U,5U,0U}}, +{MOVE_11A0,{0U,5U,0U}}, +{MOVE_11A0,{1U,5U,0U}}, +{MOVE_11A0,{2U,5U,0U}}, +{MOVE_11A0,{3U,5U,0U}}, +{MOVE_11A0,{4U,5U,0U}}, +{MOVE_11A0,{5U,5U,0U}}, +{MOVE_11A0,{6U,5U,0U}}, +{MOVE_11A0,{7U,5U,0U}}, +{MOVE_11A8,{0U,5U,0U}}, +{MOVE_11A8,{1U,5U,0U}}, +{MOVE_11A8,{2U,5U,0U}}, +{MOVE_11A8,{3U,5U,0U}}, +{MOVE_11A8,{4U,5U,0U}}, +{MOVE_11A8,{5U,5U,0U}}, +{MOVE_11A8,{6U,5U,0U}}, +{MOVE_11A8,{7U,5U,0U}}, +{MOVE_11B0,{0U,5U,0U}}, +{MOVE_11B0,{1U,5U,0U}}, +{MOVE_11B0,{2U,5U,0U}}, +{MOVE_11B0,{3U,5U,0U}}, +{MOVE_11B0,{4U,5U,0U}}, +{MOVE_11B0,{5U,5U,0U}}, +{MOVE_11B0,{6U,5U,0U}}, +{MOVE_11B0,{7U,5U,0U}}, +{MOVE_11B8,{0U,5U,0U}}, +{MOVE_11B9,{0U,5U,0U}}, +{MOVE_11BA,{0U,5U,0U}}, +{MOVE_11BB,{0U,5U,0U}}, +{MOVE_11BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1000,{0U,6U,0U}}, +{MOVE_1000,{1U,6U,0U}}, +{MOVE_1000,{2U,6U,0U}}, +{MOVE_1000,{3U,6U,0U}}, +{MOVE_1000,{4U,6U,0U}}, +{MOVE_1000,{5U,6U,0U}}, +{MOVE_1000,{6U,6U,0U}}, +{MOVE_1000,{7U,6U,0U}}, +{MOVE_1008,{0U,6U,0U}}, +{MOVE_1008,{1U,6U,0U}}, +{MOVE_1008,{2U,6U,0U}}, +{MOVE_1008,{3U,6U,0U}}, +{MOVE_1008,{4U,6U,0U}}, +{MOVE_1008,{5U,6U,0U}}, +{MOVE_1008,{6U,6U,0U}}, +{MOVE_1008,{7U,6U,0U}}, +{MOVE_1010,{0U,6U,0U}}, +{MOVE_1010,{1U,6U,0U}}, +{MOVE_1010,{2U,6U,0U}}, +{MOVE_1010,{3U,6U,0U}}, +{MOVE_1010,{4U,6U,0U}}, +{MOVE_1010,{5U,6U,0U}}, +{MOVE_1010,{6U,6U,0U}}, +{MOVE_1010,{7U,6U,0U}}, +{MOVE_1018,{0U,6U,0U}}, +{MOVE_1018,{1U,6U,0U}}, +{MOVE_1018,{2U,6U,0U}}, +{MOVE_1018,{3U,6U,0U}}, +{MOVE_1018,{4U,6U,0U}}, +{MOVE_1018,{5U,6U,0U}}, +{MOVE_1018,{6U,6U,0U}}, +{MOVE_1018,{7U,6U,0U}}, +{MOVE_1020,{0U,6U,0U}}, +{MOVE_1020,{1U,6U,0U}}, +{MOVE_1020,{2U,6U,0U}}, +{MOVE_1020,{3U,6U,0U}}, +{MOVE_1020,{4U,6U,0U}}, +{MOVE_1020,{5U,6U,0U}}, +{MOVE_1020,{6U,6U,0U}}, +{MOVE_1020,{7U,6U,0U}}, +{MOVE_1028,{0U,6U,0U}}, +{MOVE_1028,{1U,6U,0U}}, +{MOVE_1028,{2U,6U,0U}}, +{MOVE_1028,{3U,6U,0U}}, +{MOVE_1028,{4U,6U,0U}}, +{MOVE_1028,{5U,6U,0U}}, +{MOVE_1028,{6U,6U,0U}}, +{MOVE_1028,{7U,6U,0U}}, +{MOVE_1030,{0U,6U,0U}}, +{MOVE_1030,{1U,6U,0U}}, +{MOVE_1030,{2U,6U,0U}}, +{MOVE_1030,{3U,6U,0U}}, +{MOVE_1030,{4U,6U,0U}}, +{MOVE_1030,{5U,6U,0U}}, +{MOVE_1030,{6U,6U,0U}}, +{MOVE_1030,{7U,6U,0U}}, +{MOVE_1038,{0U,6U,0U}}, +{MOVE_1039,{0U,6U,0U}}, +{MOVE_103A,{0U,6U,0U}}, +{MOVE_103B,{0U,6U,0U}}, +{MOVE_103C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1080,{0U,6U,0U}}, +{MOVE_1080,{1U,6U,0U}}, +{MOVE_1080,{2U,6U,0U}}, +{MOVE_1080,{3U,6U,0U}}, +{MOVE_1080,{4U,6U,0U}}, +{MOVE_1080,{5U,6U,0U}}, +{MOVE_1080,{6U,6U,0U}}, +{MOVE_1080,{7U,6U,0U}}, +{MOVE_1088,{0U,6U,0U}}, +{MOVE_1088,{1U,6U,0U}}, +{MOVE_1088,{2U,6U,0U}}, +{MOVE_1088,{3U,6U,0U}}, +{MOVE_1088,{4U,6U,0U}}, +{MOVE_1088,{5U,6U,0U}}, +{MOVE_1088,{6U,6U,0U}}, +{MOVE_1088,{7U,6U,0U}}, +{MOVE_1090,{0U,6U,0U}}, +{MOVE_1090,{1U,6U,0U}}, +{MOVE_1090,{2U,6U,0U}}, +{MOVE_1090,{3U,6U,0U}}, +{MOVE_1090,{4U,6U,0U}}, +{MOVE_1090,{5U,6U,0U}}, +{MOVE_1090,{6U,6U,0U}}, +{MOVE_1090,{7U,6U,0U}}, +{MOVE_1098,{0U,6U,0U}}, +{MOVE_1098,{1U,6U,0U}}, +{MOVE_1098,{2U,6U,0U}}, +{MOVE_1098,{3U,6U,0U}}, +{MOVE_1098,{4U,6U,0U}}, +{MOVE_1098,{5U,6U,0U}}, +{MOVE_1098,{6U,6U,0U}}, +{MOVE_1098,{7U,6U,0U}}, +{MOVE_10A0,{0U,6U,0U}}, +{MOVE_10A0,{1U,6U,0U}}, +{MOVE_10A0,{2U,6U,0U}}, +{MOVE_10A0,{3U,6U,0U}}, +{MOVE_10A0,{4U,6U,0U}}, +{MOVE_10A0,{5U,6U,0U}}, +{MOVE_10A0,{6U,6U,0U}}, +{MOVE_10A0,{7U,6U,0U}}, +{MOVE_10A8,{0U,6U,0U}}, +{MOVE_10A8,{1U,6U,0U}}, +{MOVE_10A8,{2U,6U,0U}}, +{MOVE_10A8,{3U,6U,0U}}, +{MOVE_10A8,{4U,6U,0U}}, +{MOVE_10A8,{5U,6U,0U}}, +{MOVE_10A8,{6U,6U,0U}}, +{MOVE_10A8,{7U,6U,0U}}, +{MOVE_10B0,{0U,6U,0U}}, +{MOVE_10B0,{1U,6U,0U}}, +{MOVE_10B0,{2U,6U,0U}}, +{MOVE_10B0,{3U,6U,0U}}, +{MOVE_10B0,{4U,6U,0U}}, +{MOVE_10B0,{5U,6U,0U}}, +{MOVE_10B0,{6U,6U,0U}}, +{MOVE_10B0,{7U,6U,0U}}, +{MOVE_10B8,{0U,6U,0U}}, +{MOVE_10B9,{0U,6U,0U}}, +{MOVE_10BA,{0U,6U,0U}}, +{MOVE_10BB,{0U,6U,0U}}, +{MOVE_10BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_10C0,{0U,6U,0U}}, +{MOVE_10C0,{1U,6U,0U}}, +{MOVE_10C0,{2U,6U,0U}}, +{MOVE_10C0,{3U,6U,0U}}, +{MOVE_10C0,{4U,6U,0U}}, +{MOVE_10C0,{5U,6U,0U}}, +{MOVE_10C0,{6U,6U,0U}}, +{MOVE_10C0,{7U,6U,0U}}, +{MOVE_10C8,{0U,6U,0U}}, +{MOVE_10C8,{1U,6U,0U}}, +{MOVE_10C8,{2U,6U,0U}}, +{MOVE_10C8,{3U,6U,0U}}, +{MOVE_10C8,{4U,6U,0U}}, +{MOVE_10C8,{5U,6U,0U}}, +{MOVE_10C8,{6U,6U,0U}}, +{MOVE_10C8,{7U,6U,0U}}, +{MOVE_10D0,{0U,6U,0U}}, +{MOVE_10D0,{1U,6U,0U}}, +{MOVE_10D0,{2U,6U,0U}}, +{MOVE_10D0,{3U,6U,0U}}, +{MOVE_10D0,{4U,6U,0U}}, +{MOVE_10D0,{5U,6U,0U}}, +{MOVE_10D0,{6U,6U,0U}}, +{MOVE_10D0,{7U,6U,0U}}, +{MOVE_10D8,{0U,6U,0U}}, +{MOVE_10D8,{1U,6U,0U}}, +{MOVE_10D8,{2U,6U,0U}}, +{MOVE_10D8,{3U,6U,0U}}, +{MOVE_10D8,{4U,6U,0U}}, +{MOVE_10D8,{5U,6U,0U}}, +{MOVE_10D8,{6U,6U,0U}}, +{MOVE_10D8,{7U,6U,0U}}, +{MOVE_10E0,{0U,6U,0U}}, +{MOVE_10E0,{1U,6U,0U}}, +{MOVE_10E0,{2U,6U,0U}}, +{MOVE_10E0,{3U,6U,0U}}, +{MOVE_10E0,{4U,6U,0U}}, +{MOVE_10E0,{5U,6U,0U}}, +{MOVE_10E0,{6U,6U,0U}}, +{MOVE_10E0,{7U,6U,0U}}, +{MOVE_10E8,{0U,6U,0U}}, +{MOVE_10E8,{1U,6U,0U}}, +{MOVE_10E8,{2U,6U,0U}}, +{MOVE_10E8,{3U,6U,0U}}, +{MOVE_10E8,{4U,6U,0U}}, +{MOVE_10E8,{5U,6U,0U}}, +{MOVE_10E8,{6U,6U,0U}}, +{MOVE_10E8,{7U,6U,0U}}, +{MOVE_10F0,{0U,6U,0U}}, +{MOVE_10F0,{1U,6U,0U}}, +{MOVE_10F0,{2U,6U,0U}}, +{MOVE_10F0,{3U,6U,0U}}, +{MOVE_10F0,{4U,6U,0U}}, +{MOVE_10F0,{5U,6U,0U}}, +{MOVE_10F0,{6U,6U,0U}}, +{MOVE_10F0,{7U,6U,0U}}, +{MOVE_10F8,{0U,6U,0U}}, +{MOVE_10F9,{0U,6U,0U}}, +{MOVE_10FA,{0U,6U,0U}}, +{MOVE_10FB,{0U,6U,0U}}, +{MOVE_10FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1100,{0U,6U,0U}}, +{MOVE_1100,{1U,6U,0U}}, +{MOVE_1100,{2U,6U,0U}}, +{MOVE_1100,{3U,6U,0U}}, +{MOVE_1100,{4U,6U,0U}}, +{MOVE_1100,{5U,6U,0U}}, +{MOVE_1100,{6U,6U,0U}}, +{MOVE_1100,{7U,6U,0U}}, +{MOVE_1108,{0U,6U,0U}}, +{MOVE_1108,{1U,6U,0U}}, +{MOVE_1108,{2U,6U,0U}}, +{MOVE_1108,{3U,6U,0U}}, +{MOVE_1108,{4U,6U,0U}}, +{MOVE_1108,{5U,6U,0U}}, +{MOVE_1108,{6U,6U,0U}}, +{MOVE_1108,{7U,6U,0U}}, +{MOVE_1110,{0U,6U,0U}}, +{MOVE_1110,{1U,6U,0U}}, +{MOVE_1110,{2U,6U,0U}}, +{MOVE_1110,{3U,6U,0U}}, +{MOVE_1110,{4U,6U,0U}}, +{MOVE_1110,{5U,6U,0U}}, +{MOVE_1110,{6U,6U,0U}}, +{MOVE_1110,{7U,6U,0U}}, +{MOVE_1118,{0U,6U,0U}}, +{MOVE_1118,{1U,6U,0U}}, +{MOVE_1118,{2U,6U,0U}}, +{MOVE_1118,{3U,6U,0U}}, +{MOVE_1118,{4U,6U,0U}}, +{MOVE_1118,{5U,6U,0U}}, +{MOVE_1118,{6U,6U,0U}}, +{MOVE_1118,{7U,6U,0U}}, +{MOVE_1120,{0U,6U,0U}}, +{MOVE_1120,{1U,6U,0U}}, +{MOVE_1120,{2U,6U,0U}}, +{MOVE_1120,{3U,6U,0U}}, +{MOVE_1120,{4U,6U,0U}}, +{MOVE_1120,{5U,6U,0U}}, +{MOVE_1120,{6U,6U,0U}}, +{MOVE_1120,{7U,6U,0U}}, +{MOVE_1128,{0U,6U,0U}}, +{MOVE_1128,{1U,6U,0U}}, +{MOVE_1128,{2U,6U,0U}}, +{MOVE_1128,{3U,6U,0U}}, +{MOVE_1128,{4U,6U,0U}}, +{MOVE_1128,{5U,6U,0U}}, +{MOVE_1128,{6U,6U,0U}}, +{MOVE_1128,{7U,6U,0U}}, +{MOVE_1130,{0U,6U,0U}}, +{MOVE_1130,{1U,6U,0U}}, +{MOVE_1130,{2U,6U,0U}}, +{MOVE_1130,{3U,6U,0U}}, +{MOVE_1130,{4U,6U,0U}}, +{MOVE_1130,{5U,6U,0U}}, +{MOVE_1130,{6U,6U,0U}}, +{MOVE_1130,{7U,6U,0U}}, +{MOVE_1138,{0U,6U,0U}}, +{MOVE_1139,{0U,6U,0U}}, +{MOVE_113A,{0U,6U,0U}}, +{MOVE_113B,{0U,6U,0U}}, +{MOVE_113C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1140,{0U,6U,0U}}, +{MOVE_1140,{1U,6U,0U}}, +{MOVE_1140,{2U,6U,0U}}, +{MOVE_1140,{3U,6U,0U}}, +{MOVE_1140,{4U,6U,0U}}, +{MOVE_1140,{5U,6U,0U}}, +{MOVE_1140,{6U,6U,0U}}, +{MOVE_1140,{7U,6U,0U}}, +{MOVE_1148,{0U,6U,0U}}, +{MOVE_1148,{1U,6U,0U}}, +{MOVE_1148,{2U,6U,0U}}, +{MOVE_1148,{3U,6U,0U}}, +{MOVE_1148,{4U,6U,0U}}, +{MOVE_1148,{5U,6U,0U}}, +{MOVE_1148,{6U,6U,0U}}, +{MOVE_1148,{7U,6U,0U}}, +{MOVE_1150,{0U,6U,0U}}, +{MOVE_1150,{1U,6U,0U}}, +{MOVE_1150,{2U,6U,0U}}, +{MOVE_1150,{3U,6U,0U}}, +{MOVE_1150,{4U,6U,0U}}, +{MOVE_1150,{5U,6U,0U}}, +{MOVE_1150,{6U,6U,0U}}, +{MOVE_1150,{7U,6U,0U}}, +{MOVE_1158,{0U,6U,0U}}, +{MOVE_1158,{1U,6U,0U}}, +{MOVE_1158,{2U,6U,0U}}, +{MOVE_1158,{3U,6U,0U}}, +{MOVE_1158,{4U,6U,0U}}, +{MOVE_1158,{5U,6U,0U}}, +{MOVE_1158,{6U,6U,0U}}, +{MOVE_1158,{7U,6U,0U}}, +{MOVE_1160,{0U,6U,0U}}, +{MOVE_1160,{1U,6U,0U}}, +{MOVE_1160,{2U,6U,0U}}, +{MOVE_1160,{3U,6U,0U}}, +{MOVE_1160,{4U,6U,0U}}, +{MOVE_1160,{5U,6U,0U}}, +{MOVE_1160,{6U,6U,0U}}, +{MOVE_1160,{7U,6U,0U}}, +{MOVE_1168,{0U,6U,0U}}, +{MOVE_1168,{1U,6U,0U}}, +{MOVE_1168,{2U,6U,0U}}, +{MOVE_1168,{3U,6U,0U}}, +{MOVE_1168,{4U,6U,0U}}, +{MOVE_1168,{5U,6U,0U}}, +{MOVE_1168,{6U,6U,0U}}, +{MOVE_1168,{7U,6U,0U}}, +{MOVE_1170,{0U,6U,0U}}, +{MOVE_1170,{1U,6U,0U}}, +{MOVE_1170,{2U,6U,0U}}, +{MOVE_1170,{3U,6U,0U}}, +{MOVE_1170,{4U,6U,0U}}, +{MOVE_1170,{5U,6U,0U}}, +{MOVE_1170,{6U,6U,0U}}, +{MOVE_1170,{7U,6U,0U}}, +{MOVE_1178,{0U,6U,0U}}, +{MOVE_1179,{0U,6U,0U}}, +{MOVE_117A,{0U,6U,0U}}, +{MOVE_117B,{0U,6U,0U}}, +{MOVE_117C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1180,{0U,6U,0U}}, +{MOVE_1180,{1U,6U,0U}}, +{MOVE_1180,{2U,6U,0U}}, +{MOVE_1180,{3U,6U,0U}}, +{MOVE_1180,{4U,6U,0U}}, +{MOVE_1180,{5U,6U,0U}}, +{MOVE_1180,{6U,6U,0U}}, +{MOVE_1180,{7U,6U,0U}}, +{MOVE_1188,{0U,6U,0U}}, +{MOVE_1188,{1U,6U,0U}}, +{MOVE_1188,{2U,6U,0U}}, +{MOVE_1188,{3U,6U,0U}}, +{MOVE_1188,{4U,6U,0U}}, +{MOVE_1188,{5U,6U,0U}}, +{MOVE_1188,{6U,6U,0U}}, +{MOVE_1188,{7U,6U,0U}}, +{MOVE_1190,{0U,6U,0U}}, +{MOVE_1190,{1U,6U,0U}}, +{MOVE_1190,{2U,6U,0U}}, +{MOVE_1190,{3U,6U,0U}}, +{MOVE_1190,{4U,6U,0U}}, +{MOVE_1190,{5U,6U,0U}}, +{MOVE_1190,{6U,6U,0U}}, +{MOVE_1190,{7U,6U,0U}}, +{MOVE_1198,{0U,6U,0U}}, +{MOVE_1198,{1U,6U,0U}}, +{MOVE_1198,{2U,6U,0U}}, +{MOVE_1198,{3U,6U,0U}}, +{MOVE_1198,{4U,6U,0U}}, +{MOVE_1198,{5U,6U,0U}}, +{MOVE_1198,{6U,6U,0U}}, +{MOVE_1198,{7U,6U,0U}}, +{MOVE_11A0,{0U,6U,0U}}, +{MOVE_11A0,{1U,6U,0U}}, +{MOVE_11A0,{2U,6U,0U}}, +{MOVE_11A0,{3U,6U,0U}}, +{MOVE_11A0,{4U,6U,0U}}, +{MOVE_11A0,{5U,6U,0U}}, +{MOVE_11A0,{6U,6U,0U}}, +{MOVE_11A0,{7U,6U,0U}}, +{MOVE_11A8,{0U,6U,0U}}, +{MOVE_11A8,{1U,6U,0U}}, +{MOVE_11A8,{2U,6U,0U}}, +{MOVE_11A8,{3U,6U,0U}}, +{MOVE_11A8,{4U,6U,0U}}, +{MOVE_11A8,{5U,6U,0U}}, +{MOVE_11A8,{6U,6U,0U}}, +{MOVE_11A8,{7U,6U,0U}}, +{MOVE_11B0,{0U,6U,0U}}, +{MOVE_11B0,{1U,6U,0U}}, +{MOVE_11B0,{2U,6U,0U}}, +{MOVE_11B0,{3U,6U,0U}}, +{MOVE_11B0,{4U,6U,0U}}, +{MOVE_11B0,{5U,6U,0U}}, +{MOVE_11B0,{6U,6U,0U}}, +{MOVE_11B0,{7U,6U,0U}}, +{MOVE_11B8,{0U,6U,0U}}, +{MOVE_11B9,{0U,6U,0U}}, +{MOVE_11BA,{0U,6U,0U}}, +{MOVE_11BB,{0U,6U,0U}}, +{MOVE_11BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1000,{0U,7U,0U}}, +{MOVE_1000,{1U,7U,0U}}, +{MOVE_1000,{2U,7U,0U}}, +{MOVE_1000,{3U,7U,0U}}, +{MOVE_1000,{4U,7U,0U}}, +{MOVE_1000,{5U,7U,0U}}, +{MOVE_1000,{6U,7U,0U}}, +{MOVE_1000,{7U,7U,0U}}, +{MOVE_1008,{0U,7U,0U}}, +{MOVE_1008,{1U,7U,0U}}, +{MOVE_1008,{2U,7U,0U}}, +{MOVE_1008,{3U,7U,0U}}, +{MOVE_1008,{4U,7U,0U}}, +{MOVE_1008,{5U,7U,0U}}, +{MOVE_1008,{6U,7U,0U}}, +{MOVE_1008,{7U,7U,0U}}, +{MOVE_1010,{0U,7U,0U}}, +{MOVE_1010,{1U,7U,0U}}, +{MOVE_1010,{2U,7U,0U}}, +{MOVE_1010,{3U,7U,0U}}, +{MOVE_1010,{4U,7U,0U}}, +{MOVE_1010,{5U,7U,0U}}, +{MOVE_1010,{6U,7U,0U}}, +{MOVE_1010,{7U,7U,0U}}, +{MOVE_1018,{0U,7U,0U}}, +{MOVE_1018,{1U,7U,0U}}, +{MOVE_1018,{2U,7U,0U}}, +{MOVE_1018,{3U,7U,0U}}, +{MOVE_1018,{4U,7U,0U}}, +{MOVE_1018,{5U,7U,0U}}, +{MOVE_1018,{6U,7U,0U}}, +{MOVE_1018,{7U,7U,0U}}, +{MOVE_1020,{0U,7U,0U}}, +{MOVE_1020,{1U,7U,0U}}, +{MOVE_1020,{2U,7U,0U}}, +{MOVE_1020,{3U,7U,0U}}, +{MOVE_1020,{4U,7U,0U}}, +{MOVE_1020,{5U,7U,0U}}, +{MOVE_1020,{6U,7U,0U}}, +{MOVE_1020,{7U,7U,0U}}, +{MOVE_1028,{0U,7U,0U}}, +{MOVE_1028,{1U,7U,0U}}, +{MOVE_1028,{2U,7U,0U}}, +{MOVE_1028,{3U,7U,0U}}, +{MOVE_1028,{4U,7U,0U}}, +{MOVE_1028,{5U,7U,0U}}, +{MOVE_1028,{6U,7U,0U}}, +{MOVE_1028,{7U,7U,0U}}, +{MOVE_1030,{0U,7U,0U}}, +{MOVE_1030,{1U,7U,0U}}, +{MOVE_1030,{2U,7U,0U}}, +{MOVE_1030,{3U,7U,0U}}, +{MOVE_1030,{4U,7U,0U}}, +{MOVE_1030,{5U,7U,0U}}, +{MOVE_1030,{6U,7U,0U}}, +{MOVE_1030,{7U,7U,0U}}, +{MOVE_1038,{0U,7U,0U}}, +{MOVE_1039,{0U,7U,0U}}, +{MOVE_103A,{0U,7U,0U}}, +{MOVE_103B,{0U,7U,0U}}, +{MOVE_103C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1080,{0U,7U,0U}}, +{MOVE_1080,{1U,7U,0U}}, +{MOVE_1080,{2U,7U,0U}}, +{MOVE_1080,{3U,7U,0U}}, +{MOVE_1080,{4U,7U,0U}}, +{MOVE_1080,{5U,7U,0U}}, +{MOVE_1080,{6U,7U,0U}}, +{MOVE_1080,{7U,7U,0U}}, +{MOVE_1088,{0U,7U,0U}}, +{MOVE_1088,{1U,7U,0U}}, +{MOVE_1088,{2U,7U,0U}}, +{MOVE_1088,{3U,7U,0U}}, +{MOVE_1088,{4U,7U,0U}}, +{MOVE_1088,{5U,7U,0U}}, +{MOVE_1088,{6U,7U,0U}}, +{MOVE_1088,{7U,7U,0U}}, +{MOVE_1090,{0U,7U,0U}}, +{MOVE_1090,{1U,7U,0U}}, +{MOVE_1090,{2U,7U,0U}}, +{MOVE_1090,{3U,7U,0U}}, +{MOVE_1090,{4U,7U,0U}}, +{MOVE_1090,{5U,7U,0U}}, +{MOVE_1090,{6U,7U,0U}}, +{MOVE_1090,{7U,7U,0U}}, +{MOVE_1098,{0U,7U,0U}}, +{MOVE_1098,{1U,7U,0U}}, +{MOVE_1098,{2U,7U,0U}}, +{MOVE_1098,{3U,7U,0U}}, +{MOVE_1098,{4U,7U,0U}}, +{MOVE_1098,{5U,7U,0U}}, +{MOVE_1098,{6U,7U,0U}}, +{MOVE_1098,{7U,7U,0U}}, +{MOVE_10A0,{0U,7U,0U}}, +{MOVE_10A0,{1U,7U,0U}}, +{MOVE_10A0,{2U,7U,0U}}, +{MOVE_10A0,{3U,7U,0U}}, +{MOVE_10A0,{4U,7U,0U}}, +{MOVE_10A0,{5U,7U,0U}}, +{MOVE_10A0,{6U,7U,0U}}, +{MOVE_10A0,{7U,7U,0U}}, +{MOVE_10A8,{0U,7U,0U}}, +{MOVE_10A8,{1U,7U,0U}}, +{MOVE_10A8,{2U,7U,0U}}, +{MOVE_10A8,{3U,7U,0U}}, +{MOVE_10A8,{4U,7U,0U}}, +{MOVE_10A8,{5U,7U,0U}}, +{MOVE_10A8,{6U,7U,0U}}, +{MOVE_10A8,{7U,7U,0U}}, +{MOVE_10B0,{0U,7U,0U}}, +{MOVE_10B0,{1U,7U,0U}}, +{MOVE_10B0,{2U,7U,0U}}, +{MOVE_10B0,{3U,7U,0U}}, +{MOVE_10B0,{4U,7U,0U}}, +{MOVE_10B0,{5U,7U,0U}}, +{MOVE_10B0,{6U,7U,0U}}, +{MOVE_10B0,{7U,7U,0U}}, +{MOVE_10B8,{0U,7U,0U}}, +{MOVE_10B9,{0U,7U,0U}}, +{MOVE_10BA,{0U,7U,0U}}, +{MOVE_10BB,{0U,7U,0U}}, +{MOVE_10BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_10C0,{0U,7U,0U}}, +{MOVE_10C0,{1U,7U,0U}}, +{MOVE_10C0,{2U,7U,0U}}, +{MOVE_10C0,{3U,7U,0U}}, +{MOVE_10C0,{4U,7U,0U}}, +{MOVE_10C0,{5U,7U,0U}}, +{MOVE_10C0,{6U,7U,0U}}, +{MOVE_10C0,{7U,7U,0U}}, +{MOVE_10C8,{0U,7U,0U}}, +{MOVE_10C8,{1U,7U,0U}}, +{MOVE_10C8,{2U,7U,0U}}, +{MOVE_10C8,{3U,7U,0U}}, +{MOVE_10C8,{4U,7U,0U}}, +{MOVE_10C8,{5U,7U,0U}}, +{MOVE_10C8,{6U,7U,0U}}, +{MOVE_10C8,{7U,7U,0U}}, +{MOVE_10D0,{0U,7U,0U}}, +{MOVE_10D0,{1U,7U,0U}}, +{MOVE_10D0,{2U,7U,0U}}, +{MOVE_10D0,{3U,7U,0U}}, +{MOVE_10D0,{4U,7U,0U}}, +{MOVE_10D0,{5U,7U,0U}}, +{MOVE_10D0,{6U,7U,0U}}, +{MOVE_10D0,{7U,7U,0U}}, +{MOVE_10D8,{0U,7U,0U}}, +{MOVE_10D8,{1U,7U,0U}}, +{MOVE_10D8,{2U,7U,0U}}, +{MOVE_10D8,{3U,7U,0U}}, +{MOVE_10D8,{4U,7U,0U}}, +{MOVE_10D8,{5U,7U,0U}}, +{MOVE_10D8,{6U,7U,0U}}, +{MOVE_10D8,{7U,7U,0U}}, +{MOVE_10E0,{0U,7U,0U}}, +{MOVE_10E0,{1U,7U,0U}}, +{MOVE_10E0,{2U,7U,0U}}, +{MOVE_10E0,{3U,7U,0U}}, +{MOVE_10E0,{4U,7U,0U}}, +{MOVE_10E0,{5U,7U,0U}}, +{MOVE_10E0,{6U,7U,0U}}, +{MOVE_10E0,{7U,7U,0U}}, +{MOVE_10E8,{0U,7U,0U}}, +{MOVE_10E8,{1U,7U,0U}}, +{MOVE_10E8,{2U,7U,0U}}, +{MOVE_10E8,{3U,7U,0U}}, +{MOVE_10E8,{4U,7U,0U}}, +{MOVE_10E8,{5U,7U,0U}}, +{MOVE_10E8,{6U,7U,0U}}, +{MOVE_10E8,{7U,7U,0U}}, +{MOVE_10F0,{0U,7U,0U}}, +{MOVE_10F0,{1U,7U,0U}}, +{MOVE_10F0,{2U,7U,0U}}, +{MOVE_10F0,{3U,7U,0U}}, +{MOVE_10F0,{4U,7U,0U}}, +{MOVE_10F0,{5U,7U,0U}}, +{MOVE_10F0,{6U,7U,0U}}, +{MOVE_10F0,{7U,7U,0U}}, +{MOVE_10F8,{0U,7U,0U}}, +{MOVE_10F9,{0U,7U,0U}}, +{MOVE_10FA,{0U,7U,0U}}, +{MOVE_10FB,{0U,7U,0U}}, +{MOVE_10FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1100,{0U,7U,0U}}, +{MOVE_1100,{1U,7U,0U}}, +{MOVE_1100,{2U,7U,0U}}, +{MOVE_1100,{3U,7U,0U}}, +{MOVE_1100,{4U,7U,0U}}, +{MOVE_1100,{5U,7U,0U}}, +{MOVE_1100,{6U,7U,0U}}, +{MOVE_1100,{7U,7U,0U}}, +{MOVE_1108,{0U,7U,0U}}, +{MOVE_1108,{1U,7U,0U}}, +{MOVE_1108,{2U,7U,0U}}, +{MOVE_1108,{3U,7U,0U}}, +{MOVE_1108,{4U,7U,0U}}, +{MOVE_1108,{5U,7U,0U}}, +{MOVE_1108,{6U,7U,0U}}, +{MOVE_1108,{7U,7U,0U}}, +{MOVE_1110,{0U,7U,0U}}, +{MOVE_1110,{1U,7U,0U}}, +{MOVE_1110,{2U,7U,0U}}, +{MOVE_1110,{3U,7U,0U}}, +{MOVE_1110,{4U,7U,0U}}, +{MOVE_1110,{5U,7U,0U}}, +{MOVE_1110,{6U,7U,0U}}, +{MOVE_1110,{7U,7U,0U}}, +{MOVE_1118,{0U,7U,0U}}, +{MOVE_1118,{1U,7U,0U}}, +{MOVE_1118,{2U,7U,0U}}, +{MOVE_1118,{3U,7U,0U}}, +{MOVE_1118,{4U,7U,0U}}, +{MOVE_1118,{5U,7U,0U}}, +{MOVE_1118,{6U,7U,0U}}, +{MOVE_1118,{7U,7U,0U}}, +{MOVE_1120,{0U,7U,0U}}, +{MOVE_1120,{1U,7U,0U}}, +{MOVE_1120,{2U,7U,0U}}, +{MOVE_1120,{3U,7U,0U}}, +{MOVE_1120,{4U,7U,0U}}, +{MOVE_1120,{5U,7U,0U}}, +{MOVE_1120,{6U,7U,0U}}, +{MOVE_1120,{7U,7U,0U}}, +{MOVE_1128,{0U,7U,0U}}, +{MOVE_1128,{1U,7U,0U}}, +{MOVE_1128,{2U,7U,0U}}, +{MOVE_1128,{3U,7U,0U}}, +{MOVE_1128,{4U,7U,0U}}, +{MOVE_1128,{5U,7U,0U}}, +{MOVE_1128,{6U,7U,0U}}, +{MOVE_1128,{7U,7U,0U}}, +{MOVE_1130,{0U,7U,0U}}, +{MOVE_1130,{1U,7U,0U}}, +{MOVE_1130,{2U,7U,0U}}, +{MOVE_1130,{3U,7U,0U}}, +{MOVE_1130,{4U,7U,0U}}, +{MOVE_1130,{5U,7U,0U}}, +{MOVE_1130,{6U,7U,0U}}, +{MOVE_1130,{7U,7U,0U}}, +{MOVE_1138,{0U,7U,0U}}, +{MOVE_1139,{0U,7U,0U}}, +{MOVE_113A,{0U,7U,0U}}, +{MOVE_113B,{0U,7U,0U}}, +{MOVE_113C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1140,{0U,7U,0U}}, +{MOVE_1140,{1U,7U,0U}}, +{MOVE_1140,{2U,7U,0U}}, +{MOVE_1140,{3U,7U,0U}}, +{MOVE_1140,{4U,7U,0U}}, +{MOVE_1140,{5U,7U,0U}}, +{MOVE_1140,{6U,7U,0U}}, +{MOVE_1140,{7U,7U,0U}}, +{MOVE_1148,{0U,7U,0U}}, +{MOVE_1148,{1U,7U,0U}}, +{MOVE_1148,{2U,7U,0U}}, +{MOVE_1148,{3U,7U,0U}}, +{MOVE_1148,{4U,7U,0U}}, +{MOVE_1148,{5U,7U,0U}}, +{MOVE_1148,{6U,7U,0U}}, +{MOVE_1148,{7U,7U,0U}}, +{MOVE_1150,{0U,7U,0U}}, +{MOVE_1150,{1U,7U,0U}}, +{MOVE_1150,{2U,7U,0U}}, +{MOVE_1150,{3U,7U,0U}}, +{MOVE_1150,{4U,7U,0U}}, +{MOVE_1150,{5U,7U,0U}}, +{MOVE_1150,{6U,7U,0U}}, +{MOVE_1150,{7U,7U,0U}}, +{MOVE_1158,{0U,7U,0U}}, +{MOVE_1158,{1U,7U,0U}}, +{MOVE_1158,{2U,7U,0U}}, +{MOVE_1158,{3U,7U,0U}}, +{MOVE_1158,{4U,7U,0U}}, +{MOVE_1158,{5U,7U,0U}}, +{MOVE_1158,{6U,7U,0U}}, +{MOVE_1158,{7U,7U,0U}}, +{MOVE_1160,{0U,7U,0U}}, +{MOVE_1160,{1U,7U,0U}}, +{MOVE_1160,{2U,7U,0U}}, +{MOVE_1160,{3U,7U,0U}}, +{MOVE_1160,{4U,7U,0U}}, +{MOVE_1160,{5U,7U,0U}}, +{MOVE_1160,{6U,7U,0U}}, +{MOVE_1160,{7U,7U,0U}}, +{MOVE_1168,{0U,7U,0U}}, +{MOVE_1168,{1U,7U,0U}}, +{MOVE_1168,{2U,7U,0U}}, +{MOVE_1168,{3U,7U,0U}}, +{MOVE_1168,{4U,7U,0U}}, +{MOVE_1168,{5U,7U,0U}}, +{MOVE_1168,{6U,7U,0U}}, +{MOVE_1168,{7U,7U,0U}}, +{MOVE_1170,{0U,7U,0U}}, +{MOVE_1170,{1U,7U,0U}}, +{MOVE_1170,{2U,7U,0U}}, +{MOVE_1170,{3U,7U,0U}}, +{MOVE_1170,{4U,7U,0U}}, +{MOVE_1170,{5U,7U,0U}}, +{MOVE_1170,{6U,7U,0U}}, +{MOVE_1170,{7U,7U,0U}}, +{MOVE_1178,{0U,7U,0U}}, +{MOVE_1179,{0U,7U,0U}}, +{MOVE_117A,{0U,7U,0U}}, +{MOVE_117B,{0U,7U,0U}}, +{MOVE_117C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_1180,{0U,7U,0U}}, +{MOVE_1180,{1U,7U,0U}}, +{MOVE_1180,{2U,7U,0U}}, +{MOVE_1180,{3U,7U,0U}}, +{MOVE_1180,{4U,7U,0U}}, +{MOVE_1180,{5U,7U,0U}}, +{MOVE_1180,{6U,7U,0U}}, +{MOVE_1180,{7U,7U,0U}}, +{MOVE_1188,{0U,7U,0U}}, +{MOVE_1188,{1U,7U,0U}}, +{MOVE_1188,{2U,7U,0U}}, +{MOVE_1188,{3U,7U,0U}}, +{MOVE_1188,{4U,7U,0U}}, +{MOVE_1188,{5U,7U,0U}}, +{MOVE_1188,{6U,7U,0U}}, +{MOVE_1188,{7U,7U,0U}}, +{MOVE_1190,{0U,7U,0U}}, +{MOVE_1190,{1U,7U,0U}}, +{MOVE_1190,{2U,7U,0U}}, +{MOVE_1190,{3U,7U,0U}}, +{MOVE_1190,{4U,7U,0U}}, +{MOVE_1190,{5U,7U,0U}}, +{MOVE_1190,{6U,7U,0U}}, +{MOVE_1190,{7U,7U,0U}}, +{MOVE_1198,{0U,7U,0U}}, +{MOVE_1198,{1U,7U,0U}}, +{MOVE_1198,{2U,7U,0U}}, +{MOVE_1198,{3U,7U,0U}}, +{MOVE_1198,{4U,7U,0U}}, +{MOVE_1198,{5U,7U,0U}}, +{MOVE_1198,{6U,7U,0U}}, +{MOVE_1198,{7U,7U,0U}}, +{MOVE_11A0,{0U,7U,0U}}, +{MOVE_11A0,{1U,7U,0U}}, +{MOVE_11A0,{2U,7U,0U}}, +{MOVE_11A0,{3U,7U,0U}}, +{MOVE_11A0,{4U,7U,0U}}, +{MOVE_11A0,{5U,7U,0U}}, +{MOVE_11A0,{6U,7U,0U}}, +{MOVE_11A0,{7U,7U,0U}}, +{MOVE_11A8,{0U,7U,0U}}, +{MOVE_11A8,{1U,7U,0U}}, +{MOVE_11A8,{2U,7U,0U}}, +{MOVE_11A8,{3U,7U,0U}}, +{MOVE_11A8,{4U,7U,0U}}, +{MOVE_11A8,{5U,7U,0U}}, +{MOVE_11A8,{6U,7U,0U}}, +{MOVE_11A8,{7U,7U,0U}}, +{MOVE_11B0,{0U,7U,0U}}, +{MOVE_11B0,{1U,7U,0U}}, +{MOVE_11B0,{2U,7U,0U}}, +{MOVE_11B0,{3U,7U,0U}}, +{MOVE_11B0,{4U,7U,0U}}, +{MOVE_11B0,{5U,7U,0U}}, +{MOVE_11B0,{6U,7U,0U}}, +{MOVE_11B0,{7U,7U,0U}}, +{MOVE_11B8,{0U,7U,0U}}, +{MOVE_11B9,{0U,7U,0U}}, +{MOVE_11BA,{0U,7U,0U}}, +{MOVE_11BB,{0U,7U,0U}}, +{MOVE_11BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2000,{0U,0U,0U}}, +{MOVE_2000,{1U,0U,0U}}, +{MOVE_2000,{2U,0U,0U}}, +{MOVE_2000,{3U,0U,0U}}, +{MOVE_2000,{4U,0U,0U}}, +{MOVE_2000,{5U,0U,0U}}, +{MOVE_2000,{6U,0U,0U}}, +{MOVE_2000,{7U,0U,0U}}, +{MOVE_2008,{0U,0U,0U}}, +{MOVE_2008,{1U,0U,0U}}, +{MOVE_2008,{2U,0U,0U}}, +{MOVE_2008,{3U,0U,0U}}, +{MOVE_2008,{4U,0U,0U}}, +{MOVE_2008,{5U,0U,0U}}, +{MOVE_2008,{6U,0U,0U}}, +{MOVE_2008,{7U,0U,0U}}, +{MOVE_2010,{0U,0U,0U}}, +{MOVE_2010,{1U,0U,0U}}, +{MOVE_2010,{2U,0U,0U}}, +{MOVE_2010,{3U,0U,0U}}, +{MOVE_2010,{4U,0U,0U}}, +{MOVE_2010,{5U,0U,0U}}, +{MOVE_2010,{6U,0U,0U}}, +{MOVE_2010,{7U,0U,0U}}, +{MOVE_2018,{0U,0U,0U}}, +{MOVE_2018,{1U,0U,0U}}, +{MOVE_2018,{2U,0U,0U}}, +{MOVE_2018,{3U,0U,0U}}, +{MOVE_2018,{4U,0U,0U}}, +{MOVE_2018,{5U,0U,0U}}, +{MOVE_2018,{6U,0U,0U}}, +{MOVE_2018,{7U,0U,0U}}, +{MOVE_2020,{0U,0U,0U}}, +{MOVE_2020,{1U,0U,0U}}, +{MOVE_2020,{2U,0U,0U}}, +{MOVE_2020,{3U,0U,0U}}, +{MOVE_2020,{4U,0U,0U}}, +{MOVE_2020,{5U,0U,0U}}, +{MOVE_2020,{6U,0U,0U}}, +{MOVE_2020,{7U,0U,0U}}, +{MOVE_2028,{0U,0U,0U}}, +{MOVE_2028,{1U,0U,0U}}, +{MOVE_2028,{2U,0U,0U}}, +{MOVE_2028,{3U,0U,0U}}, +{MOVE_2028,{4U,0U,0U}}, +{MOVE_2028,{5U,0U,0U}}, +{MOVE_2028,{6U,0U,0U}}, +{MOVE_2028,{7U,0U,0U}}, +{MOVE_2030,{0U,0U,0U}}, +{MOVE_2030,{1U,0U,0U}}, +{MOVE_2030,{2U,0U,0U}}, +{MOVE_2030,{3U,0U,0U}}, +{MOVE_2030,{4U,0U,0U}}, +{MOVE_2030,{5U,0U,0U}}, +{MOVE_2030,{6U,0U,0U}}, +{MOVE_2030,{7U,0U,0U}}, +{MOVE_2038,{0U,0U,0U}}, +{MOVE_2039,{0U,0U,0U}}, +{MOVE_203A,{0U,0U,0U}}, +{MOVE_203B,{0U,0U,0U}}, +{MOVE_203C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_2040,{0U,0U,0U}}, +{MOVEA_2040,{1U,0U,0U}}, +{MOVEA_2040,{2U,0U,0U}}, +{MOVEA_2040,{3U,0U,0U}}, +{MOVEA_2040,{4U,0U,0U}}, +{MOVEA_2040,{5U,0U,0U}}, +{MOVEA_2040,{6U,0U,0U}}, +{MOVEA_2040,{7U,0U,0U}}, +{MOVEA_2048,{0U,0U,0U}}, +{MOVEA_2048,{1U,0U,0U}}, +{MOVEA_2048,{2U,0U,0U}}, +{MOVEA_2048,{3U,0U,0U}}, +{MOVEA_2048,{4U,0U,0U}}, +{MOVEA_2048,{5U,0U,0U}}, +{MOVEA_2048,{6U,0U,0U}}, +{MOVEA_2048,{7U,0U,0U}}, +{MOVEA_2050,{0U,0U,0U}}, +{MOVEA_2050,{1U,0U,0U}}, +{MOVEA_2050,{2U,0U,0U}}, +{MOVEA_2050,{3U,0U,0U}}, +{MOVEA_2050,{4U,0U,0U}}, +{MOVEA_2050,{5U,0U,0U}}, +{MOVEA_2050,{6U,0U,0U}}, +{MOVEA_2050,{7U,0U,0U}}, +{MOVEA_2058,{0U,0U,0U}}, +{MOVEA_2058,{1U,0U,0U}}, +{MOVEA_2058,{2U,0U,0U}}, +{MOVEA_2058,{3U,0U,0U}}, +{MOVEA_2058,{4U,0U,0U}}, +{MOVEA_2058,{5U,0U,0U}}, +{MOVEA_2058,{6U,0U,0U}}, +{MOVEA_2058,{7U,0U,0U}}, +{MOVEA_2060,{0U,0U,0U}}, +{MOVEA_2060,{1U,0U,0U}}, +{MOVEA_2060,{2U,0U,0U}}, +{MOVEA_2060,{3U,0U,0U}}, +{MOVEA_2060,{4U,0U,0U}}, +{MOVEA_2060,{5U,0U,0U}}, +{MOVEA_2060,{6U,0U,0U}}, +{MOVEA_2060,{7U,0U,0U}}, +{MOVEA_2068,{0U,0U,0U}}, +{MOVEA_2068,{1U,0U,0U}}, +{MOVEA_2068,{2U,0U,0U}}, +{MOVEA_2068,{3U,0U,0U}}, +{MOVEA_2068,{4U,0U,0U}}, +{MOVEA_2068,{5U,0U,0U}}, +{MOVEA_2068,{6U,0U,0U}}, +{MOVEA_2068,{7U,0U,0U}}, +{MOVEA_2070,{0U,0U,0U}}, +{MOVEA_2070,{1U,0U,0U}}, +{MOVEA_2070,{2U,0U,0U}}, +{MOVEA_2070,{3U,0U,0U}}, +{MOVEA_2070,{4U,0U,0U}}, +{MOVEA_2070,{5U,0U,0U}}, +{MOVEA_2070,{6U,0U,0U}}, +{MOVEA_2070,{7U,0U,0U}}, +{MOVEA_2078,{0U,0U,0U}}, +{MOVEA_2079,{0U,0U,0U}}, +{MOVEA_207A,{0U,0U,0U}}, +{MOVEA_207B,{0U,0U,0U}}, +{MOVEA_207C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2080,{0U,0U,0U}}, +{MOVE_2080,{1U,0U,0U}}, +{MOVE_2080,{2U,0U,0U}}, +{MOVE_2080,{3U,0U,0U}}, +{MOVE_2080,{4U,0U,0U}}, +{MOVE_2080,{5U,0U,0U}}, +{MOVE_2080,{6U,0U,0U}}, +{MOVE_2080,{7U,0U,0U}}, +{MOVE_2088,{0U,0U,0U}}, +{MOVE_2088,{1U,0U,0U}}, +{MOVE_2088,{2U,0U,0U}}, +{MOVE_2088,{3U,0U,0U}}, +{MOVE_2088,{4U,0U,0U}}, +{MOVE_2088,{5U,0U,0U}}, +{MOVE_2088,{6U,0U,0U}}, +{MOVE_2088,{7U,0U,0U}}, +{MOVE_2090,{0U,0U,0U}}, +{MOVE_2090,{1U,0U,0U}}, +{MOVE_2090,{2U,0U,0U}}, +{MOVE_2090,{3U,0U,0U}}, +{MOVE_2090,{4U,0U,0U}}, +{MOVE_2090,{5U,0U,0U}}, +{MOVE_2090,{6U,0U,0U}}, +{MOVE_2090,{7U,0U,0U}}, +{MOVE_2098,{0U,0U,0U}}, +{MOVE_2098,{1U,0U,0U}}, +{MOVE_2098,{2U,0U,0U}}, +{MOVE_2098,{3U,0U,0U}}, +{MOVE_2098,{4U,0U,0U}}, +{MOVE_2098,{5U,0U,0U}}, +{MOVE_2098,{6U,0U,0U}}, +{MOVE_2098,{7U,0U,0U}}, +{MOVE_20A0,{0U,0U,0U}}, +{MOVE_20A0,{1U,0U,0U}}, +{MOVE_20A0,{2U,0U,0U}}, +{MOVE_20A0,{3U,0U,0U}}, +{MOVE_20A0,{4U,0U,0U}}, +{MOVE_20A0,{5U,0U,0U}}, +{MOVE_20A0,{6U,0U,0U}}, +{MOVE_20A0,{7U,0U,0U}}, +{MOVE_20A8,{0U,0U,0U}}, +{MOVE_20A8,{1U,0U,0U}}, +{MOVE_20A8,{2U,0U,0U}}, +{MOVE_20A8,{3U,0U,0U}}, +{MOVE_20A8,{4U,0U,0U}}, +{MOVE_20A8,{5U,0U,0U}}, +{MOVE_20A8,{6U,0U,0U}}, +{MOVE_20A8,{7U,0U,0U}}, +{MOVE_20B0,{0U,0U,0U}}, +{MOVE_20B0,{1U,0U,0U}}, +{MOVE_20B0,{2U,0U,0U}}, +{MOVE_20B0,{3U,0U,0U}}, +{MOVE_20B0,{4U,0U,0U}}, +{MOVE_20B0,{5U,0U,0U}}, +{MOVE_20B0,{6U,0U,0U}}, +{MOVE_20B0,{7U,0U,0U}}, +{MOVE_20B8,{0U,0U,0U}}, +{MOVE_20B9,{0U,0U,0U}}, +{MOVE_20BA,{0U,0U,0U}}, +{MOVE_20BB,{0U,0U,0U}}, +{MOVE_20BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_20C0,{0U,0U,0U}}, +{MOVE_20C0,{1U,0U,0U}}, +{MOVE_20C0,{2U,0U,0U}}, +{MOVE_20C0,{3U,0U,0U}}, +{MOVE_20C0,{4U,0U,0U}}, +{MOVE_20C0,{5U,0U,0U}}, +{MOVE_20C0,{6U,0U,0U}}, +{MOVE_20C0,{7U,0U,0U}}, +{MOVE_20C8,{0U,0U,0U}}, +{MOVE_20C8,{1U,0U,0U}}, +{MOVE_20C8,{2U,0U,0U}}, +{MOVE_20C8,{3U,0U,0U}}, +{MOVE_20C8,{4U,0U,0U}}, +{MOVE_20C8,{5U,0U,0U}}, +{MOVE_20C8,{6U,0U,0U}}, +{MOVE_20C8,{7U,0U,0U}}, +{MOVE_20D0,{0U,0U,0U}}, +{MOVE_20D0,{1U,0U,0U}}, +{MOVE_20D0,{2U,0U,0U}}, +{MOVE_20D0,{3U,0U,0U}}, +{MOVE_20D0,{4U,0U,0U}}, +{MOVE_20D0,{5U,0U,0U}}, +{MOVE_20D0,{6U,0U,0U}}, +{MOVE_20D0,{7U,0U,0U}}, +{MOVE_20D8,{0U,0U,0U}}, +{MOVE_20D8,{1U,0U,0U}}, +{MOVE_20D8,{2U,0U,0U}}, +{MOVE_20D8,{3U,0U,0U}}, +{MOVE_20D8,{4U,0U,0U}}, +{MOVE_20D8,{5U,0U,0U}}, +{MOVE_20D8,{6U,0U,0U}}, +{MOVE_20D8,{7U,0U,0U}}, +{MOVE_20E0,{0U,0U,0U}}, +{MOVE_20E0,{1U,0U,0U}}, +{MOVE_20E0,{2U,0U,0U}}, +{MOVE_20E0,{3U,0U,0U}}, +{MOVE_20E0,{4U,0U,0U}}, +{MOVE_20E0,{5U,0U,0U}}, +{MOVE_20E0,{6U,0U,0U}}, +{MOVE_20E0,{7U,0U,0U}}, +{MOVE_20E8,{0U,0U,0U}}, +{MOVE_20E8,{1U,0U,0U}}, +{MOVE_20E8,{2U,0U,0U}}, +{MOVE_20E8,{3U,0U,0U}}, +{MOVE_20E8,{4U,0U,0U}}, +{MOVE_20E8,{5U,0U,0U}}, +{MOVE_20E8,{6U,0U,0U}}, +{MOVE_20E8,{7U,0U,0U}}, +{MOVE_20F0,{0U,0U,0U}}, +{MOVE_20F0,{1U,0U,0U}}, +{MOVE_20F0,{2U,0U,0U}}, +{MOVE_20F0,{3U,0U,0U}}, +{MOVE_20F0,{4U,0U,0U}}, +{MOVE_20F0,{5U,0U,0U}}, +{MOVE_20F0,{6U,0U,0U}}, +{MOVE_20F0,{7U,0U,0U}}, +{MOVE_20F8,{0U,0U,0U}}, +{MOVE_20F9,{0U,0U,0U}}, +{MOVE_20FA,{0U,0U,0U}}, +{MOVE_20FB,{0U,0U,0U}}, +{MOVE_20FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2100,{0U,0U,0U}}, +{MOVE_2100,{1U,0U,0U}}, +{MOVE_2100,{2U,0U,0U}}, +{MOVE_2100,{3U,0U,0U}}, +{MOVE_2100,{4U,0U,0U}}, +{MOVE_2100,{5U,0U,0U}}, +{MOVE_2100,{6U,0U,0U}}, +{MOVE_2100,{7U,0U,0U}}, +{MOVE_2108,{0U,0U,0U}}, +{MOVE_2108,{1U,0U,0U}}, +{MOVE_2108,{2U,0U,0U}}, +{MOVE_2108,{3U,0U,0U}}, +{MOVE_2108,{4U,0U,0U}}, +{MOVE_2108,{5U,0U,0U}}, +{MOVE_2108,{6U,0U,0U}}, +{MOVE_2108,{7U,0U,0U}}, +{MOVE_2110,{0U,0U,0U}}, +{MOVE_2110,{1U,0U,0U}}, +{MOVE_2110,{2U,0U,0U}}, +{MOVE_2110,{3U,0U,0U}}, +{MOVE_2110,{4U,0U,0U}}, +{MOVE_2110,{5U,0U,0U}}, +{MOVE_2110,{6U,0U,0U}}, +{MOVE_2110,{7U,0U,0U}}, +{MOVE_2118,{0U,0U,0U}}, +{MOVE_2118,{1U,0U,0U}}, +{MOVE_2118,{2U,0U,0U}}, +{MOVE_2118,{3U,0U,0U}}, +{MOVE_2118,{4U,0U,0U}}, +{MOVE_2118,{5U,0U,0U}}, +{MOVE_2118,{6U,0U,0U}}, +{MOVE_2118,{7U,0U,0U}}, +{MOVE_2120,{0U,0U,0U}}, +{MOVE_2120,{1U,0U,0U}}, +{MOVE_2120,{2U,0U,0U}}, +{MOVE_2120,{3U,0U,0U}}, +{MOVE_2120,{4U,0U,0U}}, +{MOVE_2120,{5U,0U,0U}}, +{MOVE_2120,{6U,0U,0U}}, +{MOVE_2120,{7U,0U,0U}}, +{MOVE_2128,{0U,0U,0U}}, +{MOVE_2128,{1U,0U,0U}}, +{MOVE_2128,{2U,0U,0U}}, +{MOVE_2128,{3U,0U,0U}}, +{MOVE_2128,{4U,0U,0U}}, +{MOVE_2128,{5U,0U,0U}}, +{MOVE_2128,{6U,0U,0U}}, +{MOVE_2128,{7U,0U,0U}}, +{MOVE_2130,{0U,0U,0U}}, +{MOVE_2130,{1U,0U,0U}}, +{MOVE_2130,{2U,0U,0U}}, +{MOVE_2130,{3U,0U,0U}}, +{MOVE_2130,{4U,0U,0U}}, +{MOVE_2130,{5U,0U,0U}}, +{MOVE_2130,{6U,0U,0U}}, +{MOVE_2130,{7U,0U,0U}}, +{MOVE_2138,{0U,0U,0U}}, +{MOVE_2139,{0U,0U,0U}}, +{MOVE_213A,{0U,0U,0U}}, +{MOVE_213B,{0U,0U,0U}}, +{MOVE_213C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2140,{0U,0U,0U}}, +{MOVE_2140,{1U,0U,0U}}, +{MOVE_2140,{2U,0U,0U}}, +{MOVE_2140,{3U,0U,0U}}, +{MOVE_2140,{4U,0U,0U}}, +{MOVE_2140,{5U,0U,0U}}, +{MOVE_2140,{6U,0U,0U}}, +{MOVE_2140,{7U,0U,0U}}, +{MOVE_2148,{0U,0U,0U}}, +{MOVE_2148,{1U,0U,0U}}, +{MOVE_2148,{2U,0U,0U}}, +{MOVE_2148,{3U,0U,0U}}, +{MOVE_2148,{4U,0U,0U}}, +{MOVE_2148,{5U,0U,0U}}, +{MOVE_2148,{6U,0U,0U}}, +{MOVE_2148,{7U,0U,0U}}, +{MOVE_2150,{0U,0U,0U}}, +{MOVE_2150,{1U,0U,0U}}, +{MOVE_2150,{2U,0U,0U}}, +{MOVE_2150,{3U,0U,0U}}, +{MOVE_2150,{4U,0U,0U}}, +{MOVE_2150,{5U,0U,0U}}, +{MOVE_2150,{6U,0U,0U}}, +{MOVE_2150,{7U,0U,0U}}, +{MOVE_2158,{0U,0U,0U}}, +{MOVE_2158,{1U,0U,0U}}, +{MOVE_2158,{2U,0U,0U}}, +{MOVE_2158,{3U,0U,0U}}, +{MOVE_2158,{4U,0U,0U}}, +{MOVE_2158,{5U,0U,0U}}, +{MOVE_2158,{6U,0U,0U}}, +{MOVE_2158,{7U,0U,0U}}, +{MOVE_2160,{0U,0U,0U}}, +{MOVE_2160,{1U,0U,0U}}, +{MOVE_2160,{2U,0U,0U}}, +{MOVE_2160,{3U,0U,0U}}, +{MOVE_2160,{4U,0U,0U}}, +{MOVE_2160,{5U,0U,0U}}, +{MOVE_2160,{6U,0U,0U}}, +{MOVE_2160,{7U,0U,0U}}, +{MOVE_2168,{0U,0U,0U}}, +{MOVE_2168,{1U,0U,0U}}, +{MOVE_2168,{2U,0U,0U}}, +{MOVE_2168,{3U,0U,0U}}, +{MOVE_2168,{4U,0U,0U}}, +{MOVE_2168,{5U,0U,0U}}, +{MOVE_2168,{6U,0U,0U}}, +{MOVE_2168,{7U,0U,0U}}, +{MOVE_2170,{0U,0U,0U}}, +{MOVE_2170,{1U,0U,0U}}, +{MOVE_2170,{2U,0U,0U}}, +{MOVE_2170,{3U,0U,0U}}, +{MOVE_2170,{4U,0U,0U}}, +{MOVE_2170,{5U,0U,0U}}, +{MOVE_2170,{6U,0U,0U}}, +{MOVE_2170,{7U,0U,0U}}, +{MOVE_2178,{0U,0U,0U}}, +{MOVE_2179,{0U,0U,0U}}, +{MOVE_217A,{0U,0U,0U}}, +{MOVE_217B,{0U,0U,0U}}, +{MOVE_217C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2180,{0U,0U,0U}}, +{MOVE_2180,{1U,0U,0U}}, +{MOVE_2180,{2U,0U,0U}}, +{MOVE_2180,{3U,0U,0U}}, +{MOVE_2180,{4U,0U,0U}}, +{MOVE_2180,{5U,0U,0U}}, +{MOVE_2180,{6U,0U,0U}}, +{MOVE_2180,{7U,0U,0U}}, +{MOVE_2188,{0U,0U,0U}}, +{MOVE_2188,{1U,0U,0U}}, +{MOVE_2188,{2U,0U,0U}}, +{MOVE_2188,{3U,0U,0U}}, +{MOVE_2188,{4U,0U,0U}}, +{MOVE_2188,{5U,0U,0U}}, +{MOVE_2188,{6U,0U,0U}}, +{MOVE_2188,{7U,0U,0U}}, +{MOVE_2190,{0U,0U,0U}}, +{MOVE_2190,{1U,0U,0U}}, +{MOVE_2190,{2U,0U,0U}}, +{MOVE_2190,{3U,0U,0U}}, +{MOVE_2190,{4U,0U,0U}}, +{MOVE_2190,{5U,0U,0U}}, +{MOVE_2190,{6U,0U,0U}}, +{MOVE_2190,{7U,0U,0U}}, +{MOVE_2198,{0U,0U,0U}}, +{MOVE_2198,{1U,0U,0U}}, +{MOVE_2198,{2U,0U,0U}}, +{MOVE_2198,{3U,0U,0U}}, +{MOVE_2198,{4U,0U,0U}}, +{MOVE_2198,{5U,0U,0U}}, +{MOVE_2198,{6U,0U,0U}}, +{MOVE_2198,{7U,0U,0U}}, +{MOVE_21A0,{0U,0U,0U}}, +{MOVE_21A0,{1U,0U,0U}}, +{MOVE_21A0,{2U,0U,0U}}, +{MOVE_21A0,{3U,0U,0U}}, +{MOVE_21A0,{4U,0U,0U}}, +{MOVE_21A0,{5U,0U,0U}}, +{MOVE_21A0,{6U,0U,0U}}, +{MOVE_21A0,{7U,0U,0U}}, +{MOVE_21A8,{0U,0U,0U}}, +{MOVE_21A8,{1U,0U,0U}}, +{MOVE_21A8,{2U,0U,0U}}, +{MOVE_21A8,{3U,0U,0U}}, +{MOVE_21A8,{4U,0U,0U}}, +{MOVE_21A8,{5U,0U,0U}}, +{MOVE_21A8,{6U,0U,0U}}, +{MOVE_21A8,{7U,0U,0U}}, +{MOVE_21B0,{0U,0U,0U}}, +{MOVE_21B0,{1U,0U,0U}}, +{MOVE_21B0,{2U,0U,0U}}, +{MOVE_21B0,{3U,0U,0U}}, +{MOVE_21B0,{4U,0U,0U}}, +{MOVE_21B0,{5U,0U,0U}}, +{MOVE_21B0,{6U,0U,0U}}, +{MOVE_21B0,{7U,0U,0U}}, +{MOVE_21B8,{0U,0U,0U}}, +{MOVE_21B9,{0U,0U,0U}}, +{MOVE_21BA,{0U,0U,0U}}, +{MOVE_21BB,{0U,0U,0U}}, +{MOVE_21BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_21C0,{0U,0U,0U}}, +{MOVE_21C0,{1U,0U,0U}}, +{MOVE_21C0,{2U,0U,0U}}, +{MOVE_21C0,{3U,0U,0U}}, +{MOVE_21C0,{4U,0U,0U}}, +{MOVE_21C0,{5U,0U,0U}}, +{MOVE_21C0,{6U,0U,0U}}, +{MOVE_21C0,{7U,0U,0U}}, +{MOVE_21C8,{0U,0U,0U}}, +{MOVE_21C8,{1U,0U,0U}}, +{MOVE_21C8,{2U,0U,0U}}, +{MOVE_21C8,{3U,0U,0U}}, +{MOVE_21C8,{4U,0U,0U}}, +{MOVE_21C8,{5U,0U,0U}}, +{MOVE_21C8,{6U,0U,0U}}, +{MOVE_21C8,{7U,0U,0U}}, +{MOVE_21D0,{0U,0U,0U}}, +{MOVE_21D0,{1U,0U,0U}}, +{MOVE_21D0,{2U,0U,0U}}, +{MOVE_21D0,{3U,0U,0U}}, +{MOVE_21D0,{4U,0U,0U}}, +{MOVE_21D0,{5U,0U,0U}}, +{MOVE_21D0,{6U,0U,0U}}, +{MOVE_21D0,{7U,0U,0U}}, +{MOVE_21D8,{0U,0U,0U}}, +{MOVE_21D8,{1U,0U,0U}}, +{MOVE_21D8,{2U,0U,0U}}, +{MOVE_21D8,{3U,0U,0U}}, +{MOVE_21D8,{4U,0U,0U}}, +{MOVE_21D8,{5U,0U,0U}}, +{MOVE_21D8,{6U,0U,0U}}, +{MOVE_21D8,{7U,0U,0U}}, +{MOVE_21E0,{0U,0U,0U}}, +{MOVE_21E0,{1U,0U,0U}}, +{MOVE_21E0,{2U,0U,0U}}, +{MOVE_21E0,{3U,0U,0U}}, +{MOVE_21E0,{4U,0U,0U}}, +{MOVE_21E0,{5U,0U,0U}}, +{MOVE_21E0,{6U,0U,0U}}, +{MOVE_21E0,{7U,0U,0U}}, +{MOVE_21E8,{0U,0U,0U}}, +{MOVE_21E8,{1U,0U,0U}}, +{MOVE_21E8,{2U,0U,0U}}, +{MOVE_21E8,{3U,0U,0U}}, +{MOVE_21E8,{4U,0U,0U}}, +{MOVE_21E8,{5U,0U,0U}}, +{MOVE_21E8,{6U,0U,0U}}, +{MOVE_21E8,{7U,0U,0U}}, +{MOVE_21F0,{0U,0U,0U}}, +{MOVE_21F0,{1U,0U,0U}}, +{MOVE_21F0,{2U,0U,0U}}, +{MOVE_21F0,{3U,0U,0U}}, +{MOVE_21F0,{4U,0U,0U}}, +{MOVE_21F0,{5U,0U,0U}}, +{MOVE_21F0,{6U,0U,0U}}, +{MOVE_21F0,{7U,0U,0U}}, +{MOVE_21F8,{0U,0U,0U}}, +{MOVE_21F9,{0U,0U,0U}}, +{MOVE_21FA,{0U,0U,0U}}, +{MOVE_21FB,{0U,0U,0U}}, +{MOVE_21FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2000,{0U,1U,0U}}, +{MOVE_2000,{1U,1U,0U}}, +{MOVE_2000,{2U,1U,0U}}, +{MOVE_2000,{3U,1U,0U}}, +{MOVE_2000,{4U,1U,0U}}, +{MOVE_2000,{5U,1U,0U}}, +{MOVE_2000,{6U,1U,0U}}, +{MOVE_2000,{7U,1U,0U}}, +{MOVE_2008,{0U,1U,0U}}, +{MOVE_2008,{1U,1U,0U}}, +{MOVE_2008,{2U,1U,0U}}, +{MOVE_2008,{3U,1U,0U}}, +{MOVE_2008,{4U,1U,0U}}, +{MOVE_2008,{5U,1U,0U}}, +{MOVE_2008,{6U,1U,0U}}, +{MOVE_2008,{7U,1U,0U}}, +{MOVE_2010,{0U,1U,0U}}, +{MOVE_2010,{1U,1U,0U}}, +{MOVE_2010,{2U,1U,0U}}, +{MOVE_2010,{3U,1U,0U}}, +{MOVE_2010,{4U,1U,0U}}, +{MOVE_2010,{5U,1U,0U}}, +{MOVE_2010,{6U,1U,0U}}, +{MOVE_2010,{7U,1U,0U}}, +{MOVE_2018,{0U,1U,0U}}, +{MOVE_2018,{1U,1U,0U}}, +{MOVE_2018,{2U,1U,0U}}, +{MOVE_2018,{3U,1U,0U}}, +{MOVE_2018,{4U,1U,0U}}, +{MOVE_2018,{5U,1U,0U}}, +{MOVE_2018,{6U,1U,0U}}, +{MOVE_2018,{7U,1U,0U}}, +{MOVE_2020,{0U,1U,0U}}, +{MOVE_2020,{1U,1U,0U}}, +{MOVE_2020,{2U,1U,0U}}, +{MOVE_2020,{3U,1U,0U}}, +{MOVE_2020,{4U,1U,0U}}, +{MOVE_2020,{5U,1U,0U}}, +{MOVE_2020,{6U,1U,0U}}, +{MOVE_2020,{7U,1U,0U}}, +{MOVE_2028,{0U,1U,0U}}, +{MOVE_2028,{1U,1U,0U}}, +{MOVE_2028,{2U,1U,0U}}, +{MOVE_2028,{3U,1U,0U}}, +{MOVE_2028,{4U,1U,0U}}, +{MOVE_2028,{5U,1U,0U}}, +{MOVE_2028,{6U,1U,0U}}, +{MOVE_2028,{7U,1U,0U}}, +{MOVE_2030,{0U,1U,0U}}, +{MOVE_2030,{1U,1U,0U}}, +{MOVE_2030,{2U,1U,0U}}, +{MOVE_2030,{3U,1U,0U}}, +{MOVE_2030,{4U,1U,0U}}, +{MOVE_2030,{5U,1U,0U}}, +{MOVE_2030,{6U,1U,0U}}, +{MOVE_2030,{7U,1U,0U}}, +{MOVE_2038,{0U,1U,0U}}, +{MOVE_2039,{0U,1U,0U}}, +{MOVE_203A,{0U,1U,0U}}, +{MOVE_203B,{0U,1U,0U}}, +{MOVE_203C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_2040,{0U,1U,0U}}, +{MOVEA_2040,{1U,1U,0U}}, +{MOVEA_2040,{2U,1U,0U}}, +{MOVEA_2040,{3U,1U,0U}}, +{MOVEA_2040,{4U,1U,0U}}, +{MOVEA_2040,{5U,1U,0U}}, +{MOVEA_2040,{6U,1U,0U}}, +{MOVEA_2040,{7U,1U,0U}}, +{MOVEA_2048,{0U,1U,0U}}, +{MOVEA_2048,{1U,1U,0U}}, +{MOVEA_2048,{2U,1U,0U}}, +{MOVEA_2048,{3U,1U,0U}}, +{MOVEA_2048,{4U,1U,0U}}, +{MOVEA_2048,{5U,1U,0U}}, +{MOVEA_2048,{6U,1U,0U}}, +{MOVEA_2048,{7U,1U,0U}}, +{MOVEA_2050,{0U,1U,0U}}, +{MOVEA_2050,{1U,1U,0U}}, +{MOVEA_2050,{2U,1U,0U}}, +{MOVEA_2050,{3U,1U,0U}}, +{MOVEA_2050,{4U,1U,0U}}, +{MOVEA_2050,{5U,1U,0U}}, +{MOVEA_2050,{6U,1U,0U}}, +{MOVEA_2050,{7U,1U,0U}}, +{MOVEA_2058,{0U,1U,0U}}, +{MOVEA_2058,{1U,1U,0U}}, +{MOVEA_2058,{2U,1U,0U}}, +{MOVEA_2058,{3U,1U,0U}}, +{MOVEA_2058,{4U,1U,0U}}, +{MOVEA_2058,{5U,1U,0U}}, +{MOVEA_2058,{6U,1U,0U}}, +{MOVEA_2058,{7U,1U,0U}}, +{MOVEA_2060,{0U,1U,0U}}, +{MOVEA_2060,{1U,1U,0U}}, +{MOVEA_2060,{2U,1U,0U}}, +{MOVEA_2060,{3U,1U,0U}}, +{MOVEA_2060,{4U,1U,0U}}, +{MOVEA_2060,{5U,1U,0U}}, +{MOVEA_2060,{6U,1U,0U}}, +{MOVEA_2060,{7U,1U,0U}}, +{MOVEA_2068,{0U,1U,0U}}, +{MOVEA_2068,{1U,1U,0U}}, +{MOVEA_2068,{2U,1U,0U}}, +{MOVEA_2068,{3U,1U,0U}}, +{MOVEA_2068,{4U,1U,0U}}, +{MOVEA_2068,{5U,1U,0U}}, +{MOVEA_2068,{6U,1U,0U}}, +{MOVEA_2068,{7U,1U,0U}}, +{MOVEA_2070,{0U,1U,0U}}, +{MOVEA_2070,{1U,1U,0U}}, +{MOVEA_2070,{2U,1U,0U}}, +{MOVEA_2070,{3U,1U,0U}}, +{MOVEA_2070,{4U,1U,0U}}, +{MOVEA_2070,{5U,1U,0U}}, +{MOVEA_2070,{6U,1U,0U}}, +{MOVEA_2070,{7U,1U,0U}}, +{MOVEA_2078,{0U,1U,0U}}, +{MOVEA_2079,{0U,1U,0U}}, +{MOVEA_207A,{0U,1U,0U}}, +{MOVEA_207B,{0U,1U,0U}}, +{MOVEA_207C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2080,{0U,1U,0U}}, +{MOVE_2080,{1U,1U,0U}}, +{MOVE_2080,{2U,1U,0U}}, +{MOVE_2080,{3U,1U,0U}}, +{MOVE_2080,{4U,1U,0U}}, +{MOVE_2080,{5U,1U,0U}}, +{MOVE_2080,{6U,1U,0U}}, +{MOVE_2080,{7U,1U,0U}}, +{MOVE_2088,{0U,1U,0U}}, +{MOVE_2088,{1U,1U,0U}}, +{MOVE_2088,{2U,1U,0U}}, +{MOVE_2088,{3U,1U,0U}}, +{MOVE_2088,{4U,1U,0U}}, +{MOVE_2088,{5U,1U,0U}}, +{MOVE_2088,{6U,1U,0U}}, +{MOVE_2088,{7U,1U,0U}}, +{MOVE_2090,{0U,1U,0U}}, +{MOVE_2090,{1U,1U,0U}}, +{MOVE_2090,{2U,1U,0U}}, +{MOVE_2090,{3U,1U,0U}}, +{MOVE_2090,{4U,1U,0U}}, +{MOVE_2090,{5U,1U,0U}}, +{MOVE_2090,{6U,1U,0U}}, +{MOVE_2090,{7U,1U,0U}}, +{MOVE_2098,{0U,1U,0U}}, +{MOVE_2098,{1U,1U,0U}}, +{MOVE_2098,{2U,1U,0U}}, +{MOVE_2098,{3U,1U,0U}}, +{MOVE_2098,{4U,1U,0U}}, +{MOVE_2098,{5U,1U,0U}}, +{MOVE_2098,{6U,1U,0U}}, +{MOVE_2098,{7U,1U,0U}}, +{MOVE_20A0,{0U,1U,0U}}, +{MOVE_20A0,{1U,1U,0U}}, +{MOVE_20A0,{2U,1U,0U}}, +{MOVE_20A0,{3U,1U,0U}}, +{MOVE_20A0,{4U,1U,0U}}, +{MOVE_20A0,{5U,1U,0U}}, +{MOVE_20A0,{6U,1U,0U}}, +{MOVE_20A0,{7U,1U,0U}}, +{MOVE_20A8,{0U,1U,0U}}, +{MOVE_20A8,{1U,1U,0U}}, +{MOVE_20A8,{2U,1U,0U}}, +{MOVE_20A8,{3U,1U,0U}}, +{MOVE_20A8,{4U,1U,0U}}, +{MOVE_20A8,{5U,1U,0U}}, +{MOVE_20A8,{6U,1U,0U}}, +{MOVE_20A8,{7U,1U,0U}}, +{MOVE_20B0,{0U,1U,0U}}, +{MOVE_20B0,{1U,1U,0U}}, +{MOVE_20B0,{2U,1U,0U}}, +{MOVE_20B0,{3U,1U,0U}}, +{MOVE_20B0,{4U,1U,0U}}, +{MOVE_20B0,{5U,1U,0U}}, +{MOVE_20B0,{6U,1U,0U}}, +{MOVE_20B0,{7U,1U,0U}}, +{MOVE_20B8,{0U,1U,0U}}, +{MOVE_20B9,{0U,1U,0U}}, +{MOVE_20BA,{0U,1U,0U}}, +{MOVE_20BB,{0U,1U,0U}}, +{MOVE_20BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_20C0,{0U,1U,0U}}, +{MOVE_20C0,{1U,1U,0U}}, +{MOVE_20C0,{2U,1U,0U}}, +{MOVE_20C0,{3U,1U,0U}}, +{MOVE_20C0,{4U,1U,0U}}, +{MOVE_20C0,{5U,1U,0U}}, +{MOVE_20C0,{6U,1U,0U}}, +{MOVE_20C0,{7U,1U,0U}}, +{MOVE_20C8,{0U,1U,0U}}, +{MOVE_20C8,{1U,1U,0U}}, +{MOVE_20C8,{2U,1U,0U}}, +{MOVE_20C8,{3U,1U,0U}}, +{MOVE_20C8,{4U,1U,0U}}, +{MOVE_20C8,{5U,1U,0U}}, +{MOVE_20C8,{6U,1U,0U}}, +{MOVE_20C8,{7U,1U,0U}}, +{MOVE_20D0,{0U,1U,0U}}, +{MOVE_20D0,{1U,1U,0U}}, +{MOVE_20D0,{2U,1U,0U}}, +{MOVE_20D0,{3U,1U,0U}}, +{MOVE_20D0,{4U,1U,0U}}, +{MOVE_20D0,{5U,1U,0U}}, +{MOVE_20D0,{6U,1U,0U}}, +{MOVE_20D0,{7U,1U,0U}}, +{MOVE_20D8,{0U,1U,0U}}, +{MOVE_20D8,{1U,1U,0U}}, +{MOVE_20D8,{2U,1U,0U}}, +{MOVE_20D8,{3U,1U,0U}}, +{MOVE_20D8,{4U,1U,0U}}, +{MOVE_20D8,{5U,1U,0U}}, +{MOVE_20D8,{6U,1U,0U}}, +{MOVE_20D8,{7U,1U,0U}}, +{MOVE_20E0,{0U,1U,0U}}, +{MOVE_20E0,{1U,1U,0U}}, +{MOVE_20E0,{2U,1U,0U}}, +{MOVE_20E0,{3U,1U,0U}}, +{MOVE_20E0,{4U,1U,0U}}, +{MOVE_20E0,{5U,1U,0U}}, +{MOVE_20E0,{6U,1U,0U}}, +{MOVE_20E0,{7U,1U,0U}}, +{MOVE_20E8,{0U,1U,0U}}, +{MOVE_20E8,{1U,1U,0U}}, +{MOVE_20E8,{2U,1U,0U}}, +{MOVE_20E8,{3U,1U,0U}}, +{MOVE_20E8,{4U,1U,0U}}, +{MOVE_20E8,{5U,1U,0U}}, +{MOVE_20E8,{6U,1U,0U}}, +{MOVE_20E8,{7U,1U,0U}}, +{MOVE_20F0,{0U,1U,0U}}, +{MOVE_20F0,{1U,1U,0U}}, +{MOVE_20F0,{2U,1U,0U}}, +{MOVE_20F0,{3U,1U,0U}}, +{MOVE_20F0,{4U,1U,0U}}, +{MOVE_20F0,{5U,1U,0U}}, +{MOVE_20F0,{6U,1U,0U}}, +{MOVE_20F0,{7U,1U,0U}}, +{MOVE_20F8,{0U,1U,0U}}, +{MOVE_20F9,{0U,1U,0U}}, +{MOVE_20FA,{0U,1U,0U}}, +{MOVE_20FB,{0U,1U,0U}}, +{MOVE_20FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2100,{0U,1U,0U}}, +{MOVE_2100,{1U,1U,0U}}, +{MOVE_2100,{2U,1U,0U}}, +{MOVE_2100,{3U,1U,0U}}, +{MOVE_2100,{4U,1U,0U}}, +{MOVE_2100,{5U,1U,0U}}, +{MOVE_2100,{6U,1U,0U}}, +{MOVE_2100,{7U,1U,0U}}, +{MOVE_2108,{0U,1U,0U}}, +{MOVE_2108,{1U,1U,0U}}, +{MOVE_2108,{2U,1U,0U}}, +{MOVE_2108,{3U,1U,0U}}, +{MOVE_2108,{4U,1U,0U}}, +{MOVE_2108,{5U,1U,0U}}, +{MOVE_2108,{6U,1U,0U}}, +{MOVE_2108,{7U,1U,0U}}, +{MOVE_2110,{0U,1U,0U}}, +{MOVE_2110,{1U,1U,0U}}, +{MOVE_2110,{2U,1U,0U}}, +{MOVE_2110,{3U,1U,0U}}, +{MOVE_2110,{4U,1U,0U}}, +{MOVE_2110,{5U,1U,0U}}, +{MOVE_2110,{6U,1U,0U}}, +{MOVE_2110,{7U,1U,0U}}, +{MOVE_2118,{0U,1U,0U}}, +{MOVE_2118,{1U,1U,0U}}, +{MOVE_2118,{2U,1U,0U}}, +{MOVE_2118,{3U,1U,0U}}, +{MOVE_2118,{4U,1U,0U}}, +{MOVE_2118,{5U,1U,0U}}, +{MOVE_2118,{6U,1U,0U}}, +{MOVE_2118,{7U,1U,0U}}, +{MOVE_2120,{0U,1U,0U}}, +{MOVE_2120,{1U,1U,0U}}, +{MOVE_2120,{2U,1U,0U}}, +{MOVE_2120,{3U,1U,0U}}, +{MOVE_2120,{4U,1U,0U}}, +{MOVE_2120,{5U,1U,0U}}, +{MOVE_2120,{6U,1U,0U}}, +{MOVE_2120,{7U,1U,0U}}, +{MOVE_2128,{0U,1U,0U}}, +{MOVE_2128,{1U,1U,0U}}, +{MOVE_2128,{2U,1U,0U}}, +{MOVE_2128,{3U,1U,0U}}, +{MOVE_2128,{4U,1U,0U}}, +{MOVE_2128,{5U,1U,0U}}, +{MOVE_2128,{6U,1U,0U}}, +{MOVE_2128,{7U,1U,0U}}, +{MOVE_2130,{0U,1U,0U}}, +{MOVE_2130,{1U,1U,0U}}, +{MOVE_2130,{2U,1U,0U}}, +{MOVE_2130,{3U,1U,0U}}, +{MOVE_2130,{4U,1U,0U}}, +{MOVE_2130,{5U,1U,0U}}, +{MOVE_2130,{6U,1U,0U}}, +{MOVE_2130,{7U,1U,0U}}, +{MOVE_2138,{0U,1U,0U}}, +{MOVE_2139,{0U,1U,0U}}, +{MOVE_213A,{0U,1U,0U}}, +{MOVE_213B,{0U,1U,0U}}, +{MOVE_213C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2140,{0U,1U,0U}}, +{MOVE_2140,{1U,1U,0U}}, +{MOVE_2140,{2U,1U,0U}}, +{MOVE_2140,{3U,1U,0U}}, +{MOVE_2140,{4U,1U,0U}}, +{MOVE_2140,{5U,1U,0U}}, +{MOVE_2140,{6U,1U,0U}}, +{MOVE_2140,{7U,1U,0U}}, +{MOVE_2148,{0U,1U,0U}}, +{MOVE_2148,{1U,1U,0U}}, +{MOVE_2148,{2U,1U,0U}}, +{MOVE_2148,{3U,1U,0U}}, +{MOVE_2148,{4U,1U,0U}}, +{MOVE_2148,{5U,1U,0U}}, +{MOVE_2148,{6U,1U,0U}}, +{MOVE_2148,{7U,1U,0U}}, +{MOVE_2150,{0U,1U,0U}}, +{MOVE_2150,{1U,1U,0U}}, +{MOVE_2150,{2U,1U,0U}}, +{MOVE_2150,{3U,1U,0U}}, +{MOVE_2150,{4U,1U,0U}}, +{MOVE_2150,{5U,1U,0U}}, +{MOVE_2150,{6U,1U,0U}}, +{MOVE_2150,{7U,1U,0U}}, +{MOVE_2158,{0U,1U,0U}}, +{MOVE_2158,{1U,1U,0U}}, +{MOVE_2158,{2U,1U,0U}}, +{MOVE_2158,{3U,1U,0U}}, +{MOVE_2158,{4U,1U,0U}}, +{MOVE_2158,{5U,1U,0U}}, +{MOVE_2158,{6U,1U,0U}}, +{MOVE_2158,{7U,1U,0U}}, +{MOVE_2160,{0U,1U,0U}}, +{MOVE_2160,{1U,1U,0U}}, +{MOVE_2160,{2U,1U,0U}}, +{MOVE_2160,{3U,1U,0U}}, +{MOVE_2160,{4U,1U,0U}}, +{MOVE_2160,{5U,1U,0U}}, +{MOVE_2160,{6U,1U,0U}}, +{MOVE_2160,{7U,1U,0U}}, +{MOVE_2168,{0U,1U,0U}}, +{MOVE_2168,{1U,1U,0U}}, +{MOVE_2168,{2U,1U,0U}}, +{MOVE_2168,{3U,1U,0U}}, +{MOVE_2168,{4U,1U,0U}}, +{MOVE_2168,{5U,1U,0U}}, +{MOVE_2168,{6U,1U,0U}}, +{MOVE_2168,{7U,1U,0U}}, +{MOVE_2170,{0U,1U,0U}}, +{MOVE_2170,{1U,1U,0U}}, +{MOVE_2170,{2U,1U,0U}}, +{MOVE_2170,{3U,1U,0U}}, +{MOVE_2170,{4U,1U,0U}}, +{MOVE_2170,{5U,1U,0U}}, +{MOVE_2170,{6U,1U,0U}}, +{MOVE_2170,{7U,1U,0U}}, +{MOVE_2178,{0U,1U,0U}}, +{MOVE_2179,{0U,1U,0U}}, +{MOVE_217A,{0U,1U,0U}}, +{MOVE_217B,{0U,1U,0U}}, +{MOVE_217C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2180,{0U,1U,0U}}, +{MOVE_2180,{1U,1U,0U}}, +{MOVE_2180,{2U,1U,0U}}, +{MOVE_2180,{3U,1U,0U}}, +{MOVE_2180,{4U,1U,0U}}, +{MOVE_2180,{5U,1U,0U}}, +{MOVE_2180,{6U,1U,0U}}, +{MOVE_2180,{7U,1U,0U}}, +{MOVE_2188,{0U,1U,0U}}, +{MOVE_2188,{1U,1U,0U}}, +{MOVE_2188,{2U,1U,0U}}, +{MOVE_2188,{3U,1U,0U}}, +{MOVE_2188,{4U,1U,0U}}, +{MOVE_2188,{5U,1U,0U}}, +{MOVE_2188,{6U,1U,0U}}, +{MOVE_2188,{7U,1U,0U}}, +{MOVE_2190,{0U,1U,0U}}, +{MOVE_2190,{1U,1U,0U}}, +{MOVE_2190,{2U,1U,0U}}, +{MOVE_2190,{3U,1U,0U}}, +{MOVE_2190,{4U,1U,0U}}, +{MOVE_2190,{5U,1U,0U}}, +{MOVE_2190,{6U,1U,0U}}, +{MOVE_2190,{7U,1U,0U}}, +{MOVE_2198,{0U,1U,0U}}, +{MOVE_2198,{1U,1U,0U}}, +{MOVE_2198,{2U,1U,0U}}, +{MOVE_2198,{3U,1U,0U}}, +{MOVE_2198,{4U,1U,0U}}, +{MOVE_2198,{5U,1U,0U}}, +{MOVE_2198,{6U,1U,0U}}, +{MOVE_2198,{7U,1U,0U}}, +{MOVE_21A0,{0U,1U,0U}}, +{MOVE_21A0,{1U,1U,0U}}, +{MOVE_21A0,{2U,1U,0U}}, +{MOVE_21A0,{3U,1U,0U}}, +{MOVE_21A0,{4U,1U,0U}}, +{MOVE_21A0,{5U,1U,0U}}, +{MOVE_21A0,{6U,1U,0U}}, +{MOVE_21A0,{7U,1U,0U}}, +{MOVE_21A8,{0U,1U,0U}}, +{MOVE_21A8,{1U,1U,0U}}, +{MOVE_21A8,{2U,1U,0U}}, +{MOVE_21A8,{3U,1U,0U}}, +{MOVE_21A8,{4U,1U,0U}}, +{MOVE_21A8,{5U,1U,0U}}, +{MOVE_21A8,{6U,1U,0U}}, +{MOVE_21A8,{7U,1U,0U}}, +{MOVE_21B0,{0U,1U,0U}}, +{MOVE_21B0,{1U,1U,0U}}, +{MOVE_21B0,{2U,1U,0U}}, +{MOVE_21B0,{3U,1U,0U}}, +{MOVE_21B0,{4U,1U,0U}}, +{MOVE_21B0,{5U,1U,0U}}, +{MOVE_21B0,{6U,1U,0U}}, +{MOVE_21B0,{7U,1U,0U}}, +{MOVE_21B8,{0U,1U,0U}}, +{MOVE_21B9,{0U,1U,0U}}, +{MOVE_21BA,{0U,1U,0U}}, +{MOVE_21BB,{0U,1U,0U}}, +{MOVE_21BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_23C0,{0U,0U,0U}}, +{MOVE_23C0,{1U,0U,0U}}, +{MOVE_23C0,{2U,0U,0U}}, +{MOVE_23C0,{3U,0U,0U}}, +{MOVE_23C0,{4U,0U,0U}}, +{MOVE_23C0,{5U,0U,0U}}, +{MOVE_23C0,{6U,0U,0U}}, +{MOVE_23C0,{7U,0U,0U}}, +{MOVE_23C8,{0U,0U,0U}}, +{MOVE_23C8,{1U,0U,0U}}, +{MOVE_23C8,{2U,0U,0U}}, +{MOVE_23C8,{3U,0U,0U}}, +{MOVE_23C8,{4U,0U,0U}}, +{MOVE_23C8,{5U,0U,0U}}, +{MOVE_23C8,{6U,0U,0U}}, +{MOVE_23C8,{7U,0U,0U}}, +{MOVE_23D0,{0U,0U,0U}}, +{MOVE_23D0,{1U,0U,0U}}, +{MOVE_23D0,{2U,0U,0U}}, +{MOVE_23D0,{3U,0U,0U}}, +{MOVE_23D0,{4U,0U,0U}}, +{MOVE_23D0,{5U,0U,0U}}, +{MOVE_23D0,{6U,0U,0U}}, +{MOVE_23D0,{7U,0U,0U}}, +{MOVE_23D8,{0U,0U,0U}}, +{MOVE_23D8,{1U,0U,0U}}, +{MOVE_23D8,{2U,0U,0U}}, +{MOVE_23D8,{3U,0U,0U}}, +{MOVE_23D8,{4U,0U,0U}}, +{MOVE_23D8,{5U,0U,0U}}, +{MOVE_23D8,{6U,0U,0U}}, +{MOVE_23D8,{7U,0U,0U}}, +{MOVE_23E0,{0U,0U,0U}}, +{MOVE_23E0,{1U,0U,0U}}, +{MOVE_23E0,{2U,0U,0U}}, +{MOVE_23E0,{3U,0U,0U}}, +{MOVE_23E0,{4U,0U,0U}}, +{MOVE_23E0,{5U,0U,0U}}, +{MOVE_23E0,{6U,0U,0U}}, +{MOVE_23E0,{7U,0U,0U}}, +{MOVE_23E8,{0U,0U,0U}}, +{MOVE_23E8,{1U,0U,0U}}, +{MOVE_23E8,{2U,0U,0U}}, +{MOVE_23E8,{3U,0U,0U}}, +{MOVE_23E8,{4U,0U,0U}}, +{MOVE_23E8,{5U,0U,0U}}, +{MOVE_23E8,{6U,0U,0U}}, +{MOVE_23E8,{7U,0U,0U}}, +{MOVE_23F0,{0U,0U,0U}}, +{MOVE_23F0,{1U,0U,0U}}, +{MOVE_23F0,{2U,0U,0U}}, +{MOVE_23F0,{3U,0U,0U}}, +{MOVE_23F0,{4U,0U,0U}}, +{MOVE_23F0,{5U,0U,0U}}, +{MOVE_23F0,{6U,0U,0U}}, +{MOVE_23F0,{7U,0U,0U}}, +{MOVE_23F8,{0U,0U,0U}}, +{MOVE_23F9,{0U,0U,0U}}, +{MOVE_23FA,{0U,0U,0U}}, +{MOVE_23FB,{0U,0U,0U}}, +{MOVE_23FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2000,{0U,2U,0U}}, +{MOVE_2000,{1U,2U,0U}}, +{MOVE_2000,{2U,2U,0U}}, +{MOVE_2000,{3U,2U,0U}}, +{MOVE_2000,{4U,2U,0U}}, +{MOVE_2000,{5U,2U,0U}}, +{MOVE_2000,{6U,2U,0U}}, +{MOVE_2000,{7U,2U,0U}}, +{MOVE_2008,{0U,2U,0U}}, +{MOVE_2008,{1U,2U,0U}}, +{MOVE_2008,{2U,2U,0U}}, +{MOVE_2008,{3U,2U,0U}}, +{MOVE_2008,{4U,2U,0U}}, +{MOVE_2008,{5U,2U,0U}}, +{MOVE_2008,{6U,2U,0U}}, +{MOVE_2008,{7U,2U,0U}}, +{MOVE_2010,{0U,2U,0U}}, +{MOVE_2010,{1U,2U,0U}}, +{MOVE_2010,{2U,2U,0U}}, +{MOVE_2010,{3U,2U,0U}}, +{MOVE_2010,{4U,2U,0U}}, +{MOVE_2010,{5U,2U,0U}}, +{MOVE_2010,{6U,2U,0U}}, +{MOVE_2010,{7U,2U,0U}}, +{MOVE_2018,{0U,2U,0U}}, +{MOVE_2018,{1U,2U,0U}}, +{MOVE_2018,{2U,2U,0U}}, +{MOVE_2018,{3U,2U,0U}}, +{MOVE_2018,{4U,2U,0U}}, +{MOVE_2018,{5U,2U,0U}}, +{MOVE_2018,{6U,2U,0U}}, +{MOVE_2018,{7U,2U,0U}}, +{MOVE_2020,{0U,2U,0U}}, +{MOVE_2020,{1U,2U,0U}}, +{MOVE_2020,{2U,2U,0U}}, +{MOVE_2020,{3U,2U,0U}}, +{MOVE_2020,{4U,2U,0U}}, +{MOVE_2020,{5U,2U,0U}}, +{MOVE_2020,{6U,2U,0U}}, +{MOVE_2020,{7U,2U,0U}}, +{MOVE_2028,{0U,2U,0U}}, +{MOVE_2028,{1U,2U,0U}}, +{MOVE_2028,{2U,2U,0U}}, +{MOVE_2028,{3U,2U,0U}}, +{MOVE_2028,{4U,2U,0U}}, +{MOVE_2028,{5U,2U,0U}}, +{MOVE_2028,{6U,2U,0U}}, +{MOVE_2028,{7U,2U,0U}}, +{MOVE_2030,{0U,2U,0U}}, +{MOVE_2030,{1U,2U,0U}}, +{MOVE_2030,{2U,2U,0U}}, +{MOVE_2030,{3U,2U,0U}}, +{MOVE_2030,{4U,2U,0U}}, +{MOVE_2030,{5U,2U,0U}}, +{MOVE_2030,{6U,2U,0U}}, +{MOVE_2030,{7U,2U,0U}}, +{MOVE_2038,{0U,2U,0U}}, +{MOVE_2039,{0U,2U,0U}}, +{MOVE_203A,{0U,2U,0U}}, +{MOVE_203B,{0U,2U,0U}}, +{MOVE_203C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_2040,{0U,2U,0U}}, +{MOVEA_2040,{1U,2U,0U}}, +{MOVEA_2040,{2U,2U,0U}}, +{MOVEA_2040,{3U,2U,0U}}, +{MOVEA_2040,{4U,2U,0U}}, +{MOVEA_2040,{5U,2U,0U}}, +{MOVEA_2040,{6U,2U,0U}}, +{MOVEA_2040,{7U,2U,0U}}, +{MOVEA_2048,{0U,2U,0U}}, +{MOVEA_2048,{1U,2U,0U}}, +{MOVEA_2048,{2U,2U,0U}}, +{MOVEA_2048,{3U,2U,0U}}, +{MOVEA_2048,{4U,2U,0U}}, +{MOVEA_2048,{5U,2U,0U}}, +{MOVEA_2048,{6U,2U,0U}}, +{MOVEA_2048,{7U,2U,0U}}, +{MOVEA_2050,{0U,2U,0U}}, +{MOVEA_2050,{1U,2U,0U}}, +{MOVEA_2050,{2U,2U,0U}}, +{MOVEA_2050,{3U,2U,0U}}, +{MOVEA_2050,{4U,2U,0U}}, +{MOVEA_2050,{5U,2U,0U}}, +{MOVEA_2050,{6U,2U,0U}}, +{MOVEA_2050,{7U,2U,0U}}, +{MOVEA_2058,{0U,2U,0U}}, +{MOVEA_2058,{1U,2U,0U}}, +{MOVEA_2058,{2U,2U,0U}}, +{MOVEA_2058,{3U,2U,0U}}, +{MOVEA_2058,{4U,2U,0U}}, +{MOVEA_2058,{5U,2U,0U}}, +{MOVEA_2058,{6U,2U,0U}}, +{MOVEA_2058,{7U,2U,0U}}, +{MOVEA_2060,{0U,2U,0U}}, +{MOVEA_2060,{1U,2U,0U}}, +{MOVEA_2060,{2U,2U,0U}}, +{MOVEA_2060,{3U,2U,0U}}, +{MOVEA_2060,{4U,2U,0U}}, +{MOVEA_2060,{5U,2U,0U}}, +{MOVEA_2060,{6U,2U,0U}}, +{MOVEA_2060,{7U,2U,0U}}, +{MOVEA_2068,{0U,2U,0U}}, +{MOVEA_2068,{1U,2U,0U}}, +{MOVEA_2068,{2U,2U,0U}}, +{MOVEA_2068,{3U,2U,0U}}, +{MOVEA_2068,{4U,2U,0U}}, +{MOVEA_2068,{5U,2U,0U}}, +{MOVEA_2068,{6U,2U,0U}}, +{MOVEA_2068,{7U,2U,0U}}, +{MOVEA_2070,{0U,2U,0U}}, +{MOVEA_2070,{1U,2U,0U}}, +{MOVEA_2070,{2U,2U,0U}}, +{MOVEA_2070,{3U,2U,0U}}, +{MOVEA_2070,{4U,2U,0U}}, +{MOVEA_2070,{5U,2U,0U}}, +{MOVEA_2070,{6U,2U,0U}}, +{MOVEA_2070,{7U,2U,0U}}, +{MOVEA_2078,{0U,2U,0U}}, +{MOVEA_2079,{0U,2U,0U}}, +{MOVEA_207A,{0U,2U,0U}}, +{MOVEA_207B,{0U,2U,0U}}, +{MOVEA_207C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2080,{0U,2U,0U}}, +{MOVE_2080,{1U,2U,0U}}, +{MOVE_2080,{2U,2U,0U}}, +{MOVE_2080,{3U,2U,0U}}, +{MOVE_2080,{4U,2U,0U}}, +{MOVE_2080,{5U,2U,0U}}, +{MOVE_2080,{6U,2U,0U}}, +{MOVE_2080,{7U,2U,0U}}, +{MOVE_2088,{0U,2U,0U}}, +{MOVE_2088,{1U,2U,0U}}, +{MOVE_2088,{2U,2U,0U}}, +{MOVE_2088,{3U,2U,0U}}, +{MOVE_2088,{4U,2U,0U}}, +{MOVE_2088,{5U,2U,0U}}, +{MOVE_2088,{6U,2U,0U}}, +{MOVE_2088,{7U,2U,0U}}, +{MOVE_2090,{0U,2U,0U}}, +{MOVE_2090,{1U,2U,0U}}, +{MOVE_2090,{2U,2U,0U}}, +{MOVE_2090,{3U,2U,0U}}, +{MOVE_2090,{4U,2U,0U}}, +{MOVE_2090,{5U,2U,0U}}, +{MOVE_2090,{6U,2U,0U}}, +{MOVE_2090,{7U,2U,0U}}, +{MOVE_2098,{0U,2U,0U}}, +{MOVE_2098,{1U,2U,0U}}, +{MOVE_2098,{2U,2U,0U}}, +{MOVE_2098,{3U,2U,0U}}, +{MOVE_2098,{4U,2U,0U}}, +{MOVE_2098,{5U,2U,0U}}, +{MOVE_2098,{6U,2U,0U}}, +{MOVE_2098,{7U,2U,0U}}, +{MOVE_20A0,{0U,2U,0U}}, +{MOVE_20A0,{1U,2U,0U}}, +{MOVE_20A0,{2U,2U,0U}}, +{MOVE_20A0,{3U,2U,0U}}, +{MOVE_20A0,{4U,2U,0U}}, +{MOVE_20A0,{5U,2U,0U}}, +{MOVE_20A0,{6U,2U,0U}}, +{MOVE_20A0,{7U,2U,0U}}, +{MOVE_20A8,{0U,2U,0U}}, +{MOVE_20A8,{1U,2U,0U}}, +{MOVE_20A8,{2U,2U,0U}}, +{MOVE_20A8,{3U,2U,0U}}, +{MOVE_20A8,{4U,2U,0U}}, +{MOVE_20A8,{5U,2U,0U}}, +{MOVE_20A8,{6U,2U,0U}}, +{MOVE_20A8,{7U,2U,0U}}, +{MOVE_20B0,{0U,2U,0U}}, +{MOVE_20B0,{1U,2U,0U}}, +{MOVE_20B0,{2U,2U,0U}}, +{MOVE_20B0,{3U,2U,0U}}, +{MOVE_20B0,{4U,2U,0U}}, +{MOVE_20B0,{5U,2U,0U}}, +{MOVE_20B0,{6U,2U,0U}}, +{MOVE_20B0,{7U,2U,0U}}, +{MOVE_20B8,{0U,2U,0U}}, +{MOVE_20B9,{0U,2U,0U}}, +{MOVE_20BA,{0U,2U,0U}}, +{MOVE_20BB,{0U,2U,0U}}, +{MOVE_20BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_20C0,{0U,2U,0U}}, +{MOVE_20C0,{1U,2U,0U}}, +{MOVE_20C0,{2U,2U,0U}}, +{MOVE_20C0,{3U,2U,0U}}, +{MOVE_20C0,{4U,2U,0U}}, +{MOVE_20C0,{5U,2U,0U}}, +{MOVE_20C0,{6U,2U,0U}}, +{MOVE_20C0,{7U,2U,0U}}, +{MOVE_20C8,{0U,2U,0U}}, +{MOVE_20C8,{1U,2U,0U}}, +{MOVE_20C8,{2U,2U,0U}}, +{MOVE_20C8,{3U,2U,0U}}, +{MOVE_20C8,{4U,2U,0U}}, +{MOVE_20C8,{5U,2U,0U}}, +{MOVE_20C8,{6U,2U,0U}}, +{MOVE_20C8,{7U,2U,0U}}, +{MOVE_20D0,{0U,2U,0U}}, +{MOVE_20D0,{1U,2U,0U}}, +{MOVE_20D0,{2U,2U,0U}}, +{MOVE_20D0,{3U,2U,0U}}, +{MOVE_20D0,{4U,2U,0U}}, +{MOVE_20D0,{5U,2U,0U}}, +{MOVE_20D0,{6U,2U,0U}}, +{MOVE_20D0,{7U,2U,0U}}, +{MOVE_20D8,{0U,2U,0U}}, +{MOVE_20D8,{1U,2U,0U}}, +{MOVE_20D8,{2U,2U,0U}}, +{MOVE_20D8,{3U,2U,0U}}, +{MOVE_20D8,{4U,2U,0U}}, +{MOVE_20D8,{5U,2U,0U}}, +{MOVE_20D8,{6U,2U,0U}}, +{MOVE_20D8,{7U,2U,0U}}, +{MOVE_20E0,{0U,2U,0U}}, +{MOVE_20E0,{1U,2U,0U}}, +{MOVE_20E0,{2U,2U,0U}}, +{MOVE_20E0,{3U,2U,0U}}, +{MOVE_20E0,{4U,2U,0U}}, +{MOVE_20E0,{5U,2U,0U}}, +{MOVE_20E0,{6U,2U,0U}}, +{MOVE_20E0,{7U,2U,0U}}, +{MOVE_20E8,{0U,2U,0U}}, +{MOVE_20E8,{1U,2U,0U}}, +{MOVE_20E8,{2U,2U,0U}}, +{MOVE_20E8,{3U,2U,0U}}, +{MOVE_20E8,{4U,2U,0U}}, +{MOVE_20E8,{5U,2U,0U}}, +{MOVE_20E8,{6U,2U,0U}}, +{MOVE_20E8,{7U,2U,0U}}, +{MOVE_20F0,{0U,2U,0U}}, +{MOVE_20F0,{1U,2U,0U}}, +{MOVE_20F0,{2U,2U,0U}}, +{MOVE_20F0,{3U,2U,0U}}, +{MOVE_20F0,{4U,2U,0U}}, +{MOVE_20F0,{5U,2U,0U}}, +{MOVE_20F0,{6U,2U,0U}}, +{MOVE_20F0,{7U,2U,0U}}, +{MOVE_20F8,{0U,2U,0U}}, +{MOVE_20F9,{0U,2U,0U}}, +{MOVE_20FA,{0U,2U,0U}}, +{MOVE_20FB,{0U,2U,0U}}, +{MOVE_20FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2100,{0U,2U,0U}}, +{MOVE_2100,{1U,2U,0U}}, +{MOVE_2100,{2U,2U,0U}}, +{MOVE_2100,{3U,2U,0U}}, +{MOVE_2100,{4U,2U,0U}}, +{MOVE_2100,{5U,2U,0U}}, +{MOVE_2100,{6U,2U,0U}}, +{MOVE_2100,{7U,2U,0U}}, +{MOVE_2108,{0U,2U,0U}}, +{MOVE_2108,{1U,2U,0U}}, +{MOVE_2108,{2U,2U,0U}}, +{MOVE_2108,{3U,2U,0U}}, +{MOVE_2108,{4U,2U,0U}}, +{MOVE_2108,{5U,2U,0U}}, +{MOVE_2108,{6U,2U,0U}}, +{MOVE_2108,{7U,2U,0U}}, +{MOVE_2110,{0U,2U,0U}}, +{MOVE_2110,{1U,2U,0U}}, +{MOVE_2110,{2U,2U,0U}}, +{MOVE_2110,{3U,2U,0U}}, +{MOVE_2110,{4U,2U,0U}}, +{MOVE_2110,{5U,2U,0U}}, +{MOVE_2110,{6U,2U,0U}}, +{MOVE_2110,{7U,2U,0U}}, +{MOVE_2118,{0U,2U,0U}}, +{MOVE_2118,{1U,2U,0U}}, +{MOVE_2118,{2U,2U,0U}}, +{MOVE_2118,{3U,2U,0U}}, +{MOVE_2118,{4U,2U,0U}}, +{MOVE_2118,{5U,2U,0U}}, +{MOVE_2118,{6U,2U,0U}}, +{MOVE_2118,{7U,2U,0U}}, +{MOVE_2120,{0U,2U,0U}}, +{MOVE_2120,{1U,2U,0U}}, +{MOVE_2120,{2U,2U,0U}}, +{MOVE_2120,{3U,2U,0U}}, +{MOVE_2120,{4U,2U,0U}}, +{MOVE_2120,{5U,2U,0U}}, +{MOVE_2120,{6U,2U,0U}}, +{MOVE_2120,{7U,2U,0U}}, +{MOVE_2128,{0U,2U,0U}}, +{MOVE_2128,{1U,2U,0U}}, +{MOVE_2128,{2U,2U,0U}}, +{MOVE_2128,{3U,2U,0U}}, +{MOVE_2128,{4U,2U,0U}}, +{MOVE_2128,{5U,2U,0U}}, +{MOVE_2128,{6U,2U,0U}}, +{MOVE_2128,{7U,2U,0U}}, +{MOVE_2130,{0U,2U,0U}}, +{MOVE_2130,{1U,2U,0U}}, +{MOVE_2130,{2U,2U,0U}}, +{MOVE_2130,{3U,2U,0U}}, +{MOVE_2130,{4U,2U,0U}}, +{MOVE_2130,{5U,2U,0U}}, +{MOVE_2130,{6U,2U,0U}}, +{MOVE_2130,{7U,2U,0U}}, +{MOVE_2138,{0U,2U,0U}}, +{MOVE_2139,{0U,2U,0U}}, +{MOVE_213A,{0U,2U,0U}}, +{MOVE_213B,{0U,2U,0U}}, +{MOVE_213C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2140,{0U,2U,0U}}, +{MOVE_2140,{1U,2U,0U}}, +{MOVE_2140,{2U,2U,0U}}, +{MOVE_2140,{3U,2U,0U}}, +{MOVE_2140,{4U,2U,0U}}, +{MOVE_2140,{5U,2U,0U}}, +{MOVE_2140,{6U,2U,0U}}, +{MOVE_2140,{7U,2U,0U}}, +{MOVE_2148,{0U,2U,0U}}, +{MOVE_2148,{1U,2U,0U}}, +{MOVE_2148,{2U,2U,0U}}, +{MOVE_2148,{3U,2U,0U}}, +{MOVE_2148,{4U,2U,0U}}, +{MOVE_2148,{5U,2U,0U}}, +{MOVE_2148,{6U,2U,0U}}, +{MOVE_2148,{7U,2U,0U}}, +{MOVE_2150,{0U,2U,0U}}, +{MOVE_2150,{1U,2U,0U}}, +{MOVE_2150,{2U,2U,0U}}, +{MOVE_2150,{3U,2U,0U}}, +{MOVE_2150,{4U,2U,0U}}, +{MOVE_2150,{5U,2U,0U}}, +{MOVE_2150,{6U,2U,0U}}, +{MOVE_2150,{7U,2U,0U}}, +{MOVE_2158,{0U,2U,0U}}, +{MOVE_2158,{1U,2U,0U}}, +{MOVE_2158,{2U,2U,0U}}, +{MOVE_2158,{3U,2U,0U}}, +{MOVE_2158,{4U,2U,0U}}, +{MOVE_2158,{5U,2U,0U}}, +{MOVE_2158,{6U,2U,0U}}, +{MOVE_2158,{7U,2U,0U}}, +{MOVE_2160,{0U,2U,0U}}, +{MOVE_2160,{1U,2U,0U}}, +{MOVE_2160,{2U,2U,0U}}, +{MOVE_2160,{3U,2U,0U}}, +{MOVE_2160,{4U,2U,0U}}, +{MOVE_2160,{5U,2U,0U}}, +{MOVE_2160,{6U,2U,0U}}, +{MOVE_2160,{7U,2U,0U}}, +{MOVE_2168,{0U,2U,0U}}, +{MOVE_2168,{1U,2U,0U}}, +{MOVE_2168,{2U,2U,0U}}, +{MOVE_2168,{3U,2U,0U}}, +{MOVE_2168,{4U,2U,0U}}, +{MOVE_2168,{5U,2U,0U}}, +{MOVE_2168,{6U,2U,0U}}, +{MOVE_2168,{7U,2U,0U}}, +{MOVE_2170,{0U,2U,0U}}, +{MOVE_2170,{1U,2U,0U}}, +{MOVE_2170,{2U,2U,0U}}, +{MOVE_2170,{3U,2U,0U}}, +{MOVE_2170,{4U,2U,0U}}, +{MOVE_2170,{5U,2U,0U}}, +{MOVE_2170,{6U,2U,0U}}, +{MOVE_2170,{7U,2U,0U}}, +{MOVE_2178,{0U,2U,0U}}, +{MOVE_2179,{0U,2U,0U}}, +{MOVE_217A,{0U,2U,0U}}, +{MOVE_217B,{0U,2U,0U}}, +{MOVE_217C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2180,{0U,2U,0U}}, +{MOVE_2180,{1U,2U,0U}}, +{MOVE_2180,{2U,2U,0U}}, +{MOVE_2180,{3U,2U,0U}}, +{MOVE_2180,{4U,2U,0U}}, +{MOVE_2180,{5U,2U,0U}}, +{MOVE_2180,{6U,2U,0U}}, +{MOVE_2180,{7U,2U,0U}}, +{MOVE_2188,{0U,2U,0U}}, +{MOVE_2188,{1U,2U,0U}}, +{MOVE_2188,{2U,2U,0U}}, +{MOVE_2188,{3U,2U,0U}}, +{MOVE_2188,{4U,2U,0U}}, +{MOVE_2188,{5U,2U,0U}}, +{MOVE_2188,{6U,2U,0U}}, +{MOVE_2188,{7U,2U,0U}}, +{MOVE_2190,{0U,2U,0U}}, +{MOVE_2190,{1U,2U,0U}}, +{MOVE_2190,{2U,2U,0U}}, +{MOVE_2190,{3U,2U,0U}}, +{MOVE_2190,{4U,2U,0U}}, +{MOVE_2190,{5U,2U,0U}}, +{MOVE_2190,{6U,2U,0U}}, +{MOVE_2190,{7U,2U,0U}}, +{MOVE_2198,{0U,2U,0U}}, +{MOVE_2198,{1U,2U,0U}}, +{MOVE_2198,{2U,2U,0U}}, +{MOVE_2198,{3U,2U,0U}}, +{MOVE_2198,{4U,2U,0U}}, +{MOVE_2198,{5U,2U,0U}}, +{MOVE_2198,{6U,2U,0U}}, +{MOVE_2198,{7U,2U,0U}}, +{MOVE_21A0,{0U,2U,0U}}, +{MOVE_21A0,{1U,2U,0U}}, +{MOVE_21A0,{2U,2U,0U}}, +{MOVE_21A0,{3U,2U,0U}}, +{MOVE_21A0,{4U,2U,0U}}, +{MOVE_21A0,{5U,2U,0U}}, +{MOVE_21A0,{6U,2U,0U}}, +{MOVE_21A0,{7U,2U,0U}}, +{MOVE_21A8,{0U,2U,0U}}, +{MOVE_21A8,{1U,2U,0U}}, +{MOVE_21A8,{2U,2U,0U}}, +{MOVE_21A8,{3U,2U,0U}}, +{MOVE_21A8,{4U,2U,0U}}, +{MOVE_21A8,{5U,2U,0U}}, +{MOVE_21A8,{6U,2U,0U}}, +{MOVE_21A8,{7U,2U,0U}}, +{MOVE_21B0,{0U,2U,0U}}, +{MOVE_21B0,{1U,2U,0U}}, +{MOVE_21B0,{2U,2U,0U}}, +{MOVE_21B0,{3U,2U,0U}}, +{MOVE_21B0,{4U,2U,0U}}, +{MOVE_21B0,{5U,2U,0U}}, +{MOVE_21B0,{6U,2U,0U}}, +{MOVE_21B0,{7U,2U,0U}}, +{MOVE_21B8,{0U,2U,0U}}, +{MOVE_21B9,{0U,2U,0U}}, +{MOVE_21BA,{0U,2U,0U}}, +{MOVE_21BB,{0U,2U,0U}}, +{MOVE_21BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2000,{0U,3U,0U}}, +{MOVE_2000,{1U,3U,0U}}, +{MOVE_2000,{2U,3U,0U}}, +{MOVE_2000,{3U,3U,0U}}, +{MOVE_2000,{4U,3U,0U}}, +{MOVE_2000,{5U,3U,0U}}, +{MOVE_2000,{6U,3U,0U}}, +{MOVE_2000,{7U,3U,0U}}, +{MOVE_2008,{0U,3U,0U}}, +{MOVE_2008,{1U,3U,0U}}, +{MOVE_2008,{2U,3U,0U}}, +{MOVE_2008,{3U,3U,0U}}, +{MOVE_2008,{4U,3U,0U}}, +{MOVE_2008,{5U,3U,0U}}, +{MOVE_2008,{6U,3U,0U}}, +{MOVE_2008,{7U,3U,0U}}, +{MOVE_2010,{0U,3U,0U}}, +{MOVE_2010,{1U,3U,0U}}, +{MOVE_2010,{2U,3U,0U}}, +{MOVE_2010,{3U,3U,0U}}, +{MOVE_2010,{4U,3U,0U}}, +{MOVE_2010,{5U,3U,0U}}, +{MOVE_2010,{6U,3U,0U}}, +{MOVE_2010,{7U,3U,0U}}, +{MOVE_2018,{0U,3U,0U}}, +{MOVE_2018,{1U,3U,0U}}, +{MOVE_2018,{2U,3U,0U}}, +{MOVE_2018,{3U,3U,0U}}, +{MOVE_2018,{4U,3U,0U}}, +{MOVE_2018,{5U,3U,0U}}, +{MOVE_2018,{6U,3U,0U}}, +{MOVE_2018,{7U,3U,0U}}, +{MOVE_2020,{0U,3U,0U}}, +{MOVE_2020,{1U,3U,0U}}, +{MOVE_2020,{2U,3U,0U}}, +{MOVE_2020,{3U,3U,0U}}, +{MOVE_2020,{4U,3U,0U}}, +{MOVE_2020,{5U,3U,0U}}, +{MOVE_2020,{6U,3U,0U}}, +{MOVE_2020,{7U,3U,0U}}, +{MOVE_2028,{0U,3U,0U}}, +{MOVE_2028,{1U,3U,0U}}, +{MOVE_2028,{2U,3U,0U}}, +{MOVE_2028,{3U,3U,0U}}, +{MOVE_2028,{4U,3U,0U}}, +{MOVE_2028,{5U,3U,0U}}, +{MOVE_2028,{6U,3U,0U}}, +{MOVE_2028,{7U,3U,0U}}, +{MOVE_2030,{0U,3U,0U}}, +{MOVE_2030,{1U,3U,0U}}, +{MOVE_2030,{2U,3U,0U}}, +{MOVE_2030,{3U,3U,0U}}, +{MOVE_2030,{4U,3U,0U}}, +{MOVE_2030,{5U,3U,0U}}, +{MOVE_2030,{6U,3U,0U}}, +{MOVE_2030,{7U,3U,0U}}, +{MOVE_2038,{0U,3U,0U}}, +{MOVE_2039,{0U,3U,0U}}, +{MOVE_203A,{0U,3U,0U}}, +{MOVE_203B,{0U,3U,0U}}, +{MOVE_203C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_2040,{0U,3U,0U}}, +{MOVEA_2040,{1U,3U,0U}}, +{MOVEA_2040,{2U,3U,0U}}, +{MOVEA_2040,{3U,3U,0U}}, +{MOVEA_2040,{4U,3U,0U}}, +{MOVEA_2040,{5U,3U,0U}}, +{MOVEA_2040,{6U,3U,0U}}, +{MOVEA_2040,{7U,3U,0U}}, +{MOVEA_2048,{0U,3U,0U}}, +{MOVEA_2048,{1U,3U,0U}}, +{MOVEA_2048,{2U,3U,0U}}, +{MOVEA_2048,{3U,3U,0U}}, +{MOVEA_2048,{4U,3U,0U}}, +{MOVEA_2048,{5U,3U,0U}}, +{MOVEA_2048,{6U,3U,0U}}, +{MOVEA_2048,{7U,3U,0U}}, +{MOVEA_2050,{0U,3U,0U}}, +{MOVEA_2050,{1U,3U,0U}}, +{MOVEA_2050,{2U,3U,0U}}, +{MOVEA_2050,{3U,3U,0U}}, +{MOVEA_2050,{4U,3U,0U}}, +{MOVEA_2050,{5U,3U,0U}}, +{MOVEA_2050,{6U,3U,0U}}, +{MOVEA_2050,{7U,3U,0U}}, +{MOVEA_2058,{0U,3U,0U}}, +{MOVEA_2058,{1U,3U,0U}}, +{MOVEA_2058,{2U,3U,0U}}, +{MOVEA_2058,{3U,3U,0U}}, +{MOVEA_2058,{4U,3U,0U}}, +{MOVEA_2058,{5U,3U,0U}}, +{MOVEA_2058,{6U,3U,0U}}, +{MOVEA_2058,{7U,3U,0U}}, +{MOVEA_2060,{0U,3U,0U}}, +{MOVEA_2060,{1U,3U,0U}}, +{MOVEA_2060,{2U,3U,0U}}, +{MOVEA_2060,{3U,3U,0U}}, +{MOVEA_2060,{4U,3U,0U}}, +{MOVEA_2060,{5U,3U,0U}}, +{MOVEA_2060,{6U,3U,0U}}, +{MOVEA_2060,{7U,3U,0U}}, +{MOVEA_2068,{0U,3U,0U}}, +{MOVEA_2068,{1U,3U,0U}}, +{MOVEA_2068,{2U,3U,0U}}, +{MOVEA_2068,{3U,3U,0U}}, +{MOVEA_2068,{4U,3U,0U}}, +{MOVEA_2068,{5U,3U,0U}}, +{MOVEA_2068,{6U,3U,0U}}, +{MOVEA_2068,{7U,3U,0U}}, +{MOVEA_2070,{0U,3U,0U}}, +{MOVEA_2070,{1U,3U,0U}}, +{MOVEA_2070,{2U,3U,0U}}, +{MOVEA_2070,{3U,3U,0U}}, +{MOVEA_2070,{4U,3U,0U}}, +{MOVEA_2070,{5U,3U,0U}}, +{MOVEA_2070,{6U,3U,0U}}, +{MOVEA_2070,{7U,3U,0U}}, +{MOVEA_2078,{0U,3U,0U}}, +{MOVEA_2079,{0U,3U,0U}}, +{MOVEA_207A,{0U,3U,0U}}, +{MOVEA_207B,{0U,3U,0U}}, +{MOVEA_207C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2080,{0U,3U,0U}}, +{MOVE_2080,{1U,3U,0U}}, +{MOVE_2080,{2U,3U,0U}}, +{MOVE_2080,{3U,3U,0U}}, +{MOVE_2080,{4U,3U,0U}}, +{MOVE_2080,{5U,3U,0U}}, +{MOVE_2080,{6U,3U,0U}}, +{MOVE_2080,{7U,3U,0U}}, +{MOVE_2088,{0U,3U,0U}}, +{MOVE_2088,{1U,3U,0U}}, +{MOVE_2088,{2U,3U,0U}}, +{MOVE_2088,{3U,3U,0U}}, +{MOVE_2088,{4U,3U,0U}}, +{MOVE_2088,{5U,3U,0U}}, +{MOVE_2088,{6U,3U,0U}}, +{MOVE_2088,{7U,3U,0U}}, +{MOVE_2090,{0U,3U,0U}}, +{MOVE_2090,{1U,3U,0U}}, +{MOVE_2090,{2U,3U,0U}}, +{MOVE_2090,{3U,3U,0U}}, +{MOVE_2090,{4U,3U,0U}}, +{MOVE_2090,{5U,3U,0U}}, +{MOVE_2090,{6U,3U,0U}}, +{MOVE_2090,{7U,3U,0U}}, +{MOVE_2098,{0U,3U,0U}}, +{MOVE_2098,{1U,3U,0U}}, +{MOVE_2098,{2U,3U,0U}}, +{MOVE_2098,{3U,3U,0U}}, +{MOVE_2098,{4U,3U,0U}}, +{MOVE_2098,{5U,3U,0U}}, +{MOVE_2098,{6U,3U,0U}}, +{MOVE_2098,{7U,3U,0U}}, +{MOVE_20A0,{0U,3U,0U}}, +{MOVE_20A0,{1U,3U,0U}}, +{MOVE_20A0,{2U,3U,0U}}, +{MOVE_20A0,{3U,3U,0U}}, +{MOVE_20A0,{4U,3U,0U}}, +{MOVE_20A0,{5U,3U,0U}}, +{MOVE_20A0,{6U,3U,0U}}, +{MOVE_20A0,{7U,3U,0U}}, +{MOVE_20A8,{0U,3U,0U}}, +{MOVE_20A8,{1U,3U,0U}}, +{MOVE_20A8,{2U,3U,0U}}, +{MOVE_20A8,{3U,3U,0U}}, +{MOVE_20A8,{4U,3U,0U}}, +{MOVE_20A8,{5U,3U,0U}}, +{MOVE_20A8,{6U,3U,0U}}, +{MOVE_20A8,{7U,3U,0U}}, +{MOVE_20B0,{0U,3U,0U}}, +{MOVE_20B0,{1U,3U,0U}}, +{MOVE_20B0,{2U,3U,0U}}, +{MOVE_20B0,{3U,3U,0U}}, +{MOVE_20B0,{4U,3U,0U}}, +{MOVE_20B0,{5U,3U,0U}}, +{MOVE_20B0,{6U,3U,0U}}, +{MOVE_20B0,{7U,3U,0U}}, +{MOVE_20B8,{0U,3U,0U}}, +{MOVE_20B9,{0U,3U,0U}}, +{MOVE_20BA,{0U,3U,0U}}, +{MOVE_20BB,{0U,3U,0U}}, +{MOVE_20BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_20C0,{0U,3U,0U}}, +{MOVE_20C0,{1U,3U,0U}}, +{MOVE_20C0,{2U,3U,0U}}, +{MOVE_20C0,{3U,3U,0U}}, +{MOVE_20C0,{4U,3U,0U}}, +{MOVE_20C0,{5U,3U,0U}}, +{MOVE_20C0,{6U,3U,0U}}, +{MOVE_20C0,{7U,3U,0U}}, +{MOVE_20C8,{0U,3U,0U}}, +{MOVE_20C8,{1U,3U,0U}}, +{MOVE_20C8,{2U,3U,0U}}, +{MOVE_20C8,{3U,3U,0U}}, +{MOVE_20C8,{4U,3U,0U}}, +{MOVE_20C8,{5U,3U,0U}}, +{MOVE_20C8,{6U,3U,0U}}, +{MOVE_20C8,{7U,3U,0U}}, +{MOVE_20D0,{0U,3U,0U}}, +{MOVE_20D0,{1U,3U,0U}}, +{MOVE_20D0,{2U,3U,0U}}, +{MOVE_20D0,{3U,3U,0U}}, +{MOVE_20D0,{4U,3U,0U}}, +{MOVE_20D0,{5U,3U,0U}}, +{MOVE_20D0,{6U,3U,0U}}, +{MOVE_20D0,{7U,3U,0U}}, +{MOVE_20D8,{0U,3U,0U}}, +{MOVE_20D8,{1U,3U,0U}}, +{MOVE_20D8,{2U,3U,0U}}, +{MOVE_20D8,{3U,3U,0U}}, +{MOVE_20D8,{4U,3U,0U}}, +{MOVE_20D8,{5U,3U,0U}}, +{MOVE_20D8,{6U,3U,0U}}, +{MOVE_20D8,{7U,3U,0U}}, +{MOVE_20E0,{0U,3U,0U}}, +{MOVE_20E0,{1U,3U,0U}}, +{MOVE_20E0,{2U,3U,0U}}, +{MOVE_20E0,{3U,3U,0U}}, +{MOVE_20E0,{4U,3U,0U}}, +{MOVE_20E0,{5U,3U,0U}}, +{MOVE_20E0,{6U,3U,0U}}, +{MOVE_20E0,{7U,3U,0U}}, +{MOVE_20E8,{0U,3U,0U}}, +{MOVE_20E8,{1U,3U,0U}}, +{MOVE_20E8,{2U,3U,0U}}, +{MOVE_20E8,{3U,3U,0U}}, +{MOVE_20E8,{4U,3U,0U}}, +{MOVE_20E8,{5U,3U,0U}}, +{MOVE_20E8,{6U,3U,0U}}, +{MOVE_20E8,{7U,3U,0U}}, +{MOVE_20F0,{0U,3U,0U}}, +{MOVE_20F0,{1U,3U,0U}}, +{MOVE_20F0,{2U,3U,0U}}, +{MOVE_20F0,{3U,3U,0U}}, +{MOVE_20F0,{4U,3U,0U}}, +{MOVE_20F0,{5U,3U,0U}}, +{MOVE_20F0,{6U,3U,0U}}, +{MOVE_20F0,{7U,3U,0U}}, +{MOVE_20F8,{0U,3U,0U}}, +{MOVE_20F9,{0U,3U,0U}}, +{MOVE_20FA,{0U,3U,0U}}, +{MOVE_20FB,{0U,3U,0U}}, +{MOVE_20FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2100,{0U,3U,0U}}, +{MOVE_2100,{1U,3U,0U}}, +{MOVE_2100,{2U,3U,0U}}, +{MOVE_2100,{3U,3U,0U}}, +{MOVE_2100,{4U,3U,0U}}, +{MOVE_2100,{5U,3U,0U}}, +{MOVE_2100,{6U,3U,0U}}, +{MOVE_2100,{7U,3U,0U}}, +{MOVE_2108,{0U,3U,0U}}, +{MOVE_2108,{1U,3U,0U}}, +{MOVE_2108,{2U,3U,0U}}, +{MOVE_2108,{3U,3U,0U}}, +{MOVE_2108,{4U,3U,0U}}, +{MOVE_2108,{5U,3U,0U}}, +{MOVE_2108,{6U,3U,0U}}, +{MOVE_2108,{7U,3U,0U}}, +{MOVE_2110,{0U,3U,0U}}, +{MOVE_2110,{1U,3U,0U}}, +{MOVE_2110,{2U,3U,0U}}, +{MOVE_2110,{3U,3U,0U}}, +{MOVE_2110,{4U,3U,0U}}, +{MOVE_2110,{5U,3U,0U}}, +{MOVE_2110,{6U,3U,0U}}, +{MOVE_2110,{7U,3U,0U}}, +{MOVE_2118,{0U,3U,0U}}, +{MOVE_2118,{1U,3U,0U}}, +{MOVE_2118,{2U,3U,0U}}, +{MOVE_2118,{3U,3U,0U}}, +{MOVE_2118,{4U,3U,0U}}, +{MOVE_2118,{5U,3U,0U}}, +{MOVE_2118,{6U,3U,0U}}, +{MOVE_2118,{7U,3U,0U}}, +{MOVE_2120,{0U,3U,0U}}, +{MOVE_2120,{1U,3U,0U}}, +{MOVE_2120,{2U,3U,0U}}, +{MOVE_2120,{3U,3U,0U}}, +{MOVE_2120,{4U,3U,0U}}, +{MOVE_2120,{5U,3U,0U}}, +{MOVE_2120,{6U,3U,0U}}, +{MOVE_2120,{7U,3U,0U}}, +{MOVE_2128,{0U,3U,0U}}, +{MOVE_2128,{1U,3U,0U}}, +{MOVE_2128,{2U,3U,0U}}, +{MOVE_2128,{3U,3U,0U}}, +{MOVE_2128,{4U,3U,0U}}, +{MOVE_2128,{5U,3U,0U}}, +{MOVE_2128,{6U,3U,0U}}, +{MOVE_2128,{7U,3U,0U}}, +{MOVE_2130,{0U,3U,0U}}, +{MOVE_2130,{1U,3U,0U}}, +{MOVE_2130,{2U,3U,0U}}, +{MOVE_2130,{3U,3U,0U}}, +{MOVE_2130,{4U,3U,0U}}, +{MOVE_2130,{5U,3U,0U}}, +{MOVE_2130,{6U,3U,0U}}, +{MOVE_2130,{7U,3U,0U}}, +{MOVE_2138,{0U,3U,0U}}, +{MOVE_2139,{0U,3U,0U}}, +{MOVE_213A,{0U,3U,0U}}, +{MOVE_213B,{0U,3U,0U}}, +{MOVE_213C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2140,{0U,3U,0U}}, +{MOVE_2140,{1U,3U,0U}}, +{MOVE_2140,{2U,3U,0U}}, +{MOVE_2140,{3U,3U,0U}}, +{MOVE_2140,{4U,3U,0U}}, +{MOVE_2140,{5U,3U,0U}}, +{MOVE_2140,{6U,3U,0U}}, +{MOVE_2140,{7U,3U,0U}}, +{MOVE_2148,{0U,3U,0U}}, +{MOVE_2148,{1U,3U,0U}}, +{MOVE_2148,{2U,3U,0U}}, +{MOVE_2148,{3U,3U,0U}}, +{MOVE_2148,{4U,3U,0U}}, +{MOVE_2148,{5U,3U,0U}}, +{MOVE_2148,{6U,3U,0U}}, +{MOVE_2148,{7U,3U,0U}}, +{MOVE_2150,{0U,3U,0U}}, +{MOVE_2150,{1U,3U,0U}}, +{MOVE_2150,{2U,3U,0U}}, +{MOVE_2150,{3U,3U,0U}}, +{MOVE_2150,{4U,3U,0U}}, +{MOVE_2150,{5U,3U,0U}}, +{MOVE_2150,{6U,3U,0U}}, +{MOVE_2150,{7U,3U,0U}}, +{MOVE_2158,{0U,3U,0U}}, +{MOVE_2158,{1U,3U,0U}}, +{MOVE_2158,{2U,3U,0U}}, +{MOVE_2158,{3U,3U,0U}}, +{MOVE_2158,{4U,3U,0U}}, +{MOVE_2158,{5U,3U,0U}}, +{MOVE_2158,{6U,3U,0U}}, +{MOVE_2158,{7U,3U,0U}}, +{MOVE_2160,{0U,3U,0U}}, +{MOVE_2160,{1U,3U,0U}}, +{MOVE_2160,{2U,3U,0U}}, +{MOVE_2160,{3U,3U,0U}}, +{MOVE_2160,{4U,3U,0U}}, +{MOVE_2160,{5U,3U,0U}}, +{MOVE_2160,{6U,3U,0U}}, +{MOVE_2160,{7U,3U,0U}}, +{MOVE_2168,{0U,3U,0U}}, +{MOVE_2168,{1U,3U,0U}}, +{MOVE_2168,{2U,3U,0U}}, +{MOVE_2168,{3U,3U,0U}}, +{MOVE_2168,{4U,3U,0U}}, +{MOVE_2168,{5U,3U,0U}}, +{MOVE_2168,{6U,3U,0U}}, +{MOVE_2168,{7U,3U,0U}}, +{MOVE_2170,{0U,3U,0U}}, +{MOVE_2170,{1U,3U,0U}}, +{MOVE_2170,{2U,3U,0U}}, +{MOVE_2170,{3U,3U,0U}}, +{MOVE_2170,{4U,3U,0U}}, +{MOVE_2170,{5U,3U,0U}}, +{MOVE_2170,{6U,3U,0U}}, +{MOVE_2170,{7U,3U,0U}}, +{MOVE_2178,{0U,3U,0U}}, +{MOVE_2179,{0U,3U,0U}}, +{MOVE_217A,{0U,3U,0U}}, +{MOVE_217B,{0U,3U,0U}}, +{MOVE_217C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2180,{0U,3U,0U}}, +{MOVE_2180,{1U,3U,0U}}, +{MOVE_2180,{2U,3U,0U}}, +{MOVE_2180,{3U,3U,0U}}, +{MOVE_2180,{4U,3U,0U}}, +{MOVE_2180,{5U,3U,0U}}, +{MOVE_2180,{6U,3U,0U}}, +{MOVE_2180,{7U,3U,0U}}, +{MOVE_2188,{0U,3U,0U}}, +{MOVE_2188,{1U,3U,0U}}, +{MOVE_2188,{2U,3U,0U}}, +{MOVE_2188,{3U,3U,0U}}, +{MOVE_2188,{4U,3U,0U}}, +{MOVE_2188,{5U,3U,0U}}, +{MOVE_2188,{6U,3U,0U}}, +{MOVE_2188,{7U,3U,0U}}, +{MOVE_2190,{0U,3U,0U}}, +{MOVE_2190,{1U,3U,0U}}, +{MOVE_2190,{2U,3U,0U}}, +{MOVE_2190,{3U,3U,0U}}, +{MOVE_2190,{4U,3U,0U}}, +{MOVE_2190,{5U,3U,0U}}, +{MOVE_2190,{6U,3U,0U}}, +{MOVE_2190,{7U,3U,0U}}, +{MOVE_2198,{0U,3U,0U}}, +{MOVE_2198,{1U,3U,0U}}, +{MOVE_2198,{2U,3U,0U}}, +{MOVE_2198,{3U,3U,0U}}, +{MOVE_2198,{4U,3U,0U}}, +{MOVE_2198,{5U,3U,0U}}, +{MOVE_2198,{6U,3U,0U}}, +{MOVE_2198,{7U,3U,0U}}, +{MOVE_21A0,{0U,3U,0U}}, +{MOVE_21A0,{1U,3U,0U}}, +{MOVE_21A0,{2U,3U,0U}}, +{MOVE_21A0,{3U,3U,0U}}, +{MOVE_21A0,{4U,3U,0U}}, +{MOVE_21A0,{5U,3U,0U}}, +{MOVE_21A0,{6U,3U,0U}}, +{MOVE_21A0,{7U,3U,0U}}, +{MOVE_21A8,{0U,3U,0U}}, +{MOVE_21A8,{1U,3U,0U}}, +{MOVE_21A8,{2U,3U,0U}}, +{MOVE_21A8,{3U,3U,0U}}, +{MOVE_21A8,{4U,3U,0U}}, +{MOVE_21A8,{5U,3U,0U}}, +{MOVE_21A8,{6U,3U,0U}}, +{MOVE_21A8,{7U,3U,0U}}, +{MOVE_21B0,{0U,3U,0U}}, +{MOVE_21B0,{1U,3U,0U}}, +{MOVE_21B0,{2U,3U,0U}}, +{MOVE_21B0,{3U,3U,0U}}, +{MOVE_21B0,{4U,3U,0U}}, +{MOVE_21B0,{5U,3U,0U}}, +{MOVE_21B0,{6U,3U,0U}}, +{MOVE_21B0,{7U,3U,0U}}, +{MOVE_21B8,{0U,3U,0U}}, +{MOVE_21B9,{0U,3U,0U}}, +{MOVE_21BA,{0U,3U,0U}}, +{MOVE_21BB,{0U,3U,0U}}, +{MOVE_21BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2000,{0U,4U,0U}}, +{MOVE_2000,{1U,4U,0U}}, +{MOVE_2000,{2U,4U,0U}}, +{MOVE_2000,{3U,4U,0U}}, +{MOVE_2000,{4U,4U,0U}}, +{MOVE_2000,{5U,4U,0U}}, +{MOVE_2000,{6U,4U,0U}}, +{MOVE_2000,{7U,4U,0U}}, +{MOVE_2008,{0U,4U,0U}}, +{MOVE_2008,{1U,4U,0U}}, +{MOVE_2008,{2U,4U,0U}}, +{MOVE_2008,{3U,4U,0U}}, +{MOVE_2008,{4U,4U,0U}}, +{MOVE_2008,{5U,4U,0U}}, +{MOVE_2008,{6U,4U,0U}}, +{MOVE_2008,{7U,4U,0U}}, +{MOVE_2010,{0U,4U,0U}}, +{MOVE_2010,{1U,4U,0U}}, +{MOVE_2010,{2U,4U,0U}}, +{MOVE_2010,{3U,4U,0U}}, +{MOVE_2010,{4U,4U,0U}}, +{MOVE_2010,{5U,4U,0U}}, +{MOVE_2010,{6U,4U,0U}}, +{MOVE_2010,{7U,4U,0U}}, +{MOVE_2018,{0U,4U,0U}}, +{MOVE_2018,{1U,4U,0U}}, +{MOVE_2018,{2U,4U,0U}}, +{MOVE_2018,{3U,4U,0U}}, +{MOVE_2018,{4U,4U,0U}}, +{MOVE_2018,{5U,4U,0U}}, +{MOVE_2018,{6U,4U,0U}}, +{MOVE_2018,{7U,4U,0U}}, +{MOVE_2020,{0U,4U,0U}}, +{MOVE_2020,{1U,4U,0U}}, +{MOVE_2020,{2U,4U,0U}}, +{MOVE_2020,{3U,4U,0U}}, +{MOVE_2020,{4U,4U,0U}}, +{MOVE_2020,{5U,4U,0U}}, +{MOVE_2020,{6U,4U,0U}}, +{MOVE_2020,{7U,4U,0U}}, +{MOVE_2028,{0U,4U,0U}}, +{MOVE_2028,{1U,4U,0U}}, +{MOVE_2028,{2U,4U,0U}}, +{MOVE_2028,{3U,4U,0U}}, +{MOVE_2028,{4U,4U,0U}}, +{MOVE_2028,{5U,4U,0U}}, +{MOVE_2028,{6U,4U,0U}}, +{MOVE_2028,{7U,4U,0U}}, +{MOVE_2030,{0U,4U,0U}}, +{MOVE_2030,{1U,4U,0U}}, +{MOVE_2030,{2U,4U,0U}}, +{MOVE_2030,{3U,4U,0U}}, +{MOVE_2030,{4U,4U,0U}}, +{MOVE_2030,{5U,4U,0U}}, +{MOVE_2030,{6U,4U,0U}}, +{MOVE_2030,{7U,4U,0U}}, +{MOVE_2038,{0U,4U,0U}}, +{MOVE_2039,{0U,4U,0U}}, +{MOVE_203A,{0U,4U,0U}}, +{MOVE_203B,{0U,4U,0U}}, +{MOVE_203C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_2040,{0U,4U,0U}}, +{MOVEA_2040,{1U,4U,0U}}, +{MOVEA_2040,{2U,4U,0U}}, +{MOVEA_2040,{3U,4U,0U}}, +{MOVEA_2040,{4U,4U,0U}}, +{MOVEA_2040,{5U,4U,0U}}, +{MOVEA_2040,{6U,4U,0U}}, +{MOVEA_2040,{7U,4U,0U}}, +{MOVEA_2048,{0U,4U,0U}}, +{MOVEA_2048,{1U,4U,0U}}, +{MOVEA_2048,{2U,4U,0U}}, +{MOVEA_2048,{3U,4U,0U}}, +{MOVEA_2048,{4U,4U,0U}}, +{MOVEA_2048,{5U,4U,0U}}, +{MOVEA_2048,{6U,4U,0U}}, +{MOVEA_2048,{7U,4U,0U}}, +{MOVEA_2050,{0U,4U,0U}}, +{MOVEA_2050,{1U,4U,0U}}, +{MOVEA_2050,{2U,4U,0U}}, +{MOVEA_2050,{3U,4U,0U}}, +{MOVEA_2050,{4U,4U,0U}}, +{MOVEA_2050,{5U,4U,0U}}, +{MOVEA_2050,{6U,4U,0U}}, +{MOVEA_2050,{7U,4U,0U}}, +{MOVEA_2058,{0U,4U,0U}}, +{MOVEA_2058,{1U,4U,0U}}, +{MOVEA_2058,{2U,4U,0U}}, +{MOVEA_2058,{3U,4U,0U}}, +{MOVEA_2058,{4U,4U,0U}}, +{MOVEA_2058,{5U,4U,0U}}, +{MOVEA_2058,{6U,4U,0U}}, +{MOVEA_2058,{7U,4U,0U}}, +{MOVEA_2060,{0U,4U,0U}}, +{MOVEA_2060,{1U,4U,0U}}, +{MOVEA_2060,{2U,4U,0U}}, +{MOVEA_2060,{3U,4U,0U}}, +{MOVEA_2060,{4U,4U,0U}}, +{MOVEA_2060,{5U,4U,0U}}, +{MOVEA_2060,{6U,4U,0U}}, +{MOVEA_2060,{7U,4U,0U}}, +{MOVEA_2068,{0U,4U,0U}}, +{MOVEA_2068,{1U,4U,0U}}, +{MOVEA_2068,{2U,4U,0U}}, +{MOVEA_2068,{3U,4U,0U}}, +{MOVEA_2068,{4U,4U,0U}}, +{MOVEA_2068,{5U,4U,0U}}, +{MOVEA_2068,{6U,4U,0U}}, +{MOVEA_2068,{7U,4U,0U}}, +{MOVEA_2070,{0U,4U,0U}}, +{MOVEA_2070,{1U,4U,0U}}, +{MOVEA_2070,{2U,4U,0U}}, +{MOVEA_2070,{3U,4U,0U}}, +{MOVEA_2070,{4U,4U,0U}}, +{MOVEA_2070,{5U,4U,0U}}, +{MOVEA_2070,{6U,4U,0U}}, +{MOVEA_2070,{7U,4U,0U}}, +{MOVEA_2078,{0U,4U,0U}}, +{MOVEA_2079,{0U,4U,0U}}, +{MOVEA_207A,{0U,4U,0U}}, +{MOVEA_207B,{0U,4U,0U}}, +{MOVEA_207C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2080,{0U,4U,0U}}, +{MOVE_2080,{1U,4U,0U}}, +{MOVE_2080,{2U,4U,0U}}, +{MOVE_2080,{3U,4U,0U}}, +{MOVE_2080,{4U,4U,0U}}, +{MOVE_2080,{5U,4U,0U}}, +{MOVE_2080,{6U,4U,0U}}, +{MOVE_2080,{7U,4U,0U}}, +{MOVE_2088,{0U,4U,0U}}, +{MOVE_2088,{1U,4U,0U}}, +{MOVE_2088,{2U,4U,0U}}, +{MOVE_2088,{3U,4U,0U}}, +{MOVE_2088,{4U,4U,0U}}, +{MOVE_2088,{5U,4U,0U}}, +{MOVE_2088,{6U,4U,0U}}, +{MOVE_2088,{7U,4U,0U}}, +{MOVE_2090,{0U,4U,0U}}, +{MOVE_2090,{1U,4U,0U}}, +{MOVE_2090,{2U,4U,0U}}, +{MOVE_2090,{3U,4U,0U}}, +{MOVE_2090,{4U,4U,0U}}, +{MOVE_2090,{5U,4U,0U}}, +{MOVE_2090,{6U,4U,0U}}, +{MOVE_2090,{7U,4U,0U}}, +{MOVE_2098,{0U,4U,0U}}, +{MOVE_2098,{1U,4U,0U}}, +{MOVE_2098,{2U,4U,0U}}, +{MOVE_2098,{3U,4U,0U}}, +{MOVE_2098,{4U,4U,0U}}, +{MOVE_2098,{5U,4U,0U}}, +{MOVE_2098,{6U,4U,0U}}, +{MOVE_2098,{7U,4U,0U}}, +{MOVE_20A0,{0U,4U,0U}}, +{MOVE_20A0,{1U,4U,0U}}, +{MOVE_20A0,{2U,4U,0U}}, +{MOVE_20A0,{3U,4U,0U}}, +{MOVE_20A0,{4U,4U,0U}}, +{MOVE_20A0,{5U,4U,0U}}, +{MOVE_20A0,{6U,4U,0U}}, +{MOVE_20A0,{7U,4U,0U}}, +{MOVE_20A8,{0U,4U,0U}}, +{MOVE_20A8,{1U,4U,0U}}, +{MOVE_20A8,{2U,4U,0U}}, +{MOVE_20A8,{3U,4U,0U}}, +{MOVE_20A8,{4U,4U,0U}}, +{MOVE_20A8,{5U,4U,0U}}, +{MOVE_20A8,{6U,4U,0U}}, +{MOVE_20A8,{7U,4U,0U}}, +{MOVE_20B0,{0U,4U,0U}}, +{MOVE_20B0,{1U,4U,0U}}, +{MOVE_20B0,{2U,4U,0U}}, +{MOVE_20B0,{3U,4U,0U}}, +{MOVE_20B0,{4U,4U,0U}}, +{MOVE_20B0,{5U,4U,0U}}, +{MOVE_20B0,{6U,4U,0U}}, +{MOVE_20B0,{7U,4U,0U}}, +{MOVE_20B8,{0U,4U,0U}}, +{MOVE_20B9,{0U,4U,0U}}, +{MOVE_20BA,{0U,4U,0U}}, +{MOVE_20BB,{0U,4U,0U}}, +{MOVE_20BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_20C0,{0U,4U,0U}}, +{MOVE_20C0,{1U,4U,0U}}, +{MOVE_20C0,{2U,4U,0U}}, +{MOVE_20C0,{3U,4U,0U}}, +{MOVE_20C0,{4U,4U,0U}}, +{MOVE_20C0,{5U,4U,0U}}, +{MOVE_20C0,{6U,4U,0U}}, +{MOVE_20C0,{7U,4U,0U}}, +{MOVE_20C8,{0U,4U,0U}}, +{MOVE_20C8,{1U,4U,0U}}, +{MOVE_20C8,{2U,4U,0U}}, +{MOVE_20C8,{3U,4U,0U}}, +{MOVE_20C8,{4U,4U,0U}}, +{MOVE_20C8,{5U,4U,0U}}, +{MOVE_20C8,{6U,4U,0U}}, +{MOVE_20C8,{7U,4U,0U}}, +{MOVE_20D0,{0U,4U,0U}}, +{MOVE_20D0,{1U,4U,0U}}, +{MOVE_20D0,{2U,4U,0U}}, +{MOVE_20D0,{3U,4U,0U}}, +{MOVE_20D0,{4U,4U,0U}}, +{MOVE_20D0,{5U,4U,0U}}, +{MOVE_20D0,{6U,4U,0U}}, +{MOVE_20D0,{7U,4U,0U}}, +{MOVE_20D8,{0U,4U,0U}}, +{MOVE_20D8,{1U,4U,0U}}, +{MOVE_20D8,{2U,4U,0U}}, +{MOVE_20D8,{3U,4U,0U}}, +{MOVE_20D8,{4U,4U,0U}}, +{MOVE_20D8,{5U,4U,0U}}, +{MOVE_20D8,{6U,4U,0U}}, +{MOVE_20D8,{7U,4U,0U}}, +{MOVE_20E0,{0U,4U,0U}}, +{MOVE_20E0,{1U,4U,0U}}, +{MOVE_20E0,{2U,4U,0U}}, +{MOVE_20E0,{3U,4U,0U}}, +{MOVE_20E0,{4U,4U,0U}}, +{MOVE_20E0,{5U,4U,0U}}, +{MOVE_20E0,{6U,4U,0U}}, +{MOVE_20E0,{7U,4U,0U}}, +{MOVE_20E8,{0U,4U,0U}}, +{MOVE_20E8,{1U,4U,0U}}, +{MOVE_20E8,{2U,4U,0U}}, +{MOVE_20E8,{3U,4U,0U}}, +{MOVE_20E8,{4U,4U,0U}}, +{MOVE_20E8,{5U,4U,0U}}, +{MOVE_20E8,{6U,4U,0U}}, +{MOVE_20E8,{7U,4U,0U}}, +{MOVE_20F0,{0U,4U,0U}}, +{MOVE_20F0,{1U,4U,0U}}, +{MOVE_20F0,{2U,4U,0U}}, +{MOVE_20F0,{3U,4U,0U}}, +{MOVE_20F0,{4U,4U,0U}}, +{MOVE_20F0,{5U,4U,0U}}, +{MOVE_20F0,{6U,4U,0U}}, +{MOVE_20F0,{7U,4U,0U}}, +{MOVE_20F8,{0U,4U,0U}}, +{MOVE_20F9,{0U,4U,0U}}, +{MOVE_20FA,{0U,4U,0U}}, +{MOVE_20FB,{0U,4U,0U}}, +{MOVE_20FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2100,{0U,4U,0U}}, +{MOVE_2100,{1U,4U,0U}}, +{MOVE_2100,{2U,4U,0U}}, +{MOVE_2100,{3U,4U,0U}}, +{MOVE_2100,{4U,4U,0U}}, +{MOVE_2100,{5U,4U,0U}}, +{MOVE_2100,{6U,4U,0U}}, +{MOVE_2100,{7U,4U,0U}}, +{MOVE_2108,{0U,4U,0U}}, +{MOVE_2108,{1U,4U,0U}}, +{MOVE_2108,{2U,4U,0U}}, +{MOVE_2108,{3U,4U,0U}}, +{MOVE_2108,{4U,4U,0U}}, +{MOVE_2108,{5U,4U,0U}}, +{MOVE_2108,{6U,4U,0U}}, +{MOVE_2108,{7U,4U,0U}}, +{MOVE_2110,{0U,4U,0U}}, +{MOVE_2110,{1U,4U,0U}}, +{MOVE_2110,{2U,4U,0U}}, +{MOVE_2110,{3U,4U,0U}}, +{MOVE_2110,{4U,4U,0U}}, +{MOVE_2110,{5U,4U,0U}}, +{MOVE_2110,{6U,4U,0U}}, +{MOVE_2110,{7U,4U,0U}}, +{MOVE_2118,{0U,4U,0U}}, +{MOVE_2118,{1U,4U,0U}}, +{MOVE_2118,{2U,4U,0U}}, +{MOVE_2118,{3U,4U,0U}}, +{MOVE_2118,{4U,4U,0U}}, +{MOVE_2118,{5U,4U,0U}}, +{MOVE_2118,{6U,4U,0U}}, +{MOVE_2118,{7U,4U,0U}}, +{MOVE_2120,{0U,4U,0U}}, +{MOVE_2120,{1U,4U,0U}}, +{MOVE_2120,{2U,4U,0U}}, +{MOVE_2120,{3U,4U,0U}}, +{MOVE_2120,{4U,4U,0U}}, +{MOVE_2120,{5U,4U,0U}}, +{MOVE_2120,{6U,4U,0U}}, +{MOVE_2120,{7U,4U,0U}}, +{MOVE_2128,{0U,4U,0U}}, +{MOVE_2128,{1U,4U,0U}}, +{MOVE_2128,{2U,4U,0U}}, +{MOVE_2128,{3U,4U,0U}}, +{MOVE_2128,{4U,4U,0U}}, +{MOVE_2128,{5U,4U,0U}}, +{MOVE_2128,{6U,4U,0U}}, +{MOVE_2128,{7U,4U,0U}}, +{MOVE_2130,{0U,4U,0U}}, +{MOVE_2130,{1U,4U,0U}}, +{MOVE_2130,{2U,4U,0U}}, +{MOVE_2130,{3U,4U,0U}}, +{MOVE_2130,{4U,4U,0U}}, +{MOVE_2130,{5U,4U,0U}}, +{MOVE_2130,{6U,4U,0U}}, +{MOVE_2130,{7U,4U,0U}}, +{MOVE_2138,{0U,4U,0U}}, +{MOVE_2139,{0U,4U,0U}}, +{MOVE_213A,{0U,4U,0U}}, +{MOVE_213B,{0U,4U,0U}}, +{MOVE_213C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2140,{0U,4U,0U}}, +{MOVE_2140,{1U,4U,0U}}, +{MOVE_2140,{2U,4U,0U}}, +{MOVE_2140,{3U,4U,0U}}, +{MOVE_2140,{4U,4U,0U}}, +{MOVE_2140,{5U,4U,0U}}, +{MOVE_2140,{6U,4U,0U}}, +{MOVE_2140,{7U,4U,0U}}, +{MOVE_2148,{0U,4U,0U}}, +{MOVE_2148,{1U,4U,0U}}, +{MOVE_2148,{2U,4U,0U}}, +{MOVE_2148,{3U,4U,0U}}, +{MOVE_2148,{4U,4U,0U}}, +{MOVE_2148,{5U,4U,0U}}, +{MOVE_2148,{6U,4U,0U}}, +{MOVE_2148,{7U,4U,0U}}, +{MOVE_2150,{0U,4U,0U}}, +{MOVE_2150,{1U,4U,0U}}, +{MOVE_2150,{2U,4U,0U}}, +{MOVE_2150,{3U,4U,0U}}, +{MOVE_2150,{4U,4U,0U}}, +{MOVE_2150,{5U,4U,0U}}, +{MOVE_2150,{6U,4U,0U}}, +{MOVE_2150,{7U,4U,0U}}, +{MOVE_2158,{0U,4U,0U}}, +{MOVE_2158,{1U,4U,0U}}, +{MOVE_2158,{2U,4U,0U}}, +{MOVE_2158,{3U,4U,0U}}, +{MOVE_2158,{4U,4U,0U}}, +{MOVE_2158,{5U,4U,0U}}, +{MOVE_2158,{6U,4U,0U}}, +{MOVE_2158,{7U,4U,0U}}, +{MOVE_2160,{0U,4U,0U}}, +{MOVE_2160,{1U,4U,0U}}, +{MOVE_2160,{2U,4U,0U}}, +{MOVE_2160,{3U,4U,0U}}, +{MOVE_2160,{4U,4U,0U}}, +{MOVE_2160,{5U,4U,0U}}, +{MOVE_2160,{6U,4U,0U}}, +{MOVE_2160,{7U,4U,0U}}, +{MOVE_2168,{0U,4U,0U}}, +{MOVE_2168,{1U,4U,0U}}, +{MOVE_2168,{2U,4U,0U}}, +{MOVE_2168,{3U,4U,0U}}, +{MOVE_2168,{4U,4U,0U}}, +{MOVE_2168,{5U,4U,0U}}, +{MOVE_2168,{6U,4U,0U}}, +{MOVE_2168,{7U,4U,0U}}, +{MOVE_2170,{0U,4U,0U}}, +{MOVE_2170,{1U,4U,0U}}, +{MOVE_2170,{2U,4U,0U}}, +{MOVE_2170,{3U,4U,0U}}, +{MOVE_2170,{4U,4U,0U}}, +{MOVE_2170,{5U,4U,0U}}, +{MOVE_2170,{6U,4U,0U}}, +{MOVE_2170,{7U,4U,0U}}, +{MOVE_2178,{0U,4U,0U}}, +{MOVE_2179,{0U,4U,0U}}, +{MOVE_217A,{0U,4U,0U}}, +{MOVE_217B,{0U,4U,0U}}, +{MOVE_217C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2180,{0U,4U,0U}}, +{MOVE_2180,{1U,4U,0U}}, +{MOVE_2180,{2U,4U,0U}}, +{MOVE_2180,{3U,4U,0U}}, +{MOVE_2180,{4U,4U,0U}}, +{MOVE_2180,{5U,4U,0U}}, +{MOVE_2180,{6U,4U,0U}}, +{MOVE_2180,{7U,4U,0U}}, +{MOVE_2188,{0U,4U,0U}}, +{MOVE_2188,{1U,4U,0U}}, +{MOVE_2188,{2U,4U,0U}}, +{MOVE_2188,{3U,4U,0U}}, +{MOVE_2188,{4U,4U,0U}}, +{MOVE_2188,{5U,4U,0U}}, +{MOVE_2188,{6U,4U,0U}}, +{MOVE_2188,{7U,4U,0U}}, +{MOVE_2190,{0U,4U,0U}}, +{MOVE_2190,{1U,4U,0U}}, +{MOVE_2190,{2U,4U,0U}}, +{MOVE_2190,{3U,4U,0U}}, +{MOVE_2190,{4U,4U,0U}}, +{MOVE_2190,{5U,4U,0U}}, +{MOVE_2190,{6U,4U,0U}}, +{MOVE_2190,{7U,4U,0U}}, +{MOVE_2198,{0U,4U,0U}}, +{MOVE_2198,{1U,4U,0U}}, +{MOVE_2198,{2U,4U,0U}}, +{MOVE_2198,{3U,4U,0U}}, +{MOVE_2198,{4U,4U,0U}}, +{MOVE_2198,{5U,4U,0U}}, +{MOVE_2198,{6U,4U,0U}}, +{MOVE_2198,{7U,4U,0U}}, +{MOVE_21A0,{0U,4U,0U}}, +{MOVE_21A0,{1U,4U,0U}}, +{MOVE_21A0,{2U,4U,0U}}, +{MOVE_21A0,{3U,4U,0U}}, +{MOVE_21A0,{4U,4U,0U}}, +{MOVE_21A0,{5U,4U,0U}}, +{MOVE_21A0,{6U,4U,0U}}, +{MOVE_21A0,{7U,4U,0U}}, +{MOVE_21A8,{0U,4U,0U}}, +{MOVE_21A8,{1U,4U,0U}}, +{MOVE_21A8,{2U,4U,0U}}, +{MOVE_21A8,{3U,4U,0U}}, +{MOVE_21A8,{4U,4U,0U}}, +{MOVE_21A8,{5U,4U,0U}}, +{MOVE_21A8,{6U,4U,0U}}, +{MOVE_21A8,{7U,4U,0U}}, +{MOVE_21B0,{0U,4U,0U}}, +{MOVE_21B0,{1U,4U,0U}}, +{MOVE_21B0,{2U,4U,0U}}, +{MOVE_21B0,{3U,4U,0U}}, +{MOVE_21B0,{4U,4U,0U}}, +{MOVE_21B0,{5U,4U,0U}}, +{MOVE_21B0,{6U,4U,0U}}, +{MOVE_21B0,{7U,4U,0U}}, +{MOVE_21B8,{0U,4U,0U}}, +{MOVE_21B9,{0U,4U,0U}}, +{MOVE_21BA,{0U,4U,0U}}, +{MOVE_21BB,{0U,4U,0U}}, +{MOVE_21BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2000,{0U,5U,0U}}, +{MOVE_2000,{1U,5U,0U}}, +{MOVE_2000,{2U,5U,0U}}, +{MOVE_2000,{3U,5U,0U}}, +{MOVE_2000,{4U,5U,0U}}, +{MOVE_2000,{5U,5U,0U}}, +{MOVE_2000,{6U,5U,0U}}, +{MOVE_2000,{7U,5U,0U}}, +{MOVE_2008,{0U,5U,0U}}, +{MOVE_2008,{1U,5U,0U}}, +{MOVE_2008,{2U,5U,0U}}, +{MOVE_2008,{3U,5U,0U}}, +{MOVE_2008,{4U,5U,0U}}, +{MOVE_2008,{5U,5U,0U}}, +{MOVE_2008,{6U,5U,0U}}, +{MOVE_2008,{7U,5U,0U}}, +{MOVE_2010,{0U,5U,0U}}, +{MOVE_2010,{1U,5U,0U}}, +{MOVE_2010,{2U,5U,0U}}, +{MOVE_2010,{3U,5U,0U}}, +{MOVE_2010,{4U,5U,0U}}, +{MOVE_2010,{5U,5U,0U}}, +{MOVE_2010,{6U,5U,0U}}, +{MOVE_2010,{7U,5U,0U}}, +{MOVE_2018,{0U,5U,0U}}, +{MOVE_2018,{1U,5U,0U}}, +{MOVE_2018,{2U,5U,0U}}, +{MOVE_2018,{3U,5U,0U}}, +{MOVE_2018,{4U,5U,0U}}, +{MOVE_2018,{5U,5U,0U}}, +{MOVE_2018,{6U,5U,0U}}, +{MOVE_2018,{7U,5U,0U}}, +{MOVE_2020,{0U,5U,0U}}, +{MOVE_2020,{1U,5U,0U}}, +{MOVE_2020,{2U,5U,0U}}, +{MOVE_2020,{3U,5U,0U}}, +{MOVE_2020,{4U,5U,0U}}, +{MOVE_2020,{5U,5U,0U}}, +{MOVE_2020,{6U,5U,0U}}, +{MOVE_2020,{7U,5U,0U}}, +{MOVE_2028,{0U,5U,0U}}, +{MOVE_2028,{1U,5U,0U}}, +{MOVE_2028,{2U,5U,0U}}, +{MOVE_2028,{3U,5U,0U}}, +{MOVE_2028,{4U,5U,0U}}, +{MOVE_2028,{5U,5U,0U}}, +{MOVE_2028,{6U,5U,0U}}, +{MOVE_2028,{7U,5U,0U}}, +{MOVE_2030,{0U,5U,0U}}, +{MOVE_2030,{1U,5U,0U}}, +{MOVE_2030,{2U,5U,0U}}, +{MOVE_2030,{3U,5U,0U}}, +{MOVE_2030,{4U,5U,0U}}, +{MOVE_2030,{5U,5U,0U}}, +{MOVE_2030,{6U,5U,0U}}, +{MOVE_2030,{7U,5U,0U}}, +{MOVE_2038,{0U,5U,0U}}, +{MOVE_2039,{0U,5U,0U}}, +{MOVE_203A,{0U,5U,0U}}, +{MOVE_203B,{0U,5U,0U}}, +{MOVE_203C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_2040,{0U,5U,0U}}, +{MOVEA_2040,{1U,5U,0U}}, +{MOVEA_2040,{2U,5U,0U}}, +{MOVEA_2040,{3U,5U,0U}}, +{MOVEA_2040,{4U,5U,0U}}, +{MOVEA_2040,{5U,5U,0U}}, +{MOVEA_2040,{6U,5U,0U}}, +{MOVEA_2040,{7U,5U,0U}}, +{MOVEA_2048,{0U,5U,0U}}, +{MOVEA_2048,{1U,5U,0U}}, +{MOVEA_2048,{2U,5U,0U}}, +{MOVEA_2048,{3U,5U,0U}}, +{MOVEA_2048,{4U,5U,0U}}, +{MOVEA_2048,{5U,5U,0U}}, +{MOVEA_2048,{6U,5U,0U}}, +{MOVEA_2048,{7U,5U,0U}}, +{MOVEA_2050,{0U,5U,0U}}, +{MOVEA_2050,{1U,5U,0U}}, +{MOVEA_2050,{2U,5U,0U}}, +{MOVEA_2050,{3U,5U,0U}}, +{MOVEA_2050,{4U,5U,0U}}, +{MOVEA_2050,{5U,5U,0U}}, +{MOVEA_2050,{6U,5U,0U}}, +{MOVEA_2050,{7U,5U,0U}}, +{MOVEA_2058,{0U,5U,0U}}, +{MOVEA_2058,{1U,5U,0U}}, +{MOVEA_2058,{2U,5U,0U}}, +{MOVEA_2058,{3U,5U,0U}}, +{MOVEA_2058,{4U,5U,0U}}, +{MOVEA_2058,{5U,5U,0U}}, +{MOVEA_2058,{6U,5U,0U}}, +{MOVEA_2058,{7U,5U,0U}}, +{MOVEA_2060,{0U,5U,0U}}, +{MOVEA_2060,{1U,5U,0U}}, +{MOVEA_2060,{2U,5U,0U}}, +{MOVEA_2060,{3U,5U,0U}}, +{MOVEA_2060,{4U,5U,0U}}, +{MOVEA_2060,{5U,5U,0U}}, +{MOVEA_2060,{6U,5U,0U}}, +{MOVEA_2060,{7U,5U,0U}}, +{MOVEA_2068,{0U,5U,0U}}, +{MOVEA_2068,{1U,5U,0U}}, +{MOVEA_2068,{2U,5U,0U}}, +{MOVEA_2068,{3U,5U,0U}}, +{MOVEA_2068,{4U,5U,0U}}, +{MOVEA_2068,{5U,5U,0U}}, +{MOVEA_2068,{6U,5U,0U}}, +{MOVEA_2068,{7U,5U,0U}}, +{MOVEA_2070,{0U,5U,0U}}, +{MOVEA_2070,{1U,5U,0U}}, +{MOVEA_2070,{2U,5U,0U}}, +{MOVEA_2070,{3U,5U,0U}}, +{MOVEA_2070,{4U,5U,0U}}, +{MOVEA_2070,{5U,5U,0U}}, +{MOVEA_2070,{6U,5U,0U}}, +{MOVEA_2070,{7U,5U,0U}}, +{MOVEA_2078,{0U,5U,0U}}, +{MOVEA_2079,{0U,5U,0U}}, +{MOVEA_207A,{0U,5U,0U}}, +{MOVEA_207B,{0U,5U,0U}}, +{MOVEA_207C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2080,{0U,5U,0U}}, +{MOVE_2080,{1U,5U,0U}}, +{MOVE_2080,{2U,5U,0U}}, +{MOVE_2080,{3U,5U,0U}}, +{MOVE_2080,{4U,5U,0U}}, +{MOVE_2080,{5U,5U,0U}}, +{MOVE_2080,{6U,5U,0U}}, +{MOVE_2080,{7U,5U,0U}}, +{MOVE_2088,{0U,5U,0U}}, +{MOVE_2088,{1U,5U,0U}}, +{MOVE_2088,{2U,5U,0U}}, +{MOVE_2088,{3U,5U,0U}}, +{MOVE_2088,{4U,5U,0U}}, +{MOVE_2088,{5U,5U,0U}}, +{MOVE_2088,{6U,5U,0U}}, +{MOVE_2088,{7U,5U,0U}}, +{MOVE_2090,{0U,5U,0U}}, +{MOVE_2090,{1U,5U,0U}}, +{MOVE_2090,{2U,5U,0U}}, +{MOVE_2090,{3U,5U,0U}}, +{MOVE_2090,{4U,5U,0U}}, +{MOVE_2090,{5U,5U,0U}}, +{MOVE_2090,{6U,5U,0U}}, +{MOVE_2090,{7U,5U,0U}}, +{MOVE_2098,{0U,5U,0U}}, +{MOVE_2098,{1U,5U,0U}}, +{MOVE_2098,{2U,5U,0U}}, +{MOVE_2098,{3U,5U,0U}}, +{MOVE_2098,{4U,5U,0U}}, +{MOVE_2098,{5U,5U,0U}}, +{MOVE_2098,{6U,5U,0U}}, +{MOVE_2098,{7U,5U,0U}}, +{MOVE_20A0,{0U,5U,0U}}, +{MOVE_20A0,{1U,5U,0U}}, +{MOVE_20A0,{2U,5U,0U}}, +{MOVE_20A0,{3U,5U,0U}}, +{MOVE_20A0,{4U,5U,0U}}, +{MOVE_20A0,{5U,5U,0U}}, +{MOVE_20A0,{6U,5U,0U}}, +{MOVE_20A0,{7U,5U,0U}}, +{MOVE_20A8,{0U,5U,0U}}, +{MOVE_20A8,{1U,5U,0U}}, +{MOVE_20A8,{2U,5U,0U}}, +{MOVE_20A8,{3U,5U,0U}}, +{MOVE_20A8,{4U,5U,0U}}, +{MOVE_20A8,{5U,5U,0U}}, +{MOVE_20A8,{6U,5U,0U}}, +{MOVE_20A8,{7U,5U,0U}}, +{MOVE_20B0,{0U,5U,0U}}, +{MOVE_20B0,{1U,5U,0U}}, +{MOVE_20B0,{2U,5U,0U}}, +{MOVE_20B0,{3U,5U,0U}}, +{MOVE_20B0,{4U,5U,0U}}, +{MOVE_20B0,{5U,5U,0U}}, +{MOVE_20B0,{6U,5U,0U}}, +{MOVE_20B0,{7U,5U,0U}}, +{MOVE_20B8,{0U,5U,0U}}, +{MOVE_20B9,{0U,5U,0U}}, +{MOVE_20BA,{0U,5U,0U}}, +{MOVE_20BB,{0U,5U,0U}}, +{MOVE_20BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_20C0,{0U,5U,0U}}, +{MOVE_20C0,{1U,5U,0U}}, +{MOVE_20C0,{2U,5U,0U}}, +{MOVE_20C0,{3U,5U,0U}}, +{MOVE_20C0,{4U,5U,0U}}, +{MOVE_20C0,{5U,5U,0U}}, +{MOVE_20C0,{6U,5U,0U}}, +{MOVE_20C0,{7U,5U,0U}}, +{MOVE_20C8,{0U,5U,0U}}, +{MOVE_20C8,{1U,5U,0U}}, +{MOVE_20C8,{2U,5U,0U}}, +{MOVE_20C8,{3U,5U,0U}}, +{MOVE_20C8,{4U,5U,0U}}, +{MOVE_20C8,{5U,5U,0U}}, +{MOVE_20C8,{6U,5U,0U}}, +{MOVE_20C8,{7U,5U,0U}}, +{MOVE_20D0,{0U,5U,0U}}, +{MOVE_20D0,{1U,5U,0U}}, +{MOVE_20D0,{2U,5U,0U}}, +{MOVE_20D0,{3U,5U,0U}}, +{MOVE_20D0,{4U,5U,0U}}, +{MOVE_20D0,{5U,5U,0U}}, +{MOVE_20D0,{6U,5U,0U}}, +{MOVE_20D0,{7U,5U,0U}}, +{MOVE_20D8,{0U,5U,0U}}, +{MOVE_20D8,{1U,5U,0U}}, +{MOVE_20D8,{2U,5U,0U}}, +{MOVE_20D8,{3U,5U,0U}}, +{MOVE_20D8,{4U,5U,0U}}, +{MOVE_20D8,{5U,5U,0U}}, +{MOVE_20D8,{6U,5U,0U}}, +{MOVE_20D8,{7U,5U,0U}}, +{MOVE_20E0,{0U,5U,0U}}, +{MOVE_20E0,{1U,5U,0U}}, +{MOVE_20E0,{2U,5U,0U}}, +{MOVE_20E0,{3U,5U,0U}}, +{MOVE_20E0,{4U,5U,0U}}, +{MOVE_20E0,{5U,5U,0U}}, +{MOVE_20E0,{6U,5U,0U}}, +{MOVE_20E0,{7U,5U,0U}}, +{MOVE_20E8,{0U,5U,0U}}, +{MOVE_20E8,{1U,5U,0U}}, +{MOVE_20E8,{2U,5U,0U}}, +{MOVE_20E8,{3U,5U,0U}}, +{MOVE_20E8,{4U,5U,0U}}, +{MOVE_20E8,{5U,5U,0U}}, +{MOVE_20E8,{6U,5U,0U}}, +{MOVE_20E8,{7U,5U,0U}}, +{MOVE_20F0,{0U,5U,0U}}, +{MOVE_20F0,{1U,5U,0U}}, +{MOVE_20F0,{2U,5U,0U}}, +{MOVE_20F0,{3U,5U,0U}}, +{MOVE_20F0,{4U,5U,0U}}, +{MOVE_20F0,{5U,5U,0U}}, +{MOVE_20F0,{6U,5U,0U}}, +{MOVE_20F0,{7U,5U,0U}}, +{MOVE_20F8,{0U,5U,0U}}, +{MOVE_20F9,{0U,5U,0U}}, +{MOVE_20FA,{0U,5U,0U}}, +{MOVE_20FB,{0U,5U,0U}}, +{MOVE_20FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2100,{0U,5U,0U}}, +{MOVE_2100,{1U,5U,0U}}, +{MOVE_2100,{2U,5U,0U}}, +{MOVE_2100,{3U,5U,0U}}, +{MOVE_2100,{4U,5U,0U}}, +{MOVE_2100,{5U,5U,0U}}, +{MOVE_2100,{6U,5U,0U}}, +{MOVE_2100,{7U,5U,0U}}, +{MOVE_2108,{0U,5U,0U}}, +{MOVE_2108,{1U,5U,0U}}, +{MOVE_2108,{2U,5U,0U}}, +{MOVE_2108,{3U,5U,0U}}, +{MOVE_2108,{4U,5U,0U}}, +{MOVE_2108,{5U,5U,0U}}, +{MOVE_2108,{6U,5U,0U}}, +{MOVE_2108,{7U,5U,0U}}, +{MOVE_2110,{0U,5U,0U}}, +{MOVE_2110,{1U,5U,0U}}, +{MOVE_2110,{2U,5U,0U}}, +{MOVE_2110,{3U,5U,0U}}, +{MOVE_2110,{4U,5U,0U}}, +{MOVE_2110,{5U,5U,0U}}, +{MOVE_2110,{6U,5U,0U}}, +{MOVE_2110,{7U,5U,0U}}, +{MOVE_2118,{0U,5U,0U}}, +{MOVE_2118,{1U,5U,0U}}, +{MOVE_2118,{2U,5U,0U}}, +{MOVE_2118,{3U,5U,0U}}, +{MOVE_2118,{4U,5U,0U}}, +{MOVE_2118,{5U,5U,0U}}, +{MOVE_2118,{6U,5U,0U}}, +{MOVE_2118,{7U,5U,0U}}, +{MOVE_2120,{0U,5U,0U}}, +{MOVE_2120,{1U,5U,0U}}, +{MOVE_2120,{2U,5U,0U}}, +{MOVE_2120,{3U,5U,0U}}, +{MOVE_2120,{4U,5U,0U}}, +{MOVE_2120,{5U,5U,0U}}, +{MOVE_2120,{6U,5U,0U}}, +{MOVE_2120,{7U,5U,0U}}, +{MOVE_2128,{0U,5U,0U}}, +{MOVE_2128,{1U,5U,0U}}, +{MOVE_2128,{2U,5U,0U}}, +{MOVE_2128,{3U,5U,0U}}, +{MOVE_2128,{4U,5U,0U}}, +{MOVE_2128,{5U,5U,0U}}, +{MOVE_2128,{6U,5U,0U}}, +{MOVE_2128,{7U,5U,0U}}, +{MOVE_2130,{0U,5U,0U}}, +{MOVE_2130,{1U,5U,0U}}, +{MOVE_2130,{2U,5U,0U}}, +{MOVE_2130,{3U,5U,0U}}, +{MOVE_2130,{4U,5U,0U}}, +{MOVE_2130,{5U,5U,0U}}, +{MOVE_2130,{6U,5U,0U}}, +{MOVE_2130,{7U,5U,0U}}, +{MOVE_2138,{0U,5U,0U}}, +{MOVE_2139,{0U,5U,0U}}, +{MOVE_213A,{0U,5U,0U}}, +{MOVE_213B,{0U,5U,0U}}, +{MOVE_213C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2140,{0U,5U,0U}}, +{MOVE_2140,{1U,5U,0U}}, +{MOVE_2140,{2U,5U,0U}}, +{MOVE_2140,{3U,5U,0U}}, +{MOVE_2140,{4U,5U,0U}}, +{MOVE_2140,{5U,5U,0U}}, +{MOVE_2140,{6U,5U,0U}}, +{MOVE_2140,{7U,5U,0U}}, +{MOVE_2148,{0U,5U,0U}}, +{MOVE_2148,{1U,5U,0U}}, +{MOVE_2148,{2U,5U,0U}}, +{MOVE_2148,{3U,5U,0U}}, +{MOVE_2148,{4U,5U,0U}}, +{MOVE_2148,{5U,5U,0U}}, +{MOVE_2148,{6U,5U,0U}}, +{MOVE_2148,{7U,5U,0U}}, +{MOVE_2150,{0U,5U,0U}}, +{MOVE_2150,{1U,5U,0U}}, +{MOVE_2150,{2U,5U,0U}}, +{MOVE_2150,{3U,5U,0U}}, +{MOVE_2150,{4U,5U,0U}}, +{MOVE_2150,{5U,5U,0U}}, +{MOVE_2150,{6U,5U,0U}}, +{MOVE_2150,{7U,5U,0U}}, +{MOVE_2158,{0U,5U,0U}}, +{MOVE_2158,{1U,5U,0U}}, +{MOVE_2158,{2U,5U,0U}}, +{MOVE_2158,{3U,5U,0U}}, +{MOVE_2158,{4U,5U,0U}}, +{MOVE_2158,{5U,5U,0U}}, +{MOVE_2158,{6U,5U,0U}}, +{MOVE_2158,{7U,5U,0U}}, +{MOVE_2160,{0U,5U,0U}}, +{MOVE_2160,{1U,5U,0U}}, +{MOVE_2160,{2U,5U,0U}}, +{MOVE_2160,{3U,5U,0U}}, +{MOVE_2160,{4U,5U,0U}}, +{MOVE_2160,{5U,5U,0U}}, +{MOVE_2160,{6U,5U,0U}}, +{MOVE_2160,{7U,5U,0U}}, +{MOVE_2168,{0U,5U,0U}}, +{MOVE_2168,{1U,5U,0U}}, +{MOVE_2168,{2U,5U,0U}}, +{MOVE_2168,{3U,5U,0U}}, +{MOVE_2168,{4U,5U,0U}}, +{MOVE_2168,{5U,5U,0U}}, +{MOVE_2168,{6U,5U,0U}}, +{MOVE_2168,{7U,5U,0U}}, +{MOVE_2170,{0U,5U,0U}}, +{MOVE_2170,{1U,5U,0U}}, +{MOVE_2170,{2U,5U,0U}}, +{MOVE_2170,{3U,5U,0U}}, +{MOVE_2170,{4U,5U,0U}}, +{MOVE_2170,{5U,5U,0U}}, +{MOVE_2170,{6U,5U,0U}}, +{MOVE_2170,{7U,5U,0U}}, +{MOVE_2178,{0U,5U,0U}}, +{MOVE_2179,{0U,5U,0U}}, +{MOVE_217A,{0U,5U,0U}}, +{MOVE_217B,{0U,5U,0U}}, +{MOVE_217C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2180,{0U,5U,0U}}, +{MOVE_2180,{1U,5U,0U}}, +{MOVE_2180,{2U,5U,0U}}, +{MOVE_2180,{3U,5U,0U}}, +{MOVE_2180,{4U,5U,0U}}, +{MOVE_2180,{5U,5U,0U}}, +{MOVE_2180,{6U,5U,0U}}, +{MOVE_2180,{7U,5U,0U}}, +{MOVE_2188,{0U,5U,0U}}, +{MOVE_2188,{1U,5U,0U}}, +{MOVE_2188,{2U,5U,0U}}, +{MOVE_2188,{3U,5U,0U}}, +{MOVE_2188,{4U,5U,0U}}, +{MOVE_2188,{5U,5U,0U}}, +{MOVE_2188,{6U,5U,0U}}, +{MOVE_2188,{7U,5U,0U}}, +{MOVE_2190,{0U,5U,0U}}, +{MOVE_2190,{1U,5U,0U}}, +{MOVE_2190,{2U,5U,0U}}, +{MOVE_2190,{3U,5U,0U}}, +{MOVE_2190,{4U,5U,0U}}, +{MOVE_2190,{5U,5U,0U}}, +{MOVE_2190,{6U,5U,0U}}, +{MOVE_2190,{7U,5U,0U}}, +{MOVE_2198,{0U,5U,0U}}, +{MOVE_2198,{1U,5U,0U}}, +{MOVE_2198,{2U,5U,0U}}, +{MOVE_2198,{3U,5U,0U}}, +{MOVE_2198,{4U,5U,0U}}, +{MOVE_2198,{5U,5U,0U}}, +{MOVE_2198,{6U,5U,0U}}, +{MOVE_2198,{7U,5U,0U}}, +{MOVE_21A0,{0U,5U,0U}}, +{MOVE_21A0,{1U,5U,0U}}, +{MOVE_21A0,{2U,5U,0U}}, +{MOVE_21A0,{3U,5U,0U}}, +{MOVE_21A0,{4U,5U,0U}}, +{MOVE_21A0,{5U,5U,0U}}, +{MOVE_21A0,{6U,5U,0U}}, +{MOVE_21A0,{7U,5U,0U}}, +{MOVE_21A8,{0U,5U,0U}}, +{MOVE_21A8,{1U,5U,0U}}, +{MOVE_21A8,{2U,5U,0U}}, +{MOVE_21A8,{3U,5U,0U}}, +{MOVE_21A8,{4U,5U,0U}}, +{MOVE_21A8,{5U,5U,0U}}, +{MOVE_21A8,{6U,5U,0U}}, +{MOVE_21A8,{7U,5U,0U}}, +{MOVE_21B0,{0U,5U,0U}}, +{MOVE_21B0,{1U,5U,0U}}, +{MOVE_21B0,{2U,5U,0U}}, +{MOVE_21B0,{3U,5U,0U}}, +{MOVE_21B0,{4U,5U,0U}}, +{MOVE_21B0,{5U,5U,0U}}, +{MOVE_21B0,{6U,5U,0U}}, +{MOVE_21B0,{7U,5U,0U}}, +{MOVE_21B8,{0U,5U,0U}}, +{MOVE_21B9,{0U,5U,0U}}, +{MOVE_21BA,{0U,5U,0U}}, +{MOVE_21BB,{0U,5U,0U}}, +{MOVE_21BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2000,{0U,6U,0U}}, +{MOVE_2000,{1U,6U,0U}}, +{MOVE_2000,{2U,6U,0U}}, +{MOVE_2000,{3U,6U,0U}}, +{MOVE_2000,{4U,6U,0U}}, +{MOVE_2000,{5U,6U,0U}}, +{MOVE_2000,{6U,6U,0U}}, +{MOVE_2000,{7U,6U,0U}}, +{MOVE_2008,{0U,6U,0U}}, +{MOVE_2008,{1U,6U,0U}}, +{MOVE_2008,{2U,6U,0U}}, +{MOVE_2008,{3U,6U,0U}}, +{MOVE_2008,{4U,6U,0U}}, +{MOVE_2008,{5U,6U,0U}}, +{MOVE_2008,{6U,6U,0U}}, +{MOVE_2008,{7U,6U,0U}}, +{MOVE_2010,{0U,6U,0U}}, +{MOVE_2010,{1U,6U,0U}}, +{MOVE_2010,{2U,6U,0U}}, +{MOVE_2010,{3U,6U,0U}}, +{MOVE_2010,{4U,6U,0U}}, +{MOVE_2010,{5U,6U,0U}}, +{MOVE_2010,{6U,6U,0U}}, +{MOVE_2010,{7U,6U,0U}}, +{MOVE_2018,{0U,6U,0U}}, +{MOVE_2018,{1U,6U,0U}}, +{MOVE_2018,{2U,6U,0U}}, +{MOVE_2018,{3U,6U,0U}}, +{MOVE_2018,{4U,6U,0U}}, +{MOVE_2018,{5U,6U,0U}}, +{MOVE_2018,{6U,6U,0U}}, +{MOVE_2018,{7U,6U,0U}}, +{MOVE_2020,{0U,6U,0U}}, +{MOVE_2020,{1U,6U,0U}}, +{MOVE_2020,{2U,6U,0U}}, +{MOVE_2020,{3U,6U,0U}}, +{MOVE_2020,{4U,6U,0U}}, +{MOVE_2020,{5U,6U,0U}}, +{MOVE_2020,{6U,6U,0U}}, +{MOVE_2020,{7U,6U,0U}}, +{MOVE_2028,{0U,6U,0U}}, +{MOVE_2028,{1U,6U,0U}}, +{MOVE_2028,{2U,6U,0U}}, +{MOVE_2028,{3U,6U,0U}}, +{MOVE_2028,{4U,6U,0U}}, +{MOVE_2028,{5U,6U,0U}}, +{MOVE_2028,{6U,6U,0U}}, +{MOVE_2028,{7U,6U,0U}}, +{MOVE_2030,{0U,6U,0U}}, +{MOVE_2030,{1U,6U,0U}}, +{MOVE_2030,{2U,6U,0U}}, +{MOVE_2030,{3U,6U,0U}}, +{MOVE_2030,{4U,6U,0U}}, +{MOVE_2030,{5U,6U,0U}}, +{MOVE_2030,{6U,6U,0U}}, +{MOVE_2030,{7U,6U,0U}}, +{MOVE_2038,{0U,6U,0U}}, +{MOVE_2039,{0U,6U,0U}}, +{MOVE_203A,{0U,6U,0U}}, +{MOVE_203B,{0U,6U,0U}}, +{MOVE_203C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_2040,{0U,6U,0U}}, +{MOVEA_2040,{1U,6U,0U}}, +{MOVEA_2040,{2U,6U,0U}}, +{MOVEA_2040,{3U,6U,0U}}, +{MOVEA_2040,{4U,6U,0U}}, +{MOVEA_2040,{5U,6U,0U}}, +{MOVEA_2040,{6U,6U,0U}}, +{MOVEA_2040,{7U,6U,0U}}, +{MOVEA_2048,{0U,6U,0U}}, +{MOVEA_2048,{1U,6U,0U}}, +{MOVEA_2048,{2U,6U,0U}}, +{MOVEA_2048,{3U,6U,0U}}, +{MOVEA_2048,{4U,6U,0U}}, +{MOVEA_2048,{5U,6U,0U}}, +{MOVEA_2048,{6U,6U,0U}}, +{MOVEA_2048,{7U,6U,0U}}, +{MOVEA_2050,{0U,6U,0U}}, +{MOVEA_2050,{1U,6U,0U}}, +{MOVEA_2050,{2U,6U,0U}}, +{MOVEA_2050,{3U,6U,0U}}, +{MOVEA_2050,{4U,6U,0U}}, +{MOVEA_2050,{5U,6U,0U}}, +{MOVEA_2050,{6U,6U,0U}}, +{MOVEA_2050,{7U,6U,0U}}, +{MOVEA_2058,{0U,6U,0U}}, +{MOVEA_2058,{1U,6U,0U}}, +{MOVEA_2058,{2U,6U,0U}}, +{MOVEA_2058,{3U,6U,0U}}, +{MOVEA_2058,{4U,6U,0U}}, +{MOVEA_2058,{5U,6U,0U}}, +{MOVEA_2058,{6U,6U,0U}}, +{MOVEA_2058,{7U,6U,0U}}, +{MOVEA_2060,{0U,6U,0U}}, +{MOVEA_2060,{1U,6U,0U}}, +{MOVEA_2060,{2U,6U,0U}}, +{MOVEA_2060,{3U,6U,0U}}, +{MOVEA_2060,{4U,6U,0U}}, +{MOVEA_2060,{5U,6U,0U}}, +{MOVEA_2060,{6U,6U,0U}}, +{MOVEA_2060,{7U,6U,0U}}, +{MOVEA_2068,{0U,6U,0U}}, +{MOVEA_2068,{1U,6U,0U}}, +{MOVEA_2068,{2U,6U,0U}}, +{MOVEA_2068,{3U,6U,0U}}, +{MOVEA_2068,{4U,6U,0U}}, +{MOVEA_2068,{5U,6U,0U}}, +{MOVEA_2068,{6U,6U,0U}}, +{MOVEA_2068,{7U,6U,0U}}, +{MOVEA_2070,{0U,6U,0U}}, +{MOVEA_2070,{1U,6U,0U}}, +{MOVEA_2070,{2U,6U,0U}}, +{MOVEA_2070,{3U,6U,0U}}, +{MOVEA_2070,{4U,6U,0U}}, +{MOVEA_2070,{5U,6U,0U}}, +{MOVEA_2070,{6U,6U,0U}}, +{MOVEA_2070,{7U,6U,0U}}, +{MOVEA_2078,{0U,6U,0U}}, +{MOVEA_2079,{0U,6U,0U}}, +{MOVEA_207A,{0U,6U,0U}}, +{MOVEA_207B,{0U,6U,0U}}, +{MOVEA_207C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2080,{0U,6U,0U}}, +{MOVE_2080,{1U,6U,0U}}, +{MOVE_2080,{2U,6U,0U}}, +{MOVE_2080,{3U,6U,0U}}, +{MOVE_2080,{4U,6U,0U}}, +{MOVE_2080,{5U,6U,0U}}, +{MOVE_2080,{6U,6U,0U}}, +{MOVE_2080,{7U,6U,0U}}, +{MOVE_2088,{0U,6U,0U}}, +{MOVE_2088,{1U,6U,0U}}, +{MOVE_2088,{2U,6U,0U}}, +{MOVE_2088,{3U,6U,0U}}, +{MOVE_2088,{4U,6U,0U}}, +{MOVE_2088,{5U,6U,0U}}, +{MOVE_2088,{6U,6U,0U}}, +{MOVE_2088,{7U,6U,0U}}, +{MOVE_2090,{0U,6U,0U}}, +{MOVE_2090,{1U,6U,0U}}, +{MOVE_2090,{2U,6U,0U}}, +{MOVE_2090,{3U,6U,0U}}, +{MOVE_2090,{4U,6U,0U}}, +{MOVE_2090,{5U,6U,0U}}, +{MOVE_2090,{6U,6U,0U}}, +{MOVE_2090,{7U,6U,0U}}, +{MOVE_2098,{0U,6U,0U}}, +{MOVE_2098,{1U,6U,0U}}, +{MOVE_2098,{2U,6U,0U}}, +{MOVE_2098,{3U,6U,0U}}, +{MOVE_2098,{4U,6U,0U}}, +{MOVE_2098,{5U,6U,0U}}, +{MOVE_2098,{6U,6U,0U}}, +{MOVE_2098,{7U,6U,0U}}, +{MOVE_20A0,{0U,6U,0U}}, +{MOVE_20A0,{1U,6U,0U}}, +{MOVE_20A0,{2U,6U,0U}}, +{MOVE_20A0,{3U,6U,0U}}, +{MOVE_20A0,{4U,6U,0U}}, +{MOVE_20A0,{5U,6U,0U}}, +{MOVE_20A0,{6U,6U,0U}}, +{MOVE_20A0,{7U,6U,0U}}, +{MOVE_20A8,{0U,6U,0U}}, +{MOVE_20A8,{1U,6U,0U}}, +{MOVE_20A8,{2U,6U,0U}}, +{MOVE_20A8,{3U,6U,0U}}, +{MOVE_20A8,{4U,6U,0U}}, +{MOVE_20A8,{5U,6U,0U}}, +{MOVE_20A8,{6U,6U,0U}}, +{MOVE_20A8,{7U,6U,0U}}, +{MOVE_20B0,{0U,6U,0U}}, +{MOVE_20B0,{1U,6U,0U}}, +{MOVE_20B0,{2U,6U,0U}}, +{MOVE_20B0,{3U,6U,0U}}, +{MOVE_20B0,{4U,6U,0U}}, +{MOVE_20B0,{5U,6U,0U}}, +{MOVE_20B0,{6U,6U,0U}}, +{MOVE_20B0,{7U,6U,0U}}, +{MOVE_20B8,{0U,6U,0U}}, +{MOVE_20B9,{0U,6U,0U}}, +{MOVE_20BA,{0U,6U,0U}}, +{MOVE_20BB,{0U,6U,0U}}, +{MOVE_20BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_20C0,{0U,6U,0U}}, +{MOVE_20C0,{1U,6U,0U}}, +{MOVE_20C0,{2U,6U,0U}}, +{MOVE_20C0,{3U,6U,0U}}, +{MOVE_20C0,{4U,6U,0U}}, +{MOVE_20C0,{5U,6U,0U}}, +{MOVE_20C0,{6U,6U,0U}}, +{MOVE_20C0,{7U,6U,0U}}, +{MOVE_20C8,{0U,6U,0U}}, +{MOVE_20C8,{1U,6U,0U}}, +{MOVE_20C8,{2U,6U,0U}}, +{MOVE_20C8,{3U,6U,0U}}, +{MOVE_20C8,{4U,6U,0U}}, +{MOVE_20C8,{5U,6U,0U}}, +{MOVE_20C8,{6U,6U,0U}}, +{MOVE_20C8,{7U,6U,0U}}, +{MOVE_20D0,{0U,6U,0U}}, +{MOVE_20D0,{1U,6U,0U}}, +{MOVE_20D0,{2U,6U,0U}}, +{MOVE_20D0,{3U,6U,0U}}, +{MOVE_20D0,{4U,6U,0U}}, +{MOVE_20D0,{5U,6U,0U}}, +{MOVE_20D0,{6U,6U,0U}}, +{MOVE_20D0,{7U,6U,0U}}, +{MOVE_20D8,{0U,6U,0U}}, +{MOVE_20D8,{1U,6U,0U}}, +{MOVE_20D8,{2U,6U,0U}}, +{MOVE_20D8,{3U,6U,0U}}, +{MOVE_20D8,{4U,6U,0U}}, +{MOVE_20D8,{5U,6U,0U}}, +{MOVE_20D8,{6U,6U,0U}}, +{MOVE_20D8,{7U,6U,0U}}, +{MOVE_20E0,{0U,6U,0U}}, +{MOVE_20E0,{1U,6U,0U}}, +{MOVE_20E0,{2U,6U,0U}}, +{MOVE_20E0,{3U,6U,0U}}, +{MOVE_20E0,{4U,6U,0U}}, +{MOVE_20E0,{5U,6U,0U}}, +{MOVE_20E0,{6U,6U,0U}}, +{MOVE_20E0,{7U,6U,0U}}, +{MOVE_20E8,{0U,6U,0U}}, +{MOVE_20E8,{1U,6U,0U}}, +{MOVE_20E8,{2U,6U,0U}}, +{MOVE_20E8,{3U,6U,0U}}, +{MOVE_20E8,{4U,6U,0U}}, +{MOVE_20E8,{5U,6U,0U}}, +{MOVE_20E8,{6U,6U,0U}}, +{MOVE_20E8,{7U,6U,0U}}, +{MOVE_20F0,{0U,6U,0U}}, +{MOVE_20F0,{1U,6U,0U}}, +{MOVE_20F0,{2U,6U,0U}}, +{MOVE_20F0,{3U,6U,0U}}, +{MOVE_20F0,{4U,6U,0U}}, +{MOVE_20F0,{5U,6U,0U}}, +{MOVE_20F0,{6U,6U,0U}}, +{MOVE_20F0,{7U,6U,0U}}, +{MOVE_20F8,{0U,6U,0U}}, +{MOVE_20F9,{0U,6U,0U}}, +{MOVE_20FA,{0U,6U,0U}}, +{MOVE_20FB,{0U,6U,0U}}, +{MOVE_20FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2100,{0U,6U,0U}}, +{MOVE_2100,{1U,6U,0U}}, +{MOVE_2100,{2U,6U,0U}}, +{MOVE_2100,{3U,6U,0U}}, +{MOVE_2100,{4U,6U,0U}}, +{MOVE_2100,{5U,6U,0U}}, +{MOVE_2100,{6U,6U,0U}}, +{MOVE_2100,{7U,6U,0U}}, +{MOVE_2108,{0U,6U,0U}}, +{MOVE_2108,{1U,6U,0U}}, +{MOVE_2108,{2U,6U,0U}}, +{MOVE_2108,{3U,6U,0U}}, +{MOVE_2108,{4U,6U,0U}}, +{MOVE_2108,{5U,6U,0U}}, +{MOVE_2108,{6U,6U,0U}}, +{MOVE_2108,{7U,6U,0U}}, +{MOVE_2110,{0U,6U,0U}}, +{MOVE_2110,{1U,6U,0U}}, +{MOVE_2110,{2U,6U,0U}}, +{MOVE_2110,{3U,6U,0U}}, +{MOVE_2110,{4U,6U,0U}}, +{MOVE_2110,{5U,6U,0U}}, +{MOVE_2110,{6U,6U,0U}}, +{MOVE_2110,{7U,6U,0U}}, +{MOVE_2118,{0U,6U,0U}}, +{MOVE_2118,{1U,6U,0U}}, +{MOVE_2118,{2U,6U,0U}}, +{MOVE_2118,{3U,6U,0U}}, +{MOVE_2118,{4U,6U,0U}}, +{MOVE_2118,{5U,6U,0U}}, +{MOVE_2118,{6U,6U,0U}}, +{MOVE_2118,{7U,6U,0U}}, +{MOVE_2120,{0U,6U,0U}}, +{MOVE_2120,{1U,6U,0U}}, +{MOVE_2120,{2U,6U,0U}}, +{MOVE_2120,{3U,6U,0U}}, +{MOVE_2120,{4U,6U,0U}}, +{MOVE_2120,{5U,6U,0U}}, +{MOVE_2120,{6U,6U,0U}}, +{MOVE_2120,{7U,6U,0U}}, +{MOVE_2128,{0U,6U,0U}}, +{MOVE_2128,{1U,6U,0U}}, +{MOVE_2128,{2U,6U,0U}}, +{MOVE_2128,{3U,6U,0U}}, +{MOVE_2128,{4U,6U,0U}}, +{MOVE_2128,{5U,6U,0U}}, +{MOVE_2128,{6U,6U,0U}}, +{MOVE_2128,{7U,6U,0U}}, +{MOVE_2130,{0U,6U,0U}}, +{MOVE_2130,{1U,6U,0U}}, +{MOVE_2130,{2U,6U,0U}}, +{MOVE_2130,{3U,6U,0U}}, +{MOVE_2130,{4U,6U,0U}}, +{MOVE_2130,{5U,6U,0U}}, +{MOVE_2130,{6U,6U,0U}}, +{MOVE_2130,{7U,6U,0U}}, +{MOVE_2138,{0U,6U,0U}}, +{MOVE_2139,{0U,6U,0U}}, +{MOVE_213A,{0U,6U,0U}}, +{MOVE_213B,{0U,6U,0U}}, +{MOVE_213C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2140,{0U,6U,0U}}, +{MOVE_2140,{1U,6U,0U}}, +{MOVE_2140,{2U,6U,0U}}, +{MOVE_2140,{3U,6U,0U}}, +{MOVE_2140,{4U,6U,0U}}, +{MOVE_2140,{5U,6U,0U}}, +{MOVE_2140,{6U,6U,0U}}, +{MOVE_2140,{7U,6U,0U}}, +{MOVE_2148,{0U,6U,0U}}, +{MOVE_2148,{1U,6U,0U}}, +{MOVE_2148,{2U,6U,0U}}, +{MOVE_2148,{3U,6U,0U}}, +{MOVE_2148,{4U,6U,0U}}, +{MOVE_2148,{5U,6U,0U}}, +{MOVE_2148,{6U,6U,0U}}, +{MOVE_2148,{7U,6U,0U}}, +{MOVE_2150,{0U,6U,0U}}, +{MOVE_2150,{1U,6U,0U}}, +{MOVE_2150,{2U,6U,0U}}, +{MOVE_2150,{3U,6U,0U}}, +{MOVE_2150,{4U,6U,0U}}, +{MOVE_2150,{5U,6U,0U}}, +{MOVE_2150,{6U,6U,0U}}, +{MOVE_2150,{7U,6U,0U}}, +{MOVE_2158,{0U,6U,0U}}, +{MOVE_2158,{1U,6U,0U}}, +{MOVE_2158,{2U,6U,0U}}, +{MOVE_2158,{3U,6U,0U}}, +{MOVE_2158,{4U,6U,0U}}, +{MOVE_2158,{5U,6U,0U}}, +{MOVE_2158,{6U,6U,0U}}, +{MOVE_2158,{7U,6U,0U}}, +{MOVE_2160,{0U,6U,0U}}, +{MOVE_2160,{1U,6U,0U}}, +{MOVE_2160,{2U,6U,0U}}, +{MOVE_2160,{3U,6U,0U}}, +{MOVE_2160,{4U,6U,0U}}, +{MOVE_2160,{5U,6U,0U}}, +{MOVE_2160,{6U,6U,0U}}, +{MOVE_2160,{7U,6U,0U}}, +{MOVE_2168,{0U,6U,0U}}, +{MOVE_2168,{1U,6U,0U}}, +{MOVE_2168,{2U,6U,0U}}, +{MOVE_2168,{3U,6U,0U}}, +{MOVE_2168,{4U,6U,0U}}, +{MOVE_2168,{5U,6U,0U}}, +{MOVE_2168,{6U,6U,0U}}, +{MOVE_2168,{7U,6U,0U}}, +{MOVE_2170,{0U,6U,0U}}, +{MOVE_2170,{1U,6U,0U}}, +{MOVE_2170,{2U,6U,0U}}, +{MOVE_2170,{3U,6U,0U}}, +{MOVE_2170,{4U,6U,0U}}, +{MOVE_2170,{5U,6U,0U}}, +{MOVE_2170,{6U,6U,0U}}, +{MOVE_2170,{7U,6U,0U}}, +{MOVE_2178,{0U,6U,0U}}, +{MOVE_2179,{0U,6U,0U}}, +{MOVE_217A,{0U,6U,0U}}, +{MOVE_217B,{0U,6U,0U}}, +{MOVE_217C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2180,{0U,6U,0U}}, +{MOVE_2180,{1U,6U,0U}}, +{MOVE_2180,{2U,6U,0U}}, +{MOVE_2180,{3U,6U,0U}}, +{MOVE_2180,{4U,6U,0U}}, +{MOVE_2180,{5U,6U,0U}}, +{MOVE_2180,{6U,6U,0U}}, +{MOVE_2180,{7U,6U,0U}}, +{MOVE_2188,{0U,6U,0U}}, +{MOVE_2188,{1U,6U,0U}}, +{MOVE_2188,{2U,6U,0U}}, +{MOVE_2188,{3U,6U,0U}}, +{MOVE_2188,{4U,6U,0U}}, +{MOVE_2188,{5U,6U,0U}}, +{MOVE_2188,{6U,6U,0U}}, +{MOVE_2188,{7U,6U,0U}}, +{MOVE_2190,{0U,6U,0U}}, +{MOVE_2190,{1U,6U,0U}}, +{MOVE_2190,{2U,6U,0U}}, +{MOVE_2190,{3U,6U,0U}}, +{MOVE_2190,{4U,6U,0U}}, +{MOVE_2190,{5U,6U,0U}}, +{MOVE_2190,{6U,6U,0U}}, +{MOVE_2190,{7U,6U,0U}}, +{MOVE_2198,{0U,6U,0U}}, +{MOVE_2198,{1U,6U,0U}}, +{MOVE_2198,{2U,6U,0U}}, +{MOVE_2198,{3U,6U,0U}}, +{MOVE_2198,{4U,6U,0U}}, +{MOVE_2198,{5U,6U,0U}}, +{MOVE_2198,{6U,6U,0U}}, +{MOVE_2198,{7U,6U,0U}}, +{MOVE_21A0,{0U,6U,0U}}, +{MOVE_21A0,{1U,6U,0U}}, +{MOVE_21A0,{2U,6U,0U}}, +{MOVE_21A0,{3U,6U,0U}}, +{MOVE_21A0,{4U,6U,0U}}, +{MOVE_21A0,{5U,6U,0U}}, +{MOVE_21A0,{6U,6U,0U}}, +{MOVE_21A0,{7U,6U,0U}}, +{MOVE_21A8,{0U,6U,0U}}, +{MOVE_21A8,{1U,6U,0U}}, +{MOVE_21A8,{2U,6U,0U}}, +{MOVE_21A8,{3U,6U,0U}}, +{MOVE_21A8,{4U,6U,0U}}, +{MOVE_21A8,{5U,6U,0U}}, +{MOVE_21A8,{6U,6U,0U}}, +{MOVE_21A8,{7U,6U,0U}}, +{MOVE_21B0,{0U,6U,0U}}, +{MOVE_21B0,{1U,6U,0U}}, +{MOVE_21B0,{2U,6U,0U}}, +{MOVE_21B0,{3U,6U,0U}}, +{MOVE_21B0,{4U,6U,0U}}, +{MOVE_21B0,{5U,6U,0U}}, +{MOVE_21B0,{6U,6U,0U}}, +{MOVE_21B0,{7U,6U,0U}}, +{MOVE_21B8,{0U,6U,0U}}, +{MOVE_21B9,{0U,6U,0U}}, +{MOVE_21BA,{0U,6U,0U}}, +{MOVE_21BB,{0U,6U,0U}}, +{MOVE_21BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2000,{0U,7U,0U}}, +{MOVE_2000,{1U,7U,0U}}, +{MOVE_2000,{2U,7U,0U}}, +{MOVE_2000,{3U,7U,0U}}, +{MOVE_2000,{4U,7U,0U}}, +{MOVE_2000,{5U,7U,0U}}, +{MOVE_2000,{6U,7U,0U}}, +{MOVE_2000,{7U,7U,0U}}, +{MOVE_2008,{0U,7U,0U}}, +{MOVE_2008,{1U,7U,0U}}, +{MOVE_2008,{2U,7U,0U}}, +{MOVE_2008,{3U,7U,0U}}, +{MOVE_2008,{4U,7U,0U}}, +{MOVE_2008,{5U,7U,0U}}, +{MOVE_2008,{6U,7U,0U}}, +{MOVE_2008,{7U,7U,0U}}, +{MOVE_2010,{0U,7U,0U}}, +{MOVE_2010,{1U,7U,0U}}, +{MOVE_2010,{2U,7U,0U}}, +{MOVE_2010,{3U,7U,0U}}, +{MOVE_2010,{4U,7U,0U}}, +{MOVE_2010,{5U,7U,0U}}, +{MOVE_2010,{6U,7U,0U}}, +{MOVE_2010,{7U,7U,0U}}, +{MOVE_2018,{0U,7U,0U}}, +{MOVE_2018,{1U,7U,0U}}, +{MOVE_2018,{2U,7U,0U}}, +{MOVE_2018,{3U,7U,0U}}, +{MOVE_2018,{4U,7U,0U}}, +{MOVE_2018,{5U,7U,0U}}, +{MOVE_2018,{6U,7U,0U}}, +{MOVE_2018,{7U,7U,0U}}, +{MOVE_2020,{0U,7U,0U}}, +{MOVE_2020,{1U,7U,0U}}, +{MOVE_2020,{2U,7U,0U}}, +{MOVE_2020,{3U,7U,0U}}, +{MOVE_2020,{4U,7U,0U}}, +{MOVE_2020,{5U,7U,0U}}, +{MOVE_2020,{6U,7U,0U}}, +{MOVE_2020,{7U,7U,0U}}, +{MOVE_2028,{0U,7U,0U}}, +{MOVE_2028,{1U,7U,0U}}, +{MOVE_2028,{2U,7U,0U}}, +{MOVE_2028,{3U,7U,0U}}, +{MOVE_2028,{4U,7U,0U}}, +{MOVE_2028,{5U,7U,0U}}, +{MOVE_2028,{6U,7U,0U}}, +{MOVE_2028,{7U,7U,0U}}, +{MOVE_2030,{0U,7U,0U}}, +{MOVE_2030,{1U,7U,0U}}, +{MOVE_2030,{2U,7U,0U}}, +{MOVE_2030,{3U,7U,0U}}, +{MOVE_2030,{4U,7U,0U}}, +{MOVE_2030,{5U,7U,0U}}, +{MOVE_2030,{6U,7U,0U}}, +{MOVE_2030,{7U,7U,0U}}, +{MOVE_2038,{0U,7U,0U}}, +{MOVE_2039,{0U,7U,0U}}, +{MOVE_203A,{0U,7U,0U}}, +{MOVE_203B,{0U,7U,0U}}, +{MOVE_203C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_2040,{0U,7U,0U}}, +{MOVEA_2040,{1U,7U,0U}}, +{MOVEA_2040,{2U,7U,0U}}, +{MOVEA_2040,{3U,7U,0U}}, +{MOVEA_2040,{4U,7U,0U}}, +{MOVEA_2040,{5U,7U,0U}}, +{MOVEA_2040,{6U,7U,0U}}, +{MOVEA_2040,{7U,7U,0U}}, +{MOVEA_2048,{0U,7U,0U}}, +{MOVEA_2048,{1U,7U,0U}}, +{MOVEA_2048,{2U,7U,0U}}, +{MOVEA_2048,{3U,7U,0U}}, +{MOVEA_2048,{4U,7U,0U}}, +{MOVEA_2048,{5U,7U,0U}}, +{MOVEA_2048,{6U,7U,0U}}, +{MOVEA_2048,{7U,7U,0U}}, +{MOVEA_2050,{0U,7U,0U}}, +{MOVEA_2050,{1U,7U,0U}}, +{MOVEA_2050,{2U,7U,0U}}, +{MOVEA_2050,{3U,7U,0U}}, +{MOVEA_2050,{4U,7U,0U}}, +{MOVEA_2050,{5U,7U,0U}}, +{MOVEA_2050,{6U,7U,0U}}, +{MOVEA_2050,{7U,7U,0U}}, +{MOVEA_2058,{0U,7U,0U}}, +{MOVEA_2058,{1U,7U,0U}}, +{MOVEA_2058,{2U,7U,0U}}, +{MOVEA_2058,{3U,7U,0U}}, +{MOVEA_2058,{4U,7U,0U}}, +{MOVEA_2058,{5U,7U,0U}}, +{MOVEA_2058,{6U,7U,0U}}, +{MOVEA_2058,{7U,7U,0U}}, +{MOVEA_2060,{0U,7U,0U}}, +{MOVEA_2060,{1U,7U,0U}}, +{MOVEA_2060,{2U,7U,0U}}, +{MOVEA_2060,{3U,7U,0U}}, +{MOVEA_2060,{4U,7U,0U}}, +{MOVEA_2060,{5U,7U,0U}}, +{MOVEA_2060,{6U,7U,0U}}, +{MOVEA_2060,{7U,7U,0U}}, +{MOVEA_2068,{0U,7U,0U}}, +{MOVEA_2068,{1U,7U,0U}}, +{MOVEA_2068,{2U,7U,0U}}, +{MOVEA_2068,{3U,7U,0U}}, +{MOVEA_2068,{4U,7U,0U}}, +{MOVEA_2068,{5U,7U,0U}}, +{MOVEA_2068,{6U,7U,0U}}, +{MOVEA_2068,{7U,7U,0U}}, +{MOVEA_2070,{0U,7U,0U}}, +{MOVEA_2070,{1U,7U,0U}}, +{MOVEA_2070,{2U,7U,0U}}, +{MOVEA_2070,{3U,7U,0U}}, +{MOVEA_2070,{4U,7U,0U}}, +{MOVEA_2070,{5U,7U,0U}}, +{MOVEA_2070,{6U,7U,0U}}, +{MOVEA_2070,{7U,7U,0U}}, +{MOVEA_2078,{0U,7U,0U}}, +{MOVEA_2079,{0U,7U,0U}}, +{MOVEA_207A,{0U,7U,0U}}, +{MOVEA_207B,{0U,7U,0U}}, +{MOVEA_207C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2080,{0U,7U,0U}}, +{MOVE_2080,{1U,7U,0U}}, +{MOVE_2080,{2U,7U,0U}}, +{MOVE_2080,{3U,7U,0U}}, +{MOVE_2080,{4U,7U,0U}}, +{MOVE_2080,{5U,7U,0U}}, +{MOVE_2080,{6U,7U,0U}}, +{MOVE_2080,{7U,7U,0U}}, +{MOVE_2088,{0U,7U,0U}}, +{MOVE_2088,{1U,7U,0U}}, +{MOVE_2088,{2U,7U,0U}}, +{MOVE_2088,{3U,7U,0U}}, +{MOVE_2088,{4U,7U,0U}}, +{MOVE_2088,{5U,7U,0U}}, +{MOVE_2088,{6U,7U,0U}}, +{MOVE_2088,{7U,7U,0U}}, +{MOVE_2090,{0U,7U,0U}}, +{MOVE_2090,{1U,7U,0U}}, +{MOVE_2090,{2U,7U,0U}}, +{MOVE_2090,{3U,7U,0U}}, +{MOVE_2090,{4U,7U,0U}}, +{MOVE_2090,{5U,7U,0U}}, +{MOVE_2090,{6U,7U,0U}}, +{MOVE_2090,{7U,7U,0U}}, +{MOVE_2098,{0U,7U,0U}}, +{MOVE_2098,{1U,7U,0U}}, +{MOVE_2098,{2U,7U,0U}}, +{MOVE_2098,{3U,7U,0U}}, +{MOVE_2098,{4U,7U,0U}}, +{MOVE_2098,{5U,7U,0U}}, +{MOVE_2098,{6U,7U,0U}}, +{MOVE_2098,{7U,7U,0U}}, +{MOVE_20A0,{0U,7U,0U}}, +{MOVE_20A0,{1U,7U,0U}}, +{MOVE_20A0,{2U,7U,0U}}, +{MOVE_20A0,{3U,7U,0U}}, +{MOVE_20A0,{4U,7U,0U}}, +{MOVE_20A0,{5U,7U,0U}}, +{MOVE_20A0,{6U,7U,0U}}, +{MOVE_20A0,{7U,7U,0U}}, +{MOVE_20A8,{0U,7U,0U}}, +{MOVE_20A8,{1U,7U,0U}}, +{MOVE_20A8,{2U,7U,0U}}, +{MOVE_20A8,{3U,7U,0U}}, +{MOVE_20A8,{4U,7U,0U}}, +{MOVE_20A8,{5U,7U,0U}}, +{MOVE_20A8,{6U,7U,0U}}, +{MOVE_20A8,{7U,7U,0U}}, +{MOVE_20B0,{0U,7U,0U}}, +{MOVE_20B0,{1U,7U,0U}}, +{MOVE_20B0,{2U,7U,0U}}, +{MOVE_20B0,{3U,7U,0U}}, +{MOVE_20B0,{4U,7U,0U}}, +{MOVE_20B0,{5U,7U,0U}}, +{MOVE_20B0,{6U,7U,0U}}, +{MOVE_20B0,{7U,7U,0U}}, +{MOVE_20B8,{0U,7U,0U}}, +{MOVE_20B9,{0U,7U,0U}}, +{MOVE_20BA,{0U,7U,0U}}, +{MOVE_20BB,{0U,7U,0U}}, +{MOVE_20BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_20C0,{0U,7U,0U}}, +{MOVE_20C0,{1U,7U,0U}}, +{MOVE_20C0,{2U,7U,0U}}, +{MOVE_20C0,{3U,7U,0U}}, +{MOVE_20C0,{4U,7U,0U}}, +{MOVE_20C0,{5U,7U,0U}}, +{MOVE_20C0,{6U,7U,0U}}, +{MOVE_20C0,{7U,7U,0U}}, +{MOVE_20C8,{0U,7U,0U}}, +{MOVE_20C8,{1U,7U,0U}}, +{MOVE_20C8,{2U,7U,0U}}, +{MOVE_20C8,{3U,7U,0U}}, +{MOVE_20C8,{4U,7U,0U}}, +{MOVE_20C8,{5U,7U,0U}}, +{MOVE_20C8,{6U,7U,0U}}, +{MOVE_20C8,{7U,7U,0U}}, +{MOVE_20D0,{0U,7U,0U}}, +{MOVE_20D0,{1U,7U,0U}}, +{MOVE_20D0,{2U,7U,0U}}, +{MOVE_20D0,{3U,7U,0U}}, +{MOVE_20D0,{4U,7U,0U}}, +{MOVE_20D0,{5U,7U,0U}}, +{MOVE_20D0,{6U,7U,0U}}, +{MOVE_20D0,{7U,7U,0U}}, +{MOVE_20D8,{0U,7U,0U}}, +{MOVE_20D8,{1U,7U,0U}}, +{MOVE_20D8,{2U,7U,0U}}, +{MOVE_20D8,{3U,7U,0U}}, +{MOVE_20D8,{4U,7U,0U}}, +{MOVE_20D8,{5U,7U,0U}}, +{MOVE_20D8,{6U,7U,0U}}, +{MOVE_20D8,{7U,7U,0U}}, +{MOVE_20E0,{0U,7U,0U}}, +{MOVE_20E0,{1U,7U,0U}}, +{MOVE_20E0,{2U,7U,0U}}, +{MOVE_20E0,{3U,7U,0U}}, +{MOVE_20E0,{4U,7U,0U}}, +{MOVE_20E0,{5U,7U,0U}}, +{MOVE_20E0,{6U,7U,0U}}, +{MOVE_20E0,{7U,7U,0U}}, +{MOVE_20E8,{0U,7U,0U}}, +{MOVE_20E8,{1U,7U,0U}}, +{MOVE_20E8,{2U,7U,0U}}, +{MOVE_20E8,{3U,7U,0U}}, +{MOVE_20E8,{4U,7U,0U}}, +{MOVE_20E8,{5U,7U,0U}}, +{MOVE_20E8,{6U,7U,0U}}, +{MOVE_20E8,{7U,7U,0U}}, +{MOVE_20F0,{0U,7U,0U}}, +{MOVE_20F0,{1U,7U,0U}}, +{MOVE_20F0,{2U,7U,0U}}, +{MOVE_20F0,{3U,7U,0U}}, +{MOVE_20F0,{4U,7U,0U}}, +{MOVE_20F0,{5U,7U,0U}}, +{MOVE_20F0,{6U,7U,0U}}, +{MOVE_20F0,{7U,7U,0U}}, +{MOVE_20F8,{0U,7U,0U}}, +{MOVE_20F9,{0U,7U,0U}}, +{MOVE_20FA,{0U,7U,0U}}, +{MOVE_20FB,{0U,7U,0U}}, +{MOVE_20FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2100,{0U,7U,0U}}, +{MOVE_2100,{1U,7U,0U}}, +{MOVE_2100,{2U,7U,0U}}, +{MOVE_2100,{3U,7U,0U}}, +{MOVE_2100,{4U,7U,0U}}, +{MOVE_2100,{5U,7U,0U}}, +{MOVE_2100,{6U,7U,0U}}, +{MOVE_2100,{7U,7U,0U}}, +{MOVE_2108,{0U,7U,0U}}, +{MOVE_2108,{1U,7U,0U}}, +{MOVE_2108,{2U,7U,0U}}, +{MOVE_2108,{3U,7U,0U}}, +{MOVE_2108,{4U,7U,0U}}, +{MOVE_2108,{5U,7U,0U}}, +{MOVE_2108,{6U,7U,0U}}, +{MOVE_2108,{7U,7U,0U}}, +{MOVE_2110,{0U,7U,0U}}, +{MOVE_2110,{1U,7U,0U}}, +{MOVE_2110,{2U,7U,0U}}, +{MOVE_2110,{3U,7U,0U}}, +{MOVE_2110,{4U,7U,0U}}, +{MOVE_2110,{5U,7U,0U}}, +{MOVE_2110,{6U,7U,0U}}, +{MOVE_2110,{7U,7U,0U}}, +{MOVE_2118,{0U,7U,0U}}, +{MOVE_2118,{1U,7U,0U}}, +{MOVE_2118,{2U,7U,0U}}, +{MOVE_2118,{3U,7U,0U}}, +{MOVE_2118,{4U,7U,0U}}, +{MOVE_2118,{5U,7U,0U}}, +{MOVE_2118,{6U,7U,0U}}, +{MOVE_2118,{7U,7U,0U}}, +{MOVE_2120,{0U,7U,0U}}, +{MOVE_2120,{1U,7U,0U}}, +{MOVE_2120,{2U,7U,0U}}, +{MOVE_2120,{3U,7U,0U}}, +{MOVE_2120,{4U,7U,0U}}, +{MOVE_2120,{5U,7U,0U}}, +{MOVE_2120,{6U,7U,0U}}, +{MOVE_2120,{7U,7U,0U}}, +{MOVE_2128,{0U,7U,0U}}, +{MOVE_2128,{1U,7U,0U}}, +{MOVE_2128,{2U,7U,0U}}, +{MOVE_2128,{3U,7U,0U}}, +{MOVE_2128,{4U,7U,0U}}, +{MOVE_2128,{5U,7U,0U}}, +{MOVE_2128,{6U,7U,0U}}, +{MOVE_2128,{7U,7U,0U}}, +{MOVE_2130,{0U,7U,0U}}, +{MOVE_2130,{1U,7U,0U}}, +{MOVE_2130,{2U,7U,0U}}, +{MOVE_2130,{3U,7U,0U}}, +{MOVE_2130,{4U,7U,0U}}, +{MOVE_2130,{5U,7U,0U}}, +{MOVE_2130,{6U,7U,0U}}, +{MOVE_2130,{7U,7U,0U}}, +{MOVE_2138,{0U,7U,0U}}, +{MOVE_2139,{0U,7U,0U}}, +{MOVE_213A,{0U,7U,0U}}, +{MOVE_213B,{0U,7U,0U}}, +{MOVE_213C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2140,{0U,7U,0U}}, +{MOVE_2140,{1U,7U,0U}}, +{MOVE_2140,{2U,7U,0U}}, +{MOVE_2140,{3U,7U,0U}}, +{MOVE_2140,{4U,7U,0U}}, +{MOVE_2140,{5U,7U,0U}}, +{MOVE_2140,{6U,7U,0U}}, +{MOVE_2140,{7U,7U,0U}}, +{MOVE_2148,{0U,7U,0U}}, +{MOVE_2148,{1U,7U,0U}}, +{MOVE_2148,{2U,7U,0U}}, +{MOVE_2148,{3U,7U,0U}}, +{MOVE_2148,{4U,7U,0U}}, +{MOVE_2148,{5U,7U,0U}}, +{MOVE_2148,{6U,7U,0U}}, +{MOVE_2148,{7U,7U,0U}}, +{MOVE_2150,{0U,7U,0U}}, +{MOVE_2150,{1U,7U,0U}}, +{MOVE_2150,{2U,7U,0U}}, +{MOVE_2150,{3U,7U,0U}}, +{MOVE_2150,{4U,7U,0U}}, +{MOVE_2150,{5U,7U,0U}}, +{MOVE_2150,{6U,7U,0U}}, +{MOVE_2150,{7U,7U,0U}}, +{MOVE_2158,{0U,7U,0U}}, +{MOVE_2158,{1U,7U,0U}}, +{MOVE_2158,{2U,7U,0U}}, +{MOVE_2158,{3U,7U,0U}}, +{MOVE_2158,{4U,7U,0U}}, +{MOVE_2158,{5U,7U,0U}}, +{MOVE_2158,{6U,7U,0U}}, +{MOVE_2158,{7U,7U,0U}}, +{MOVE_2160,{0U,7U,0U}}, +{MOVE_2160,{1U,7U,0U}}, +{MOVE_2160,{2U,7U,0U}}, +{MOVE_2160,{3U,7U,0U}}, +{MOVE_2160,{4U,7U,0U}}, +{MOVE_2160,{5U,7U,0U}}, +{MOVE_2160,{6U,7U,0U}}, +{MOVE_2160,{7U,7U,0U}}, +{MOVE_2168,{0U,7U,0U}}, +{MOVE_2168,{1U,7U,0U}}, +{MOVE_2168,{2U,7U,0U}}, +{MOVE_2168,{3U,7U,0U}}, +{MOVE_2168,{4U,7U,0U}}, +{MOVE_2168,{5U,7U,0U}}, +{MOVE_2168,{6U,7U,0U}}, +{MOVE_2168,{7U,7U,0U}}, +{MOVE_2170,{0U,7U,0U}}, +{MOVE_2170,{1U,7U,0U}}, +{MOVE_2170,{2U,7U,0U}}, +{MOVE_2170,{3U,7U,0U}}, +{MOVE_2170,{4U,7U,0U}}, +{MOVE_2170,{5U,7U,0U}}, +{MOVE_2170,{6U,7U,0U}}, +{MOVE_2170,{7U,7U,0U}}, +{MOVE_2178,{0U,7U,0U}}, +{MOVE_2179,{0U,7U,0U}}, +{MOVE_217A,{0U,7U,0U}}, +{MOVE_217B,{0U,7U,0U}}, +{MOVE_217C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_2180,{0U,7U,0U}}, +{MOVE_2180,{1U,7U,0U}}, +{MOVE_2180,{2U,7U,0U}}, +{MOVE_2180,{3U,7U,0U}}, +{MOVE_2180,{4U,7U,0U}}, +{MOVE_2180,{5U,7U,0U}}, +{MOVE_2180,{6U,7U,0U}}, +{MOVE_2180,{7U,7U,0U}}, +{MOVE_2188,{0U,7U,0U}}, +{MOVE_2188,{1U,7U,0U}}, +{MOVE_2188,{2U,7U,0U}}, +{MOVE_2188,{3U,7U,0U}}, +{MOVE_2188,{4U,7U,0U}}, +{MOVE_2188,{5U,7U,0U}}, +{MOVE_2188,{6U,7U,0U}}, +{MOVE_2188,{7U,7U,0U}}, +{MOVE_2190,{0U,7U,0U}}, +{MOVE_2190,{1U,7U,0U}}, +{MOVE_2190,{2U,7U,0U}}, +{MOVE_2190,{3U,7U,0U}}, +{MOVE_2190,{4U,7U,0U}}, +{MOVE_2190,{5U,7U,0U}}, +{MOVE_2190,{6U,7U,0U}}, +{MOVE_2190,{7U,7U,0U}}, +{MOVE_2198,{0U,7U,0U}}, +{MOVE_2198,{1U,7U,0U}}, +{MOVE_2198,{2U,7U,0U}}, +{MOVE_2198,{3U,7U,0U}}, +{MOVE_2198,{4U,7U,0U}}, +{MOVE_2198,{5U,7U,0U}}, +{MOVE_2198,{6U,7U,0U}}, +{MOVE_2198,{7U,7U,0U}}, +{MOVE_21A0,{0U,7U,0U}}, +{MOVE_21A0,{1U,7U,0U}}, +{MOVE_21A0,{2U,7U,0U}}, +{MOVE_21A0,{3U,7U,0U}}, +{MOVE_21A0,{4U,7U,0U}}, +{MOVE_21A0,{5U,7U,0U}}, +{MOVE_21A0,{6U,7U,0U}}, +{MOVE_21A0,{7U,7U,0U}}, +{MOVE_21A8,{0U,7U,0U}}, +{MOVE_21A8,{1U,7U,0U}}, +{MOVE_21A8,{2U,7U,0U}}, +{MOVE_21A8,{3U,7U,0U}}, +{MOVE_21A8,{4U,7U,0U}}, +{MOVE_21A8,{5U,7U,0U}}, +{MOVE_21A8,{6U,7U,0U}}, +{MOVE_21A8,{7U,7U,0U}}, +{MOVE_21B0,{0U,7U,0U}}, +{MOVE_21B0,{1U,7U,0U}}, +{MOVE_21B0,{2U,7U,0U}}, +{MOVE_21B0,{3U,7U,0U}}, +{MOVE_21B0,{4U,7U,0U}}, +{MOVE_21B0,{5U,7U,0U}}, +{MOVE_21B0,{6U,7U,0U}}, +{MOVE_21B0,{7U,7U,0U}}, +{MOVE_21B8,{0U,7U,0U}}, +{MOVE_21B9,{0U,7U,0U}}, +{MOVE_21BA,{0U,7U,0U}}, +{MOVE_21BB,{0U,7U,0U}}, +{MOVE_21BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3000,{0U,0U,0U}}, +{MOVE_3000,{1U,0U,0U}}, +{MOVE_3000,{2U,0U,0U}}, +{MOVE_3000,{3U,0U,0U}}, +{MOVE_3000,{4U,0U,0U}}, +{MOVE_3000,{5U,0U,0U}}, +{MOVE_3000,{6U,0U,0U}}, +{MOVE_3000,{7U,0U,0U}}, +{MOVE_3008,{0U,0U,0U}}, +{MOVE_3008,{1U,0U,0U}}, +{MOVE_3008,{2U,0U,0U}}, +{MOVE_3008,{3U,0U,0U}}, +{MOVE_3008,{4U,0U,0U}}, +{MOVE_3008,{5U,0U,0U}}, +{MOVE_3008,{6U,0U,0U}}, +{MOVE_3008,{7U,0U,0U}}, +{MOVE_3010,{0U,0U,0U}}, +{MOVE_3010,{1U,0U,0U}}, +{MOVE_3010,{2U,0U,0U}}, +{MOVE_3010,{3U,0U,0U}}, +{MOVE_3010,{4U,0U,0U}}, +{MOVE_3010,{5U,0U,0U}}, +{MOVE_3010,{6U,0U,0U}}, +{MOVE_3010,{7U,0U,0U}}, +{MOVE_3018,{0U,0U,0U}}, +{MOVE_3018,{1U,0U,0U}}, +{MOVE_3018,{2U,0U,0U}}, +{MOVE_3018,{3U,0U,0U}}, +{MOVE_3018,{4U,0U,0U}}, +{MOVE_3018,{5U,0U,0U}}, +{MOVE_3018,{6U,0U,0U}}, +{MOVE_3018,{7U,0U,0U}}, +{MOVE_3020,{0U,0U,0U}}, +{MOVE_3020,{1U,0U,0U}}, +{MOVE_3020,{2U,0U,0U}}, +{MOVE_3020,{3U,0U,0U}}, +{MOVE_3020,{4U,0U,0U}}, +{MOVE_3020,{5U,0U,0U}}, +{MOVE_3020,{6U,0U,0U}}, +{MOVE_3020,{7U,0U,0U}}, +{MOVE_3028,{0U,0U,0U}}, +{MOVE_3028,{1U,0U,0U}}, +{MOVE_3028,{2U,0U,0U}}, +{MOVE_3028,{3U,0U,0U}}, +{MOVE_3028,{4U,0U,0U}}, +{MOVE_3028,{5U,0U,0U}}, +{MOVE_3028,{6U,0U,0U}}, +{MOVE_3028,{7U,0U,0U}}, +{MOVE_3030,{0U,0U,0U}}, +{MOVE_3030,{1U,0U,0U}}, +{MOVE_3030,{2U,0U,0U}}, +{MOVE_3030,{3U,0U,0U}}, +{MOVE_3030,{4U,0U,0U}}, +{MOVE_3030,{5U,0U,0U}}, +{MOVE_3030,{6U,0U,0U}}, +{MOVE_3030,{7U,0U,0U}}, +{MOVE_3038,{0U,0U,0U}}, +{MOVE_3039,{0U,0U,0U}}, +{MOVE_303A,{0U,0U,0U}}, +{MOVE_303B,{0U,0U,0U}}, +{MOVE_303C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_3040,{0U,0U,0U}}, +{MOVEA_3040,{1U,0U,0U}}, +{MOVEA_3040,{2U,0U,0U}}, +{MOVEA_3040,{3U,0U,0U}}, +{MOVEA_3040,{4U,0U,0U}}, +{MOVEA_3040,{5U,0U,0U}}, +{MOVEA_3040,{6U,0U,0U}}, +{MOVEA_3040,{7U,0U,0U}}, +{MOVEA_3048,{0U,0U,0U}}, +{MOVEA_3048,{1U,0U,0U}}, +{MOVEA_3048,{2U,0U,0U}}, +{MOVEA_3048,{3U,0U,0U}}, +{MOVEA_3048,{4U,0U,0U}}, +{MOVEA_3048,{5U,0U,0U}}, +{MOVEA_3048,{6U,0U,0U}}, +{MOVEA_3048,{7U,0U,0U}}, +{MOVEA_3050,{0U,0U,0U}}, +{MOVEA_3050,{1U,0U,0U}}, +{MOVEA_3050,{2U,0U,0U}}, +{MOVEA_3050,{3U,0U,0U}}, +{MOVEA_3050,{4U,0U,0U}}, +{MOVEA_3050,{5U,0U,0U}}, +{MOVEA_3050,{6U,0U,0U}}, +{MOVEA_3050,{7U,0U,0U}}, +{MOVEA_3058,{0U,0U,0U}}, +{MOVEA_3058,{1U,0U,0U}}, +{MOVEA_3058,{2U,0U,0U}}, +{MOVEA_3058,{3U,0U,0U}}, +{MOVEA_3058,{4U,0U,0U}}, +{MOVEA_3058,{5U,0U,0U}}, +{MOVEA_3058,{6U,0U,0U}}, +{MOVEA_3058,{7U,0U,0U}}, +{MOVEA_3060,{0U,0U,0U}}, +{MOVEA_3060,{1U,0U,0U}}, +{MOVEA_3060,{2U,0U,0U}}, +{MOVEA_3060,{3U,0U,0U}}, +{MOVEA_3060,{4U,0U,0U}}, +{MOVEA_3060,{5U,0U,0U}}, +{MOVEA_3060,{6U,0U,0U}}, +{MOVEA_3060,{7U,0U,0U}}, +{MOVEA_3068,{0U,0U,0U}}, +{MOVEA_3068,{1U,0U,0U}}, +{MOVEA_3068,{2U,0U,0U}}, +{MOVEA_3068,{3U,0U,0U}}, +{MOVEA_3068,{4U,0U,0U}}, +{MOVEA_3068,{5U,0U,0U}}, +{MOVEA_3068,{6U,0U,0U}}, +{MOVEA_3068,{7U,0U,0U}}, +{MOVEA_3070,{0U,0U,0U}}, +{MOVEA_3070,{1U,0U,0U}}, +{MOVEA_3070,{2U,0U,0U}}, +{MOVEA_3070,{3U,0U,0U}}, +{MOVEA_3070,{4U,0U,0U}}, +{MOVEA_3070,{5U,0U,0U}}, +{MOVEA_3070,{6U,0U,0U}}, +{MOVEA_3070,{7U,0U,0U}}, +{MOVEA_3078,{0U,0U,0U}}, +{MOVEA_3079,{0U,0U,0U}}, +{MOVEA_307A,{0U,0U,0U}}, +{MOVEA_307B,{0U,0U,0U}}, +{MOVEA_307C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3080,{0U,0U,0U}}, +{MOVE_3080,{1U,0U,0U}}, +{MOVE_3080,{2U,0U,0U}}, +{MOVE_3080,{3U,0U,0U}}, +{MOVE_3080,{4U,0U,0U}}, +{MOVE_3080,{5U,0U,0U}}, +{MOVE_3080,{6U,0U,0U}}, +{MOVE_3080,{7U,0U,0U}}, +{MOVE_3088,{0U,0U,0U}}, +{MOVE_3088,{1U,0U,0U}}, +{MOVE_3088,{2U,0U,0U}}, +{MOVE_3088,{3U,0U,0U}}, +{MOVE_3088,{4U,0U,0U}}, +{MOVE_3088,{5U,0U,0U}}, +{MOVE_3088,{6U,0U,0U}}, +{MOVE_3088,{7U,0U,0U}}, +{MOVE_3090,{0U,0U,0U}}, +{MOVE_3090,{1U,0U,0U}}, +{MOVE_3090,{2U,0U,0U}}, +{MOVE_3090,{3U,0U,0U}}, +{MOVE_3090,{4U,0U,0U}}, +{MOVE_3090,{5U,0U,0U}}, +{MOVE_3090,{6U,0U,0U}}, +{MOVE_3090,{7U,0U,0U}}, +{MOVE_3098,{0U,0U,0U}}, +{MOVE_3098,{1U,0U,0U}}, +{MOVE_3098,{2U,0U,0U}}, +{MOVE_3098,{3U,0U,0U}}, +{MOVE_3098,{4U,0U,0U}}, +{MOVE_3098,{5U,0U,0U}}, +{MOVE_3098,{6U,0U,0U}}, +{MOVE_3098,{7U,0U,0U}}, +{MOVE_30A0,{0U,0U,0U}}, +{MOVE_30A0,{1U,0U,0U}}, +{MOVE_30A0,{2U,0U,0U}}, +{MOVE_30A0,{3U,0U,0U}}, +{MOVE_30A0,{4U,0U,0U}}, +{MOVE_30A0,{5U,0U,0U}}, +{MOVE_30A0,{6U,0U,0U}}, +{MOVE_30A0,{7U,0U,0U}}, +{MOVE_30A8,{0U,0U,0U}}, +{MOVE_30A8,{1U,0U,0U}}, +{MOVE_30A8,{2U,0U,0U}}, +{MOVE_30A8,{3U,0U,0U}}, +{MOVE_30A8,{4U,0U,0U}}, +{MOVE_30A8,{5U,0U,0U}}, +{MOVE_30A8,{6U,0U,0U}}, +{MOVE_30A8,{7U,0U,0U}}, +{MOVE_30B0,{0U,0U,0U}}, +{MOVE_30B0,{1U,0U,0U}}, +{MOVE_30B0,{2U,0U,0U}}, +{MOVE_30B0,{3U,0U,0U}}, +{MOVE_30B0,{4U,0U,0U}}, +{MOVE_30B0,{5U,0U,0U}}, +{MOVE_30B0,{6U,0U,0U}}, +{MOVE_30B0,{7U,0U,0U}}, +{MOVE_30B8,{0U,0U,0U}}, +{MOVE_30B9,{0U,0U,0U}}, +{MOVE_30BA,{0U,0U,0U}}, +{MOVE_30BB,{0U,0U,0U}}, +{MOVE_30BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_30C0,{0U,0U,0U}}, +{MOVE_30C0,{1U,0U,0U}}, +{MOVE_30C0,{2U,0U,0U}}, +{MOVE_30C0,{3U,0U,0U}}, +{MOVE_30C0,{4U,0U,0U}}, +{MOVE_30C0,{5U,0U,0U}}, +{MOVE_30C0,{6U,0U,0U}}, +{MOVE_30C0,{7U,0U,0U}}, +{MOVE_30C8,{0U,0U,0U}}, +{MOVE_30C8,{1U,0U,0U}}, +{MOVE_30C8,{2U,0U,0U}}, +{MOVE_30C8,{3U,0U,0U}}, +{MOVE_30C8,{4U,0U,0U}}, +{MOVE_30C8,{5U,0U,0U}}, +{MOVE_30C8,{6U,0U,0U}}, +{MOVE_30C8,{7U,0U,0U}}, +{MOVE_30D0,{0U,0U,0U}}, +{MOVE_30D0,{1U,0U,0U}}, +{MOVE_30D0,{2U,0U,0U}}, +{MOVE_30D0,{3U,0U,0U}}, +{MOVE_30D0,{4U,0U,0U}}, +{MOVE_30D0,{5U,0U,0U}}, +{MOVE_30D0,{6U,0U,0U}}, +{MOVE_30D0,{7U,0U,0U}}, +{MOVE_30D8,{0U,0U,0U}}, +{MOVE_30D8,{1U,0U,0U}}, +{MOVE_30D8,{2U,0U,0U}}, +{MOVE_30D8,{3U,0U,0U}}, +{MOVE_30D8,{4U,0U,0U}}, +{MOVE_30D8,{5U,0U,0U}}, +{MOVE_30D8,{6U,0U,0U}}, +{MOVE_30D8,{7U,0U,0U}}, +{MOVE_30E0,{0U,0U,0U}}, +{MOVE_30E0,{1U,0U,0U}}, +{MOVE_30E0,{2U,0U,0U}}, +{MOVE_30E0,{3U,0U,0U}}, +{MOVE_30E0,{4U,0U,0U}}, +{MOVE_30E0,{5U,0U,0U}}, +{MOVE_30E0,{6U,0U,0U}}, +{MOVE_30E0,{7U,0U,0U}}, +{MOVE_30E8,{0U,0U,0U}}, +{MOVE_30E8,{1U,0U,0U}}, +{MOVE_30E8,{2U,0U,0U}}, +{MOVE_30E8,{3U,0U,0U}}, +{MOVE_30E8,{4U,0U,0U}}, +{MOVE_30E8,{5U,0U,0U}}, +{MOVE_30E8,{6U,0U,0U}}, +{MOVE_30E8,{7U,0U,0U}}, +{MOVE_30F0,{0U,0U,0U}}, +{MOVE_30F0,{1U,0U,0U}}, +{MOVE_30F0,{2U,0U,0U}}, +{MOVE_30F0,{3U,0U,0U}}, +{MOVE_30F0,{4U,0U,0U}}, +{MOVE_30F0,{5U,0U,0U}}, +{MOVE_30F0,{6U,0U,0U}}, +{MOVE_30F0,{7U,0U,0U}}, +{MOVE_30F8,{0U,0U,0U}}, +{MOVE_30F9,{0U,0U,0U}}, +{MOVE_30FA,{0U,0U,0U}}, +{MOVE_30FB,{0U,0U,0U}}, +{MOVE_30FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3100,{0U,0U,0U}}, +{MOVE_3100,{1U,0U,0U}}, +{MOVE_3100,{2U,0U,0U}}, +{MOVE_3100,{3U,0U,0U}}, +{MOVE_3100,{4U,0U,0U}}, +{MOVE_3100,{5U,0U,0U}}, +{MOVE_3100,{6U,0U,0U}}, +{MOVE_3100,{7U,0U,0U}}, +{MOVE_3108,{0U,0U,0U}}, +{MOVE_3108,{1U,0U,0U}}, +{MOVE_3108,{2U,0U,0U}}, +{MOVE_3108,{3U,0U,0U}}, +{MOVE_3108,{4U,0U,0U}}, +{MOVE_3108,{5U,0U,0U}}, +{MOVE_3108,{6U,0U,0U}}, +{MOVE_3108,{7U,0U,0U}}, +{MOVE_3110,{0U,0U,0U}}, +{MOVE_3110,{1U,0U,0U}}, +{MOVE_3110,{2U,0U,0U}}, +{MOVE_3110,{3U,0U,0U}}, +{MOVE_3110,{4U,0U,0U}}, +{MOVE_3110,{5U,0U,0U}}, +{MOVE_3110,{6U,0U,0U}}, +{MOVE_3110,{7U,0U,0U}}, +{MOVE_3118,{0U,0U,0U}}, +{MOVE_3118,{1U,0U,0U}}, +{MOVE_3118,{2U,0U,0U}}, +{MOVE_3118,{3U,0U,0U}}, +{MOVE_3118,{4U,0U,0U}}, +{MOVE_3118,{5U,0U,0U}}, +{MOVE_3118,{6U,0U,0U}}, +{MOVE_3118,{7U,0U,0U}}, +{MOVE_3120,{0U,0U,0U}}, +{MOVE_3120,{1U,0U,0U}}, +{MOVE_3120,{2U,0U,0U}}, +{MOVE_3120,{3U,0U,0U}}, +{MOVE_3120,{4U,0U,0U}}, +{MOVE_3120,{5U,0U,0U}}, +{MOVE_3120,{6U,0U,0U}}, +{MOVE_3120,{7U,0U,0U}}, +{MOVE_3128,{0U,0U,0U}}, +{MOVE_3128,{1U,0U,0U}}, +{MOVE_3128,{2U,0U,0U}}, +{MOVE_3128,{3U,0U,0U}}, +{MOVE_3128,{4U,0U,0U}}, +{MOVE_3128,{5U,0U,0U}}, +{MOVE_3128,{6U,0U,0U}}, +{MOVE_3128,{7U,0U,0U}}, +{MOVE_3130,{0U,0U,0U}}, +{MOVE_3130,{1U,0U,0U}}, +{MOVE_3130,{2U,0U,0U}}, +{MOVE_3130,{3U,0U,0U}}, +{MOVE_3130,{4U,0U,0U}}, +{MOVE_3130,{5U,0U,0U}}, +{MOVE_3130,{6U,0U,0U}}, +{MOVE_3130,{7U,0U,0U}}, +{MOVE_3138,{0U,0U,0U}}, +{MOVE_3139,{0U,0U,0U}}, +{MOVE_313A,{0U,0U,0U}}, +{MOVE_313B,{0U,0U,0U}}, +{MOVE_313C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3140,{0U,0U,0U}}, +{MOVE_3140,{1U,0U,0U}}, +{MOVE_3140,{2U,0U,0U}}, +{MOVE_3140,{3U,0U,0U}}, +{MOVE_3140,{4U,0U,0U}}, +{MOVE_3140,{5U,0U,0U}}, +{MOVE_3140,{6U,0U,0U}}, +{MOVE_3140,{7U,0U,0U}}, +{MOVE_3148,{0U,0U,0U}}, +{MOVE_3148,{1U,0U,0U}}, +{MOVE_3148,{2U,0U,0U}}, +{MOVE_3148,{3U,0U,0U}}, +{MOVE_3148,{4U,0U,0U}}, +{MOVE_3148,{5U,0U,0U}}, +{MOVE_3148,{6U,0U,0U}}, +{MOVE_3148,{7U,0U,0U}}, +{MOVE_3150,{0U,0U,0U}}, +{MOVE_3150,{1U,0U,0U}}, +{MOVE_3150,{2U,0U,0U}}, +{MOVE_3150,{3U,0U,0U}}, +{MOVE_3150,{4U,0U,0U}}, +{MOVE_3150,{5U,0U,0U}}, +{MOVE_3150,{6U,0U,0U}}, +{MOVE_3150,{7U,0U,0U}}, +{MOVE_3158,{0U,0U,0U}}, +{MOVE_3158,{1U,0U,0U}}, +{MOVE_3158,{2U,0U,0U}}, +{MOVE_3158,{3U,0U,0U}}, +{MOVE_3158,{4U,0U,0U}}, +{MOVE_3158,{5U,0U,0U}}, +{MOVE_3158,{6U,0U,0U}}, +{MOVE_3158,{7U,0U,0U}}, +{MOVE_3160,{0U,0U,0U}}, +{MOVE_3160,{1U,0U,0U}}, +{MOVE_3160,{2U,0U,0U}}, +{MOVE_3160,{3U,0U,0U}}, +{MOVE_3160,{4U,0U,0U}}, +{MOVE_3160,{5U,0U,0U}}, +{MOVE_3160,{6U,0U,0U}}, +{MOVE_3160,{7U,0U,0U}}, +{MOVE_3168,{0U,0U,0U}}, +{MOVE_3168,{1U,0U,0U}}, +{MOVE_3168,{2U,0U,0U}}, +{MOVE_3168,{3U,0U,0U}}, +{MOVE_3168,{4U,0U,0U}}, +{MOVE_3168,{5U,0U,0U}}, +{MOVE_3168,{6U,0U,0U}}, +{MOVE_3168,{7U,0U,0U}}, +{MOVE_3170,{0U,0U,0U}}, +{MOVE_3170,{1U,0U,0U}}, +{MOVE_3170,{2U,0U,0U}}, +{MOVE_3170,{3U,0U,0U}}, +{MOVE_3170,{4U,0U,0U}}, +{MOVE_3170,{5U,0U,0U}}, +{MOVE_3170,{6U,0U,0U}}, +{MOVE_3170,{7U,0U,0U}}, +{MOVE_3178,{0U,0U,0U}}, +{MOVE_3179,{0U,0U,0U}}, +{MOVE_317A,{0U,0U,0U}}, +{MOVE_317B,{0U,0U,0U}}, +{MOVE_317C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3180,{0U,0U,0U}}, +{MOVE_3180,{1U,0U,0U}}, +{MOVE_3180,{2U,0U,0U}}, +{MOVE_3180,{3U,0U,0U}}, +{MOVE_3180,{4U,0U,0U}}, +{MOVE_3180,{5U,0U,0U}}, +{MOVE_3180,{6U,0U,0U}}, +{MOVE_3180,{7U,0U,0U}}, +{MOVE_3188,{0U,0U,0U}}, +{MOVE_3188,{1U,0U,0U}}, +{MOVE_3188,{2U,0U,0U}}, +{MOVE_3188,{3U,0U,0U}}, +{MOVE_3188,{4U,0U,0U}}, +{MOVE_3188,{5U,0U,0U}}, +{MOVE_3188,{6U,0U,0U}}, +{MOVE_3188,{7U,0U,0U}}, +{MOVE_3190,{0U,0U,0U}}, +{MOVE_3190,{1U,0U,0U}}, +{MOVE_3190,{2U,0U,0U}}, +{MOVE_3190,{3U,0U,0U}}, +{MOVE_3190,{4U,0U,0U}}, +{MOVE_3190,{5U,0U,0U}}, +{MOVE_3190,{6U,0U,0U}}, +{MOVE_3190,{7U,0U,0U}}, +{MOVE_3198,{0U,0U,0U}}, +{MOVE_3198,{1U,0U,0U}}, +{MOVE_3198,{2U,0U,0U}}, +{MOVE_3198,{3U,0U,0U}}, +{MOVE_3198,{4U,0U,0U}}, +{MOVE_3198,{5U,0U,0U}}, +{MOVE_3198,{6U,0U,0U}}, +{MOVE_3198,{7U,0U,0U}}, +{MOVE_31A0,{0U,0U,0U}}, +{MOVE_31A0,{1U,0U,0U}}, +{MOVE_31A0,{2U,0U,0U}}, +{MOVE_31A0,{3U,0U,0U}}, +{MOVE_31A0,{4U,0U,0U}}, +{MOVE_31A0,{5U,0U,0U}}, +{MOVE_31A0,{6U,0U,0U}}, +{MOVE_31A0,{7U,0U,0U}}, +{MOVE_31A8,{0U,0U,0U}}, +{MOVE_31A8,{1U,0U,0U}}, +{MOVE_31A8,{2U,0U,0U}}, +{MOVE_31A8,{3U,0U,0U}}, +{MOVE_31A8,{4U,0U,0U}}, +{MOVE_31A8,{5U,0U,0U}}, +{MOVE_31A8,{6U,0U,0U}}, +{MOVE_31A8,{7U,0U,0U}}, +{MOVE_31B0,{0U,0U,0U}}, +{MOVE_31B0,{1U,0U,0U}}, +{MOVE_31B0,{2U,0U,0U}}, +{MOVE_31B0,{3U,0U,0U}}, +{MOVE_31B0,{4U,0U,0U}}, +{MOVE_31B0,{5U,0U,0U}}, +{MOVE_31B0,{6U,0U,0U}}, +{MOVE_31B0,{7U,0U,0U}}, +{MOVE_31B8,{0U,0U,0U}}, +{MOVE_31B9,{0U,0U,0U}}, +{MOVE_31BA,{0U,0U,0U}}, +{MOVE_31BB,{0U,0U,0U}}, +{MOVE_31BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_31C0,{0U,0U,0U}}, +{MOVE_31C0,{1U,0U,0U}}, +{MOVE_31C0,{2U,0U,0U}}, +{MOVE_31C0,{3U,0U,0U}}, +{MOVE_31C0,{4U,0U,0U}}, +{MOVE_31C0,{5U,0U,0U}}, +{MOVE_31C0,{6U,0U,0U}}, +{MOVE_31C0,{7U,0U,0U}}, +{MOVE_31C8,{0U,0U,0U}}, +{MOVE_31C8,{1U,0U,0U}}, +{MOVE_31C8,{2U,0U,0U}}, +{MOVE_31C8,{3U,0U,0U}}, +{MOVE_31C8,{4U,0U,0U}}, +{MOVE_31C8,{5U,0U,0U}}, +{MOVE_31C8,{6U,0U,0U}}, +{MOVE_31C8,{7U,0U,0U}}, +{MOVE_31D0,{0U,0U,0U}}, +{MOVE_31D0,{1U,0U,0U}}, +{MOVE_31D0,{2U,0U,0U}}, +{MOVE_31D0,{3U,0U,0U}}, +{MOVE_31D0,{4U,0U,0U}}, +{MOVE_31D0,{5U,0U,0U}}, +{MOVE_31D0,{6U,0U,0U}}, +{MOVE_31D0,{7U,0U,0U}}, +{MOVE_31D8,{0U,0U,0U}}, +{MOVE_31D8,{1U,0U,0U}}, +{MOVE_31D8,{2U,0U,0U}}, +{MOVE_31D8,{3U,0U,0U}}, +{MOVE_31D8,{4U,0U,0U}}, +{MOVE_31D8,{5U,0U,0U}}, +{MOVE_31D8,{6U,0U,0U}}, +{MOVE_31D8,{7U,0U,0U}}, +{MOVE_31E0,{0U,0U,0U}}, +{MOVE_31E0,{1U,0U,0U}}, +{MOVE_31E0,{2U,0U,0U}}, +{MOVE_31E0,{3U,0U,0U}}, +{MOVE_31E0,{4U,0U,0U}}, +{MOVE_31E0,{5U,0U,0U}}, +{MOVE_31E0,{6U,0U,0U}}, +{MOVE_31E0,{7U,0U,0U}}, +{MOVE_31E8,{0U,0U,0U}}, +{MOVE_31E8,{1U,0U,0U}}, +{MOVE_31E8,{2U,0U,0U}}, +{MOVE_31E8,{3U,0U,0U}}, +{MOVE_31E8,{4U,0U,0U}}, +{MOVE_31E8,{5U,0U,0U}}, +{MOVE_31E8,{6U,0U,0U}}, +{MOVE_31E8,{7U,0U,0U}}, +{MOVE_31F0,{0U,0U,0U}}, +{MOVE_31F0,{1U,0U,0U}}, +{MOVE_31F0,{2U,0U,0U}}, +{MOVE_31F0,{3U,0U,0U}}, +{MOVE_31F0,{4U,0U,0U}}, +{MOVE_31F0,{5U,0U,0U}}, +{MOVE_31F0,{6U,0U,0U}}, +{MOVE_31F0,{7U,0U,0U}}, +{MOVE_31F8,{0U,0U,0U}}, +{MOVE_31F9,{0U,0U,0U}}, +{MOVE_31FA,{0U,0U,0U}}, +{MOVE_31FB,{0U,0U,0U}}, +{MOVE_31FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3000,{0U,1U,0U}}, +{MOVE_3000,{1U,1U,0U}}, +{MOVE_3000,{2U,1U,0U}}, +{MOVE_3000,{3U,1U,0U}}, +{MOVE_3000,{4U,1U,0U}}, +{MOVE_3000,{5U,1U,0U}}, +{MOVE_3000,{6U,1U,0U}}, +{MOVE_3000,{7U,1U,0U}}, +{MOVE_3008,{0U,1U,0U}}, +{MOVE_3008,{1U,1U,0U}}, +{MOVE_3008,{2U,1U,0U}}, +{MOVE_3008,{3U,1U,0U}}, +{MOVE_3008,{4U,1U,0U}}, +{MOVE_3008,{5U,1U,0U}}, +{MOVE_3008,{6U,1U,0U}}, +{MOVE_3008,{7U,1U,0U}}, +{MOVE_3010,{0U,1U,0U}}, +{MOVE_3010,{1U,1U,0U}}, +{MOVE_3010,{2U,1U,0U}}, +{MOVE_3010,{3U,1U,0U}}, +{MOVE_3010,{4U,1U,0U}}, +{MOVE_3010,{5U,1U,0U}}, +{MOVE_3010,{6U,1U,0U}}, +{MOVE_3010,{7U,1U,0U}}, +{MOVE_3018,{0U,1U,0U}}, +{MOVE_3018,{1U,1U,0U}}, +{MOVE_3018,{2U,1U,0U}}, +{MOVE_3018,{3U,1U,0U}}, +{MOVE_3018,{4U,1U,0U}}, +{MOVE_3018,{5U,1U,0U}}, +{MOVE_3018,{6U,1U,0U}}, +{MOVE_3018,{7U,1U,0U}}, +{MOVE_3020,{0U,1U,0U}}, +{MOVE_3020,{1U,1U,0U}}, +{MOVE_3020,{2U,1U,0U}}, +{MOVE_3020,{3U,1U,0U}}, +{MOVE_3020,{4U,1U,0U}}, +{MOVE_3020,{5U,1U,0U}}, +{MOVE_3020,{6U,1U,0U}}, +{MOVE_3020,{7U,1U,0U}}, +{MOVE_3028,{0U,1U,0U}}, +{MOVE_3028,{1U,1U,0U}}, +{MOVE_3028,{2U,1U,0U}}, +{MOVE_3028,{3U,1U,0U}}, +{MOVE_3028,{4U,1U,0U}}, +{MOVE_3028,{5U,1U,0U}}, +{MOVE_3028,{6U,1U,0U}}, +{MOVE_3028,{7U,1U,0U}}, +{MOVE_3030,{0U,1U,0U}}, +{MOVE_3030,{1U,1U,0U}}, +{MOVE_3030,{2U,1U,0U}}, +{MOVE_3030,{3U,1U,0U}}, +{MOVE_3030,{4U,1U,0U}}, +{MOVE_3030,{5U,1U,0U}}, +{MOVE_3030,{6U,1U,0U}}, +{MOVE_3030,{7U,1U,0U}}, +{MOVE_3038,{0U,1U,0U}}, +{MOVE_3039,{0U,1U,0U}}, +{MOVE_303A,{0U,1U,0U}}, +{MOVE_303B,{0U,1U,0U}}, +{MOVE_303C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_3040,{0U,1U,0U}}, +{MOVEA_3040,{1U,1U,0U}}, +{MOVEA_3040,{2U,1U,0U}}, +{MOVEA_3040,{3U,1U,0U}}, +{MOVEA_3040,{4U,1U,0U}}, +{MOVEA_3040,{5U,1U,0U}}, +{MOVEA_3040,{6U,1U,0U}}, +{MOVEA_3040,{7U,1U,0U}}, +{MOVEA_3048,{0U,1U,0U}}, +{MOVEA_3048,{1U,1U,0U}}, +{MOVEA_3048,{2U,1U,0U}}, +{MOVEA_3048,{3U,1U,0U}}, +{MOVEA_3048,{4U,1U,0U}}, +{MOVEA_3048,{5U,1U,0U}}, +{MOVEA_3048,{6U,1U,0U}}, +{MOVEA_3048,{7U,1U,0U}}, +{MOVEA_3050,{0U,1U,0U}}, +{MOVEA_3050,{1U,1U,0U}}, +{MOVEA_3050,{2U,1U,0U}}, +{MOVEA_3050,{3U,1U,0U}}, +{MOVEA_3050,{4U,1U,0U}}, +{MOVEA_3050,{5U,1U,0U}}, +{MOVEA_3050,{6U,1U,0U}}, +{MOVEA_3050,{7U,1U,0U}}, +{MOVEA_3058,{0U,1U,0U}}, +{MOVEA_3058,{1U,1U,0U}}, +{MOVEA_3058,{2U,1U,0U}}, +{MOVEA_3058,{3U,1U,0U}}, +{MOVEA_3058,{4U,1U,0U}}, +{MOVEA_3058,{5U,1U,0U}}, +{MOVEA_3058,{6U,1U,0U}}, +{MOVEA_3058,{7U,1U,0U}}, +{MOVEA_3060,{0U,1U,0U}}, +{MOVEA_3060,{1U,1U,0U}}, +{MOVEA_3060,{2U,1U,0U}}, +{MOVEA_3060,{3U,1U,0U}}, +{MOVEA_3060,{4U,1U,0U}}, +{MOVEA_3060,{5U,1U,0U}}, +{MOVEA_3060,{6U,1U,0U}}, +{MOVEA_3060,{7U,1U,0U}}, +{MOVEA_3068,{0U,1U,0U}}, +{MOVEA_3068,{1U,1U,0U}}, +{MOVEA_3068,{2U,1U,0U}}, +{MOVEA_3068,{3U,1U,0U}}, +{MOVEA_3068,{4U,1U,0U}}, +{MOVEA_3068,{5U,1U,0U}}, +{MOVEA_3068,{6U,1U,0U}}, +{MOVEA_3068,{7U,1U,0U}}, +{MOVEA_3070,{0U,1U,0U}}, +{MOVEA_3070,{1U,1U,0U}}, +{MOVEA_3070,{2U,1U,0U}}, +{MOVEA_3070,{3U,1U,0U}}, +{MOVEA_3070,{4U,1U,0U}}, +{MOVEA_3070,{5U,1U,0U}}, +{MOVEA_3070,{6U,1U,0U}}, +{MOVEA_3070,{7U,1U,0U}}, +{MOVEA_3078,{0U,1U,0U}}, +{MOVEA_3079,{0U,1U,0U}}, +{MOVEA_307A,{0U,1U,0U}}, +{MOVEA_307B,{0U,1U,0U}}, +{MOVEA_307C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3080,{0U,1U,0U}}, +{MOVE_3080,{1U,1U,0U}}, +{MOVE_3080,{2U,1U,0U}}, +{MOVE_3080,{3U,1U,0U}}, +{MOVE_3080,{4U,1U,0U}}, +{MOVE_3080,{5U,1U,0U}}, +{MOVE_3080,{6U,1U,0U}}, +{MOVE_3080,{7U,1U,0U}}, +{MOVE_3088,{0U,1U,0U}}, +{MOVE_3088,{1U,1U,0U}}, +{MOVE_3088,{2U,1U,0U}}, +{MOVE_3088,{3U,1U,0U}}, +{MOVE_3088,{4U,1U,0U}}, +{MOVE_3088,{5U,1U,0U}}, +{MOVE_3088,{6U,1U,0U}}, +{MOVE_3088,{7U,1U,0U}}, +{MOVE_3090,{0U,1U,0U}}, +{MOVE_3090,{1U,1U,0U}}, +{MOVE_3090,{2U,1U,0U}}, +{MOVE_3090,{3U,1U,0U}}, +{MOVE_3090,{4U,1U,0U}}, +{MOVE_3090,{5U,1U,0U}}, +{MOVE_3090,{6U,1U,0U}}, +{MOVE_3090,{7U,1U,0U}}, +{MOVE_3098,{0U,1U,0U}}, +{MOVE_3098,{1U,1U,0U}}, +{MOVE_3098,{2U,1U,0U}}, +{MOVE_3098,{3U,1U,0U}}, +{MOVE_3098,{4U,1U,0U}}, +{MOVE_3098,{5U,1U,0U}}, +{MOVE_3098,{6U,1U,0U}}, +{MOVE_3098,{7U,1U,0U}}, +{MOVE_30A0,{0U,1U,0U}}, +{MOVE_30A0,{1U,1U,0U}}, +{MOVE_30A0,{2U,1U,0U}}, +{MOVE_30A0,{3U,1U,0U}}, +{MOVE_30A0,{4U,1U,0U}}, +{MOVE_30A0,{5U,1U,0U}}, +{MOVE_30A0,{6U,1U,0U}}, +{MOVE_30A0,{7U,1U,0U}}, +{MOVE_30A8,{0U,1U,0U}}, +{MOVE_30A8,{1U,1U,0U}}, +{MOVE_30A8,{2U,1U,0U}}, +{MOVE_30A8,{3U,1U,0U}}, +{MOVE_30A8,{4U,1U,0U}}, +{MOVE_30A8,{5U,1U,0U}}, +{MOVE_30A8,{6U,1U,0U}}, +{MOVE_30A8,{7U,1U,0U}}, +{MOVE_30B0,{0U,1U,0U}}, +{MOVE_30B0,{1U,1U,0U}}, +{MOVE_30B0,{2U,1U,0U}}, +{MOVE_30B0,{3U,1U,0U}}, +{MOVE_30B0,{4U,1U,0U}}, +{MOVE_30B0,{5U,1U,0U}}, +{MOVE_30B0,{6U,1U,0U}}, +{MOVE_30B0,{7U,1U,0U}}, +{MOVE_30B8,{0U,1U,0U}}, +{MOVE_30B9,{0U,1U,0U}}, +{MOVE_30BA,{0U,1U,0U}}, +{MOVE_30BB,{0U,1U,0U}}, +{MOVE_30BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_30C0,{0U,1U,0U}}, +{MOVE_30C0,{1U,1U,0U}}, +{MOVE_30C0,{2U,1U,0U}}, +{MOVE_30C0,{3U,1U,0U}}, +{MOVE_30C0,{4U,1U,0U}}, +{MOVE_30C0,{5U,1U,0U}}, +{MOVE_30C0,{6U,1U,0U}}, +{MOVE_30C0,{7U,1U,0U}}, +{MOVE_30C8,{0U,1U,0U}}, +{MOVE_30C8,{1U,1U,0U}}, +{MOVE_30C8,{2U,1U,0U}}, +{MOVE_30C8,{3U,1U,0U}}, +{MOVE_30C8,{4U,1U,0U}}, +{MOVE_30C8,{5U,1U,0U}}, +{MOVE_30C8,{6U,1U,0U}}, +{MOVE_30C8,{7U,1U,0U}}, +{MOVE_30D0,{0U,1U,0U}}, +{MOVE_30D0,{1U,1U,0U}}, +{MOVE_30D0,{2U,1U,0U}}, +{MOVE_30D0,{3U,1U,0U}}, +{MOVE_30D0,{4U,1U,0U}}, +{MOVE_30D0,{5U,1U,0U}}, +{MOVE_30D0,{6U,1U,0U}}, +{MOVE_30D0,{7U,1U,0U}}, +{MOVE_30D8,{0U,1U,0U}}, +{MOVE_30D8,{1U,1U,0U}}, +{MOVE_30D8,{2U,1U,0U}}, +{MOVE_30D8,{3U,1U,0U}}, +{MOVE_30D8,{4U,1U,0U}}, +{MOVE_30D8,{5U,1U,0U}}, +{MOVE_30D8,{6U,1U,0U}}, +{MOVE_30D8,{7U,1U,0U}}, +{MOVE_30E0,{0U,1U,0U}}, +{MOVE_30E0,{1U,1U,0U}}, +{MOVE_30E0,{2U,1U,0U}}, +{MOVE_30E0,{3U,1U,0U}}, +{MOVE_30E0,{4U,1U,0U}}, +{MOVE_30E0,{5U,1U,0U}}, +{MOVE_30E0,{6U,1U,0U}}, +{MOVE_30E0,{7U,1U,0U}}, +{MOVE_30E8,{0U,1U,0U}}, +{MOVE_30E8,{1U,1U,0U}}, +{MOVE_30E8,{2U,1U,0U}}, +{MOVE_30E8,{3U,1U,0U}}, +{MOVE_30E8,{4U,1U,0U}}, +{MOVE_30E8,{5U,1U,0U}}, +{MOVE_30E8,{6U,1U,0U}}, +{MOVE_30E8,{7U,1U,0U}}, +{MOVE_30F0,{0U,1U,0U}}, +{MOVE_30F0,{1U,1U,0U}}, +{MOVE_30F0,{2U,1U,0U}}, +{MOVE_30F0,{3U,1U,0U}}, +{MOVE_30F0,{4U,1U,0U}}, +{MOVE_30F0,{5U,1U,0U}}, +{MOVE_30F0,{6U,1U,0U}}, +{MOVE_30F0,{7U,1U,0U}}, +{MOVE_30F8,{0U,1U,0U}}, +{MOVE_30F9,{0U,1U,0U}}, +{MOVE_30FA,{0U,1U,0U}}, +{MOVE_30FB,{0U,1U,0U}}, +{MOVE_30FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3100,{0U,1U,0U}}, +{MOVE_3100,{1U,1U,0U}}, +{MOVE_3100,{2U,1U,0U}}, +{MOVE_3100,{3U,1U,0U}}, +{MOVE_3100,{4U,1U,0U}}, +{MOVE_3100,{5U,1U,0U}}, +{MOVE_3100,{6U,1U,0U}}, +{MOVE_3100,{7U,1U,0U}}, +{MOVE_3108,{0U,1U,0U}}, +{MOVE_3108,{1U,1U,0U}}, +{MOVE_3108,{2U,1U,0U}}, +{MOVE_3108,{3U,1U,0U}}, +{MOVE_3108,{4U,1U,0U}}, +{MOVE_3108,{5U,1U,0U}}, +{MOVE_3108,{6U,1U,0U}}, +{MOVE_3108,{7U,1U,0U}}, +{MOVE_3110,{0U,1U,0U}}, +{MOVE_3110,{1U,1U,0U}}, +{MOVE_3110,{2U,1U,0U}}, +{MOVE_3110,{3U,1U,0U}}, +{MOVE_3110,{4U,1U,0U}}, +{MOVE_3110,{5U,1U,0U}}, +{MOVE_3110,{6U,1U,0U}}, +{MOVE_3110,{7U,1U,0U}}, +{MOVE_3118,{0U,1U,0U}}, +{MOVE_3118,{1U,1U,0U}}, +{MOVE_3118,{2U,1U,0U}}, +{MOVE_3118,{3U,1U,0U}}, +{MOVE_3118,{4U,1U,0U}}, +{MOVE_3118,{5U,1U,0U}}, +{MOVE_3118,{6U,1U,0U}}, +{MOVE_3118,{7U,1U,0U}}, +{MOVE_3120,{0U,1U,0U}}, +{MOVE_3120,{1U,1U,0U}}, +{MOVE_3120,{2U,1U,0U}}, +{MOVE_3120,{3U,1U,0U}}, +{MOVE_3120,{4U,1U,0U}}, +{MOVE_3120,{5U,1U,0U}}, +{MOVE_3120,{6U,1U,0U}}, +{MOVE_3120,{7U,1U,0U}}, +{MOVE_3128,{0U,1U,0U}}, +{MOVE_3128,{1U,1U,0U}}, +{MOVE_3128,{2U,1U,0U}}, +{MOVE_3128,{3U,1U,0U}}, +{MOVE_3128,{4U,1U,0U}}, +{MOVE_3128,{5U,1U,0U}}, +{MOVE_3128,{6U,1U,0U}}, +{MOVE_3128,{7U,1U,0U}}, +{MOVE_3130,{0U,1U,0U}}, +{MOVE_3130,{1U,1U,0U}}, +{MOVE_3130,{2U,1U,0U}}, +{MOVE_3130,{3U,1U,0U}}, +{MOVE_3130,{4U,1U,0U}}, +{MOVE_3130,{5U,1U,0U}}, +{MOVE_3130,{6U,1U,0U}}, +{MOVE_3130,{7U,1U,0U}}, +{MOVE_3138,{0U,1U,0U}}, +{MOVE_3139,{0U,1U,0U}}, +{MOVE_313A,{0U,1U,0U}}, +{MOVE_313B,{0U,1U,0U}}, +{MOVE_313C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3140,{0U,1U,0U}}, +{MOVE_3140,{1U,1U,0U}}, +{MOVE_3140,{2U,1U,0U}}, +{MOVE_3140,{3U,1U,0U}}, +{MOVE_3140,{4U,1U,0U}}, +{MOVE_3140,{5U,1U,0U}}, +{MOVE_3140,{6U,1U,0U}}, +{MOVE_3140,{7U,1U,0U}}, +{MOVE_3148,{0U,1U,0U}}, +{MOVE_3148,{1U,1U,0U}}, +{MOVE_3148,{2U,1U,0U}}, +{MOVE_3148,{3U,1U,0U}}, +{MOVE_3148,{4U,1U,0U}}, +{MOVE_3148,{5U,1U,0U}}, +{MOVE_3148,{6U,1U,0U}}, +{MOVE_3148,{7U,1U,0U}}, +{MOVE_3150,{0U,1U,0U}}, +{MOVE_3150,{1U,1U,0U}}, +{MOVE_3150,{2U,1U,0U}}, +{MOVE_3150,{3U,1U,0U}}, +{MOVE_3150,{4U,1U,0U}}, +{MOVE_3150,{5U,1U,0U}}, +{MOVE_3150,{6U,1U,0U}}, +{MOVE_3150,{7U,1U,0U}}, +{MOVE_3158,{0U,1U,0U}}, +{MOVE_3158,{1U,1U,0U}}, +{MOVE_3158,{2U,1U,0U}}, +{MOVE_3158,{3U,1U,0U}}, +{MOVE_3158,{4U,1U,0U}}, +{MOVE_3158,{5U,1U,0U}}, +{MOVE_3158,{6U,1U,0U}}, +{MOVE_3158,{7U,1U,0U}}, +{MOVE_3160,{0U,1U,0U}}, +{MOVE_3160,{1U,1U,0U}}, +{MOVE_3160,{2U,1U,0U}}, +{MOVE_3160,{3U,1U,0U}}, +{MOVE_3160,{4U,1U,0U}}, +{MOVE_3160,{5U,1U,0U}}, +{MOVE_3160,{6U,1U,0U}}, +{MOVE_3160,{7U,1U,0U}}, +{MOVE_3168,{0U,1U,0U}}, +{MOVE_3168,{1U,1U,0U}}, +{MOVE_3168,{2U,1U,0U}}, +{MOVE_3168,{3U,1U,0U}}, +{MOVE_3168,{4U,1U,0U}}, +{MOVE_3168,{5U,1U,0U}}, +{MOVE_3168,{6U,1U,0U}}, +{MOVE_3168,{7U,1U,0U}}, +{MOVE_3170,{0U,1U,0U}}, +{MOVE_3170,{1U,1U,0U}}, +{MOVE_3170,{2U,1U,0U}}, +{MOVE_3170,{3U,1U,0U}}, +{MOVE_3170,{4U,1U,0U}}, +{MOVE_3170,{5U,1U,0U}}, +{MOVE_3170,{6U,1U,0U}}, +{MOVE_3170,{7U,1U,0U}}, +{MOVE_3178,{0U,1U,0U}}, +{MOVE_3179,{0U,1U,0U}}, +{MOVE_317A,{0U,1U,0U}}, +{MOVE_317B,{0U,1U,0U}}, +{MOVE_317C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3180,{0U,1U,0U}}, +{MOVE_3180,{1U,1U,0U}}, +{MOVE_3180,{2U,1U,0U}}, +{MOVE_3180,{3U,1U,0U}}, +{MOVE_3180,{4U,1U,0U}}, +{MOVE_3180,{5U,1U,0U}}, +{MOVE_3180,{6U,1U,0U}}, +{MOVE_3180,{7U,1U,0U}}, +{MOVE_3188,{0U,1U,0U}}, +{MOVE_3188,{1U,1U,0U}}, +{MOVE_3188,{2U,1U,0U}}, +{MOVE_3188,{3U,1U,0U}}, +{MOVE_3188,{4U,1U,0U}}, +{MOVE_3188,{5U,1U,0U}}, +{MOVE_3188,{6U,1U,0U}}, +{MOVE_3188,{7U,1U,0U}}, +{MOVE_3190,{0U,1U,0U}}, +{MOVE_3190,{1U,1U,0U}}, +{MOVE_3190,{2U,1U,0U}}, +{MOVE_3190,{3U,1U,0U}}, +{MOVE_3190,{4U,1U,0U}}, +{MOVE_3190,{5U,1U,0U}}, +{MOVE_3190,{6U,1U,0U}}, +{MOVE_3190,{7U,1U,0U}}, +{MOVE_3198,{0U,1U,0U}}, +{MOVE_3198,{1U,1U,0U}}, +{MOVE_3198,{2U,1U,0U}}, +{MOVE_3198,{3U,1U,0U}}, +{MOVE_3198,{4U,1U,0U}}, +{MOVE_3198,{5U,1U,0U}}, +{MOVE_3198,{6U,1U,0U}}, +{MOVE_3198,{7U,1U,0U}}, +{MOVE_31A0,{0U,1U,0U}}, +{MOVE_31A0,{1U,1U,0U}}, +{MOVE_31A0,{2U,1U,0U}}, +{MOVE_31A0,{3U,1U,0U}}, +{MOVE_31A0,{4U,1U,0U}}, +{MOVE_31A0,{5U,1U,0U}}, +{MOVE_31A0,{6U,1U,0U}}, +{MOVE_31A0,{7U,1U,0U}}, +{MOVE_31A8,{0U,1U,0U}}, +{MOVE_31A8,{1U,1U,0U}}, +{MOVE_31A8,{2U,1U,0U}}, +{MOVE_31A8,{3U,1U,0U}}, +{MOVE_31A8,{4U,1U,0U}}, +{MOVE_31A8,{5U,1U,0U}}, +{MOVE_31A8,{6U,1U,0U}}, +{MOVE_31A8,{7U,1U,0U}}, +{MOVE_31B0,{0U,1U,0U}}, +{MOVE_31B0,{1U,1U,0U}}, +{MOVE_31B0,{2U,1U,0U}}, +{MOVE_31B0,{3U,1U,0U}}, +{MOVE_31B0,{4U,1U,0U}}, +{MOVE_31B0,{5U,1U,0U}}, +{MOVE_31B0,{6U,1U,0U}}, +{MOVE_31B0,{7U,1U,0U}}, +{MOVE_31B8,{0U,1U,0U}}, +{MOVE_31B9,{0U,1U,0U}}, +{MOVE_31BA,{0U,1U,0U}}, +{MOVE_31BB,{0U,1U,0U}}, +{MOVE_31BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_33C0,{0U,0U,0U}}, +{MOVE_33C0,{1U,0U,0U}}, +{MOVE_33C0,{2U,0U,0U}}, +{MOVE_33C0,{3U,0U,0U}}, +{MOVE_33C0,{4U,0U,0U}}, +{MOVE_33C0,{5U,0U,0U}}, +{MOVE_33C0,{6U,0U,0U}}, +{MOVE_33C0,{7U,0U,0U}}, +{MOVE_33C8,{0U,0U,0U}}, +{MOVE_33C8,{1U,0U,0U}}, +{MOVE_33C8,{2U,0U,0U}}, +{MOVE_33C8,{3U,0U,0U}}, +{MOVE_33C8,{4U,0U,0U}}, +{MOVE_33C8,{5U,0U,0U}}, +{MOVE_33C8,{6U,0U,0U}}, +{MOVE_33C8,{7U,0U,0U}}, +{MOVE_33D0,{0U,0U,0U}}, +{MOVE_33D0,{1U,0U,0U}}, +{MOVE_33D0,{2U,0U,0U}}, +{MOVE_33D0,{3U,0U,0U}}, +{MOVE_33D0,{4U,0U,0U}}, +{MOVE_33D0,{5U,0U,0U}}, +{MOVE_33D0,{6U,0U,0U}}, +{MOVE_33D0,{7U,0U,0U}}, +{MOVE_33D8,{0U,0U,0U}}, +{MOVE_33D8,{1U,0U,0U}}, +{MOVE_33D8,{2U,0U,0U}}, +{MOVE_33D8,{3U,0U,0U}}, +{MOVE_33D8,{4U,0U,0U}}, +{MOVE_33D8,{5U,0U,0U}}, +{MOVE_33D8,{6U,0U,0U}}, +{MOVE_33D8,{7U,0U,0U}}, +{MOVE_33E0,{0U,0U,0U}}, +{MOVE_33E0,{1U,0U,0U}}, +{MOVE_33E0,{2U,0U,0U}}, +{MOVE_33E0,{3U,0U,0U}}, +{MOVE_33E0,{4U,0U,0U}}, +{MOVE_33E0,{5U,0U,0U}}, +{MOVE_33E0,{6U,0U,0U}}, +{MOVE_33E0,{7U,0U,0U}}, +{MOVE_33E8,{0U,0U,0U}}, +{MOVE_33E8,{1U,0U,0U}}, +{MOVE_33E8,{2U,0U,0U}}, +{MOVE_33E8,{3U,0U,0U}}, +{MOVE_33E8,{4U,0U,0U}}, +{MOVE_33E8,{5U,0U,0U}}, +{MOVE_33E8,{6U,0U,0U}}, +{MOVE_33E8,{7U,0U,0U}}, +{MOVE_33F0,{0U,0U,0U}}, +{MOVE_33F0,{1U,0U,0U}}, +{MOVE_33F0,{2U,0U,0U}}, +{MOVE_33F0,{3U,0U,0U}}, +{MOVE_33F0,{4U,0U,0U}}, +{MOVE_33F0,{5U,0U,0U}}, +{MOVE_33F0,{6U,0U,0U}}, +{MOVE_33F0,{7U,0U,0U}}, +{MOVE_33F8,{0U,0U,0U}}, +{MOVE_33F9,{0U,0U,0U}}, +{MOVE_33FA,{0U,0U,0U}}, +{MOVE_33FB,{0U,0U,0U}}, +{MOVE_33FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3000,{0U,2U,0U}}, +{MOVE_3000,{1U,2U,0U}}, +{MOVE_3000,{2U,2U,0U}}, +{MOVE_3000,{3U,2U,0U}}, +{MOVE_3000,{4U,2U,0U}}, +{MOVE_3000,{5U,2U,0U}}, +{MOVE_3000,{6U,2U,0U}}, +{MOVE_3000,{7U,2U,0U}}, +{MOVE_3008,{0U,2U,0U}}, +{MOVE_3008,{1U,2U,0U}}, +{MOVE_3008,{2U,2U,0U}}, +{MOVE_3008,{3U,2U,0U}}, +{MOVE_3008,{4U,2U,0U}}, +{MOVE_3008,{5U,2U,0U}}, +{MOVE_3008,{6U,2U,0U}}, +{MOVE_3008,{7U,2U,0U}}, +{MOVE_3010,{0U,2U,0U}}, +{MOVE_3010,{1U,2U,0U}}, +{MOVE_3010,{2U,2U,0U}}, +{MOVE_3010,{3U,2U,0U}}, +{MOVE_3010,{4U,2U,0U}}, +{MOVE_3010,{5U,2U,0U}}, +{MOVE_3010,{6U,2U,0U}}, +{MOVE_3010,{7U,2U,0U}}, +{MOVE_3018,{0U,2U,0U}}, +{MOVE_3018,{1U,2U,0U}}, +{MOVE_3018,{2U,2U,0U}}, +{MOVE_3018,{3U,2U,0U}}, +{MOVE_3018,{4U,2U,0U}}, +{MOVE_3018,{5U,2U,0U}}, +{MOVE_3018,{6U,2U,0U}}, +{MOVE_3018,{7U,2U,0U}}, +{MOVE_3020,{0U,2U,0U}}, +{MOVE_3020,{1U,2U,0U}}, +{MOVE_3020,{2U,2U,0U}}, +{MOVE_3020,{3U,2U,0U}}, +{MOVE_3020,{4U,2U,0U}}, +{MOVE_3020,{5U,2U,0U}}, +{MOVE_3020,{6U,2U,0U}}, +{MOVE_3020,{7U,2U,0U}}, +{MOVE_3028,{0U,2U,0U}}, +{MOVE_3028,{1U,2U,0U}}, +{MOVE_3028,{2U,2U,0U}}, +{MOVE_3028,{3U,2U,0U}}, +{MOVE_3028,{4U,2U,0U}}, +{MOVE_3028,{5U,2U,0U}}, +{MOVE_3028,{6U,2U,0U}}, +{MOVE_3028,{7U,2U,0U}}, +{MOVE_3030,{0U,2U,0U}}, +{MOVE_3030,{1U,2U,0U}}, +{MOVE_3030,{2U,2U,0U}}, +{MOVE_3030,{3U,2U,0U}}, +{MOVE_3030,{4U,2U,0U}}, +{MOVE_3030,{5U,2U,0U}}, +{MOVE_3030,{6U,2U,0U}}, +{MOVE_3030,{7U,2U,0U}}, +{MOVE_3038,{0U,2U,0U}}, +{MOVE_3039,{0U,2U,0U}}, +{MOVE_303A,{0U,2U,0U}}, +{MOVE_303B,{0U,2U,0U}}, +{MOVE_303C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_3040,{0U,2U,0U}}, +{MOVEA_3040,{1U,2U,0U}}, +{MOVEA_3040,{2U,2U,0U}}, +{MOVEA_3040,{3U,2U,0U}}, +{MOVEA_3040,{4U,2U,0U}}, +{MOVEA_3040,{5U,2U,0U}}, +{MOVEA_3040,{6U,2U,0U}}, +{MOVEA_3040,{7U,2U,0U}}, +{MOVEA_3048,{0U,2U,0U}}, +{MOVEA_3048,{1U,2U,0U}}, +{MOVEA_3048,{2U,2U,0U}}, +{MOVEA_3048,{3U,2U,0U}}, +{MOVEA_3048,{4U,2U,0U}}, +{MOVEA_3048,{5U,2U,0U}}, +{MOVEA_3048,{6U,2U,0U}}, +{MOVEA_3048,{7U,2U,0U}}, +{MOVEA_3050,{0U,2U,0U}}, +{MOVEA_3050,{1U,2U,0U}}, +{MOVEA_3050,{2U,2U,0U}}, +{MOVEA_3050,{3U,2U,0U}}, +{MOVEA_3050,{4U,2U,0U}}, +{MOVEA_3050,{5U,2U,0U}}, +{MOVEA_3050,{6U,2U,0U}}, +{MOVEA_3050,{7U,2U,0U}}, +{MOVEA_3058,{0U,2U,0U}}, +{MOVEA_3058,{1U,2U,0U}}, +{MOVEA_3058,{2U,2U,0U}}, +{MOVEA_3058,{3U,2U,0U}}, +{MOVEA_3058,{4U,2U,0U}}, +{MOVEA_3058,{5U,2U,0U}}, +{MOVEA_3058,{6U,2U,0U}}, +{MOVEA_3058,{7U,2U,0U}}, +{MOVEA_3060,{0U,2U,0U}}, +{MOVEA_3060,{1U,2U,0U}}, +{MOVEA_3060,{2U,2U,0U}}, +{MOVEA_3060,{3U,2U,0U}}, +{MOVEA_3060,{4U,2U,0U}}, +{MOVEA_3060,{5U,2U,0U}}, +{MOVEA_3060,{6U,2U,0U}}, +{MOVEA_3060,{7U,2U,0U}}, +{MOVEA_3068,{0U,2U,0U}}, +{MOVEA_3068,{1U,2U,0U}}, +{MOVEA_3068,{2U,2U,0U}}, +{MOVEA_3068,{3U,2U,0U}}, +{MOVEA_3068,{4U,2U,0U}}, +{MOVEA_3068,{5U,2U,0U}}, +{MOVEA_3068,{6U,2U,0U}}, +{MOVEA_3068,{7U,2U,0U}}, +{MOVEA_3070,{0U,2U,0U}}, +{MOVEA_3070,{1U,2U,0U}}, +{MOVEA_3070,{2U,2U,0U}}, +{MOVEA_3070,{3U,2U,0U}}, +{MOVEA_3070,{4U,2U,0U}}, +{MOVEA_3070,{5U,2U,0U}}, +{MOVEA_3070,{6U,2U,0U}}, +{MOVEA_3070,{7U,2U,0U}}, +{MOVEA_3078,{0U,2U,0U}}, +{MOVEA_3079,{0U,2U,0U}}, +{MOVEA_307A,{0U,2U,0U}}, +{MOVEA_307B,{0U,2U,0U}}, +{MOVEA_307C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3080,{0U,2U,0U}}, +{MOVE_3080,{1U,2U,0U}}, +{MOVE_3080,{2U,2U,0U}}, +{MOVE_3080,{3U,2U,0U}}, +{MOVE_3080,{4U,2U,0U}}, +{MOVE_3080,{5U,2U,0U}}, +{MOVE_3080,{6U,2U,0U}}, +{MOVE_3080,{7U,2U,0U}}, +{MOVE_3088,{0U,2U,0U}}, +{MOVE_3088,{1U,2U,0U}}, +{MOVE_3088,{2U,2U,0U}}, +{MOVE_3088,{3U,2U,0U}}, +{MOVE_3088,{4U,2U,0U}}, +{MOVE_3088,{5U,2U,0U}}, +{MOVE_3088,{6U,2U,0U}}, +{MOVE_3088,{7U,2U,0U}}, +{MOVE_3090,{0U,2U,0U}}, +{MOVE_3090,{1U,2U,0U}}, +{MOVE_3090,{2U,2U,0U}}, +{MOVE_3090,{3U,2U,0U}}, +{MOVE_3090,{4U,2U,0U}}, +{MOVE_3090,{5U,2U,0U}}, +{MOVE_3090,{6U,2U,0U}}, +{MOVE_3090,{7U,2U,0U}}, +{MOVE_3098,{0U,2U,0U}}, +{MOVE_3098,{1U,2U,0U}}, +{MOVE_3098,{2U,2U,0U}}, +{MOVE_3098,{3U,2U,0U}}, +{MOVE_3098,{4U,2U,0U}}, +{MOVE_3098,{5U,2U,0U}}, +{MOVE_3098,{6U,2U,0U}}, +{MOVE_3098,{7U,2U,0U}}, +{MOVE_30A0,{0U,2U,0U}}, +{MOVE_30A0,{1U,2U,0U}}, +{MOVE_30A0,{2U,2U,0U}}, +{MOVE_30A0,{3U,2U,0U}}, +{MOVE_30A0,{4U,2U,0U}}, +{MOVE_30A0,{5U,2U,0U}}, +{MOVE_30A0,{6U,2U,0U}}, +{MOVE_30A0,{7U,2U,0U}}, +{MOVE_30A8,{0U,2U,0U}}, +{MOVE_30A8,{1U,2U,0U}}, +{MOVE_30A8,{2U,2U,0U}}, +{MOVE_30A8,{3U,2U,0U}}, +{MOVE_30A8,{4U,2U,0U}}, +{MOVE_30A8,{5U,2U,0U}}, +{MOVE_30A8,{6U,2U,0U}}, +{MOVE_30A8,{7U,2U,0U}}, +{MOVE_30B0,{0U,2U,0U}}, +{MOVE_30B0,{1U,2U,0U}}, +{MOVE_30B0,{2U,2U,0U}}, +{MOVE_30B0,{3U,2U,0U}}, +{MOVE_30B0,{4U,2U,0U}}, +{MOVE_30B0,{5U,2U,0U}}, +{MOVE_30B0,{6U,2U,0U}}, +{MOVE_30B0,{7U,2U,0U}}, +{MOVE_30B8,{0U,2U,0U}}, +{MOVE_30B9,{0U,2U,0U}}, +{MOVE_30BA,{0U,2U,0U}}, +{MOVE_30BB,{0U,2U,0U}}, +{MOVE_30BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_30C0,{0U,2U,0U}}, +{MOVE_30C0,{1U,2U,0U}}, +{MOVE_30C0,{2U,2U,0U}}, +{MOVE_30C0,{3U,2U,0U}}, +{MOVE_30C0,{4U,2U,0U}}, +{MOVE_30C0,{5U,2U,0U}}, +{MOVE_30C0,{6U,2U,0U}}, +{MOVE_30C0,{7U,2U,0U}}, +{MOVE_30C8,{0U,2U,0U}}, +{MOVE_30C8,{1U,2U,0U}}, +{MOVE_30C8,{2U,2U,0U}}, +{MOVE_30C8,{3U,2U,0U}}, +{MOVE_30C8,{4U,2U,0U}}, +{MOVE_30C8,{5U,2U,0U}}, +{MOVE_30C8,{6U,2U,0U}}, +{MOVE_30C8,{7U,2U,0U}}, +{MOVE_30D0,{0U,2U,0U}}, +{MOVE_30D0,{1U,2U,0U}}, +{MOVE_30D0,{2U,2U,0U}}, +{MOVE_30D0,{3U,2U,0U}}, +{MOVE_30D0,{4U,2U,0U}}, +{MOVE_30D0,{5U,2U,0U}}, +{MOVE_30D0,{6U,2U,0U}}, +{MOVE_30D0,{7U,2U,0U}}, +{MOVE_30D8,{0U,2U,0U}}, +{MOVE_30D8,{1U,2U,0U}}, +{MOVE_30D8,{2U,2U,0U}}, +{MOVE_30D8,{3U,2U,0U}}, +{MOVE_30D8,{4U,2U,0U}}, +{MOVE_30D8,{5U,2U,0U}}, +{MOVE_30D8,{6U,2U,0U}}, +{MOVE_30D8,{7U,2U,0U}}, +{MOVE_30E0,{0U,2U,0U}}, +{MOVE_30E0,{1U,2U,0U}}, +{MOVE_30E0,{2U,2U,0U}}, +{MOVE_30E0,{3U,2U,0U}}, +{MOVE_30E0,{4U,2U,0U}}, +{MOVE_30E0,{5U,2U,0U}}, +{MOVE_30E0,{6U,2U,0U}}, +{MOVE_30E0,{7U,2U,0U}}, +{MOVE_30E8,{0U,2U,0U}}, +{MOVE_30E8,{1U,2U,0U}}, +{MOVE_30E8,{2U,2U,0U}}, +{MOVE_30E8,{3U,2U,0U}}, +{MOVE_30E8,{4U,2U,0U}}, +{MOVE_30E8,{5U,2U,0U}}, +{MOVE_30E8,{6U,2U,0U}}, +{MOVE_30E8,{7U,2U,0U}}, +{MOVE_30F0,{0U,2U,0U}}, +{MOVE_30F0,{1U,2U,0U}}, +{MOVE_30F0,{2U,2U,0U}}, +{MOVE_30F0,{3U,2U,0U}}, +{MOVE_30F0,{4U,2U,0U}}, +{MOVE_30F0,{5U,2U,0U}}, +{MOVE_30F0,{6U,2U,0U}}, +{MOVE_30F0,{7U,2U,0U}}, +{MOVE_30F8,{0U,2U,0U}}, +{MOVE_30F9,{0U,2U,0U}}, +{MOVE_30FA,{0U,2U,0U}}, +{MOVE_30FB,{0U,2U,0U}}, +{MOVE_30FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3100,{0U,2U,0U}}, +{MOVE_3100,{1U,2U,0U}}, +{MOVE_3100,{2U,2U,0U}}, +{MOVE_3100,{3U,2U,0U}}, +{MOVE_3100,{4U,2U,0U}}, +{MOVE_3100,{5U,2U,0U}}, +{MOVE_3100,{6U,2U,0U}}, +{MOVE_3100,{7U,2U,0U}}, +{MOVE_3108,{0U,2U,0U}}, +{MOVE_3108,{1U,2U,0U}}, +{MOVE_3108,{2U,2U,0U}}, +{MOVE_3108,{3U,2U,0U}}, +{MOVE_3108,{4U,2U,0U}}, +{MOVE_3108,{5U,2U,0U}}, +{MOVE_3108,{6U,2U,0U}}, +{MOVE_3108,{7U,2U,0U}}, +{MOVE_3110,{0U,2U,0U}}, +{MOVE_3110,{1U,2U,0U}}, +{MOVE_3110,{2U,2U,0U}}, +{MOVE_3110,{3U,2U,0U}}, +{MOVE_3110,{4U,2U,0U}}, +{MOVE_3110,{5U,2U,0U}}, +{MOVE_3110,{6U,2U,0U}}, +{MOVE_3110,{7U,2U,0U}}, +{MOVE_3118,{0U,2U,0U}}, +{MOVE_3118,{1U,2U,0U}}, +{MOVE_3118,{2U,2U,0U}}, +{MOVE_3118,{3U,2U,0U}}, +{MOVE_3118,{4U,2U,0U}}, +{MOVE_3118,{5U,2U,0U}}, +{MOVE_3118,{6U,2U,0U}}, +{MOVE_3118,{7U,2U,0U}}, +{MOVE_3120,{0U,2U,0U}}, +{MOVE_3120,{1U,2U,0U}}, +{MOVE_3120,{2U,2U,0U}}, +{MOVE_3120,{3U,2U,0U}}, +{MOVE_3120,{4U,2U,0U}}, +{MOVE_3120,{5U,2U,0U}}, +{MOVE_3120,{6U,2U,0U}}, +{MOVE_3120,{7U,2U,0U}}, +{MOVE_3128,{0U,2U,0U}}, +{MOVE_3128,{1U,2U,0U}}, +{MOVE_3128,{2U,2U,0U}}, +{MOVE_3128,{3U,2U,0U}}, +{MOVE_3128,{4U,2U,0U}}, +{MOVE_3128,{5U,2U,0U}}, +{MOVE_3128,{6U,2U,0U}}, +{MOVE_3128,{7U,2U,0U}}, +{MOVE_3130,{0U,2U,0U}}, +{MOVE_3130,{1U,2U,0U}}, +{MOVE_3130,{2U,2U,0U}}, +{MOVE_3130,{3U,2U,0U}}, +{MOVE_3130,{4U,2U,0U}}, +{MOVE_3130,{5U,2U,0U}}, +{MOVE_3130,{6U,2U,0U}}, +{MOVE_3130,{7U,2U,0U}}, +{MOVE_3138,{0U,2U,0U}}, +{MOVE_3139,{0U,2U,0U}}, +{MOVE_313A,{0U,2U,0U}}, +{MOVE_313B,{0U,2U,0U}}, +{MOVE_313C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3140,{0U,2U,0U}}, +{MOVE_3140,{1U,2U,0U}}, +{MOVE_3140,{2U,2U,0U}}, +{MOVE_3140,{3U,2U,0U}}, +{MOVE_3140,{4U,2U,0U}}, +{MOVE_3140,{5U,2U,0U}}, +{MOVE_3140,{6U,2U,0U}}, +{MOVE_3140,{7U,2U,0U}}, +{MOVE_3148,{0U,2U,0U}}, +{MOVE_3148,{1U,2U,0U}}, +{MOVE_3148,{2U,2U,0U}}, +{MOVE_3148,{3U,2U,0U}}, +{MOVE_3148,{4U,2U,0U}}, +{MOVE_3148,{5U,2U,0U}}, +{MOVE_3148,{6U,2U,0U}}, +{MOVE_3148,{7U,2U,0U}}, +{MOVE_3150,{0U,2U,0U}}, +{MOVE_3150,{1U,2U,0U}}, +{MOVE_3150,{2U,2U,0U}}, +{MOVE_3150,{3U,2U,0U}}, +{MOVE_3150,{4U,2U,0U}}, +{MOVE_3150,{5U,2U,0U}}, +{MOVE_3150,{6U,2U,0U}}, +{MOVE_3150,{7U,2U,0U}}, +{MOVE_3158,{0U,2U,0U}}, +{MOVE_3158,{1U,2U,0U}}, +{MOVE_3158,{2U,2U,0U}}, +{MOVE_3158,{3U,2U,0U}}, +{MOVE_3158,{4U,2U,0U}}, +{MOVE_3158,{5U,2U,0U}}, +{MOVE_3158,{6U,2U,0U}}, +{MOVE_3158,{7U,2U,0U}}, +{MOVE_3160,{0U,2U,0U}}, +{MOVE_3160,{1U,2U,0U}}, +{MOVE_3160,{2U,2U,0U}}, +{MOVE_3160,{3U,2U,0U}}, +{MOVE_3160,{4U,2U,0U}}, +{MOVE_3160,{5U,2U,0U}}, +{MOVE_3160,{6U,2U,0U}}, +{MOVE_3160,{7U,2U,0U}}, +{MOVE_3168,{0U,2U,0U}}, +{MOVE_3168,{1U,2U,0U}}, +{MOVE_3168,{2U,2U,0U}}, +{MOVE_3168,{3U,2U,0U}}, +{MOVE_3168,{4U,2U,0U}}, +{MOVE_3168,{5U,2U,0U}}, +{MOVE_3168,{6U,2U,0U}}, +{MOVE_3168,{7U,2U,0U}}, +{MOVE_3170,{0U,2U,0U}}, +{MOVE_3170,{1U,2U,0U}}, +{MOVE_3170,{2U,2U,0U}}, +{MOVE_3170,{3U,2U,0U}}, +{MOVE_3170,{4U,2U,0U}}, +{MOVE_3170,{5U,2U,0U}}, +{MOVE_3170,{6U,2U,0U}}, +{MOVE_3170,{7U,2U,0U}}, +{MOVE_3178,{0U,2U,0U}}, +{MOVE_3179,{0U,2U,0U}}, +{MOVE_317A,{0U,2U,0U}}, +{MOVE_317B,{0U,2U,0U}}, +{MOVE_317C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3180,{0U,2U,0U}}, +{MOVE_3180,{1U,2U,0U}}, +{MOVE_3180,{2U,2U,0U}}, +{MOVE_3180,{3U,2U,0U}}, +{MOVE_3180,{4U,2U,0U}}, +{MOVE_3180,{5U,2U,0U}}, +{MOVE_3180,{6U,2U,0U}}, +{MOVE_3180,{7U,2U,0U}}, +{MOVE_3188,{0U,2U,0U}}, +{MOVE_3188,{1U,2U,0U}}, +{MOVE_3188,{2U,2U,0U}}, +{MOVE_3188,{3U,2U,0U}}, +{MOVE_3188,{4U,2U,0U}}, +{MOVE_3188,{5U,2U,0U}}, +{MOVE_3188,{6U,2U,0U}}, +{MOVE_3188,{7U,2U,0U}}, +{MOVE_3190,{0U,2U,0U}}, +{MOVE_3190,{1U,2U,0U}}, +{MOVE_3190,{2U,2U,0U}}, +{MOVE_3190,{3U,2U,0U}}, +{MOVE_3190,{4U,2U,0U}}, +{MOVE_3190,{5U,2U,0U}}, +{MOVE_3190,{6U,2U,0U}}, +{MOVE_3190,{7U,2U,0U}}, +{MOVE_3198,{0U,2U,0U}}, +{MOVE_3198,{1U,2U,0U}}, +{MOVE_3198,{2U,2U,0U}}, +{MOVE_3198,{3U,2U,0U}}, +{MOVE_3198,{4U,2U,0U}}, +{MOVE_3198,{5U,2U,0U}}, +{MOVE_3198,{6U,2U,0U}}, +{MOVE_3198,{7U,2U,0U}}, +{MOVE_31A0,{0U,2U,0U}}, +{MOVE_31A0,{1U,2U,0U}}, +{MOVE_31A0,{2U,2U,0U}}, +{MOVE_31A0,{3U,2U,0U}}, +{MOVE_31A0,{4U,2U,0U}}, +{MOVE_31A0,{5U,2U,0U}}, +{MOVE_31A0,{6U,2U,0U}}, +{MOVE_31A0,{7U,2U,0U}}, +{MOVE_31A8,{0U,2U,0U}}, +{MOVE_31A8,{1U,2U,0U}}, +{MOVE_31A8,{2U,2U,0U}}, +{MOVE_31A8,{3U,2U,0U}}, +{MOVE_31A8,{4U,2U,0U}}, +{MOVE_31A8,{5U,2U,0U}}, +{MOVE_31A8,{6U,2U,0U}}, +{MOVE_31A8,{7U,2U,0U}}, +{MOVE_31B0,{0U,2U,0U}}, +{MOVE_31B0,{1U,2U,0U}}, +{MOVE_31B0,{2U,2U,0U}}, +{MOVE_31B0,{3U,2U,0U}}, +{MOVE_31B0,{4U,2U,0U}}, +{MOVE_31B0,{5U,2U,0U}}, +{MOVE_31B0,{6U,2U,0U}}, +{MOVE_31B0,{7U,2U,0U}}, +{MOVE_31B8,{0U,2U,0U}}, +{MOVE_31B9,{0U,2U,0U}}, +{MOVE_31BA,{0U,2U,0U}}, +{MOVE_31BB,{0U,2U,0U}}, +{MOVE_31BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3000,{0U,3U,0U}}, +{MOVE_3000,{1U,3U,0U}}, +{MOVE_3000,{2U,3U,0U}}, +{MOVE_3000,{3U,3U,0U}}, +{MOVE_3000,{4U,3U,0U}}, +{MOVE_3000,{5U,3U,0U}}, +{MOVE_3000,{6U,3U,0U}}, +{MOVE_3000,{7U,3U,0U}}, +{MOVE_3008,{0U,3U,0U}}, +{MOVE_3008,{1U,3U,0U}}, +{MOVE_3008,{2U,3U,0U}}, +{MOVE_3008,{3U,3U,0U}}, +{MOVE_3008,{4U,3U,0U}}, +{MOVE_3008,{5U,3U,0U}}, +{MOVE_3008,{6U,3U,0U}}, +{MOVE_3008,{7U,3U,0U}}, +{MOVE_3010,{0U,3U,0U}}, +{MOVE_3010,{1U,3U,0U}}, +{MOVE_3010,{2U,3U,0U}}, +{MOVE_3010,{3U,3U,0U}}, +{MOVE_3010,{4U,3U,0U}}, +{MOVE_3010,{5U,3U,0U}}, +{MOVE_3010,{6U,3U,0U}}, +{MOVE_3010,{7U,3U,0U}}, +{MOVE_3018,{0U,3U,0U}}, +{MOVE_3018,{1U,3U,0U}}, +{MOVE_3018,{2U,3U,0U}}, +{MOVE_3018,{3U,3U,0U}}, +{MOVE_3018,{4U,3U,0U}}, +{MOVE_3018,{5U,3U,0U}}, +{MOVE_3018,{6U,3U,0U}}, +{MOVE_3018,{7U,3U,0U}}, +{MOVE_3020,{0U,3U,0U}}, +{MOVE_3020,{1U,3U,0U}}, +{MOVE_3020,{2U,3U,0U}}, +{MOVE_3020,{3U,3U,0U}}, +{MOVE_3020,{4U,3U,0U}}, +{MOVE_3020,{5U,3U,0U}}, +{MOVE_3020,{6U,3U,0U}}, +{MOVE_3020,{7U,3U,0U}}, +{MOVE_3028,{0U,3U,0U}}, +{MOVE_3028,{1U,3U,0U}}, +{MOVE_3028,{2U,3U,0U}}, +{MOVE_3028,{3U,3U,0U}}, +{MOVE_3028,{4U,3U,0U}}, +{MOVE_3028,{5U,3U,0U}}, +{MOVE_3028,{6U,3U,0U}}, +{MOVE_3028,{7U,3U,0U}}, +{MOVE_3030,{0U,3U,0U}}, +{MOVE_3030,{1U,3U,0U}}, +{MOVE_3030,{2U,3U,0U}}, +{MOVE_3030,{3U,3U,0U}}, +{MOVE_3030,{4U,3U,0U}}, +{MOVE_3030,{5U,3U,0U}}, +{MOVE_3030,{6U,3U,0U}}, +{MOVE_3030,{7U,3U,0U}}, +{MOVE_3038,{0U,3U,0U}}, +{MOVE_3039,{0U,3U,0U}}, +{MOVE_303A,{0U,3U,0U}}, +{MOVE_303B,{0U,3U,0U}}, +{MOVE_303C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_3040,{0U,3U,0U}}, +{MOVEA_3040,{1U,3U,0U}}, +{MOVEA_3040,{2U,3U,0U}}, +{MOVEA_3040,{3U,3U,0U}}, +{MOVEA_3040,{4U,3U,0U}}, +{MOVEA_3040,{5U,3U,0U}}, +{MOVEA_3040,{6U,3U,0U}}, +{MOVEA_3040,{7U,3U,0U}}, +{MOVEA_3048,{0U,3U,0U}}, +{MOVEA_3048,{1U,3U,0U}}, +{MOVEA_3048,{2U,3U,0U}}, +{MOVEA_3048,{3U,3U,0U}}, +{MOVEA_3048,{4U,3U,0U}}, +{MOVEA_3048,{5U,3U,0U}}, +{MOVEA_3048,{6U,3U,0U}}, +{MOVEA_3048,{7U,3U,0U}}, +{MOVEA_3050,{0U,3U,0U}}, +{MOVEA_3050,{1U,3U,0U}}, +{MOVEA_3050,{2U,3U,0U}}, +{MOVEA_3050,{3U,3U,0U}}, +{MOVEA_3050,{4U,3U,0U}}, +{MOVEA_3050,{5U,3U,0U}}, +{MOVEA_3050,{6U,3U,0U}}, +{MOVEA_3050,{7U,3U,0U}}, +{MOVEA_3058,{0U,3U,0U}}, +{MOVEA_3058,{1U,3U,0U}}, +{MOVEA_3058,{2U,3U,0U}}, +{MOVEA_3058,{3U,3U,0U}}, +{MOVEA_3058,{4U,3U,0U}}, +{MOVEA_3058,{5U,3U,0U}}, +{MOVEA_3058,{6U,3U,0U}}, +{MOVEA_3058,{7U,3U,0U}}, +{MOVEA_3060,{0U,3U,0U}}, +{MOVEA_3060,{1U,3U,0U}}, +{MOVEA_3060,{2U,3U,0U}}, +{MOVEA_3060,{3U,3U,0U}}, +{MOVEA_3060,{4U,3U,0U}}, +{MOVEA_3060,{5U,3U,0U}}, +{MOVEA_3060,{6U,3U,0U}}, +{MOVEA_3060,{7U,3U,0U}}, +{MOVEA_3068,{0U,3U,0U}}, +{MOVEA_3068,{1U,3U,0U}}, +{MOVEA_3068,{2U,3U,0U}}, +{MOVEA_3068,{3U,3U,0U}}, +{MOVEA_3068,{4U,3U,0U}}, +{MOVEA_3068,{5U,3U,0U}}, +{MOVEA_3068,{6U,3U,0U}}, +{MOVEA_3068,{7U,3U,0U}}, +{MOVEA_3070,{0U,3U,0U}}, +{MOVEA_3070,{1U,3U,0U}}, +{MOVEA_3070,{2U,3U,0U}}, +{MOVEA_3070,{3U,3U,0U}}, +{MOVEA_3070,{4U,3U,0U}}, +{MOVEA_3070,{5U,3U,0U}}, +{MOVEA_3070,{6U,3U,0U}}, +{MOVEA_3070,{7U,3U,0U}}, +{MOVEA_3078,{0U,3U,0U}}, +{MOVEA_3079,{0U,3U,0U}}, +{MOVEA_307A,{0U,3U,0U}}, +{MOVEA_307B,{0U,3U,0U}}, +{MOVEA_307C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3080,{0U,3U,0U}}, +{MOVE_3080,{1U,3U,0U}}, +{MOVE_3080,{2U,3U,0U}}, +{MOVE_3080,{3U,3U,0U}}, +{MOVE_3080,{4U,3U,0U}}, +{MOVE_3080,{5U,3U,0U}}, +{MOVE_3080,{6U,3U,0U}}, +{MOVE_3080,{7U,3U,0U}}, +{MOVE_3088,{0U,3U,0U}}, +{MOVE_3088,{1U,3U,0U}}, +{MOVE_3088,{2U,3U,0U}}, +{MOVE_3088,{3U,3U,0U}}, +{MOVE_3088,{4U,3U,0U}}, +{MOVE_3088,{5U,3U,0U}}, +{MOVE_3088,{6U,3U,0U}}, +{MOVE_3088,{7U,3U,0U}}, +{MOVE_3090,{0U,3U,0U}}, +{MOVE_3090,{1U,3U,0U}}, +{MOVE_3090,{2U,3U,0U}}, +{MOVE_3090,{3U,3U,0U}}, +{MOVE_3090,{4U,3U,0U}}, +{MOVE_3090,{5U,3U,0U}}, +{MOVE_3090,{6U,3U,0U}}, +{MOVE_3090,{7U,3U,0U}}, +{MOVE_3098,{0U,3U,0U}}, +{MOVE_3098,{1U,3U,0U}}, +{MOVE_3098,{2U,3U,0U}}, +{MOVE_3098,{3U,3U,0U}}, +{MOVE_3098,{4U,3U,0U}}, +{MOVE_3098,{5U,3U,0U}}, +{MOVE_3098,{6U,3U,0U}}, +{MOVE_3098,{7U,3U,0U}}, +{MOVE_30A0,{0U,3U,0U}}, +{MOVE_30A0,{1U,3U,0U}}, +{MOVE_30A0,{2U,3U,0U}}, +{MOVE_30A0,{3U,3U,0U}}, +{MOVE_30A0,{4U,3U,0U}}, +{MOVE_30A0,{5U,3U,0U}}, +{MOVE_30A0,{6U,3U,0U}}, +{MOVE_30A0,{7U,3U,0U}}, +{MOVE_30A8,{0U,3U,0U}}, +{MOVE_30A8,{1U,3U,0U}}, +{MOVE_30A8,{2U,3U,0U}}, +{MOVE_30A8,{3U,3U,0U}}, +{MOVE_30A8,{4U,3U,0U}}, +{MOVE_30A8,{5U,3U,0U}}, +{MOVE_30A8,{6U,3U,0U}}, +{MOVE_30A8,{7U,3U,0U}}, +{MOVE_30B0,{0U,3U,0U}}, +{MOVE_30B0,{1U,3U,0U}}, +{MOVE_30B0,{2U,3U,0U}}, +{MOVE_30B0,{3U,3U,0U}}, +{MOVE_30B0,{4U,3U,0U}}, +{MOVE_30B0,{5U,3U,0U}}, +{MOVE_30B0,{6U,3U,0U}}, +{MOVE_30B0,{7U,3U,0U}}, +{MOVE_30B8,{0U,3U,0U}}, +{MOVE_30B9,{0U,3U,0U}}, +{MOVE_30BA,{0U,3U,0U}}, +{MOVE_30BB,{0U,3U,0U}}, +{MOVE_30BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_30C0,{0U,3U,0U}}, +{MOVE_30C0,{1U,3U,0U}}, +{MOVE_30C0,{2U,3U,0U}}, +{MOVE_30C0,{3U,3U,0U}}, +{MOVE_30C0,{4U,3U,0U}}, +{MOVE_30C0,{5U,3U,0U}}, +{MOVE_30C0,{6U,3U,0U}}, +{MOVE_30C0,{7U,3U,0U}}, +{MOVE_30C8,{0U,3U,0U}}, +{MOVE_30C8,{1U,3U,0U}}, +{MOVE_30C8,{2U,3U,0U}}, +{MOVE_30C8,{3U,3U,0U}}, +{MOVE_30C8,{4U,3U,0U}}, +{MOVE_30C8,{5U,3U,0U}}, +{MOVE_30C8,{6U,3U,0U}}, +{MOVE_30C8,{7U,3U,0U}}, +{MOVE_30D0,{0U,3U,0U}}, +{MOVE_30D0,{1U,3U,0U}}, +{MOVE_30D0,{2U,3U,0U}}, +{MOVE_30D0,{3U,3U,0U}}, +{MOVE_30D0,{4U,3U,0U}}, +{MOVE_30D0,{5U,3U,0U}}, +{MOVE_30D0,{6U,3U,0U}}, +{MOVE_30D0,{7U,3U,0U}}, +{MOVE_30D8,{0U,3U,0U}}, +{MOVE_30D8,{1U,3U,0U}}, +{MOVE_30D8,{2U,3U,0U}}, +{MOVE_30D8,{3U,3U,0U}}, +{MOVE_30D8,{4U,3U,0U}}, +{MOVE_30D8,{5U,3U,0U}}, +{MOVE_30D8,{6U,3U,0U}}, +{MOVE_30D8,{7U,3U,0U}}, +{MOVE_30E0,{0U,3U,0U}}, +{MOVE_30E0,{1U,3U,0U}}, +{MOVE_30E0,{2U,3U,0U}}, +{MOVE_30E0,{3U,3U,0U}}, +{MOVE_30E0,{4U,3U,0U}}, +{MOVE_30E0,{5U,3U,0U}}, +{MOVE_30E0,{6U,3U,0U}}, +{MOVE_30E0,{7U,3U,0U}}, +{MOVE_30E8,{0U,3U,0U}}, +{MOVE_30E8,{1U,3U,0U}}, +{MOVE_30E8,{2U,3U,0U}}, +{MOVE_30E8,{3U,3U,0U}}, +{MOVE_30E8,{4U,3U,0U}}, +{MOVE_30E8,{5U,3U,0U}}, +{MOVE_30E8,{6U,3U,0U}}, +{MOVE_30E8,{7U,3U,0U}}, +{MOVE_30F0,{0U,3U,0U}}, +{MOVE_30F0,{1U,3U,0U}}, +{MOVE_30F0,{2U,3U,0U}}, +{MOVE_30F0,{3U,3U,0U}}, +{MOVE_30F0,{4U,3U,0U}}, +{MOVE_30F0,{5U,3U,0U}}, +{MOVE_30F0,{6U,3U,0U}}, +{MOVE_30F0,{7U,3U,0U}}, +{MOVE_30F8,{0U,3U,0U}}, +{MOVE_30F9,{0U,3U,0U}}, +{MOVE_30FA,{0U,3U,0U}}, +{MOVE_30FB,{0U,3U,0U}}, +{MOVE_30FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3100,{0U,3U,0U}}, +{MOVE_3100,{1U,3U,0U}}, +{MOVE_3100,{2U,3U,0U}}, +{MOVE_3100,{3U,3U,0U}}, +{MOVE_3100,{4U,3U,0U}}, +{MOVE_3100,{5U,3U,0U}}, +{MOVE_3100,{6U,3U,0U}}, +{MOVE_3100,{7U,3U,0U}}, +{MOVE_3108,{0U,3U,0U}}, +{MOVE_3108,{1U,3U,0U}}, +{MOVE_3108,{2U,3U,0U}}, +{MOVE_3108,{3U,3U,0U}}, +{MOVE_3108,{4U,3U,0U}}, +{MOVE_3108,{5U,3U,0U}}, +{MOVE_3108,{6U,3U,0U}}, +{MOVE_3108,{7U,3U,0U}}, +{MOVE_3110,{0U,3U,0U}}, +{MOVE_3110,{1U,3U,0U}}, +{MOVE_3110,{2U,3U,0U}}, +{MOVE_3110,{3U,3U,0U}}, +{MOVE_3110,{4U,3U,0U}}, +{MOVE_3110,{5U,3U,0U}}, +{MOVE_3110,{6U,3U,0U}}, +{MOVE_3110,{7U,3U,0U}}, +{MOVE_3118,{0U,3U,0U}}, +{MOVE_3118,{1U,3U,0U}}, +{MOVE_3118,{2U,3U,0U}}, +{MOVE_3118,{3U,3U,0U}}, +{MOVE_3118,{4U,3U,0U}}, +{MOVE_3118,{5U,3U,0U}}, +{MOVE_3118,{6U,3U,0U}}, +{MOVE_3118,{7U,3U,0U}}, +{MOVE_3120,{0U,3U,0U}}, +{MOVE_3120,{1U,3U,0U}}, +{MOVE_3120,{2U,3U,0U}}, +{MOVE_3120,{3U,3U,0U}}, +{MOVE_3120,{4U,3U,0U}}, +{MOVE_3120,{5U,3U,0U}}, +{MOVE_3120,{6U,3U,0U}}, +{MOVE_3120,{7U,3U,0U}}, +{MOVE_3128,{0U,3U,0U}}, +{MOVE_3128,{1U,3U,0U}}, +{MOVE_3128,{2U,3U,0U}}, +{MOVE_3128,{3U,3U,0U}}, +{MOVE_3128,{4U,3U,0U}}, +{MOVE_3128,{5U,3U,0U}}, +{MOVE_3128,{6U,3U,0U}}, +{MOVE_3128,{7U,3U,0U}}, +{MOVE_3130,{0U,3U,0U}}, +{MOVE_3130,{1U,3U,0U}}, +{MOVE_3130,{2U,3U,0U}}, +{MOVE_3130,{3U,3U,0U}}, +{MOVE_3130,{4U,3U,0U}}, +{MOVE_3130,{5U,3U,0U}}, +{MOVE_3130,{6U,3U,0U}}, +{MOVE_3130,{7U,3U,0U}}, +{MOVE_3138,{0U,3U,0U}}, +{MOVE_3139,{0U,3U,0U}}, +{MOVE_313A,{0U,3U,0U}}, +{MOVE_313B,{0U,3U,0U}}, +{MOVE_313C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3140,{0U,3U,0U}}, +{MOVE_3140,{1U,3U,0U}}, +{MOVE_3140,{2U,3U,0U}}, +{MOVE_3140,{3U,3U,0U}}, +{MOVE_3140,{4U,3U,0U}}, +{MOVE_3140,{5U,3U,0U}}, +{MOVE_3140,{6U,3U,0U}}, +{MOVE_3140,{7U,3U,0U}}, +{MOVE_3148,{0U,3U,0U}}, +{MOVE_3148,{1U,3U,0U}}, +{MOVE_3148,{2U,3U,0U}}, +{MOVE_3148,{3U,3U,0U}}, +{MOVE_3148,{4U,3U,0U}}, +{MOVE_3148,{5U,3U,0U}}, +{MOVE_3148,{6U,3U,0U}}, +{MOVE_3148,{7U,3U,0U}}, +{MOVE_3150,{0U,3U,0U}}, +{MOVE_3150,{1U,3U,0U}}, +{MOVE_3150,{2U,3U,0U}}, +{MOVE_3150,{3U,3U,0U}}, +{MOVE_3150,{4U,3U,0U}}, +{MOVE_3150,{5U,3U,0U}}, +{MOVE_3150,{6U,3U,0U}}, +{MOVE_3150,{7U,3U,0U}}, +{MOVE_3158,{0U,3U,0U}}, +{MOVE_3158,{1U,3U,0U}}, +{MOVE_3158,{2U,3U,0U}}, +{MOVE_3158,{3U,3U,0U}}, +{MOVE_3158,{4U,3U,0U}}, +{MOVE_3158,{5U,3U,0U}}, +{MOVE_3158,{6U,3U,0U}}, +{MOVE_3158,{7U,3U,0U}}, +{MOVE_3160,{0U,3U,0U}}, +{MOVE_3160,{1U,3U,0U}}, +{MOVE_3160,{2U,3U,0U}}, +{MOVE_3160,{3U,3U,0U}}, +{MOVE_3160,{4U,3U,0U}}, +{MOVE_3160,{5U,3U,0U}}, +{MOVE_3160,{6U,3U,0U}}, +{MOVE_3160,{7U,3U,0U}}, +{MOVE_3168,{0U,3U,0U}}, +{MOVE_3168,{1U,3U,0U}}, +{MOVE_3168,{2U,3U,0U}}, +{MOVE_3168,{3U,3U,0U}}, +{MOVE_3168,{4U,3U,0U}}, +{MOVE_3168,{5U,3U,0U}}, +{MOVE_3168,{6U,3U,0U}}, +{MOVE_3168,{7U,3U,0U}}, +{MOVE_3170,{0U,3U,0U}}, +{MOVE_3170,{1U,3U,0U}}, +{MOVE_3170,{2U,3U,0U}}, +{MOVE_3170,{3U,3U,0U}}, +{MOVE_3170,{4U,3U,0U}}, +{MOVE_3170,{5U,3U,0U}}, +{MOVE_3170,{6U,3U,0U}}, +{MOVE_3170,{7U,3U,0U}}, +{MOVE_3178,{0U,3U,0U}}, +{MOVE_3179,{0U,3U,0U}}, +{MOVE_317A,{0U,3U,0U}}, +{MOVE_317B,{0U,3U,0U}}, +{MOVE_317C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3180,{0U,3U,0U}}, +{MOVE_3180,{1U,3U,0U}}, +{MOVE_3180,{2U,3U,0U}}, +{MOVE_3180,{3U,3U,0U}}, +{MOVE_3180,{4U,3U,0U}}, +{MOVE_3180,{5U,3U,0U}}, +{MOVE_3180,{6U,3U,0U}}, +{MOVE_3180,{7U,3U,0U}}, +{MOVE_3188,{0U,3U,0U}}, +{MOVE_3188,{1U,3U,0U}}, +{MOVE_3188,{2U,3U,0U}}, +{MOVE_3188,{3U,3U,0U}}, +{MOVE_3188,{4U,3U,0U}}, +{MOVE_3188,{5U,3U,0U}}, +{MOVE_3188,{6U,3U,0U}}, +{MOVE_3188,{7U,3U,0U}}, +{MOVE_3190,{0U,3U,0U}}, +{MOVE_3190,{1U,3U,0U}}, +{MOVE_3190,{2U,3U,0U}}, +{MOVE_3190,{3U,3U,0U}}, +{MOVE_3190,{4U,3U,0U}}, +{MOVE_3190,{5U,3U,0U}}, +{MOVE_3190,{6U,3U,0U}}, +{MOVE_3190,{7U,3U,0U}}, +{MOVE_3198,{0U,3U,0U}}, +{MOVE_3198,{1U,3U,0U}}, +{MOVE_3198,{2U,3U,0U}}, +{MOVE_3198,{3U,3U,0U}}, +{MOVE_3198,{4U,3U,0U}}, +{MOVE_3198,{5U,3U,0U}}, +{MOVE_3198,{6U,3U,0U}}, +{MOVE_3198,{7U,3U,0U}}, +{MOVE_31A0,{0U,3U,0U}}, +{MOVE_31A0,{1U,3U,0U}}, +{MOVE_31A0,{2U,3U,0U}}, +{MOVE_31A0,{3U,3U,0U}}, +{MOVE_31A0,{4U,3U,0U}}, +{MOVE_31A0,{5U,3U,0U}}, +{MOVE_31A0,{6U,3U,0U}}, +{MOVE_31A0,{7U,3U,0U}}, +{MOVE_31A8,{0U,3U,0U}}, +{MOVE_31A8,{1U,3U,0U}}, +{MOVE_31A8,{2U,3U,0U}}, +{MOVE_31A8,{3U,3U,0U}}, +{MOVE_31A8,{4U,3U,0U}}, +{MOVE_31A8,{5U,3U,0U}}, +{MOVE_31A8,{6U,3U,0U}}, +{MOVE_31A8,{7U,3U,0U}}, +{MOVE_31B0,{0U,3U,0U}}, +{MOVE_31B0,{1U,3U,0U}}, +{MOVE_31B0,{2U,3U,0U}}, +{MOVE_31B0,{3U,3U,0U}}, +{MOVE_31B0,{4U,3U,0U}}, +{MOVE_31B0,{5U,3U,0U}}, +{MOVE_31B0,{6U,3U,0U}}, +{MOVE_31B0,{7U,3U,0U}}, +{MOVE_31B8,{0U,3U,0U}}, +{MOVE_31B9,{0U,3U,0U}}, +{MOVE_31BA,{0U,3U,0U}}, +{MOVE_31BB,{0U,3U,0U}}, +{MOVE_31BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3000,{0U,4U,0U}}, +{MOVE_3000,{1U,4U,0U}}, +{MOVE_3000,{2U,4U,0U}}, +{MOVE_3000,{3U,4U,0U}}, +{MOVE_3000,{4U,4U,0U}}, +{MOVE_3000,{5U,4U,0U}}, +{MOVE_3000,{6U,4U,0U}}, +{MOVE_3000,{7U,4U,0U}}, +{MOVE_3008,{0U,4U,0U}}, +{MOVE_3008,{1U,4U,0U}}, +{MOVE_3008,{2U,4U,0U}}, +{MOVE_3008,{3U,4U,0U}}, +{MOVE_3008,{4U,4U,0U}}, +{MOVE_3008,{5U,4U,0U}}, +{MOVE_3008,{6U,4U,0U}}, +{MOVE_3008,{7U,4U,0U}}, +{MOVE_3010,{0U,4U,0U}}, +{MOVE_3010,{1U,4U,0U}}, +{MOVE_3010,{2U,4U,0U}}, +{MOVE_3010,{3U,4U,0U}}, +{MOVE_3010,{4U,4U,0U}}, +{MOVE_3010,{5U,4U,0U}}, +{MOVE_3010,{6U,4U,0U}}, +{MOVE_3010,{7U,4U,0U}}, +{MOVE_3018,{0U,4U,0U}}, +{MOVE_3018,{1U,4U,0U}}, +{MOVE_3018,{2U,4U,0U}}, +{MOVE_3018,{3U,4U,0U}}, +{MOVE_3018,{4U,4U,0U}}, +{MOVE_3018,{5U,4U,0U}}, +{MOVE_3018,{6U,4U,0U}}, +{MOVE_3018,{7U,4U,0U}}, +{MOVE_3020,{0U,4U,0U}}, +{MOVE_3020,{1U,4U,0U}}, +{MOVE_3020,{2U,4U,0U}}, +{MOVE_3020,{3U,4U,0U}}, +{MOVE_3020,{4U,4U,0U}}, +{MOVE_3020,{5U,4U,0U}}, +{MOVE_3020,{6U,4U,0U}}, +{MOVE_3020,{7U,4U,0U}}, +{MOVE_3028,{0U,4U,0U}}, +{MOVE_3028,{1U,4U,0U}}, +{MOVE_3028,{2U,4U,0U}}, +{MOVE_3028,{3U,4U,0U}}, +{MOVE_3028,{4U,4U,0U}}, +{MOVE_3028,{5U,4U,0U}}, +{MOVE_3028,{6U,4U,0U}}, +{MOVE_3028,{7U,4U,0U}}, +{MOVE_3030,{0U,4U,0U}}, +{MOVE_3030,{1U,4U,0U}}, +{MOVE_3030,{2U,4U,0U}}, +{MOVE_3030,{3U,4U,0U}}, +{MOVE_3030,{4U,4U,0U}}, +{MOVE_3030,{5U,4U,0U}}, +{MOVE_3030,{6U,4U,0U}}, +{MOVE_3030,{7U,4U,0U}}, +{MOVE_3038,{0U,4U,0U}}, +{MOVE_3039,{0U,4U,0U}}, +{MOVE_303A,{0U,4U,0U}}, +{MOVE_303B,{0U,4U,0U}}, +{MOVE_303C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_3040,{0U,4U,0U}}, +{MOVEA_3040,{1U,4U,0U}}, +{MOVEA_3040,{2U,4U,0U}}, +{MOVEA_3040,{3U,4U,0U}}, +{MOVEA_3040,{4U,4U,0U}}, +{MOVEA_3040,{5U,4U,0U}}, +{MOVEA_3040,{6U,4U,0U}}, +{MOVEA_3040,{7U,4U,0U}}, +{MOVEA_3048,{0U,4U,0U}}, +{MOVEA_3048,{1U,4U,0U}}, +{MOVEA_3048,{2U,4U,0U}}, +{MOVEA_3048,{3U,4U,0U}}, +{MOVEA_3048,{4U,4U,0U}}, +{MOVEA_3048,{5U,4U,0U}}, +{MOVEA_3048,{6U,4U,0U}}, +{MOVEA_3048,{7U,4U,0U}}, +{MOVEA_3050,{0U,4U,0U}}, +{MOVEA_3050,{1U,4U,0U}}, +{MOVEA_3050,{2U,4U,0U}}, +{MOVEA_3050,{3U,4U,0U}}, +{MOVEA_3050,{4U,4U,0U}}, +{MOVEA_3050,{5U,4U,0U}}, +{MOVEA_3050,{6U,4U,0U}}, +{MOVEA_3050,{7U,4U,0U}}, +{MOVEA_3058,{0U,4U,0U}}, +{MOVEA_3058,{1U,4U,0U}}, +{MOVEA_3058,{2U,4U,0U}}, +{MOVEA_3058,{3U,4U,0U}}, +{MOVEA_3058,{4U,4U,0U}}, +{MOVEA_3058,{5U,4U,0U}}, +{MOVEA_3058,{6U,4U,0U}}, +{MOVEA_3058,{7U,4U,0U}}, +{MOVEA_3060,{0U,4U,0U}}, +{MOVEA_3060,{1U,4U,0U}}, +{MOVEA_3060,{2U,4U,0U}}, +{MOVEA_3060,{3U,4U,0U}}, +{MOVEA_3060,{4U,4U,0U}}, +{MOVEA_3060,{5U,4U,0U}}, +{MOVEA_3060,{6U,4U,0U}}, +{MOVEA_3060,{7U,4U,0U}}, +{MOVEA_3068,{0U,4U,0U}}, +{MOVEA_3068,{1U,4U,0U}}, +{MOVEA_3068,{2U,4U,0U}}, +{MOVEA_3068,{3U,4U,0U}}, +{MOVEA_3068,{4U,4U,0U}}, +{MOVEA_3068,{5U,4U,0U}}, +{MOVEA_3068,{6U,4U,0U}}, +{MOVEA_3068,{7U,4U,0U}}, +{MOVEA_3070,{0U,4U,0U}}, +{MOVEA_3070,{1U,4U,0U}}, +{MOVEA_3070,{2U,4U,0U}}, +{MOVEA_3070,{3U,4U,0U}}, +{MOVEA_3070,{4U,4U,0U}}, +{MOVEA_3070,{5U,4U,0U}}, +{MOVEA_3070,{6U,4U,0U}}, +{MOVEA_3070,{7U,4U,0U}}, +{MOVEA_3078,{0U,4U,0U}}, +{MOVEA_3079,{0U,4U,0U}}, +{MOVEA_307A,{0U,4U,0U}}, +{MOVEA_307B,{0U,4U,0U}}, +{MOVEA_307C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3080,{0U,4U,0U}}, +{MOVE_3080,{1U,4U,0U}}, +{MOVE_3080,{2U,4U,0U}}, +{MOVE_3080,{3U,4U,0U}}, +{MOVE_3080,{4U,4U,0U}}, +{MOVE_3080,{5U,4U,0U}}, +{MOVE_3080,{6U,4U,0U}}, +{MOVE_3080,{7U,4U,0U}}, +{MOVE_3088,{0U,4U,0U}}, +{MOVE_3088,{1U,4U,0U}}, +{MOVE_3088,{2U,4U,0U}}, +{MOVE_3088,{3U,4U,0U}}, +{MOVE_3088,{4U,4U,0U}}, +{MOVE_3088,{5U,4U,0U}}, +{MOVE_3088,{6U,4U,0U}}, +{MOVE_3088,{7U,4U,0U}}, +{MOVE_3090,{0U,4U,0U}}, +{MOVE_3090,{1U,4U,0U}}, +{MOVE_3090,{2U,4U,0U}}, +{MOVE_3090,{3U,4U,0U}}, +{MOVE_3090,{4U,4U,0U}}, +{MOVE_3090,{5U,4U,0U}}, +{MOVE_3090,{6U,4U,0U}}, +{MOVE_3090,{7U,4U,0U}}, +{MOVE_3098,{0U,4U,0U}}, +{MOVE_3098,{1U,4U,0U}}, +{MOVE_3098,{2U,4U,0U}}, +{MOVE_3098,{3U,4U,0U}}, +{MOVE_3098,{4U,4U,0U}}, +{MOVE_3098,{5U,4U,0U}}, +{MOVE_3098,{6U,4U,0U}}, +{MOVE_3098,{7U,4U,0U}}, +{MOVE_30A0,{0U,4U,0U}}, +{MOVE_30A0,{1U,4U,0U}}, +{MOVE_30A0,{2U,4U,0U}}, +{MOVE_30A0,{3U,4U,0U}}, +{MOVE_30A0,{4U,4U,0U}}, +{MOVE_30A0,{5U,4U,0U}}, +{MOVE_30A0,{6U,4U,0U}}, +{MOVE_30A0,{7U,4U,0U}}, +{MOVE_30A8,{0U,4U,0U}}, +{MOVE_30A8,{1U,4U,0U}}, +{MOVE_30A8,{2U,4U,0U}}, +{MOVE_30A8,{3U,4U,0U}}, +{MOVE_30A8,{4U,4U,0U}}, +{MOVE_30A8,{5U,4U,0U}}, +{MOVE_30A8,{6U,4U,0U}}, +{MOVE_30A8,{7U,4U,0U}}, +{MOVE_30B0,{0U,4U,0U}}, +{MOVE_30B0,{1U,4U,0U}}, +{MOVE_30B0,{2U,4U,0U}}, +{MOVE_30B0,{3U,4U,0U}}, +{MOVE_30B0,{4U,4U,0U}}, +{MOVE_30B0,{5U,4U,0U}}, +{MOVE_30B0,{6U,4U,0U}}, +{MOVE_30B0,{7U,4U,0U}}, +{MOVE_30B8,{0U,4U,0U}}, +{MOVE_30B9,{0U,4U,0U}}, +{MOVE_30BA,{0U,4U,0U}}, +{MOVE_30BB,{0U,4U,0U}}, +{MOVE_30BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_30C0,{0U,4U,0U}}, +{MOVE_30C0,{1U,4U,0U}}, +{MOVE_30C0,{2U,4U,0U}}, +{MOVE_30C0,{3U,4U,0U}}, +{MOVE_30C0,{4U,4U,0U}}, +{MOVE_30C0,{5U,4U,0U}}, +{MOVE_30C0,{6U,4U,0U}}, +{MOVE_30C0,{7U,4U,0U}}, +{MOVE_30C8,{0U,4U,0U}}, +{MOVE_30C8,{1U,4U,0U}}, +{MOVE_30C8,{2U,4U,0U}}, +{MOVE_30C8,{3U,4U,0U}}, +{MOVE_30C8,{4U,4U,0U}}, +{MOVE_30C8,{5U,4U,0U}}, +{MOVE_30C8,{6U,4U,0U}}, +{MOVE_30C8,{7U,4U,0U}}, +{MOVE_30D0,{0U,4U,0U}}, +{MOVE_30D0,{1U,4U,0U}}, +{MOVE_30D0,{2U,4U,0U}}, +{MOVE_30D0,{3U,4U,0U}}, +{MOVE_30D0,{4U,4U,0U}}, +{MOVE_30D0,{5U,4U,0U}}, +{MOVE_30D0,{6U,4U,0U}}, +{MOVE_30D0,{7U,4U,0U}}, +{MOVE_30D8,{0U,4U,0U}}, +{MOVE_30D8,{1U,4U,0U}}, +{MOVE_30D8,{2U,4U,0U}}, +{MOVE_30D8,{3U,4U,0U}}, +{MOVE_30D8,{4U,4U,0U}}, +{MOVE_30D8,{5U,4U,0U}}, +{MOVE_30D8,{6U,4U,0U}}, +{MOVE_30D8,{7U,4U,0U}}, +{MOVE_30E0,{0U,4U,0U}}, +{MOVE_30E0,{1U,4U,0U}}, +{MOVE_30E0,{2U,4U,0U}}, +{MOVE_30E0,{3U,4U,0U}}, +{MOVE_30E0,{4U,4U,0U}}, +{MOVE_30E0,{5U,4U,0U}}, +{MOVE_30E0,{6U,4U,0U}}, +{MOVE_30E0,{7U,4U,0U}}, +{MOVE_30E8,{0U,4U,0U}}, +{MOVE_30E8,{1U,4U,0U}}, +{MOVE_30E8,{2U,4U,0U}}, +{MOVE_30E8,{3U,4U,0U}}, +{MOVE_30E8,{4U,4U,0U}}, +{MOVE_30E8,{5U,4U,0U}}, +{MOVE_30E8,{6U,4U,0U}}, +{MOVE_30E8,{7U,4U,0U}}, +{MOVE_30F0,{0U,4U,0U}}, +{MOVE_30F0,{1U,4U,0U}}, +{MOVE_30F0,{2U,4U,0U}}, +{MOVE_30F0,{3U,4U,0U}}, +{MOVE_30F0,{4U,4U,0U}}, +{MOVE_30F0,{5U,4U,0U}}, +{MOVE_30F0,{6U,4U,0U}}, +{MOVE_30F0,{7U,4U,0U}}, +{MOVE_30F8,{0U,4U,0U}}, +{MOVE_30F9,{0U,4U,0U}}, +{MOVE_30FA,{0U,4U,0U}}, +{MOVE_30FB,{0U,4U,0U}}, +{MOVE_30FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3100,{0U,4U,0U}}, +{MOVE_3100,{1U,4U,0U}}, +{MOVE_3100,{2U,4U,0U}}, +{MOVE_3100,{3U,4U,0U}}, +{MOVE_3100,{4U,4U,0U}}, +{MOVE_3100,{5U,4U,0U}}, +{MOVE_3100,{6U,4U,0U}}, +{MOVE_3100,{7U,4U,0U}}, +{MOVE_3108,{0U,4U,0U}}, +{MOVE_3108,{1U,4U,0U}}, +{MOVE_3108,{2U,4U,0U}}, +{MOVE_3108,{3U,4U,0U}}, +{MOVE_3108,{4U,4U,0U}}, +{MOVE_3108,{5U,4U,0U}}, +{MOVE_3108,{6U,4U,0U}}, +{MOVE_3108,{7U,4U,0U}}, +{MOVE_3110,{0U,4U,0U}}, +{MOVE_3110,{1U,4U,0U}}, +{MOVE_3110,{2U,4U,0U}}, +{MOVE_3110,{3U,4U,0U}}, +{MOVE_3110,{4U,4U,0U}}, +{MOVE_3110,{5U,4U,0U}}, +{MOVE_3110,{6U,4U,0U}}, +{MOVE_3110,{7U,4U,0U}}, +{MOVE_3118,{0U,4U,0U}}, +{MOVE_3118,{1U,4U,0U}}, +{MOVE_3118,{2U,4U,0U}}, +{MOVE_3118,{3U,4U,0U}}, +{MOVE_3118,{4U,4U,0U}}, +{MOVE_3118,{5U,4U,0U}}, +{MOVE_3118,{6U,4U,0U}}, +{MOVE_3118,{7U,4U,0U}}, +{MOVE_3120,{0U,4U,0U}}, +{MOVE_3120,{1U,4U,0U}}, +{MOVE_3120,{2U,4U,0U}}, +{MOVE_3120,{3U,4U,0U}}, +{MOVE_3120,{4U,4U,0U}}, +{MOVE_3120,{5U,4U,0U}}, +{MOVE_3120,{6U,4U,0U}}, +{MOVE_3120,{7U,4U,0U}}, +{MOVE_3128,{0U,4U,0U}}, +{MOVE_3128,{1U,4U,0U}}, +{MOVE_3128,{2U,4U,0U}}, +{MOVE_3128,{3U,4U,0U}}, +{MOVE_3128,{4U,4U,0U}}, +{MOVE_3128,{5U,4U,0U}}, +{MOVE_3128,{6U,4U,0U}}, +{MOVE_3128,{7U,4U,0U}}, +{MOVE_3130,{0U,4U,0U}}, +{MOVE_3130,{1U,4U,0U}}, +{MOVE_3130,{2U,4U,0U}}, +{MOVE_3130,{3U,4U,0U}}, +{MOVE_3130,{4U,4U,0U}}, +{MOVE_3130,{5U,4U,0U}}, +{MOVE_3130,{6U,4U,0U}}, +{MOVE_3130,{7U,4U,0U}}, +{MOVE_3138,{0U,4U,0U}}, +{MOVE_3139,{0U,4U,0U}}, +{MOVE_313A,{0U,4U,0U}}, +{MOVE_313B,{0U,4U,0U}}, +{MOVE_313C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3140,{0U,4U,0U}}, +{MOVE_3140,{1U,4U,0U}}, +{MOVE_3140,{2U,4U,0U}}, +{MOVE_3140,{3U,4U,0U}}, +{MOVE_3140,{4U,4U,0U}}, +{MOVE_3140,{5U,4U,0U}}, +{MOVE_3140,{6U,4U,0U}}, +{MOVE_3140,{7U,4U,0U}}, +{MOVE_3148,{0U,4U,0U}}, +{MOVE_3148,{1U,4U,0U}}, +{MOVE_3148,{2U,4U,0U}}, +{MOVE_3148,{3U,4U,0U}}, +{MOVE_3148,{4U,4U,0U}}, +{MOVE_3148,{5U,4U,0U}}, +{MOVE_3148,{6U,4U,0U}}, +{MOVE_3148,{7U,4U,0U}}, +{MOVE_3150,{0U,4U,0U}}, +{MOVE_3150,{1U,4U,0U}}, +{MOVE_3150,{2U,4U,0U}}, +{MOVE_3150,{3U,4U,0U}}, +{MOVE_3150,{4U,4U,0U}}, +{MOVE_3150,{5U,4U,0U}}, +{MOVE_3150,{6U,4U,0U}}, +{MOVE_3150,{7U,4U,0U}}, +{MOVE_3158,{0U,4U,0U}}, +{MOVE_3158,{1U,4U,0U}}, +{MOVE_3158,{2U,4U,0U}}, +{MOVE_3158,{3U,4U,0U}}, +{MOVE_3158,{4U,4U,0U}}, +{MOVE_3158,{5U,4U,0U}}, +{MOVE_3158,{6U,4U,0U}}, +{MOVE_3158,{7U,4U,0U}}, +{MOVE_3160,{0U,4U,0U}}, +{MOVE_3160,{1U,4U,0U}}, +{MOVE_3160,{2U,4U,0U}}, +{MOVE_3160,{3U,4U,0U}}, +{MOVE_3160,{4U,4U,0U}}, +{MOVE_3160,{5U,4U,0U}}, +{MOVE_3160,{6U,4U,0U}}, +{MOVE_3160,{7U,4U,0U}}, +{MOVE_3168,{0U,4U,0U}}, +{MOVE_3168,{1U,4U,0U}}, +{MOVE_3168,{2U,4U,0U}}, +{MOVE_3168,{3U,4U,0U}}, +{MOVE_3168,{4U,4U,0U}}, +{MOVE_3168,{5U,4U,0U}}, +{MOVE_3168,{6U,4U,0U}}, +{MOVE_3168,{7U,4U,0U}}, +{MOVE_3170,{0U,4U,0U}}, +{MOVE_3170,{1U,4U,0U}}, +{MOVE_3170,{2U,4U,0U}}, +{MOVE_3170,{3U,4U,0U}}, +{MOVE_3170,{4U,4U,0U}}, +{MOVE_3170,{5U,4U,0U}}, +{MOVE_3170,{6U,4U,0U}}, +{MOVE_3170,{7U,4U,0U}}, +{MOVE_3178,{0U,4U,0U}}, +{MOVE_3179,{0U,4U,0U}}, +{MOVE_317A,{0U,4U,0U}}, +{MOVE_317B,{0U,4U,0U}}, +{MOVE_317C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3180,{0U,4U,0U}}, +{MOVE_3180,{1U,4U,0U}}, +{MOVE_3180,{2U,4U,0U}}, +{MOVE_3180,{3U,4U,0U}}, +{MOVE_3180,{4U,4U,0U}}, +{MOVE_3180,{5U,4U,0U}}, +{MOVE_3180,{6U,4U,0U}}, +{MOVE_3180,{7U,4U,0U}}, +{MOVE_3188,{0U,4U,0U}}, +{MOVE_3188,{1U,4U,0U}}, +{MOVE_3188,{2U,4U,0U}}, +{MOVE_3188,{3U,4U,0U}}, +{MOVE_3188,{4U,4U,0U}}, +{MOVE_3188,{5U,4U,0U}}, +{MOVE_3188,{6U,4U,0U}}, +{MOVE_3188,{7U,4U,0U}}, +{MOVE_3190,{0U,4U,0U}}, +{MOVE_3190,{1U,4U,0U}}, +{MOVE_3190,{2U,4U,0U}}, +{MOVE_3190,{3U,4U,0U}}, +{MOVE_3190,{4U,4U,0U}}, +{MOVE_3190,{5U,4U,0U}}, +{MOVE_3190,{6U,4U,0U}}, +{MOVE_3190,{7U,4U,0U}}, +{MOVE_3198,{0U,4U,0U}}, +{MOVE_3198,{1U,4U,0U}}, +{MOVE_3198,{2U,4U,0U}}, +{MOVE_3198,{3U,4U,0U}}, +{MOVE_3198,{4U,4U,0U}}, +{MOVE_3198,{5U,4U,0U}}, +{MOVE_3198,{6U,4U,0U}}, +{MOVE_3198,{7U,4U,0U}}, +{MOVE_31A0,{0U,4U,0U}}, +{MOVE_31A0,{1U,4U,0U}}, +{MOVE_31A0,{2U,4U,0U}}, +{MOVE_31A0,{3U,4U,0U}}, +{MOVE_31A0,{4U,4U,0U}}, +{MOVE_31A0,{5U,4U,0U}}, +{MOVE_31A0,{6U,4U,0U}}, +{MOVE_31A0,{7U,4U,0U}}, +{MOVE_31A8,{0U,4U,0U}}, +{MOVE_31A8,{1U,4U,0U}}, +{MOVE_31A8,{2U,4U,0U}}, +{MOVE_31A8,{3U,4U,0U}}, +{MOVE_31A8,{4U,4U,0U}}, +{MOVE_31A8,{5U,4U,0U}}, +{MOVE_31A8,{6U,4U,0U}}, +{MOVE_31A8,{7U,4U,0U}}, +{MOVE_31B0,{0U,4U,0U}}, +{MOVE_31B0,{1U,4U,0U}}, +{MOVE_31B0,{2U,4U,0U}}, +{MOVE_31B0,{3U,4U,0U}}, +{MOVE_31B0,{4U,4U,0U}}, +{MOVE_31B0,{5U,4U,0U}}, +{MOVE_31B0,{6U,4U,0U}}, +{MOVE_31B0,{7U,4U,0U}}, +{MOVE_31B8,{0U,4U,0U}}, +{MOVE_31B9,{0U,4U,0U}}, +{MOVE_31BA,{0U,4U,0U}}, +{MOVE_31BB,{0U,4U,0U}}, +{MOVE_31BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3000,{0U,5U,0U}}, +{MOVE_3000,{1U,5U,0U}}, +{MOVE_3000,{2U,5U,0U}}, +{MOVE_3000,{3U,5U,0U}}, +{MOVE_3000,{4U,5U,0U}}, +{MOVE_3000,{5U,5U,0U}}, +{MOVE_3000,{6U,5U,0U}}, +{MOVE_3000,{7U,5U,0U}}, +{MOVE_3008,{0U,5U,0U}}, +{MOVE_3008,{1U,5U,0U}}, +{MOVE_3008,{2U,5U,0U}}, +{MOVE_3008,{3U,5U,0U}}, +{MOVE_3008,{4U,5U,0U}}, +{MOVE_3008,{5U,5U,0U}}, +{MOVE_3008,{6U,5U,0U}}, +{MOVE_3008,{7U,5U,0U}}, +{MOVE_3010,{0U,5U,0U}}, +{MOVE_3010,{1U,5U,0U}}, +{MOVE_3010,{2U,5U,0U}}, +{MOVE_3010,{3U,5U,0U}}, +{MOVE_3010,{4U,5U,0U}}, +{MOVE_3010,{5U,5U,0U}}, +{MOVE_3010,{6U,5U,0U}}, +{MOVE_3010,{7U,5U,0U}}, +{MOVE_3018,{0U,5U,0U}}, +{MOVE_3018,{1U,5U,0U}}, +{MOVE_3018,{2U,5U,0U}}, +{MOVE_3018,{3U,5U,0U}}, +{MOVE_3018,{4U,5U,0U}}, +{MOVE_3018,{5U,5U,0U}}, +{MOVE_3018,{6U,5U,0U}}, +{MOVE_3018,{7U,5U,0U}}, +{MOVE_3020,{0U,5U,0U}}, +{MOVE_3020,{1U,5U,0U}}, +{MOVE_3020,{2U,5U,0U}}, +{MOVE_3020,{3U,5U,0U}}, +{MOVE_3020,{4U,5U,0U}}, +{MOVE_3020,{5U,5U,0U}}, +{MOVE_3020,{6U,5U,0U}}, +{MOVE_3020,{7U,5U,0U}}, +{MOVE_3028,{0U,5U,0U}}, +{MOVE_3028,{1U,5U,0U}}, +{MOVE_3028,{2U,5U,0U}}, +{MOVE_3028,{3U,5U,0U}}, +{MOVE_3028,{4U,5U,0U}}, +{MOVE_3028,{5U,5U,0U}}, +{MOVE_3028,{6U,5U,0U}}, +{MOVE_3028,{7U,5U,0U}}, +{MOVE_3030,{0U,5U,0U}}, +{MOVE_3030,{1U,5U,0U}}, +{MOVE_3030,{2U,5U,0U}}, +{MOVE_3030,{3U,5U,0U}}, +{MOVE_3030,{4U,5U,0U}}, +{MOVE_3030,{5U,5U,0U}}, +{MOVE_3030,{6U,5U,0U}}, +{MOVE_3030,{7U,5U,0U}}, +{MOVE_3038,{0U,5U,0U}}, +{MOVE_3039,{0U,5U,0U}}, +{MOVE_303A,{0U,5U,0U}}, +{MOVE_303B,{0U,5U,0U}}, +{MOVE_303C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_3040,{0U,5U,0U}}, +{MOVEA_3040,{1U,5U,0U}}, +{MOVEA_3040,{2U,5U,0U}}, +{MOVEA_3040,{3U,5U,0U}}, +{MOVEA_3040,{4U,5U,0U}}, +{MOVEA_3040,{5U,5U,0U}}, +{MOVEA_3040,{6U,5U,0U}}, +{MOVEA_3040,{7U,5U,0U}}, +{MOVEA_3048,{0U,5U,0U}}, +{MOVEA_3048,{1U,5U,0U}}, +{MOVEA_3048,{2U,5U,0U}}, +{MOVEA_3048,{3U,5U,0U}}, +{MOVEA_3048,{4U,5U,0U}}, +{MOVEA_3048,{5U,5U,0U}}, +{MOVEA_3048,{6U,5U,0U}}, +{MOVEA_3048,{7U,5U,0U}}, +{MOVEA_3050,{0U,5U,0U}}, +{MOVEA_3050,{1U,5U,0U}}, +{MOVEA_3050,{2U,5U,0U}}, +{MOVEA_3050,{3U,5U,0U}}, +{MOVEA_3050,{4U,5U,0U}}, +{MOVEA_3050,{5U,5U,0U}}, +{MOVEA_3050,{6U,5U,0U}}, +{MOVEA_3050,{7U,5U,0U}}, +{MOVEA_3058,{0U,5U,0U}}, +{MOVEA_3058,{1U,5U,0U}}, +{MOVEA_3058,{2U,5U,0U}}, +{MOVEA_3058,{3U,5U,0U}}, +{MOVEA_3058,{4U,5U,0U}}, +{MOVEA_3058,{5U,5U,0U}}, +{MOVEA_3058,{6U,5U,0U}}, +{MOVEA_3058,{7U,5U,0U}}, +{MOVEA_3060,{0U,5U,0U}}, +{MOVEA_3060,{1U,5U,0U}}, +{MOVEA_3060,{2U,5U,0U}}, +{MOVEA_3060,{3U,5U,0U}}, +{MOVEA_3060,{4U,5U,0U}}, +{MOVEA_3060,{5U,5U,0U}}, +{MOVEA_3060,{6U,5U,0U}}, +{MOVEA_3060,{7U,5U,0U}}, +{MOVEA_3068,{0U,5U,0U}}, +{MOVEA_3068,{1U,5U,0U}}, +{MOVEA_3068,{2U,5U,0U}}, +{MOVEA_3068,{3U,5U,0U}}, +{MOVEA_3068,{4U,5U,0U}}, +{MOVEA_3068,{5U,5U,0U}}, +{MOVEA_3068,{6U,5U,0U}}, +{MOVEA_3068,{7U,5U,0U}}, +{MOVEA_3070,{0U,5U,0U}}, +{MOVEA_3070,{1U,5U,0U}}, +{MOVEA_3070,{2U,5U,0U}}, +{MOVEA_3070,{3U,5U,0U}}, +{MOVEA_3070,{4U,5U,0U}}, +{MOVEA_3070,{5U,5U,0U}}, +{MOVEA_3070,{6U,5U,0U}}, +{MOVEA_3070,{7U,5U,0U}}, +{MOVEA_3078,{0U,5U,0U}}, +{MOVEA_3079,{0U,5U,0U}}, +{MOVEA_307A,{0U,5U,0U}}, +{MOVEA_307B,{0U,5U,0U}}, +{MOVEA_307C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3080,{0U,5U,0U}}, +{MOVE_3080,{1U,5U,0U}}, +{MOVE_3080,{2U,5U,0U}}, +{MOVE_3080,{3U,5U,0U}}, +{MOVE_3080,{4U,5U,0U}}, +{MOVE_3080,{5U,5U,0U}}, +{MOVE_3080,{6U,5U,0U}}, +{MOVE_3080,{7U,5U,0U}}, +{MOVE_3088,{0U,5U,0U}}, +{MOVE_3088,{1U,5U,0U}}, +{MOVE_3088,{2U,5U,0U}}, +{MOVE_3088,{3U,5U,0U}}, +{MOVE_3088,{4U,5U,0U}}, +{MOVE_3088,{5U,5U,0U}}, +{MOVE_3088,{6U,5U,0U}}, +{MOVE_3088,{7U,5U,0U}}, +{MOVE_3090,{0U,5U,0U}}, +{MOVE_3090,{1U,5U,0U}}, +{MOVE_3090,{2U,5U,0U}}, +{MOVE_3090,{3U,5U,0U}}, +{MOVE_3090,{4U,5U,0U}}, +{MOVE_3090,{5U,5U,0U}}, +{MOVE_3090,{6U,5U,0U}}, +{MOVE_3090,{7U,5U,0U}}, +{MOVE_3098,{0U,5U,0U}}, +{MOVE_3098,{1U,5U,0U}}, +{MOVE_3098,{2U,5U,0U}}, +{MOVE_3098,{3U,5U,0U}}, +{MOVE_3098,{4U,5U,0U}}, +{MOVE_3098,{5U,5U,0U}}, +{MOVE_3098,{6U,5U,0U}}, +{MOVE_3098,{7U,5U,0U}}, +{MOVE_30A0,{0U,5U,0U}}, +{MOVE_30A0,{1U,5U,0U}}, +{MOVE_30A0,{2U,5U,0U}}, +{MOVE_30A0,{3U,5U,0U}}, +{MOVE_30A0,{4U,5U,0U}}, +{MOVE_30A0,{5U,5U,0U}}, +{MOVE_30A0,{6U,5U,0U}}, +{MOVE_30A0,{7U,5U,0U}}, +{MOVE_30A8,{0U,5U,0U}}, +{MOVE_30A8,{1U,5U,0U}}, +{MOVE_30A8,{2U,5U,0U}}, +{MOVE_30A8,{3U,5U,0U}}, +{MOVE_30A8,{4U,5U,0U}}, +{MOVE_30A8,{5U,5U,0U}}, +{MOVE_30A8,{6U,5U,0U}}, +{MOVE_30A8,{7U,5U,0U}}, +{MOVE_30B0,{0U,5U,0U}}, +{MOVE_30B0,{1U,5U,0U}}, +{MOVE_30B0,{2U,5U,0U}}, +{MOVE_30B0,{3U,5U,0U}}, +{MOVE_30B0,{4U,5U,0U}}, +{MOVE_30B0,{5U,5U,0U}}, +{MOVE_30B0,{6U,5U,0U}}, +{MOVE_30B0,{7U,5U,0U}}, +{MOVE_30B8,{0U,5U,0U}}, +{MOVE_30B9,{0U,5U,0U}}, +{MOVE_30BA,{0U,5U,0U}}, +{MOVE_30BB,{0U,5U,0U}}, +{MOVE_30BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_30C0,{0U,5U,0U}}, +{MOVE_30C0,{1U,5U,0U}}, +{MOVE_30C0,{2U,5U,0U}}, +{MOVE_30C0,{3U,5U,0U}}, +{MOVE_30C0,{4U,5U,0U}}, +{MOVE_30C0,{5U,5U,0U}}, +{MOVE_30C0,{6U,5U,0U}}, +{MOVE_30C0,{7U,5U,0U}}, +{MOVE_30C8,{0U,5U,0U}}, +{MOVE_30C8,{1U,5U,0U}}, +{MOVE_30C8,{2U,5U,0U}}, +{MOVE_30C8,{3U,5U,0U}}, +{MOVE_30C8,{4U,5U,0U}}, +{MOVE_30C8,{5U,5U,0U}}, +{MOVE_30C8,{6U,5U,0U}}, +{MOVE_30C8,{7U,5U,0U}}, +{MOVE_30D0,{0U,5U,0U}}, +{MOVE_30D0,{1U,5U,0U}}, +{MOVE_30D0,{2U,5U,0U}}, +{MOVE_30D0,{3U,5U,0U}}, +{MOVE_30D0,{4U,5U,0U}}, +{MOVE_30D0,{5U,5U,0U}}, +{MOVE_30D0,{6U,5U,0U}}, +{MOVE_30D0,{7U,5U,0U}}, +{MOVE_30D8,{0U,5U,0U}}, +{MOVE_30D8,{1U,5U,0U}}, +{MOVE_30D8,{2U,5U,0U}}, +{MOVE_30D8,{3U,5U,0U}}, +{MOVE_30D8,{4U,5U,0U}}, +{MOVE_30D8,{5U,5U,0U}}, +{MOVE_30D8,{6U,5U,0U}}, +{MOVE_30D8,{7U,5U,0U}}, +{MOVE_30E0,{0U,5U,0U}}, +{MOVE_30E0,{1U,5U,0U}}, +{MOVE_30E0,{2U,5U,0U}}, +{MOVE_30E0,{3U,5U,0U}}, +{MOVE_30E0,{4U,5U,0U}}, +{MOVE_30E0,{5U,5U,0U}}, +{MOVE_30E0,{6U,5U,0U}}, +{MOVE_30E0,{7U,5U,0U}}, +{MOVE_30E8,{0U,5U,0U}}, +{MOVE_30E8,{1U,5U,0U}}, +{MOVE_30E8,{2U,5U,0U}}, +{MOVE_30E8,{3U,5U,0U}}, +{MOVE_30E8,{4U,5U,0U}}, +{MOVE_30E8,{5U,5U,0U}}, +{MOVE_30E8,{6U,5U,0U}}, +{MOVE_30E8,{7U,5U,0U}}, +{MOVE_30F0,{0U,5U,0U}}, +{MOVE_30F0,{1U,5U,0U}}, +{MOVE_30F0,{2U,5U,0U}}, +{MOVE_30F0,{3U,5U,0U}}, +{MOVE_30F0,{4U,5U,0U}}, +{MOVE_30F0,{5U,5U,0U}}, +{MOVE_30F0,{6U,5U,0U}}, +{MOVE_30F0,{7U,5U,0U}}, +{MOVE_30F8,{0U,5U,0U}}, +{MOVE_30F9,{0U,5U,0U}}, +{MOVE_30FA,{0U,5U,0U}}, +{MOVE_30FB,{0U,5U,0U}}, +{MOVE_30FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3100,{0U,5U,0U}}, +{MOVE_3100,{1U,5U,0U}}, +{MOVE_3100,{2U,5U,0U}}, +{MOVE_3100,{3U,5U,0U}}, +{MOVE_3100,{4U,5U,0U}}, +{MOVE_3100,{5U,5U,0U}}, +{MOVE_3100,{6U,5U,0U}}, +{MOVE_3100,{7U,5U,0U}}, +{MOVE_3108,{0U,5U,0U}}, +{MOVE_3108,{1U,5U,0U}}, +{MOVE_3108,{2U,5U,0U}}, +{MOVE_3108,{3U,5U,0U}}, +{MOVE_3108,{4U,5U,0U}}, +{MOVE_3108,{5U,5U,0U}}, +{MOVE_3108,{6U,5U,0U}}, +{MOVE_3108,{7U,5U,0U}}, +{MOVE_3110,{0U,5U,0U}}, +{MOVE_3110,{1U,5U,0U}}, +{MOVE_3110,{2U,5U,0U}}, +{MOVE_3110,{3U,5U,0U}}, +{MOVE_3110,{4U,5U,0U}}, +{MOVE_3110,{5U,5U,0U}}, +{MOVE_3110,{6U,5U,0U}}, +{MOVE_3110,{7U,5U,0U}}, +{MOVE_3118,{0U,5U,0U}}, +{MOVE_3118,{1U,5U,0U}}, +{MOVE_3118,{2U,5U,0U}}, +{MOVE_3118,{3U,5U,0U}}, +{MOVE_3118,{4U,5U,0U}}, +{MOVE_3118,{5U,5U,0U}}, +{MOVE_3118,{6U,5U,0U}}, +{MOVE_3118,{7U,5U,0U}}, +{MOVE_3120,{0U,5U,0U}}, +{MOVE_3120,{1U,5U,0U}}, +{MOVE_3120,{2U,5U,0U}}, +{MOVE_3120,{3U,5U,0U}}, +{MOVE_3120,{4U,5U,0U}}, +{MOVE_3120,{5U,5U,0U}}, +{MOVE_3120,{6U,5U,0U}}, +{MOVE_3120,{7U,5U,0U}}, +{MOVE_3128,{0U,5U,0U}}, +{MOVE_3128,{1U,5U,0U}}, +{MOVE_3128,{2U,5U,0U}}, +{MOVE_3128,{3U,5U,0U}}, +{MOVE_3128,{4U,5U,0U}}, +{MOVE_3128,{5U,5U,0U}}, +{MOVE_3128,{6U,5U,0U}}, +{MOVE_3128,{7U,5U,0U}}, +{MOVE_3130,{0U,5U,0U}}, +{MOVE_3130,{1U,5U,0U}}, +{MOVE_3130,{2U,5U,0U}}, +{MOVE_3130,{3U,5U,0U}}, +{MOVE_3130,{4U,5U,0U}}, +{MOVE_3130,{5U,5U,0U}}, +{MOVE_3130,{6U,5U,0U}}, +{MOVE_3130,{7U,5U,0U}}, +{MOVE_3138,{0U,5U,0U}}, +{MOVE_3139,{0U,5U,0U}}, +{MOVE_313A,{0U,5U,0U}}, +{MOVE_313B,{0U,5U,0U}}, +{MOVE_313C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3140,{0U,5U,0U}}, +{MOVE_3140,{1U,5U,0U}}, +{MOVE_3140,{2U,5U,0U}}, +{MOVE_3140,{3U,5U,0U}}, +{MOVE_3140,{4U,5U,0U}}, +{MOVE_3140,{5U,5U,0U}}, +{MOVE_3140,{6U,5U,0U}}, +{MOVE_3140,{7U,5U,0U}}, +{MOVE_3148,{0U,5U,0U}}, +{MOVE_3148,{1U,5U,0U}}, +{MOVE_3148,{2U,5U,0U}}, +{MOVE_3148,{3U,5U,0U}}, +{MOVE_3148,{4U,5U,0U}}, +{MOVE_3148,{5U,5U,0U}}, +{MOVE_3148,{6U,5U,0U}}, +{MOVE_3148,{7U,5U,0U}}, +{MOVE_3150,{0U,5U,0U}}, +{MOVE_3150,{1U,5U,0U}}, +{MOVE_3150,{2U,5U,0U}}, +{MOVE_3150,{3U,5U,0U}}, +{MOVE_3150,{4U,5U,0U}}, +{MOVE_3150,{5U,5U,0U}}, +{MOVE_3150,{6U,5U,0U}}, +{MOVE_3150,{7U,5U,0U}}, +{MOVE_3158,{0U,5U,0U}}, +{MOVE_3158,{1U,5U,0U}}, +{MOVE_3158,{2U,5U,0U}}, +{MOVE_3158,{3U,5U,0U}}, +{MOVE_3158,{4U,5U,0U}}, +{MOVE_3158,{5U,5U,0U}}, +{MOVE_3158,{6U,5U,0U}}, +{MOVE_3158,{7U,5U,0U}}, +{MOVE_3160,{0U,5U,0U}}, +{MOVE_3160,{1U,5U,0U}}, +{MOVE_3160,{2U,5U,0U}}, +{MOVE_3160,{3U,5U,0U}}, +{MOVE_3160,{4U,5U,0U}}, +{MOVE_3160,{5U,5U,0U}}, +{MOVE_3160,{6U,5U,0U}}, +{MOVE_3160,{7U,5U,0U}}, +{MOVE_3168,{0U,5U,0U}}, +{MOVE_3168,{1U,5U,0U}}, +{MOVE_3168,{2U,5U,0U}}, +{MOVE_3168,{3U,5U,0U}}, +{MOVE_3168,{4U,5U,0U}}, +{MOVE_3168,{5U,5U,0U}}, +{MOVE_3168,{6U,5U,0U}}, +{MOVE_3168,{7U,5U,0U}}, +{MOVE_3170,{0U,5U,0U}}, +{MOVE_3170,{1U,5U,0U}}, +{MOVE_3170,{2U,5U,0U}}, +{MOVE_3170,{3U,5U,0U}}, +{MOVE_3170,{4U,5U,0U}}, +{MOVE_3170,{5U,5U,0U}}, +{MOVE_3170,{6U,5U,0U}}, +{MOVE_3170,{7U,5U,0U}}, +{MOVE_3178,{0U,5U,0U}}, +{MOVE_3179,{0U,5U,0U}}, +{MOVE_317A,{0U,5U,0U}}, +{MOVE_317B,{0U,5U,0U}}, +{MOVE_317C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3180,{0U,5U,0U}}, +{MOVE_3180,{1U,5U,0U}}, +{MOVE_3180,{2U,5U,0U}}, +{MOVE_3180,{3U,5U,0U}}, +{MOVE_3180,{4U,5U,0U}}, +{MOVE_3180,{5U,5U,0U}}, +{MOVE_3180,{6U,5U,0U}}, +{MOVE_3180,{7U,5U,0U}}, +{MOVE_3188,{0U,5U,0U}}, +{MOVE_3188,{1U,5U,0U}}, +{MOVE_3188,{2U,5U,0U}}, +{MOVE_3188,{3U,5U,0U}}, +{MOVE_3188,{4U,5U,0U}}, +{MOVE_3188,{5U,5U,0U}}, +{MOVE_3188,{6U,5U,0U}}, +{MOVE_3188,{7U,5U,0U}}, +{MOVE_3190,{0U,5U,0U}}, +{MOVE_3190,{1U,5U,0U}}, +{MOVE_3190,{2U,5U,0U}}, +{MOVE_3190,{3U,5U,0U}}, +{MOVE_3190,{4U,5U,0U}}, +{MOVE_3190,{5U,5U,0U}}, +{MOVE_3190,{6U,5U,0U}}, +{MOVE_3190,{7U,5U,0U}}, +{MOVE_3198,{0U,5U,0U}}, +{MOVE_3198,{1U,5U,0U}}, +{MOVE_3198,{2U,5U,0U}}, +{MOVE_3198,{3U,5U,0U}}, +{MOVE_3198,{4U,5U,0U}}, +{MOVE_3198,{5U,5U,0U}}, +{MOVE_3198,{6U,5U,0U}}, +{MOVE_3198,{7U,5U,0U}}, +{MOVE_31A0,{0U,5U,0U}}, +{MOVE_31A0,{1U,5U,0U}}, +{MOVE_31A0,{2U,5U,0U}}, +{MOVE_31A0,{3U,5U,0U}}, +{MOVE_31A0,{4U,5U,0U}}, +{MOVE_31A0,{5U,5U,0U}}, +{MOVE_31A0,{6U,5U,0U}}, +{MOVE_31A0,{7U,5U,0U}}, +{MOVE_31A8,{0U,5U,0U}}, +{MOVE_31A8,{1U,5U,0U}}, +{MOVE_31A8,{2U,5U,0U}}, +{MOVE_31A8,{3U,5U,0U}}, +{MOVE_31A8,{4U,5U,0U}}, +{MOVE_31A8,{5U,5U,0U}}, +{MOVE_31A8,{6U,5U,0U}}, +{MOVE_31A8,{7U,5U,0U}}, +{MOVE_31B0,{0U,5U,0U}}, +{MOVE_31B0,{1U,5U,0U}}, +{MOVE_31B0,{2U,5U,0U}}, +{MOVE_31B0,{3U,5U,0U}}, +{MOVE_31B0,{4U,5U,0U}}, +{MOVE_31B0,{5U,5U,0U}}, +{MOVE_31B0,{6U,5U,0U}}, +{MOVE_31B0,{7U,5U,0U}}, +{MOVE_31B8,{0U,5U,0U}}, +{MOVE_31B9,{0U,5U,0U}}, +{MOVE_31BA,{0U,5U,0U}}, +{MOVE_31BB,{0U,5U,0U}}, +{MOVE_31BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3000,{0U,6U,0U}}, +{MOVE_3000,{1U,6U,0U}}, +{MOVE_3000,{2U,6U,0U}}, +{MOVE_3000,{3U,6U,0U}}, +{MOVE_3000,{4U,6U,0U}}, +{MOVE_3000,{5U,6U,0U}}, +{MOVE_3000,{6U,6U,0U}}, +{MOVE_3000,{7U,6U,0U}}, +{MOVE_3008,{0U,6U,0U}}, +{MOVE_3008,{1U,6U,0U}}, +{MOVE_3008,{2U,6U,0U}}, +{MOVE_3008,{3U,6U,0U}}, +{MOVE_3008,{4U,6U,0U}}, +{MOVE_3008,{5U,6U,0U}}, +{MOVE_3008,{6U,6U,0U}}, +{MOVE_3008,{7U,6U,0U}}, +{MOVE_3010,{0U,6U,0U}}, +{MOVE_3010,{1U,6U,0U}}, +{MOVE_3010,{2U,6U,0U}}, +{MOVE_3010,{3U,6U,0U}}, +{MOVE_3010,{4U,6U,0U}}, +{MOVE_3010,{5U,6U,0U}}, +{MOVE_3010,{6U,6U,0U}}, +{MOVE_3010,{7U,6U,0U}}, +{MOVE_3018,{0U,6U,0U}}, +{MOVE_3018,{1U,6U,0U}}, +{MOVE_3018,{2U,6U,0U}}, +{MOVE_3018,{3U,6U,0U}}, +{MOVE_3018,{4U,6U,0U}}, +{MOVE_3018,{5U,6U,0U}}, +{MOVE_3018,{6U,6U,0U}}, +{MOVE_3018,{7U,6U,0U}}, +{MOVE_3020,{0U,6U,0U}}, +{MOVE_3020,{1U,6U,0U}}, +{MOVE_3020,{2U,6U,0U}}, +{MOVE_3020,{3U,6U,0U}}, +{MOVE_3020,{4U,6U,0U}}, +{MOVE_3020,{5U,6U,0U}}, +{MOVE_3020,{6U,6U,0U}}, +{MOVE_3020,{7U,6U,0U}}, +{MOVE_3028,{0U,6U,0U}}, +{MOVE_3028,{1U,6U,0U}}, +{MOVE_3028,{2U,6U,0U}}, +{MOVE_3028,{3U,6U,0U}}, +{MOVE_3028,{4U,6U,0U}}, +{MOVE_3028,{5U,6U,0U}}, +{MOVE_3028,{6U,6U,0U}}, +{MOVE_3028,{7U,6U,0U}}, +{MOVE_3030,{0U,6U,0U}}, +{MOVE_3030,{1U,6U,0U}}, +{MOVE_3030,{2U,6U,0U}}, +{MOVE_3030,{3U,6U,0U}}, +{MOVE_3030,{4U,6U,0U}}, +{MOVE_3030,{5U,6U,0U}}, +{MOVE_3030,{6U,6U,0U}}, +{MOVE_3030,{7U,6U,0U}}, +{MOVE_3038,{0U,6U,0U}}, +{MOVE_3039,{0U,6U,0U}}, +{MOVE_303A,{0U,6U,0U}}, +{MOVE_303B,{0U,6U,0U}}, +{MOVE_303C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_3040,{0U,6U,0U}}, +{MOVEA_3040,{1U,6U,0U}}, +{MOVEA_3040,{2U,6U,0U}}, +{MOVEA_3040,{3U,6U,0U}}, +{MOVEA_3040,{4U,6U,0U}}, +{MOVEA_3040,{5U,6U,0U}}, +{MOVEA_3040,{6U,6U,0U}}, +{MOVEA_3040,{7U,6U,0U}}, +{MOVEA_3048,{0U,6U,0U}}, +{MOVEA_3048,{1U,6U,0U}}, +{MOVEA_3048,{2U,6U,0U}}, +{MOVEA_3048,{3U,6U,0U}}, +{MOVEA_3048,{4U,6U,0U}}, +{MOVEA_3048,{5U,6U,0U}}, +{MOVEA_3048,{6U,6U,0U}}, +{MOVEA_3048,{7U,6U,0U}}, +{MOVEA_3050,{0U,6U,0U}}, +{MOVEA_3050,{1U,6U,0U}}, +{MOVEA_3050,{2U,6U,0U}}, +{MOVEA_3050,{3U,6U,0U}}, +{MOVEA_3050,{4U,6U,0U}}, +{MOVEA_3050,{5U,6U,0U}}, +{MOVEA_3050,{6U,6U,0U}}, +{MOVEA_3050,{7U,6U,0U}}, +{MOVEA_3058,{0U,6U,0U}}, +{MOVEA_3058,{1U,6U,0U}}, +{MOVEA_3058,{2U,6U,0U}}, +{MOVEA_3058,{3U,6U,0U}}, +{MOVEA_3058,{4U,6U,0U}}, +{MOVEA_3058,{5U,6U,0U}}, +{MOVEA_3058,{6U,6U,0U}}, +{MOVEA_3058,{7U,6U,0U}}, +{MOVEA_3060,{0U,6U,0U}}, +{MOVEA_3060,{1U,6U,0U}}, +{MOVEA_3060,{2U,6U,0U}}, +{MOVEA_3060,{3U,6U,0U}}, +{MOVEA_3060,{4U,6U,0U}}, +{MOVEA_3060,{5U,6U,0U}}, +{MOVEA_3060,{6U,6U,0U}}, +{MOVEA_3060,{7U,6U,0U}}, +{MOVEA_3068,{0U,6U,0U}}, +{MOVEA_3068,{1U,6U,0U}}, +{MOVEA_3068,{2U,6U,0U}}, +{MOVEA_3068,{3U,6U,0U}}, +{MOVEA_3068,{4U,6U,0U}}, +{MOVEA_3068,{5U,6U,0U}}, +{MOVEA_3068,{6U,6U,0U}}, +{MOVEA_3068,{7U,6U,0U}}, +{MOVEA_3070,{0U,6U,0U}}, +{MOVEA_3070,{1U,6U,0U}}, +{MOVEA_3070,{2U,6U,0U}}, +{MOVEA_3070,{3U,6U,0U}}, +{MOVEA_3070,{4U,6U,0U}}, +{MOVEA_3070,{5U,6U,0U}}, +{MOVEA_3070,{6U,6U,0U}}, +{MOVEA_3070,{7U,6U,0U}}, +{MOVEA_3078,{0U,6U,0U}}, +{MOVEA_3079,{0U,6U,0U}}, +{MOVEA_307A,{0U,6U,0U}}, +{MOVEA_307B,{0U,6U,0U}}, +{MOVEA_307C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3080,{0U,6U,0U}}, +{MOVE_3080,{1U,6U,0U}}, +{MOVE_3080,{2U,6U,0U}}, +{MOVE_3080,{3U,6U,0U}}, +{MOVE_3080,{4U,6U,0U}}, +{MOVE_3080,{5U,6U,0U}}, +{MOVE_3080,{6U,6U,0U}}, +{MOVE_3080,{7U,6U,0U}}, +{MOVE_3088,{0U,6U,0U}}, +{MOVE_3088,{1U,6U,0U}}, +{MOVE_3088,{2U,6U,0U}}, +{MOVE_3088,{3U,6U,0U}}, +{MOVE_3088,{4U,6U,0U}}, +{MOVE_3088,{5U,6U,0U}}, +{MOVE_3088,{6U,6U,0U}}, +{MOVE_3088,{7U,6U,0U}}, +{MOVE_3090,{0U,6U,0U}}, +{MOVE_3090,{1U,6U,0U}}, +{MOVE_3090,{2U,6U,0U}}, +{MOVE_3090,{3U,6U,0U}}, +{MOVE_3090,{4U,6U,0U}}, +{MOVE_3090,{5U,6U,0U}}, +{MOVE_3090,{6U,6U,0U}}, +{MOVE_3090,{7U,6U,0U}}, +{MOVE_3098,{0U,6U,0U}}, +{MOVE_3098,{1U,6U,0U}}, +{MOVE_3098,{2U,6U,0U}}, +{MOVE_3098,{3U,6U,0U}}, +{MOVE_3098,{4U,6U,0U}}, +{MOVE_3098,{5U,6U,0U}}, +{MOVE_3098,{6U,6U,0U}}, +{MOVE_3098,{7U,6U,0U}}, +{MOVE_30A0,{0U,6U,0U}}, +{MOVE_30A0,{1U,6U,0U}}, +{MOVE_30A0,{2U,6U,0U}}, +{MOVE_30A0,{3U,6U,0U}}, +{MOVE_30A0,{4U,6U,0U}}, +{MOVE_30A0,{5U,6U,0U}}, +{MOVE_30A0,{6U,6U,0U}}, +{MOVE_30A0,{7U,6U,0U}}, +{MOVE_30A8,{0U,6U,0U}}, +{MOVE_30A8,{1U,6U,0U}}, +{MOVE_30A8,{2U,6U,0U}}, +{MOVE_30A8,{3U,6U,0U}}, +{MOVE_30A8,{4U,6U,0U}}, +{MOVE_30A8,{5U,6U,0U}}, +{MOVE_30A8,{6U,6U,0U}}, +{MOVE_30A8,{7U,6U,0U}}, +{MOVE_30B0,{0U,6U,0U}}, +{MOVE_30B0,{1U,6U,0U}}, +{MOVE_30B0,{2U,6U,0U}}, +{MOVE_30B0,{3U,6U,0U}}, +{MOVE_30B0,{4U,6U,0U}}, +{MOVE_30B0,{5U,6U,0U}}, +{MOVE_30B0,{6U,6U,0U}}, +{MOVE_30B0,{7U,6U,0U}}, +{MOVE_30B8,{0U,6U,0U}}, +{MOVE_30B9,{0U,6U,0U}}, +{MOVE_30BA,{0U,6U,0U}}, +{MOVE_30BB,{0U,6U,0U}}, +{MOVE_30BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_30C0,{0U,6U,0U}}, +{MOVE_30C0,{1U,6U,0U}}, +{MOVE_30C0,{2U,6U,0U}}, +{MOVE_30C0,{3U,6U,0U}}, +{MOVE_30C0,{4U,6U,0U}}, +{MOVE_30C0,{5U,6U,0U}}, +{MOVE_30C0,{6U,6U,0U}}, +{MOVE_30C0,{7U,6U,0U}}, +{MOVE_30C8,{0U,6U,0U}}, +{MOVE_30C8,{1U,6U,0U}}, +{MOVE_30C8,{2U,6U,0U}}, +{MOVE_30C8,{3U,6U,0U}}, +{MOVE_30C8,{4U,6U,0U}}, +{MOVE_30C8,{5U,6U,0U}}, +{MOVE_30C8,{6U,6U,0U}}, +{MOVE_30C8,{7U,6U,0U}}, +{MOVE_30D0,{0U,6U,0U}}, +{MOVE_30D0,{1U,6U,0U}}, +{MOVE_30D0,{2U,6U,0U}}, +{MOVE_30D0,{3U,6U,0U}}, +{MOVE_30D0,{4U,6U,0U}}, +{MOVE_30D0,{5U,6U,0U}}, +{MOVE_30D0,{6U,6U,0U}}, +{MOVE_30D0,{7U,6U,0U}}, +{MOVE_30D8,{0U,6U,0U}}, +{MOVE_30D8,{1U,6U,0U}}, +{MOVE_30D8,{2U,6U,0U}}, +{MOVE_30D8,{3U,6U,0U}}, +{MOVE_30D8,{4U,6U,0U}}, +{MOVE_30D8,{5U,6U,0U}}, +{MOVE_30D8,{6U,6U,0U}}, +{MOVE_30D8,{7U,6U,0U}}, +{MOVE_30E0,{0U,6U,0U}}, +{MOVE_30E0,{1U,6U,0U}}, +{MOVE_30E0,{2U,6U,0U}}, +{MOVE_30E0,{3U,6U,0U}}, +{MOVE_30E0,{4U,6U,0U}}, +{MOVE_30E0,{5U,6U,0U}}, +{MOVE_30E0,{6U,6U,0U}}, +{MOVE_30E0,{7U,6U,0U}}, +{MOVE_30E8,{0U,6U,0U}}, +{MOVE_30E8,{1U,6U,0U}}, +{MOVE_30E8,{2U,6U,0U}}, +{MOVE_30E8,{3U,6U,0U}}, +{MOVE_30E8,{4U,6U,0U}}, +{MOVE_30E8,{5U,6U,0U}}, +{MOVE_30E8,{6U,6U,0U}}, +{MOVE_30E8,{7U,6U,0U}}, +{MOVE_30F0,{0U,6U,0U}}, +{MOVE_30F0,{1U,6U,0U}}, +{MOVE_30F0,{2U,6U,0U}}, +{MOVE_30F0,{3U,6U,0U}}, +{MOVE_30F0,{4U,6U,0U}}, +{MOVE_30F0,{5U,6U,0U}}, +{MOVE_30F0,{6U,6U,0U}}, +{MOVE_30F0,{7U,6U,0U}}, +{MOVE_30F8,{0U,6U,0U}}, +{MOVE_30F9,{0U,6U,0U}}, +{MOVE_30FA,{0U,6U,0U}}, +{MOVE_30FB,{0U,6U,0U}}, +{MOVE_30FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3100,{0U,6U,0U}}, +{MOVE_3100,{1U,6U,0U}}, +{MOVE_3100,{2U,6U,0U}}, +{MOVE_3100,{3U,6U,0U}}, +{MOVE_3100,{4U,6U,0U}}, +{MOVE_3100,{5U,6U,0U}}, +{MOVE_3100,{6U,6U,0U}}, +{MOVE_3100,{7U,6U,0U}}, +{MOVE_3108,{0U,6U,0U}}, +{MOVE_3108,{1U,6U,0U}}, +{MOVE_3108,{2U,6U,0U}}, +{MOVE_3108,{3U,6U,0U}}, +{MOVE_3108,{4U,6U,0U}}, +{MOVE_3108,{5U,6U,0U}}, +{MOVE_3108,{6U,6U,0U}}, +{MOVE_3108,{7U,6U,0U}}, +{MOVE_3110,{0U,6U,0U}}, +{MOVE_3110,{1U,6U,0U}}, +{MOVE_3110,{2U,6U,0U}}, +{MOVE_3110,{3U,6U,0U}}, +{MOVE_3110,{4U,6U,0U}}, +{MOVE_3110,{5U,6U,0U}}, +{MOVE_3110,{6U,6U,0U}}, +{MOVE_3110,{7U,6U,0U}}, +{MOVE_3118,{0U,6U,0U}}, +{MOVE_3118,{1U,6U,0U}}, +{MOVE_3118,{2U,6U,0U}}, +{MOVE_3118,{3U,6U,0U}}, +{MOVE_3118,{4U,6U,0U}}, +{MOVE_3118,{5U,6U,0U}}, +{MOVE_3118,{6U,6U,0U}}, +{MOVE_3118,{7U,6U,0U}}, +{MOVE_3120,{0U,6U,0U}}, +{MOVE_3120,{1U,6U,0U}}, +{MOVE_3120,{2U,6U,0U}}, +{MOVE_3120,{3U,6U,0U}}, +{MOVE_3120,{4U,6U,0U}}, +{MOVE_3120,{5U,6U,0U}}, +{MOVE_3120,{6U,6U,0U}}, +{MOVE_3120,{7U,6U,0U}}, +{MOVE_3128,{0U,6U,0U}}, +{MOVE_3128,{1U,6U,0U}}, +{MOVE_3128,{2U,6U,0U}}, +{MOVE_3128,{3U,6U,0U}}, +{MOVE_3128,{4U,6U,0U}}, +{MOVE_3128,{5U,6U,0U}}, +{MOVE_3128,{6U,6U,0U}}, +{MOVE_3128,{7U,6U,0U}}, +{MOVE_3130,{0U,6U,0U}}, +{MOVE_3130,{1U,6U,0U}}, +{MOVE_3130,{2U,6U,0U}}, +{MOVE_3130,{3U,6U,0U}}, +{MOVE_3130,{4U,6U,0U}}, +{MOVE_3130,{5U,6U,0U}}, +{MOVE_3130,{6U,6U,0U}}, +{MOVE_3130,{7U,6U,0U}}, +{MOVE_3138,{0U,6U,0U}}, +{MOVE_3139,{0U,6U,0U}}, +{MOVE_313A,{0U,6U,0U}}, +{MOVE_313B,{0U,6U,0U}}, +{MOVE_313C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3140,{0U,6U,0U}}, +{MOVE_3140,{1U,6U,0U}}, +{MOVE_3140,{2U,6U,0U}}, +{MOVE_3140,{3U,6U,0U}}, +{MOVE_3140,{4U,6U,0U}}, +{MOVE_3140,{5U,6U,0U}}, +{MOVE_3140,{6U,6U,0U}}, +{MOVE_3140,{7U,6U,0U}}, +{MOVE_3148,{0U,6U,0U}}, +{MOVE_3148,{1U,6U,0U}}, +{MOVE_3148,{2U,6U,0U}}, +{MOVE_3148,{3U,6U,0U}}, +{MOVE_3148,{4U,6U,0U}}, +{MOVE_3148,{5U,6U,0U}}, +{MOVE_3148,{6U,6U,0U}}, +{MOVE_3148,{7U,6U,0U}}, +{MOVE_3150,{0U,6U,0U}}, +{MOVE_3150,{1U,6U,0U}}, +{MOVE_3150,{2U,6U,0U}}, +{MOVE_3150,{3U,6U,0U}}, +{MOVE_3150,{4U,6U,0U}}, +{MOVE_3150,{5U,6U,0U}}, +{MOVE_3150,{6U,6U,0U}}, +{MOVE_3150,{7U,6U,0U}}, +{MOVE_3158,{0U,6U,0U}}, +{MOVE_3158,{1U,6U,0U}}, +{MOVE_3158,{2U,6U,0U}}, +{MOVE_3158,{3U,6U,0U}}, +{MOVE_3158,{4U,6U,0U}}, +{MOVE_3158,{5U,6U,0U}}, +{MOVE_3158,{6U,6U,0U}}, +{MOVE_3158,{7U,6U,0U}}, +{MOVE_3160,{0U,6U,0U}}, +{MOVE_3160,{1U,6U,0U}}, +{MOVE_3160,{2U,6U,0U}}, +{MOVE_3160,{3U,6U,0U}}, +{MOVE_3160,{4U,6U,0U}}, +{MOVE_3160,{5U,6U,0U}}, +{MOVE_3160,{6U,6U,0U}}, +{MOVE_3160,{7U,6U,0U}}, +{MOVE_3168,{0U,6U,0U}}, +{MOVE_3168,{1U,6U,0U}}, +{MOVE_3168,{2U,6U,0U}}, +{MOVE_3168,{3U,6U,0U}}, +{MOVE_3168,{4U,6U,0U}}, +{MOVE_3168,{5U,6U,0U}}, +{MOVE_3168,{6U,6U,0U}}, +{MOVE_3168,{7U,6U,0U}}, +{MOVE_3170,{0U,6U,0U}}, +{MOVE_3170,{1U,6U,0U}}, +{MOVE_3170,{2U,6U,0U}}, +{MOVE_3170,{3U,6U,0U}}, +{MOVE_3170,{4U,6U,0U}}, +{MOVE_3170,{5U,6U,0U}}, +{MOVE_3170,{6U,6U,0U}}, +{MOVE_3170,{7U,6U,0U}}, +{MOVE_3178,{0U,6U,0U}}, +{MOVE_3179,{0U,6U,0U}}, +{MOVE_317A,{0U,6U,0U}}, +{MOVE_317B,{0U,6U,0U}}, +{MOVE_317C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3180,{0U,6U,0U}}, +{MOVE_3180,{1U,6U,0U}}, +{MOVE_3180,{2U,6U,0U}}, +{MOVE_3180,{3U,6U,0U}}, +{MOVE_3180,{4U,6U,0U}}, +{MOVE_3180,{5U,6U,0U}}, +{MOVE_3180,{6U,6U,0U}}, +{MOVE_3180,{7U,6U,0U}}, +{MOVE_3188,{0U,6U,0U}}, +{MOVE_3188,{1U,6U,0U}}, +{MOVE_3188,{2U,6U,0U}}, +{MOVE_3188,{3U,6U,0U}}, +{MOVE_3188,{4U,6U,0U}}, +{MOVE_3188,{5U,6U,0U}}, +{MOVE_3188,{6U,6U,0U}}, +{MOVE_3188,{7U,6U,0U}}, +{MOVE_3190,{0U,6U,0U}}, +{MOVE_3190,{1U,6U,0U}}, +{MOVE_3190,{2U,6U,0U}}, +{MOVE_3190,{3U,6U,0U}}, +{MOVE_3190,{4U,6U,0U}}, +{MOVE_3190,{5U,6U,0U}}, +{MOVE_3190,{6U,6U,0U}}, +{MOVE_3190,{7U,6U,0U}}, +{MOVE_3198,{0U,6U,0U}}, +{MOVE_3198,{1U,6U,0U}}, +{MOVE_3198,{2U,6U,0U}}, +{MOVE_3198,{3U,6U,0U}}, +{MOVE_3198,{4U,6U,0U}}, +{MOVE_3198,{5U,6U,0U}}, +{MOVE_3198,{6U,6U,0U}}, +{MOVE_3198,{7U,6U,0U}}, +{MOVE_31A0,{0U,6U,0U}}, +{MOVE_31A0,{1U,6U,0U}}, +{MOVE_31A0,{2U,6U,0U}}, +{MOVE_31A0,{3U,6U,0U}}, +{MOVE_31A0,{4U,6U,0U}}, +{MOVE_31A0,{5U,6U,0U}}, +{MOVE_31A0,{6U,6U,0U}}, +{MOVE_31A0,{7U,6U,0U}}, +{MOVE_31A8,{0U,6U,0U}}, +{MOVE_31A8,{1U,6U,0U}}, +{MOVE_31A8,{2U,6U,0U}}, +{MOVE_31A8,{3U,6U,0U}}, +{MOVE_31A8,{4U,6U,0U}}, +{MOVE_31A8,{5U,6U,0U}}, +{MOVE_31A8,{6U,6U,0U}}, +{MOVE_31A8,{7U,6U,0U}}, +{MOVE_31B0,{0U,6U,0U}}, +{MOVE_31B0,{1U,6U,0U}}, +{MOVE_31B0,{2U,6U,0U}}, +{MOVE_31B0,{3U,6U,0U}}, +{MOVE_31B0,{4U,6U,0U}}, +{MOVE_31B0,{5U,6U,0U}}, +{MOVE_31B0,{6U,6U,0U}}, +{MOVE_31B0,{7U,6U,0U}}, +{MOVE_31B8,{0U,6U,0U}}, +{MOVE_31B9,{0U,6U,0U}}, +{MOVE_31BA,{0U,6U,0U}}, +{MOVE_31BB,{0U,6U,0U}}, +{MOVE_31BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3000,{0U,7U,0U}}, +{MOVE_3000,{1U,7U,0U}}, +{MOVE_3000,{2U,7U,0U}}, +{MOVE_3000,{3U,7U,0U}}, +{MOVE_3000,{4U,7U,0U}}, +{MOVE_3000,{5U,7U,0U}}, +{MOVE_3000,{6U,7U,0U}}, +{MOVE_3000,{7U,7U,0U}}, +{MOVE_3008,{0U,7U,0U}}, +{MOVE_3008,{1U,7U,0U}}, +{MOVE_3008,{2U,7U,0U}}, +{MOVE_3008,{3U,7U,0U}}, +{MOVE_3008,{4U,7U,0U}}, +{MOVE_3008,{5U,7U,0U}}, +{MOVE_3008,{6U,7U,0U}}, +{MOVE_3008,{7U,7U,0U}}, +{MOVE_3010,{0U,7U,0U}}, +{MOVE_3010,{1U,7U,0U}}, +{MOVE_3010,{2U,7U,0U}}, +{MOVE_3010,{3U,7U,0U}}, +{MOVE_3010,{4U,7U,0U}}, +{MOVE_3010,{5U,7U,0U}}, +{MOVE_3010,{6U,7U,0U}}, +{MOVE_3010,{7U,7U,0U}}, +{MOVE_3018,{0U,7U,0U}}, +{MOVE_3018,{1U,7U,0U}}, +{MOVE_3018,{2U,7U,0U}}, +{MOVE_3018,{3U,7U,0U}}, +{MOVE_3018,{4U,7U,0U}}, +{MOVE_3018,{5U,7U,0U}}, +{MOVE_3018,{6U,7U,0U}}, +{MOVE_3018,{7U,7U,0U}}, +{MOVE_3020,{0U,7U,0U}}, +{MOVE_3020,{1U,7U,0U}}, +{MOVE_3020,{2U,7U,0U}}, +{MOVE_3020,{3U,7U,0U}}, +{MOVE_3020,{4U,7U,0U}}, +{MOVE_3020,{5U,7U,0U}}, +{MOVE_3020,{6U,7U,0U}}, +{MOVE_3020,{7U,7U,0U}}, +{MOVE_3028,{0U,7U,0U}}, +{MOVE_3028,{1U,7U,0U}}, +{MOVE_3028,{2U,7U,0U}}, +{MOVE_3028,{3U,7U,0U}}, +{MOVE_3028,{4U,7U,0U}}, +{MOVE_3028,{5U,7U,0U}}, +{MOVE_3028,{6U,7U,0U}}, +{MOVE_3028,{7U,7U,0U}}, +{MOVE_3030,{0U,7U,0U}}, +{MOVE_3030,{1U,7U,0U}}, +{MOVE_3030,{2U,7U,0U}}, +{MOVE_3030,{3U,7U,0U}}, +{MOVE_3030,{4U,7U,0U}}, +{MOVE_3030,{5U,7U,0U}}, +{MOVE_3030,{6U,7U,0U}}, +{MOVE_3030,{7U,7U,0U}}, +{MOVE_3038,{0U,7U,0U}}, +{MOVE_3039,{0U,7U,0U}}, +{MOVE_303A,{0U,7U,0U}}, +{MOVE_303B,{0U,7U,0U}}, +{MOVE_303C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEA_3040,{0U,7U,0U}}, +{MOVEA_3040,{1U,7U,0U}}, +{MOVEA_3040,{2U,7U,0U}}, +{MOVEA_3040,{3U,7U,0U}}, +{MOVEA_3040,{4U,7U,0U}}, +{MOVEA_3040,{5U,7U,0U}}, +{MOVEA_3040,{6U,7U,0U}}, +{MOVEA_3040,{7U,7U,0U}}, +{MOVEA_3048,{0U,7U,0U}}, +{MOVEA_3048,{1U,7U,0U}}, +{MOVEA_3048,{2U,7U,0U}}, +{MOVEA_3048,{3U,7U,0U}}, +{MOVEA_3048,{4U,7U,0U}}, +{MOVEA_3048,{5U,7U,0U}}, +{MOVEA_3048,{6U,7U,0U}}, +{MOVEA_3048,{7U,7U,0U}}, +{MOVEA_3050,{0U,7U,0U}}, +{MOVEA_3050,{1U,7U,0U}}, +{MOVEA_3050,{2U,7U,0U}}, +{MOVEA_3050,{3U,7U,0U}}, +{MOVEA_3050,{4U,7U,0U}}, +{MOVEA_3050,{5U,7U,0U}}, +{MOVEA_3050,{6U,7U,0U}}, +{MOVEA_3050,{7U,7U,0U}}, +{MOVEA_3058,{0U,7U,0U}}, +{MOVEA_3058,{1U,7U,0U}}, +{MOVEA_3058,{2U,7U,0U}}, +{MOVEA_3058,{3U,7U,0U}}, +{MOVEA_3058,{4U,7U,0U}}, +{MOVEA_3058,{5U,7U,0U}}, +{MOVEA_3058,{6U,7U,0U}}, +{MOVEA_3058,{7U,7U,0U}}, +{MOVEA_3060,{0U,7U,0U}}, +{MOVEA_3060,{1U,7U,0U}}, +{MOVEA_3060,{2U,7U,0U}}, +{MOVEA_3060,{3U,7U,0U}}, +{MOVEA_3060,{4U,7U,0U}}, +{MOVEA_3060,{5U,7U,0U}}, +{MOVEA_3060,{6U,7U,0U}}, +{MOVEA_3060,{7U,7U,0U}}, +{MOVEA_3068,{0U,7U,0U}}, +{MOVEA_3068,{1U,7U,0U}}, +{MOVEA_3068,{2U,7U,0U}}, +{MOVEA_3068,{3U,7U,0U}}, +{MOVEA_3068,{4U,7U,0U}}, +{MOVEA_3068,{5U,7U,0U}}, +{MOVEA_3068,{6U,7U,0U}}, +{MOVEA_3068,{7U,7U,0U}}, +{MOVEA_3070,{0U,7U,0U}}, +{MOVEA_3070,{1U,7U,0U}}, +{MOVEA_3070,{2U,7U,0U}}, +{MOVEA_3070,{3U,7U,0U}}, +{MOVEA_3070,{4U,7U,0U}}, +{MOVEA_3070,{5U,7U,0U}}, +{MOVEA_3070,{6U,7U,0U}}, +{MOVEA_3070,{7U,7U,0U}}, +{MOVEA_3078,{0U,7U,0U}}, +{MOVEA_3079,{0U,7U,0U}}, +{MOVEA_307A,{0U,7U,0U}}, +{MOVEA_307B,{0U,7U,0U}}, +{MOVEA_307C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3080,{0U,7U,0U}}, +{MOVE_3080,{1U,7U,0U}}, +{MOVE_3080,{2U,7U,0U}}, +{MOVE_3080,{3U,7U,0U}}, +{MOVE_3080,{4U,7U,0U}}, +{MOVE_3080,{5U,7U,0U}}, +{MOVE_3080,{6U,7U,0U}}, +{MOVE_3080,{7U,7U,0U}}, +{MOVE_3088,{0U,7U,0U}}, +{MOVE_3088,{1U,7U,0U}}, +{MOVE_3088,{2U,7U,0U}}, +{MOVE_3088,{3U,7U,0U}}, +{MOVE_3088,{4U,7U,0U}}, +{MOVE_3088,{5U,7U,0U}}, +{MOVE_3088,{6U,7U,0U}}, +{MOVE_3088,{7U,7U,0U}}, +{MOVE_3090,{0U,7U,0U}}, +{MOVE_3090,{1U,7U,0U}}, +{MOVE_3090,{2U,7U,0U}}, +{MOVE_3090,{3U,7U,0U}}, +{MOVE_3090,{4U,7U,0U}}, +{MOVE_3090,{5U,7U,0U}}, +{MOVE_3090,{6U,7U,0U}}, +{MOVE_3090,{7U,7U,0U}}, +{MOVE_3098,{0U,7U,0U}}, +{MOVE_3098,{1U,7U,0U}}, +{MOVE_3098,{2U,7U,0U}}, +{MOVE_3098,{3U,7U,0U}}, +{MOVE_3098,{4U,7U,0U}}, +{MOVE_3098,{5U,7U,0U}}, +{MOVE_3098,{6U,7U,0U}}, +{MOVE_3098,{7U,7U,0U}}, +{MOVE_30A0,{0U,7U,0U}}, +{MOVE_30A0,{1U,7U,0U}}, +{MOVE_30A0,{2U,7U,0U}}, +{MOVE_30A0,{3U,7U,0U}}, +{MOVE_30A0,{4U,7U,0U}}, +{MOVE_30A0,{5U,7U,0U}}, +{MOVE_30A0,{6U,7U,0U}}, +{MOVE_30A0,{7U,7U,0U}}, +{MOVE_30A8,{0U,7U,0U}}, +{MOVE_30A8,{1U,7U,0U}}, +{MOVE_30A8,{2U,7U,0U}}, +{MOVE_30A8,{3U,7U,0U}}, +{MOVE_30A8,{4U,7U,0U}}, +{MOVE_30A8,{5U,7U,0U}}, +{MOVE_30A8,{6U,7U,0U}}, +{MOVE_30A8,{7U,7U,0U}}, +{MOVE_30B0,{0U,7U,0U}}, +{MOVE_30B0,{1U,7U,0U}}, +{MOVE_30B0,{2U,7U,0U}}, +{MOVE_30B0,{3U,7U,0U}}, +{MOVE_30B0,{4U,7U,0U}}, +{MOVE_30B0,{5U,7U,0U}}, +{MOVE_30B0,{6U,7U,0U}}, +{MOVE_30B0,{7U,7U,0U}}, +{MOVE_30B8,{0U,7U,0U}}, +{MOVE_30B9,{0U,7U,0U}}, +{MOVE_30BA,{0U,7U,0U}}, +{MOVE_30BB,{0U,7U,0U}}, +{MOVE_30BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_30C0,{0U,7U,0U}}, +{MOVE_30C0,{1U,7U,0U}}, +{MOVE_30C0,{2U,7U,0U}}, +{MOVE_30C0,{3U,7U,0U}}, +{MOVE_30C0,{4U,7U,0U}}, +{MOVE_30C0,{5U,7U,0U}}, +{MOVE_30C0,{6U,7U,0U}}, +{MOVE_30C0,{7U,7U,0U}}, +{MOVE_30C8,{0U,7U,0U}}, +{MOVE_30C8,{1U,7U,0U}}, +{MOVE_30C8,{2U,7U,0U}}, +{MOVE_30C8,{3U,7U,0U}}, +{MOVE_30C8,{4U,7U,0U}}, +{MOVE_30C8,{5U,7U,0U}}, +{MOVE_30C8,{6U,7U,0U}}, +{MOVE_30C8,{7U,7U,0U}}, +{MOVE_30D0,{0U,7U,0U}}, +{MOVE_30D0,{1U,7U,0U}}, +{MOVE_30D0,{2U,7U,0U}}, +{MOVE_30D0,{3U,7U,0U}}, +{MOVE_30D0,{4U,7U,0U}}, +{MOVE_30D0,{5U,7U,0U}}, +{MOVE_30D0,{6U,7U,0U}}, +{MOVE_30D0,{7U,7U,0U}}, +{MOVE_30D8,{0U,7U,0U}}, +{MOVE_30D8,{1U,7U,0U}}, +{MOVE_30D8,{2U,7U,0U}}, +{MOVE_30D8,{3U,7U,0U}}, +{MOVE_30D8,{4U,7U,0U}}, +{MOVE_30D8,{5U,7U,0U}}, +{MOVE_30D8,{6U,7U,0U}}, +{MOVE_30D8,{7U,7U,0U}}, +{MOVE_30E0,{0U,7U,0U}}, +{MOVE_30E0,{1U,7U,0U}}, +{MOVE_30E0,{2U,7U,0U}}, +{MOVE_30E0,{3U,7U,0U}}, +{MOVE_30E0,{4U,7U,0U}}, +{MOVE_30E0,{5U,7U,0U}}, +{MOVE_30E0,{6U,7U,0U}}, +{MOVE_30E0,{7U,7U,0U}}, +{MOVE_30E8,{0U,7U,0U}}, +{MOVE_30E8,{1U,7U,0U}}, +{MOVE_30E8,{2U,7U,0U}}, +{MOVE_30E8,{3U,7U,0U}}, +{MOVE_30E8,{4U,7U,0U}}, +{MOVE_30E8,{5U,7U,0U}}, +{MOVE_30E8,{6U,7U,0U}}, +{MOVE_30E8,{7U,7U,0U}}, +{MOVE_30F0,{0U,7U,0U}}, +{MOVE_30F0,{1U,7U,0U}}, +{MOVE_30F0,{2U,7U,0U}}, +{MOVE_30F0,{3U,7U,0U}}, +{MOVE_30F0,{4U,7U,0U}}, +{MOVE_30F0,{5U,7U,0U}}, +{MOVE_30F0,{6U,7U,0U}}, +{MOVE_30F0,{7U,7U,0U}}, +{MOVE_30F8,{0U,7U,0U}}, +{MOVE_30F9,{0U,7U,0U}}, +{MOVE_30FA,{0U,7U,0U}}, +{MOVE_30FB,{0U,7U,0U}}, +{MOVE_30FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3100,{0U,7U,0U}}, +{MOVE_3100,{1U,7U,0U}}, +{MOVE_3100,{2U,7U,0U}}, +{MOVE_3100,{3U,7U,0U}}, +{MOVE_3100,{4U,7U,0U}}, +{MOVE_3100,{5U,7U,0U}}, +{MOVE_3100,{6U,7U,0U}}, +{MOVE_3100,{7U,7U,0U}}, +{MOVE_3108,{0U,7U,0U}}, +{MOVE_3108,{1U,7U,0U}}, +{MOVE_3108,{2U,7U,0U}}, +{MOVE_3108,{3U,7U,0U}}, +{MOVE_3108,{4U,7U,0U}}, +{MOVE_3108,{5U,7U,0U}}, +{MOVE_3108,{6U,7U,0U}}, +{MOVE_3108,{7U,7U,0U}}, +{MOVE_3110,{0U,7U,0U}}, +{MOVE_3110,{1U,7U,0U}}, +{MOVE_3110,{2U,7U,0U}}, +{MOVE_3110,{3U,7U,0U}}, +{MOVE_3110,{4U,7U,0U}}, +{MOVE_3110,{5U,7U,0U}}, +{MOVE_3110,{6U,7U,0U}}, +{MOVE_3110,{7U,7U,0U}}, +{MOVE_3118,{0U,7U,0U}}, +{MOVE_3118,{1U,7U,0U}}, +{MOVE_3118,{2U,7U,0U}}, +{MOVE_3118,{3U,7U,0U}}, +{MOVE_3118,{4U,7U,0U}}, +{MOVE_3118,{5U,7U,0U}}, +{MOVE_3118,{6U,7U,0U}}, +{MOVE_3118,{7U,7U,0U}}, +{MOVE_3120,{0U,7U,0U}}, +{MOVE_3120,{1U,7U,0U}}, +{MOVE_3120,{2U,7U,0U}}, +{MOVE_3120,{3U,7U,0U}}, +{MOVE_3120,{4U,7U,0U}}, +{MOVE_3120,{5U,7U,0U}}, +{MOVE_3120,{6U,7U,0U}}, +{MOVE_3120,{7U,7U,0U}}, +{MOVE_3128,{0U,7U,0U}}, +{MOVE_3128,{1U,7U,0U}}, +{MOVE_3128,{2U,7U,0U}}, +{MOVE_3128,{3U,7U,0U}}, +{MOVE_3128,{4U,7U,0U}}, +{MOVE_3128,{5U,7U,0U}}, +{MOVE_3128,{6U,7U,0U}}, +{MOVE_3128,{7U,7U,0U}}, +{MOVE_3130,{0U,7U,0U}}, +{MOVE_3130,{1U,7U,0U}}, +{MOVE_3130,{2U,7U,0U}}, +{MOVE_3130,{3U,7U,0U}}, +{MOVE_3130,{4U,7U,0U}}, +{MOVE_3130,{5U,7U,0U}}, +{MOVE_3130,{6U,7U,0U}}, +{MOVE_3130,{7U,7U,0U}}, +{MOVE_3138,{0U,7U,0U}}, +{MOVE_3139,{0U,7U,0U}}, +{MOVE_313A,{0U,7U,0U}}, +{MOVE_313B,{0U,7U,0U}}, +{MOVE_313C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3140,{0U,7U,0U}}, +{MOVE_3140,{1U,7U,0U}}, +{MOVE_3140,{2U,7U,0U}}, +{MOVE_3140,{3U,7U,0U}}, +{MOVE_3140,{4U,7U,0U}}, +{MOVE_3140,{5U,7U,0U}}, +{MOVE_3140,{6U,7U,0U}}, +{MOVE_3140,{7U,7U,0U}}, +{MOVE_3148,{0U,7U,0U}}, +{MOVE_3148,{1U,7U,0U}}, +{MOVE_3148,{2U,7U,0U}}, +{MOVE_3148,{3U,7U,0U}}, +{MOVE_3148,{4U,7U,0U}}, +{MOVE_3148,{5U,7U,0U}}, +{MOVE_3148,{6U,7U,0U}}, +{MOVE_3148,{7U,7U,0U}}, +{MOVE_3150,{0U,7U,0U}}, +{MOVE_3150,{1U,7U,0U}}, +{MOVE_3150,{2U,7U,0U}}, +{MOVE_3150,{3U,7U,0U}}, +{MOVE_3150,{4U,7U,0U}}, +{MOVE_3150,{5U,7U,0U}}, +{MOVE_3150,{6U,7U,0U}}, +{MOVE_3150,{7U,7U,0U}}, +{MOVE_3158,{0U,7U,0U}}, +{MOVE_3158,{1U,7U,0U}}, +{MOVE_3158,{2U,7U,0U}}, +{MOVE_3158,{3U,7U,0U}}, +{MOVE_3158,{4U,7U,0U}}, +{MOVE_3158,{5U,7U,0U}}, +{MOVE_3158,{6U,7U,0U}}, +{MOVE_3158,{7U,7U,0U}}, +{MOVE_3160,{0U,7U,0U}}, +{MOVE_3160,{1U,7U,0U}}, +{MOVE_3160,{2U,7U,0U}}, +{MOVE_3160,{3U,7U,0U}}, +{MOVE_3160,{4U,7U,0U}}, +{MOVE_3160,{5U,7U,0U}}, +{MOVE_3160,{6U,7U,0U}}, +{MOVE_3160,{7U,7U,0U}}, +{MOVE_3168,{0U,7U,0U}}, +{MOVE_3168,{1U,7U,0U}}, +{MOVE_3168,{2U,7U,0U}}, +{MOVE_3168,{3U,7U,0U}}, +{MOVE_3168,{4U,7U,0U}}, +{MOVE_3168,{5U,7U,0U}}, +{MOVE_3168,{6U,7U,0U}}, +{MOVE_3168,{7U,7U,0U}}, +{MOVE_3170,{0U,7U,0U}}, +{MOVE_3170,{1U,7U,0U}}, +{MOVE_3170,{2U,7U,0U}}, +{MOVE_3170,{3U,7U,0U}}, +{MOVE_3170,{4U,7U,0U}}, +{MOVE_3170,{5U,7U,0U}}, +{MOVE_3170,{6U,7U,0U}}, +{MOVE_3170,{7U,7U,0U}}, +{MOVE_3178,{0U,7U,0U}}, +{MOVE_3179,{0U,7U,0U}}, +{MOVE_317A,{0U,7U,0U}}, +{MOVE_317B,{0U,7U,0U}}, +{MOVE_317C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVE_3180,{0U,7U,0U}}, +{MOVE_3180,{1U,7U,0U}}, +{MOVE_3180,{2U,7U,0U}}, +{MOVE_3180,{3U,7U,0U}}, +{MOVE_3180,{4U,7U,0U}}, +{MOVE_3180,{5U,7U,0U}}, +{MOVE_3180,{6U,7U,0U}}, +{MOVE_3180,{7U,7U,0U}}, +{MOVE_3188,{0U,7U,0U}}, +{MOVE_3188,{1U,7U,0U}}, +{MOVE_3188,{2U,7U,0U}}, +{MOVE_3188,{3U,7U,0U}}, +{MOVE_3188,{4U,7U,0U}}, +{MOVE_3188,{5U,7U,0U}}, +{MOVE_3188,{6U,7U,0U}}, +{MOVE_3188,{7U,7U,0U}}, +{MOVE_3190,{0U,7U,0U}}, +{MOVE_3190,{1U,7U,0U}}, +{MOVE_3190,{2U,7U,0U}}, +{MOVE_3190,{3U,7U,0U}}, +{MOVE_3190,{4U,7U,0U}}, +{MOVE_3190,{5U,7U,0U}}, +{MOVE_3190,{6U,7U,0U}}, +{MOVE_3190,{7U,7U,0U}}, +{MOVE_3198,{0U,7U,0U}}, +{MOVE_3198,{1U,7U,0U}}, +{MOVE_3198,{2U,7U,0U}}, +{MOVE_3198,{3U,7U,0U}}, +{MOVE_3198,{4U,7U,0U}}, +{MOVE_3198,{5U,7U,0U}}, +{MOVE_3198,{6U,7U,0U}}, +{MOVE_3198,{7U,7U,0U}}, +{MOVE_31A0,{0U,7U,0U}}, +{MOVE_31A0,{1U,7U,0U}}, +{MOVE_31A0,{2U,7U,0U}}, +{MOVE_31A0,{3U,7U,0U}}, +{MOVE_31A0,{4U,7U,0U}}, +{MOVE_31A0,{5U,7U,0U}}, +{MOVE_31A0,{6U,7U,0U}}, +{MOVE_31A0,{7U,7U,0U}}, +{MOVE_31A8,{0U,7U,0U}}, +{MOVE_31A8,{1U,7U,0U}}, +{MOVE_31A8,{2U,7U,0U}}, +{MOVE_31A8,{3U,7U,0U}}, +{MOVE_31A8,{4U,7U,0U}}, +{MOVE_31A8,{5U,7U,0U}}, +{MOVE_31A8,{6U,7U,0U}}, +{MOVE_31A8,{7U,7U,0U}}, +{MOVE_31B0,{0U,7U,0U}}, +{MOVE_31B0,{1U,7U,0U}}, +{MOVE_31B0,{2U,7U,0U}}, +{MOVE_31B0,{3U,7U,0U}}, +{MOVE_31B0,{4U,7U,0U}}, +{MOVE_31B0,{5U,7U,0U}}, +{MOVE_31B0,{6U,7U,0U}}, +{MOVE_31B0,{7U,7U,0U}}, +{MOVE_31B8,{0U,7U,0U}}, +{MOVE_31B9,{0U,7U,0U}}, +{MOVE_31BA,{0U,7U,0U}}, +{MOVE_31BB,{0U,7U,0U}}, +{MOVE_31BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEGX_4000,{0U,0U,0U}}, +{NEGX_4000,{1U,0U,0U}}, +{NEGX_4000,{2U,0U,0U}}, +{NEGX_4000,{3U,0U,0U}}, +{NEGX_4000,{4U,0U,0U}}, +{NEGX_4000,{5U,0U,0U}}, +{NEGX_4000,{6U,0U,0U}}, +{NEGX_4000,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEGX_4010,{0U,0U,0U}}, +{NEGX_4010,{1U,0U,0U}}, +{NEGX_4010,{2U,0U,0U}}, +{NEGX_4010,{3U,0U,0U}}, +{NEGX_4010,{4U,0U,0U}}, +{NEGX_4010,{5U,0U,0U}}, +{NEGX_4010,{6U,0U,0U}}, +{NEGX_4010,{7U,0U,0U}}, +{NEGX_4018,{0U,0U,0U}}, +{NEGX_4018,{1U,0U,0U}}, +{NEGX_4018,{2U,0U,0U}}, +{NEGX_4018,{3U,0U,0U}}, +{NEGX_4018,{4U,0U,0U}}, +{NEGX_4018,{5U,0U,0U}}, +{NEGX_4018,{6U,0U,0U}}, +{NEGX_4018,{7U,0U,0U}}, +{NEGX_4020,{0U,0U,0U}}, +{NEGX_4020,{1U,0U,0U}}, +{NEGX_4020,{2U,0U,0U}}, +{NEGX_4020,{3U,0U,0U}}, +{NEGX_4020,{4U,0U,0U}}, +{NEGX_4020,{5U,0U,0U}}, +{NEGX_4020,{6U,0U,0U}}, +{NEGX_4020,{7U,0U,0U}}, +{NEGX_4028,{0U,0U,0U}}, +{NEGX_4028,{1U,0U,0U}}, +{NEGX_4028,{2U,0U,0U}}, +{NEGX_4028,{3U,0U,0U}}, +{NEGX_4028,{4U,0U,0U}}, +{NEGX_4028,{5U,0U,0U}}, +{NEGX_4028,{6U,0U,0U}}, +{NEGX_4028,{7U,0U,0U}}, +{NEGX_4030,{0U,0U,0U}}, +{NEGX_4030,{1U,0U,0U}}, +{NEGX_4030,{2U,0U,0U}}, +{NEGX_4030,{3U,0U,0U}}, +{NEGX_4030,{4U,0U,0U}}, +{NEGX_4030,{5U,0U,0U}}, +{NEGX_4030,{6U,0U,0U}}, +{NEGX_4030,{7U,0U,0U}}, +{NEGX_4038,{0U,0U,0U}}, +{NEGX_4039,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEGX_4040,{0U,0U,0U}}, +{NEGX_4040,{1U,0U,0U}}, +{NEGX_4040,{2U,0U,0U}}, +{NEGX_4040,{3U,0U,0U}}, +{NEGX_4040,{4U,0U,0U}}, +{NEGX_4040,{5U,0U,0U}}, +{NEGX_4040,{6U,0U,0U}}, +{NEGX_4040,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEGX_4050,{0U,0U,0U}}, +{NEGX_4050,{1U,0U,0U}}, +{NEGX_4050,{2U,0U,0U}}, +{NEGX_4050,{3U,0U,0U}}, +{NEGX_4050,{4U,0U,0U}}, +{NEGX_4050,{5U,0U,0U}}, +{NEGX_4050,{6U,0U,0U}}, +{NEGX_4050,{7U,0U,0U}}, +{NEGX_4058,{0U,0U,0U}}, +{NEGX_4058,{1U,0U,0U}}, +{NEGX_4058,{2U,0U,0U}}, +{NEGX_4058,{3U,0U,0U}}, +{NEGX_4058,{4U,0U,0U}}, +{NEGX_4058,{5U,0U,0U}}, +{NEGX_4058,{6U,0U,0U}}, +{NEGX_4058,{7U,0U,0U}}, +{NEGX_4060,{0U,0U,0U}}, +{NEGX_4060,{1U,0U,0U}}, +{NEGX_4060,{2U,0U,0U}}, +{NEGX_4060,{3U,0U,0U}}, +{NEGX_4060,{4U,0U,0U}}, +{NEGX_4060,{5U,0U,0U}}, +{NEGX_4060,{6U,0U,0U}}, +{NEGX_4060,{7U,0U,0U}}, +{NEGX_4068,{0U,0U,0U}}, +{NEGX_4068,{1U,0U,0U}}, +{NEGX_4068,{2U,0U,0U}}, +{NEGX_4068,{3U,0U,0U}}, +{NEGX_4068,{4U,0U,0U}}, +{NEGX_4068,{5U,0U,0U}}, +{NEGX_4068,{6U,0U,0U}}, +{NEGX_4068,{7U,0U,0U}}, +{NEGX_4070,{0U,0U,0U}}, +{NEGX_4070,{1U,0U,0U}}, +{NEGX_4070,{2U,0U,0U}}, +{NEGX_4070,{3U,0U,0U}}, +{NEGX_4070,{4U,0U,0U}}, +{NEGX_4070,{5U,0U,0U}}, +{NEGX_4070,{6U,0U,0U}}, +{NEGX_4070,{7U,0U,0U}}, +{NEGX_4078,{0U,0U,0U}}, +{NEGX_4079,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEGX_4080,{0U,0U,0U}}, +{NEGX_4080,{1U,0U,0U}}, +{NEGX_4080,{2U,0U,0U}}, +{NEGX_4080,{3U,0U,0U}}, +{NEGX_4080,{4U,0U,0U}}, +{NEGX_4080,{5U,0U,0U}}, +{NEGX_4080,{6U,0U,0U}}, +{NEGX_4080,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEGX_4090,{0U,0U,0U}}, +{NEGX_4090,{1U,0U,0U}}, +{NEGX_4090,{2U,0U,0U}}, +{NEGX_4090,{3U,0U,0U}}, +{NEGX_4090,{4U,0U,0U}}, +{NEGX_4090,{5U,0U,0U}}, +{NEGX_4090,{6U,0U,0U}}, +{NEGX_4090,{7U,0U,0U}}, +{NEGX_4098,{0U,0U,0U}}, +{NEGX_4098,{1U,0U,0U}}, +{NEGX_4098,{2U,0U,0U}}, +{NEGX_4098,{3U,0U,0U}}, +{NEGX_4098,{4U,0U,0U}}, +{NEGX_4098,{5U,0U,0U}}, +{NEGX_4098,{6U,0U,0U}}, +{NEGX_4098,{7U,0U,0U}}, +{NEGX_40A0,{0U,0U,0U}}, +{NEGX_40A0,{1U,0U,0U}}, +{NEGX_40A0,{2U,0U,0U}}, +{NEGX_40A0,{3U,0U,0U}}, +{NEGX_40A0,{4U,0U,0U}}, +{NEGX_40A0,{5U,0U,0U}}, +{NEGX_40A0,{6U,0U,0U}}, +{NEGX_40A0,{7U,0U,0U}}, +{NEGX_40A8,{0U,0U,0U}}, +{NEGX_40A8,{1U,0U,0U}}, +{NEGX_40A8,{2U,0U,0U}}, +{NEGX_40A8,{3U,0U,0U}}, +{NEGX_40A8,{4U,0U,0U}}, +{NEGX_40A8,{5U,0U,0U}}, +{NEGX_40A8,{6U,0U,0U}}, +{NEGX_40A8,{7U,0U,0U}}, +{NEGX_40B0,{0U,0U,0U}}, +{NEGX_40B0,{1U,0U,0U}}, +{NEGX_40B0,{2U,0U,0U}}, +{NEGX_40B0,{3U,0U,0U}}, +{NEGX_40B0,{4U,0U,0U}}, +{NEGX_40B0,{5U,0U,0U}}, +{NEGX_40B0,{6U,0U,0U}}, +{NEGX_40B0,{7U,0U,0U}}, +{NEGX_40B8,{0U,0U,0U}}, +{NEGX_40B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEFROMSR_40C0,{0U,0U,0U}}, +{MOVEFROMSR_40C0,{1U,0U,0U}}, +{MOVEFROMSR_40C0,{2U,0U,0U}}, +{MOVEFROMSR_40C0,{3U,0U,0U}}, +{MOVEFROMSR_40C0,{4U,0U,0U}}, +{MOVEFROMSR_40C0,{5U,0U,0U}}, +{MOVEFROMSR_40C0,{6U,0U,0U}}, +{MOVEFROMSR_40C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEFROMSR_40D0,{0U,0U,0U}}, +{MOVEFROMSR_40D0,{1U,0U,0U}}, +{MOVEFROMSR_40D0,{2U,0U,0U}}, +{MOVEFROMSR_40D0,{3U,0U,0U}}, +{MOVEFROMSR_40D0,{4U,0U,0U}}, +{MOVEFROMSR_40D0,{5U,0U,0U}}, +{MOVEFROMSR_40D0,{6U,0U,0U}}, +{MOVEFROMSR_40D0,{7U,0U,0U}}, +{MOVEFROMSR_40D8,{0U,0U,0U}}, +{MOVEFROMSR_40D8,{1U,0U,0U}}, +{MOVEFROMSR_40D8,{2U,0U,0U}}, +{MOVEFROMSR_40D8,{3U,0U,0U}}, +{MOVEFROMSR_40D8,{4U,0U,0U}}, +{MOVEFROMSR_40D8,{5U,0U,0U}}, +{MOVEFROMSR_40D8,{6U,0U,0U}}, +{MOVEFROMSR_40D8,{7U,0U,0U}}, +{MOVEFROMSR_40E0,{0U,0U,0U}}, +{MOVEFROMSR_40E0,{1U,0U,0U}}, +{MOVEFROMSR_40E0,{2U,0U,0U}}, +{MOVEFROMSR_40E0,{3U,0U,0U}}, +{MOVEFROMSR_40E0,{4U,0U,0U}}, +{MOVEFROMSR_40E0,{5U,0U,0U}}, +{MOVEFROMSR_40E0,{6U,0U,0U}}, +{MOVEFROMSR_40E0,{7U,0U,0U}}, +{MOVEFROMSR_40E8,{0U,0U,0U}}, +{MOVEFROMSR_40E8,{1U,0U,0U}}, +{MOVEFROMSR_40E8,{2U,0U,0U}}, +{MOVEFROMSR_40E8,{3U,0U,0U}}, +{MOVEFROMSR_40E8,{4U,0U,0U}}, +{MOVEFROMSR_40E8,{5U,0U,0U}}, +{MOVEFROMSR_40E8,{6U,0U,0U}}, +{MOVEFROMSR_40E8,{7U,0U,0U}}, +{MOVEFROMSR_40F0,{0U,0U,0U}}, +{MOVEFROMSR_40F0,{1U,0U,0U}}, +{MOVEFROMSR_40F0,{2U,0U,0U}}, +{MOVEFROMSR_40F0,{3U,0U,0U}}, +{MOVEFROMSR_40F0,{4U,0U,0U}}, +{MOVEFROMSR_40F0,{5U,0U,0U}}, +{MOVEFROMSR_40F0,{6U,0U,0U}}, +{MOVEFROMSR_40F0,{7U,0U,0U}}, +{MOVEFROMSR_40F8,{0U,0U,0U}}, +{MOVEFROMSR_40F9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4100,{0U,0U,0U}}, +{CHK_4100,{1U,0U,0U}}, +{CHK_4100,{2U,0U,0U}}, +{CHK_4100,{3U,0U,0U}}, +{CHK_4100,{4U,0U,0U}}, +{CHK_4100,{5U,0U,0U}}, +{CHK_4100,{6U,0U,0U}}, +{CHK_4100,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4110,{0U,0U,0U}}, +{CHK_4110,{1U,0U,0U}}, +{CHK_4110,{2U,0U,0U}}, +{CHK_4110,{3U,0U,0U}}, +{CHK_4110,{4U,0U,0U}}, +{CHK_4110,{5U,0U,0U}}, +{CHK_4110,{6U,0U,0U}}, +{CHK_4110,{7U,0U,0U}}, +{CHK_4118,{0U,0U,0U}}, +{CHK_4118,{1U,0U,0U}}, +{CHK_4118,{2U,0U,0U}}, +{CHK_4118,{3U,0U,0U}}, +{CHK_4118,{4U,0U,0U}}, +{CHK_4118,{5U,0U,0U}}, +{CHK_4118,{6U,0U,0U}}, +{CHK_4118,{7U,0U,0U}}, +{CHK_4120,{0U,0U,0U}}, +{CHK_4120,{1U,0U,0U}}, +{CHK_4120,{2U,0U,0U}}, +{CHK_4120,{3U,0U,0U}}, +{CHK_4120,{4U,0U,0U}}, +{CHK_4120,{5U,0U,0U}}, +{CHK_4120,{6U,0U,0U}}, +{CHK_4120,{7U,0U,0U}}, +{CHK_4128,{0U,0U,0U}}, +{CHK_4128,{1U,0U,0U}}, +{CHK_4128,{2U,0U,0U}}, +{CHK_4128,{3U,0U,0U}}, +{CHK_4128,{4U,0U,0U}}, +{CHK_4128,{5U,0U,0U}}, +{CHK_4128,{6U,0U,0U}}, +{CHK_4128,{7U,0U,0U}}, +{CHK_4130,{0U,0U,0U}}, +{CHK_4130,{1U,0U,0U}}, +{CHK_4130,{2U,0U,0U}}, +{CHK_4130,{3U,0U,0U}}, +{CHK_4130,{4U,0U,0U}}, +{CHK_4130,{5U,0U,0U}}, +{CHK_4130,{6U,0U,0U}}, +{CHK_4130,{7U,0U,0U}}, +{CHK_4138,{0U,0U,0U}}, +{CHK_4139,{0U,0U,0U}}, +{CHK_413A,{0U,0U,0U}}, +{CHK_413B,{0U,0U,0U}}, +{CHK_413C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4180,{0U,0U,0U}}, +{CHK_4180,{1U,0U,0U}}, +{CHK_4180,{2U,0U,0U}}, +{CHK_4180,{3U,0U,0U}}, +{CHK_4180,{4U,0U,0U}}, +{CHK_4180,{5U,0U,0U}}, +{CHK_4180,{6U,0U,0U}}, +{CHK_4180,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4190,{0U,0U,0U}}, +{CHK_4190,{1U,0U,0U}}, +{CHK_4190,{2U,0U,0U}}, +{CHK_4190,{3U,0U,0U}}, +{CHK_4190,{4U,0U,0U}}, +{CHK_4190,{5U,0U,0U}}, +{CHK_4190,{6U,0U,0U}}, +{CHK_4190,{7U,0U,0U}}, +{CHK_4198,{0U,0U,0U}}, +{CHK_4198,{1U,0U,0U}}, +{CHK_4198,{2U,0U,0U}}, +{CHK_4198,{3U,0U,0U}}, +{CHK_4198,{4U,0U,0U}}, +{CHK_4198,{5U,0U,0U}}, +{CHK_4198,{6U,0U,0U}}, +{CHK_4198,{7U,0U,0U}}, +{CHK_41A0,{0U,0U,0U}}, +{CHK_41A0,{1U,0U,0U}}, +{CHK_41A0,{2U,0U,0U}}, +{CHK_41A0,{3U,0U,0U}}, +{CHK_41A0,{4U,0U,0U}}, +{CHK_41A0,{5U,0U,0U}}, +{CHK_41A0,{6U,0U,0U}}, +{CHK_41A0,{7U,0U,0U}}, +{CHK_41A8,{0U,0U,0U}}, +{CHK_41A8,{1U,0U,0U}}, +{CHK_41A8,{2U,0U,0U}}, +{CHK_41A8,{3U,0U,0U}}, +{CHK_41A8,{4U,0U,0U}}, +{CHK_41A8,{5U,0U,0U}}, +{CHK_41A8,{6U,0U,0U}}, +{CHK_41A8,{7U,0U,0U}}, +{CHK_41B0,{0U,0U,0U}}, +{CHK_41B0,{1U,0U,0U}}, +{CHK_41B0,{2U,0U,0U}}, +{CHK_41B0,{3U,0U,0U}}, +{CHK_41B0,{4U,0U,0U}}, +{CHK_41B0,{5U,0U,0U}}, +{CHK_41B0,{6U,0U,0U}}, +{CHK_41B0,{7U,0U,0U}}, +{CHK_41B8,{0U,0U,0U}}, +{CHK_41B9,{0U,0U,0U}}, +{CHK_41BA,{0U,0U,0U}}, +{CHK_41BB,{0U,0U,0U}}, +{CHK_41BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41D0,{0U,0U,0U}}, +{LEA_41D0,{1U,0U,0U}}, +{LEA_41D0,{2U,0U,0U}}, +{LEA_41D0,{3U,0U,0U}}, +{LEA_41D0,{4U,0U,0U}}, +{LEA_41D0,{5U,0U,0U}}, +{LEA_41D0,{6U,0U,0U}}, +{LEA_41D0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41E8,{0U,0U,0U}}, +{LEA_41E8,{1U,0U,0U}}, +{LEA_41E8,{2U,0U,0U}}, +{LEA_41E8,{3U,0U,0U}}, +{LEA_41E8,{4U,0U,0U}}, +{LEA_41E8,{5U,0U,0U}}, +{LEA_41E8,{6U,0U,0U}}, +{LEA_41E8,{7U,0U,0U}}, +{LEA_41F0,{0U,0U,0U}}, +{LEA_41F0,{1U,0U,0U}}, +{LEA_41F0,{2U,0U,0U}}, +{LEA_41F0,{3U,0U,0U}}, +{LEA_41F0,{4U,0U,0U}}, +{LEA_41F0,{5U,0U,0U}}, +{LEA_41F0,{6U,0U,0U}}, +{LEA_41F0,{7U,0U,0U}}, +{LEA_41F8,{0U,0U,0U}}, +{LEA_41F9,{0U,0U,0U}}, +{LEA_41FA,{0U,0U,0U}}, +{LEA_41FB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CLR_4200,{0U,0U,0U}}, +{CLR_4200,{1U,0U,0U}}, +{CLR_4200,{2U,0U,0U}}, +{CLR_4200,{3U,0U,0U}}, +{CLR_4200,{4U,0U,0U}}, +{CLR_4200,{5U,0U,0U}}, +{CLR_4200,{6U,0U,0U}}, +{CLR_4200,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CLR_4210,{0U,0U,0U}}, +{CLR_4210,{1U,0U,0U}}, +{CLR_4210,{2U,0U,0U}}, +{CLR_4210,{3U,0U,0U}}, +{CLR_4210,{4U,0U,0U}}, +{CLR_4210,{5U,0U,0U}}, +{CLR_4210,{6U,0U,0U}}, +{CLR_4210,{7U,0U,0U}}, +{CLR_4218,{0U,0U,0U}}, +{CLR_4218,{1U,0U,0U}}, +{CLR_4218,{2U,0U,0U}}, +{CLR_4218,{3U,0U,0U}}, +{CLR_4218,{4U,0U,0U}}, +{CLR_4218,{5U,0U,0U}}, +{CLR_4218,{6U,0U,0U}}, +{CLR_4218,{7U,0U,0U}}, +{CLR_4220,{0U,0U,0U}}, +{CLR_4220,{1U,0U,0U}}, +{CLR_4220,{2U,0U,0U}}, +{CLR_4220,{3U,0U,0U}}, +{CLR_4220,{4U,0U,0U}}, +{CLR_4220,{5U,0U,0U}}, +{CLR_4220,{6U,0U,0U}}, +{CLR_4220,{7U,0U,0U}}, +{CLR_4228,{0U,0U,0U}}, +{CLR_4228,{1U,0U,0U}}, +{CLR_4228,{2U,0U,0U}}, +{CLR_4228,{3U,0U,0U}}, +{CLR_4228,{4U,0U,0U}}, +{CLR_4228,{5U,0U,0U}}, +{CLR_4228,{6U,0U,0U}}, +{CLR_4228,{7U,0U,0U}}, +{CLR_4230,{0U,0U,0U}}, +{CLR_4230,{1U,0U,0U}}, +{CLR_4230,{2U,0U,0U}}, +{CLR_4230,{3U,0U,0U}}, +{CLR_4230,{4U,0U,0U}}, +{CLR_4230,{5U,0U,0U}}, +{CLR_4230,{6U,0U,0U}}, +{CLR_4230,{7U,0U,0U}}, +{CLR_4238,{0U,0U,0U}}, +{CLR_4239,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CLR_4240,{0U,0U,0U}}, +{CLR_4240,{1U,0U,0U}}, +{CLR_4240,{2U,0U,0U}}, +{CLR_4240,{3U,0U,0U}}, +{CLR_4240,{4U,0U,0U}}, +{CLR_4240,{5U,0U,0U}}, +{CLR_4240,{6U,0U,0U}}, +{CLR_4240,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CLR_4250,{0U,0U,0U}}, +{CLR_4250,{1U,0U,0U}}, +{CLR_4250,{2U,0U,0U}}, +{CLR_4250,{3U,0U,0U}}, +{CLR_4250,{4U,0U,0U}}, +{CLR_4250,{5U,0U,0U}}, +{CLR_4250,{6U,0U,0U}}, +{CLR_4250,{7U,0U,0U}}, +{CLR_4258,{0U,0U,0U}}, +{CLR_4258,{1U,0U,0U}}, +{CLR_4258,{2U,0U,0U}}, +{CLR_4258,{3U,0U,0U}}, +{CLR_4258,{4U,0U,0U}}, +{CLR_4258,{5U,0U,0U}}, +{CLR_4258,{6U,0U,0U}}, +{CLR_4258,{7U,0U,0U}}, +{CLR_4260,{0U,0U,0U}}, +{CLR_4260,{1U,0U,0U}}, +{CLR_4260,{2U,0U,0U}}, +{CLR_4260,{3U,0U,0U}}, +{CLR_4260,{4U,0U,0U}}, +{CLR_4260,{5U,0U,0U}}, +{CLR_4260,{6U,0U,0U}}, +{CLR_4260,{7U,0U,0U}}, +{CLR_4268,{0U,0U,0U}}, +{CLR_4268,{1U,0U,0U}}, +{CLR_4268,{2U,0U,0U}}, +{CLR_4268,{3U,0U,0U}}, +{CLR_4268,{4U,0U,0U}}, +{CLR_4268,{5U,0U,0U}}, +{CLR_4268,{6U,0U,0U}}, +{CLR_4268,{7U,0U,0U}}, +{CLR_4270,{0U,0U,0U}}, +{CLR_4270,{1U,0U,0U}}, +{CLR_4270,{2U,0U,0U}}, +{CLR_4270,{3U,0U,0U}}, +{CLR_4270,{4U,0U,0U}}, +{CLR_4270,{5U,0U,0U}}, +{CLR_4270,{6U,0U,0U}}, +{CLR_4270,{7U,0U,0U}}, +{CLR_4278,{0U,0U,0U}}, +{CLR_4279,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CLR_4280,{0U,0U,0U}}, +{CLR_4280,{1U,0U,0U}}, +{CLR_4280,{2U,0U,0U}}, +{CLR_4280,{3U,0U,0U}}, +{CLR_4280,{4U,0U,0U}}, +{CLR_4280,{5U,0U,0U}}, +{CLR_4280,{6U,0U,0U}}, +{CLR_4280,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CLR_4290,{0U,0U,0U}}, +{CLR_4290,{1U,0U,0U}}, +{CLR_4290,{2U,0U,0U}}, +{CLR_4290,{3U,0U,0U}}, +{CLR_4290,{4U,0U,0U}}, +{CLR_4290,{5U,0U,0U}}, +{CLR_4290,{6U,0U,0U}}, +{CLR_4290,{7U,0U,0U}}, +{CLR_4298,{0U,0U,0U}}, +{CLR_4298,{1U,0U,0U}}, +{CLR_4298,{2U,0U,0U}}, +{CLR_4298,{3U,0U,0U}}, +{CLR_4298,{4U,0U,0U}}, +{CLR_4298,{5U,0U,0U}}, +{CLR_4298,{6U,0U,0U}}, +{CLR_4298,{7U,0U,0U}}, +{CLR_42A0,{0U,0U,0U}}, +{CLR_42A0,{1U,0U,0U}}, +{CLR_42A0,{2U,0U,0U}}, +{CLR_42A0,{3U,0U,0U}}, +{CLR_42A0,{4U,0U,0U}}, +{CLR_42A0,{5U,0U,0U}}, +{CLR_42A0,{6U,0U,0U}}, +{CLR_42A0,{7U,0U,0U}}, +{CLR_42A8,{0U,0U,0U}}, +{CLR_42A8,{1U,0U,0U}}, +{CLR_42A8,{2U,0U,0U}}, +{CLR_42A8,{3U,0U,0U}}, +{CLR_42A8,{4U,0U,0U}}, +{CLR_42A8,{5U,0U,0U}}, +{CLR_42A8,{6U,0U,0U}}, +{CLR_42A8,{7U,0U,0U}}, +{CLR_42B0,{0U,0U,0U}}, +{CLR_42B0,{1U,0U,0U}}, +{CLR_42B0,{2U,0U,0U}}, +{CLR_42B0,{3U,0U,0U}}, +{CLR_42B0,{4U,0U,0U}}, +{CLR_42B0,{5U,0U,0U}}, +{CLR_42B0,{6U,0U,0U}}, +{CLR_42B0,{7U,0U,0U}}, +{CLR_42B8,{0U,0U,0U}}, +{CLR_42B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEFROMCCR_42C0,{0U,0U,0U}}, +{MOVEFROMCCR_42C0,{1U,0U,0U}}, +{MOVEFROMCCR_42C0,{2U,0U,0U}}, +{MOVEFROMCCR_42C0,{3U,0U,0U}}, +{MOVEFROMCCR_42C0,{4U,0U,0U}}, +{MOVEFROMCCR_42C0,{5U,0U,0U}}, +{MOVEFROMCCR_42C0,{6U,0U,0U}}, +{MOVEFROMCCR_42C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEFROMCCR_42D0,{0U,0U,0U}}, +{MOVEFROMCCR_42D0,{1U,0U,0U}}, +{MOVEFROMCCR_42D0,{2U,0U,0U}}, +{MOVEFROMCCR_42D0,{3U,0U,0U}}, +{MOVEFROMCCR_42D0,{4U,0U,0U}}, +{MOVEFROMCCR_42D0,{5U,0U,0U}}, +{MOVEFROMCCR_42D0,{6U,0U,0U}}, +{MOVEFROMCCR_42D0,{7U,0U,0U}}, +{MOVEFROMCCR_42D8,{0U,0U,0U}}, +{MOVEFROMCCR_42D8,{1U,0U,0U}}, +{MOVEFROMCCR_42D8,{2U,0U,0U}}, +{MOVEFROMCCR_42D8,{3U,0U,0U}}, +{MOVEFROMCCR_42D8,{4U,0U,0U}}, +{MOVEFROMCCR_42D8,{5U,0U,0U}}, +{MOVEFROMCCR_42D8,{6U,0U,0U}}, +{MOVEFROMCCR_42D8,{7U,0U,0U}}, +{MOVEFROMCCR_42E0,{0U,0U,0U}}, +{MOVEFROMCCR_42E0,{1U,0U,0U}}, +{MOVEFROMCCR_42E0,{2U,0U,0U}}, +{MOVEFROMCCR_42E0,{3U,0U,0U}}, +{MOVEFROMCCR_42E0,{4U,0U,0U}}, +{MOVEFROMCCR_42E0,{5U,0U,0U}}, +{MOVEFROMCCR_42E0,{6U,0U,0U}}, +{MOVEFROMCCR_42E0,{7U,0U,0U}}, +{MOVEFROMCCR_42E8,{0U,0U,0U}}, +{MOVEFROMCCR_42E8,{1U,0U,0U}}, +{MOVEFROMCCR_42E8,{2U,0U,0U}}, +{MOVEFROMCCR_42E8,{3U,0U,0U}}, +{MOVEFROMCCR_42E8,{4U,0U,0U}}, +{MOVEFROMCCR_42E8,{5U,0U,0U}}, +{MOVEFROMCCR_42E8,{6U,0U,0U}}, +{MOVEFROMCCR_42E8,{7U,0U,0U}}, +{MOVEFROMCCR_42F0,{0U,0U,0U}}, +{MOVEFROMCCR_42F0,{1U,0U,0U}}, +{MOVEFROMCCR_42F0,{2U,0U,0U}}, +{MOVEFROMCCR_42F0,{3U,0U,0U}}, +{MOVEFROMCCR_42F0,{4U,0U,0U}}, +{MOVEFROMCCR_42F0,{5U,0U,0U}}, +{MOVEFROMCCR_42F0,{6U,0U,0U}}, +{MOVEFROMCCR_42F0,{7U,0U,0U}}, +{MOVEFROMCCR_42F8,{0U,0U,0U}}, +{MOVEFROMCCR_42F9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4100,{0U,1U,0U}}, +{CHK_4100,{1U,1U,0U}}, +{CHK_4100,{2U,1U,0U}}, +{CHK_4100,{3U,1U,0U}}, +{CHK_4100,{4U,1U,0U}}, +{CHK_4100,{5U,1U,0U}}, +{CHK_4100,{6U,1U,0U}}, +{CHK_4100,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4110,{0U,1U,0U}}, +{CHK_4110,{1U,1U,0U}}, +{CHK_4110,{2U,1U,0U}}, +{CHK_4110,{3U,1U,0U}}, +{CHK_4110,{4U,1U,0U}}, +{CHK_4110,{5U,1U,0U}}, +{CHK_4110,{6U,1U,0U}}, +{CHK_4110,{7U,1U,0U}}, +{CHK_4118,{0U,1U,0U}}, +{CHK_4118,{1U,1U,0U}}, +{CHK_4118,{2U,1U,0U}}, +{CHK_4118,{3U,1U,0U}}, +{CHK_4118,{4U,1U,0U}}, +{CHK_4118,{5U,1U,0U}}, +{CHK_4118,{6U,1U,0U}}, +{CHK_4118,{7U,1U,0U}}, +{CHK_4120,{0U,1U,0U}}, +{CHK_4120,{1U,1U,0U}}, +{CHK_4120,{2U,1U,0U}}, +{CHK_4120,{3U,1U,0U}}, +{CHK_4120,{4U,1U,0U}}, +{CHK_4120,{5U,1U,0U}}, +{CHK_4120,{6U,1U,0U}}, +{CHK_4120,{7U,1U,0U}}, +{CHK_4128,{0U,1U,0U}}, +{CHK_4128,{1U,1U,0U}}, +{CHK_4128,{2U,1U,0U}}, +{CHK_4128,{3U,1U,0U}}, +{CHK_4128,{4U,1U,0U}}, +{CHK_4128,{5U,1U,0U}}, +{CHK_4128,{6U,1U,0U}}, +{CHK_4128,{7U,1U,0U}}, +{CHK_4130,{0U,1U,0U}}, +{CHK_4130,{1U,1U,0U}}, +{CHK_4130,{2U,1U,0U}}, +{CHK_4130,{3U,1U,0U}}, +{CHK_4130,{4U,1U,0U}}, +{CHK_4130,{5U,1U,0U}}, +{CHK_4130,{6U,1U,0U}}, +{CHK_4130,{7U,1U,0U}}, +{CHK_4138,{0U,1U,0U}}, +{CHK_4139,{0U,1U,0U}}, +{CHK_413A,{0U,1U,0U}}, +{CHK_413B,{0U,1U,0U}}, +{CHK_413C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4180,{0U,1U,0U}}, +{CHK_4180,{1U,1U,0U}}, +{CHK_4180,{2U,1U,0U}}, +{CHK_4180,{3U,1U,0U}}, +{CHK_4180,{4U,1U,0U}}, +{CHK_4180,{5U,1U,0U}}, +{CHK_4180,{6U,1U,0U}}, +{CHK_4180,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4190,{0U,1U,0U}}, +{CHK_4190,{1U,1U,0U}}, +{CHK_4190,{2U,1U,0U}}, +{CHK_4190,{3U,1U,0U}}, +{CHK_4190,{4U,1U,0U}}, +{CHK_4190,{5U,1U,0U}}, +{CHK_4190,{6U,1U,0U}}, +{CHK_4190,{7U,1U,0U}}, +{CHK_4198,{0U,1U,0U}}, +{CHK_4198,{1U,1U,0U}}, +{CHK_4198,{2U,1U,0U}}, +{CHK_4198,{3U,1U,0U}}, +{CHK_4198,{4U,1U,0U}}, +{CHK_4198,{5U,1U,0U}}, +{CHK_4198,{6U,1U,0U}}, +{CHK_4198,{7U,1U,0U}}, +{CHK_41A0,{0U,1U,0U}}, +{CHK_41A0,{1U,1U,0U}}, +{CHK_41A0,{2U,1U,0U}}, +{CHK_41A0,{3U,1U,0U}}, +{CHK_41A0,{4U,1U,0U}}, +{CHK_41A0,{5U,1U,0U}}, +{CHK_41A0,{6U,1U,0U}}, +{CHK_41A0,{7U,1U,0U}}, +{CHK_41A8,{0U,1U,0U}}, +{CHK_41A8,{1U,1U,0U}}, +{CHK_41A8,{2U,1U,0U}}, +{CHK_41A8,{3U,1U,0U}}, +{CHK_41A8,{4U,1U,0U}}, +{CHK_41A8,{5U,1U,0U}}, +{CHK_41A8,{6U,1U,0U}}, +{CHK_41A8,{7U,1U,0U}}, +{CHK_41B0,{0U,1U,0U}}, +{CHK_41B0,{1U,1U,0U}}, +{CHK_41B0,{2U,1U,0U}}, +{CHK_41B0,{3U,1U,0U}}, +{CHK_41B0,{4U,1U,0U}}, +{CHK_41B0,{5U,1U,0U}}, +{CHK_41B0,{6U,1U,0U}}, +{CHK_41B0,{7U,1U,0U}}, +{CHK_41B8,{0U,1U,0U}}, +{CHK_41B9,{0U,1U,0U}}, +{CHK_41BA,{0U,1U,0U}}, +{CHK_41BB,{0U,1U,0U}}, +{CHK_41BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41D0,{0U,1U,0U}}, +{LEA_41D0,{1U,1U,0U}}, +{LEA_41D0,{2U,1U,0U}}, +{LEA_41D0,{3U,1U,0U}}, +{LEA_41D0,{4U,1U,0U}}, +{LEA_41D0,{5U,1U,0U}}, +{LEA_41D0,{6U,1U,0U}}, +{LEA_41D0,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41E8,{0U,1U,0U}}, +{LEA_41E8,{1U,1U,0U}}, +{LEA_41E8,{2U,1U,0U}}, +{LEA_41E8,{3U,1U,0U}}, +{LEA_41E8,{4U,1U,0U}}, +{LEA_41E8,{5U,1U,0U}}, +{LEA_41E8,{6U,1U,0U}}, +{LEA_41E8,{7U,1U,0U}}, +{LEA_41F0,{0U,1U,0U}}, +{LEA_41F0,{1U,1U,0U}}, +{LEA_41F0,{2U,1U,0U}}, +{LEA_41F0,{3U,1U,0U}}, +{LEA_41F0,{4U,1U,0U}}, +{LEA_41F0,{5U,1U,0U}}, +{LEA_41F0,{6U,1U,0U}}, +{LEA_41F0,{7U,1U,0U}}, +{LEA_41F8,{0U,1U,0U}}, +{LEA_41F9,{0U,1U,0U}}, +{LEA_41FA,{0U,1U,0U}}, +{LEA_41FB,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEG_4400,{0U,0U,0U}}, +{NEG_4400,{1U,0U,0U}}, +{NEG_4400,{2U,0U,0U}}, +{NEG_4400,{3U,0U,0U}}, +{NEG_4400,{4U,0U,0U}}, +{NEG_4400,{5U,0U,0U}}, +{NEG_4400,{6U,0U,0U}}, +{NEG_4400,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEG_4410,{0U,0U,0U}}, +{NEG_4410,{1U,0U,0U}}, +{NEG_4410,{2U,0U,0U}}, +{NEG_4410,{3U,0U,0U}}, +{NEG_4410,{4U,0U,0U}}, +{NEG_4410,{5U,0U,0U}}, +{NEG_4410,{6U,0U,0U}}, +{NEG_4410,{7U,0U,0U}}, +{NEG_4418,{0U,0U,0U}}, +{NEG_4418,{1U,0U,0U}}, +{NEG_4418,{2U,0U,0U}}, +{NEG_4418,{3U,0U,0U}}, +{NEG_4418,{4U,0U,0U}}, +{NEG_4418,{5U,0U,0U}}, +{NEG_4418,{6U,0U,0U}}, +{NEG_4418,{7U,0U,0U}}, +{NEG_4420,{0U,0U,0U}}, +{NEG_4420,{1U,0U,0U}}, +{NEG_4420,{2U,0U,0U}}, +{NEG_4420,{3U,0U,0U}}, +{NEG_4420,{4U,0U,0U}}, +{NEG_4420,{5U,0U,0U}}, +{NEG_4420,{6U,0U,0U}}, +{NEG_4420,{7U,0U,0U}}, +{NEG_4428,{0U,0U,0U}}, +{NEG_4428,{1U,0U,0U}}, +{NEG_4428,{2U,0U,0U}}, +{NEG_4428,{3U,0U,0U}}, +{NEG_4428,{4U,0U,0U}}, +{NEG_4428,{5U,0U,0U}}, +{NEG_4428,{6U,0U,0U}}, +{NEG_4428,{7U,0U,0U}}, +{NEG_4430,{0U,0U,0U}}, +{NEG_4430,{1U,0U,0U}}, +{NEG_4430,{2U,0U,0U}}, +{NEG_4430,{3U,0U,0U}}, +{NEG_4430,{4U,0U,0U}}, +{NEG_4430,{5U,0U,0U}}, +{NEG_4430,{6U,0U,0U}}, +{NEG_4430,{7U,0U,0U}}, +{NEG_4438,{0U,0U,0U}}, +{NEG_4439,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEG_4440,{0U,0U,0U}}, +{NEG_4440,{1U,0U,0U}}, +{NEG_4440,{2U,0U,0U}}, +{NEG_4440,{3U,0U,0U}}, +{NEG_4440,{4U,0U,0U}}, +{NEG_4440,{5U,0U,0U}}, +{NEG_4440,{6U,0U,0U}}, +{NEG_4440,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEG_4450,{0U,0U,0U}}, +{NEG_4450,{1U,0U,0U}}, +{NEG_4450,{2U,0U,0U}}, +{NEG_4450,{3U,0U,0U}}, +{NEG_4450,{4U,0U,0U}}, +{NEG_4450,{5U,0U,0U}}, +{NEG_4450,{6U,0U,0U}}, +{NEG_4450,{7U,0U,0U}}, +{NEG_4458,{0U,0U,0U}}, +{NEG_4458,{1U,0U,0U}}, +{NEG_4458,{2U,0U,0U}}, +{NEG_4458,{3U,0U,0U}}, +{NEG_4458,{4U,0U,0U}}, +{NEG_4458,{5U,0U,0U}}, +{NEG_4458,{6U,0U,0U}}, +{NEG_4458,{7U,0U,0U}}, +{NEG_4460,{0U,0U,0U}}, +{NEG_4460,{1U,0U,0U}}, +{NEG_4460,{2U,0U,0U}}, +{NEG_4460,{3U,0U,0U}}, +{NEG_4460,{4U,0U,0U}}, +{NEG_4460,{5U,0U,0U}}, +{NEG_4460,{6U,0U,0U}}, +{NEG_4460,{7U,0U,0U}}, +{NEG_4468,{0U,0U,0U}}, +{NEG_4468,{1U,0U,0U}}, +{NEG_4468,{2U,0U,0U}}, +{NEG_4468,{3U,0U,0U}}, +{NEG_4468,{4U,0U,0U}}, +{NEG_4468,{5U,0U,0U}}, +{NEG_4468,{6U,0U,0U}}, +{NEG_4468,{7U,0U,0U}}, +{NEG_4470,{0U,0U,0U}}, +{NEG_4470,{1U,0U,0U}}, +{NEG_4470,{2U,0U,0U}}, +{NEG_4470,{3U,0U,0U}}, +{NEG_4470,{4U,0U,0U}}, +{NEG_4470,{5U,0U,0U}}, +{NEG_4470,{6U,0U,0U}}, +{NEG_4470,{7U,0U,0U}}, +{NEG_4478,{0U,0U,0U}}, +{NEG_4479,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEG_4480,{0U,0U,0U}}, +{NEG_4480,{1U,0U,0U}}, +{NEG_4480,{2U,0U,0U}}, +{NEG_4480,{3U,0U,0U}}, +{NEG_4480,{4U,0U,0U}}, +{NEG_4480,{5U,0U,0U}}, +{NEG_4480,{6U,0U,0U}}, +{NEG_4480,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NEG_4490,{0U,0U,0U}}, +{NEG_4490,{1U,0U,0U}}, +{NEG_4490,{2U,0U,0U}}, +{NEG_4490,{3U,0U,0U}}, +{NEG_4490,{4U,0U,0U}}, +{NEG_4490,{5U,0U,0U}}, +{NEG_4490,{6U,0U,0U}}, +{NEG_4490,{7U,0U,0U}}, +{NEG_4498,{0U,0U,0U}}, +{NEG_4498,{1U,0U,0U}}, +{NEG_4498,{2U,0U,0U}}, +{NEG_4498,{3U,0U,0U}}, +{NEG_4498,{4U,0U,0U}}, +{NEG_4498,{5U,0U,0U}}, +{NEG_4498,{6U,0U,0U}}, +{NEG_4498,{7U,0U,0U}}, +{NEG_44A0,{0U,0U,0U}}, +{NEG_44A0,{1U,0U,0U}}, +{NEG_44A0,{2U,0U,0U}}, +{NEG_44A0,{3U,0U,0U}}, +{NEG_44A0,{4U,0U,0U}}, +{NEG_44A0,{5U,0U,0U}}, +{NEG_44A0,{6U,0U,0U}}, +{NEG_44A0,{7U,0U,0U}}, +{NEG_44A8,{0U,0U,0U}}, +{NEG_44A8,{1U,0U,0U}}, +{NEG_44A8,{2U,0U,0U}}, +{NEG_44A8,{3U,0U,0U}}, +{NEG_44A8,{4U,0U,0U}}, +{NEG_44A8,{5U,0U,0U}}, +{NEG_44A8,{6U,0U,0U}}, +{NEG_44A8,{7U,0U,0U}}, +{NEG_44B0,{0U,0U,0U}}, +{NEG_44B0,{1U,0U,0U}}, +{NEG_44B0,{2U,0U,0U}}, +{NEG_44B0,{3U,0U,0U}}, +{NEG_44B0,{4U,0U,0U}}, +{NEG_44B0,{5U,0U,0U}}, +{NEG_44B0,{6U,0U,0U}}, +{NEG_44B0,{7U,0U,0U}}, +{NEG_44B8,{0U,0U,0U}}, +{NEG_44B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVETOCCR_44C0,{0U,0U,0U}}, +{MOVETOCCR_44C0,{1U,0U,0U}}, +{MOVETOCCR_44C0,{2U,0U,0U}}, +{MOVETOCCR_44C0,{3U,0U,0U}}, +{MOVETOCCR_44C0,{4U,0U,0U}}, +{MOVETOCCR_44C0,{5U,0U,0U}}, +{MOVETOCCR_44C0,{6U,0U,0U}}, +{MOVETOCCR_44C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVETOCCR_44D0,{0U,0U,0U}}, +{MOVETOCCR_44D0,{1U,0U,0U}}, +{MOVETOCCR_44D0,{2U,0U,0U}}, +{MOVETOCCR_44D0,{3U,0U,0U}}, +{MOVETOCCR_44D0,{4U,0U,0U}}, +{MOVETOCCR_44D0,{5U,0U,0U}}, +{MOVETOCCR_44D0,{6U,0U,0U}}, +{MOVETOCCR_44D0,{7U,0U,0U}}, +{MOVETOCCR_44D8,{0U,0U,0U}}, +{MOVETOCCR_44D8,{1U,0U,0U}}, +{MOVETOCCR_44D8,{2U,0U,0U}}, +{MOVETOCCR_44D8,{3U,0U,0U}}, +{MOVETOCCR_44D8,{4U,0U,0U}}, +{MOVETOCCR_44D8,{5U,0U,0U}}, +{MOVETOCCR_44D8,{6U,0U,0U}}, +{MOVETOCCR_44D8,{7U,0U,0U}}, +{MOVETOCCR_44E0,{0U,0U,0U}}, +{MOVETOCCR_44E0,{1U,0U,0U}}, +{MOVETOCCR_44E0,{2U,0U,0U}}, +{MOVETOCCR_44E0,{3U,0U,0U}}, +{MOVETOCCR_44E0,{4U,0U,0U}}, +{MOVETOCCR_44E0,{5U,0U,0U}}, +{MOVETOCCR_44E0,{6U,0U,0U}}, +{MOVETOCCR_44E0,{7U,0U,0U}}, +{MOVETOCCR_44E8,{0U,0U,0U}}, +{MOVETOCCR_44E8,{1U,0U,0U}}, +{MOVETOCCR_44E8,{2U,0U,0U}}, +{MOVETOCCR_44E8,{3U,0U,0U}}, +{MOVETOCCR_44E8,{4U,0U,0U}}, +{MOVETOCCR_44E8,{5U,0U,0U}}, +{MOVETOCCR_44E8,{6U,0U,0U}}, +{MOVETOCCR_44E8,{7U,0U,0U}}, +{MOVETOCCR_44F0,{0U,0U,0U}}, +{MOVETOCCR_44F0,{1U,0U,0U}}, +{MOVETOCCR_44F0,{2U,0U,0U}}, +{MOVETOCCR_44F0,{3U,0U,0U}}, +{MOVETOCCR_44F0,{4U,0U,0U}}, +{MOVETOCCR_44F0,{5U,0U,0U}}, +{MOVETOCCR_44F0,{6U,0U,0U}}, +{MOVETOCCR_44F0,{7U,0U,0U}}, +{MOVETOCCR_44F8,{0U,0U,0U}}, +{MOVETOCCR_44F9,{0U,0U,0U}}, +{MOVETOCCR_44FA,{0U,0U,0U}}, +{MOVETOCCR_44FB,{0U,0U,0U}}, +{MOVETOCCR_44FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4100,{0U,2U,0U}}, +{CHK_4100,{1U,2U,0U}}, +{CHK_4100,{2U,2U,0U}}, +{CHK_4100,{3U,2U,0U}}, +{CHK_4100,{4U,2U,0U}}, +{CHK_4100,{5U,2U,0U}}, +{CHK_4100,{6U,2U,0U}}, +{CHK_4100,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4110,{0U,2U,0U}}, +{CHK_4110,{1U,2U,0U}}, +{CHK_4110,{2U,2U,0U}}, +{CHK_4110,{3U,2U,0U}}, +{CHK_4110,{4U,2U,0U}}, +{CHK_4110,{5U,2U,0U}}, +{CHK_4110,{6U,2U,0U}}, +{CHK_4110,{7U,2U,0U}}, +{CHK_4118,{0U,2U,0U}}, +{CHK_4118,{1U,2U,0U}}, +{CHK_4118,{2U,2U,0U}}, +{CHK_4118,{3U,2U,0U}}, +{CHK_4118,{4U,2U,0U}}, +{CHK_4118,{5U,2U,0U}}, +{CHK_4118,{6U,2U,0U}}, +{CHK_4118,{7U,2U,0U}}, +{CHK_4120,{0U,2U,0U}}, +{CHK_4120,{1U,2U,0U}}, +{CHK_4120,{2U,2U,0U}}, +{CHK_4120,{3U,2U,0U}}, +{CHK_4120,{4U,2U,0U}}, +{CHK_4120,{5U,2U,0U}}, +{CHK_4120,{6U,2U,0U}}, +{CHK_4120,{7U,2U,0U}}, +{CHK_4128,{0U,2U,0U}}, +{CHK_4128,{1U,2U,0U}}, +{CHK_4128,{2U,2U,0U}}, +{CHK_4128,{3U,2U,0U}}, +{CHK_4128,{4U,2U,0U}}, +{CHK_4128,{5U,2U,0U}}, +{CHK_4128,{6U,2U,0U}}, +{CHK_4128,{7U,2U,0U}}, +{CHK_4130,{0U,2U,0U}}, +{CHK_4130,{1U,2U,0U}}, +{CHK_4130,{2U,2U,0U}}, +{CHK_4130,{3U,2U,0U}}, +{CHK_4130,{4U,2U,0U}}, +{CHK_4130,{5U,2U,0U}}, +{CHK_4130,{6U,2U,0U}}, +{CHK_4130,{7U,2U,0U}}, +{CHK_4138,{0U,2U,0U}}, +{CHK_4139,{0U,2U,0U}}, +{CHK_413A,{0U,2U,0U}}, +{CHK_413B,{0U,2U,0U}}, +{CHK_413C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4180,{0U,2U,0U}}, +{CHK_4180,{1U,2U,0U}}, +{CHK_4180,{2U,2U,0U}}, +{CHK_4180,{3U,2U,0U}}, +{CHK_4180,{4U,2U,0U}}, +{CHK_4180,{5U,2U,0U}}, +{CHK_4180,{6U,2U,0U}}, +{CHK_4180,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4190,{0U,2U,0U}}, +{CHK_4190,{1U,2U,0U}}, +{CHK_4190,{2U,2U,0U}}, +{CHK_4190,{3U,2U,0U}}, +{CHK_4190,{4U,2U,0U}}, +{CHK_4190,{5U,2U,0U}}, +{CHK_4190,{6U,2U,0U}}, +{CHK_4190,{7U,2U,0U}}, +{CHK_4198,{0U,2U,0U}}, +{CHK_4198,{1U,2U,0U}}, +{CHK_4198,{2U,2U,0U}}, +{CHK_4198,{3U,2U,0U}}, +{CHK_4198,{4U,2U,0U}}, +{CHK_4198,{5U,2U,0U}}, +{CHK_4198,{6U,2U,0U}}, +{CHK_4198,{7U,2U,0U}}, +{CHK_41A0,{0U,2U,0U}}, +{CHK_41A0,{1U,2U,0U}}, +{CHK_41A0,{2U,2U,0U}}, +{CHK_41A0,{3U,2U,0U}}, +{CHK_41A0,{4U,2U,0U}}, +{CHK_41A0,{5U,2U,0U}}, +{CHK_41A0,{6U,2U,0U}}, +{CHK_41A0,{7U,2U,0U}}, +{CHK_41A8,{0U,2U,0U}}, +{CHK_41A8,{1U,2U,0U}}, +{CHK_41A8,{2U,2U,0U}}, +{CHK_41A8,{3U,2U,0U}}, +{CHK_41A8,{4U,2U,0U}}, +{CHK_41A8,{5U,2U,0U}}, +{CHK_41A8,{6U,2U,0U}}, +{CHK_41A8,{7U,2U,0U}}, +{CHK_41B0,{0U,2U,0U}}, +{CHK_41B0,{1U,2U,0U}}, +{CHK_41B0,{2U,2U,0U}}, +{CHK_41B0,{3U,2U,0U}}, +{CHK_41B0,{4U,2U,0U}}, +{CHK_41B0,{5U,2U,0U}}, +{CHK_41B0,{6U,2U,0U}}, +{CHK_41B0,{7U,2U,0U}}, +{CHK_41B8,{0U,2U,0U}}, +{CHK_41B9,{0U,2U,0U}}, +{CHK_41BA,{0U,2U,0U}}, +{CHK_41BB,{0U,2U,0U}}, +{CHK_41BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41D0,{0U,2U,0U}}, +{LEA_41D0,{1U,2U,0U}}, +{LEA_41D0,{2U,2U,0U}}, +{LEA_41D0,{3U,2U,0U}}, +{LEA_41D0,{4U,2U,0U}}, +{LEA_41D0,{5U,2U,0U}}, +{LEA_41D0,{6U,2U,0U}}, +{LEA_41D0,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41E8,{0U,2U,0U}}, +{LEA_41E8,{1U,2U,0U}}, +{LEA_41E8,{2U,2U,0U}}, +{LEA_41E8,{3U,2U,0U}}, +{LEA_41E8,{4U,2U,0U}}, +{LEA_41E8,{5U,2U,0U}}, +{LEA_41E8,{6U,2U,0U}}, +{LEA_41E8,{7U,2U,0U}}, +{LEA_41F0,{0U,2U,0U}}, +{LEA_41F0,{1U,2U,0U}}, +{LEA_41F0,{2U,2U,0U}}, +{LEA_41F0,{3U,2U,0U}}, +{LEA_41F0,{4U,2U,0U}}, +{LEA_41F0,{5U,2U,0U}}, +{LEA_41F0,{6U,2U,0U}}, +{LEA_41F0,{7U,2U,0U}}, +{LEA_41F8,{0U,2U,0U}}, +{LEA_41F9,{0U,2U,0U}}, +{LEA_41FA,{0U,2U,0U}}, +{LEA_41FB,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NOT_4600,{0U,0U,0U}}, +{NOT_4600,{1U,0U,0U}}, +{NOT_4600,{2U,0U,0U}}, +{NOT_4600,{3U,0U,0U}}, +{NOT_4600,{4U,0U,0U}}, +{NOT_4600,{5U,0U,0U}}, +{NOT_4600,{6U,0U,0U}}, +{NOT_4600,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NOT_4610,{0U,0U,0U}}, +{NOT_4610,{1U,0U,0U}}, +{NOT_4610,{2U,0U,0U}}, +{NOT_4610,{3U,0U,0U}}, +{NOT_4610,{4U,0U,0U}}, +{NOT_4610,{5U,0U,0U}}, +{NOT_4610,{6U,0U,0U}}, +{NOT_4610,{7U,0U,0U}}, +{NOT_4618,{0U,0U,0U}}, +{NOT_4618,{1U,0U,0U}}, +{NOT_4618,{2U,0U,0U}}, +{NOT_4618,{3U,0U,0U}}, +{NOT_4618,{4U,0U,0U}}, +{NOT_4618,{5U,0U,0U}}, +{NOT_4618,{6U,0U,0U}}, +{NOT_4618,{7U,0U,0U}}, +{NOT_4620,{0U,0U,0U}}, +{NOT_4620,{1U,0U,0U}}, +{NOT_4620,{2U,0U,0U}}, +{NOT_4620,{3U,0U,0U}}, +{NOT_4620,{4U,0U,0U}}, +{NOT_4620,{5U,0U,0U}}, +{NOT_4620,{6U,0U,0U}}, +{NOT_4620,{7U,0U,0U}}, +{NOT_4628,{0U,0U,0U}}, +{NOT_4628,{1U,0U,0U}}, +{NOT_4628,{2U,0U,0U}}, +{NOT_4628,{3U,0U,0U}}, +{NOT_4628,{4U,0U,0U}}, +{NOT_4628,{5U,0U,0U}}, +{NOT_4628,{6U,0U,0U}}, +{NOT_4628,{7U,0U,0U}}, +{NOT_4630,{0U,0U,0U}}, +{NOT_4630,{1U,0U,0U}}, +{NOT_4630,{2U,0U,0U}}, +{NOT_4630,{3U,0U,0U}}, +{NOT_4630,{4U,0U,0U}}, +{NOT_4630,{5U,0U,0U}}, +{NOT_4630,{6U,0U,0U}}, +{NOT_4630,{7U,0U,0U}}, +{NOT_4638,{0U,0U,0U}}, +{NOT_4639,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NOT_4640,{0U,0U,0U}}, +{NOT_4640,{1U,0U,0U}}, +{NOT_4640,{2U,0U,0U}}, +{NOT_4640,{3U,0U,0U}}, +{NOT_4640,{4U,0U,0U}}, +{NOT_4640,{5U,0U,0U}}, +{NOT_4640,{6U,0U,0U}}, +{NOT_4640,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NOT_4650,{0U,0U,0U}}, +{NOT_4650,{1U,0U,0U}}, +{NOT_4650,{2U,0U,0U}}, +{NOT_4650,{3U,0U,0U}}, +{NOT_4650,{4U,0U,0U}}, +{NOT_4650,{5U,0U,0U}}, +{NOT_4650,{6U,0U,0U}}, +{NOT_4650,{7U,0U,0U}}, +{NOT_4658,{0U,0U,0U}}, +{NOT_4658,{1U,0U,0U}}, +{NOT_4658,{2U,0U,0U}}, +{NOT_4658,{3U,0U,0U}}, +{NOT_4658,{4U,0U,0U}}, +{NOT_4658,{5U,0U,0U}}, +{NOT_4658,{6U,0U,0U}}, +{NOT_4658,{7U,0U,0U}}, +{NOT_4660,{0U,0U,0U}}, +{NOT_4660,{1U,0U,0U}}, +{NOT_4660,{2U,0U,0U}}, +{NOT_4660,{3U,0U,0U}}, +{NOT_4660,{4U,0U,0U}}, +{NOT_4660,{5U,0U,0U}}, +{NOT_4660,{6U,0U,0U}}, +{NOT_4660,{7U,0U,0U}}, +{NOT_4668,{0U,0U,0U}}, +{NOT_4668,{1U,0U,0U}}, +{NOT_4668,{2U,0U,0U}}, +{NOT_4668,{3U,0U,0U}}, +{NOT_4668,{4U,0U,0U}}, +{NOT_4668,{5U,0U,0U}}, +{NOT_4668,{6U,0U,0U}}, +{NOT_4668,{7U,0U,0U}}, +{NOT_4670,{0U,0U,0U}}, +{NOT_4670,{1U,0U,0U}}, +{NOT_4670,{2U,0U,0U}}, +{NOT_4670,{3U,0U,0U}}, +{NOT_4670,{4U,0U,0U}}, +{NOT_4670,{5U,0U,0U}}, +{NOT_4670,{6U,0U,0U}}, +{NOT_4670,{7U,0U,0U}}, +{NOT_4678,{0U,0U,0U}}, +{NOT_4679,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NOT_4680,{0U,0U,0U}}, +{NOT_4680,{1U,0U,0U}}, +{NOT_4680,{2U,0U,0U}}, +{NOT_4680,{3U,0U,0U}}, +{NOT_4680,{4U,0U,0U}}, +{NOT_4680,{5U,0U,0U}}, +{NOT_4680,{6U,0U,0U}}, +{NOT_4680,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NOT_4690,{0U,0U,0U}}, +{NOT_4690,{1U,0U,0U}}, +{NOT_4690,{2U,0U,0U}}, +{NOT_4690,{3U,0U,0U}}, +{NOT_4690,{4U,0U,0U}}, +{NOT_4690,{5U,0U,0U}}, +{NOT_4690,{6U,0U,0U}}, +{NOT_4690,{7U,0U,0U}}, +{NOT_4698,{0U,0U,0U}}, +{NOT_4698,{1U,0U,0U}}, +{NOT_4698,{2U,0U,0U}}, +{NOT_4698,{3U,0U,0U}}, +{NOT_4698,{4U,0U,0U}}, +{NOT_4698,{5U,0U,0U}}, +{NOT_4698,{6U,0U,0U}}, +{NOT_4698,{7U,0U,0U}}, +{NOT_46A0,{0U,0U,0U}}, +{NOT_46A0,{1U,0U,0U}}, +{NOT_46A0,{2U,0U,0U}}, +{NOT_46A0,{3U,0U,0U}}, +{NOT_46A0,{4U,0U,0U}}, +{NOT_46A0,{5U,0U,0U}}, +{NOT_46A0,{6U,0U,0U}}, +{NOT_46A0,{7U,0U,0U}}, +{NOT_46A8,{0U,0U,0U}}, +{NOT_46A8,{1U,0U,0U}}, +{NOT_46A8,{2U,0U,0U}}, +{NOT_46A8,{3U,0U,0U}}, +{NOT_46A8,{4U,0U,0U}}, +{NOT_46A8,{5U,0U,0U}}, +{NOT_46A8,{6U,0U,0U}}, +{NOT_46A8,{7U,0U,0U}}, +{NOT_46B0,{0U,0U,0U}}, +{NOT_46B0,{1U,0U,0U}}, +{NOT_46B0,{2U,0U,0U}}, +{NOT_46B0,{3U,0U,0U}}, +{NOT_46B0,{4U,0U,0U}}, +{NOT_46B0,{5U,0U,0U}}, +{NOT_46B0,{6U,0U,0U}}, +{NOT_46B0,{7U,0U,0U}}, +{NOT_46B8,{0U,0U,0U}}, +{NOT_46B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVETOSR_46C0,{0U,0U,0U}}, +{MOVETOSR_46C0,{1U,0U,0U}}, +{MOVETOSR_46C0,{2U,0U,0U}}, +{MOVETOSR_46C0,{3U,0U,0U}}, +{MOVETOSR_46C0,{4U,0U,0U}}, +{MOVETOSR_46C0,{5U,0U,0U}}, +{MOVETOSR_46C0,{6U,0U,0U}}, +{MOVETOSR_46C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVETOSR_46D0,{0U,0U,0U}}, +{MOVETOSR_46D0,{1U,0U,0U}}, +{MOVETOSR_46D0,{2U,0U,0U}}, +{MOVETOSR_46D0,{3U,0U,0U}}, +{MOVETOSR_46D0,{4U,0U,0U}}, +{MOVETOSR_46D0,{5U,0U,0U}}, +{MOVETOSR_46D0,{6U,0U,0U}}, +{MOVETOSR_46D0,{7U,0U,0U}}, +{MOVETOSR_46D8,{0U,0U,0U}}, +{MOVETOSR_46D8,{1U,0U,0U}}, +{MOVETOSR_46D8,{2U,0U,0U}}, +{MOVETOSR_46D8,{3U,0U,0U}}, +{MOVETOSR_46D8,{4U,0U,0U}}, +{MOVETOSR_46D8,{5U,0U,0U}}, +{MOVETOSR_46D8,{6U,0U,0U}}, +{MOVETOSR_46D8,{7U,0U,0U}}, +{MOVETOSR_46E0,{0U,0U,0U}}, +{MOVETOSR_46E0,{1U,0U,0U}}, +{MOVETOSR_46E0,{2U,0U,0U}}, +{MOVETOSR_46E0,{3U,0U,0U}}, +{MOVETOSR_46E0,{4U,0U,0U}}, +{MOVETOSR_46E0,{5U,0U,0U}}, +{MOVETOSR_46E0,{6U,0U,0U}}, +{MOVETOSR_46E0,{7U,0U,0U}}, +{MOVETOSR_46E8,{0U,0U,0U}}, +{MOVETOSR_46E8,{1U,0U,0U}}, +{MOVETOSR_46E8,{2U,0U,0U}}, +{MOVETOSR_46E8,{3U,0U,0U}}, +{MOVETOSR_46E8,{4U,0U,0U}}, +{MOVETOSR_46E8,{5U,0U,0U}}, +{MOVETOSR_46E8,{6U,0U,0U}}, +{MOVETOSR_46E8,{7U,0U,0U}}, +{MOVETOSR_46F0,{0U,0U,0U}}, +{MOVETOSR_46F0,{1U,0U,0U}}, +{MOVETOSR_46F0,{2U,0U,0U}}, +{MOVETOSR_46F0,{3U,0U,0U}}, +{MOVETOSR_46F0,{4U,0U,0U}}, +{MOVETOSR_46F0,{5U,0U,0U}}, +{MOVETOSR_46F0,{6U,0U,0U}}, +{MOVETOSR_46F0,{7U,0U,0U}}, +{MOVETOSR_46F8,{0U,0U,0U}}, +{MOVETOSR_46F9,{0U,0U,0U}}, +{MOVETOSR_46FA,{0U,0U,0U}}, +{MOVETOSR_46FB,{0U,0U,0U}}, +{MOVETOSR_46FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4100,{0U,3U,0U}}, +{CHK_4100,{1U,3U,0U}}, +{CHK_4100,{2U,3U,0U}}, +{CHK_4100,{3U,3U,0U}}, +{CHK_4100,{4U,3U,0U}}, +{CHK_4100,{5U,3U,0U}}, +{CHK_4100,{6U,3U,0U}}, +{CHK_4100,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4110,{0U,3U,0U}}, +{CHK_4110,{1U,3U,0U}}, +{CHK_4110,{2U,3U,0U}}, +{CHK_4110,{3U,3U,0U}}, +{CHK_4110,{4U,3U,0U}}, +{CHK_4110,{5U,3U,0U}}, +{CHK_4110,{6U,3U,0U}}, +{CHK_4110,{7U,3U,0U}}, +{CHK_4118,{0U,3U,0U}}, +{CHK_4118,{1U,3U,0U}}, +{CHK_4118,{2U,3U,0U}}, +{CHK_4118,{3U,3U,0U}}, +{CHK_4118,{4U,3U,0U}}, +{CHK_4118,{5U,3U,0U}}, +{CHK_4118,{6U,3U,0U}}, +{CHK_4118,{7U,3U,0U}}, +{CHK_4120,{0U,3U,0U}}, +{CHK_4120,{1U,3U,0U}}, +{CHK_4120,{2U,3U,0U}}, +{CHK_4120,{3U,3U,0U}}, +{CHK_4120,{4U,3U,0U}}, +{CHK_4120,{5U,3U,0U}}, +{CHK_4120,{6U,3U,0U}}, +{CHK_4120,{7U,3U,0U}}, +{CHK_4128,{0U,3U,0U}}, +{CHK_4128,{1U,3U,0U}}, +{CHK_4128,{2U,3U,0U}}, +{CHK_4128,{3U,3U,0U}}, +{CHK_4128,{4U,3U,0U}}, +{CHK_4128,{5U,3U,0U}}, +{CHK_4128,{6U,3U,0U}}, +{CHK_4128,{7U,3U,0U}}, +{CHK_4130,{0U,3U,0U}}, +{CHK_4130,{1U,3U,0U}}, +{CHK_4130,{2U,3U,0U}}, +{CHK_4130,{3U,3U,0U}}, +{CHK_4130,{4U,3U,0U}}, +{CHK_4130,{5U,3U,0U}}, +{CHK_4130,{6U,3U,0U}}, +{CHK_4130,{7U,3U,0U}}, +{CHK_4138,{0U,3U,0U}}, +{CHK_4139,{0U,3U,0U}}, +{CHK_413A,{0U,3U,0U}}, +{CHK_413B,{0U,3U,0U}}, +{CHK_413C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4180,{0U,3U,0U}}, +{CHK_4180,{1U,3U,0U}}, +{CHK_4180,{2U,3U,0U}}, +{CHK_4180,{3U,3U,0U}}, +{CHK_4180,{4U,3U,0U}}, +{CHK_4180,{5U,3U,0U}}, +{CHK_4180,{6U,3U,0U}}, +{CHK_4180,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4190,{0U,3U,0U}}, +{CHK_4190,{1U,3U,0U}}, +{CHK_4190,{2U,3U,0U}}, +{CHK_4190,{3U,3U,0U}}, +{CHK_4190,{4U,3U,0U}}, +{CHK_4190,{5U,3U,0U}}, +{CHK_4190,{6U,3U,0U}}, +{CHK_4190,{7U,3U,0U}}, +{CHK_4198,{0U,3U,0U}}, +{CHK_4198,{1U,3U,0U}}, +{CHK_4198,{2U,3U,0U}}, +{CHK_4198,{3U,3U,0U}}, +{CHK_4198,{4U,3U,0U}}, +{CHK_4198,{5U,3U,0U}}, +{CHK_4198,{6U,3U,0U}}, +{CHK_4198,{7U,3U,0U}}, +{CHK_41A0,{0U,3U,0U}}, +{CHK_41A0,{1U,3U,0U}}, +{CHK_41A0,{2U,3U,0U}}, +{CHK_41A0,{3U,3U,0U}}, +{CHK_41A0,{4U,3U,0U}}, +{CHK_41A0,{5U,3U,0U}}, +{CHK_41A0,{6U,3U,0U}}, +{CHK_41A0,{7U,3U,0U}}, +{CHK_41A8,{0U,3U,0U}}, +{CHK_41A8,{1U,3U,0U}}, +{CHK_41A8,{2U,3U,0U}}, +{CHK_41A8,{3U,3U,0U}}, +{CHK_41A8,{4U,3U,0U}}, +{CHK_41A8,{5U,3U,0U}}, +{CHK_41A8,{6U,3U,0U}}, +{CHK_41A8,{7U,3U,0U}}, +{CHK_41B0,{0U,3U,0U}}, +{CHK_41B0,{1U,3U,0U}}, +{CHK_41B0,{2U,3U,0U}}, +{CHK_41B0,{3U,3U,0U}}, +{CHK_41B0,{4U,3U,0U}}, +{CHK_41B0,{5U,3U,0U}}, +{CHK_41B0,{6U,3U,0U}}, +{CHK_41B0,{7U,3U,0U}}, +{CHK_41B8,{0U,3U,0U}}, +{CHK_41B9,{0U,3U,0U}}, +{CHK_41BA,{0U,3U,0U}}, +{CHK_41BB,{0U,3U,0U}}, +{CHK_41BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41D0,{0U,3U,0U}}, +{LEA_41D0,{1U,3U,0U}}, +{LEA_41D0,{2U,3U,0U}}, +{LEA_41D0,{3U,3U,0U}}, +{LEA_41D0,{4U,3U,0U}}, +{LEA_41D0,{5U,3U,0U}}, +{LEA_41D0,{6U,3U,0U}}, +{LEA_41D0,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41E8,{0U,3U,0U}}, +{LEA_41E8,{1U,3U,0U}}, +{LEA_41E8,{2U,3U,0U}}, +{LEA_41E8,{3U,3U,0U}}, +{LEA_41E8,{4U,3U,0U}}, +{LEA_41E8,{5U,3U,0U}}, +{LEA_41E8,{6U,3U,0U}}, +{LEA_41E8,{7U,3U,0U}}, +{LEA_41F0,{0U,3U,0U}}, +{LEA_41F0,{1U,3U,0U}}, +{LEA_41F0,{2U,3U,0U}}, +{LEA_41F0,{3U,3U,0U}}, +{LEA_41F0,{4U,3U,0U}}, +{LEA_41F0,{5U,3U,0U}}, +{LEA_41F0,{6U,3U,0U}}, +{LEA_41F0,{7U,3U,0U}}, +{LEA_41F8,{0U,3U,0U}}, +{LEA_41F9,{0U,3U,0U}}, +{LEA_41FA,{0U,3U,0U}}, +{LEA_41FB,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{NBCD_4800,{0U,0U,0U}}, +{NBCD_4800,{1U,0U,0U}}, +{NBCD_4800,{2U,0U,0U}}, +{NBCD_4800,{3U,0U,0U}}, +{NBCD_4800,{4U,0U,0U}}, +{NBCD_4800,{5U,0U,0U}}, +{NBCD_4800,{6U,0U,0U}}, +{NBCD_4800,{7U,0U,0U}}, +{LINK_4808,{0U,0U,0U}}, +{LINK_4808,{1U,0U,0U}}, +{LINK_4808,{2U,0U,0U}}, +{LINK_4808,{3U,0U,0U}}, +{LINK_4808,{4U,0U,0U}}, +{LINK_4808,{5U,0U,0U}}, +{LINK_4808,{6U,0U,0U}}, +{LINK_4808,{7U,0U,0U}}, +{NBCD_4810,{0U,0U,0U}}, +{NBCD_4810,{1U,0U,0U}}, +{NBCD_4810,{2U,0U,0U}}, +{NBCD_4810,{3U,0U,0U}}, +{NBCD_4810,{4U,0U,0U}}, +{NBCD_4810,{5U,0U,0U}}, +{NBCD_4810,{6U,0U,0U}}, +{NBCD_4810,{7U,0U,0U}}, +{NBCD_4818,{0U,0U,0U}}, +{NBCD_4818,{1U,0U,0U}}, +{NBCD_4818,{2U,0U,0U}}, +{NBCD_4818,{3U,0U,0U}}, +{NBCD_4818,{4U,0U,0U}}, +{NBCD_4818,{5U,0U,0U}}, +{NBCD_4818,{6U,0U,0U}}, +{NBCD_4818,{7U,0U,0U}}, +{NBCD_4820,{0U,0U,0U}}, +{NBCD_4820,{1U,0U,0U}}, +{NBCD_4820,{2U,0U,0U}}, +{NBCD_4820,{3U,0U,0U}}, +{NBCD_4820,{4U,0U,0U}}, +{NBCD_4820,{5U,0U,0U}}, +{NBCD_4820,{6U,0U,0U}}, +{NBCD_4820,{7U,0U,0U}}, +{NBCD_4828,{0U,0U,0U}}, +{NBCD_4828,{1U,0U,0U}}, +{NBCD_4828,{2U,0U,0U}}, +{NBCD_4828,{3U,0U,0U}}, +{NBCD_4828,{4U,0U,0U}}, +{NBCD_4828,{5U,0U,0U}}, +{NBCD_4828,{6U,0U,0U}}, +{NBCD_4828,{7U,0U,0U}}, +{NBCD_4830,{0U,0U,0U}}, +{NBCD_4830,{1U,0U,0U}}, +{NBCD_4830,{2U,0U,0U}}, +{NBCD_4830,{3U,0U,0U}}, +{NBCD_4830,{4U,0U,0U}}, +{NBCD_4830,{5U,0U,0U}}, +{NBCD_4830,{6U,0U,0U}}, +{NBCD_4830,{7U,0U,0U}}, +{NBCD_4838,{0U,0U,0U}}, +{NBCD_4839,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SWAP_4840,{0U,0U,0U}}, +{SWAP_4840,{1U,0U,0U}}, +{SWAP_4840,{2U,0U,0U}}, +{SWAP_4840,{3U,0U,0U}}, +{SWAP_4840,{4U,0U,0U}}, +{SWAP_4840,{5U,0U,0U}}, +{SWAP_4840,{6U,0U,0U}}, +{SWAP_4840,{7U,0U,0U}}, +{BKPT_4848,{0U,0U,0U}}, +{BKPT_4848,{1U,0U,0U}}, +{BKPT_4848,{2U,0U,0U}}, +{BKPT_4848,{3U,0U,0U}}, +{BKPT_4848,{4U,0U,0U}}, +{BKPT_4848,{5U,0U,0U}}, +{BKPT_4848,{6U,0U,0U}}, +{BKPT_4848,{7U,0U,0U}}, +{PEA_4850,{0U,0U,0U}}, +{PEA_4850,{1U,0U,0U}}, +{PEA_4850,{2U,0U,0U}}, +{PEA_4850,{3U,0U,0U}}, +{PEA_4850,{4U,0U,0U}}, +{PEA_4850,{5U,0U,0U}}, +{PEA_4850,{6U,0U,0U}}, +{PEA_4850,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PEA_4868,{0U,0U,0U}}, +{PEA_4868,{1U,0U,0U}}, +{PEA_4868,{2U,0U,0U}}, +{PEA_4868,{3U,0U,0U}}, +{PEA_4868,{4U,0U,0U}}, +{PEA_4868,{5U,0U,0U}}, +{PEA_4868,{6U,0U,0U}}, +{PEA_4868,{7U,0U,0U}}, +{PEA_4870,{0U,0U,0U}}, +{PEA_4870,{1U,0U,0U}}, +{PEA_4870,{2U,0U,0U}}, +{PEA_4870,{3U,0U,0U}}, +{PEA_4870,{4U,0U,0U}}, +{PEA_4870,{5U,0U,0U}}, +{PEA_4870,{6U,0U,0U}}, +{PEA_4870,{7U,0U,0U}}, +{PEA_4878,{0U,0U,0U}}, +{PEA_4879,{0U,0U,0U}}, +{PEA_487A,{0U,0U,0U}}, +{PEA_487B,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXT_4880,{0U,0U,0U}}, +{EXT_4880,{1U,0U,0U}}, +{EXT_4880,{2U,0U,0U}}, +{EXT_4880,{3U,0U,0U}}, +{EXT_4880,{4U,0U,0U}}, +{EXT_4880,{5U,0U,0U}}, +{EXT_4880,{6U,0U,0U}}, +{EXT_4880,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEM_4890,{0U,8U,0U}}, +{MOVEM_4890,{1U,8U,0U}}, +{MOVEM_4890,{2U,8U,0U}}, +{MOVEM_4890,{3U,8U,0U}}, +{MOVEM_4890,{4U,8U,0U}}, +{MOVEM_4890,{5U,8U,0U}}, +{MOVEM_4890,{6U,8U,0U}}, +{MOVEM_4890,{7U,8U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEM_48A0,{0U,0U,0U}}, +{MOVEM_48A0,{1U,0U,0U}}, +{MOVEM_48A0,{2U,0U,0U}}, +{MOVEM_48A0,{3U,0U,0U}}, +{MOVEM_48A0,{4U,0U,0U}}, +{MOVEM_48A0,{5U,0U,0U}}, +{MOVEM_48A0,{6U,0U,0U}}, +{MOVEM_48A0,{7U,0U,0U}}, +{MOVEM_48A8,{0U,12U,0U}}, +{MOVEM_48A8,{1U,12U,0U}}, +{MOVEM_48A8,{2U,12U,0U}}, +{MOVEM_48A8,{3U,12U,0U}}, +{MOVEM_48A8,{4U,12U,0U}}, +{MOVEM_48A8,{5U,12U,0U}}, +{MOVEM_48A8,{6U,12U,0U}}, +{MOVEM_48A8,{7U,12U,0U}}, +{MOVEM_48B0,{0U,14U,0U}}, +{MOVEM_48B0,{1U,14U,0U}}, +{MOVEM_48B0,{2U,14U,0U}}, +{MOVEM_48B0,{3U,14U,0U}}, +{MOVEM_48B0,{4U,14U,0U}}, +{MOVEM_48B0,{5U,14U,0U}}, +{MOVEM_48B0,{6U,14U,0U}}, +{MOVEM_48B0,{7U,14U,0U}}, +{MOVEM_48B8,{0U,12U,0U}}, +{MOVEM_48B9,{0U,16U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXT_48C0,{0U,0U,0U}}, +{EXT_48C0,{1U,0U,0U}}, +{EXT_48C0,{2U,0U,0U}}, +{EXT_48C0,{3U,0U,0U}}, +{EXT_48C0,{4U,0U,0U}}, +{EXT_48C0,{5U,0U,0U}}, +{EXT_48C0,{6U,0U,0U}}, +{EXT_48C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEM_48D0,{0U,8U,0U}}, +{MOVEM_48D0,{1U,8U,0U}}, +{MOVEM_48D0,{2U,8U,0U}}, +{MOVEM_48D0,{3U,8U,0U}}, +{MOVEM_48D0,{4U,8U,0U}}, +{MOVEM_48D0,{5U,8U,0U}}, +{MOVEM_48D0,{6U,8U,0U}}, +{MOVEM_48D0,{7U,8U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEM_48E0,{0U,0U,0U}}, +{MOVEM_48E0,{1U,0U,0U}}, +{MOVEM_48E0,{2U,0U,0U}}, +{MOVEM_48E0,{3U,0U,0U}}, +{MOVEM_48E0,{4U,0U,0U}}, +{MOVEM_48E0,{5U,0U,0U}}, +{MOVEM_48E0,{6U,0U,0U}}, +{MOVEM_48E0,{7U,0U,0U}}, +{MOVEM_48E8,{0U,12U,0U}}, +{MOVEM_48E8,{1U,12U,0U}}, +{MOVEM_48E8,{2U,12U,0U}}, +{MOVEM_48E8,{3U,12U,0U}}, +{MOVEM_48E8,{4U,12U,0U}}, +{MOVEM_48E8,{5U,12U,0U}}, +{MOVEM_48E8,{6U,12U,0U}}, +{MOVEM_48E8,{7U,12U,0U}}, +{MOVEM_48F0,{0U,14U,0U}}, +{MOVEM_48F0,{1U,14U,0U}}, +{MOVEM_48F0,{2U,14U,0U}}, +{MOVEM_48F0,{3U,14U,0U}}, +{MOVEM_48F0,{4U,14U,0U}}, +{MOVEM_48F0,{5U,14U,0U}}, +{MOVEM_48F0,{6U,14U,0U}}, +{MOVEM_48F0,{7U,14U,0U}}, +{MOVEM_48F8,{0U,12U,0U}}, +{MOVEM_48F9,{0U,16U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4100,{0U,4U,0U}}, +{CHK_4100,{1U,4U,0U}}, +{CHK_4100,{2U,4U,0U}}, +{CHK_4100,{3U,4U,0U}}, +{CHK_4100,{4U,4U,0U}}, +{CHK_4100,{5U,4U,0U}}, +{CHK_4100,{6U,4U,0U}}, +{CHK_4100,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4110,{0U,4U,0U}}, +{CHK_4110,{1U,4U,0U}}, +{CHK_4110,{2U,4U,0U}}, +{CHK_4110,{3U,4U,0U}}, +{CHK_4110,{4U,4U,0U}}, +{CHK_4110,{5U,4U,0U}}, +{CHK_4110,{6U,4U,0U}}, +{CHK_4110,{7U,4U,0U}}, +{CHK_4118,{0U,4U,0U}}, +{CHK_4118,{1U,4U,0U}}, +{CHK_4118,{2U,4U,0U}}, +{CHK_4118,{3U,4U,0U}}, +{CHK_4118,{4U,4U,0U}}, +{CHK_4118,{5U,4U,0U}}, +{CHK_4118,{6U,4U,0U}}, +{CHK_4118,{7U,4U,0U}}, +{CHK_4120,{0U,4U,0U}}, +{CHK_4120,{1U,4U,0U}}, +{CHK_4120,{2U,4U,0U}}, +{CHK_4120,{3U,4U,0U}}, +{CHK_4120,{4U,4U,0U}}, +{CHK_4120,{5U,4U,0U}}, +{CHK_4120,{6U,4U,0U}}, +{CHK_4120,{7U,4U,0U}}, +{CHK_4128,{0U,4U,0U}}, +{CHK_4128,{1U,4U,0U}}, +{CHK_4128,{2U,4U,0U}}, +{CHK_4128,{3U,4U,0U}}, +{CHK_4128,{4U,4U,0U}}, +{CHK_4128,{5U,4U,0U}}, +{CHK_4128,{6U,4U,0U}}, +{CHK_4128,{7U,4U,0U}}, +{CHK_4130,{0U,4U,0U}}, +{CHK_4130,{1U,4U,0U}}, +{CHK_4130,{2U,4U,0U}}, +{CHK_4130,{3U,4U,0U}}, +{CHK_4130,{4U,4U,0U}}, +{CHK_4130,{5U,4U,0U}}, +{CHK_4130,{6U,4U,0U}}, +{CHK_4130,{7U,4U,0U}}, +{CHK_4138,{0U,4U,0U}}, +{CHK_4139,{0U,4U,0U}}, +{CHK_413A,{0U,4U,0U}}, +{CHK_413B,{0U,4U,0U}}, +{CHK_413C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4180,{0U,4U,0U}}, +{CHK_4180,{1U,4U,0U}}, +{CHK_4180,{2U,4U,0U}}, +{CHK_4180,{3U,4U,0U}}, +{CHK_4180,{4U,4U,0U}}, +{CHK_4180,{5U,4U,0U}}, +{CHK_4180,{6U,4U,0U}}, +{CHK_4180,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, 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+{CHK_41B0,{3U,4U,0U}}, +{CHK_41B0,{4U,4U,0U}}, +{CHK_41B0,{5U,4U,0U}}, +{CHK_41B0,{6U,4U,0U}}, +{CHK_41B0,{7U,4U,0U}}, +{CHK_41B8,{0U,4U,0U}}, +{CHK_41B9,{0U,4U,0U}}, +{CHK_41BA,{0U,4U,0U}}, +{CHK_41BB,{0U,4U,0U}}, +{CHK_41BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXT_49C0,{0U,0U,0U}}, +{EXT_49C0,{1U,0U,0U}}, +{EXT_49C0,{2U,0U,0U}}, +{EXT_49C0,{3U,0U,0U}}, +{EXT_49C0,{4U,0U,0U}}, +{EXT_49C0,{5U,0U,0U}}, +{EXT_49C0,{6U,0U,0U}}, +{EXT_49C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41D0,{0U,4U,0U}}, +{LEA_41D0,{1U,4U,0U}}, +{LEA_41D0,{2U,4U,0U}}, +{LEA_41D0,{3U,4U,0U}}, +{LEA_41D0,{4U,4U,0U}}, +{LEA_41D0,{5U,4U,0U}}, +{LEA_41D0,{6U,4U,0U}}, +{LEA_41D0,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41E8,{0U,4U,0U}}, +{LEA_41E8,{1U,4U,0U}}, +{LEA_41E8,{2U,4U,0U}}, +{LEA_41E8,{3U,4U,0U}}, +{LEA_41E8,{4U,4U,0U}}, +{LEA_41E8,{5U,4U,0U}}, +{LEA_41E8,{6U,4U,0U}}, +{LEA_41E8,{7U,4U,0U}}, +{LEA_41F0,{0U,4U,0U}}, +{LEA_41F0,{1U,4U,0U}}, +{LEA_41F0,{2U,4U,0U}}, +{LEA_41F0,{3U,4U,0U}}, +{LEA_41F0,{4U,4U,0U}}, +{LEA_41F0,{5U,4U,0U}}, +{LEA_41F0,{6U,4U,0U}}, +{LEA_41F0,{7U,4U,0U}}, +{LEA_41F8,{0U,4U,0U}}, +{LEA_41F9,{0U,4U,0U}}, +{LEA_41FA,{0U,4U,0U}}, +{LEA_41FB,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{TST_4A00,{0U,0U,0U}}, +{TST_4A00,{1U,0U,0U}}, +{TST_4A00,{2U,0U,0U}}, +{TST_4A00,{3U,0U,0U}}, +{TST_4A00,{4U,0U,0U}}, +{TST_4A00,{5U,0U,0U}}, +{TST_4A00,{6U,0U,0U}}, +{TST_4A00,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{TST_4A10,{0U,0U,0U}}, +{TST_4A10,{1U,0U,0U}}, +{TST_4A10,{2U,0U,0U}}, +{TST_4A10,{3U,0U,0U}}, +{TST_4A10,{4U,0U,0U}}, +{TST_4A10,{5U,0U,0U}}, +{TST_4A10,{6U,0U,0U}}, +{TST_4A10,{7U,0U,0U}}, +{TST_4A18,{0U,0U,0U}}, +{TST_4A18,{1U,0U,0U}}, +{TST_4A18,{2U,0U,0U}}, +{TST_4A18,{3U,0U,0U}}, +{TST_4A18,{4U,0U,0U}}, +{TST_4A18,{5U,0U,0U}}, +{TST_4A18,{6U,0U,0U}}, +{TST_4A18,{7U,0U,0U}}, +{TST_4A20,{0U,0U,0U}}, +{TST_4A20,{1U,0U,0U}}, +{TST_4A20,{2U,0U,0U}}, +{TST_4A20,{3U,0U,0U}}, +{TST_4A20,{4U,0U,0U}}, +{TST_4A20,{5U,0U,0U}}, +{TST_4A20,{6U,0U,0U}}, +{TST_4A20,{7U,0U,0U}}, +{TST_4A28,{0U,0U,0U}}, +{TST_4A28,{1U,0U,0U}}, +{TST_4A28,{2U,0U,0U}}, +{TST_4A28,{3U,0U,0U}}, +{TST_4A28,{4U,0U,0U}}, +{TST_4A28,{5U,0U,0U}}, +{TST_4A28,{6U,0U,0U}}, +{TST_4A28,{7U,0U,0U}}, +{TST_4A30,{0U,0U,0U}}, +{TST_4A30,{1U,0U,0U}}, +{TST_4A30,{2U,0U,0U}}, +{TST_4A30,{3U,0U,0U}}, +{TST_4A30,{4U,0U,0U}}, +{TST_4A30,{5U,0U,0U}}, +{TST_4A30,{6U,0U,0U}}, +{TST_4A30,{7U,0U,0U}}, +{TST_4A38,{0U,0U,0U}}, +{TST_4A39,{0U,0U,0U}}, +{TST_4A3A,{0U,0U,0U}}, +{TST_4A3B,{0U,0U,0U}}, +{TST_4A3C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{TST_4A40,{0U,0U,0U}}, +{TST_4A40,{1U,0U,0U}}, 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+{TST_4A90,{3U,0U,0U}}, +{TST_4A90,{4U,0U,0U}}, +{TST_4A90,{5U,0U,0U}}, +{TST_4A90,{6U,0U,0U}}, +{TST_4A90,{7U,0U,0U}}, +{TST_4A98,{0U,0U,0U}}, +{TST_4A98,{1U,0U,0U}}, +{TST_4A98,{2U,0U,0U}}, +{TST_4A98,{3U,0U,0U}}, +{TST_4A98,{4U,0U,0U}}, +{TST_4A98,{5U,0U,0U}}, +{TST_4A98,{6U,0U,0U}}, +{TST_4A98,{7U,0U,0U}}, +{TST_4AA0,{0U,0U,0U}}, +{TST_4AA0,{1U,0U,0U}}, +{TST_4AA0,{2U,0U,0U}}, +{TST_4AA0,{3U,0U,0U}}, +{TST_4AA0,{4U,0U,0U}}, +{TST_4AA0,{5U,0U,0U}}, +{TST_4AA0,{6U,0U,0U}}, +{TST_4AA0,{7U,0U,0U}}, +{TST_4AA8,{0U,0U,0U}}, +{TST_4AA8,{1U,0U,0U}}, +{TST_4AA8,{2U,0U,0U}}, +{TST_4AA8,{3U,0U,0U}}, +{TST_4AA8,{4U,0U,0U}}, +{TST_4AA8,{5U,0U,0U}}, +{TST_4AA8,{6U,0U,0U}}, +{TST_4AA8,{7U,0U,0U}}, +{TST_4AB0,{0U,0U,0U}}, +{TST_4AB0,{1U,0U,0U}}, +{TST_4AB0,{2U,0U,0U}}, +{TST_4AB0,{3U,0U,0U}}, +{TST_4AB0,{4U,0U,0U}}, +{TST_4AB0,{5U,0U,0U}}, +{TST_4AB0,{6U,0U,0U}}, +{TST_4AB0,{7U,0U,0U}}, +{TST_4AB8,{0U,0U,0U}}, +{TST_4AB9,{0U,0U,0U}}, +{TST_4ABA,{0U,0U,0U}}, +{TST_4ABB,{0U,0U,0U}}, +{TST_4ABC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{TAS_4AC0,{0U,0U,0U}}, +{TAS_4AC0,{1U,0U,0U}}, +{TAS_4AC0,{2U,0U,0U}}, +{TAS_4AC0,{3U,0U,0U}}, +{TAS_4AC0,{4U,0U,0U}}, +{TAS_4AC0,{5U,0U,0U}}, +{TAS_4AC0,{6U,0U,0U}}, +{TAS_4AC0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{TAS_4AD0,{0U,0U,0U}}, +{TAS_4AD0,{1U,0U,0U}}, +{TAS_4AD0,{2U,0U,0U}}, +{TAS_4AD0,{3U,0U,0U}}, +{TAS_4AD0,{4U,0U,0U}}, +{TAS_4AD0,{5U,0U,0U}}, +{TAS_4AD0,{6U,0U,0U}}, +{TAS_4AD0,{7U,0U,0U}}, +{TAS_4AD8,{0U,0U,0U}}, +{TAS_4AD8,{1U,0U,0U}}, +{TAS_4AD8,{2U,0U,0U}}, +{TAS_4AD8,{3U,0U,0U}}, +{TAS_4AD8,{4U,0U,0U}}, +{TAS_4AD8,{5U,0U,0U}}, +{TAS_4AD8,{6U,0U,0U}}, +{TAS_4AD8,{7U,0U,0U}}, +{TAS_4AE0,{0U,0U,0U}}, +{TAS_4AE0,{1U,0U,0U}}, +{TAS_4AE0,{2U,0U,0U}}, +{TAS_4AE0,{3U,0U,0U}}, +{TAS_4AE0,{4U,0U,0U}}, +{TAS_4AE0,{5U,0U,0U}}, +{TAS_4AE0,{6U,0U,0U}}, +{TAS_4AE0,{7U,0U,0U}}, +{TAS_4AE8,{0U,0U,0U}}, +{TAS_4AE8,{1U,0U,0U}}, +{TAS_4AE8,{2U,0U,0U}}, +{TAS_4AE8,{3U,0U,0U}}, +{TAS_4AE8,{4U,0U,0U}}, +{TAS_4AE8,{5U,0U,0U}}, +{TAS_4AE8,{6U,0U,0U}}, +{TAS_4AE8,{7U,0U,0U}}, +{TAS_4AF0,{0U,0U,0U}}, +{TAS_4AF0,{1U,0U,0U}}, +{TAS_4AF0,{2U,0U,0U}}, +{TAS_4AF0,{3U,0U,0U}}, +{TAS_4AF0,{4U,0U,0U}}, +{TAS_4AF0,{5U,0U,0U}}, +{TAS_4AF0,{6U,0U,0U}}, +{TAS_4AF0,{7U,0U,0U}}, +{TAS_4AF8,{0U,0U,0U}}, +{TAS_4AF9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4100,{0U,5U,0U}}, +{CHK_4100,{1U,5U,0U}}, +{CHK_4100,{2U,5U,0U}}, +{CHK_4100,{3U,5U,0U}}, +{CHK_4100,{4U,5U,0U}}, +{CHK_4100,{5U,5U,0U}}, +{CHK_4100,{6U,5U,0U}}, +{CHK_4100,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4110,{0U,5U,0U}}, +{CHK_4110,{1U,5U,0U}}, +{CHK_4110,{2U,5U,0U}}, +{CHK_4110,{3U,5U,0U}}, +{CHK_4110,{4U,5U,0U}}, +{CHK_4110,{5U,5U,0U}}, +{CHK_4110,{6U,5U,0U}}, +{CHK_4110,{7U,5U,0U}}, +{CHK_4118,{0U,5U,0U}}, +{CHK_4118,{1U,5U,0U}}, +{CHK_4118,{2U,5U,0U}}, +{CHK_4118,{3U,5U,0U}}, +{CHK_4118,{4U,5U,0U}}, +{CHK_4118,{5U,5U,0U}}, +{CHK_4118,{6U,5U,0U}}, +{CHK_4118,{7U,5U,0U}}, +{CHK_4120,{0U,5U,0U}}, +{CHK_4120,{1U,5U,0U}}, +{CHK_4120,{2U,5U,0U}}, +{CHK_4120,{3U,5U,0U}}, +{CHK_4120,{4U,5U,0U}}, +{CHK_4120,{5U,5U,0U}}, +{CHK_4120,{6U,5U,0U}}, +{CHK_4120,{7U,5U,0U}}, +{CHK_4128,{0U,5U,0U}}, +{CHK_4128,{1U,5U,0U}}, +{CHK_4128,{2U,5U,0U}}, +{CHK_4128,{3U,5U,0U}}, +{CHK_4128,{4U,5U,0U}}, +{CHK_4128,{5U,5U,0U}}, +{CHK_4128,{6U,5U,0U}}, +{CHK_4128,{7U,5U,0U}}, +{CHK_4130,{0U,5U,0U}}, +{CHK_4130,{1U,5U,0U}}, +{CHK_4130,{2U,5U,0U}}, +{CHK_4130,{3U,5U,0U}}, +{CHK_4130,{4U,5U,0U}}, +{CHK_4130,{5U,5U,0U}}, +{CHK_4130,{6U,5U,0U}}, +{CHK_4130,{7U,5U,0U}}, +{CHK_4138,{0U,5U,0U}}, +{CHK_4139,{0U,5U,0U}}, +{CHK_413A,{0U,5U,0U}}, +{CHK_413B,{0U,5U,0U}}, +{CHK_413C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4180,{0U,5U,0U}}, +{CHK_4180,{1U,5U,0U}}, +{CHK_4180,{2U,5U,0U}}, +{CHK_4180,{3U,5U,0U}}, +{CHK_4180,{4U,5U,0U}}, +{CHK_4180,{5U,5U,0U}}, +{CHK_4180,{6U,5U,0U}}, +{CHK_4180,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4190,{0U,5U,0U}}, +{CHK_4190,{1U,5U,0U}}, +{CHK_4190,{2U,5U,0U}}, +{CHK_4190,{3U,5U,0U}}, +{CHK_4190,{4U,5U,0U}}, +{CHK_4190,{5U,5U,0U}}, +{CHK_4190,{6U,5U,0U}}, +{CHK_4190,{7U,5U,0U}}, +{CHK_4198,{0U,5U,0U}}, +{CHK_4198,{1U,5U,0U}}, +{CHK_4198,{2U,5U,0U}}, +{CHK_4198,{3U,5U,0U}}, +{CHK_4198,{4U,5U,0U}}, +{CHK_4198,{5U,5U,0U}}, +{CHK_4198,{6U,5U,0U}}, +{CHK_4198,{7U,5U,0U}}, +{CHK_41A0,{0U,5U,0U}}, +{CHK_41A0,{1U,5U,0U}}, +{CHK_41A0,{2U,5U,0U}}, +{CHK_41A0,{3U,5U,0U}}, +{CHK_41A0,{4U,5U,0U}}, +{CHK_41A0,{5U,5U,0U}}, +{CHK_41A0,{6U,5U,0U}}, +{CHK_41A0,{7U,5U,0U}}, +{CHK_41A8,{0U,5U,0U}}, +{CHK_41A8,{1U,5U,0U}}, +{CHK_41A8,{2U,5U,0U}}, +{CHK_41A8,{3U,5U,0U}}, +{CHK_41A8,{4U,5U,0U}}, +{CHK_41A8,{5U,5U,0U}}, +{CHK_41A8,{6U,5U,0U}}, +{CHK_41A8,{7U,5U,0U}}, +{CHK_41B0,{0U,5U,0U}}, +{CHK_41B0,{1U,5U,0U}}, +{CHK_41B0,{2U,5U,0U}}, +{CHK_41B0,{3U,5U,0U}}, +{CHK_41B0,{4U,5U,0U}}, +{CHK_41B0,{5U,5U,0U}}, +{CHK_41B0,{6U,5U,0U}}, +{CHK_41B0,{7U,5U,0U}}, +{CHK_41B8,{0U,5U,0U}}, +{CHK_41B9,{0U,5U,0U}}, +{CHK_41BA,{0U,5U,0U}}, +{CHK_41BB,{0U,5U,0U}}, +{CHK_41BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41D0,{0U,5U,0U}}, +{LEA_41D0,{1U,5U,0U}}, +{LEA_41D0,{2U,5U,0U}}, +{LEA_41D0,{3U,5U,0U}}, +{LEA_41D0,{4U,5U,0U}}, +{LEA_41D0,{5U,5U,0U}}, +{LEA_41D0,{6U,5U,0U}}, +{LEA_41D0,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41E8,{0U,5U,0U}}, +{LEA_41E8,{1U,5U,0U}}, +{LEA_41E8,{2U,5U,0U}}, +{LEA_41E8,{3U,5U,0U}}, +{LEA_41E8,{4U,5U,0U}}, +{LEA_41E8,{5U,5U,0U}}, +{LEA_41E8,{6U,5U,0U}}, +{LEA_41E8,{7U,5U,0U}}, +{LEA_41F0,{0U,5U,0U}}, +{LEA_41F0,{1U,5U,0U}}, +{LEA_41F0,{2U,5U,0U}}, +{LEA_41F0,{3U,5U,0U}}, +{LEA_41F0,{4U,5U,0U}}, +{LEA_41F0,{5U,5U,0U}}, +{LEA_41F0,{6U,5U,0U}}, +{LEA_41F0,{7U,5U,0U}}, +{LEA_41F8,{0U,5U,0U}}, +{LEA_41F9,{0U,5U,0U}}, +{LEA_41FA,{0U,5U,0U}}, +{LEA_41FB,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULL_4C00,{0U,0U,0U}}, +{MULL_4C00,{1U,0U,0U}}, +{MULL_4C00,{2U,0U,0U}}, +{MULL_4C00,{3U,0U,0U}}, +{MULL_4C00,{4U,0U,0U}}, +{MULL_4C00,{5U,0U,0U}}, +{MULL_4C00,{6U,0U,0U}}, +{MULL_4C00,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULL_4C10,{0U,0U,0U}}, +{MULL_4C10,{1U,0U,0U}}, +{MULL_4C10,{2U,0U,0U}}, +{MULL_4C10,{3U,0U,0U}}, +{MULL_4C10,{4U,0U,0U}}, +{MULL_4C10,{5U,0U,0U}}, +{MULL_4C10,{6U,0U,0U}}, +{MULL_4C10,{7U,0U,0U}}, +{MULL_4C18,{0U,0U,0U}}, +{MULL_4C18,{1U,0U,0U}}, +{MULL_4C18,{2U,0U,0U}}, +{MULL_4C18,{3U,0U,0U}}, +{MULL_4C18,{4U,0U,0U}}, +{MULL_4C18,{5U,0U,0U}}, +{MULL_4C18,{6U,0U,0U}}, +{MULL_4C18,{7U,0U,0U}}, +{MULL_4C20,{0U,0U,0U}}, +{MULL_4C20,{1U,0U,0U}}, +{MULL_4C20,{2U,0U,0U}}, +{MULL_4C20,{3U,0U,0U}}, +{MULL_4C20,{4U,0U,0U}}, +{MULL_4C20,{5U,0U,0U}}, +{MULL_4C20,{6U,0U,0U}}, +{MULL_4C20,{7U,0U,0U}}, +{MULL_4C28,{0U,0U,0U}}, +{MULL_4C28,{1U,0U,0U}}, +{MULL_4C28,{2U,0U,0U}}, +{MULL_4C28,{3U,0U,0U}}, +{MULL_4C28,{4U,0U,0U}}, +{MULL_4C28,{5U,0U,0U}}, +{MULL_4C28,{6U,0U,0U}}, +{MULL_4C28,{7U,0U,0U}}, +{MULL_4C30,{0U,0U,0U}}, +{MULL_4C30,{1U,0U,0U}}, +{MULL_4C30,{2U,0U,0U}}, +{MULL_4C30,{3U,0U,0U}}, +{MULL_4C30,{4U,0U,0U}}, +{MULL_4C30,{5U,0U,0U}}, +{MULL_4C30,{6U,0U,0U}}, +{MULL_4C30,{7U,0U,0U}}, +{MULL_4C38,{0U,0U,0U}}, +{MULL_4C39,{0U,0U,0U}}, +{MULL_4C3A,{0U,0U,0U}}, +{MULL_4C3B,{0U,0U,0U}}, +{MULL_4C3C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVL_4C40,{0U,0U,4U}}, +{DIVL_4C40,{1U,0U,4U}}, +{DIVL_4C40,{2U,0U,4U}}, +{DIVL_4C40,{3U,0U,4U}}, +{DIVL_4C40,{4U,0U,4U}}, +{DIVL_4C40,{5U,0U,4U}}, +{DIVL_4C40,{6U,0U,4U}}, +{DIVL_4C40,{7U,0U,4U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVL_4C50,{0U,0U,12U}}, +{DIVL_4C50,{1U,0U,12U}}, +{DIVL_4C50,{2U,0U,12U}}, +{DIVL_4C50,{3U,0U,12U}}, +{DIVL_4C50,{4U,0U,12U}}, +{DIVL_4C50,{5U,0U,12U}}, +{DIVL_4C50,{6U,0U,12U}}, +{DIVL_4C50,{7U,0U,12U}}, +{DIVL_4C58,{0U,0U,12U}}, +{DIVL_4C58,{1U,0U,12U}}, +{DIVL_4C58,{2U,0U,12U}}, +{DIVL_4C58,{3U,0U,12U}}, +{DIVL_4C58,{4U,0U,12U}}, +{DIVL_4C58,{5U,0U,12U}}, +{DIVL_4C58,{6U,0U,12U}}, +{DIVL_4C58,{7U,0U,12U}}, +{DIVL_4C60,{0U,0U,14U}}, +{DIVL_4C60,{1U,0U,14U}}, +{DIVL_4C60,{2U,0U,14U}}, +{DIVL_4C60,{3U,0U,14U}}, +{DIVL_4C60,{4U,0U,14U}}, +{DIVL_4C60,{5U,0U,14U}}, +{DIVL_4C60,{6U,0U,14U}}, +{DIVL_4C60,{7U,0U,14U}}, +{DIVL_4C68,{0U,0U,16U}}, +{DIVL_4C68,{1U,0U,16U}}, +{DIVL_4C68,{2U,0U,16U}}, +{DIVL_4C68,{3U,0U,16U}}, +{DIVL_4C68,{4U,0U,16U}}, +{DIVL_4C68,{5U,0U,16U}}, +{DIVL_4C68,{6U,0U,16U}}, +{DIVL_4C68,{7U,0U,16U}}, +{DIVL_4C70,{0U,0U,18U}}, +{DIVL_4C70,{1U,0U,18U}}, +{DIVL_4C70,{2U,0U,18U}}, +{DIVL_4C70,{3U,0U,18U}}, +{DIVL_4C70,{4U,0U,18U}}, +{DIVL_4C70,{5U,0U,18U}}, +{DIVL_4C70,{6U,0U,18U}}, +{DIVL_4C70,{7U,0U,18U}}, +{DIVL_4C78,{0U,0U,16U}}, +{DIVL_4C79,{0U,0U,20U}}, +{DIVL_4C7A,{0U,0U,16U}}, +{DIVL_4C7B,{0U,0U,18U}}, +{DIVL_4C7C,{0U,0U,12U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEM_4C90,{0U,12U,0U}}, +{MOVEM_4C90,{1U,12U,0U}}, +{MOVEM_4C90,{2U,12U,0U}}, +{MOVEM_4C90,{3U,12U,0U}}, +{MOVEM_4C90,{4U,12U,0U}}, +{MOVEM_4C90,{5U,12U,0U}}, +{MOVEM_4C90,{6U,12U,0U}}, +{MOVEM_4C90,{7U,12U,0U}}, +{MOVEM_4C98,{0U,0U,0U}}, +{MOVEM_4C98,{1U,0U,0U}}, +{MOVEM_4C98,{2U,0U,0U}}, +{MOVEM_4C98,{3U,0U,0U}}, +{MOVEM_4C98,{4U,0U,0U}}, +{MOVEM_4C98,{5U,0U,0U}}, +{MOVEM_4C98,{6U,0U,0U}}, +{MOVEM_4C98,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEM_4CA8,{0U,16U,0U}}, +{MOVEM_4CA8,{1U,16U,0U}}, +{MOVEM_4CA8,{2U,16U,0U}}, +{MOVEM_4CA8,{3U,16U,0U}}, +{MOVEM_4CA8,{4U,16U,0U}}, +{MOVEM_4CA8,{5U,16U,0U}}, +{MOVEM_4CA8,{6U,16U,0U}}, +{MOVEM_4CA8,{7U,16U,0U}}, +{MOVEM_4CB0,{0U,18U,0U}}, +{MOVEM_4CB0,{1U,18U,0U}}, +{MOVEM_4CB0,{2U,18U,0U}}, +{MOVEM_4CB0,{3U,18U,0U}}, +{MOVEM_4CB0,{4U,18U,0U}}, +{MOVEM_4CB0,{5U,18U,0U}}, +{MOVEM_4CB0,{6U,18U,0U}}, +{MOVEM_4CB0,{7U,18U,0U}}, +{MOVEM_4CB8,{0U,16U,0U}}, +{MOVEM_4CB9,{0U,20U,0U}}, +{MOVEM_4CBA,{0U,16U,0U}}, +{MOVEM_4CBB,{0U,18U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEM_4CD0,{0U,12U,0U}}, +{MOVEM_4CD0,{1U,12U,0U}}, +{MOVEM_4CD0,{2U,12U,0U}}, +{MOVEM_4CD0,{3U,12U,0U}}, +{MOVEM_4CD0,{4U,12U,0U}}, +{MOVEM_4CD0,{5U,12U,0U}}, +{MOVEM_4CD0,{6U,12U,0U}}, +{MOVEM_4CD0,{7U,12U,0U}}, +{MOVEM_4CD8,{0U,0U,0U}}, +{MOVEM_4CD8,{1U,0U,0U}}, +{MOVEM_4CD8,{2U,0U,0U}}, +{MOVEM_4CD8,{3U,0U,0U}}, +{MOVEM_4CD8,{4U,0U,0U}}, +{MOVEM_4CD8,{5U,0U,0U}}, +{MOVEM_4CD8,{6U,0U,0U}}, +{MOVEM_4CD8,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEM_4CE8,{0U,16U,0U}}, +{MOVEM_4CE8,{1U,16U,0U}}, +{MOVEM_4CE8,{2U,16U,0U}}, +{MOVEM_4CE8,{3U,16U,0U}}, +{MOVEM_4CE8,{4U,16U,0U}}, +{MOVEM_4CE8,{5U,16U,0U}}, +{MOVEM_4CE8,{6U,16U,0U}}, +{MOVEM_4CE8,{7U,16U,0U}}, +{MOVEM_4CF0,{0U,18U,0U}}, +{MOVEM_4CF0,{1U,18U,0U}}, +{MOVEM_4CF0,{2U,18U,0U}}, +{MOVEM_4CF0,{3U,18U,0U}}, +{MOVEM_4CF0,{4U,18U,0U}}, +{MOVEM_4CF0,{5U,18U,0U}}, +{MOVEM_4CF0,{6U,18U,0U}}, +{MOVEM_4CF0,{7U,18U,0U}}, +{MOVEM_4CF8,{0U,16U,0U}}, +{MOVEM_4CF9,{0U,20U,0U}}, +{MOVEM_4CFA,{0U,16U,0U}}, +{MOVEM_4CFB,{0U,18U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4100,{0U,6U,0U}}, +{CHK_4100,{1U,6U,0U}}, +{CHK_4100,{2U,6U,0U}}, +{CHK_4100,{3U,6U,0U}}, +{CHK_4100,{4U,6U,0U}}, +{CHK_4100,{5U,6U,0U}}, +{CHK_4100,{6U,6U,0U}}, +{CHK_4100,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4110,{0U,6U,0U}}, +{CHK_4110,{1U,6U,0U}}, +{CHK_4110,{2U,6U,0U}}, +{CHK_4110,{3U,6U,0U}}, +{CHK_4110,{4U,6U,0U}}, +{CHK_4110,{5U,6U,0U}}, +{CHK_4110,{6U,6U,0U}}, +{CHK_4110,{7U,6U,0U}}, +{CHK_4118,{0U,6U,0U}}, +{CHK_4118,{1U,6U,0U}}, +{CHK_4118,{2U,6U,0U}}, +{CHK_4118,{3U,6U,0U}}, +{CHK_4118,{4U,6U,0U}}, +{CHK_4118,{5U,6U,0U}}, +{CHK_4118,{6U,6U,0U}}, +{CHK_4118,{7U,6U,0U}}, +{CHK_4120,{0U,6U,0U}}, +{CHK_4120,{1U,6U,0U}}, +{CHK_4120,{2U,6U,0U}}, +{CHK_4120,{3U,6U,0U}}, +{CHK_4120,{4U,6U,0U}}, +{CHK_4120,{5U,6U,0U}}, +{CHK_4120,{6U,6U,0U}}, +{CHK_4120,{7U,6U,0U}}, +{CHK_4128,{0U,6U,0U}}, +{CHK_4128,{1U,6U,0U}}, +{CHK_4128,{2U,6U,0U}}, +{CHK_4128,{3U,6U,0U}}, +{CHK_4128,{4U,6U,0U}}, +{CHK_4128,{5U,6U,0U}}, +{CHK_4128,{6U,6U,0U}}, +{CHK_4128,{7U,6U,0U}}, +{CHK_4130,{0U,6U,0U}}, +{CHK_4130,{1U,6U,0U}}, +{CHK_4130,{2U,6U,0U}}, +{CHK_4130,{3U,6U,0U}}, +{CHK_4130,{4U,6U,0U}}, +{CHK_4130,{5U,6U,0U}}, +{CHK_4130,{6U,6U,0U}}, +{CHK_4130,{7U,6U,0U}}, +{CHK_4138,{0U,6U,0U}}, +{CHK_4139,{0U,6U,0U}}, +{CHK_413A,{0U,6U,0U}}, +{CHK_413B,{0U,6U,0U}}, +{CHK_413C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4180,{0U,6U,0U}}, +{CHK_4180,{1U,6U,0U}}, +{CHK_4180,{2U,6U,0U}}, +{CHK_4180,{3U,6U,0U}}, +{CHK_4180,{4U,6U,0U}}, +{CHK_4180,{5U,6U,0U}}, +{CHK_4180,{6U,6U,0U}}, +{CHK_4180,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4190,{0U,6U,0U}}, +{CHK_4190,{1U,6U,0U}}, +{CHK_4190,{2U,6U,0U}}, +{CHK_4190,{3U,6U,0U}}, +{CHK_4190,{4U,6U,0U}}, +{CHK_4190,{5U,6U,0U}}, +{CHK_4190,{6U,6U,0U}}, +{CHK_4190,{7U,6U,0U}}, +{CHK_4198,{0U,6U,0U}}, +{CHK_4198,{1U,6U,0U}}, +{CHK_4198,{2U,6U,0U}}, +{CHK_4198,{3U,6U,0U}}, +{CHK_4198,{4U,6U,0U}}, +{CHK_4198,{5U,6U,0U}}, +{CHK_4198,{6U,6U,0U}}, +{CHK_4198,{7U,6U,0U}}, +{CHK_41A0,{0U,6U,0U}}, +{CHK_41A0,{1U,6U,0U}}, +{CHK_41A0,{2U,6U,0U}}, +{CHK_41A0,{3U,6U,0U}}, +{CHK_41A0,{4U,6U,0U}}, +{CHK_41A0,{5U,6U,0U}}, +{CHK_41A0,{6U,6U,0U}}, +{CHK_41A0,{7U,6U,0U}}, +{CHK_41A8,{0U,6U,0U}}, +{CHK_41A8,{1U,6U,0U}}, +{CHK_41A8,{2U,6U,0U}}, +{CHK_41A8,{3U,6U,0U}}, +{CHK_41A8,{4U,6U,0U}}, +{CHK_41A8,{5U,6U,0U}}, +{CHK_41A8,{6U,6U,0U}}, +{CHK_41A8,{7U,6U,0U}}, +{CHK_41B0,{0U,6U,0U}}, +{CHK_41B0,{1U,6U,0U}}, +{CHK_41B0,{2U,6U,0U}}, +{CHK_41B0,{3U,6U,0U}}, +{CHK_41B0,{4U,6U,0U}}, +{CHK_41B0,{5U,6U,0U}}, +{CHK_41B0,{6U,6U,0U}}, +{CHK_41B0,{7U,6U,0U}}, +{CHK_41B8,{0U,6U,0U}}, +{CHK_41B9,{0U,6U,0U}}, +{CHK_41BA,{0U,6U,0U}}, +{CHK_41BB,{0U,6U,0U}}, +{CHK_41BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41D0,{0U,6U,0U}}, +{LEA_41D0,{1U,6U,0U}}, +{LEA_41D0,{2U,6U,0U}}, +{LEA_41D0,{3U,6U,0U}}, +{LEA_41D0,{4U,6U,0U}}, +{LEA_41D0,{5U,6U,0U}}, +{LEA_41D0,{6U,6U,0U}}, +{LEA_41D0,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41E8,{0U,6U,0U}}, +{LEA_41E8,{1U,6U,0U}}, +{LEA_41E8,{2U,6U,0U}}, +{LEA_41E8,{3U,6U,0U}}, +{LEA_41E8,{4U,6U,0U}}, +{LEA_41E8,{5U,6U,0U}}, +{LEA_41E8,{6U,6U,0U}}, +{LEA_41E8,{7U,6U,0U}}, +{LEA_41F0,{0U,6U,0U}}, +{LEA_41F0,{1U,6U,0U}}, +{LEA_41F0,{2U,6U,0U}}, +{LEA_41F0,{3U,6U,0U}}, +{LEA_41F0,{4U,6U,0U}}, +{LEA_41F0,{5U,6U,0U}}, +{LEA_41F0,{6U,6U,0U}}, +{LEA_41F0,{7U,6U,0U}}, +{LEA_41F8,{0U,6U,0U}}, +{LEA_41F9,{0U,6U,0U}}, +{LEA_41FA,{0U,6U,0U}}, +{LEA_41FB,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, 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+{JSR_4E90,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{JSR_4EA8,{0U,0U,0U}}, +{JSR_4EA8,{1U,0U,0U}}, +{JSR_4EA8,{2U,0U,0U}}, +{JSR_4EA8,{3U,0U,0U}}, +{JSR_4EA8,{4U,0U,0U}}, +{JSR_4EA8,{5U,0U,0U}}, +{JSR_4EA8,{6U,0U,0U}}, +{JSR_4EA8,{7U,0U,0U}}, +{JSR_4EB0,{0U,0U,0U}}, +{JSR_4EB0,{1U,0U,0U}}, +{JSR_4EB0,{2U,0U,0U}}, +{JSR_4EB0,{3U,0U,0U}}, +{JSR_4EB0,{4U,0U,0U}}, +{JSR_4EB0,{5U,0U,0U}}, +{JSR_4EB0,{6U,0U,0U}}, +{JSR_4EB0,{7U,0U,0U}}, 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+{JMP_4EF0,{7U,0U,0U}}, +{JMP_4EF8,{0U,0U,0U}}, +{JMP_4EF9,{0U,0U,0U}}, +{JMP_4EFA,{0U,0U,0U}}, +{JMP_4EFB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4100,{0U,7U,0U}}, +{CHK_4100,{1U,7U,0U}}, +{CHK_4100,{2U,7U,0U}}, +{CHK_4100,{3U,7U,0U}}, +{CHK_4100,{4U,7U,0U}}, +{CHK_4100,{5U,7U,0U}}, +{CHK_4100,{6U,7U,0U}}, +{CHK_4100,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CHK_4110,{0U,7U,0U}}, +{CHK_4110,{1U,7U,0U}}, +{CHK_4110,{2U,7U,0U}}, +{CHK_4110,{3U,7U,0U}}, +{CHK_4110,{4U,7U,0U}}, +{CHK_4110,{5U,7U,0U}}, +{CHK_4110,{6U,7U,0U}}, +{CHK_4110,{7U,7U,0U}}, +{CHK_4118,{0U,7U,0U}}, +{CHK_4118,{1U,7U,0U}}, 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+{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41D0,{0U,7U,0U}}, +{LEA_41D0,{1U,7U,0U}}, +{LEA_41D0,{2U,7U,0U}}, +{LEA_41D0,{3U,7U,0U}}, +{LEA_41D0,{4U,7U,0U}}, +{LEA_41D0,{5U,7U,0U}}, +{LEA_41D0,{6U,7U,0U}}, +{LEA_41D0,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LEA_41E8,{0U,7U,0U}}, +{LEA_41E8,{1U,7U,0U}}, +{LEA_41E8,{2U,7U,0U}}, +{LEA_41E8,{3U,7U,0U}}, +{LEA_41E8,{4U,7U,0U}}, +{LEA_41E8,{5U,7U,0U}}, +{LEA_41E8,{6U,7U,0U}}, +{LEA_41E8,{7U,7U,0U}}, +{LEA_41F0,{0U,7U,0U}}, +{LEA_41F0,{1U,7U,0U}}, +{LEA_41F0,{2U,7U,0U}}, +{LEA_41F0,{3U,7U,0U}}, +{LEA_41F0,{4U,7U,0U}}, +{LEA_41F0,{5U,7U,0U}}, +{LEA_41F0,{6U,7U,0U}}, +{LEA_41F0,{7U,7U,0U}}, +{LEA_41F8,{0U,7U,0U}}, +{LEA_41F9,{0U,7U,0U}}, +{LEA_41FA,{0U,7U,0U}}, +{LEA_41FB,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5000,{0U,8U,0U}}, +{ADDQ_5000,{1U,8U,0U}}, +{ADDQ_5000,{2U,8U,0U}}, +{ADDQ_5000,{3U,8U,0U}}, +{ADDQ_5000,{4U,8U,0U}}, +{ADDQ_5000,{5U,8U,0U}}, +{ADDQ_5000,{6U,8U,0U}}, +{ADDQ_5000,{7U,8U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5010,{0U,8U,0U}}, +{ADDQ_5010,{1U,8U,0U}}, +{ADDQ_5010,{2U,8U,0U}}, +{ADDQ_5010,{3U,8U,0U}}, +{ADDQ_5010,{4U,8U,0U}}, +{ADDQ_5010,{5U,8U,0U}}, +{ADDQ_5010,{6U,8U,0U}}, +{ADDQ_5010,{7U,8U,0U}}, +{ADDQ_5018,{0U,8U,0U}}, +{ADDQ_5018,{1U,8U,0U}}, +{ADDQ_5018,{2U,8U,0U}}, +{ADDQ_5018,{3U,8U,0U}}, +{ADDQ_5018,{4U,8U,0U}}, +{ADDQ_5018,{5U,8U,0U}}, +{ADDQ_5018,{6U,8U,0U}}, +{ADDQ_5018,{7U,8U,0U}}, +{ADDQ_5020,{0U,8U,0U}}, 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+{ADDQ_5068,{6U,8U,0U}}, +{ADDQ_5068,{7U,8U,0U}}, +{ADDQ_5070,{0U,8U,0U}}, +{ADDQ_5070,{1U,8U,0U}}, +{ADDQ_5070,{2U,8U,0U}}, +{ADDQ_5070,{3U,8U,0U}}, +{ADDQ_5070,{4U,8U,0U}}, +{ADDQ_5070,{5U,8U,0U}}, +{ADDQ_5070,{6U,8U,0U}}, +{ADDQ_5070,{7U,8U,0U}}, +{ADDQ_5078,{0U,8U,0U}}, +{ADDQ_5079,{0U,8U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5080,{0U,8U,0U}}, +{ADDQ_5080,{1U,8U,0U}}, +{ADDQ_5080,{2U,8U,0U}}, +{ADDQ_5080,{3U,8U,0U}}, +{ADDQ_5080,{4U,8U,0U}}, +{ADDQ_5080,{5U,8U,0U}}, +{ADDQ_5080,{6U,8U,0U}}, +{ADDQ_5080,{7U,8U,0U}}, +{ADDQ_5088,{0U,8U,0U}}, +{ADDQ_5088,{1U,8U,0U}}, +{ADDQ_5088,{2U,8U,0U}}, +{ADDQ_5088,{3U,8U,0U}}, +{ADDQ_5088,{4U,8U,0U}}, +{ADDQ_5088,{5U,8U,0U}}, +{ADDQ_5088,{6U,8U,0U}}, +{ADDQ_5088,{7U,8U,0U}}, +{ADDQ_5090,{0U,8U,0U}}, +{ADDQ_5090,{1U,8U,0U}}, +{ADDQ_5090,{2U,8U,0U}}, +{ADDQ_5090,{3U,8U,0U}}, +{ADDQ_5090,{4U,8U,0U}}, +{ADDQ_5090,{5U,8U,0U}}, +{ADDQ_5090,{6U,8U,0U}}, +{ADDQ_5090,{7U,8U,0U}}, +{ADDQ_5098,{0U,8U,0U}}, +{ADDQ_5098,{1U,8U,0U}}, +{ADDQ_5098,{2U,8U,0U}}, +{ADDQ_5098,{3U,8U,0U}}, +{ADDQ_5098,{4U,8U,0U}}, +{ADDQ_5098,{5U,8U,0U}}, +{ADDQ_5098,{6U,8U,0U}}, +{ADDQ_5098,{7U,8U,0U}}, +{ADDQ_50A0,{0U,8U,0U}}, +{ADDQ_50A0,{1U,8U,0U}}, +{ADDQ_50A0,{2U,8U,0U}}, +{ADDQ_50A0,{3U,8U,0U}}, +{ADDQ_50A0,{4U,8U,0U}}, +{ADDQ_50A0,{5U,8U,0U}}, +{ADDQ_50A0,{6U,8U,0U}}, +{ADDQ_50A0,{7U,8U,0U}}, +{ADDQ_50A8,{0U,8U,0U}}, +{ADDQ_50A8,{1U,8U,0U}}, +{ADDQ_50A8,{2U,8U,0U}}, +{ADDQ_50A8,{3U,8U,0U}}, +{ADDQ_50A8,{4U,8U,0U}}, +{ADDQ_50A8,{5U,8U,0U}}, +{ADDQ_50A8,{6U,8U,0U}}, +{ADDQ_50A8,{7U,8U,0U}}, +{ADDQ_50B0,{0U,8U,0U}}, +{ADDQ_50B0,{1U,8U,0U}}, +{ADDQ_50B0,{2U,8U,0U}}, +{ADDQ_50B0,{3U,8U,0U}}, +{ADDQ_50B0,{4U,8U,0U}}, +{ADDQ_50B0,{5U,8U,0U}}, +{ADDQ_50B0,{6U,8U,0U}}, +{ADDQ_50B0,{7U,8U,0U}}, +{ADDQ_50B8,{0U,8U,0U}}, +{ADDQ_50B9,{0U,8U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,0U,0U}}, +{SCC_50C0,{1U,0U,0U}}, +{SCC_50C0,{2U,0U,0U}}, +{SCC_50C0,{3U,0U,0U}}, +{SCC_50C0,{4U,0U,0U}}, +{SCC_50C0,{5U,0U,0U}}, +{SCC_50C0,{6U,0U,0U}}, +{SCC_50C0,{7U,0U,0U}}, +{DBCC_50C8,{0U,0U,0U}}, +{DBCC_50C8,{0U,1U,0U}}, +{DBCC_50C8,{0U,2U,0U}}, +{DBCC_50C8,{0U,3U,0U}}, +{DBCC_50C8,{0U,4U,0U}}, +{DBCC_50C8,{0U,5U,0U}}, +{DBCC_50C8,{0U,6U,0U}}, +{DBCC_50C8,{0U,7U,0U}}, +{SCC_50D0,{0U,0U,0U}}, +{SCC_50D0,{1U,0U,0U}}, +{SCC_50D0,{2U,0U,0U}}, +{SCC_50D0,{3U,0U,0U}}, +{SCC_50D0,{4U,0U,0U}}, +{SCC_50D0,{5U,0U,0U}}, +{SCC_50D0,{6U,0U,0U}}, +{SCC_50D0,{7U,0U,0U}}, +{SCC_50D8,{0U,0U,0U}}, +{SCC_50D8,{1U,0U,0U}}, +{SCC_50D8,{2U,0U,0U}}, +{SCC_50D8,{3U,0U,0U}}, +{SCC_50D8,{4U,0U,0U}}, +{SCC_50D8,{5U,0U,0U}}, +{SCC_50D8,{6U,0U,0U}}, +{SCC_50D8,{7U,0U,0U}}, +{SCC_50E0,{0U,0U,0U}}, +{SCC_50E0,{1U,0U,0U}}, +{SCC_50E0,{2U,0U,0U}}, +{SCC_50E0,{3U,0U,0U}}, +{SCC_50E0,{4U,0U,0U}}, +{SCC_50E0,{5U,0U,0U}}, +{SCC_50E0,{6U,0U,0U}}, +{SCC_50E0,{7U,0U,0U}}, +{SCC_50E8,{0U,0U,0U}}, +{SCC_50E8,{1U,0U,0U}}, +{SCC_50E8,{2U,0U,0U}}, +{SCC_50E8,{3U,0U,0U}}, +{SCC_50E8,{4U,0U,0U}}, +{SCC_50E8,{5U,0U,0U}}, +{SCC_50E8,{6U,0U,0U}}, +{SCC_50E8,{7U,0U,0U}}, +{SCC_50F0,{0U,0U,0U}}, +{SCC_50F0,{1U,0U,0U}}, +{SCC_50F0,{2U,0U,0U}}, +{SCC_50F0,{3U,0U,0U}}, +{SCC_50F0,{4U,0U,0U}}, +{SCC_50F0,{5U,0U,0U}}, +{SCC_50F0,{6U,0U,0U}}, +{SCC_50F0,{7U,0U,0U}}, +{SCC_50F8,{0U,0U,0U}}, +{SCC_50F9,{0U,0U,0U}}, +{TRAPCC_50FA,{0U,0U,0U}}, +{TRAPCC_50FB,{0U,0U,0U}}, +{TRAPCC_50FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5100,{0U,8U,0U}}, +{SUBQ_5100,{1U,8U,0U}}, +{SUBQ_5100,{2U,8U,0U}}, +{SUBQ_5100,{3U,8U,0U}}, +{SUBQ_5100,{4U,8U,0U}}, +{SUBQ_5100,{5U,8U,0U}}, +{SUBQ_5100,{6U,8U,0U}}, +{SUBQ_5100,{7U,8U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5110,{0U,8U,0U}}, +{SUBQ_5110,{1U,8U,0U}}, +{SUBQ_5110,{2U,8U,0U}}, +{SUBQ_5110,{3U,8U,0U}}, +{SUBQ_5110,{4U,8U,0U}}, +{SUBQ_5110,{5U,8U,0U}}, +{SUBQ_5110,{6U,8U,0U}}, +{SUBQ_5110,{7U,8U,0U}}, +{SUBQ_5118,{0U,8U,0U}}, +{SUBQ_5118,{1U,8U,0U}}, +{SUBQ_5118,{2U,8U,0U}}, +{SUBQ_5118,{3U,8U,0U}}, +{SUBQ_5118,{4U,8U,0U}}, +{SUBQ_5118,{5U,8U,0U}}, +{SUBQ_5118,{6U,8U,0U}}, +{SUBQ_5118,{7U,8U,0U}}, +{SUBQ_5120,{0U,8U,0U}}, +{SUBQ_5120,{1U,8U,0U}}, +{SUBQ_5120,{2U,8U,0U}}, +{SUBQ_5120,{3U,8U,0U}}, +{SUBQ_5120,{4U,8U,0U}}, +{SUBQ_5120,{5U,8U,0U}}, +{SUBQ_5120,{6U,8U,0U}}, +{SUBQ_5120,{7U,8U,0U}}, +{SUBQ_5128,{0U,8U,0U}}, +{SUBQ_5128,{1U,8U,0U}}, +{SUBQ_5128,{2U,8U,0U}}, +{SUBQ_5128,{3U,8U,0U}}, +{SUBQ_5128,{4U,8U,0U}}, +{SUBQ_5128,{5U,8U,0U}}, +{SUBQ_5128,{6U,8U,0U}}, +{SUBQ_5128,{7U,8U,0U}}, +{SUBQ_5130,{0U,8U,0U}}, +{SUBQ_5130,{1U,8U,0U}}, +{SUBQ_5130,{2U,8U,0U}}, +{SUBQ_5130,{3U,8U,0U}}, +{SUBQ_5130,{4U,8U,0U}}, +{SUBQ_5130,{5U,8U,0U}}, +{SUBQ_5130,{6U,8U,0U}}, +{SUBQ_5130,{7U,8U,0U}}, +{SUBQ_5138,{0U,8U,0U}}, +{SUBQ_5139,{0U,8U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5140,{0U,8U,0U}}, +{SUBQ_5140,{1U,8U,0U}}, +{SUBQ_5140,{2U,8U,0U}}, +{SUBQ_5140,{3U,8U,0U}}, +{SUBQ_5140,{4U,8U,0U}}, +{SUBQ_5140,{5U,8U,0U}}, +{SUBQ_5140,{6U,8U,0U}}, +{SUBQ_5140,{7U,8U,0U}}, +{SUBQ_5148,{0U,8U,0U}}, +{SUBQ_5148,{1U,8U,0U}}, +{SUBQ_5148,{2U,8U,0U}}, +{SUBQ_5148,{3U,8U,0U}}, +{SUBQ_5148,{4U,8U,0U}}, +{SUBQ_5148,{5U,8U,0U}}, +{SUBQ_5148,{6U,8U,0U}}, +{SUBQ_5148,{7U,8U,0U}}, +{SUBQ_5150,{0U,8U,0U}}, +{SUBQ_5150,{1U,8U,0U}}, +{SUBQ_5150,{2U,8U,0U}}, +{SUBQ_5150,{3U,8U,0U}}, +{SUBQ_5150,{4U,8U,0U}}, +{SUBQ_5150,{5U,8U,0U}}, +{SUBQ_5150,{6U,8U,0U}}, +{SUBQ_5150,{7U,8U,0U}}, +{SUBQ_5158,{0U,8U,0U}}, +{SUBQ_5158,{1U,8U,0U}}, +{SUBQ_5158,{2U,8U,0U}}, +{SUBQ_5158,{3U,8U,0U}}, +{SUBQ_5158,{4U,8U,0U}}, +{SUBQ_5158,{5U,8U,0U}}, +{SUBQ_5158,{6U,8U,0U}}, +{SUBQ_5158,{7U,8U,0U}}, +{SUBQ_5160,{0U,8U,0U}}, +{SUBQ_5160,{1U,8U,0U}}, +{SUBQ_5160,{2U,8U,0U}}, +{SUBQ_5160,{3U,8U,0U}}, +{SUBQ_5160,{4U,8U,0U}}, +{SUBQ_5160,{5U,8U,0U}}, +{SUBQ_5160,{6U,8U,0U}}, +{SUBQ_5160,{7U,8U,0U}}, +{SUBQ_5168,{0U,8U,0U}}, +{SUBQ_5168,{1U,8U,0U}}, +{SUBQ_5168,{2U,8U,0U}}, +{SUBQ_5168,{3U,8U,0U}}, +{SUBQ_5168,{4U,8U,0U}}, +{SUBQ_5168,{5U,8U,0U}}, +{SUBQ_5168,{6U,8U,0U}}, +{SUBQ_5168,{7U,8U,0U}}, +{SUBQ_5170,{0U,8U,0U}}, +{SUBQ_5170,{1U,8U,0U}}, +{SUBQ_5170,{2U,8U,0U}}, +{SUBQ_5170,{3U,8U,0U}}, +{SUBQ_5170,{4U,8U,0U}}, +{SUBQ_5170,{5U,8U,0U}}, +{SUBQ_5170,{6U,8U,0U}}, +{SUBQ_5170,{7U,8U,0U}}, +{SUBQ_5178,{0U,8U,0U}}, +{SUBQ_5179,{0U,8U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5180,{0U,8U,0U}}, +{SUBQ_5180,{1U,8U,0U}}, +{SUBQ_5180,{2U,8U,0U}}, +{SUBQ_5180,{3U,8U,0U}}, +{SUBQ_5180,{4U,8U,0U}}, +{SUBQ_5180,{5U,8U,0U}}, +{SUBQ_5180,{6U,8U,0U}}, +{SUBQ_5180,{7U,8U,0U}}, +{SUBQ_5188,{0U,8U,0U}}, +{SUBQ_5188,{1U,8U,0U}}, +{SUBQ_5188,{2U,8U,0U}}, +{SUBQ_5188,{3U,8U,0U}}, +{SUBQ_5188,{4U,8U,0U}}, +{SUBQ_5188,{5U,8U,0U}}, +{SUBQ_5188,{6U,8U,0U}}, +{SUBQ_5188,{7U,8U,0U}}, +{SUBQ_5190,{0U,8U,0U}}, +{SUBQ_5190,{1U,8U,0U}}, +{SUBQ_5190,{2U,8U,0U}}, +{SUBQ_5190,{3U,8U,0U}}, +{SUBQ_5190,{4U,8U,0U}}, +{SUBQ_5190,{5U,8U,0U}}, +{SUBQ_5190,{6U,8U,0U}}, +{SUBQ_5190,{7U,8U,0U}}, +{SUBQ_5198,{0U,8U,0U}}, +{SUBQ_5198,{1U,8U,0U}}, +{SUBQ_5198,{2U,8U,0U}}, +{SUBQ_5198,{3U,8U,0U}}, +{SUBQ_5198,{4U,8U,0U}}, +{SUBQ_5198,{5U,8U,0U}}, +{SUBQ_5198,{6U,8U,0U}}, +{SUBQ_5198,{7U,8U,0U}}, +{SUBQ_51A0,{0U,8U,0U}}, +{SUBQ_51A0,{1U,8U,0U}}, +{SUBQ_51A0,{2U,8U,0U}}, +{SUBQ_51A0,{3U,8U,0U}}, +{SUBQ_51A0,{4U,8U,0U}}, +{SUBQ_51A0,{5U,8U,0U}}, +{SUBQ_51A0,{6U,8U,0U}}, +{SUBQ_51A0,{7U,8U,0U}}, +{SUBQ_51A8,{0U,8U,0U}}, +{SUBQ_51A8,{1U,8U,0U}}, +{SUBQ_51A8,{2U,8U,0U}}, +{SUBQ_51A8,{3U,8U,0U}}, +{SUBQ_51A8,{4U,8U,0U}}, +{SUBQ_51A8,{5U,8U,0U}}, +{SUBQ_51A8,{6U,8U,0U}}, +{SUBQ_51A8,{7U,8U,0U}}, +{SUBQ_51B0,{0U,8U,0U}}, +{SUBQ_51B0,{1U,8U,0U}}, +{SUBQ_51B0,{2U,8U,0U}}, +{SUBQ_51B0,{3U,8U,0U}}, +{SUBQ_51B0,{4U,8U,0U}}, +{SUBQ_51B0,{5U,8U,0U}}, +{SUBQ_51B0,{6U,8U,0U}}, +{SUBQ_51B0,{7U,8U,0U}}, +{SUBQ_51B8,{0U,8U,0U}}, +{SUBQ_51B9,{0U,8U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,1U,0U}}, +{SCC_50C0,{1U,1U,0U}}, +{SCC_50C0,{2U,1U,0U}}, +{SCC_50C0,{3U,1U,0U}}, +{SCC_50C0,{4U,1U,0U}}, +{SCC_50C0,{5U,1U,0U}}, +{SCC_50C0,{6U,1U,0U}}, +{SCC_50C0,{7U,1U,0U}}, +{DBCC_51C8,{0U,0U,0U}}, +{DBCC_51C8,{0U,1U,0U}}, +{DBCC_51C8,{0U,2U,0U}}, +{DBCC_51C8,{0U,3U,0U}}, +{DBCC_51C8,{0U,4U,0U}}, +{DBCC_51C8,{0U,5U,0U}}, +{DBCC_51C8,{0U,6U,0U}}, +{DBCC_51C8,{0U,7U,0U}}, +{SCC_50D0,{0U,1U,0U}}, +{SCC_50D0,{1U,1U,0U}}, +{SCC_50D0,{2U,1U,0U}}, +{SCC_50D0,{3U,1U,0U}}, +{SCC_50D0,{4U,1U,0U}}, +{SCC_50D0,{5U,1U,0U}}, +{SCC_50D0,{6U,1U,0U}}, +{SCC_50D0,{7U,1U,0U}}, +{SCC_50D8,{0U,1U,0U}}, +{SCC_50D8,{1U,1U,0U}}, +{SCC_50D8,{2U,1U,0U}}, +{SCC_50D8,{3U,1U,0U}}, +{SCC_50D8,{4U,1U,0U}}, +{SCC_50D8,{5U,1U,0U}}, +{SCC_50D8,{6U,1U,0U}}, +{SCC_50D8,{7U,1U,0U}}, +{SCC_50E0,{0U,1U,0U}}, +{SCC_50E0,{1U,1U,0U}}, +{SCC_50E0,{2U,1U,0U}}, +{SCC_50E0,{3U,1U,0U}}, +{SCC_50E0,{4U,1U,0U}}, +{SCC_50E0,{5U,1U,0U}}, +{SCC_50E0,{6U,1U,0U}}, +{SCC_50E0,{7U,1U,0U}}, +{SCC_50E8,{0U,1U,0U}}, +{SCC_50E8,{1U,1U,0U}}, +{SCC_50E8,{2U,1U,0U}}, +{SCC_50E8,{3U,1U,0U}}, +{SCC_50E8,{4U,1U,0U}}, +{SCC_50E8,{5U,1U,0U}}, +{SCC_50E8,{6U,1U,0U}}, +{SCC_50E8,{7U,1U,0U}}, +{SCC_50F0,{0U,1U,0U}}, +{SCC_50F0,{1U,1U,0U}}, +{SCC_50F0,{2U,1U,0U}}, +{SCC_50F0,{3U,1U,0U}}, +{SCC_50F0,{4U,1U,0U}}, +{SCC_50F0,{5U,1U,0U}}, +{SCC_50F0,{6U,1U,0U}}, +{SCC_50F0,{7U,1U,0U}}, +{SCC_50F8,{0U,1U,0U}}, +{SCC_50F9,{0U,1U,0U}}, +{TRAPCC_51FA,{0U,0U,0U}}, +{TRAPCC_51FB,{0U,0U,0U}}, +{TRAPCC_51FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5000,{0U,1U,0U}}, +{ADDQ_5000,{1U,1U,0U}}, +{ADDQ_5000,{2U,1U,0U}}, +{ADDQ_5000,{3U,1U,0U}}, +{ADDQ_5000,{4U,1U,0U}}, +{ADDQ_5000,{5U,1U,0U}}, +{ADDQ_5000,{6U,1U,0U}}, +{ADDQ_5000,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5010,{0U,1U,0U}}, +{ADDQ_5010,{1U,1U,0U}}, +{ADDQ_5010,{2U,1U,0U}}, +{ADDQ_5010,{3U,1U,0U}}, +{ADDQ_5010,{4U,1U,0U}}, +{ADDQ_5010,{5U,1U,0U}}, +{ADDQ_5010,{6U,1U,0U}}, +{ADDQ_5010,{7U,1U,0U}}, +{ADDQ_5018,{0U,1U,0U}}, +{ADDQ_5018,{1U,1U,0U}}, +{ADDQ_5018,{2U,1U,0U}}, +{ADDQ_5018,{3U,1U,0U}}, +{ADDQ_5018,{4U,1U,0U}}, +{ADDQ_5018,{5U,1U,0U}}, +{ADDQ_5018,{6U,1U,0U}}, +{ADDQ_5018,{7U,1U,0U}}, +{ADDQ_5020,{0U,1U,0U}}, +{ADDQ_5020,{1U,1U,0U}}, +{ADDQ_5020,{2U,1U,0U}}, +{ADDQ_5020,{3U,1U,0U}}, +{ADDQ_5020,{4U,1U,0U}}, +{ADDQ_5020,{5U,1U,0U}}, +{ADDQ_5020,{6U,1U,0U}}, +{ADDQ_5020,{7U,1U,0U}}, +{ADDQ_5028,{0U,1U,0U}}, +{ADDQ_5028,{1U,1U,0U}}, +{ADDQ_5028,{2U,1U,0U}}, +{ADDQ_5028,{3U,1U,0U}}, +{ADDQ_5028,{4U,1U,0U}}, +{ADDQ_5028,{5U,1U,0U}}, +{ADDQ_5028,{6U,1U,0U}}, +{ADDQ_5028,{7U,1U,0U}}, +{ADDQ_5030,{0U,1U,0U}}, +{ADDQ_5030,{1U,1U,0U}}, +{ADDQ_5030,{2U,1U,0U}}, +{ADDQ_5030,{3U,1U,0U}}, +{ADDQ_5030,{4U,1U,0U}}, +{ADDQ_5030,{5U,1U,0U}}, +{ADDQ_5030,{6U,1U,0U}}, +{ADDQ_5030,{7U,1U,0U}}, +{ADDQ_5038,{0U,1U,0U}}, +{ADDQ_5039,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5040,{0U,1U,0U}}, +{ADDQ_5040,{1U,1U,0U}}, +{ADDQ_5040,{2U,1U,0U}}, +{ADDQ_5040,{3U,1U,0U}}, +{ADDQ_5040,{4U,1U,0U}}, +{ADDQ_5040,{5U,1U,0U}}, +{ADDQ_5040,{6U,1U,0U}}, +{ADDQ_5040,{7U,1U,0U}}, +{ADDQ_5048,{0U,1U,0U}}, +{ADDQ_5048,{1U,1U,0U}}, +{ADDQ_5048,{2U,1U,0U}}, +{ADDQ_5048,{3U,1U,0U}}, +{ADDQ_5048,{4U,1U,0U}}, +{ADDQ_5048,{5U,1U,0U}}, +{ADDQ_5048,{6U,1U,0U}}, +{ADDQ_5048,{7U,1U,0U}}, +{ADDQ_5050,{0U,1U,0U}}, +{ADDQ_5050,{1U,1U,0U}}, +{ADDQ_5050,{2U,1U,0U}}, +{ADDQ_5050,{3U,1U,0U}}, +{ADDQ_5050,{4U,1U,0U}}, +{ADDQ_5050,{5U,1U,0U}}, +{ADDQ_5050,{6U,1U,0U}}, +{ADDQ_5050,{7U,1U,0U}}, +{ADDQ_5058,{0U,1U,0U}}, +{ADDQ_5058,{1U,1U,0U}}, +{ADDQ_5058,{2U,1U,0U}}, +{ADDQ_5058,{3U,1U,0U}}, +{ADDQ_5058,{4U,1U,0U}}, +{ADDQ_5058,{5U,1U,0U}}, +{ADDQ_5058,{6U,1U,0U}}, +{ADDQ_5058,{7U,1U,0U}}, +{ADDQ_5060,{0U,1U,0U}}, +{ADDQ_5060,{1U,1U,0U}}, +{ADDQ_5060,{2U,1U,0U}}, +{ADDQ_5060,{3U,1U,0U}}, +{ADDQ_5060,{4U,1U,0U}}, +{ADDQ_5060,{5U,1U,0U}}, +{ADDQ_5060,{6U,1U,0U}}, +{ADDQ_5060,{7U,1U,0U}}, +{ADDQ_5068,{0U,1U,0U}}, +{ADDQ_5068,{1U,1U,0U}}, +{ADDQ_5068,{2U,1U,0U}}, +{ADDQ_5068,{3U,1U,0U}}, +{ADDQ_5068,{4U,1U,0U}}, +{ADDQ_5068,{5U,1U,0U}}, +{ADDQ_5068,{6U,1U,0U}}, +{ADDQ_5068,{7U,1U,0U}}, +{ADDQ_5070,{0U,1U,0U}}, +{ADDQ_5070,{1U,1U,0U}}, +{ADDQ_5070,{2U,1U,0U}}, +{ADDQ_5070,{3U,1U,0U}}, +{ADDQ_5070,{4U,1U,0U}}, +{ADDQ_5070,{5U,1U,0U}}, +{ADDQ_5070,{6U,1U,0U}}, +{ADDQ_5070,{7U,1U,0U}}, +{ADDQ_5078,{0U,1U,0U}}, +{ADDQ_5079,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5080,{0U,1U,0U}}, +{ADDQ_5080,{1U,1U,0U}}, +{ADDQ_5080,{2U,1U,0U}}, +{ADDQ_5080,{3U,1U,0U}}, +{ADDQ_5080,{4U,1U,0U}}, +{ADDQ_5080,{5U,1U,0U}}, +{ADDQ_5080,{6U,1U,0U}}, +{ADDQ_5080,{7U,1U,0U}}, +{ADDQ_5088,{0U,1U,0U}}, +{ADDQ_5088,{1U,1U,0U}}, +{ADDQ_5088,{2U,1U,0U}}, +{ADDQ_5088,{3U,1U,0U}}, +{ADDQ_5088,{4U,1U,0U}}, +{ADDQ_5088,{5U,1U,0U}}, +{ADDQ_5088,{6U,1U,0U}}, +{ADDQ_5088,{7U,1U,0U}}, +{ADDQ_5090,{0U,1U,0U}}, +{ADDQ_5090,{1U,1U,0U}}, +{ADDQ_5090,{2U,1U,0U}}, +{ADDQ_5090,{3U,1U,0U}}, +{ADDQ_5090,{4U,1U,0U}}, +{ADDQ_5090,{5U,1U,0U}}, +{ADDQ_5090,{6U,1U,0U}}, +{ADDQ_5090,{7U,1U,0U}}, +{ADDQ_5098,{0U,1U,0U}}, +{ADDQ_5098,{1U,1U,0U}}, +{ADDQ_5098,{2U,1U,0U}}, +{ADDQ_5098,{3U,1U,0U}}, +{ADDQ_5098,{4U,1U,0U}}, +{ADDQ_5098,{5U,1U,0U}}, +{ADDQ_5098,{6U,1U,0U}}, +{ADDQ_5098,{7U,1U,0U}}, +{ADDQ_50A0,{0U,1U,0U}}, +{ADDQ_50A0,{1U,1U,0U}}, +{ADDQ_50A0,{2U,1U,0U}}, +{ADDQ_50A0,{3U,1U,0U}}, +{ADDQ_50A0,{4U,1U,0U}}, +{ADDQ_50A0,{5U,1U,0U}}, +{ADDQ_50A0,{6U,1U,0U}}, +{ADDQ_50A0,{7U,1U,0U}}, +{ADDQ_50A8,{0U,1U,0U}}, +{ADDQ_50A8,{1U,1U,0U}}, +{ADDQ_50A8,{2U,1U,0U}}, +{ADDQ_50A8,{3U,1U,0U}}, +{ADDQ_50A8,{4U,1U,0U}}, +{ADDQ_50A8,{5U,1U,0U}}, +{ADDQ_50A8,{6U,1U,0U}}, +{ADDQ_50A8,{7U,1U,0U}}, +{ADDQ_50B0,{0U,1U,0U}}, +{ADDQ_50B0,{1U,1U,0U}}, +{ADDQ_50B0,{2U,1U,0U}}, +{ADDQ_50B0,{3U,1U,0U}}, +{ADDQ_50B0,{4U,1U,0U}}, +{ADDQ_50B0,{5U,1U,0U}}, +{ADDQ_50B0,{6U,1U,0U}}, +{ADDQ_50B0,{7U,1U,0U}}, +{ADDQ_50B8,{0U,1U,0U}}, +{ADDQ_50B9,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,2U,0U}}, +{SCC_50C0,{1U,2U,0U}}, +{SCC_50C0,{2U,2U,0U}}, +{SCC_50C0,{3U,2U,0U}}, +{SCC_50C0,{4U,2U,0U}}, +{SCC_50C0,{5U,2U,0U}}, +{SCC_50C0,{6U,2U,0U}}, +{SCC_50C0,{7U,2U,0U}}, +{DBCC_52C8,{0U,0U,0U}}, +{DBCC_52C8,{0U,1U,0U}}, +{DBCC_52C8,{0U,2U,0U}}, +{DBCC_52C8,{0U,3U,0U}}, +{DBCC_52C8,{0U,4U,0U}}, +{DBCC_52C8,{0U,5U,0U}}, +{DBCC_52C8,{0U,6U,0U}}, +{DBCC_52C8,{0U,7U,0U}}, +{SCC_50D0,{0U,2U,0U}}, +{SCC_50D0,{1U,2U,0U}}, +{SCC_50D0,{2U,2U,0U}}, +{SCC_50D0,{3U,2U,0U}}, +{SCC_50D0,{4U,2U,0U}}, +{SCC_50D0,{5U,2U,0U}}, +{SCC_50D0,{6U,2U,0U}}, +{SCC_50D0,{7U,2U,0U}}, +{SCC_50D8,{0U,2U,0U}}, +{SCC_50D8,{1U,2U,0U}}, +{SCC_50D8,{2U,2U,0U}}, +{SCC_50D8,{3U,2U,0U}}, +{SCC_50D8,{4U,2U,0U}}, +{SCC_50D8,{5U,2U,0U}}, +{SCC_50D8,{6U,2U,0U}}, +{SCC_50D8,{7U,2U,0U}}, +{SCC_50E0,{0U,2U,0U}}, +{SCC_50E0,{1U,2U,0U}}, +{SCC_50E0,{2U,2U,0U}}, +{SCC_50E0,{3U,2U,0U}}, +{SCC_50E0,{4U,2U,0U}}, +{SCC_50E0,{5U,2U,0U}}, +{SCC_50E0,{6U,2U,0U}}, +{SCC_50E0,{7U,2U,0U}}, +{SCC_50E8,{0U,2U,0U}}, +{SCC_50E8,{1U,2U,0U}}, +{SCC_50E8,{2U,2U,0U}}, +{SCC_50E8,{3U,2U,0U}}, +{SCC_50E8,{4U,2U,0U}}, +{SCC_50E8,{5U,2U,0U}}, +{SCC_50E8,{6U,2U,0U}}, +{SCC_50E8,{7U,2U,0U}}, +{SCC_50F0,{0U,2U,0U}}, +{SCC_50F0,{1U,2U,0U}}, +{SCC_50F0,{2U,2U,0U}}, +{SCC_50F0,{3U,2U,0U}}, +{SCC_50F0,{4U,2U,0U}}, +{SCC_50F0,{5U,2U,0U}}, +{SCC_50F0,{6U,2U,0U}}, +{SCC_50F0,{7U,2U,0U}}, +{SCC_50F8,{0U,2U,0U}}, +{SCC_50F9,{0U,2U,0U}}, +{TRAPCC_52FA,{0U,0U,0U}}, +{TRAPCC_52FB,{0U,0U,0U}}, +{TRAPCC_52FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5100,{0U,1U,0U}}, +{SUBQ_5100,{1U,1U,0U}}, +{SUBQ_5100,{2U,1U,0U}}, +{SUBQ_5100,{3U,1U,0U}}, +{SUBQ_5100,{4U,1U,0U}}, +{SUBQ_5100,{5U,1U,0U}}, +{SUBQ_5100,{6U,1U,0U}}, +{SUBQ_5100,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5110,{0U,1U,0U}}, +{SUBQ_5110,{1U,1U,0U}}, +{SUBQ_5110,{2U,1U,0U}}, +{SUBQ_5110,{3U,1U,0U}}, +{SUBQ_5110,{4U,1U,0U}}, +{SUBQ_5110,{5U,1U,0U}}, +{SUBQ_5110,{6U,1U,0U}}, +{SUBQ_5110,{7U,1U,0U}}, +{SUBQ_5118,{0U,1U,0U}}, +{SUBQ_5118,{1U,1U,0U}}, +{SUBQ_5118,{2U,1U,0U}}, +{SUBQ_5118,{3U,1U,0U}}, +{SUBQ_5118,{4U,1U,0U}}, +{SUBQ_5118,{5U,1U,0U}}, +{SUBQ_5118,{6U,1U,0U}}, +{SUBQ_5118,{7U,1U,0U}}, +{SUBQ_5120,{0U,1U,0U}}, +{SUBQ_5120,{1U,1U,0U}}, +{SUBQ_5120,{2U,1U,0U}}, +{SUBQ_5120,{3U,1U,0U}}, +{SUBQ_5120,{4U,1U,0U}}, +{SUBQ_5120,{5U,1U,0U}}, +{SUBQ_5120,{6U,1U,0U}}, +{SUBQ_5120,{7U,1U,0U}}, +{SUBQ_5128,{0U,1U,0U}}, +{SUBQ_5128,{1U,1U,0U}}, +{SUBQ_5128,{2U,1U,0U}}, +{SUBQ_5128,{3U,1U,0U}}, +{SUBQ_5128,{4U,1U,0U}}, +{SUBQ_5128,{5U,1U,0U}}, +{SUBQ_5128,{6U,1U,0U}}, +{SUBQ_5128,{7U,1U,0U}}, +{SUBQ_5130,{0U,1U,0U}}, +{SUBQ_5130,{1U,1U,0U}}, +{SUBQ_5130,{2U,1U,0U}}, +{SUBQ_5130,{3U,1U,0U}}, +{SUBQ_5130,{4U,1U,0U}}, +{SUBQ_5130,{5U,1U,0U}}, +{SUBQ_5130,{6U,1U,0U}}, +{SUBQ_5130,{7U,1U,0U}}, +{SUBQ_5138,{0U,1U,0U}}, +{SUBQ_5139,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5140,{0U,1U,0U}}, +{SUBQ_5140,{1U,1U,0U}}, +{SUBQ_5140,{2U,1U,0U}}, +{SUBQ_5140,{3U,1U,0U}}, +{SUBQ_5140,{4U,1U,0U}}, +{SUBQ_5140,{5U,1U,0U}}, +{SUBQ_5140,{6U,1U,0U}}, +{SUBQ_5140,{7U,1U,0U}}, +{SUBQ_5148,{0U,1U,0U}}, +{SUBQ_5148,{1U,1U,0U}}, +{SUBQ_5148,{2U,1U,0U}}, +{SUBQ_5148,{3U,1U,0U}}, +{SUBQ_5148,{4U,1U,0U}}, +{SUBQ_5148,{5U,1U,0U}}, +{SUBQ_5148,{6U,1U,0U}}, +{SUBQ_5148,{7U,1U,0U}}, +{SUBQ_5150,{0U,1U,0U}}, +{SUBQ_5150,{1U,1U,0U}}, +{SUBQ_5150,{2U,1U,0U}}, +{SUBQ_5150,{3U,1U,0U}}, +{SUBQ_5150,{4U,1U,0U}}, +{SUBQ_5150,{5U,1U,0U}}, +{SUBQ_5150,{6U,1U,0U}}, +{SUBQ_5150,{7U,1U,0U}}, +{SUBQ_5158,{0U,1U,0U}}, +{SUBQ_5158,{1U,1U,0U}}, +{SUBQ_5158,{2U,1U,0U}}, +{SUBQ_5158,{3U,1U,0U}}, +{SUBQ_5158,{4U,1U,0U}}, +{SUBQ_5158,{5U,1U,0U}}, +{SUBQ_5158,{6U,1U,0U}}, +{SUBQ_5158,{7U,1U,0U}}, +{SUBQ_5160,{0U,1U,0U}}, +{SUBQ_5160,{1U,1U,0U}}, +{SUBQ_5160,{2U,1U,0U}}, +{SUBQ_5160,{3U,1U,0U}}, +{SUBQ_5160,{4U,1U,0U}}, +{SUBQ_5160,{5U,1U,0U}}, +{SUBQ_5160,{6U,1U,0U}}, +{SUBQ_5160,{7U,1U,0U}}, +{SUBQ_5168,{0U,1U,0U}}, +{SUBQ_5168,{1U,1U,0U}}, +{SUBQ_5168,{2U,1U,0U}}, +{SUBQ_5168,{3U,1U,0U}}, +{SUBQ_5168,{4U,1U,0U}}, +{SUBQ_5168,{5U,1U,0U}}, +{SUBQ_5168,{6U,1U,0U}}, +{SUBQ_5168,{7U,1U,0U}}, +{SUBQ_5170,{0U,1U,0U}}, +{SUBQ_5170,{1U,1U,0U}}, +{SUBQ_5170,{2U,1U,0U}}, +{SUBQ_5170,{3U,1U,0U}}, +{SUBQ_5170,{4U,1U,0U}}, +{SUBQ_5170,{5U,1U,0U}}, +{SUBQ_5170,{6U,1U,0U}}, +{SUBQ_5170,{7U,1U,0U}}, +{SUBQ_5178,{0U,1U,0U}}, +{SUBQ_5179,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5180,{0U,1U,0U}}, +{SUBQ_5180,{1U,1U,0U}}, +{SUBQ_5180,{2U,1U,0U}}, +{SUBQ_5180,{3U,1U,0U}}, +{SUBQ_5180,{4U,1U,0U}}, +{SUBQ_5180,{5U,1U,0U}}, +{SUBQ_5180,{6U,1U,0U}}, +{SUBQ_5180,{7U,1U,0U}}, +{SUBQ_5188,{0U,1U,0U}}, +{SUBQ_5188,{1U,1U,0U}}, +{SUBQ_5188,{2U,1U,0U}}, +{SUBQ_5188,{3U,1U,0U}}, +{SUBQ_5188,{4U,1U,0U}}, +{SUBQ_5188,{5U,1U,0U}}, +{SUBQ_5188,{6U,1U,0U}}, +{SUBQ_5188,{7U,1U,0U}}, +{SUBQ_5190,{0U,1U,0U}}, +{SUBQ_5190,{1U,1U,0U}}, +{SUBQ_5190,{2U,1U,0U}}, +{SUBQ_5190,{3U,1U,0U}}, +{SUBQ_5190,{4U,1U,0U}}, +{SUBQ_5190,{5U,1U,0U}}, +{SUBQ_5190,{6U,1U,0U}}, +{SUBQ_5190,{7U,1U,0U}}, +{SUBQ_5198,{0U,1U,0U}}, +{SUBQ_5198,{1U,1U,0U}}, +{SUBQ_5198,{2U,1U,0U}}, +{SUBQ_5198,{3U,1U,0U}}, +{SUBQ_5198,{4U,1U,0U}}, +{SUBQ_5198,{5U,1U,0U}}, +{SUBQ_5198,{6U,1U,0U}}, +{SUBQ_5198,{7U,1U,0U}}, +{SUBQ_51A0,{0U,1U,0U}}, +{SUBQ_51A0,{1U,1U,0U}}, +{SUBQ_51A0,{2U,1U,0U}}, +{SUBQ_51A0,{3U,1U,0U}}, +{SUBQ_51A0,{4U,1U,0U}}, +{SUBQ_51A0,{5U,1U,0U}}, +{SUBQ_51A0,{6U,1U,0U}}, +{SUBQ_51A0,{7U,1U,0U}}, +{SUBQ_51A8,{0U,1U,0U}}, +{SUBQ_51A8,{1U,1U,0U}}, +{SUBQ_51A8,{2U,1U,0U}}, +{SUBQ_51A8,{3U,1U,0U}}, +{SUBQ_51A8,{4U,1U,0U}}, +{SUBQ_51A8,{5U,1U,0U}}, +{SUBQ_51A8,{6U,1U,0U}}, +{SUBQ_51A8,{7U,1U,0U}}, +{SUBQ_51B0,{0U,1U,0U}}, +{SUBQ_51B0,{1U,1U,0U}}, +{SUBQ_51B0,{2U,1U,0U}}, +{SUBQ_51B0,{3U,1U,0U}}, +{SUBQ_51B0,{4U,1U,0U}}, +{SUBQ_51B0,{5U,1U,0U}}, +{SUBQ_51B0,{6U,1U,0U}}, +{SUBQ_51B0,{7U,1U,0U}}, +{SUBQ_51B8,{0U,1U,0U}}, +{SUBQ_51B9,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,3U,0U}}, +{SCC_50C0,{1U,3U,0U}}, +{SCC_50C0,{2U,3U,0U}}, +{SCC_50C0,{3U,3U,0U}}, +{SCC_50C0,{4U,3U,0U}}, +{SCC_50C0,{5U,3U,0U}}, +{SCC_50C0,{6U,3U,0U}}, +{SCC_50C0,{7U,3U,0U}}, +{DBCC_53C8,{0U,0U,0U}}, +{DBCC_53C8,{0U,1U,0U}}, +{DBCC_53C8,{0U,2U,0U}}, +{DBCC_53C8,{0U,3U,0U}}, +{DBCC_53C8,{0U,4U,0U}}, +{DBCC_53C8,{0U,5U,0U}}, +{DBCC_53C8,{0U,6U,0U}}, +{DBCC_53C8,{0U,7U,0U}}, +{SCC_50D0,{0U,3U,0U}}, +{SCC_50D0,{1U,3U,0U}}, +{SCC_50D0,{2U,3U,0U}}, +{SCC_50D0,{3U,3U,0U}}, +{SCC_50D0,{4U,3U,0U}}, +{SCC_50D0,{5U,3U,0U}}, +{SCC_50D0,{6U,3U,0U}}, +{SCC_50D0,{7U,3U,0U}}, +{SCC_50D8,{0U,3U,0U}}, +{SCC_50D8,{1U,3U,0U}}, +{SCC_50D8,{2U,3U,0U}}, +{SCC_50D8,{3U,3U,0U}}, +{SCC_50D8,{4U,3U,0U}}, +{SCC_50D8,{5U,3U,0U}}, +{SCC_50D8,{6U,3U,0U}}, +{SCC_50D8,{7U,3U,0U}}, +{SCC_50E0,{0U,3U,0U}}, +{SCC_50E0,{1U,3U,0U}}, +{SCC_50E0,{2U,3U,0U}}, +{SCC_50E0,{3U,3U,0U}}, +{SCC_50E0,{4U,3U,0U}}, +{SCC_50E0,{5U,3U,0U}}, +{SCC_50E0,{6U,3U,0U}}, +{SCC_50E0,{7U,3U,0U}}, +{SCC_50E8,{0U,3U,0U}}, +{SCC_50E8,{1U,3U,0U}}, +{SCC_50E8,{2U,3U,0U}}, +{SCC_50E8,{3U,3U,0U}}, +{SCC_50E8,{4U,3U,0U}}, +{SCC_50E8,{5U,3U,0U}}, +{SCC_50E8,{6U,3U,0U}}, +{SCC_50E8,{7U,3U,0U}}, +{SCC_50F0,{0U,3U,0U}}, +{SCC_50F0,{1U,3U,0U}}, +{SCC_50F0,{2U,3U,0U}}, +{SCC_50F0,{3U,3U,0U}}, +{SCC_50F0,{4U,3U,0U}}, +{SCC_50F0,{5U,3U,0U}}, +{SCC_50F0,{6U,3U,0U}}, +{SCC_50F0,{7U,3U,0U}}, +{SCC_50F8,{0U,3U,0U}}, +{SCC_50F9,{0U,3U,0U}}, +{TRAPCC_53FA,{0U,0U,0U}}, +{TRAPCC_53FB,{0U,0U,0U}}, +{TRAPCC_53FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5000,{0U,2U,0U}}, +{ADDQ_5000,{1U,2U,0U}}, +{ADDQ_5000,{2U,2U,0U}}, +{ADDQ_5000,{3U,2U,0U}}, +{ADDQ_5000,{4U,2U,0U}}, +{ADDQ_5000,{5U,2U,0U}}, +{ADDQ_5000,{6U,2U,0U}}, +{ADDQ_5000,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5010,{0U,2U,0U}}, +{ADDQ_5010,{1U,2U,0U}}, +{ADDQ_5010,{2U,2U,0U}}, +{ADDQ_5010,{3U,2U,0U}}, +{ADDQ_5010,{4U,2U,0U}}, +{ADDQ_5010,{5U,2U,0U}}, +{ADDQ_5010,{6U,2U,0U}}, +{ADDQ_5010,{7U,2U,0U}}, +{ADDQ_5018,{0U,2U,0U}}, +{ADDQ_5018,{1U,2U,0U}}, +{ADDQ_5018,{2U,2U,0U}}, +{ADDQ_5018,{3U,2U,0U}}, +{ADDQ_5018,{4U,2U,0U}}, +{ADDQ_5018,{5U,2U,0U}}, +{ADDQ_5018,{6U,2U,0U}}, +{ADDQ_5018,{7U,2U,0U}}, +{ADDQ_5020,{0U,2U,0U}}, +{ADDQ_5020,{1U,2U,0U}}, +{ADDQ_5020,{2U,2U,0U}}, +{ADDQ_5020,{3U,2U,0U}}, +{ADDQ_5020,{4U,2U,0U}}, +{ADDQ_5020,{5U,2U,0U}}, +{ADDQ_5020,{6U,2U,0U}}, +{ADDQ_5020,{7U,2U,0U}}, +{ADDQ_5028,{0U,2U,0U}}, +{ADDQ_5028,{1U,2U,0U}}, +{ADDQ_5028,{2U,2U,0U}}, +{ADDQ_5028,{3U,2U,0U}}, +{ADDQ_5028,{4U,2U,0U}}, +{ADDQ_5028,{5U,2U,0U}}, +{ADDQ_5028,{6U,2U,0U}}, +{ADDQ_5028,{7U,2U,0U}}, +{ADDQ_5030,{0U,2U,0U}}, +{ADDQ_5030,{1U,2U,0U}}, +{ADDQ_5030,{2U,2U,0U}}, +{ADDQ_5030,{3U,2U,0U}}, +{ADDQ_5030,{4U,2U,0U}}, +{ADDQ_5030,{5U,2U,0U}}, +{ADDQ_5030,{6U,2U,0U}}, +{ADDQ_5030,{7U,2U,0U}}, +{ADDQ_5038,{0U,2U,0U}}, +{ADDQ_5039,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5040,{0U,2U,0U}}, +{ADDQ_5040,{1U,2U,0U}}, +{ADDQ_5040,{2U,2U,0U}}, +{ADDQ_5040,{3U,2U,0U}}, +{ADDQ_5040,{4U,2U,0U}}, +{ADDQ_5040,{5U,2U,0U}}, +{ADDQ_5040,{6U,2U,0U}}, +{ADDQ_5040,{7U,2U,0U}}, +{ADDQ_5048,{0U,2U,0U}}, +{ADDQ_5048,{1U,2U,0U}}, +{ADDQ_5048,{2U,2U,0U}}, +{ADDQ_5048,{3U,2U,0U}}, +{ADDQ_5048,{4U,2U,0U}}, +{ADDQ_5048,{5U,2U,0U}}, +{ADDQ_5048,{6U,2U,0U}}, +{ADDQ_5048,{7U,2U,0U}}, +{ADDQ_5050,{0U,2U,0U}}, +{ADDQ_5050,{1U,2U,0U}}, +{ADDQ_5050,{2U,2U,0U}}, +{ADDQ_5050,{3U,2U,0U}}, +{ADDQ_5050,{4U,2U,0U}}, +{ADDQ_5050,{5U,2U,0U}}, +{ADDQ_5050,{6U,2U,0U}}, +{ADDQ_5050,{7U,2U,0U}}, +{ADDQ_5058,{0U,2U,0U}}, +{ADDQ_5058,{1U,2U,0U}}, +{ADDQ_5058,{2U,2U,0U}}, +{ADDQ_5058,{3U,2U,0U}}, +{ADDQ_5058,{4U,2U,0U}}, +{ADDQ_5058,{5U,2U,0U}}, +{ADDQ_5058,{6U,2U,0U}}, +{ADDQ_5058,{7U,2U,0U}}, +{ADDQ_5060,{0U,2U,0U}}, +{ADDQ_5060,{1U,2U,0U}}, +{ADDQ_5060,{2U,2U,0U}}, +{ADDQ_5060,{3U,2U,0U}}, +{ADDQ_5060,{4U,2U,0U}}, +{ADDQ_5060,{5U,2U,0U}}, +{ADDQ_5060,{6U,2U,0U}}, +{ADDQ_5060,{7U,2U,0U}}, +{ADDQ_5068,{0U,2U,0U}}, +{ADDQ_5068,{1U,2U,0U}}, +{ADDQ_5068,{2U,2U,0U}}, +{ADDQ_5068,{3U,2U,0U}}, +{ADDQ_5068,{4U,2U,0U}}, +{ADDQ_5068,{5U,2U,0U}}, +{ADDQ_5068,{6U,2U,0U}}, +{ADDQ_5068,{7U,2U,0U}}, +{ADDQ_5070,{0U,2U,0U}}, +{ADDQ_5070,{1U,2U,0U}}, +{ADDQ_5070,{2U,2U,0U}}, +{ADDQ_5070,{3U,2U,0U}}, +{ADDQ_5070,{4U,2U,0U}}, +{ADDQ_5070,{5U,2U,0U}}, +{ADDQ_5070,{6U,2U,0U}}, +{ADDQ_5070,{7U,2U,0U}}, +{ADDQ_5078,{0U,2U,0U}}, +{ADDQ_5079,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5080,{0U,2U,0U}}, +{ADDQ_5080,{1U,2U,0U}}, +{ADDQ_5080,{2U,2U,0U}}, +{ADDQ_5080,{3U,2U,0U}}, +{ADDQ_5080,{4U,2U,0U}}, +{ADDQ_5080,{5U,2U,0U}}, +{ADDQ_5080,{6U,2U,0U}}, +{ADDQ_5080,{7U,2U,0U}}, +{ADDQ_5088,{0U,2U,0U}}, +{ADDQ_5088,{1U,2U,0U}}, +{ADDQ_5088,{2U,2U,0U}}, +{ADDQ_5088,{3U,2U,0U}}, +{ADDQ_5088,{4U,2U,0U}}, +{ADDQ_5088,{5U,2U,0U}}, +{ADDQ_5088,{6U,2U,0U}}, +{ADDQ_5088,{7U,2U,0U}}, +{ADDQ_5090,{0U,2U,0U}}, +{ADDQ_5090,{1U,2U,0U}}, +{ADDQ_5090,{2U,2U,0U}}, +{ADDQ_5090,{3U,2U,0U}}, +{ADDQ_5090,{4U,2U,0U}}, +{ADDQ_5090,{5U,2U,0U}}, +{ADDQ_5090,{6U,2U,0U}}, +{ADDQ_5090,{7U,2U,0U}}, +{ADDQ_5098,{0U,2U,0U}}, +{ADDQ_5098,{1U,2U,0U}}, +{ADDQ_5098,{2U,2U,0U}}, +{ADDQ_5098,{3U,2U,0U}}, +{ADDQ_5098,{4U,2U,0U}}, +{ADDQ_5098,{5U,2U,0U}}, +{ADDQ_5098,{6U,2U,0U}}, +{ADDQ_5098,{7U,2U,0U}}, +{ADDQ_50A0,{0U,2U,0U}}, +{ADDQ_50A0,{1U,2U,0U}}, +{ADDQ_50A0,{2U,2U,0U}}, +{ADDQ_50A0,{3U,2U,0U}}, +{ADDQ_50A0,{4U,2U,0U}}, +{ADDQ_50A0,{5U,2U,0U}}, +{ADDQ_50A0,{6U,2U,0U}}, +{ADDQ_50A0,{7U,2U,0U}}, +{ADDQ_50A8,{0U,2U,0U}}, +{ADDQ_50A8,{1U,2U,0U}}, +{ADDQ_50A8,{2U,2U,0U}}, +{ADDQ_50A8,{3U,2U,0U}}, +{ADDQ_50A8,{4U,2U,0U}}, +{ADDQ_50A8,{5U,2U,0U}}, +{ADDQ_50A8,{6U,2U,0U}}, +{ADDQ_50A8,{7U,2U,0U}}, +{ADDQ_50B0,{0U,2U,0U}}, +{ADDQ_50B0,{1U,2U,0U}}, +{ADDQ_50B0,{2U,2U,0U}}, +{ADDQ_50B0,{3U,2U,0U}}, +{ADDQ_50B0,{4U,2U,0U}}, +{ADDQ_50B0,{5U,2U,0U}}, +{ADDQ_50B0,{6U,2U,0U}}, +{ADDQ_50B0,{7U,2U,0U}}, +{ADDQ_50B8,{0U,2U,0U}}, +{ADDQ_50B9,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,4U,0U}}, +{SCC_50C0,{1U,4U,0U}}, +{SCC_50C0,{2U,4U,0U}}, +{SCC_50C0,{3U,4U,0U}}, +{SCC_50C0,{4U,4U,0U}}, +{SCC_50C0,{5U,4U,0U}}, +{SCC_50C0,{6U,4U,0U}}, +{SCC_50C0,{7U,4U,0U}}, +{DBCC_54C8,{0U,0U,0U}}, +{DBCC_54C8,{0U,1U,0U}}, +{DBCC_54C8,{0U,2U,0U}}, +{DBCC_54C8,{0U,3U,0U}}, +{DBCC_54C8,{0U,4U,0U}}, +{DBCC_54C8,{0U,5U,0U}}, +{DBCC_54C8,{0U,6U,0U}}, +{DBCC_54C8,{0U,7U,0U}}, +{SCC_50D0,{0U,4U,0U}}, +{SCC_50D0,{1U,4U,0U}}, +{SCC_50D0,{2U,4U,0U}}, +{SCC_50D0,{3U,4U,0U}}, +{SCC_50D0,{4U,4U,0U}}, +{SCC_50D0,{5U,4U,0U}}, +{SCC_50D0,{6U,4U,0U}}, +{SCC_50D0,{7U,4U,0U}}, +{SCC_50D8,{0U,4U,0U}}, +{SCC_50D8,{1U,4U,0U}}, +{SCC_50D8,{2U,4U,0U}}, +{SCC_50D8,{3U,4U,0U}}, +{SCC_50D8,{4U,4U,0U}}, +{SCC_50D8,{5U,4U,0U}}, +{SCC_50D8,{6U,4U,0U}}, +{SCC_50D8,{7U,4U,0U}}, +{SCC_50E0,{0U,4U,0U}}, +{SCC_50E0,{1U,4U,0U}}, +{SCC_50E0,{2U,4U,0U}}, +{SCC_50E0,{3U,4U,0U}}, +{SCC_50E0,{4U,4U,0U}}, +{SCC_50E0,{5U,4U,0U}}, +{SCC_50E0,{6U,4U,0U}}, +{SCC_50E0,{7U,4U,0U}}, +{SCC_50E8,{0U,4U,0U}}, +{SCC_50E8,{1U,4U,0U}}, +{SCC_50E8,{2U,4U,0U}}, +{SCC_50E8,{3U,4U,0U}}, +{SCC_50E8,{4U,4U,0U}}, +{SCC_50E8,{5U,4U,0U}}, +{SCC_50E8,{6U,4U,0U}}, +{SCC_50E8,{7U,4U,0U}}, +{SCC_50F0,{0U,4U,0U}}, +{SCC_50F0,{1U,4U,0U}}, +{SCC_50F0,{2U,4U,0U}}, +{SCC_50F0,{3U,4U,0U}}, +{SCC_50F0,{4U,4U,0U}}, +{SCC_50F0,{5U,4U,0U}}, +{SCC_50F0,{6U,4U,0U}}, +{SCC_50F0,{7U,4U,0U}}, +{SCC_50F8,{0U,4U,0U}}, +{SCC_50F9,{0U,4U,0U}}, +{TRAPCC_54FA,{0U,0U,0U}}, +{TRAPCC_54FB,{0U,0U,0U}}, +{TRAPCC_54FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5100,{0U,2U,0U}}, +{SUBQ_5100,{1U,2U,0U}}, +{SUBQ_5100,{2U,2U,0U}}, +{SUBQ_5100,{3U,2U,0U}}, +{SUBQ_5100,{4U,2U,0U}}, +{SUBQ_5100,{5U,2U,0U}}, +{SUBQ_5100,{6U,2U,0U}}, +{SUBQ_5100,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5110,{0U,2U,0U}}, +{SUBQ_5110,{1U,2U,0U}}, +{SUBQ_5110,{2U,2U,0U}}, +{SUBQ_5110,{3U,2U,0U}}, +{SUBQ_5110,{4U,2U,0U}}, +{SUBQ_5110,{5U,2U,0U}}, +{SUBQ_5110,{6U,2U,0U}}, +{SUBQ_5110,{7U,2U,0U}}, +{SUBQ_5118,{0U,2U,0U}}, +{SUBQ_5118,{1U,2U,0U}}, +{SUBQ_5118,{2U,2U,0U}}, +{SUBQ_5118,{3U,2U,0U}}, +{SUBQ_5118,{4U,2U,0U}}, +{SUBQ_5118,{5U,2U,0U}}, +{SUBQ_5118,{6U,2U,0U}}, +{SUBQ_5118,{7U,2U,0U}}, +{SUBQ_5120,{0U,2U,0U}}, +{SUBQ_5120,{1U,2U,0U}}, +{SUBQ_5120,{2U,2U,0U}}, +{SUBQ_5120,{3U,2U,0U}}, +{SUBQ_5120,{4U,2U,0U}}, +{SUBQ_5120,{5U,2U,0U}}, +{SUBQ_5120,{6U,2U,0U}}, +{SUBQ_5120,{7U,2U,0U}}, +{SUBQ_5128,{0U,2U,0U}}, +{SUBQ_5128,{1U,2U,0U}}, +{SUBQ_5128,{2U,2U,0U}}, +{SUBQ_5128,{3U,2U,0U}}, +{SUBQ_5128,{4U,2U,0U}}, +{SUBQ_5128,{5U,2U,0U}}, +{SUBQ_5128,{6U,2U,0U}}, +{SUBQ_5128,{7U,2U,0U}}, +{SUBQ_5130,{0U,2U,0U}}, +{SUBQ_5130,{1U,2U,0U}}, +{SUBQ_5130,{2U,2U,0U}}, +{SUBQ_5130,{3U,2U,0U}}, +{SUBQ_5130,{4U,2U,0U}}, +{SUBQ_5130,{5U,2U,0U}}, +{SUBQ_5130,{6U,2U,0U}}, +{SUBQ_5130,{7U,2U,0U}}, +{SUBQ_5138,{0U,2U,0U}}, +{SUBQ_5139,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5140,{0U,2U,0U}}, +{SUBQ_5140,{1U,2U,0U}}, +{SUBQ_5140,{2U,2U,0U}}, +{SUBQ_5140,{3U,2U,0U}}, +{SUBQ_5140,{4U,2U,0U}}, +{SUBQ_5140,{5U,2U,0U}}, +{SUBQ_5140,{6U,2U,0U}}, +{SUBQ_5140,{7U,2U,0U}}, +{SUBQ_5148,{0U,2U,0U}}, +{SUBQ_5148,{1U,2U,0U}}, +{SUBQ_5148,{2U,2U,0U}}, +{SUBQ_5148,{3U,2U,0U}}, +{SUBQ_5148,{4U,2U,0U}}, +{SUBQ_5148,{5U,2U,0U}}, +{SUBQ_5148,{6U,2U,0U}}, +{SUBQ_5148,{7U,2U,0U}}, +{SUBQ_5150,{0U,2U,0U}}, +{SUBQ_5150,{1U,2U,0U}}, +{SUBQ_5150,{2U,2U,0U}}, +{SUBQ_5150,{3U,2U,0U}}, +{SUBQ_5150,{4U,2U,0U}}, +{SUBQ_5150,{5U,2U,0U}}, +{SUBQ_5150,{6U,2U,0U}}, +{SUBQ_5150,{7U,2U,0U}}, +{SUBQ_5158,{0U,2U,0U}}, +{SUBQ_5158,{1U,2U,0U}}, +{SUBQ_5158,{2U,2U,0U}}, +{SUBQ_5158,{3U,2U,0U}}, +{SUBQ_5158,{4U,2U,0U}}, +{SUBQ_5158,{5U,2U,0U}}, +{SUBQ_5158,{6U,2U,0U}}, +{SUBQ_5158,{7U,2U,0U}}, +{SUBQ_5160,{0U,2U,0U}}, +{SUBQ_5160,{1U,2U,0U}}, +{SUBQ_5160,{2U,2U,0U}}, +{SUBQ_5160,{3U,2U,0U}}, +{SUBQ_5160,{4U,2U,0U}}, +{SUBQ_5160,{5U,2U,0U}}, +{SUBQ_5160,{6U,2U,0U}}, +{SUBQ_5160,{7U,2U,0U}}, +{SUBQ_5168,{0U,2U,0U}}, +{SUBQ_5168,{1U,2U,0U}}, +{SUBQ_5168,{2U,2U,0U}}, +{SUBQ_5168,{3U,2U,0U}}, +{SUBQ_5168,{4U,2U,0U}}, +{SUBQ_5168,{5U,2U,0U}}, +{SUBQ_5168,{6U,2U,0U}}, +{SUBQ_5168,{7U,2U,0U}}, +{SUBQ_5170,{0U,2U,0U}}, +{SUBQ_5170,{1U,2U,0U}}, +{SUBQ_5170,{2U,2U,0U}}, +{SUBQ_5170,{3U,2U,0U}}, +{SUBQ_5170,{4U,2U,0U}}, +{SUBQ_5170,{5U,2U,0U}}, +{SUBQ_5170,{6U,2U,0U}}, +{SUBQ_5170,{7U,2U,0U}}, +{SUBQ_5178,{0U,2U,0U}}, +{SUBQ_5179,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5180,{0U,2U,0U}}, +{SUBQ_5180,{1U,2U,0U}}, +{SUBQ_5180,{2U,2U,0U}}, +{SUBQ_5180,{3U,2U,0U}}, +{SUBQ_5180,{4U,2U,0U}}, +{SUBQ_5180,{5U,2U,0U}}, +{SUBQ_5180,{6U,2U,0U}}, +{SUBQ_5180,{7U,2U,0U}}, +{SUBQ_5188,{0U,2U,0U}}, +{SUBQ_5188,{1U,2U,0U}}, +{SUBQ_5188,{2U,2U,0U}}, +{SUBQ_5188,{3U,2U,0U}}, +{SUBQ_5188,{4U,2U,0U}}, +{SUBQ_5188,{5U,2U,0U}}, +{SUBQ_5188,{6U,2U,0U}}, +{SUBQ_5188,{7U,2U,0U}}, +{SUBQ_5190,{0U,2U,0U}}, +{SUBQ_5190,{1U,2U,0U}}, +{SUBQ_5190,{2U,2U,0U}}, +{SUBQ_5190,{3U,2U,0U}}, +{SUBQ_5190,{4U,2U,0U}}, +{SUBQ_5190,{5U,2U,0U}}, +{SUBQ_5190,{6U,2U,0U}}, +{SUBQ_5190,{7U,2U,0U}}, +{SUBQ_5198,{0U,2U,0U}}, +{SUBQ_5198,{1U,2U,0U}}, +{SUBQ_5198,{2U,2U,0U}}, +{SUBQ_5198,{3U,2U,0U}}, +{SUBQ_5198,{4U,2U,0U}}, +{SUBQ_5198,{5U,2U,0U}}, +{SUBQ_5198,{6U,2U,0U}}, +{SUBQ_5198,{7U,2U,0U}}, +{SUBQ_51A0,{0U,2U,0U}}, +{SUBQ_51A0,{1U,2U,0U}}, +{SUBQ_51A0,{2U,2U,0U}}, +{SUBQ_51A0,{3U,2U,0U}}, +{SUBQ_51A0,{4U,2U,0U}}, +{SUBQ_51A0,{5U,2U,0U}}, +{SUBQ_51A0,{6U,2U,0U}}, +{SUBQ_51A0,{7U,2U,0U}}, +{SUBQ_51A8,{0U,2U,0U}}, +{SUBQ_51A8,{1U,2U,0U}}, +{SUBQ_51A8,{2U,2U,0U}}, +{SUBQ_51A8,{3U,2U,0U}}, +{SUBQ_51A8,{4U,2U,0U}}, +{SUBQ_51A8,{5U,2U,0U}}, +{SUBQ_51A8,{6U,2U,0U}}, +{SUBQ_51A8,{7U,2U,0U}}, +{SUBQ_51B0,{0U,2U,0U}}, +{SUBQ_51B0,{1U,2U,0U}}, +{SUBQ_51B0,{2U,2U,0U}}, +{SUBQ_51B0,{3U,2U,0U}}, +{SUBQ_51B0,{4U,2U,0U}}, +{SUBQ_51B0,{5U,2U,0U}}, +{SUBQ_51B0,{6U,2U,0U}}, +{SUBQ_51B0,{7U,2U,0U}}, +{SUBQ_51B8,{0U,2U,0U}}, +{SUBQ_51B9,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,5U,0U}}, +{SCC_50C0,{1U,5U,0U}}, +{SCC_50C0,{2U,5U,0U}}, +{SCC_50C0,{3U,5U,0U}}, +{SCC_50C0,{4U,5U,0U}}, +{SCC_50C0,{5U,5U,0U}}, +{SCC_50C0,{6U,5U,0U}}, +{SCC_50C0,{7U,5U,0U}}, +{DBCC_55C8,{0U,0U,0U}}, +{DBCC_55C8,{0U,1U,0U}}, +{DBCC_55C8,{0U,2U,0U}}, +{DBCC_55C8,{0U,3U,0U}}, +{DBCC_55C8,{0U,4U,0U}}, +{DBCC_55C8,{0U,5U,0U}}, +{DBCC_55C8,{0U,6U,0U}}, +{DBCC_55C8,{0U,7U,0U}}, +{SCC_50D0,{0U,5U,0U}}, +{SCC_50D0,{1U,5U,0U}}, +{SCC_50D0,{2U,5U,0U}}, +{SCC_50D0,{3U,5U,0U}}, +{SCC_50D0,{4U,5U,0U}}, +{SCC_50D0,{5U,5U,0U}}, +{SCC_50D0,{6U,5U,0U}}, +{SCC_50D0,{7U,5U,0U}}, +{SCC_50D8,{0U,5U,0U}}, +{SCC_50D8,{1U,5U,0U}}, +{SCC_50D8,{2U,5U,0U}}, +{SCC_50D8,{3U,5U,0U}}, +{SCC_50D8,{4U,5U,0U}}, +{SCC_50D8,{5U,5U,0U}}, +{SCC_50D8,{6U,5U,0U}}, +{SCC_50D8,{7U,5U,0U}}, +{SCC_50E0,{0U,5U,0U}}, +{SCC_50E0,{1U,5U,0U}}, +{SCC_50E0,{2U,5U,0U}}, +{SCC_50E0,{3U,5U,0U}}, +{SCC_50E0,{4U,5U,0U}}, +{SCC_50E0,{5U,5U,0U}}, +{SCC_50E0,{6U,5U,0U}}, +{SCC_50E0,{7U,5U,0U}}, +{SCC_50E8,{0U,5U,0U}}, +{SCC_50E8,{1U,5U,0U}}, +{SCC_50E8,{2U,5U,0U}}, +{SCC_50E8,{3U,5U,0U}}, +{SCC_50E8,{4U,5U,0U}}, +{SCC_50E8,{5U,5U,0U}}, +{SCC_50E8,{6U,5U,0U}}, +{SCC_50E8,{7U,5U,0U}}, +{SCC_50F0,{0U,5U,0U}}, +{SCC_50F0,{1U,5U,0U}}, +{SCC_50F0,{2U,5U,0U}}, +{SCC_50F0,{3U,5U,0U}}, +{SCC_50F0,{4U,5U,0U}}, +{SCC_50F0,{5U,5U,0U}}, +{SCC_50F0,{6U,5U,0U}}, +{SCC_50F0,{7U,5U,0U}}, +{SCC_50F8,{0U,5U,0U}}, +{SCC_50F9,{0U,5U,0U}}, +{TRAPCC_55FA,{0U,0U,0U}}, +{TRAPCC_55FB,{0U,0U,0U}}, +{TRAPCC_55FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5000,{0U,3U,0U}}, +{ADDQ_5000,{1U,3U,0U}}, +{ADDQ_5000,{2U,3U,0U}}, +{ADDQ_5000,{3U,3U,0U}}, +{ADDQ_5000,{4U,3U,0U}}, +{ADDQ_5000,{5U,3U,0U}}, +{ADDQ_5000,{6U,3U,0U}}, +{ADDQ_5000,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5010,{0U,3U,0U}}, +{ADDQ_5010,{1U,3U,0U}}, +{ADDQ_5010,{2U,3U,0U}}, +{ADDQ_5010,{3U,3U,0U}}, +{ADDQ_5010,{4U,3U,0U}}, +{ADDQ_5010,{5U,3U,0U}}, +{ADDQ_5010,{6U,3U,0U}}, +{ADDQ_5010,{7U,3U,0U}}, +{ADDQ_5018,{0U,3U,0U}}, +{ADDQ_5018,{1U,3U,0U}}, +{ADDQ_5018,{2U,3U,0U}}, +{ADDQ_5018,{3U,3U,0U}}, +{ADDQ_5018,{4U,3U,0U}}, +{ADDQ_5018,{5U,3U,0U}}, +{ADDQ_5018,{6U,3U,0U}}, +{ADDQ_5018,{7U,3U,0U}}, +{ADDQ_5020,{0U,3U,0U}}, +{ADDQ_5020,{1U,3U,0U}}, +{ADDQ_5020,{2U,3U,0U}}, +{ADDQ_5020,{3U,3U,0U}}, +{ADDQ_5020,{4U,3U,0U}}, +{ADDQ_5020,{5U,3U,0U}}, +{ADDQ_5020,{6U,3U,0U}}, +{ADDQ_5020,{7U,3U,0U}}, +{ADDQ_5028,{0U,3U,0U}}, +{ADDQ_5028,{1U,3U,0U}}, +{ADDQ_5028,{2U,3U,0U}}, +{ADDQ_5028,{3U,3U,0U}}, +{ADDQ_5028,{4U,3U,0U}}, +{ADDQ_5028,{5U,3U,0U}}, +{ADDQ_5028,{6U,3U,0U}}, +{ADDQ_5028,{7U,3U,0U}}, +{ADDQ_5030,{0U,3U,0U}}, +{ADDQ_5030,{1U,3U,0U}}, +{ADDQ_5030,{2U,3U,0U}}, +{ADDQ_5030,{3U,3U,0U}}, +{ADDQ_5030,{4U,3U,0U}}, +{ADDQ_5030,{5U,3U,0U}}, +{ADDQ_5030,{6U,3U,0U}}, +{ADDQ_5030,{7U,3U,0U}}, +{ADDQ_5038,{0U,3U,0U}}, +{ADDQ_5039,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5040,{0U,3U,0U}}, +{ADDQ_5040,{1U,3U,0U}}, +{ADDQ_5040,{2U,3U,0U}}, +{ADDQ_5040,{3U,3U,0U}}, +{ADDQ_5040,{4U,3U,0U}}, +{ADDQ_5040,{5U,3U,0U}}, +{ADDQ_5040,{6U,3U,0U}}, +{ADDQ_5040,{7U,3U,0U}}, +{ADDQ_5048,{0U,3U,0U}}, +{ADDQ_5048,{1U,3U,0U}}, +{ADDQ_5048,{2U,3U,0U}}, +{ADDQ_5048,{3U,3U,0U}}, +{ADDQ_5048,{4U,3U,0U}}, +{ADDQ_5048,{5U,3U,0U}}, +{ADDQ_5048,{6U,3U,0U}}, +{ADDQ_5048,{7U,3U,0U}}, +{ADDQ_5050,{0U,3U,0U}}, +{ADDQ_5050,{1U,3U,0U}}, +{ADDQ_5050,{2U,3U,0U}}, +{ADDQ_5050,{3U,3U,0U}}, +{ADDQ_5050,{4U,3U,0U}}, +{ADDQ_5050,{5U,3U,0U}}, +{ADDQ_5050,{6U,3U,0U}}, +{ADDQ_5050,{7U,3U,0U}}, +{ADDQ_5058,{0U,3U,0U}}, +{ADDQ_5058,{1U,3U,0U}}, +{ADDQ_5058,{2U,3U,0U}}, +{ADDQ_5058,{3U,3U,0U}}, +{ADDQ_5058,{4U,3U,0U}}, +{ADDQ_5058,{5U,3U,0U}}, +{ADDQ_5058,{6U,3U,0U}}, +{ADDQ_5058,{7U,3U,0U}}, +{ADDQ_5060,{0U,3U,0U}}, +{ADDQ_5060,{1U,3U,0U}}, +{ADDQ_5060,{2U,3U,0U}}, +{ADDQ_5060,{3U,3U,0U}}, +{ADDQ_5060,{4U,3U,0U}}, +{ADDQ_5060,{5U,3U,0U}}, +{ADDQ_5060,{6U,3U,0U}}, +{ADDQ_5060,{7U,3U,0U}}, +{ADDQ_5068,{0U,3U,0U}}, +{ADDQ_5068,{1U,3U,0U}}, +{ADDQ_5068,{2U,3U,0U}}, +{ADDQ_5068,{3U,3U,0U}}, +{ADDQ_5068,{4U,3U,0U}}, +{ADDQ_5068,{5U,3U,0U}}, +{ADDQ_5068,{6U,3U,0U}}, +{ADDQ_5068,{7U,3U,0U}}, +{ADDQ_5070,{0U,3U,0U}}, +{ADDQ_5070,{1U,3U,0U}}, +{ADDQ_5070,{2U,3U,0U}}, +{ADDQ_5070,{3U,3U,0U}}, +{ADDQ_5070,{4U,3U,0U}}, +{ADDQ_5070,{5U,3U,0U}}, +{ADDQ_5070,{6U,3U,0U}}, +{ADDQ_5070,{7U,3U,0U}}, +{ADDQ_5078,{0U,3U,0U}}, +{ADDQ_5079,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5080,{0U,3U,0U}}, +{ADDQ_5080,{1U,3U,0U}}, +{ADDQ_5080,{2U,3U,0U}}, +{ADDQ_5080,{3U,3U,0U}}, +{ADDQ_5080,{4U,3U,0U}}, +{ADDQ_5080,{5U,3U,0U}}, +{ADDQ_5080,{6U,3U,0U}}, +{ADDQ_5080,{7U,3U,0U}}, +{ADDQ_5088,{0U,3U,0U}}, +{ADDQ_5088,{1U,3U,0U}}, +{ADDQ_5088,{2U,3U,0U}}, +{ADDQ_5088,{3U,3U,0U}}, +{ADDQ_5088,{4U,3U,0U}}, +{ADDQ_5088,{5U,3U,0U}}, +{ADDQ_5088,{6U,3U,0U}}, +{ADDQ_5088,{7U,3U,0U}}, +{ADDQ_5090,{0U,3U,0U}}, +{ADDQ_5090,{1U,3U,0U}}, +{ADDQ_5090,{2U,3U,0U}}, +{ADDQ_5090,{3U,3U,0U}}, +{ADDQ_5090,{4U,3U,0U}}, +{ADDQ_5090,{5U,3U,0U}}, +{ADDQ_5090,{6U,3U,0U}}, +{ADDQ_5090,{7U,3U,0U}}, +{ADDQ_5098,{0U,3U,0U}}, +{ADDQ_5098,{1U,3U,0U}}, +{ADDQ_5098,{2U,3U,0U}}, +{ADDQ_5098,{3U,3U,0U}}, +{ADDQ_5098,{4U,3U,0U}}, +{ADDQ_5098,{5U,3U,0U}}, +{ADDQ_5098,{6U,3U,0U}}, +{ADDQ_5098,{7U,3U,0U}}, +{ADDQ_50A0,{0U,3U,0U}}, +{ADDQ_50A0,{1U,3U,0U}}, +{ADDQ_50A0,{2U,3U,0U}}, +{ADDQ_50A0,{3U,3U,0U}}, +{ADDQ_50A0,{4U,3U,0U}}, +{ADDQ_50A0,{5U,3U,0U}}, +{ADDQ_50A0,{6U,3U,0U}}, +{ADDQ_50A0,{7U,3U,0U}}, +{ADDQ_50A8,{0U,3U,0U}}, +{ADDQ_50A8,{1U,3U,0U}}, +{ADDQ_50A8,{2U,3U,0U}}, +{ADDQ_50A8,{3U,3U,0U}}, +{ADDQ_50A8,{4U,3U,0U}}, +{ADDQ_50A8,{5U,3U,0U}}, +{ADDQ_50A8,{6U,3U,0U}}, +{ADDQ_50A8,{7U,3U,0U}}, +{ADDQ_50B0,{0U,3U,0U}}, +{ADDQ_50B0,{1U,3U,0U}}, +{ADDQ_50B0,{2U,3U,0U}}, +{ADDQ_50B0,{3U,3U,0U}}, +{ADDQ_50B0,{4U,3U,0U}}, +{ADDQ_50B0,{5U,3U,0U}}, +{ADDQ_50B0,{6U,3U,0U}}, +{ADDQ_50B0,{7U,3U,0U}}, +{ADDQ_50B8,{0U,3U,0U}}, +{ADDQ_50B9,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,6U,0U}}, +{SCC_50C0,{1U,6U,0U}}, +{SCC_50C0,{2U,6U,0U}}, +{SCC_50C0,{3U,6U,0U}}, +{SCC_50C0,{4U,6U,0U}}, +{SCC_50C0,{5U,6U,0U}}, +{SCC_50C0,{6U,6U,0U}}, +{SCC_50C0,{7U,6U,0U}}, +{DBCC_56C8,{0U,0U,0U}}, +{DBCC_56C8,{0U,1U,0U}}, +{DBCC_56C8,{0U,2U,0U}}, +{DBCC_56C8,{0U,3U,0U}}, +{DBCC_56C8,{0U,4U,0U}}, +{DBCC_56C8,{0U,5U,0U}}, +{DBCC_56C8,{0U,6U,0U}}, +{DBCC_56C8,{0U,7U,0U}}, +{SCC_50D0,{0U,6U,0U}}, +{SCC_50D0,{1U,6U,0U}}, +{SCC_50D0,{2U,6U,0U}}, +{SCC_50D0,{3U,6U,0U}}, +{SCC_50D0,{4U,6U,0U}}, +{SCC_50D0,{5U,6U,0U}}, +{SCC_50D0,{6U,6U,0U}}, +{SCC_50D0,{7U,6U,0U}}, +{SCC_50D8,{0U,6U,0U}}, +{SCC_50D8,{1U,6U,0U}}, +{SCC_50D8,{2U,6U,0U}}, +{SCC_50D8,{3U,6U,0U}}, +{SCC_50D8,{4U,6U,0U}}, +{SCC_50D8,{5U,6U,0U}}, +{SCC_50D8,{6U,6U,0U}}, +{SCC_50D8,{7U,6U,0U}}, +{SCC_50E0,{0U,6U,0U}}, +{SCC_50E0,{1U,6U,0U}}, +{SCC_50E0,{2U,6U,0U}}, +{SCC_50E0,{3U,6U,0U}}, +{SCC_50E0,{4U,6U,0U}}, +{SCC_50E0,{5U,6U,0U}}, +{SCC_50E0,{6U,6U,0U}}, +{SCC_50E0,{7U,6U,0U}}, +{SCC_50E8,{0U,6U,0U}}, +{SCC_50E8,{1U,6U,0U}}, +{SCC_50E8,{2U,6U,0U}}, +{SCC_50E8,{3U,6U,0U}}, +{SCC_50E8,{4U,6U,0U}}, +{SCC_50E8,{5U,6U,0U}}, +{SCC_50E8,{6U,6U,0U}}, +{SCC_50E8,{7U,6U,0U}}, +{SCC_50F0,{0U,6U,0U}}, +{SCC_50F0,{1U,6U,0U}}, +{SCC_50F0,{2U,6U,0U}}, +{SCC_50F0,{3U,6U,0U}}, +{SCC_50F0,{4U,6U,0U}}, +{SCC_50F0,{5U,6U,0U}}, +{SCC_50F0,{6U,6U,0U}}, +{SCC_50F0,{7U,6U,0U}}, +{SCC_50F8,{0U,6U,0U}}, +{SCC_50F9,{0U,6U,0U}}, +{TRAPCC_56FA,{0U,0U,0U}}, +{TRAPCC_56FB,{0U,0U,0U}}, +{TRAPCC_56FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5100,{0U,3U,0U}}, +{SUBQ_5100,{1U,3U,0U}}, +{SUBQ_5100,{2U,3U,0U}}, +{SUBQ_5100,{3U,3U,0U}}, +{SUBQ_5100,{4U,3U,0U}}, +{SUBQ_5100,{5U,3U,0U}}, +{SUBQ_5100,{6U,3U,0U}}, +{SUBQ_5100,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5110,{0U,3U,0U}}, +{SUBQ_5110,{1U,3U,0U}}, +{SUBQ_5110,{2U,3U,0U}}, +{SUBQ_5110,{3U,3U,0U}}, +{SUBQ_5110,{4U,3U,0U}}, +{SUBQ_5110,{5U,3U,0U}}, +{SUBQ_5110,{6U,3U,0U}}, +{SUBQ_5110,{7U,3U,0U}}, +{SUBQ_5118,{0U,3U,0U}}, +{SUBQ_5118,{1U,3U,0U}}, +{SUBQ_5118,{2U,3U,0U}}, +{SUBQ_5118,{3U,3U,0U}}, +{SUBQ_5118,{4U,3U,0U}}, +{SUBQ_5118,{5U,3U,0U}}, +{SUBQ_5118,{6U,3U,0U}}, +{SUBQ_5118,{7U,3U,0U}}, +{SUBQ_5120,{0U,3U,0U}}, +{SUBQ_5120,{1U,3U,0U}}, +{SUBQ_5120,{2U,3U,0U}}, +{SUBQ_5120,{3U,3U,0U}}, +{SUBQ_5120,{4U,3U,0U}}, +{SUBQ_5120,{5U,3U,0U}}, +{SUBQ_5120,{6U,3U,0U}}, +{SUBQ_5120,{7U,3U,0U}}, +{SUBQ_5128,{0U,3U,0U}}, +{SUBQ_5128,{1U,3U,0U}}, +{SUBQ_5128,{2U,3U,0U}}, +{SUBQ_5128,{3U,3U,0U}}, +{SUBQ_5128,{4U,3U,0U}}, +{SUBQ_5128,{5U,3U,0U}}, +{SUBQ_5128,{6U,3U,0U}}, +{SUBQ_5128,{7U,3U,0U}}, +{SUBQ_5130,{0U,3U,0U}}, +{SUBQ_5130,{1U,3U,0U}}, +{SUBQ_5130,{2U,3U,0U}}, +{SUBQ_5130,{3U,3U,0U}}, +{SUBQ_5130,{4U,3U,0U}}, +{SUBQ_5130,{5U,3U,0U}}, +{SUBQ_5130,{6U,3U,0U}}, +{SUBQ_5130,{7U,3U,0U}}, +{SUBQ_5138,{0U,3U,0U}}, +{SUBQ_5139,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5140,{0U,3U,0U}}, +{SUBQ_5140,{1U,3U,0U}}, +{SUBQ_5140,{2U,3U,0U}}, +{SUBQ_5140,{3U,3U,0U}}, +{SUBQ_5140,{4U,3U,0U}}, +{SUBQ_5140,{5U,3U,0U}}, +{SUBQ_5140,{6U,3U,0U}}, +{SUBQ_5140,{7U,3U,0U}}, +{SUBQ_5148,{0U,3U,0U}}, +{SUBQ_5148,{1U,3U,0U}}, +{SUBQ_5148,{2U,3U,0U}}, +{SUBQ_5148,{3U,3U,0U}}, +{SUBQ_5148,{4U,3U,0U}}, +{SUBQ_5148,{5U,3U,0U}}, +{SUBQ_5148,{6U,3U,0U}}, +{SUBQ_5148,{7U,3U,0U}}, +{SUBQ_5150,{0U,3U,0U}}, +{SUBQ_5150,{1U,3U,0U}}, +{SUBQ_5150,{2U,3U,0U}}, +{SUBQ_5150,{3U,3U,0U}}, +{SUBQ_5150,{4U,3U,0U}}, +{SUBQ_5150,{5U,3U,0U}}, +{SUBQ_5150,{6U,3U,0U}}, +{SUBQ_5150,{7U,3U,0U}}, +{SUBQ_5158,{0U,3U,0U}}, +{SUBQ_5158,{1U,3U,0U}}, +{SUBQ_5158,{2U,3U,0U}}, +{SUBQ_5158,{3U,3U,0U}}, +{SUBQ_5158,{4U,3U,0U}}, +{SUBQ_5158,{5U,3U,0U}}, +{SUBQ_5158,{6U,3U,0U}}, +{SUBQ_5158,{7U,3U,0U}}, +{SUBQ_5160,{0U,3U,0U}}, +{SUBQ_5160,{1U,3U,0U}}, +{SUBQ_5160,{2U,3U,0U}}, +{SUBQ_5160,{3U,3U,0U}}, +{SUBQ_5160,{4U,3U,0U}}, +{SUBQ_5160,{5U,3U,0U}}, +{SUBQ_5160,{6U,3U,0U}}, +{SUBQ_5160,{7U,3U,0U}}, +{SUBQ_5168,{0U,3U,0U}}, +{SUBQ_5168,{1U,3U,0U}}, +{SUBQ_5168,{2U,3U,0U}}, +{SUBQ_5168,{3U,3U,0U}}, +{SUBQ_5168,{4U,3U,0U}}, +{SUBQ_5168,{5U,3U,0U}}, +{SUBQ_5168,{6U,3U,0U}}, +{SUBQ_5168,{7U,3U,0U}}, +{SUBQ_5170,{0U,3U,0U}}, +{SUBQ_5170,{1U,3U,0U}}, +{SUBQ_5170,{2U,3U,0U}}, +{SUBQ_5170,{3U,3U,0U}}, +{SUBQ_5170,{4U,3U,0U}}, +{SUBQ_5170,{5U,3U,0U}}, +{SUBQ_5170,{6U,3U,0U}}, +{SUBQ_5170,{7U,3U,0U}}, +{SUBQ_5178,{0U,3U,0U}}, +{SUBQ_5179,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5180,{0U,3U,0U}}, +{SUBQ_5180,{1U,3U,0U}}, +{SUBQ_5180,{2U,3U,0U}}, +{SUBQ_5180,{3U,3U,0U}}, +{SUBQ_5180,{4U,3U,0U}}, +{SUBQ_5180,{5U,3U,0U}}, +{SUBQ_5180,{6U,3U,0U}}, +{SUBQ_5180,{7U,3U,0U}}, +{SUBQ_5188,{0U,3U,0U}}, +{SUBQ_5188,{1U,3U,0U}}, +{SUBQ_5188,{2U,3U,0U}}, +{SUBQ_5188,{3U,3U,0U}}, +{SUBQ_5188,{4U,3U,0U}}, +{SUBQ_5188,{5U,3U,0U}}, +{SUBQ_5188,{6U,3U,0U}}, +{SUBQ_5188,{7U,3U,0U}}, +{SUBQ_5190,{0U,3U,0U}}, +{SUBQ_5190,{1U,3U,0U}}, +{SUBQ_5190,{2U,3U,0U}}, +{SUBQ_5190,{3U,3U,0U}}, +{SUBQ_5190,{4U,3U,0U}}, +{SUBQ_5190,{5U,3U,0U}}, +{SUBQ_5190,{6U,3U,0U}}, +{SUBQ_5190,{7U,3U,0U}}, +{SUBQ_5198,{0U,3U,0U}}, +{SUBQ_5198,{1U,3U,0U}}, +{SUBQ_5198,{2U,3U,0U}}, +{SUBQ_5198,{3U,3U,0U}}, +{SUBQ_5198,{4U,3U,0U}}, +{SUBQ_5198,{5U,3U,0U}}, +{SUBQ_5198,{6U,3U,0U}}, +{SUBQ_5198,{7U,3U,0U}}, +{SUBQ_51A0,{0U,3U,0U}}, +{SUBQ_51A0,{1U,3U,0U}}, +{SUBQ_51A0,{2U,3U,0U}}, +{SUBQ_51A0,{3U,3U,0U}}, +{SUBQ_51A0,{4U,3U,0U}}, +{SUBQ_51A0,{5U,3U,0U}}, +{SUBQ_51A0,{6U,3U,0U}}, +{SUBQ_51A0,{7U,3U,0U}}, +{SUBQ_51A8,{0U,3U,0U}}, +{SUBQ_51A8,{1U,3U,0U}}, +{SUBQ_51A8,{2U,3U,0U}}, +{SUBQ_51A8,{3U,3U,0U}}, +{SUBQ_51A8,{4U,3U,0U}}, +{SUBQ_51A8,{5U,3U,0U}}, +{SUBQ_51A8,{6U,3U,0U}}, +{SUBQ_51A8,{7U,3U,0U}}, +{SUBQ_51B0,{0U,3U,0U}}, +{SUBQ_51B0,{1U,3U,0U}}, +{SUBQ_51B0,{2U,3U,0U}}, +{SUBQ_51B0,{3U,3U,0U}}, +{SUBQ_51B0,{4U,3U,0U}}, +{SUBQ_51B0,{5U,3U,0U}}, +{SUBQ_51B0,{6U,3U,0U}}, +{SUBQ_51B0,{7U,3U,0U}}, +{SUBQ_51B8,{0U,3U,0U}}, +{SUBQ_51B9,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,7U,0U}}, +{SCC_50C0,{1U,7U,0U}}, +{SCC_50C0,{2U,7U,0U}}, +{SCC_50C0,{3U,7U,0U}}, +{SCC_50C0,{4U,7U,0U}}, +{SCC_50C0,{5U,7U,0U}}, +{SCC_50C0,{6U,7U,0U}}, +{SCC_50C0,{7U,7U,0U}}, +{DBCC_57C8,{0U,0U,0U}}, +{DBCC_57C8,{0U,1U,0U}}, +{DBCC_57C8,{0U,2U,0U}}, +{DBCC_57C8,{0U,3U,0U}}, +{DBCC_57C8,{0U,4U,0U}}, +{DBCC_57C8,{0U,5U,0U}}, +{DBCC_57C8,{0U,6U,0U}}, +{DBCC_57C8,{0U,7U,0U}}, +{SCC_50D0,{0U,7U,0U}}, +{SCC_50D0,{1U,7U,0U}}, +{SCC_50D0,{2U,7U,0U}}, +{SCC_50D0,{3U,7U,0U}}, +{SCC_50D0,{4U,7U,0U}}, +{SCC_50D0,{5U,7U,0U}}, +{SCC_50D0,{6U,7U,0U}}, +{SCC_50D0,{7U,7U,0U}}, +{SCC_50D8,{0U,7U,0U}}, +{SCC_50D8,{1U,7U,0U}}, +{SCC_50D8,{2U,7U,0U}}, +{SCC_50D8,{3U,7U,0U}}, +{SCC_50D8,{4U,7U,0U}}, +{SCC_50D8,{5U,7U,0U}}, +{SCC_50D8,{6U,7U,0U}}, +{SCC_50D8,{7U,7U,0U}}, +{SCC_50E0,{0U,7U,0U}}, +{SCC_50E0,{1U,7U,0U}}, +{SCC_50E0,{2U,7U,0U}}, +{SCC_50E0,{3U,7U,0U}}, +{SCC_50E0,{4U,7U,0U}}, +{SCC_50E0,{5U,7U,0U}}, +{SCC_50E0,{6U,7U,0U}}, +{SCC_50E0,{7U,7U,0U}}, +{SCC_50E8,{0U,7U,0U}}, +{SCC_50E8,{1U,7U,0U}}, +{SCC_50E8,{2U,7U,0U}}, +{SCC_50E8,{3U,7U,0U}}, +{SCC_50E8,{4U,7U,0U}}, +{SCC_50E8,{5U,7U,0U}}, +{SCC_50E8,{6U,7U,0U}}, +{SCC_50E8,{7U,7U,0U}}, +{SCC_50F0,{0U,7U,0U}}, +{SCC_50F0,{1U,7U,0U}}, +{SCC_50F0,{2U,7U,0U}}, +{SCC_50F0,{3U,7U,0U}}, +{SCC_50F0,{4U,7U,0U}}, +{SCC_50F0,{5U,7U,0U}}, +{SCC_50F0,{6U,7U,0U}}, +{SCC_50F0,{7U,7U,0U}}, +{SCC_50F8,{0U,7U,0U}}, +{SCC_50F9,{0U,7U,0U}}, +{TRAPCC_57FA,{0U,0U,0U}}, +{TRAPCC_57FB,{0U,0U,0U}}, +{TRAPCC_57FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5000,{0U,4U,0U}}, +{ADDQ_5000,{1U,4U,0U}}, +{ADDQ_5000,{2U,4U,0U}}, +{ADDQ_5000,{3U,4U,0U}}, +{ADDQ_5000,{4U,4U,0U}}, +{ADDQ_5000,{5U,4U,0U}}, +{ADDQ_5000,{6U,4U,0U}}, +{ADDQ_5000,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5010,{0U,4U,0U}}, +{ADDQ_5010,{1U,4U,0U}}, +{ADDQ_5010,{2U,4U,0U}}, +{ADDQ_5010,{3U,4U,0U}}, +{ADDQ_5010,{4U,4U,0U}}, +{ADDQ_5010,{5U,4U,0U}}, +{ADDQ_5010,{6U,4U,0U}}, +{ADDQ_5010,{7U,4U,0U}}, +{ADDQ_5018,{0U,4U,0U}}, +{ADDQ_5018,{1U,4U,0U}}, +{ADDQ_5018,{2U,4U,0U}}, +{ADDQ_5018,{3U,4U,0U}}, +{ADDQ_5018,{4U,4U,0U}}, +{ADDQ_5018,{5U,4U,0U}}, +{ADDQ_5018,{6U,4U,0U}}, +{ADDQ_5018,{7U,4U,0U}}, +{ADDQ_5020,{0U,4U,0U}}, +{ADDQ_5020,{1U,4U,0U}}, +{ADDQ_5020,{2U,4U,0U}}, +{ADDQ_5020,{3U,4U,0U}}, +{ADDQ_5020,{4U,4U,0U}}, +{ADDQ_5020,{5U,4U,0U}}, +{ADDQ_5020,{6U,4U,0U}}, +{ADDQ_5020,{7U,4U,0U}}, +{ADDQ_5028,{0U,4U,0U}}, +{ADDQ_5028,{1U,4U,0U}}, +{ADDQ_5028,{2U,4U,0U}}, +{ADDQ_5028,{3U,4U,0U}}, +{ADDQ_5028,{4U,4U,0U}}, +{ADDQ_5028,{5U,4U,0U}}, +{ADDQ_5028,{6U,4U,0U}}, +{ADDQ_5028,{7U,4U,0U}}, +{ADDQ_5030,{0U,4U,0U}}, +{ADDQ_5030,{1U,4U,0U}}, +{ADDQ_5030,{2U,4U,0U}}, +{ADDQ_5030,{3U,4U,0U}}, +{ADDQ_5030,{4U,4U,0U}}, +{ADDQ_5030,{5U,4U,0U}}, +{ADDQ_5030,{6U,4U,0U}}, +{ADDQ_5030,{7U,4U,0U}}, +{ADDQ_5038,{0U,4U,0U}}, +{ADDQ_5039,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5040,{0U,4U,0U}}, +{ADDQ_5040,{1U,4U,0U}}, +{ADDQ_5040,{2U,4U,0U}}, +{ADDQ_5040,{3U,4U,0U}}, +{ADDQ_5040,{4U,4U,0U}}, +{ADDQ_5040,{5U,4U,0U}}, +{ADDQ_5040,{6U,4U,0U}}, +{ADDQ_5040,{7U,4U,0U}}, +{ADDQ_5048,{0U,4U,0U}}, +{ADDQ_5048,{1U,4U,0U}}, +{ADDQ_5048,{2U,4U,0U}}, +{ADDQ_5048,{3U,4U,0U}}, +{ADDQ_5048,{4U,4U,0U}}, +{ADDQ_5048,{5U,4U,0U}}, +{ADDQ_5048,{6U,4U,0U}}, +{ADDQ_5048,{7U,4U,0U}}, +{ADDQ_5050,{0U,4U,0U}}, +{ADDQ_5050,{1U,4U,0U}}, +{ADDQ_5050,{2U,4U,0U}}, +{ADDQ_5050,{3U,4U,0U}}, +{ADDQ_5050,{4U,4U,0U}}, +{ADDQ_5050,{5U,4U,0U}}, +{ADDQ_5050,{6U,4U,0U}}, +{ADDQ_5050,{7U,4U,0U}}, +{ADDQ_5058,{0U,4U,0U}}, +{ADDQ_5058,{1U,4U,0U}}, +{ADDQ_5058,{2U,4U,0U}}, +{ADDQ_5058,{3U,4U,0U}}, +{ADDQ_5058,{4U,4U,0U}}, +{ADDQ_5058,{5U,4U,0U}}, +{ADDQ_5058,{6U,4U,0U}}, +{ADDQ_5058,{7U,4U,0U}}, +{ADDQ_5060,{0U,4U,0U}}, +{ADDQ_5060,{1U,4U,0U}}, +{ADDQ_5060,{2U,4U,0U}}, +{ADDQ_5060,{3U,4U,0U}}, +{ADDQ_5060,{4U,4U,0U}}, +{ADDQ_5060,{5U,4U,0U}}, +{ADDQ_5060,{6U,4U,0U}}, +{ADDQ_5060,{7U,4U,0U}}, +{ADDQ_5068,{0U,4U,0U}}, +{ADDQ_5068,{1U,4U,0U}}, +{ADDQ_5068,{2U,4U,0U}}, +{ADDQ_5068,{3U,4U,0U}}, +{ADDQ_5068,{4U,4U,0U}}, +{ADDQ_5068,{5U,4U,0U}}, +{ADDQ_5068,{6U,4U,0U}}, +{ADDQ_5068,{7U,4U,0U}}, +{ADDQ_5070,{0U,4U,0U}}, +{ADDQ_5070,{1U,4U,0U}}, +{ADDQ_5070,{2U,4U,0U}}, +{ADDQ_5070,{3U,4U,0U}}, +{ADDQ_5070,{4U,4U,0U}}, +{ADDQ_5070,{5U,4U,0U}}, +{ADDQ_5070,{6U,4U,0U}}, +{ADDQ_5070,{7U,4U,0U}}, +{ADDQ_5078,{0U,4U,0U}}, +{ADDQ_5079,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5080,{0U,4U,0U}}, +{ADDQ_5080,{1U,4U,0U}}, +{ADDQ_5080,{2U,4U,0U}}, +{ADDQ_5080,{3U,4U,0U}}, +{ADDQ_5080,{4U,4U,0U}}, +{ADDQ_5080,{5U,4U,0U}}, +{ADDQ_5080,{6U,4U,0U}}, +{ADDQ_5080,{7U,4U,0U}}, +{ADDQ_5088,{0U,4U,0U}}, +{ADDQ_5088,{1U,4U,0U}}, +{ADDQ_5088,{2U,4U,0U}}, +{ADDQ_5088,{3U,4U,0U}}, +{ADDQ_5088,{4U,4U,0U}}, +{ADDQ_5088,{5U,4U,0U}}, +{ADDQ_5088,{6U,4U,0U}}, +{ADDQ_5088,{7U,4U,0U}}, +{ADDQ_5090,{0U,4U,0U}}, +{ADDQ_5090,{1U,4U,0U}}, +{ADDQ_5090,{2U,4U,0U}}, +{ADDQ_5090,{3U,4U,0U}}, +{ADDQ_5090,{4U,4U,0U}}, +{ADDQ_5090,{5U,4U,0U}}, +{ADDQ_5090,{6U,4U,0U}}, +{ADDQ_5090,{7U,4U,0U}}, +{ADDQ_5098,{0U,4U,0U}}, +{ADDQ_5098,{1U,4U,0U}}, +{ADDQ_5098,{2U,4U,0U}}, +{ADDQ_5098,{3U,4U,0U}}, +{ADDQ_5098,{4U,4U,0U}}, +{ADDQ_5098,{5U,4U,0U}}, +{ADDQ_5098,{6U,4U,0U}}, +{ADDQ_5098,{7U,4U,0U}}, +{ADDQ_50A0,{0U,4U,0U}}, +{ADDQ_50A0,{1U,4U,0U}}, +{ADDQ_50A0,{2U,4U,0U}}, +{ADDQ_50A0,{3U,4U,0U}}, +{ADDQ_50A0,{4U,4U,0U}}, +{ADDQ_50A0,{5U,4U,0U}}, +{ADDQ_50A0,{6U,4U,0U}}, +{ADDQ_50A0,{7U,4U,0U}}, +{ADDQ_50A8,{0U,4U,0U}}, +{ADDQ_50A8,{1U,4U,0U}}, +{ADDQ_50A8,{2U,4U,0U}}, +{ADDQ_50A8,{3U,4U,0U}}, +{ADDQ_50A8,{4U,4U,0U}}, +{ADDQ_50A8,{5U,4U,0U}}, +{ADDQ_50A8,{6U,4U,0U}}, +{ADDQ_50A8,{7U,4U,0U}}, +{ADDQ_50B0,{0U,4U,0U}}, +{ADDQ_50B0,{1U,4U,0U}}, +{ADDQ_50B0,{2U,4U,0U}}, +{ADDQ_50B0,{3U,4U,0U}}, +{ADDQ_50B0,{4U,4U,0U}}, +{ADDQ_50B0,{5U,4U,0U}}, +{ADDQ_50B0,{6U,4U,0U}}, +{ADDQ_50B0,{7U,4U,0U}}, +{ADDQ_50B8,{0U,4U,0U}}, +{ADDQ_50B9,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,8U,0U}}, +{SCC_50C0,{1U,8U,0U}}, +{SCC_50C0,{2U,8U,0U}}, +{SCC_50C0,{3U,8U,0U}}, +{SCC_50C0,{4U,8U,0U}}, +{SCC_50C0,{5U,8U,0U}}, +{SCC_50C0,{6U,8U,0U}}, +{SCC_50C0,{7U,8U,0U}}, +{DBCC_58C8,{0U,0U,0U}}, +{DBCC_58C8,{0U,1U,0U}}, +{DBCC_58C8,{0U,2U,0U}}, +{DBCC_58C8,{0U,3U,0U}}, +{DBCC_58C8,{0U,4U,0U}}, +{DBCC_58C8,{0U,5U,0U}}, +{DBCC_58C8,{0U,6U,0U}}, +{DBCC_58C8,{0U,7U,0U}}, +{SCC_50D0,{0U,8U,0U}}, +{SCC_50D0,{1U,8U,0U}}, +{SCC_50D0,{2U,8U,0U}}, +{SCC_50D0,{3U,8U,0U}}, +{SCC_50D0,{4U,8U,0U}}, +{SCC_50D0,{5U,8U,0U}}, +{SCC_50D0,{6U,8U,0U}}, +{SCC_50D0,{7U,8U,0U}}, +{SCC_50D8,{0U,8U,0U}}, +{SCC_50D8,{1U,8U,0U}}, +{SCC_50D8,{2U,8U,0U}}, +{SCC_50D8,{3U,8U,0U}}, +{SCC_50D8,{4U,8U,0U}}, +{SCC_50D8,{5U,8U,0U}}, +{SCC_50D8,{6U,8U,0U}}, +{SCC_50D8,{7U,8U,0U}}, +{SCC_50E0,{0U,8U,0U}}, +{SCC_50E0,{1U,8U,0U}}, +{SCC_50E0,{2U,8U,0U}}, +{SCC_50E0,{3U,8U,0U}}, +{SCC_50E0,{4U,8U,0U}}, +{SCC_50E0,{5U,8U,0U}}, +{SCC_50E0,{6U,8U,0U}}, +{SCC_50E0,{7U,8U,0U}}, +{SCC_50E8,{0U,8U,0U}}, +{SCC_50E8,{1U,8U,0U}}, +{SCC_50E8,{2U,8U,0U}}, +{SCC_50E8,{3U,8U,0U}}, +{SCC_50E8,{4U,8U,0U}}, +{SCC_50E8,{5U,8U,0U}}, +{SCC_50E8,{6U,8U,0U}}, +{SCC_50E8,{7U,8U,0U}}, +{SCC_50F0,{0U,8U,0U}}, +{SCC_50F0,{1U,8U,0U}}, +{SCC_50F0,{2U,8U,0U}}, +{SCC_50F0,{3U,8U,0U}}, +{SCC_50F0,{4U,8U,0U}}, +{SCC_50F0,{5U,8U,0U}}, +{SCC_50F0,{6U,8U,0U}}, +{SCC_50F0,{7U,8U,0U}}, +{SCC_50F8,{0U,8U,0U}}, +{SCC_50F9,{0U,8U,0U}}, +{TRAPCC_58FA,{0U,0U,0U}}, +{TRAPCC_58FB,{0U,0U,0U}}, +{TRAPCC_58FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5100,{0U,4U,0U}}, +{SUBQ_5100,{1U,4U,0U}}, +{SUBQ_5100,{2U,4U,0U}}, +{SUBQ_5100,{3U,4U,0U}}, +{SUBQ_5100,{4U,4U,0U}}, +{SUBQ_5100,{5U,4U,0U}}, +{SUBQ_5100,{6U,4U,0U}}, +{SUBQ_5100,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5110,{0U,4U,0U}}, +{SUBQ_5110,{1U,4U,0U}}, +{SUBQ_5110,{2U,4U,0U}}, +{SUBQ_5110,{3U,4U,0U}}, +{SUBQ_5110,{4U,4U,0U}}, +{SUBQ_5110,{5U,4U,0U}}, +{SUBQ_5110,{6U,4U,0U}}, +{SUBQ_5110,{7U,4U,0U}}, +{SUBQ_5118,{0U,4U,0U}}, +{SUBQ_5118,{1U,4U,0U}}, +{SUBQ_5118,{2U,4U,0U}}, +{SUBQ_5118,{3U,4U,0U}}, +{SUBQ_5118,{4U,4U,0U}}, +{SUBQ_5118,{5U,4U,0U}}, +{SUBQ_5118,{6U,4U,0U}}, +{SUBQ_5118,{7U,4U,0U}}, +{SUBQ_5120,{0U,4U,0U}}, +{SUBQ_5120,{1U,4U,0U}}, +{SUBQ_5120,{2U,4U,0U}}, +{SUBQ_5120,{3U,4U,0U}}, +{SUBQ_5120,{4U,4U,0U}}, +{SUBQ_5120,{5U,4U,0U}}, +{SUBQ_5120,{6U,4U,0U}}, +{SUBQ_5120,{7U,4U,0U}}, +{SUBQ_5128,{0U,4U,0U}}, +{SUBQ_5128,{1U,4U,0U}}, +{SUBQ_5128,{2U,4U,0U}}, +{SUBQ_5128,{3U,4U,0U}}, +{SUBQ_5128,{4U,4U,0U}}, +{SUBQ_5128,{5U,4U,0U}}, +{SUBQ_5128,{6U,4U,0U}}, +{SUBQ_5128,{7U,4U,0U}}, +{SUBQ_5130,{0U,4U,0U}}, +{SUBQ_5130,{1U,4U,0U}}, +{SUBQ_5130,{2U,4U,0U}}, +{SUBQ_5130,{3U,4U,0U}}, +{SUBQ_5130,{4U,4U,0U}}, +{SUBQ_5130,{5U,4U,0U}}, +{SUBQ_5130,{6U,4U,0U}}, +{SUBQ_5130,{7U,4U,0U}}, +{SUBQ_5138,{0U,4U,0U}}, +{SUBQ_5139,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5140,{0U,4U,0U}}, +{SUBQ_5140,{1U,4U,0U}}, +{SUBQ_5140,{2U,4U,0U}}, +{SUBQ_5140,{3U,4U,0U}}, +{SUBQ_5140,{4U,4U,0U}}, +{SUBQ_5140,{5U,4U,0U}}, +{SUBQ_5140,{6U,4U,0U}}, +{SUBQ_5140,{7U,4U,0U}}, +{SUBQ_5148,{0U,4U,0U}}, +{SUBQ_5148,{1U,4U,0U}}, +{SUBQ_5148,{2U,4U,0U}}, +{SUBQ_5148,{3U,4U,0U}}, +{SUBQ_5148,{4U,4U,0U}}, +{SUBQ_5148,{5U,4U,0U}}, +{SUBQ_5148,{6U,4U,0U}}, +{SUBQ_5148,{7U,4U,0U}}, +{SUBQ_5150,{0U,4U,0U}}, +{SUBQ_5150,{1U,4U,0U}}, +{SUBQ_5150,{2U,4U,0U}}, +{SUBQ_5150,{3U,4U,0U}}, +{SUBQ_5150,{4U,4U,0U}}, +{SUBQ_5150,{5U,4U,0U}}, +{SUBQ_5150,{6U,4U,0U}}, +{SUBQ_5150,{7U,4U,0U}}, +{SUBQ_5158,{0U,4U,0U}}, +{SUBQ_5158,{1U,4U,0U}}, +{SUBQ_5158,{2U,4U,0U}}, +{SUBQ_5158,{3U,4U,0U}}, +{SUBQ_5158,{4U,4U,0U}}, +{SUBQ_5158,{5U,4U,0U}}, +{SUBQ_5158,{6U,4U,0U}}, +{SUBQ_5158,{7U,4U,0U}}, +{SUBQ_5160,{0U,4U,0U}}, +{SUBQ_5160,{1U,4U,0U}}, +{SUBQ_5160,{2U,4U,0U}}, +{SUBQ_5160,{3U,4U,0U}}, +{SUBQ_5160,{4U,4U,0U}}, +{SUBQ_5160,{5U,4U,0U}}, +{SUBQ_5160,{6U,4U,0U}}, +{SUBQ_5160,{7U,4U,0U}}, +{SUBQ_5168,{0U,4U,0U}}, +{SUBQ_5168,{1U,4U,0U}}, +{SUBQ_5168,{2U,4U,0U}}, +{SUBQ_5168,{3U,4U,0U}}, +{SUBQ_5168,{4U,4U,0U}}, +{SUBQ_5168,{5U,4U,0U}}, +{SUBQ_5168,{6U,4U,0U}}, +{SUBQ_5168,{7U,4U,0U}}, +{SUBQ_5170,{0U,4U,0U}}, +{SUBQ_5170,{1U,4U,0U}}, +{SUBQ_5170,{2U,4U,0U}}, +{SUBQ_5170,{3U,4U,0U}}, +{SUBQ_5170,{4U,4U,0U}}, +{SUBQ_5170,{5U,4U,0U}}, +{SUBQ_5170,{6U,4U,0U}}, +{SUBQ_5170,{7U,4U,0U}}, +{SUBQ_5178,{0U,4U,0U}}, +{SUBQ_5179,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5180,{0U,4U,0U}}, +{SUBQ_5180,{1U,4U,0U}}, +{SUBQ_5180,{2U,4U,0U}}, +{SUBQ_5180,{3U,4U,0U}}, +{SUBQ_5180,{4U,4U,0U}}, +{SUBQ_5180,{5U,4U,0U}}, +{SUBQ_5180,{6U,4U,0U}}, +{SUBQ_5180,{7U,4U,0U}}, +{SUBQ_5188,{0U,4U,0U}}, +{SUBQ_5188,{1U,4U,0U}}, +{SUBQ_5188,{2U,4U,0U}}, +{SUBQ_5188,{3U,4U,0U}}, +{SUBQ_5188,{4U,4U,0U}}, +{SUBQ_5188,{5U,4U,0U}}, +{SUBQ_5188,{6U,4U,0U}}, +{SUBQ_5188,{7U,4U,0U}}, +{SUBQ_5190,{0U,4U,0U}}, +{SUBQ_5190,{1U,4U,0U}}, +{SUBQ_5190,{2U,4U,0U}}, +{SUBQ_5190,{3U,4U,0U}}, +{SUBQ_5190,{4U,4U,0U}}, +{SUBQ_5190,{5U,4U,0U}}, +{SUBQ_5190,{6U,4U,0U}}, +{SUBQ_5190,{7U,4U,0U}}, +{SUBQ_5198,{0U,4U,0U}}, +{SUBQ_5198,{1U,4U,0U}}, +{SUBQ_5198,{2U,4U,0U}}, +{SUBQ_5198,{3U,4U,0U}}, +{SUBQ_5198,{4U,4U,0U}}, +{SUBQ_5198,{5U,4U,0U}}, +{SUBQ_5198,{6U,4U,0U}}, +{SUBQ_5198,{7U,4U,0U}}, +{SUBQ_51A0,{0U,4U,0U}}, +{SUBQ_51A0,{1U,4U,0U}}, +{SUBQ_51A0,{2U,4U,0U}}, +{SUBQ_51A0,{3U,4U,0U}}, +{SUBQ_51A0,{4U,4U,0U}}, +{SUBQ_51A0,{5U,4U,0U}}, +{SUBQ_51A0,{6U,4U,0U}}, +{SUBQ_51A0,{7U,4U,0U}}, +{SUBQ_51A8,{0U,4U,0U}}, +{SUBQ_51A8,{1U,4U,0U}}, +{SUBQ_51A8,{2U,4U,0U}}, +{SUBQ_51A8,{3U,4U,0U}}, +{SUBQ_51A8,{4U,4U,0U}}, +{SUBQ_51A8,{5U,4U,0U}}, +{SUBQ_51A8,{6U,4U,0U}}, +{SUBQ_51A8,{7U,4U,0U}}, +{SUBQ_51B0,{0U,4U,0U}}, +{SUBQ_51B0,{1U,4U,0U}}, +{SUBQ_51B0,{2U,4U,0U}}, +{SUBQ_51B0,{3U,4U,0U}}, +{SUBQ_51B0,{4U,4U,0U}}, +{SUBQ_51B0,{5U,4U,0U}}, +{SUBQ_51B0,{6U,4U,0U}}, +{SUBQ_51B0,{7U,4U,0U}}, +{SUBQ_51B8,{0U,4U,0U}}, +{SUBQ_51B9,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,9U,0U}}, +{SCC_50C0,{1U,9U,0U}}, +{SCC_50C0,{2U,9U,0U}}, +{SCC_50C0,{3U,9U,0U}}, +{SCC_50C0,{4U,9U,0U}}, +{SCC_50C0,{5U,9U,0U}}, +{SCC_50C0,{6U,9U,0U}}, +{SCC_50C0,{7U,9U,0U}}, +{DBCC_59C8,{0U,0U,0U}}, +{DBCC_59C8,{0U,1U,0U}}, +{DBCC_59C8,{0U,2U,0U}}, +{DBCC_59C8,{0U,3U,0U}}, +{DBCC_59C8,{0U,4U,0U}}, +{DBCC_59C8,{0U,5U,0U}}, +{DBCC_59C8,{0U,6U,0U}}, +{DBCC_59C8,{0U,7U,0U}}, +{SCC_50D0,{0U,9U,0U}}, +{SCC_50D0,{1U,9U,0U}}, +{SCC_50D0,{2U,9U,0U}}, +{SCC_50D0,{3U,9U,0U}}, +{SCC_50D0,{4U,9U,0U}}, +{SCC_50D0,{5U,9U,0U}}, +{SCC_50D0,{6U,9U,0U}}, +{SCC_50D0,{7U,9U,0U}}, +{SCC_50D8,{0U,9U,0U}}, +{SCC_50D8,{1U,9U,0U}}, +{SCC_50D8,{2U,9U,0U}}, +{SCC_50D8,{3U,9U,0U}}, +{SCC_50D8,{4U,9U,0U}}, +{SCC_50D8,{5U,9U,0U}}, +{SCC_50D8,{6U,9U,0U}}, +{SCC_50D8,{7U,9U,0U}}, +{SCC_50E0,{0U,9U,0U}}, +{SCC_50E0,{1U,9U,0U}}, +{SCC_50E0,{2U,9U,0U}}, +{SCC_50E0,{3U,9U,0U}}, +{SCC_50E0,{4U,9U,0U}}, +{SCC_50E0,{5U,9U,0U}}, +{SCC_50E0,{6U,9U,0U}}, +{SCC_50E0,{7U,9U,0U}}, +{SCC_50E8,{0U,9U,0U}}, +{SCC_50E8,{1U,9U,0U}}, +{SCC_50E8,{2U,9U,0U}}, +{SCC_50E8,{3U,9U,0U}}, +{SCC_50E8,{4U,9U,0U}}, +{SCC_50E8,{5U,9U,0U}}, +{SCC_50E8,{6U,9U,0U}}, +{SCC_50E8,{7U,9U,0U}}, +{SCC_50F0,{0U,9U,0U}}, +{SCC_50F0,{1U,9U,0U}}, +{SCC_50F0,{2U,9U,0U}}, +{SCC_50F0,{3U,9U,0U}}, +{SCC_50F0,{4U,9U,0U}}, +{SCC_50F0,{5U,9U,0U}}, +{SCC_50F0,{6U,9U,0U}}, +{SCC_50F0,{7U,9U,0U}}, +{SCC_50F8,{0U,9U,0U}}, +{SCC_50F9,{0U,9U,0U}}, +{TRAPCC_59FA,{0U,0U,0U}}, +{TRAPCC_59FB,{0U,0U,0U}}, +{TRAPCC_59FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5000,{0U,5U,0U}}, +{ADDQ_5000,{1U,5U,0U}}, +{ADDQ_5000,{2U,5U,0U}}, +{ADDQ_5000,{3U,5U,0U}}, +{ADDQ_5000,{4U,5U,0U}}, +{ADDQ_5000,{5U,5U,0U}}, +{ADDQ_5000,{6U,5U,0U}}, +{ADDQ_5000,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5010,{0U,5U,0U}}, +{ADDQ_5010,{1U,5U,0U}}, +{ADDQ_5010,{2U,5U,0U}}, +{ADDQ_5010,{3U,5U,0U}}, +{ADDQ_5010,{4U,5U,0U}}, +{ADDQ_5010,{5U,5U,0U}}, +{ADDQ_5010,{6U,5U,0U}}, +{ADDQ_5010,{7U,5U,0U}}, +{ADDQ_5018,{0U,5U,0U}}, +{ADDQ_5018,{1U,5U,0U}}, +{ADDQ_5018,{2U,5U,0U}}, +{ADDQ_5018,{3U,5U,0U}}, +{ADDQ_5018,{4U,5U,0U}}, +{ADDQ_5018,{5U,5U,0U}}, +{ADDQ_5018,{6U,5U,0U}}, +{ADDQ_5018,{7U,5U,0U}}, +{ADDQ_5020,{0U,5U,0U}}, +{ADDQ_5020,{1U,5U,0U}}, +{ADDQ_5020,{2U,5U,0U}}, +{ADDQ_5020,{3U,5U,0U}}, +{ADDQ_5020,{4U,5U,0U}}, +{ADDQ_5020,{5U,5U,0U}}, +{ADDQ_5020,{6U,5U,0U}}, +{ADDQ_5020,{7U,5U,0U}}, +{ADDQ_5028,{0U,5U,0U}}, +{ADDQ_5028,{1U,5U,0U}}, +{ADDQ_5028,{2U,5U,0U}}, +{ADDQ_5028,{3U,5U,0U}}, +{ADDQ_5028,{4U,5U,0U}}, +{ADDQ_5028,{5U,5U,0U}}, +{ADDQ_5028,{6U,5U,0U}}, +{ADDQ_5028,{7U,5U,0U}}, +{ADDQ_5030,{0U,5U,0U}}, +{ADDQ_5030,{1U,5U,0U}}, +{ADDQ_5030,{2U,5U,0U}}, +{ADDQ_5030,{3U,5U,0U}}, +{ADDQ_5030,{4U,5U,0U}}, +{ADDQ_5030,{5U,5U,0U}}, +{ADDQ_5030,{6U,5U,0U}}, +{ADDQ_5030,{7U,5U,0U}}, +{ADDQ_5038,{0U,5U,0U}}, +{ADDQ_5039,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5040,{0U,5U,0U}}, +{ADDQ_5040,{1U,5U,0U}}, +{ADDQ_5040,{2U,5U,0U}}, +{ADDQ_5040,{3U,5U,0U}}, +{ADDQ_5040,{4U,5U,0U}}, +{ADDQ_5040,{5U,5U,0U}}, +{ADDQ_5040,{6U,5U,0U}}, +{ADDQ_5040,{7U,5U,0U}}, +{ADDQ_5048,{0U,5U,0U}}, +{ADDQ_5048,{1U,5U,0U}}, +{ADDQ_5048,{2U,5U,0U}}, +{ADDQ_5048,{3U,5U,0U}}, +{ADDQ_5048,{4U,5U,0U}}, +{ADDQ_5048,{5U,5U,0U}}, +{ADDQ_5048,{6U,5U,0U}}, +{ADDQ_5048,{7U,5U,0U}}, +{ADDQ_5050,{0U,5U,0U}}, +{ADDQ_5050,{1U,5U,0U}}, +{ADDQ_5050,{2U,5U,0U}}, +{ADDQ_5050,{3U,5U,0U}}, +{ADDQ_5050,{4U,5U,0U}}, +{ADDQ_5050,{5U,5U,0U}}, +{ADDQ_5050,{6U,5U,0U}}, +{ADDQ_5050,{7U,5U,0U}}, +{ADDQ_5058,{0U,5U,0U}}, +{ADDQ_5058,{1U,5U,0U}}, +{ADDQ_5058,{2U,5U,0U}}, +{ADDQ_5058,{3U,5U,0U}}, +{ADDQ_5058,{4U,5U,0U}}, +{ADDQ_5058,{5U,5U,0U}}, +{ADDQ_5058,{6U,5U,0U}}, +{ADDQ_5058,{7U,5U,0U}}, +{ADDQ_5060,{0U,5U,0U}}, +{ADDQ_5060,{1U,5U,0U}}, +{ADDQ_5060,{2U,5U,0U}}, +{ADDQ_5060,{3U,5U,0U}}, +{ADDQ_5060,{4U,5U,0U}}, +{ADDQ_5060,{5U,5U,0U}}, +{ADDQ_5060,{6U,5U,0U}}, +{ADDQ_5060,{7U,5U,0U}}, +{ADDQ_5068,{0U,5U,0U}}, +{ADDQ_5068,{1U,5U,0U}}, +{ADDQ_5068,{2U,5U,0U}}, +{ADDQ_5068,{3U,5U,0U}}, +{ADDQ_5068,{4U,5U,0U}}, +{ADDQ_5068,{5U,5U,0U}}, +{ADDQ_5068,{6U,5U,0U}}, +{ADDQ_5068,{7U,5U,0U}}, +{ADDQ_5070,{0U,5U,0U}}, +{ADDQ_5070,{1U,5U,0U}}, +{ADDQ_5070,{2U,5U,0U}}, +{ADDQ_5070,{3U,5U,0U}}, +{ADDQ_5070,{4U,5U,0U}}, +{ADDQ_5070,{5U,5U,0U}}, +{ADDQ_5070,{6U,5U,0U}}, +{ADDQ_5070,{7U,5U,0U}}, +{ADDQ_5078,{0U,5U,0U}}, +{ADDQ_5079,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5080,{0U,5U,0U}}, +{ADDQ_5080,{1U,5U,0U}}, +{ADDQ_5080,{2U,5U,0U}}, +{ADDQ_5080,{3U,5U,0U}}, +{ADDQ_5080,{4U,5U,0U}}, +{ADDQ_5080,{5U,5U,0U}}, +{ADDQ_5080,{6U,5U,0U}}, +{ADDQ_5080,{7U,5U,0U}}, +{ADDQ_5088,{0U,5U,0U}}, +{ADDQ_5088,{1U,5U,0U}}, +{ADDQ_5088,{2U,5U,0U}}, +{ADDQ_5088,{3U,5U,0U}}, +{ADDQ_5088,{4U,5U,0U}}, +{ADDQ_5088,{5U,5U,0U}}, +{ADDQ_5088,{6U,5U,0U}}, +{ADDQ_5088,{7U,5U,0U}}, +{ADDQ_5090,{0U,5U,0U}}, +{ADDQ_5090,{1U,5U,0U}}, +{ADDQ_5090,{2U,5U,0U}}, +{ADDQ_5090,{3U,5U,0U}}, +{ADDQ_5090,{4U,5U,0U}}, +{ADDQ_5090,{5U,5U,0U}}, +{ADDQ_5090,{6U,5U,0U}}, +{ADDQ_5090,{7U,5U,0U}}, +{ADDQ_5098,{0U,5U,0U}}, +{ADDQ_5098,{1U,5U,0U}}, +{ADDQ_5098,{2U,5U,0U}}, +{ADDQ_5098,{3U,5U,0U}}, +{ADDQ_5098,{4U,5U,0U}}, +{ADDQ_5098,{5U,5U,0U}}, +{ADDQ_5098,{6U,5U,0U}}, +{ADDQ_5098,{7U,5U,0U}}, +{ADDQ_50A0,{0U,5U,0U}}, +{ADDQ_50A0,{1U,5U,0U}}, +{ADDQ_50A0,{2U,5U,0U}}, +{ADDQ_50A0,{3U,5U,0U}}, +{ADDQ_50A0,{4U,5U,0U}}, +{ADDQ_50A0,{5U,5U,0U}}, +{ADDQ_50A0,{6U,5U,0U}}, +{ADDQ_50A0,{7U,5U,0U}}, +{ADDQ_50A8,{0U,5U,0U}}, +{ADDQ_50A8,{1U,5U,0U}}, +{ADDQ_50A8,{2U,5U,0U}}, +{ADDQ_50A8,{3U,5U,0U}}, +{ADDQ_50A8,{4U,5U,0U}}, +{ADDQ_50A8,{5U,5U,0U}}, +{ADDQ_50A8,{6U,5U,0U}}, +{ADDQ_50A8,{7U,5U,0U}}, +{ADDQ_50B0,{0U,5U,0U}}, +{ADDQ_50B0,{1U,5U,0U}}, +{ADDQ_50B0,{2U,5U,0U}}, +{ADDQ_50B0,{3U,5U,0U}}, +{ADDQ_50B0,{4U,5U,0U}}, +{ADDQ_50B0,{5U,5U,0U}}, +{ADDQ_50B0,{6U,5U,0U}}, +{ADDQ_50B0,{7U,5U,0U}}, +{ADDQ_50B8,{0U,5U,0U}}, +{ADDQ_50B9,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,10U,0U}}, +{SCC_50C0,{1U,10U,0U}}, +{SCC_50C0,{2U,10U,0U}}, +{SCC_50C0,{3U,10U,0U}}, +{SCC_50C0,{4U,10U,0U}}, +{SCC_50C0,{5U,10U,0U}}, +{SCC_50C0,{6U,10U,0U}}, +{SCC_50C0,{7U,10U,0U}}, +{DBCC_5AC8,{0U,0U,0U}}, +{DBCC_5AC8,{0U,1U,0U}}, +{DBCC_5AC8,{0U,2U,0U}}, +{DBCC_5AC8,{0U,3U,0U}}, +{DBCC_5AC8,{0U,4U,0U}}, +{DBCC_5AC8,{0U,5U,0U}}, +{DBCC_5AC8,{0U,6U,0U}}, +{DBCC_5AC8,{0U,7U,0U}}, +{SCC_50D0,{0U,10U,0U}}, +{SCC_50D0,{1U,10U,0U}}, +{SCC_50D0,{2U,10U,0U}}, +{SCC_50D0,{3U,10U,0U}}, +{SCC_50D0,{4U,10U,0U}}, +{SCC_50D0,{5U,10U,0U}}, +{SCC_50D0,{6U,10U,0U}}, +{SCC_50D0,{7U,10U,0U}}, +{SCC_50D8,{0U,10U,0U}}, +{SCC_50D8,{1U,10U,0U}}, +{SCC_50D8,{2U,10U,0U}}, +{SCC_50D8,{3U,10U,0U}}, +{SCC_50D8,{4U,10U,0U}}, +{SCC_50D8,{5U,10U,0U}}, +{SCC_50D8,{6U,10U,0U}}, +{SCC_50D8,{7U,10U,0U}}, +{SCC_50E0,{0U,10U,0U}}, +{SCC_50E0,{1U,10U,0U}}, +{SCC_50E0,{2U,10U,0U}}, +{SCC_50E0,{3U,10U,0U}}, +{SCC_50E0,{4U,10U,0U}}, +{SCC_50E0,{5U,10U,0U}}, +{SCC_50E0,{6U,10U,0U}}, +{SCC_50E0,{7U,10U,0U}}, +{SCC_50E8,{0U,10U,0U}}, +{SCC_50E8,{1U,10U,0U}}, +{SCC_50E8,{2U,10U,0U}}, +{SCC_50E8,{3U,10U,0U}}, +{SCC_50E8,{4U,10U,0U}}, +{SCC_50E8,{5U,10U,0U}}, +{SCC_50E8,{6U,10U,0U}}, +{SCC_50E8,{7U,10U,0U}}, +{SCC_50F0,{0U,10U,0U}}, +{SCC_50F0,{1U,10U,0U}}, +{SCC_50F0,{2U,10U,0U}}, +{SCC_50F0,{3U,10U,0U}}, +{SCC_50F0,{4U,10U,0U}}, +{SCC_50F0,{5U,10U,0U}}, +{SCC_50F0,{6U,10U,0U}}, +{SCC_50F0,{7U,10U,0U}}, +{SCC_50F8,{0U,10U,0U}}, +{SCC_50F9,{0U,10U,0U}}, +{TRAPCC_5AFA,{0U,0U,0U}}, +{TRAPCC_5AFB,{0U,0U,0U}}, +{TRAPCC_5AFC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5100,{0U,5U,0U}}, +{SUBQ_5100,{1U,5U,0U}}, +{SUBQ_5100,{2U,5U,0U}}, +{SUBQ_5100,{3U,5U,0U}}, +{SUBQ_5100,{4U,5U,0U}}, +{SUBQ_5100,{5U,5U,0U}}, +{SUBQ_5100,{6U,5U,0U}}, +{SUBQ_5100,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5110,{0U,5U,0U}}, +{SUBQ_5110,{1U,5U,0U}}, +{SUBQ_5110,{2U,5U,0U}}, +{SUBQ_5110,{3U,5U,0U}}, +{SUBQ_5110,{4U,5U,0U}}, +{SUBQ_5110,{5U,5U,0U}}, +{SUBQ_5110,{6U,5U,0U}}, +{SUBQ_5110,{7U,5U,0U}}, +{SUBQ_5118,{0U,5U,0U}}, +{SUBQ_5118,{1U,5U,0U}}, +{SUBQ_5118,{2U,5U,0U}}, +{SUBQ_5118,{3U,5U,0U}}, +{SUBQ_5118,{4U,5U,0U}}, +{SUBQ_5118,{5U,5U,0U}}, +{SUBQ_5118,{6U,5U,0U}}, +{SUBQ_5118,{7U,5U,0U}}, +{SUBQ_5120,{0U,5U,0U}}, +{SUBQ_5120,{1U,5U,0U}}, +{SUBQ_5120,{2U,5U,0U}}, +{SUBQ_5120,{3U,5U,0U}}, +{SUBQ_5120,{4U,5U,0U}}, +{SUBQ_5120,{5U,5U,0U}}, +{SUBQ_5120,{6U,5U,0U}}, +{SUBQ_5120,{7U,5U,0U}}, +{SUBQ_5128,{0U,5U,0U}}, +{SUBQ_5128,{1U,5U,0U}}, +{SUBQ_5128,{2U,5U,0U}}, +{SUBQ_5128,{3U,5U,0U}}, +{SUBQ_5128,{4U,5U,0U}}, +{SUBQ_5128,{5U,5U,0U}}, +{SUBQ_5128,{6U,5U,0U}}, +{SUBQ_5128,{7U,5U,0U}}, +{SUBQ_5130,{0U,5U,0U}}, +{SUBQ_5130,{1U,5U,0U}}, +{SUBQ_5130,{2U,5U,0U}}, +{SUBQ_5130,{3U,5U,0U}}, +{SUBQ_5130,{4U,5U,0U}}, +{SUBQ_5130,{5U,5U,0U}}, +{SUBQ_5130,{6U,5U,0U}}, +{SUBQ_5130,{7U,5U,0U}}, +{SUBQ_5138,{0U,5U,0U}}, +{SUBQ_5139,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5140,{0U,5U,0U}}, +{SUBQ_5140,{1U,5U,0U}}, +{SUBQ_5140,{2U,5U,0U}}, +{SUBQ_5140,{3U,5U,0U}}, +{SUBQ_5140,{4U,5U,0U}}, +{SUBQ_5140,{5U,5U,0U}}, +{SUBQ_5140,{6U,5U,0U}}, +{SUBQ_5140,{7U,5U,0U}}, +{SUBQ_5148,{0U,5U,0U}}, +{SUBQ_5148,{1U,5U,0U}}, +{SUBQ_5148,{2U,5U,0U}}, +{SUBQ_5148,{3U,5U,0U}}, +{SUBQ_5148,{4U,5U,0U}}, +{SUBQ_5148,{5U,5U,0U}}, +{SUBQ_5148,{6U,5U,0U}}, +{SUBQ_5148,{7U,5U,0U}}, +{SUBQ_5150,{0U,5U,0U}}, +{SUBQ_5150,{1U,5U,0U}}, +{SUBQ_5150,{2U,5U,0U}}, +{SUBQ_5150,{3U,5U,0U}}, +{SUBQ_5150,{4U,5U,0U}}, +{SUBQ_5150,{5U,5U,0U}}, +{SUBQ_5150,{6U,5U,0U}}, +{SUBQ_5150,{7U,5U,0U}}, +{SUBQ_5158,{0U,5U,0U}}, +{SUBQ_5158,{1U,5U,0U}}, +{SUBQ_5158,{2U,5U,0U}}, +{SUBQ_5158,{3U,5U,0U}}, +{SUBQ_5158,{4U,5U,0U}}, +{SUBQ_5158,{5U,5U,0U}}, +{SUBQ_5158,{6U,5U,0U}}, +{SUBQ_5158,{7U,5U,0U}}, +{SUBQ_5160,{0U,5U,0U}}, +{SUBQ_5160,{1U,5U,0U}}, +{SUBQ_5160,{2U,5U,0U}}, +{SUBQ_5160,{3U,5U,0U}}, +{SUBQ_5160,{4U,5U,0U}}, +{SUBQ_5160,{5U,5U,0U}}, +{SUBQ_5160,{6U,5U,0U}}, +{SUBQ_5160,{7U,5U,0U}}, +{SUBQ_5168,{0U,5U,0U}}, +{SUBQ_5168,{1U,5U,0U}}, +{SUBQ_5168,{2U,5U,0U}}, +{SUBQ_5168,{3U,5U,0U}}, +{SUBQ_5168,{4U,5U,0U}}, +{SUBQ_5168,{5U,5U,0U}}, +{SUBQ_5168,{6U,5U,0U}}, +{SUBQ_5168,{7U,5U,0U}}, +{SUBQ_5170,{0U,5U,0U}}, +{SUBQ_5170,{1U,5U,0U}}, +{SUBQ_5170,{2U,5U,0U}}, +{SUBQ_5170,{3U,5U,0U}}, +{SUBQ_5170,{4U,5U,0U}}, +{SUBQ_5170,{5U,5U,0U}}, +{SUBQ_5170,{6U,5U,0U}}, +{SUBQ_5170,{7U,5U,0U}}, +{SUBQ_5178,{0U,5U,0U}}, +{SUBQ_5179,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5180,{0U,5U,0U}}, +{SUBQ_5180,{1U,5U,0U}}, +{SUBQ_5180,{2U,5U,0U}}, +{SUBQ_5180,{3U,5U,0U}}, +{SUBQ_5180,{4U,5U,0U}}, +{SUBQ_5180,{5U,5U,0U}}, +{SUBQ_5180,{6U,5U,0U}}, +{SUBQ_5180,{7U,5U,0U}}, +{SUBQ_5188,{0U,5U,0U}}, +{SUBQ_5188,{1U,5U,0U}}, +{SUBQ_5188,{2U,5U,0U}}, +{SUBQ_5188,{3U,5U,0U}}, +{SUBQ_5188,{4U,5U,0U}}, +{SUBQ_5188,{5U,5U,0U}}, +{SUBQ_5188,{6U,5U,0U}}, +{SUBQ_5188,{7U,5U,0U}}, +{SUBQ_5190,{0U,5U,0U}}, +{SUBQ_5190,{1U,5U,0U}}, +{SUBQ_5190,{2U,5U,0U}}, +{SUBQ_5190,{3U,5U,0U}}, +{SUBQ_5190,{4U,5U,0U}}, +{SUBQ_5190,{5U,5U,0U}}, +{SUBQ_5190,{6U,5U,0U}}, +{SUBQ_5190,{7U,5U,0U}}, +{SUBQ_5198,{0U,5U,0U}}, +{SUBQ_5198,{1U,5U,0U}}, +{SUBQ_5198,{2U,5U,0U}}, +{SUBQ_5198,{3U,5U,0U}}, +{SUBQ_5198,{4U,5U,0U}}, +{SUBQ_5198,{5U,5U,0U}}, +{SUBQ_5198,{6U,5U,0U}}, +{SUBQ_5198,{7U,5U,0U}}, +{SUBQ_51A0,{0U,5U,0U}}, +{SUBQ_51A0,{1U,5U,0U}}, +{SUBQ_51A0,{2U,5U,0U}}, +{SUBQ_51A0,{3U,5U,0U}}, +{SUBQ_51A0,{4U,5U,0U}}, +{SUBQ_51A0,{5U,5U,0U}}, +{SUBQ_51A0,{6U,5U,0U}}, +{SUBQ_51A0,{7U,5U,0U}}, +{SUBQ_51A8,{0U,5U,0U}}, +{SUBQ_51A8,{1U,5U,0U}}, +{SUBQ_51A8,{2U,5U,0U}}, +{SUBQ_51A8,{3U,5U,0U}}, +{SUBQ_51A8,{4U,5U,0U}}, +{SUBQ_51A8,{5U,5U,0U}}, +{SUBQ_51A8,{6U,5U,0U}}, +{SUBQ_51A8,{7U,5U,0U}}, +{SUBQ_51B0,{0U,5U,0U}}, +{SUBQ_51B0,{1U,5U,0U}}, +{SUBQ_51B0,{2U,5U,0U}}, +{SUBQ_51B0,{3U,5U,0U}}, +{SUBQ_51B0,{4U,5U,0U}}, +{SUBQ_51B0,{5U,5U,0U}}, +{SUBQ_51B0,{6U,5U,0U}}, +{SUBQ_51B0,{7U,5U,0U}}, +{SUBQ_51B8,{0U,5U,0U}}, +{SUBQ_51B9,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,11U,0U}}, +{SCC_50C0,{1U,11U,0U}}, +{SCC_50C0,{2U,11U,0U}}, +{SCC_50C0,{3U,11U,0U}}, +{SCC_50C0,{4U,11U,0U}}, +{SCC_50C0,{5U,11U,0U}}, +{SCC_50C0,{6U,11U,0U}}, +{SCC_50C0,{7U,11U,0U}}, +{DBCC_5BC8,{0U,0U,0U}}, +{DBCC_5BC8,{0U,1U,0U}}, +{DBCC_5BC8,{0U,2U,0U}}, +{DBCC_5BC8,{0U,3U,0U}}, +{DBCC_5BC8,{0U,4U,0U}}, +{DBCC_5BC8,{0U,5U,0U}}, +{DBCC_5BC8,{0U,6U,0U}}, +{DBCC_5BC8,{0U,7U,0U}}, +{SCC_50D0,{0U,11U,0U}}, +{SCC_50D0,{1U,11U,0U}}, +{SCC_50D0,{2U,11U,0U}}, +{SCC_50D0,{3U,11U,0U}}, +{SCC_50D0,{4U,11U,0U}}, +{SCC_50D0,{5U,11U,0U}}, +{SCC_50D0,{6U,11U,0U}}, +{SCC_50D0,{7U,11U,0U}}, +{SCC_50D8,{0U,11U,0U}}, +{SCC_50D8,{1U,11U,0U}}, +{SCC_50D8,{2U,11U,0U}}, +{SCC_50D8,{3U,11U,0U}}, +{SCC_50D8,{4U,11U,0U}}, +{SCC_50D8,{5U,11U,0U}}, +{SCC_50D8,{6U,11U,0U}}, +{SCC_50D8,{7U,11U,0U}}, +{SCC_50E0,{0U,11U,0U}}, +{SCC_50E0,{1U,11U,0U}}, +{SCC_50E0,{2U,11U,0U}}, +{SCC_50E0,{3U,11U,0U}}, +{SCC_50E0,{4U,11U,0U}}, +{SCC_50E0,{5U,11U,0U}}, +{SCC_50E0,{6U,11U,0U}}, +{SCC_50E0,{7U,11U,0U}}, +{SCC_50E8,{0U,11U,0U}}, +{SCC_50E8,{1U,11U,0U}}, +{SCC_50E8,{2U,11U,0U}}, +{SCC_50E8,{3U,11U,0U}}, +{SCC_50E8,{4U,11U,0U}}, +{SCC_50E8,{5U,11U,0U}}, +{SCC_50E8,{6U,11U,0U}}, +{SCC_50E8,{7U,11U,0U}}, +{SCC_50F0,{0U,11U,0U}}, +{SCC_50F0,{1U,11U,0U}}, +{SCC_50F0,{2U,11U,0U}}, +{SCC_50F0,{3U,11U,0U}}, +{SCC_50F0,{4U,11U,0U}}, +{SCC_50F0,{5U,11U,0U}}, +{SCC_50F0,{6U,11U,0U}}, +{SCC_50F0,{7U,11U,0U}}, +{SCC_50F8,{0U,11U,0U}}, +{SCC_50F9,{0U,11U,0U}}, +{TRAPCC_5BFA,{0U,0U,0U}}, +{TRAPCC_5BFB,{0U,0U,0U}}, +{TRAPCC_5BFC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5000,{0U,6U,0U}}, +{ADDQ_5000,{1U,6U,0U}}, +{ADDQ_5000,{2U,6U,0U}}, +{ADDQ_5000,{3U,6U,0U}}, +{ADDQ_5000,{4U,6U,0U}}, +{ADDQ_5000,{5U,6U,0U}}, +{ADDQ_5000,{6U,6U,0U}}, +{ADDQ_5000,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5010,{0U,6U,0U}}, +{ADDQ_5010,{1U,6U,0U}}, +{ADDQ_5010,{2U,6U,0U}}, +{ADDQ_5010,{3U,6U,0U}}, +{ADDQ_5010,{4U,6U,0U}}, +{ADDQ_5010,{5U,6U,0U}}, +{ADDQ_5010,{6U,6U,0U}}, +{ADDQ_5010,{7U,6U,0U}}, +{ADDQ_5018,{0U,6U,0U}}, +{ADDQ_5018,{1U,6U,0U}}, +{ADDQ_5018,{2U,6U,0U}}, +{ADDQ_5018,{3U,6U,0U}}, +{ADDQ_5018,{4U,6U,0U}}, +{ADDQ_5018,{5U,6U,0U}}, +{ADDQ_5018,{6U,6U,0U}}, +{ADDQ_5018,{7U,6U,0U}}, +{ADDQ_5020,{0U,6U,0U}}, +{ADDQ_5020,{1U,6U,0U}}, +{ADDQ_5020,{2U,6U,0U}}, +{ADDQ_5020,{3U,6U,0U}}, +{ADDQ_5020,{4U,6U,0U}}, +{ADDQ_5020,{5U,6U,0U}}, +{ADDQ_5020,{6U,6U,0U}}, +{ADDQ_5020,{7U,6U,0U}}, +{ADDQ_5028,{0U,6U,0U}}, +{ADDQ_5028,{1U,6U,0U}}, +{ADDQ_5028,{2U,6U,0U}}, +{ADDQ_5028,{3U,6U,0U}}, +{ADDQ_5028,{4U,6U,0U}}, +{ADDQ_5028,{5U,6U,0U}}, +{ADDQ_5028,{6U,6U,0U}}, +{ADDQ_5028,{7U,6U,0U}}, +{ADDQ_5030,{0U,6U,0U}}, +{ADDQ_5030,{1U,6U,0U}}, +{ADDQ_5030,{2U,6U,0U}}, +{ADDQ_5030,{3U,6U,0U}}, +{ADDQ_5030,{4U,6U,0U}}, +{ADDQ_5030,{5U,6U,0U}}, +{ADDQ_5030,{6U,6U,0U}}, +{ADDQ_5030,{7U,6U,0U}}, +{ADDQ_5038,{0U,6U,0U}}, +{ADDQ_5039,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5040,{0U,6U,0U}}, +{ADDQ_5040,{1U,6U,0U}}, +{ADDQ_5040,{2U,6U,0U}}, +{ADDQ_5040,{3U,6U,0U}}, +{ADDQ_5040,{4U,6U,0U}}, +{ADDQ_5040,{5U,6U,0U}}, +{ADDQ_5040,{6U,6U,0U}}, +{ADDQ_5040,{7U,6U,0U}}, +{ADDQ_5048,{0U,6U,0U}}, +{ADDQ_5048,{1U,6U,0U}}, +{ADDQ_5048,{2U,6U,0U}}, +{ADDQ_5048,{3U,6U,0U}}, +{ADDQ_5048,{4U,6U,0U}}, +{ADDQ_5048,{5U,6U,0U}}, +{ADDQ_5048,{6U,6U,0U}}, +{ADDQ_5048,{7U,6U,0U}}, +{ADDQ_5050,{0U,6U,0U}}, +{ADDQ_5050,{1U,6U,0U}}, +{ADDQ_5050,{2U,6U,0U}}, +{ADDQ_5050,{3U,6U,0U}}, +{ADDQ_5050,{4U,6U,0U}}, +{ADDQ_5050,{5U,6U,0U}}, +{ADDQ_5050,{6U,6U,0U}}, +{ADDQ_5050,{7U,6U,0U}}, +{ADDQ_5058,{0U,6U,0U}}, +{ADDQ_5058,{1U,6U,0U}}, +{ADDQ_5058,{2U,6U,0U}}, +{ADDQ_5058,{3U,6U,0U}}, +{ADDQ_5058,{4U,6U,0U}}, +{ADDQ_5058,{5U,6U,0U}}, +{ADDQ_5058,{6U,6U,0U}}, +{ADDQ_5058,{7U,6U,0U}}, +{ADDQ_5060,{0U,6U,0U}}, +{ADDQ_5060,{1U,6U,0U}}, +{ADDQ_5060,{2U,6U,0U}}, +{ADDQ_5060,{3U,6U,0U}}, +{ADDQ_5060,{4U,6U,0U}}, +{ADDQ_5060,{5U,6U,0U}}, +{ADDQ_5060,{6U,6U,0U}}, +{ADDQ_5060,{7U,6U,0U}}, +{ADDQ_5068,{0U,6U,0U}}, +{ADDQ_5068,{1U,6U,0U}}, +{ADDQ_5068,{2U,6U,0U}}, +{ADDQ_5068,{3U,6U,0U}}, +{ADDQ_5068,{4U,6U,0U}}, +{ADDQ_5068,{5U,6U,0U}}, +{ADDQ_5068,{6U,6U,0U}}, +{ADDQ_5068,{7U,6U,0U}}, +{ADDQ_5070,{0U,6U,0U}}, +{ADDQ_5070,{1U,6U,0U}}, +{ADDQ_5070,{2U,6U,0U}}, +{ADDQ_5070,{3U,6U,0U}}, +{ADDQ_5070,{4U,6U,0U}}, +{ADDQ_5070,{5U,6U,0U}}, +{ADDQ_5070,{6U,6U,0U}}, +{ADDQ_5070,{7U,6U,0U}}, +{ADDQ_5078,{0U,6U,0U}}, +{ADDQ_5079,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5080,{0U,6U,0U}}, +{ADDQ_5080,{1U,6U,0U}}, +{ADDQ_5080,{2U,6U,0U}}, +{ADDQ_5080,{3U,6U,0U}}, +{ADDQ_5080,{4U,6U,0U}}, +{ADDQ_5080,{5U,6U,0U}}, +{ADDQ_5080,{6U,6U,0U}}, +{ADDQ_5080,{7U,6U,0U}}, +{ADDQ_5088,{0U,6U,0U}}, +{ADDQ_5088,{1U,6U,0U}}, +{ADDQ_5088,{2U,6U,0U}}, +{ADDQ_5088,{3U,6U,0U}}, +{ADDQ_5088,{4U,6U,0U}}, +{ADDQ_5088,{5U,6U,0U}}, +{ADDQ_5088,{6U,6U,0U}}, +{ADDQ_5088,{7U,6U,0U}}, +{ADDQ_5090,{0U,6U,0U}}, +{ADDQ_5090,{1U,6U,0U}}, +{ADDQ_5090,{2U,6U,0U}}, +{ADDQ_5090,{3U,6U,0U}}, +{ADDQ_5090,{4U,6U,0U}}, +{ADDQ_5090,{5U,6U,0U}}, +{ADDQ_5090,{6U,6U,0U}}, +{ADDQ_5090,{7U,6U,0U}}, +{ADDQ_5098,{0U,6U,0U}}, +{ADDQ_5098,{1U,6U,0U}}, +{ADDQ_5098,{2U,6U,0U}}, +{ADDQ_5098,{3U,6U,0U}}, +{ADDQ_5098,{4U,6U,0U}}, +{ADDQ_5098,{5U,6U,0U}}, +{ADDQ_5098,{6U,6U,0U}}, +{ADDQ_5098,{7U,6U,0U}}, +{ADDQ_50A0,{0U,6U,0U}}, +{ADDQ_50A0,{1U,6U,0U}}, +{ADDQ_50A0,{2U,6U,0U}}, +{ADDQ_50A0,{3U,6U,0U}}, +{ADDQ_50A0,{4U,6U,0U}}, +{ADDQ_50A0,{5U,6U,0U}}, +{ADDQ_50A0,{6U,6U,0U}}, +{ADDQ_50A0,{7U,6U,0U}}, +{ADDQ_50A8,{0U,6U,0U}}, +{ADDQ_50A8,{1U,6U,0U}}, +{ADDQ_50A8,{2U,6U,0U}}, +{ADDQ_50A8,{3U,6U,0U}}, +{ADDQ_50A8,{4U,6U,0U}}, +{ADDQ_50A8,{5U,6U,0U}}, +{ADDQ_50A8,{6U,6U,0U}}, +{ADDQ_50A8,{7U,6U,0U}}, +{ADDQ_50B0,{0U,6U,0U}}, +{ADDQ_50B0,{1U,6U,0U}}, +{ADDQ_50B0,{2U,6U,0U}}, +{ADDQ_50B0,{3U,6U,0U}}, +{ADDQ_50B0,{4U,6U,0U}}, +{ADDQ_50B0,{5U,6U,0U}}, +{ADDQ_50B0,{6U,6U,0U}}, +{ADDQ_50B0,{7U,6U,0U}}, +{ADDQ_50B8,{0U,6U,0U}}, +{ADDQ_50B9,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,12U,0U}}, +{SCC_50C0,{1U,12U,0U}}, +{SCC_50C0,{2U,12U,0U}}, +{SCC_50C0,{3U,12U,0U}}, +{SCC_50C0,{4U,12U,0U}}, +{SCC_50C0,{5U,12U,0U}}, +{SCC_50C0,{6U,12U,0U}}, +{SCC_50C0,{7U,12U,0U}}, +{DBCC_5CC8,{0U,0U,0U}}, +{DBCC_5CC8,{0U,1U,0U}}, +{DBCC_5CC8,{0U,2U,0U}}, +{DBCC_5CC8,{0U,3U,0U}}, +{DBCC_5CC8,{0U,4U,0U}}, +{DBCC_5CC8,{0U,5U,0U}}, +{DBCC_5CC8,{0U,6U,0U}}, +{DBCC_5CC8,{0U,7U,0U}}, +{SCC_50D0,{0U,12U,0U}}, +{SCC_50D0,{1U,12U,0U}}, +{SCC_50D0,{2U,12U,0U}}, +{SCC_50D0,{3U,12U,0U}}, +{SCC_50D0,{4U,12U,0U}}, +{SCC_50D0,{5U,12U,0U}}, +{SCC_50D0,{6U,12U,0U}}, +{SCC_50D0,{7U,12U,0U}}, +{SCC_50D8,{0U,12U,0U}}, +{SCC_50D8,{1U,12U,0U}}, +{SCC_50D8,{2U,12U,0U}}, +{SCC_50D8,{3U,12U,0U}}, +{SCC_50D8,{4U,12U,0U}}, +{SCC_50D8,{5U,12U,0U}}, +{SCC_50D8,{6U,12U,0U}}, +{SCC_50D8,{7U,12U,0U}}, +{SCC_50E0,{0U,12U,0U}}, +{SCC_50E0,{1U,12U,0U}}, +{SCC_50E0,{2U,12U,0U}}, +{SCC_50E0,{3U,12U,0U}}, +{SCC_50E0,{4U,12U,0U}}, +{SCC_50E0,{5U,12U,0U}}, +{SCC_50E0,{6U,12U,0U}}, +{SCC_50E0,{7U,12U,0U}}, +{SCC_50E8,{0U,12U,0U}}, +{SCC_50E8,{1U,12U,0U}}, +{SCC_50E8,{2U,12U,0U}}, +{SCC_50E8,{3U,12U,0U}}, +{SCC_50E8,{4U,12U,0U}}, +{SCC_50E8,{5U,12U,0U}}, +{SCC_50E8,{6U,12U,0U}}, +{SCC_50E8,{7U,12U,0U}}, +{SCC_50F0,{0U,12U,0U}}, +{SCC_50F0,{1U,12U,0U}}, +{SCC_50F0,{2U,12U,0U}}, +{SCC_50F0,{3U,12U,0U}}, +{SCC_50F0,{4U,12U,0U}}, +{SCC_50F0,{5U,12U,0U}}, +{SCC_50F0,{6U,12U,0U}}, +{SCC_50F0,{7U,12U,0U}}, +{SCC_50F8,{0U,12U,0U}}, +{SCC_50F9,{0U,12U,0U}}, +{TRAPCC_5CFA,{0U,0U,0U}}, +{TRAPCC_5CFB,{0U,0U,0U}}, +{TRAPCC_5CFC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5100,{0U,6U,0U}}, +{SUBQ_5100,{1U,6U,0U}}, +{SUBQ_5100,{2U,6U,0U}}, +{SUBQ_5100,{3U,6U,0U}}, +{SUBQ_5100,{4U,6U,0U}}, +{SUBQ_5100,{5U,6U,0U}}, +{SUBQ_5100,{6U,6U,0U}}, +{SUBQ_5100,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5110,{0U,6U,0U}}, +{SUBQ_5110,{1U,6U,0U}}, +{SUBQ_5110,{2U,6U,0U}}, +{SUBQ_5110,{3U,6U,0U}}, +{SUBQ_5110,{4U,6U,0U}}, +{SUBQ_5110,{5U,6U,0U}}, +{SUBQ_5110,{6U,6U,0U}}, +{SUBQ_5110,{7U,6U,0U}}, +{SUBQ_5118,{0U,6U,0U}}, +{SUBQ_5118,{1U,6U,0U}}, +{SUBQ_5118,{2U,6U,0U}}, +{SUBQ_5118,{3U,6U,0U}}, +{SUBQ_5118,{4U,6U,0U}}, +{SUBQ_5118,{5U,6U,0U}}, +{SUBQ_5118,{6U,6U,0U}}, +{SUBQ_5118,{7U,6U,0U}}, +{SUBQ_5120,{0U,6U,0U}}, +{SUBQ_5120,{1U,6U,0U}}, +{SUBQ_5120,{2U,6U,0U}}, +{SUBQ_5120,{3U,6U,0U}}, +{SUBQ_5120,{4U,6U,0U}}, +{SUBQ_5120,{5U,6U,0U}}, +{SUBQ_5120,{6U,6U,0U}}, +{SUBQ_5120,{7U,6U,0U}}, +{SUBQ_5128,{0U,6U,0U}}, +{SUBQ_5128,{1U,6U,0U}}, +{SUBQ_5128,{2U,6U,0U}}, +{SUBQ_5128,{3U,6U,0U}}, +{SUBQ_5128,{4U,6U,0U}}, +{SUBQ_5128,{5U,6U,0U}}, +{SUBQ_5128,{6U,6U,0U}}, +{SUBQ_5128,{7U,6U,0U}}, +{SUBQ_5130,{0U,6U,0U}}, +{SUBQ_5130,{1U,6U,0U}}, +{SUBQ_5130,{2U,6U,0U}}, +{SUBQ_5130,{3U,6U,0U}}, +{SUBQ_5130,{4U,6U,0U}}, +{SUBQ_5130,{5U,6U,0U}}, +{SUBQ_5130,{6U,6U,0U}}, +{SUBQ_5130,{7U,6U,0U}}, +{SUBQ_5138,{0U,6U,0U}}, +{SUBQ_5139,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5140,{0U,6U,0U}}, +{SUBQ_5140,{1U,6U,0U}}, +{SUBQ_5140,{2U,6U,0U}}, +{SUBQ_5140,{3U,6U,0U}}, +{SUBQ_5140,{4U,6U,0U}}, +{SUBQ_5140,{5U,6U,0U}}, +{SUBQ_5140,{6U,6U,0U}}, +{SUBQ_5140,{7U,6U,0U}}, +{SUBQ_5148,{0U,6U,0U}}, +{SUBQ_5148,{1U,6U,0U}}, +{SUBQ_5148,{2U,6U,0U}}, +{SUBQ_5148,{3U,6U,0U}}, +{SUBQ_5148,{4U,6U,0U}}, +{SUBQ_5148,{5U,6U,0U}}, +{SUBQ_5148,{6U,6U,0U}}, +{SUBQ_5148,{7U,6U,0U}}, +{SUBQ_5150,{0U,6U,0U}}, +{SUBQ_5150,{1U,6U,0U}}, +{SUBQ_5150,{2U,6U,0U}}, +{SUBQ_5150,{3U,6U,0U}}, +{SUBQ_5150,{4U,6U,0U}}, +{SUBQ_5150,{5U,6U,0U}}, +{SUBQ_5150,{6U,6U,0U}}, +{SUBQ_5150,{7U,6U,0U}}, +{SUBQ_5158,{0U,6U,0U}}, +{SUBQ_5158,{1U,6U,0U}}, +{SUBQ_5158,{2U,6U,0U}}, +{SUBQ_5158,{3U,6U,0U}}, +{SUBQ_5158,{4U,6U,0U}}, +{SUBQ_5158,{5U,6U,0U}}, +{SUBQ_5158,{6U,6U,0U}}, +{SUBQ_5158,{7U,6U,0U}}, +{SUBQ_5160,{0U,6U,0U}}, +{SUBQ_5160,{1U,6U,0U}}, +{SUBQ_5160,{2U,6U,0U}}, +{SUBQ_5160,{3U,6U,0U}}, +{SUBQ_5160,{4U,6U,0U}}, +{SUBQ_5160,{5U,6U,0U}}, +{SUBQ_5160,{6U,6U,0U}}, +{SUBQ_5160,{7U,6U,0U}}, +{SUBQ_5168,{0U,6U,0U}}, +{SUBQ_5168,{1U,6U,0U}}, +{SUBQ_5168,{2U,6U,0U}}, +{SUBQ_5168,{3U,6U,0U}}, +{SUBQ_5168,{4U,6U,0U}}, +{SUBQ_5168,{5U,6U,0U}}, +{SUBQ_5168,{6U,6U,0U}}, +{SUBQ_5168,{7U,6U,0U}}, +{SUBQ_5170,{0U,6U,0U}}, +{SUBQ_5170,{1U,6U,0U}}, +{SUBQ_5170,{2U,6U,0U}}, +{SUBQ_5170,{3U,6U,0U}}, +{SUBQ_5170,{4U,6U,0U}}, +{SUBQ_5170,{5U,6U,0U}}, +{SUBQ_5170,{6U,6U,0U}}, +{SUBQ_5170,{7U,6U,0U}}, +{SUBQ_5178,{0U,6U,0U}}, +{SUBQ_5179,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5180,{0U,6U,0U}}, +{SUBQ_5180,{1U,6U,0U}}, +{SUBQ_5180,{2U,6U,0U}}, +{SUBQ_5180,{3U,6U,0U}}, +{SUBQ_5180,{4U,6U,0U}}, +{SUBQ_5180,{5U,6U,0U}}, +{SUBQ_5180,{6U,6U,0U}}, +{SUBQ_5180,{7U,6U,0U}}, +{SUBQ_5188,{0U,6U,0U}}, +{SUBQ_5188,{1U,6U,0U}}, +{SUBQ_5188,{2U,6U,0U}}, +{SUBQ_5188,{3U,6U,0U}}, +{SUBQ_5188,{4U,6U,0U}}, +{SUBQ_5188,{5U,6U,0U}}, +{SUBQ_5188,{6U,6U,0U}}, +{SUBQ_5188,{7U,6U,0U}}, +{SUBQ_5190,{0U,6U,0U}}, +{SUBQ_5190,{1U,6U,0U}}, +{SUBQ_5190,{2U,6U,0U}}, +{SUBQ_5190,{3U,6U,0U}}, +{SUBQ_5190,{4U,6U,0U}}, +{SUBQ_5190,{5U,6U,0U}}, +{SUBQ_5190,{6U,6U,0U}}, +{SUBQ_5190,{7U,6U,0U}}, +{SUBQ_5198,{0U,6U,0U}}, +{SUBQ_5198,{1U,6U,0U}}, +{SUBQ_5198,{2U,6U,0U}}, +{SUBQ_5198,{3U,6U,0U}}, +{SUBQ_5198,{4U,6U,0U}}, +{SUBQ_5198,{5U,6U,0U}}, +{SUBQ_5198,{6U,6U,0U}}, +{SUBQ_5198,{7U,6U,0U}}, +{SUBQ_51A0,{0U,6U,0U}}, +{SUBQ_51A0,{1U,6U,0U}}, +{SUBQ_51A0,{2U,6U,0U}}, +{SUBQ_51A0,{3U,6U,0U}}, +{SUBQ_51A0,{4U,6U,0U}}, +{SUBQ_51A0,{5U,6U,0U}}, +{SUBQ_51A0,{6U,6U,0U}}, +{SUBQ_51A0,{7U,6U,0U}}, +{SUBQ_51A8,{0U,6U,0U}}, +{SUBQ_51A8,{1U,6U,0U}}, +{SUBQ_51A8,{2U,6U,0U}}, +{SUBQ_51A8,{3U,6U,0U}}, +{SUBQ_51A8,{4U,6U,0U}}, +{SUBQ_51A8,{5U,6U,0U}}, +{SUBQ_51A8,{6U,6U,0U}}, +{SUBQ_51A8,{7U,6U,0U}}, +{SUBQ_51B0,{0U,6U,0U}}, +{SUBQ_51B0,{1U,6U,0U}}, +{SUBQ_51B0,{2U,6U,0U}}, +{SUBQ_51B0,{3U,6U,0U}}, +{SUBQ_51B0,{4U,6U,0U}}, +{SUBQ_51B0,{5U,6U,0U}}, +{SUBQ_51B0,{6U,6U,0U}}, +{SUBQ_51B0,{7U,6U,0U}}, +{SUBQ_51B8,{0U,6U,0U}}, +{SUBQ_51B9,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,13U,0U}}, +{SCC_50C0,{1U,13U,0U}}, +{SCC_50C0,{2U,13U,0U}}, +{SCC_50C0,{3U,13U,0U}}, +{SCC_50C0,{4U,13U,0U}}, +{SCC_50C0,{5U,13U,0U}}, +{SCC_50C0,{6U,13U,0U}}, +{SCC_50C0,{7U,13U,0U}}, +{DBCC_5DC8,{0U,0U,0U}}, +{DBCC_5DC8,{0U,1U,0U}}, +{DBCC_5DC8,{0U,2U,0U}}, +{DBCC_5DC8,{0U,3U,0U}}, +{DBCC_5DC8,{0U,4U,0U}}, +{DBCC_5DC8,{0U,5U,0U}}, +{DBCC_5DC8,{0U,6U,0U}}, +{DBCC_5DC8,{0U,7U,0U}}, +{SCC_50D0,{0U,13U,0U}}, +{SCC_50D0,{1U,13U,0U}}, +{SCC_50D0,{2U,13U,0U}}, +{SCC_50D0,{3U,13U,0U}}, +{SCC_50D0,{4U,13U,0U}}, +{SCC_50D0,{5U,13U,0U}}, +{SCC_50D0,{6U,13U,0U}}, +{SCC_50D0,{7U,13U,0U}}, +{SCC_50D8,{0U,13U,0U}}, +{SCC_50D8,{1U,13U,0U}}, +{SCC_50D8,{2U,13U,0U}}, +{SCC_50D8,{3U,13U,0U}}, +{SCC_50D8,{4U,13U,0U}}, +{SCC_50D8,{5U,13U,0U}}, +{SCC_50D8,{6U,13U,0U}}, +{SCC_50D8,{7U,13U,0U}}, +{SCC_50E0,{0U,13U,0U}}, +{SCC_50E0,{1U,13U,0U}}, +{SCC_50E0,{2U,13U,0U}}, +{SCC_50E0,{3U,13U,0U}}, +{SCC_50E0,{4U,13U,0U}}, +{SCC_50E0,{5U,13U,0U}}, +{SCC_50E0,{6U,13U,0U}}, +{SCC_50E0,{7U,13U,0U}}, +{SCC_50E8,{0U,13U,0U}}, +{SCC_50E8,{1U,13U,0U}}, +{SCC_50E8,{2U,13U,0U}}, +{SCC_50E8,{3U,13U,0U}}, +{SCC_50E8,{4U,13U,0U}}, +{SCC_50E8,{5U,13U,0U}}, +{SCC_50E8,{6U,13U,0U}}, +{SCC_50E8,{7U,13U,0U}}, +{SCC_50F0,{0U,13U,0U}}, +{SCC_50F0,{1U,13U,0U}}, +{SCC_50F0,{2U,13U,0U}}, +{SCC_50F0,{3U,13U,0U}}, +{SCC_50F0,{4U,13U,0U}}, +{SCC_50F0,{5U,13U,0U}}, +{SCC_50F0,{6U,13U,0U}}, +{SCC_50F0,{7U,13U,0U}}, +{SCC_50F8,{0U,13U,0U}}, +{SCC_50F9,{0U,13U,0U}}, +{TRAPCC_5DFA,{0U,0U,0U}}, +{TRAPCC_5DFB,{0U,0U,0U}}, +{TRAPCC_5DFC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5000,{0U,7U,0U}}, +{ADDQ_5000,{1U,7U,0U}}, +{ADDQ_5000,{2U,7U,0U}}, +{ADDQ_5000,{3U,7U,0U}}, +{ADDQ_5000,{4U,7U,0U}}, +{ADDQ_5000,{5U,7U,0U}}, +{ADDQ_5000,{6U,7U,0U}}, +{ADDQ_5000,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5010,{0U,7U,0U}}, +{ADDQ_5010,{1U,7U,0U}}, +{ADDQ_5010,{2U,7U,0U}}, +{ADDQ_5010,{3U,7U,0U}}, +{ADDQ_5010,{4U,7U,0U}}, +{ADDQ_5010,{5U,7U,0U}}, +{ADDQ_5010,{6U,7U,0U}}, +{ADDQ_5010,{7U,7U,0U}}, +{ADDQ_5018,{0U,7U,0U}}, +{ADDQ_5018,{1U,7U,0U}}, +{ADDQ_5018,{2U,7U,0U}}, +{ADDQ_5018,{3U,7U,0U}}, +{ADDQ_5018,{4U,7U,0U}}, +{ADDQ_5018,{5U,7U,0U}}, +{ADDQ_5018,{6U,7U,0U}}, +{ADDQ_5018,{7U,7U,0U}}, +{ADDQ_5020,{0U,7U,0U}}, +{ADDQ_5020,{1U,7U,0U}}, +{ADDQ_5020,{2U,7U,0U}}, +{ADDQ_5020,{3U,7U,0U}}, +{ADDQ_5020,{4U,7U,0U}}, +{ADDQ_5020,{5U,7U,0U}}, +{ADDQ_5020,{6U,7U,0U}}, +{ADDQ_5020,{7U,7U,0U}}, +{ADDQ_5028,{0U,7U,0U}}, +{ADDQ_5028,{1U,7U,0U}}, +{ADDQ_5028,{2U,7U,0U}}, +{ADDQ_5028,{3U,7U,0U}}, +{ADDQ_5028,{4U,7U,0U}}, +{ADDQ_5028,{5U,7U,0U}}, +{ADDQ_5028,{6U,7U,0U}}, +{ADDQ_5028,{7U,7U,0U}}, +{ADDQ_5030,{0U,7U,0U}}, +{ADDQ_5030,{1U,7U,0U}}, +{ADDQ_5030,{2U,7U,0U}}, +{ADDQ_5030,{3U,7U,0U}}, +{ADDQ_5030,{4U,7U,0U}}, +{ADDQ_5030,{5U,7U,0U}}, +{ADDQ_5030,{6U,7U,0U}}, +{ADDQ_5030,{7U,7U,0U}}, +{ADDQ_5038,{0U,7U,0U}}, +{ADDQ_5039,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5040,{0U,7U,0U}}, +{ADDQ_5040,{1U,7U,0U}}, +{ADDQ_5040,{2U,7U,0U}}, +{ADDQ_5040,{3U,7U,0U}}, +{ADDQ_5040,{4U,7U,0U}}, +{ADDQ_5040,{5U,7U,0U}}, +{ADDQ_5040,{6U,7U,0U}}, +{ADDQ_5040,{7U,7U,0U}}, +{ADDQ_5048,{0U,7U,0U}}, +{ADDQ_5048,{1U,7U,0U}}, +{ADDQ_5048,{2U,7U,0U}}, +{ADDQ_5048,{3U,7U,0U}}, +{ADDQ_5048,{4U,7U,0U}}, +{ADDQ_5048,{5U,7U,0U}}, +{ADDQ_5048,{6U,7U,0U}}, +{ADDQ_5048,{7U,7U,0U}}, +{ADDQ_5050,{0U,7U,0U}}, +{ADDQ_5050,{1U,7U,0U}}, +{ADDQ_5050,{2U,7U,0U}}, +{ADDQ_5050,{3U,7U,0U}}, +{ADDQ_5050,{4U,7U,0U}}, +{ADDQ_5050,{5U,7U,0U}}, +{ADDQ_5050,{6U,7U,0U}}, +{ADDQ_5050,{7U,7U,0U}}, +{ADDQ_5058,{0U,7U,0U}}, +{ADDQ_5058,{1U,7U,0U}}, +{ADDQ_5058,{2U,7U,0U}}, +{ADDQ_5058,{3U,7U,0U}}, +{ADDQ_5058,{4U,7U,0U}}, +{ADDQ_5058,{5U,7U,0U}}, +{ADDQ_5058,{6U,7U,0U}}, +{ADDQ_5058,{7U,7U,0U}}, +{ADDQ_5060,{0U,7U,0U}}, +{ADDQ_5060,{1U,7U,0U}}, +{ADDQ_5060,{2U,7U,0U}}, +{ADDQ_5060,{3U,7U,0U}}, +{ADDQ_5060,{4U,7U,0U}}, +{ADDQ_5060,{5U,7U,0U}}, +{ADDQ_5060,{6U,7U,0U}}, +{ADDQ_5060,{7U,7U,0U}}, +{ADDQ_5068,{0U,7U,0U}}, +{ADDQ_5068,{1U,7U,0U}}, +{ADDQ_5068,{2U,7U,0U}}, +{ADDQ_5068,{3U,7U,0U}}, +{ADDQ_5068,{4U,7U,0U}}, +{ADDQ_5068,{5U,7U,0U}}, +{ADDQ_5068,{6U,7U,0U}}, +{ADDQ_5068,{7U,7U,0U}}, +{ADDQ_5070,{0U,7U,0U}}, +{ADDQ_5070,{1U,7U,0U}}, +{ADDQ_5070,{2U,7U,0U}}, +{ADDQ_5070,{3U,7U,0U}}, +{ADDQ_5070,{4U,7U,0U}}, +{ADDQ_5070,{5U,7U,0U}}, +{ADDQ_5070,{6U,7U,0U}}, +{ADDQ_5070,{7U,7U,0U}}, +{ADDQ_5078,{0U,7U,0U}}, +{ADDQ_5079,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDQ_5080,{0U,7U,0U}}, +{ADDQ_5080,{1U,7U,0U}}, +{ADDQ_5080,{2U,7U,0U}}, +{ADDQ_5080,{3U,7U,0U}}, +{ADDQ_5080,{4U,7U,0U}}, +{ADDQ_5080,{5U,7U,0U}}, +{ADDQ_5080,{6U,7U,0U}}, +{ADDQ_5080,{7U,7U,0U}}, +{ADDQ_5088,{0U,7U,0U}}, +{ADDQ_5088,{1U,7U,0U}}, +{ADDQ_5088,{2U,7U,0U}}, +{ADDQ_5088,{3U,7U,0U}}, +{ADDQ_5088,{4U,7U,0U}}, +{ADDQ_5088,{5U,7U,0U}}, +{ADDQ_5088,{6U,7U,0U}}, +{ADDQ_5088,{7U,7U,0U}}, +{ADDQ_5090,{0U,7U,0U}}, +{ADDQ_5090,{1U,7U,0U}}, +{ADDQ_5090,{2U,7U,0U}}, +{ADDQ_5090,{3U,7U,0U}}, +{ADDQ_5090,{4U,7U,0U}}, +{ADDQ_5090,{5U,7U,0U}}, +{ADDQ_5090,{6U,7U,0U}}, +{ADDQ_5090,{7U,7U,0U}}, +{ADDQ_5098,{0U,7U,0U}}, +{ADDQ_5098,{1U,7U,0U}}, +{ADDQ_5098,{2U,7U,0U}}, +{ADDQ_5098,{3U,7U,0U}}, +{ADDQ_5098,{4U,7U,0U}}, +{ADDQ_5098,{5U,7U,0U}}, +{ADDQ_5098,{6U,7U,0U}}, +{ADDQ_5098,{7U,7U,0U}}, +{ADDQ_50A0,{0U,7U,0U}}, +{ADDQ_50A0,{1U,7U,0U}}, +{ADDQ_50A0,{2U,7U,0U}}, +{ADDQ_50A0,{3U,7U,0U}}, +{ADDQ_50A0,{4U,7U,0U}}, +{ADDQ_50A0,{5U,7U,0U}}, +{ADDQ_50A0,{6U,7U,0U}}, +{ADDQ_50A0,{7U,7U,0U}}, +{ADDQ_50A8,{0U,7U,0U}}, +{ADDQ_50A8,{1U,7U,0U}}, +{ADDQ_50A8,{2U,7U,0U}}, +{ADDQ_50A8,{3U,7U,0U}}, +{ADDQ_50A8,{4U,7U,0U}}, +{ADDQ_50A8,{5U,7U,0U}}, +{ADDQ_50A8,{6U,7U,0U}}, +{ADDQ_50A8,{7U,7U,0U}}, +{ADDQ_50B0,{0U,7U,0U}}, +{ADDQ_50B0,{1U,7U,0U}}, +{ADDQ_50B0,{2U,7U,0U}}, +{ADDQ_50B0,{3U,7U,0U}}, +{ADDQ_50B0,{4U,7U,0U}}, +{ADDQ_50B0,{5U,7U,0U}}, +{ADDQ_50B0,{6U,7U,0U}}, +{ADDQ_50B0,{7U,7U,0U}}, +{ADDQ_50B8,{0U,7U,0U}}, +{ADDQ_50B9,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,14U,0U}}, +{SCC_50C0,{1U,14U,0U}}, +{SCC_50C0,{2U,14U,0U}}, +{SCC_50C0,{3U,14U,0U}}, +{SCC_50C0,{4U,14U,0U}}, +{SCC_50C0,{5U,14U,0U}}, +{SCC_50C0,{6U,14U,0U}}, +{SCC_50C0,{7U,14U,0U}}, +{DBCC_5EC8,{0U,0U,0U}}, +{DBCC_5EC8,{0U,1U,0U}}, +{DBCC_5EC8,{0U,2U,0U}}, +{DBCC_5EC8,{0U,3U,0U}}, +{DBCC_5EC8,{0U,4U,0U}}, +{DBCC_5EC8,{0U,5U,0U}}, +{DBCC_5EC8,{0U,6U,0U}}, +{DBCC_5EC8,{0U,7U,0U}}, +{SCC_50D0,{0U,14U,0U}}, +{SCC_50D0,{1U,14U,0U}}, +{SCC_50D0,{2U,14U,0U}}, +{SCC_50D0,{3U,14U,0U}}, +{SCC_50D0,{4U,14U,0U}}, +{SCC_50D0,{5U,14U,0U}}, +{SCC_50D0,{6U,14U,0U}}, +{SCC_50D0,{7U,14U,0U}}, +{SCC_50D8,{0U,14U,0U}}, +{SCC_50D8,{1U,14U,0U}}, +{SCC_50D8,{2U,14U,0U}}, +{SCC_50D8,{3U,14U,0U}}, +{SCC_50D8,{4U,14U,0U}}, +{SCC_50D8,{5U,14U,0U}}, +{SCC_50D8,{6U,14U,0U}}, +{SCC_50D8,{7U,14U,0U}}, +{SCC_50E0,{0U,14U,0U}}, +{SCC_50E0,{1U,14U,0U}}, +{SCC_50E0,{2U,14U,0U}}, +{SCC_50E0,{3U,14U,0U}}, +{SCC_50E0,{4U,14U,0U}}, +{SCC_50E0,{5U,14U,0U}}, +{SCC_50E0,{6U,14U,0U}}, +{SCC_50E0,{7U,14U,0U}}, +{SCC_50E8,{0U,14U,0U}}, +{SCC_50E8,{1U,14U,0U}}, +{SCC_50E8,{2U,14U,0U}}, +{SCC_50E8,{3U,14U,0U}}, +{SCC_50E8,{4U,14U,0U}}, +{SCC_50E8,{5U,14U,0U}}, +{SCC_50E8,{6U,14U,0U}}, +{SCC_50E8,{7U,14U,0U}}, +{SCC_50F0,{0U,14U,0U}}, +{SCC_50F0,{1U,14U,0U}}, +{SCC_50F0,{2U,14U,0U}}, +{SCC_50F0,{3U,14U,0U}}, +{SCC_50F0,{4U,14U,0U}}, +{SCC_50F0,{5U,14U,0U}}, +{SCC_50F0,{6U,14U,0U}}, +{SCC_50F0,{7U,14U,0U}}, +{SCC_50F8,{0U,14U,0U}}, +{SCC_50F9,{0U,14U,0U}}, +{TRAPCC_5EFA,{0U,0U,0U}}, +{TRAPCC_5EFB,{0U,0U,0U}}, +{TRAPCC_5EFC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5100,{0U,7U,0U}}, +{SUBQ_5100,{1U,7U,0U}}, +{SUBQ_5100,{2U,7U,0U}}, +{SUBQ_5100,{3U,7U,0U}}, +{SUBQ_5100,{4U,7U,0U}}, +{SUBQ_5100,{5U,7U,0U}}, +{SUBQ_5100,{6U,7U,0U}}, +{SUBQ_5100,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5110,{0U,7U,0U}}, +{SUBQ_5110,{1U,7U,0U}}, +{SUBQ_5110,{2U,7U,0U}}, +{SUBQ_5110,{3U,7U,0U}}, +{SUBQ_5110,{4U,7U,0U}}, +{SUBQ_5110,{5U,7U,0U}}, +{SUBQ_5110,{6U,7U,0U}}, +{SUBQ_5110,{7U,7U,0U}}, +{SUBQ_5118,{0U,7U,0U}}, +{SUBQ_5118,{1U,7U,0U}}, +{SUBQ_5118,{2U,7U,0U}}, +{SUBQ_5118,{3U,7U,0U}}, +{SUBQ_5118,{4U,7U,0U}}, +{SUBQ_5118,{5U,7U,0U}}, +{SUBQ_5118,{6U,7U,0U}}, +{SUBQ_5118,{7U,7U,0U}}, +{SUBQ_5120,{0U,7U,0U}}, +{SUBQ_5120,{1U,7U,0U}}, +{SUBQ_5120,{2U,7U,0U}}, +{SUBQ_5120,{3U,7U,0U}}, +{SUBQ_5120,{4U,7U,0U}}, +{SUBQ_5120,{5U,7U,0U}}, +{SUBQ_5120,{6U,7U,0U}}, +{SUBQ_5120,{7U,7U,0U}}, +{SUBQ_5128,{0U,7U,0U}}, +{SUBQ_5128,{1U,7U,0U}}, +{SUBQ_5128,{2U,7U,0U}}, +{SUBQ_5128,{3U,7U,0U}}, +{SUBQ_5128,{4U,7U,0U}}, +{SUBQ_5128,{5U,7U,0U}}, +{SUBQ_5128,{6U,7U,0U}}, +{SUBQ_5128,{7U,7U,0U}}, +{SUBQ_5130,{0U,7U,0U}}, +{SUBQ_5130,{1U,7U,0U}}, +{SUBQ_5130,{2U,7U,0U}}, +{SUBQ_5130,{3U,7U,0U}}, +{SUBQ_5130,{4U,7U,0U}}, +{SUBQ_5130,{5U,7U,0U}}, +{SUBQ_5130,{6U,7U,0U}}, +{SUBQ_5130,{7U,7U,0U}}, +{SUBQ_5138,{0U,7U,0U}}, +{SUBQ_5139,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5140,{0U,7U,0U}}, +{SUBQ_5140,{1U,7U,0U}}, +{SUBQ_5140,{2U,7U,0U}}, +{SUBQ_5140,{3U,7U,0U}}, +{SUBQ_5140,{4U,7U,0U}}, +{SUBQ_5140,{5U,7U,0U}}, +{SUBQ_5140,{6U,7U,0U}}, +{SUBQ_5140,{7U,7U,0U}}, +{SUBQ_5148,{0U,7U,0U}}, +{SUBQ_5148,{1U,7U,0U}}, +{SUBQ_5148,{2U,7U,0U}}, +{SUBQ_5148,{3U,7U,0U}}, +{SUBQ_5148,{4U,7U,0U}}, +{SUBQ_5148,{5U,7U,0U}}, +{SUBQ_5148,{6U,7U,0U}}, +{SUBQ_5148,{7U,7U,0U}}, +{SUBQ_5150,{0U,7U,0U}}, +{SUBQ_5150,{1U,7U,0U}}, +{SUBQ_5150,{2U,7U,0U}}, +{SUBQ_5150,{3U,7U,0U}}, +{SUBQ_5150,{4U,7U,0U}}, +{SUBQ_5150,{5U,7U,0U}}, +{SUBQ_5150,{6U,7U,0U}}, +{SUBQ_5150,{7U,7U,0U}}, +{SUBQ_5158,{0U,7U,0U}}, +{SUBQ_5158,{1U,7U,0U}}, +{SUBQ_5158,{2U,7U,0U}}, +{SUBQ_5158,{3U,7U,0U}}, +{SUBQ_5158,{4U,7U,0U}}, +{SUBQ_5158,{5U,7U,0U}}, +{SUBQ_5158,{6U,7U,0U}}, +{SUBQ_5158,{7U,7U,0U}}, +{SUBQ_5160,{0U,7U,0U}}, +{SUBQ_5160,{1U,7U,0U}}, +{SUBQ_5160,{2U,7U,0U}}, +{SUBQ_5160,{3U,7U,0U}}, +{SUBQ_5160,{4U,7U,0U}}, +{SUBQ_5160,{5U,7U,0U}}, +{SUBQ_5160,{6U,7U,0U}}, +{SUBQ_5160,{7U,7U,0U}}, +{SUBQ_5168,{0U,7U,0U}}, +{SUBQ_5168,{1U,7U,0U}}, +{SUBQ_5168,{2U,7U,0U}}, +{SUBQ_5168,{3U,7U,0U}}, +{SUBQ_5168,{4U,7U,0U}}, +{SUBQ_5168,{5U,7U,0U}}, +{SUBQ_5168,{6U,7U,0U}}, +{SUBQ_5168,{7U,7U,0U}}, +{SUBQ_5170,{0U,7U,0U}}, +{SUBQ_5170,{1U,7U,0U}}, +{SUBQ_5170,{2U,7U,0U}}, +{SUBQ_5170,{3U,7U,0U}}, +{SUBQ_5170,{4U,7U,0U}}, +{SUBQ_5170,{5U,7U,0U}}, +{SUBQ_5170,{6U,7U,0U}}, +{SUBQ_5170,{7U,7U,0U}}, +{SUBQ_5178,{0U,7U,0U}}, +{SUBQ_5179,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBQ_5180,{0U,7U,0U}}, +{SUBQ_5180,{1U,7U,0U}}, +{SUBQ_5180,{2U,7U,0U}}, +{SUBQ_5180,{3U,7U,0U}}, +{SUBQ_5180,{4U,7U,0U}}, +{SUBQ_5180,{5U,7U,0U}}, +{SUBQ_5180,{6U,7U,0U}}, +{SUBQ_5180,{7U,7U,0U}}, +{SUBQ_5188,{0U,7U,0U}}, +{SUBQ_5188,{1U,7U,0U}}, +{SUBQ_5188,{2U,7U,0U}}, +{SUBQ_5188,{3U,7U,0U}}, +{SUBQ_5188,{4U,7U,0U}}, +{SUBQ_5188,{5U,7U,0U}}, +{SUBQ_5188,{6U,7U,0U}}, +{SUBQ_5188,{7U,7U,0U}}, +{SUBQ_5190,{0U,7U,0U}}, +{SUBQ_5190,{1U,7U,0U}}, +{SUBQ_5190,{2U,7U,0U}}, +{SUBQ_5190,{3U,7U,0U}}, +{SUBQ_5190,{4U,7U,0U}}, +{SUBQ_5190,{5U,7U,0U}}, +{SUBQ_5190,{6U,7U,0U}}, +{SUBQ_5190,{7U,7U,0U}}, +{SUBQ_5198,{0U,7U,0U}}, +{SUBQ_5198,{1U,7U,0U}}, +{SUBQ_5198,{2U,7U,0U}}, +{SUBQ_5198,{3U,7U,0U}}, +{SUBQ_5198,{4U,7U,0U}}, +{SUBQ_5198,{5U,7U,0U}}, +{SUBQ_5198,{6U,7U,0U}}, +{SUBQ_5198,{7U,7U,0U}}, +{SUBQ_51A0,{0U,7U,0U}}, +{SUBQ_51A0,{1U,7U,0U}}, +{SUBQ_51A0,{2U,7U,0U}}, +{SUBQ_51A0,{3U,7U,0U}}, +{SUBQ_51A0,{4U,7U,0U}}, +{SUBQ_51A0,{5U,7U,0U}}, +{SUBQ_51A0,{6U,7U,0U}}, +{SUBQ_51A0,{7U,7U,0U}}, +{SUBQ_51A8,{0U,7U,0U}}, +{SUBQ_51A8,{1U,7U,0U}}, +{SUBQ_51A8,{2U,7U,0U}}, +{SUBQ_51A8,{3U,7U,0U}}, +{SUBQ_51A8,{4U,7U,0U}}, +{SUBQ_51A8,{5U,7U,0U}}, +{SUBQ_51A8,{6U,7U,0U}}, +{SUBQ_51A8,{7U,7U,0U}}, +{SUBQ_51B0,{0U,7U,0U}}, +{SUBQ_51B0,{1U,7U,0U}}, +{SUBQ_51B0,{2U,7U,0U}}, +{SUBQ_51B0,{3U,7U,0U}}, +{SUBQ_51B0,{4U,7U,0U}}, +{SUBQ_51B0,{5U,7U,0U}}, +{SUBQ_51B0,{6U,7U,0U}}, +{SUBQ_51B0,{7U,7U,0U}}, +{SUBQ_51B8,{0U,7U,0U}}, +{SUBQ_51B9,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SCC_50C0,{0U,15U,0U}}, +{SCC_50C0,{1U,15U,0U}}, +{SCC_50C0,{2U,15U,0U}}, +{SCC_50C0,{3U,15U,0U}}, +{SCC_50C0,{4U,15U,0U}}, +{SCC_50C0,{5U,15U,0U}}, +{SCC_50C0,{6U,15U,0U}}, +{SCC_50C0,{7U,15U,0U}}, +{DBCC_5FC8,{0U,0U,0U}}, +{DBCC_5FC8,{0U,1U,0U}}, +{DBCC_5FC8,{0U,2U,0U}}, +{DBCC_5FC8,{0U,3U,0U}}, +{DBCC_5FC8,{0U,4U,0U}}, +{DBCC_5FC8,{0U,5U,0U}}, +{DBCC_5FC8,{0U,6U,0U}}, +{DBCC_5FC8,{0U,7U,0U}}, +{SCC_50D0,{0U,15U,0U}}, +{SCC_50D0,{1U,15U,0U}}, +{SCC_50D0,{2U,15U,0U}}, +{SCC_50D0,{3U,15U,0U}}, +{SCC_50D0,{4U,15U,0U}}, +{SCC_50D0,{5U,15U,0U}}, +{SCC_50D0,{6U,15U,0U}}, +{SCC_50D0,{7U,15U,0U}}, +{SCC_50D8,{0U,15U,0U}}, +{SCC_50D8,{1U,15U,0U}}, +{SCC_50D8,{2U,15U,0U}}, +{SCC_50D8,{3U,15U,0U}}, +{SCC_50D8,{4U,15U,0U}}, +{SCC_50D8,{5U,15U,0U}}, +{SCC_50D8,{6U,15U,0U}}, +{SCC_50D8,{7U,15U,0U}}, +{SCC_50E0,{0U,15U,0U}}, +{SCC_50E0,{1U,15U,0U}}, +{SCC_50E0,{2U,15U,0U}}, +{SCC_50E0,{3U,15U,0U}}, +{SCC_50E0,{4U,15U,0U}}, +{SCC_50E0,{5U,15U,0U}}, +{SCC_50E0,{6U,15U,0U}}, +{SCC_50E0,{7U,15U,0U}}, +{SCC_50E8,{0U,15U,0U}}, +{SCC_50E8,{1U,15U,0U}}, +{SCC_50E8,{2U,15U,0U}}, +{SCC_50E8,{3U,15U,0U}}, +{SCC_50E8,{4U,15U,0U}}, +{SCC_50E8,{5U,15U,0U}}, +{SCC_50E8,{6U,15U,0U}}, +{SCC_50E8,{7U,15U,0U}}, +{SCC_50F0,{0U,15U,0U}}, +{SCC_50F0,{1U,15U,0U}}, +{SCC_50F0,{2U,15U,0U}}, +{SCC_50F0,{3U,15U,0U}}, +{SCC_50F0,{4U,15U,0U}}, +{SCC_50F0,{5U,15U,0U}}, +{SCC_50F0,{6U,15U,0U}}, +{SCC_50F0,{7U,15U,0U}}, +{SCC_50F8,{0U,15U,0U}}, +{SCC_50F9,{0U,15U,0U}}, +{TRAPCC_5FFA,{0U,0U,0U}}, +{TRAPCC_5FFB,{0U,0U,0U}}, +{TRAPCC_5FFC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BRAW_6000,{0U,0U,0U}}, +{BRAB_6000,{0U,1U,0U}}, +{BRAB_6000,{0U,2U,0U}}, +{BRAB_6000,{0U,3U,0U}}, +{BRAB_6000,{0U,4U,0U}}, +{BRAB_6000,{0U,5U,0U}}, +{BRAB_6000,{0U,6U,0U}}, +{BRAB_6000,{0U,7U,0U}}, +{BRAB_6000,{0U,8U,0U}}, +{BRAB_6000,{0U,9U,0U}}, +{BRAB_6000,{0U,10U,0U}}, +{BRAB_6000,{0U,11U,0U}}, +{BRAB_6000,{0U,12U,0U}}, +{BRAB_6000,{0U,13U,0U}}, +{BRAB_6000,{0U,14U,0U}}, +{BRAB_6000,{0U,15U,0U}}, +{BRAB_6000,{0U,16U,0U}}, +{BRAB_6000,{0U,17U,0U}}, +{BRAB_6000,{0U,18U,0U}}, +{BRAB_6000,{0U,19U,0U}}, +{BRAB_6000,{0U,20U,0U}}, +{BRAB_6000,{0U,21U,0U}}, +{BRAB_6000,{0U,22U,0U}}, +{BRAB_6000,{0U,23U,0U}}, +{BRAB_6000,{0U,24U,0U}}, +{BRAB_6000,{0U,25U,0U}}, +{BRAB_6000,{0U,26U,0U}}, +{BRAB_6000,{0U,27U,0U}}, +{BRAB_6000,{0U,28U,0U}}, +{BRAB_6000,{0U,29U,0U}}, +{BRAB_6000,{0U,30U,0U}}, +{BRAB_6000,{0U,31U,0U}}, +{BRAB_6000,{0U,32U,0U}}, +{BRAB_6000,{0U,33U,0U}}, +{BRAB_6000,{0U,34U,0U}}, +{BRAB_6000,{0U,35U,0U}}, +{BRAB_6000,{0U,36U,0U}}, +{BRAB_6000,{0U,37U,0U}}, +{BRAB_6000,{0U,38U,0U}}, +{BRAB_6000,{0U,39U,0U}}, +{BRAB_6000,{0U,40U,0U}}, +{BRAB_6000,{0U,41U,0U}}, +{BRAB_6000,{0U,42U,0U}}, +{BRAB_6000,{0U,43U,0U}}, +{BRAB_6000,{0U,44U,0U}}, +{BRAB_6000,{0U,45U,0U}}, +{BRAB_6000,{0U,46U,0U}}, +{BRAB_6000,{0U,47U,0U}}, +{BRAB_6000,{0U,48U,0U}}, +{BRAB_6000,{0U,49U,0U}}, +{BRAB_6000,{0U,50U,0U}}, +{BRAB_6000,{0U,51U,0U}}, +{BRAB_6000,{0U,52U,0U}}, +{BRAB_6000,{0U,53U,0U}}, +{BRAB_6000,{0U,54U,0U}}, +{BRAB_6000,{0U,55U,0U}}, +{BRAB_6000,{0U,56U,0U}}, +{BRAB_6000,{0U,57U,0U}}, +{BRAB_6000,{0U,58U,0U}}, +{BRAB_6000,{0U,59U,0U}}, +{BRAB_6000,{0U,60U,0U}}, +{BRAB_6000,{0U,61U,0U}}, +{BRAB_6000,{0U,62U,0U}}, +{BRAB_6000,{0U,63U,0U}}, +{BRAB_6000,{0U,64U,0U}}, +{BRAB_6000,{0U,65U,0U}}, +{BRAB_6000,{0U,66U,0U}}, +{BRAB_6000,{0U,67U,0U}}, +{BRAB_6000,{0U,68U,0U}}, +{BRAB_6000,{0U,69U,0U}}, +{BRAB_6000,{0U,70U,0U}}, +{BRAB_6000,{0U,71U,0U}}, +{BRAB_6000,{0U,72U,0U}}, +{BRAB_6000,{0U,73U,0U}}, +{BRAB_6000,{0U,74U,0U}}, +{BRAB_6000,{0U,75U,0U}}, +{BRAB_6000,{0U,76U,0U}}, +{BRAB_6000,{0U,77U,0U}}, +{BRAB_6000,{0U,78U,0U}}, +{BRAB_6000,{0U,79U,0U}}, +{BRAB_6000,{0U,80U,0U}}, +{BRAB_6000,{0U,81U,0U}}, +{BRAB_6000,{0U,82U,0U}}, +{BRAB_6000,{0U,83U,0U}}, +{BRAB_6000,{0U,84U,0U}}, +{BRAB_6000,{0U,85U,0U}}, +{BRAB_6000,{0U,86U,0U}}, +{BRAB_6000,{0U,87U,0U}}, +{BRAB_6000,{0U,88U,0U}}, +{BRAB_6000,{0U,89U,0U}}, +{BRAB_6000,{0U,90U,0U}}, +{BRAB_6000,{0U,91U,0U}}, +{BRAB_6000,{0U,92U,0U}}, +{BRAB_6000,{0U,93U,0U}}, +{BRAB_6000,{0U,94U,0U}}, +{BRAB_6000,{0U,95U,0U}}, +{BRAB_6000,{0U,96U,0U}}, +{BRAB_6000,{0U,97U,0U}}, +{BRAB_6000,{0U,98U,0U}}, +{BRAB_6000,{0U,99U,0U}}, +{BRAB_6000,{0U,100U,0U}}, +{BRAB_6000,{0U,101U,0U}}, +{BRAB_6000,{0U,102U,0U}}, +{BRAB_6000,{0U,103U,0U}}, +{BRAB_6000,{0U,104U,0U}}, +{BRAB_6000,{0U,105U,0U}}, +{BRAB_6000,{0U,106U,0U}}, +{BRAB_6000,{0U,107U,0U}}, +{BRAB_6000,{0U,108U,0U}}, +{BRAB_6000,{0U,109U,0U}}, +{BRAB_6000,{0U,110U,0U}}, +{BRAB_6000,{0U,111U,0U}}, +{BRAB_6000,{0U,112U,0U}}, +{BRAB_6000,{0U,113U,0U}}, +{BRAB_6000,{0U,114U,0U}}, +{BRAB_6000,{0U,115U,0U}}, +{BRAB_6000,{0U,116U,0U}}, +{BRAB_6000,{0U,117U,0U}}, +{BRAB_6000,{0U,118U,0U}}, +{BRAB_6000,{0U,119U,0U}}, +{BRAB_6000,{0U,120U,0U}}, +{BRAB_6000,{0U,121U,0U}}, +{BRAB_6000,{0U,122U,0U}}, +{BRAB_6000,{0U,123U,0U}}, +{BRAB_6000,{0U,124U,0U}}, +{BRAB_6000,{0U,125U,0U}}, +{BRAB_6000,{0U,126U,0U}}, +{BRAB_6000,{0U,127U,0U}}, +{BRAB_6000,{0U,4294967168U,0U}}, +{BRAB_6000,{0U,4294967169U,0U}}, +{BRAB_6000,{0U,4294967170U,0U}}, +{BRAB_6000,{0U,4294967171U,0U}}, +{BRAB_6000,{0U,4294967172U,0U}}, +{BRAB_6000,{0U,4294967173U,0U}}, +{BRAB_6000,{0U,4294967174U,0U}}, +{BRAB_6000,{0U,4294967175U,0U}}, +{BRAB_6000,{0U,4294967176U,0U}}, +{BRAB_6000,{0U,4294967177U,0U}}, +{BRAB_6000,{0U,4294967178U,0U}}, +{BRAB_6000,{0U,4294967179U,0U}}, +{BRAB_6000,{0U,4294967180U,0U}}, +{BRAB_6000,{0U,4294967181U,0U}}, +{BRAB_6000,{0U,4294967182U,0U}}, +{BRAB_6000,{0U,4294967183U,0U}}, +{BRAB_6000,{0U,4294967184U,0U}}, +{BRAB_6000,{0U,4294967185U,0U}}, +{BRAB_6000,{0U,4294967186U,0U}}, +{BRAB_6000,{0U,4294967187U,0U}}, +{BRAB_6000,{0U,4294967188U,0U}}, +{BRAB_6000,{0U,4294967189U,0U}}, +{BRAB_6000,{0U,4294967190U,0U}}, +{BRAB_6000,{0U,4294967191U,0U}}, +{BRAB_6000,{0U,4294967192U,0U}}, +{BRAB_6000,{0U,4294967193U,0U}}, +{BRAB_6000,{0U,4294967194U,0U}}, +{BRAB_6000,{0U,4294967195U,0U}}, +{BRAB_6000,{0U,4294967196U,0U}}, +{BRAB_6000,{0U,4294967197U,0U}}, +{BRAB_6000,{0U,4294967198U,0U}}, +{BRAB_6000,{0U,4294967199U,0U}}, +{BRAB_6000,{0U,4294967200U,0U}}, +{BRAB_6000,{0U,4294967201U,0U}}, +{BRAB_6000,{0U,4294967202U,0U}}, +{BRAB_6000,{0U,4294967203U,0U}}, +{BRAB_6000,{0U,4294967204U,0U}}, +{BRAB_6000,{0U,4294967205U,0U}}, +{BRAB_6000,{0U,4294967206U,0U}}, +{BRAB_6000,{0U,4294967207U,0U}}, +{BRAB_6000,{0U,4294967208U,0U}}, +{BRAB_6000,{0U,4294967209U,0U}}, +{BRAB_6000,{0U,4294967210U,0U}}, +{BRAB_6000,{0U,4294967211U,0U}}, +{BRAB_6000,{0U,4294967212U,0U}}, +{BRAB_6000,{0U,4294967213U,0U}}, +{BRAB_6000,{0U,4294967214U,0U}}, +{BRAB_6000,{0U,4294967215U,0U}}, +{BRAB_6000,{0U,4294967216U,0U}}, +{BRAB_6000,{0U,4294967217U,0U}}, +{BRAB_6000,{0U,4294967218U,0U}}, +{BRAB_6000,{0U,4294967219U,0U}}, +{BRAB_6000,{0U,4294967220U,0U}}, +{BRAB_6000,{0U,4294967221U,0U}}, +{BRAB_6000,{0U,4294967222U,0U}}, +{BRAB_6000,{0U,4294967223U,0U}}, +{BRAB_6000,{0U,4294967224U,0U}}, +{BRAB_6000,{0U,4294967225U,0U}}, +{BRAB_6000,{0U,4294967226U,0U}}, +{BRAB_6000,{0U,4294967227U,0U}}, +{BRAB_6000,{0U,4294967228U,0U}}, +{BRAB_6000,{0U,4294967229U,0U}}, +{BRAB_6000,{0U,4294967230U,0U}}, +{BRAB_6000,{0U,4294967231U,0U}}, +{BRAB_6000,{0U,4294967232U,0U}}, +{BRAB_6000,{0U,4294967233U,0U}}, +{BRAB_6000,{0U,4294967234U,0U}}, +{BRAB_6000,{0U,4294967235U,0U}}, +{BRAB_6000,{0U,4294967236U,0U}}, +{BRAB_6000,{0U,4294967237U,0U}}, +{BRAB_6000,{0U,4294967238U,0U}}, +{BRAB_6000,{0U,4294967239U,0U}}, +{BRAB_6000,{0U,4294967240U,0U}}, +{BRAB_6000,{0U,4294967241U,0U}}, +{BRAB_6000,{0U,4294967242U,0U}}, +{BRAB_6000,{0U,4294967243U,0U}}, +{BRAB_6000,{0U,4294967244U,0U}}, +{BRAB_6000,{0U,4294967245U,0U}}, +{BRAB_6000,{0U,4294967246U,0U}}, +{BRAB_6000,{0U,4294967247U,0U}}, +{BRAB_6000,{0U,4294967248U,0U}}, +{BRAB_6000,{0U,4294967249U,0U}}, +{BRAB_6000,{0U,4294967250U,0U}}, +{BRAB_6000,{0U,4294967251U,0U}}, +{BRAB_6000,{0U,4294967252U,0U}}, +{BRAB_6000,{0U,4294967253U,0U}}, +{BRAB_6000,{0U,4294967254U,0U}}, +{BRAB_6000,{0U,4294967255U,0U}}, +{BRAB_6000,{0U,4294967256U,0U}}, +{BRAB_6000,{0U,4294967257U,0U}}, +{BRAB_6000,{0U,4294967258U,0U}}, +{BRAB_6000,{0U,4294967259U,0U}}, +{BRAB_6000,{0U,4294967260U,0U}}, +{BRAB_6000,{0U,4294967261U,0U}}, +{BRAB_6000,{0U,4294967262U,0U}}, +{BRAB_6000,{0U,4294967263U,0U}}, +{BRAB_6000,{0U,4294967264U,0U}}, +{BRAB_6000,{0U,4294967265U,0U}}, +{BRAB_6000,{0U,4294967266U,0U}}, +{BRAB_6000,{0U,4294967267U,0U}}, +{BRAB_6000,{0U,4294967268U,0U}}, +{BRAB_6000,{0U,4294967269U,0U}}, +{BRAB_6000,{0U,4294967270U,0U}}, +{BRAB_6000,{0U,4294967271U,0U}}, +{BRAB_6000,{0U,4294967272U,0U}}, +{BRAB_6000,{0U,4294967273U,0U}}, +{BRAB_6000,{0U,4294967274U,0U}}, +{BRAB_6000,{0U,4294967275U,0U}}, +{BRAB_6000,{0U,4294967276U,0U}}, +{BRAB_6000,{0U,4294967277U,0U}}, +{BRAB_6000,{0U,4294967278U,0U}}, +{BRAB_6000,{0U,4294967279U,0U}}, +{BRAB_6000,{0U,4294967280U,0U}}, +{BRAB_6000,{0U,4294967281U,0U}}, +{BRAB_6000,{0U,4294967282U,0U}}, +{BRAB_6000,{0U,4294967283U,0U}}, +{BRAB_6000,{0U,4294967284U,0U}}, +{BRAB_6000,{0U,4294967285U,0U}}, +{BRAB_6000,{0U,4294967286U,0U}}, +{BRAB_6000,{0U,4294967287U,0U}}, +{BRAB_6000,{0U,4294967288U,0U}}, +{BRAB_6000,{0U,4294967289U,0U}}, +{BRAB_6000,{0U,4294967290U,0U}}, +{BRAB_6000,{0U,4294967291U,0U}}, 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+{BCCB_6F00,{0U,107U,0U}}, +{BCCB_6F00,{0U,108U,0U}}, +{BCCB_6F00,{0U,109U,0U}}, +{BCCB_6F00,{0U,110U,0U}}, +{BCCB_6F00,{0U,111U,0U}}, +{BCCB_6F00,{0U,112U,0U}}, +{BCCB_6F00,{0U,113U,0U}}, +{BCCB_6F00,{0U,114U,0U}}, +{BCCB_6F00,{0U,115U,0U}}, +{BCCB_6F00,{0U,116U,0U}}, +{BCCB_6F00,{0U,117U,0U}}, +{BCCB_6F00,{0U,118U,0U}}, +{BCCB_6F00,{0U,119U,0U}}, +{BCCB_6F00,{0U,120U,0U}}, +{BCCB_6F00,{0U,121U,0U}}, +{BCCB_6F00,{0U,122U,0U}}, +{BCCB_6F00,{0U,123U,0U}}, +{BCCB_6F00,{0U,124U,0U}}, +{BCCB_6F00,{0U,125U,0U}}, +{BCCB_6F00,{0U,126U,0U}}, +{BCCB_6F00,{0U,127U,0U}}, +{BCCB_6F00,{0U,4294967168U,0U}}, +{BCCB_6F00,{0U,4294967169U,0U}}, +{BCCB_6F00,{0U,4294967170U,0U}}, +{BCCB_6F00,{0U,4294967171U,0U}}, +{BCCB_6F00,{0U,4294967172U,0U}}, +{BCCB_6F00,{0U,4294967173U,0U}}, +{BCCB_6F00,{0U,4294967174U,0U}}, +{BCCB_6F00,{0U,4294967175U,0U}}, +{BCCB_6F00,{0U,4294967176U,0U}}, +{BCCB_6F00,{0U,4294967177U,0U}}, +{BCCB_6F00,{0U,4294967178U,0U}}, +{BCCB_6F00,{0U,4294967179U,0U}}, +{BCCB_6F00,{0U,4294967180U,0U}}, +{BCCB_6F00,{0U,4294967181U,0U}}, +{BCCB_6F00,{0U,4294967182U,0U}}, +{BCCB_6F00,{0U,4294967183U,0U}}, +{BCCB_6F00,{0U,4294967184U,0U}}, +{BCCB_6F00,{0U,4294967185U,0U}}, +{BCCB_6F00,{0U,4294967186U,0U}}, +{BCCB_6F00,{0U,4294967187U,0U}}, +{BCCB_6F00,{0U,4294967188U,0U}}, +{BCCB_6F00,{0U,4294967189U,0U}}, +{BCCB_6F00,{0U,4294967190U,0U}}, +{BCCB_6F00,{0U,4294967191U,0U}}, +{BCCB_6F00,{0U,4294967192U,0U}}, +{BCCB_6F00,{0U,4294967193U,0U}}, +{BCCB_6F00,{0U,4294967194U,0U}}, +{BCCB_6F00,{0U,4294967195U,0U}}, +{BCCB_6F00,{0U,4294967196U,0U}}, +{BCCB_6F00,{0U,4294967197U,0U}}, +{BCCB_6F00,{0U,4294967198U,0U}}, +{BCCB_6F00,{0U,4294967199U,0U}}, +{BCCB_6F00,{0U,4294967200U,0U}}, +{BCCB_6F00,{0U,4294967201U,0U}}, +{BCCB_6F00,{0U,4294967202U,0U}}, +{BCCB_6F00,{0U,4294967203U,0U}}, +{BCCB_6F00,{0U,4294967204U,0U}}, +{BCCB_6F00,{0U,4294967205U,0U}}, +{BCCB_6F00,{0U,4294967206U,0U}}, +{BCCB_6F00,{0U,4294967207U,0U}}, +{BCCB_6F00,{0U,4294967208U,0U}}, +{BCCB_6F00,{0U,4294967209U,0U}}, +{BCCB_6F00,{0U,4294967210U,0U}}, +{BCCB_6F00,{0U,4294967211U,0U}}, +{BCCB_6F00,{0U,4294967212U,0U}}, +{BCCB_6F00,{0U,4294967213U,0U}}, +{BCCB_6F00,{0U,4294967214U,0U}}, +{BCCB_6F00,{0U,4294967215U,0U}}, +{BCCB_6F00,{0U,4294967216U,0U}}, +{BCCB_6F00,{0U,4294967217U,0U}}, +{BCCB_6F00,{0U,4294967218U,0U}}, +{BCCB_6F00,{0U,4294967219U,0U}}, +{BCCB_6F00,{0U,4294967220U,0U}}, +{BCCB_6F00,{0U,4294967221U,0U}}, +{BCCB_6F00,{0U,4294967222U,0U}}, +{BCCB_6F00,{0U,4294967223U,0U}}, +{BCCB_6F00,{0U,4294967224U,0U}}, +{BCCB_6F00,{0U,4294967225U,0U}}, +{BCCB_6F00,{0U,4294967226U,0U}}, +{BCCB_6F00,{0U,4294967227U,0U}}, +{BCCB_6F00,{0U,4294967228U,0U}}, +{BCCB_6F00,{0U,4294967229U,0U}}, +{BCCB_6F00,{0U,4294967230U,0U}}, +{BCCB_6F00,{0U,4294967231U,0U}}, +{BCCB_6F00,{0U,4294967232U,0U}}, +{BCCB_6F00,{0U,4294967233U,0U}}, +{BCCB_6F00,{0U,4294967234U,0U}}, +{BCCB_6F00,{0U,4294967235U,0U}}, +{BCCB_6F00,{0U,4294967236U,0U}}, +{BCCB_6F00,{0U,4294967237U,0U}}, +{BCCB_6F00,{0U,4294967238U,0U}}, +{BCCB_6F00,{0U,4294967239U,0U}}, +{BCCB_6F00,{0U,4294967240U,0U}}, +{BCCB_6F00,{0U,4294967241U,0U}}, +{BCCB_6F00,{0U,4294967242U,0U}}, +{BCCB_6F00,{0U,4294967243U,0U}}, +{BCCB_6F00,{0U,4294967244U,0U}}, +{BCCB_6F00,{0U,4294967245U,0U}}, +{BCCB_6F00,{0U,4294967246U,0U}}, +{BCCB_6F00,{0U,4294967247U,0U}}, +{BCCB_6F00,{0U,4294967248U,0U}}, +{BCCB_6F00,{0U,4294967249U,0U}}, +{BCCB_6F00,{0U,4294967250U,0U}}, +{BCCB_6F00,{0U,4294967251U,0U}}, +{BCCB_6F00,{0U,4294967252U,0U}}, +{BCCB_6F00,{0U,4294967253U,0U}}, +{BCCB_6F00,{0U,4294967254U,0U}}, +{BCCB_6F00,{0U,4294967255U,0U}}, +{BCCB_6F00,{0U,4294967256U,0U}}, +{BCCB_6F00,{0U,4294967257U,0U}}, +{BCCB_6F00,{0U,4294967258U,0U}}, +{BCCB_6F00,{0U,4294967259U,0U}}, +{BCCB_6F00,{0U,4294967260U,0U}}, +{BCCB_6F00,{0U,4294967261U,0U}}, +{BCCB_6F00,{0U,4294967262U,0U}}, +{BCCB_6F00,{0U,4294967263U,0U}}, +{BCCB_6F00,{0U,4294967264U,0U}}, +{BCCB_6F00,{0U,4294967265U,0U}}, +{BCCB_6F00,{0U,4294967266U,0U}}, +{BCCB_6F00,{0U,4294967267U,0U}}, +{BCCB_6F00,{0U,4294967268U,0U}}, +{BCCB_6F00,{0U,4294967269U,0U}}, +{BCCB_6F00,{0U,4294967270U,0U}}, +{BCCB_6F00,{0U,4294967271U,0U}}, +{BCCB_6F00,{0U,4294967272U,0U}}, +{BCCB_6F00,{0U,4294967273U,0U}}, +{BCCB_6F00,{0U,4294967274U,0U}}, +{BCCB_6F00,{0U,4294967275U,0U}}, +{BCCB_6F00,{0U,4294967276U,0U}}, +{BCCB_6F00,{0U,4294967277U,0U}}, +{BCCB_6F00,{0U,4294967278U,0U}}, +{BCCB_6F00,{0U,4294967279U,0U}}, +{BCCB_6F00,{0U,4294967280U,0U}}, +{BCCB_6F00,{0U,4294967281U,0U}}, +{BCCB_6F00,{0U,4294967282U,0U}}, +{BCCB_6F00,{0U,4294967283U,0U}}, +{BCCB_6F00,{0U,4294967284U,0U}}, +{BCCB_6F00,{0U,4294967285U,0U}}, +{BCCB_6F00,{0U,4294967286U,0U}}, +{BCCB_6F00,{0U,4294967287U,0U}}, +{BCCB_6F00,{0U,4294967288U,0U}}, +{BCCB_6F00,{0U,4294967289U,0U}}, +{BCCB_6F00,{0U,4294967290U,0U}}, +{BCCB_6F00,{0U,4294967291U,0U}}, +{BCCB_6F00,{0U,4294967292U,0U}}, +{BCCB_6F00,{0U,4294967293U,0U}}, +{BCCB_6F00,{0U,4294967294U,0U}}, +{BCCL_6FFF,{0U,0U,0U}}, +{MOVEQ_7000,{0U,0U,4U}}, +{MOVEQ_7000,{0U,1U,0U}}, +{MOVEQ_7000,{0U,2U,0U}}, +{MOVEQ_7000,{0U,3U,0U}}, +{MOVEQ_7000,{0U,4U,0U}}, +{MOVEQ_7000,{0U,5U,0U}}, +{MOVEQ_7000,{0U,6U,0U}}, +{MOVEQ_7000,{0U,7U,0U}}, +{MOVEQ_7000,{0U,8U,0U}}, +{MOVEQ_7000,{0U,9U,0U}}, +{MOVEQ_7000,{0U,10U,0U}}, +{MOVEQ_7000,{0U,11U,0U}}, +{MOVEQ_7000,{0U,12U,0U}}, +{MOVEQ_7000,{0U,13U,0U}}, +{MOVEQ_7000,{0U,14U,0U}}, +{MOVEQ_7000,{0U,15U,0U}}, +{MOVEQ_7000,{0U,16U,0U}}, +{MOVEQ_7000,{0U,17U,0U}}, +{MOVEQ_7000,{0U,18U,0U}}, +{MOVEQ_7000,{0U,19U,0U}}, +{MOVEQ_7000,{0U,20U,0U}}, +{MOVEQ_7000,{0U,21U,0U}}, +{MOVEQ_7000,{0U,22U,0U}}, +{MOVEQ_7000,{0U,23U,0U}}, +{MOVEQ_7000,{0U,24U,0U}}, +{MOVEQ_7000,{0U,25U,0U}}, +{MOVEQ_7000,{0U,26U,0U}}, +{MOVEQ_7000,{0U,27U,0U}}, +{MOVEQ_7000,{0U,28U,0U}}, +{MOVEQ_7000,{0U,29U,0U}}, +{MOVEQ_7000,{0U,30U,0U}}, +{MOVEQ_7000,{0U,31U,0U}}, +{MOVEQ_7000,{0U,32U,0U}}, +{MOVEQ_7000,{0U,33U,0U}}, +{MOVEQ_7000,{0U,34U,0U}}, +{MOVEQ_7000,{0U,35U,0U}}, +{MOVEQ_7000,{0U,36U,0U}}, +{MOVEQ_7000,{0U,37U,0U}}, +{MOVEQ_7000,{0U,38U,0U}}, +{MOVEQ_7000,{0U,39U,0U}}, +{MOVEQ_7000,{0U,40U,0U}}, +{MOVEQ_7000,{0U,41U,0U}}, +{MOVEQ_7000,{0U,42U,0U}}, +{MOVEQ_7000,{0U,43U,0U}}, +{MOVEQ_7000,{0U,44U,0U}}, +{MOVEQ_7000,{0U,45U,0U}}, +{MOVEQ_7000,{0U,46U,0U}}, +{MOVEQ_7000,{0U,47U,0U}}, +{MOVEQ_7000,{0U,48U,0U}}, +{MOVEQ_7000,{0U,49U,0U}}, +{MOVEQ_7000,{0U,50U,0U}}, +{MOVEQ_7000,{0U,51U,0U}}, +{MOVEQ_7000,{0U,52U,0U}}, +{MOVEQ_7000,{0U,53U,0U}}, +{MOVEQ_7000,{0U,54U,0U}}, +{MOVEQ_7000,{0U,55U,0U}}, +{MOVEQ_7000,{0U,56U,0U}}, +{MOVEQ_7000,{0U,57U,0U}}, +{MOVEQ_7000,{0U,58U,0U}}, +{MOVEQ_7000,{0U,59U,0U}}, +{MOVEQ_7000,{0U,60U,0U}}, +{MOVEQ_7000,{0U,61U,0U}}, +{MOVEQ_7000,{0U,62U,0U}}, +{MOVEQ_7000,{0U,63U,0U}}, +{MOVEQ_7000,{0U,64U,0U}}, +{MOVEQ_7000,{0U,65U,0U}}, +{MOVEQ_7000,{0U,66U,0U}}, +{MOVEQ_7000,{0U,67U,0U}}, +{MOVEQ_7000,{0U,68U,0U}}, +{MOVEQ_7000,{0U,69U,0U}}, +{MOVEQ_7000,{0U,70U,0U}}, +{MOVEQ_7000,{0U,71U,0U}}, +{MOVEQ_7000,{0U,72U,0U}}, +{MOVEQ_7000,{0U,73U,0U}}, +{MOVEQ_7000,{0U,74U,0U}}, +{MOVEQ_7000,{0U,75U,0U}}, +{MOVEQ_7000,{0U,76U,0U}}, +{MOVEQ_7000,{0U,77U,0U}}, +{MOVEQ_7000,{0U,78U,0U}}, +{MOVEQ_7000,{0U,79U,0U}}, +{MOVEQ_7000,{0U,80U,0U}}, +{MOVEQ_7000,{0U,81U,0U}}, +{MOVEQ_7000,{0U,82U,0U}}, +{MOVEQ_7000,{0U,83U,0U}}, +{MOVEQ_7000,{0U,84U,0U}}, +{MOVEQ_7000,{0U,85U,0U}}, +{MOVEQ_7000,{0U,86U,0U}}, +{MOVEQ_7000,{0U,87U,0U}}, +{MOVEQ_7000,{0U,88U,0U}}, +{MOVEQ_7000,{0U,89U,0U}}, +{MOVEQ_7000,{0U,90U,0U}}, +{MOVEQ_7000,{0U,91U,0U}}, +{MOVEQ_7000,{0U,92U,0U}}, +{MOVEQ_7000,{0U,93U,0U}}, +{MOVEQ_7000,{0U,94U,0U}}, +{MOVEQ_7000,{0U,95U,0U}}, +{MOVEQ_7000,{0U,96U,0U}}, +{MOVEQ_7000,{0U,97U,0U}}, +{MOVEQ_7000,{0U,98U,0U}}, +{MOVEQ_7000,{0U,99U,0U}}, +{MOVEQ_7000,{0U,100U,0U}}, +{MOVEQ_7000,{0U,101U,0U}}, +{MOVEQ_7000,{0U,102U,0U}}, +{MOVEQ_7000,{0U,103U,0U}}, +{MOVEQ_7000,{0U,104U,0U}}, +{MOVEQ_7000,{0U,105U,0U}}, +{MOVEQ_7000,{0U,106U,0U}}, +{MOVEQ_7000,{0U,107U,0U}}, +{MOVEQ_7000,{0U,108U,0U}}, +{MOVEQ_7000,{0U,109U,0U}}, +{MOVEQ_7000,{0U,110U,0U}}, +{MOVEQ_7000,{0U,111U,0U}}, +{MOVEQ_7000,{0U,112U,0U}}, +{MOVEQ_7000,{0U,113U,0U}}, +{MOVEQ_7000,{0U,114U,0U}}, +{MOVEQ_7000,{0U,115U,0U}}, +{MOVEQ_7000,{0U,116U,0U}}, +{MOVEQ_7000,{0U,117U,0U}}, +{MOVEQ_7000,{0U,118U,0U}}, +{MOVEQ_7000,{0U,119U,0U}}, +{MOVEQ_7000,{0U,120U,0U}}, +{MOVEQ_7000,{0U,121U,0U}}, +{MOVEQ_7000,{0U,122U,0U}}, +{MOVEQ_7000,{0U,123U,0U}}, +{MOVEQ_7000,{0U,124U,0U}}, +{MOVEQ_7000,{0U,125U,0U}}, +{MOVEQ_7000,{0U,126U,0U}}, +{MOVEQ_7000,{0U,127U,0U}}, +{MOVEQ_7000,{0U,4294967168U,8U}}, +{MOVEQ_7000,{0U,4294967169U,8U}}, +{MOVEQ_7000,{0U,4294967170U,8U}}, +{MOVEQ_7000,{0U,4294967171U,8U}}, +{MOVEQ_7000,{0U,4294967172U,8U}}, +{MOVEQ_7000,{0U,4294967173U,8U}}, +{MOVEQ_7000,{0U,4294967174U,8U}}, +{MOVEQ_7000,{0U,4294967175U,8U}}, +{MOVEQ_7000,{0U,4294967176U,8U}}, +{MOVEQ_7000,{0U,4294967177U,8U}}, +{MOVEQ_7000,{0U,4294967178U,8U}}, +{MOVEQ_7000,{0U,4294967179U,8U}}, +{MOVEQ_7000,{0U,4294967180U,8U}}, +{MOVEQ_7000,{0U,4294967181U,8U}}, +{MOVEQ_7000,{0U,4294967182U,8U}}, +{MOVEQ_7000,{0U,4294967183U,8U}}, +{MOVEQ_7000,{0U,4294967184U,8U}}, +{MOVEQ_7000,{0U,4294967185U,8U}}, +{MOVEQ_7000,{0U,4294967186U,8U}}, +{MOVEQ_7000,{0U,4294967187U,8U}}, +{MOVEQ_7000,{0U,4294967188U,8U}}, +{MOVEQ_7000,{0U,4294967189U,8U}}, +{MOVEQ_7000,{0U,4294967190U,8U}}, +{MOVEQ_7000,{0U,4294967191U,8U}}, +{MOVEQ_7000,{0U,4294967192U,8U}}, +{MOVEQ_7000,{0U,4294967193U,8U}}, +{MOVEQ_7000,{0U,4294967194U,8U}}, +{MOVEQ_7000,{0U,4294967195U,8U}}, +{MOVEQ_7000,{0U,4294967196U,8U}}, +{MOVEQ_7000,{0U,4294967197U,8U}}, +{MOVEQ_7000,{0U,4294967198U,8U}}, +{MOVEQ_7000,{0U,4294967199U,8U}}, +{MOVEQ_7000,{0U,4294967200U,8U}}, +{MOVEQ_7000,{0U,4294967201U,8U}}, +{MOVEQ_7000,{0U,4294967202U,8U}}, +{MOVEQ_7000,{0U,4294967203U,8U}}, +{MOVEQ_7000,{0U,4294967204U,8U}}, +{MOVEQ_7000,{0U,4294967205U,8U}}, +{MOVEQ_7000,{0U,4294967206U,8U}}, +{MOVEQ_7000,{0U,4294967207U,8U}}, +{MOVEQ_7000,{0U,4294967208U,8U}}, +{MOVEQ_7000,{0U,4294967209U,8U}}, +{MOVEQ_7000,{0U,4294967210U,8U}}, +{MOVEQ_7000,{0U,4294967211U,8U}}, +{MOVEQ_7000,{0U,4294967212U,8U}}, +{MOVEQ_7000,{0U,4294967213U,8U}}, +{MOVEQ_7000,{0U,4294967214U,8U}}, +{MOVEQ_7000,{0U,4294967215U,8U}}, +{MOVEQ_7000,{0U,4294967216U,8U}}, +{MOVEQ_7000,{0U,4294967217U,8U}}, +{MOVEQ_7000,{0U,4294967218U,8U}}, +{MOVEQ_7000,{0U,4294967219U,8U}}, +{MOVEQ_7000,{0U,4294967220U,8U}}, +{MOVEQ_7000,{0U,4294967221U,8U}}, +{MOVEQ_7000,{0U,4294967222U,8U}}, +{MOVEQ_7000,{0U,4294967223U,8U}}, +{MOVEQ_7000,{0U,4294967224U,8U}}, +{MOVEQ_7000,{0U,4294967225U,8U}}, +{MOVEQ_7000,{0U,4294967226U,8U}}, +{MOVEQ_7000,{0U,4294967227U,8U}}, +{MOVEQ_7000,{0U,4294967228U,8U}}, +{MOVEQ_7000,{0U,4294967229U,8U}}, +{MOVEQ_7000,{0U,4294967230U,8U}}, +{MOVEQ_7000,{0U,4294967231U,8U}}, +{MOVEQ_7000,{0U,4294967232U,8U}}, +{MOVEQ_7000,{0U,4294967233U,8U}}, +{MOVEQ_7000,{0U,4294967234U,8U}}, +{MOVEQ_7000,{0U,4294967235U,8U}}, +{MOVEQ_7000,{0U,4294967236U,8U}}, +{MOVEQ_7000,{0U,4294967237U,8U}}, +{MOVEQ_7000,{0U,4294967238U,8U}}, +{MOVEQ_7000,{0U,4294967239U,8U}}, +{MOVEQ_7000,{0U,4294967240U,8U}}, +{MOVEQ_7000,{0U,4294967241U,8U}}, +{MOVEQ_7000,{0U,4294967242U,8U}}, +{MOVEQ_7000,{0U,4294967243U,8U}}, +{MOVEQ_7000,{0U,4294967244U,8U}}, +{MOVEQ_7000,{0U,4294967245U,8U}}, +{MOVEQ_7000,{0U,4294967246U,8U}}, +{MOVEQ_7000,{0U,4294967247U,8U}}, +{MOVEQ_7000,{0U,4294967248U,8U}}, +{MOVEQ_7000,{0U,4294967249U,8U}}, +{MOVEQ_7000,{0U,4294967250U,8U}}, +{MOVEQ_7000,{0U,4294967251U,8U}}, +{MOVEQ_7000,{0U,4294967252U,8U}}, +{MOVEQ_7000,{0U,4294967253U,8U}}, +{MOVEQ_7000,{0U,4294967254U,8U}}, +{MOVEQ_7000,{0U,4294967255U,8U}}, +{MOVEQ_7000,{0U,4294967256U,8U}}, +{MOVEQ_7000,{0U,4294967257U,8U}}, +{MOVEQ_7000,{0U,4294967258U,8U}}, +{MOVEQ_7000,{0U,4294967259U,8U}}, +{MOVEQ_7000,{0U,4294967260U,8U}}, +{MOVEQ_7000,{0U,4294967261U,8U}}, +{MOVEQ_7000,{0U,4294967262U,8U}}, +{MOVEQ_7000,{0U,4294967263U,8U}}, +{MOVEQ_7000,{0U,4294967264U,8U}}, +{MOVEQ_7000,{0U,4294967265U,8U}}, +{MOVEQ_7000,{0U,4294967266U,8U}}, +{MOVEQ_7000,{0U,4294967267U,8U}}, +{MOVEQ_7000,{0U,4294967268U,8U}}, +{MOVEQ_7000,{0U,4294967269U,8U}}, +{MOVEQ_7000,{0U,4294967270U,8U}}, +{MOVEQ_7000,{0U,4294967271U,8U}}, +{MOVEQ_7000,{0U,4294967272U,8U}}, +{MOVEQ_7000,{0U,4294967273U,8U}}, +{MOVEQ_7000,{0U,4294967274U,8U}}, +{MOVEQ_7000,{0U,4294967275U,8U}}, +{MOVEQ_7000,{0U,4294967276U,8U}}, +{MOVEQ_7000,{0U,4294967277U,8U}}, +{MOVEQ_7000,{0U,4294967278U,8U}}, +{MOVEQ_7000,{0U,4294967279U,8U}}, +{MOVEQ_7000,{0U,4294967280U,8U}}, +{MOVEQ_7000,{0U,4294967281U,8U}}, +{MOVEQ_7000,{0U,4294967282U,8U}}, +{MOVEQ_7000,{0U,4294967283U,8U}}, +{MOVEQ_7000,{0U,4294967284U,8U}}, +{MOVEQ_7000,{0U,4294967285U,8U}}, +{MOVEQ_7000,{0U,4294967286U,8U}}, +{MOVEQ_7000,{0U,4294967287U,8U}}, +{MOVEQ_7000,{0U,4294967288U,8U}}, +{MOVEQ_7000,{0U,4294967289U,8U}}, +{MOVEQ_7000,{0U,4294967290U,8U}}, +{MOVEQ_7000,{0U,4294967291U,8U}}, +{MOVEQ_7000,{0U,4294967292U,8U}}, +{MOVEQ_7000,{0U,4294967293U,8U}}, +{MOVEQ_7000,{0U,4294967294U,8U}}, +{MOVEQ_7000,{0U,4294967295U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEQ_7000,{1U,0U,4U}}, +{MOVEQ_7000,{1U,1U,0U}}, +{MOVEQ_7000,{1U,2U,0U}}, +{MOVEQ_7000,{1U,3U,0U}}, +{MOVEQ_7000,{1U,4U,0U}}, +{MOVEQ_7000,{1U,5U,0U}}, +{MOVEQ_7000,{1U,6U,0U}}, +{MOVEQ_7000,{1U,7U,0U}}, +{MOVEQ_7000,{1U,8U,0U}}, +{MOVEQ_7000,{1U,9U,0U}}, +{MOVEQ_7000,{1U,10U,0U}}, +{MOVEQ_7000,{1U,11U,0U}}, +{MOVEQ_7000,{1U,12U,0U}}, +{MOVEQ_7000,{1U,13U,0U}}, +{MOVEQ_7000,{1U,14U,0U}}, +{MOVEQ_7000,{1U,15U,0U}}, +{MOVEQ_7000,{1U,16U,0U}}, +{MOVEQ_7000,{1U,17U,0U}}, +{MOVEQ_7000,{1U,18U,0U}}, +{MOVEQ_7000,{1U,19U,0U}}, +{MOVEQ_7000,{1U,20U,0U}}, +{MOVEQ_7000,{1U,21U,0U}}, +{MOVEQ_7000,{1U,22U,0U}}, +{MOVEQ_7000,{1U,23U,0U}}, +{MOVEQ_7000,{1U,24U,0U}}, +{MOVEQ_7000,{1U,25U,0U}}, +{MOVEQ_7000,{1U,26U,0U}}, +{MOVEQ_7000,{1U,27U,0U}}, +{MOVEQ_7000,{1U,28U,0U}}, +{MOVEQ_7000,{1U,29U,0U}}, +{MOVEQ_7000,{1U,30U,0U}}, +{MOVEQ_7000,{1U,31U,0U}}, +{MOVEQ_7000,{1U,32U,0U}}, +{MOVEQ_7000,{1U,33U,0U}}, +{MOVEQ_7000,{1U,34U,0U}}, +{MOVEQ_7000,{1U,35U,0U}}, +{MOVEQ_7000,{1U,36U,0U}}, +{MOVEQ_7000,{1U,37U,0U}}, +{MOVEQ_7000,{1U,38U,0U}}, +{MOVEQ_7000,{1U,39U,0U}}, +{MOVEQ_7000,{1U,40U,0U}}, +{MOVEQ_7000,{1U,41U,0U}}, +{MOVEQ_7000,{1U,42U,0U}}, +{MOVEQ_7000,{1U,43U,0U}}, +{MOVEQ_7000,{1U,44U,0U}}, +{MOVEQ_7000,{1U,45U,0U}}, +{MOVEQ_7000,{1U,46U,0U}}, +{MOVEQ_7000,{1U,47U,0U}}, +{MOVEQ_7000,{1U,48U,0U}}, +{MOVEQ_7000,{1U,49U,0U}}, +{MOVEQ_7000,{1U,50U,0U}}, +{MOVEQ_7000,{1U,51U,0U}}, +{MOVEQ_7000,{1U,52U,0U}}, +{MOVEQ_7000,{1U,53U,0U}}, +{MOVEQ_7000,{1U,54U,0U}}, +{MOVEQ_7000,{1U,55U,0U}}, +{MOVEQ_7000,{1U,56U,0U}}, +{MOVEQ_7000,{1U,57U,0U}}, +{MOVEQ_7000,{1U,58U,0U}}, +{MOVEQ_7000,{1U,59U,0U}}, +{MOVEQ_7000,{1U,60U,0U}}, +{MOVEQ_7000,{1U,61U,0U}}, +{MOVEQ_7000,{1U,62U,0U}}, +{MOVEQ_7000,{1U,63U,0U}}, +{MOVEQ_7000,{1U,64U,0U}}, +{MOVEQ_7000,{1U,65U,0U}}, +{MOVEQ_7000,{1U,66U,0U}}, +{MOVEQ_7000,{1U,67U,0U}}, +{MOVEQ_7000,{1U,68U,0U}}, +{MOVEQ_7000,{1U,69U,0U}}, +{MOVEQ_7000,{1U,70U,0U}}, +{MOVEQ_7000,{1U,71U,0U}}, +{MOVEQ_7000,{1U,72U,0U}}, +{MOVEQ_7000,{1U,73U,0U}}, +{MOVEQ_7000,{1U,74U,0U}}, +{MOVEQ_7000,{1U,75U,0U}}, +{MOVEQ_7000,{1U,76U,0U}}, +{MOVEQ_7000,{1U,77U,0U}}, +{MOVEQ_7000,{1U,78U,0U}}, +{MOVEQ_7000,{1U,79U,0U}}, +{MOVEQ_7000,{1U,80U,0U}}, +{MOVEQ_7000,{1U,81U,0U}}, +{MOVEQ_7000,{1U,82U,0U}}, +{MOVEQ_7000,{1U,83U,0U}}, +{MOVEQ_7000,{1U,84U,0U}}, +{MOVEQ_7000,{1U,85U,0U}}, +{MOVEQ_7000,{1U,86U,0U}}, +{MOVEQ_7000,{1U,87U,0U}}, +{MOVEQ_7000,{1U,88U,0U}}, +{MOVEQ_7000,{1U,89U,0U}}, +{MOVEQ_7000,{1U,90U,0U}}, +{MOVEQ_7000,{1U,91U,0U}}, +{MOVEQ_7000,{1U,92U,0U}}, +{MOVEQ_7000,{1U,93U,0U}}, +{MOVEQ_7000,{1U,94U,0U}}, +{MOVEQ_7000,{1U,95U,0U}}, +{MOVEQ_7000,{1U,96U,0U}}, +{MOVEQ_7000,{1U,97U,0U}}, +{MOVEQ_7000,{1U,98U,0U}}, +{MOVEQ_7000,{1U,99U,0U}}, +{MOVEQ_7000,{1U,100U,0U}}, +{MOVEQ_7000,{1U,101U,0U}}, +{MOVEQ_7000,{1U,102U,0U}}, +{MOVEQ_7000,{1U,103U,0U}}, +{MOVEQ_7000,{1U,104U,0U}}, +{MOVEQ_7000,{1U,105U,0U}}, +{MOVEQ_7000,{1U,106U,0U}}, +{MOVEQ_7000,{1U,107U,0U}}, +{MOVEQ_7000,{1U,108U,0U}}, +{MOVEQ_7000,{1U,109U,0U}}, +{MOVEQ_7000,{1U,110U,0U}}, +{MOVEQ_7000,{1U,111U,0U}}, +{MOVEQ_7000,{1U,112U,0U}}, +{MOVEQ_7000,{1U,113U,0U}}, +{MOVEQ_7000,{1U,114U,0U}}, +{MOVEQ_7000,{1U,115U,0U}}, +{MOVEQ_7000,{1U,116U,0U}}, +{MOVEQ_7000,{1U,117U,0U}}, +{MOVEQ_7000,{1U,118U,0U}}, +{MOVEQ_7000,{1U,119U,0U}}, +{MOVEQ_7000,{1U,120U,0U}}, +{MOVEQ_7000,{1U,121U,0U}}, +{MOVEQ_7000,{1U,122U,0U}}, +{MOVEQ_7000,{1U,123U,0U}}, +{MOVEQ_7000,{1U,124U,0U}}, +{MOVEQ_7000,{1U,125U,0U}}, +{MOVEQ_7000,{1U,126U,0U}}, +{MOVEQ_7000,{1U,127U,0U}}, +{MOVEQ_7000,{1U,4294967168U,8U}}, +{MOVEQ_7000,{1U,4294967169U,8U}}, +{MOVEQ_7000,{1U,4294967170U,8U}}, +{MOVEQ_7000,{1U,4294967171U,8U}}, +{MOVEQ_7000,{1U,4294967172U,8U}}, +{MOVEQ_7000,{1U,4294967173U,8U}}, +{MOVEQ_7000,{1U,4294967174U,8U}}, +{MOVEQ_7000,{1U,4294967175U,8U}}, +{MOVEQ_7000,{1U,4294967176U,8U}}, +{MOVEQ_7000,{1U,4294967177U,8U}}, +{MOVEQ_7000,{1U,4294967178U,8U}}, +{MOVEQ_7000,{1U,4294967179U,8U}}, +{MOVEQ_7000,{1U,4294967180U,8U}}, +{MOVEQ_7000,{1U,4294967181U,8U}}, +{MOVEQ_7000,{1U,4294967182U,8U}}, +{MOVEQ_7000,{1U,4294967183U,8U}}, +{MOVEQ_7000,{1U,4294967184U,8U}}, +{MOVEQ_7000,{1U,4294967185U,8U}}, +{MOVEQ_7000,{1U,4294967186U,8U}}, +{MOVEQ_7000,{1U,4294967187U,8U}}, +{MOVEQ_7000,{1U,4294967188U,8U}}, +{MOVEQ_7000,{1U,4294967189U,8U}}, +{MOVEQ_7000,{1U,4294967190U,8U}}, +{MOVEQ_7000,{1U,4294967191U,8U}}, +{MOVEQ_7000,{1U,4294967192U,8U}}, +{MOVEQ_7000,{1U,4294967193U,8U}}, +{MOVEQ_7000,{1U,4294967194U,8U}}, +{MOVEQ_7000,{1U,4294967195U,8U}}, +{MOVEQ_7000,{1U,4294967196U,8U}}, +{MOVEQ_7000,{1U,4294967197U,8U}}, +{MOVEQ_7000,{1U,4294967198U,8U}}, +{MOVEQ_7000,{1U,4294967199U,8U}}, +{MOVEQ_7000,{1U,4294967200U,8U}}, +{MOVEQ_7000,{1U,4294967201U,8U}}, +{MOVEQ_7000,{1U,4294967202U,8U}}, +{MOVEQ_7000,{1U,4294967203U,8U}}, +{MOVEQ_7000,{1U,4294967204U,8U}}, +{MOVEQ_7000,{1U,4294967205U,8U}}, +{MOVEQ_7000,{1U,4294967206U,8U}}, +{MOVEQ_7000,{1U,4294967207U,8U}}, +{MOVEQ_7000,{1U,4294967208U,8U}}, +{MOVEQ_7000,{1U,4294967209U,8U}}, +{MOVEQ_7000,{1U,4294967210U,8U}}, +{MOVEQ_7000,{1U,4294967211U,8U}}, +{MOVEQ_7000,{1U,4294967212U,8U}}, +{MOVEQ_7000,{1U,4294967213U,8U}}, +{MOVEQ_7000,{1U,4294967214U,8U}}, +{MOVEQ_7000,{1U,4294967215U,8U}}, +{MOVEQ_7000,{1U,4294967216U,8U}}, +{MOVEQ_7000,{1U,4294967217U,8U}}, +{MOVEQ_7000,{1U,4294967218U,8U}}, +{MOVEQ_7000,{1U,4294967219U,8U}}, +{MOVEQ_7000,{1U,4294967220U,8U}}, +{MOVEQ_7000,{1U,4294967221U,8U}}, +{MOVEQ_7000,{1U,4294967222U,8U}}, +{MOVEQ_7000,{1U,4294967223U,8U}}, +{MOVEQ_7000,{1U,4294967224U,8U}}, +{MOVEQ_7000,{1U,4294967225U,8U}}, +{MOVEQ_7000,{1U,4294967226U,8U}}, +{MOVEQ_7000,{1U,4294967227U,8U}}, +{MOVEQ_7000,{1U,4294967228U,8U}}, +{MOVEQ_7000,{1U,4294967229U,8U}}, +{MOVEQ_7000,{1U,4294967230U,8U}}, +{MOVEQ_7000,{1U,4294967231U,8U}}, +{MOVEQ_7000,{1U,4294967232U,8U}}, +{MOVEQ_7000,{1U,4294967233U,8U}}, +{MOVEQ_7000,{1U,4294967234U,8U}}, +{MOVEQ_7000,{1U,4294967235U,8U}}, +{MOVEQ_7000,{1U,4294967236U,8U}}, +{MOVEQ_7000,{1U,4294967237U,8U}}, +{MOVEQ_7000,{1U,4294967238U,8U}}, +{MOVEQ_7000,{1U,4294967239U,8U}}, +{MOVEQ_7000,{1U,4294967240U,8U}}, +{MOVEQ_7000,{1U,4294967241U,8U}}, +{MOVEQ_7000,{1U,4294967242U,8U}}, +{MOVEQ_7000,{1U,4294967243U,8U}}, +{MOVEQ_7000,{1U,4294967244U,8U}}, +{MOVEQ_7000,{1U,4294967245U,8U}}, +{MOVEQ_7000,{1U,4294967246U,8U}}, +{MOVEQ_7000,{1U,4294967247U,8U}}, +{MOVEQ_7000,{1U,4294967248U,8U}}, +{MOVEQ_7000,{1U,4294967249U,8U}}, +{MOVEQ_7000,{1U,4294967250U,8U}}, +{MOVEQ_7000,{1U,4294967251U,8U}}, +{MOVEQ_7000,{1U,4294967252U,8U}}, +{MOVEQ_7000,{1U,4294967253U,8U}}, +{MOVEQ_7000,{1U,4294967254U,8U}}, +{MOVEQ_7000,{1U,4294967255U,8U}}, +{MOVEQ_7000,{1U,4294967256U,8U}}, +{MOVEQ_7000,{1U,4294967257U,8U}}, +{MOVEQ_7000,{1U,4294967258U,8U}}, +{MOVEQ_7000,{1U,4294967259U,8U}}, +{MOVEQ_7000,{1U,4294967260U,8U}}, +{MOVEQ_7000,{1U,4294967261U,8U}}, +{MOVEQ_7000,{1U,4294967262U,8U}}, +{MOVEQ_7000,{1U,4294967263U,8U}}, +{MOVEQ_7000,{1U,4294967264U,8U}}, +{MOVEQ_7000,{1U,4294967265U,8U}}, +{MOVEQ_7000,{1U,4294967266U,8U}}, +{MOVEQ_7000,{1U,4294967267U,8U}}, +{MOVEQ_7000,{1U,4294967268U,8U}}, +{MOVEQ_7000,{1U,4294967269U,8U}}, +{MOVEQ_7000,{1U,4294967270U,8U}}, +{MOVEQ_7000,{1U,4294967271U,8U}}, +{MOVEQ_7000,{1U,4294967272U,8U}}, +{MOVEQ_7000,{1U,4294967273U,8U}}, +{MOVEQ_7000,{1U,4294967274U,8U}}, +{MOVEQ_7000,{1U,4294967275U,8U}}, +{MOVEQ_7000,{1U,4294967276U,8U}}, +{MOVEQ_7000,{1U,4294967277U,8U}}, +{MOVEQ_7000,{1U,4294967278U,8U}}, +{MOVEQ_7000,{1U,4294967279U,8U}}, +{MOVEQ_7000,{1U,4294967280U,8U}}, +{MOVEQ_7000,{1U,4294967281U,8U}}, +{MOVEQ_7000,{1U,4294967282U,8U}}, +{MOVEQ_7000,{1U,4294967283U,8U}}, +{MOVEQ_7000,{1U,4294967284U,8U}}, +{MOVEQ_7000,{1U,4294967285U,8U}}, +{MOVEQ_7000,{1U,4294967286U,8U}}, +{MOVEQ_7000,{1U,4294967287U,8U}}, +{MOVEQ_7000,{1U,4294967288U,8U}}, +{MOVEQ_7000,{1U,4294967289U,8U}}, +{MOVEQ_7000,{1U,4294967290U,8U}}, +{MOVEQ_7000,{1U,4294967291U,8U}}, +{MOVEQ_7000,{1U,4294967292U,8U}}, +{MOVEQ_7000,{1U,4294967293U,8U}}, +{MOVEQ_7000,{1U,4294967294U,8U}}, +{MOVEQ_7000,{1U,4294967295U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEQ_7000,{2U,0U,4U}}, +{MOVEQ_7000,{2U,1U,0U}}, +{MOVEQ_7000,{2U,2U,0U}}, +{MOVEQ_7000,{2U,3U,0U}}, +{MOVEQ_7000,{2U,4U,0U}}, +{MOVEQ_7000,{2U,5U,0U}}, +{MOVEQ_7000,{2U,6U,0U}}, +{MOVEQ_7000,{2U,7U,0U}}, +{MOVEQ_7000,{2U,8U,0U}}, +{MOVEQ_7000,{2U,9U,0U}}, +{MOVEQ_7000,{2U,10U,0U}}, +{MOVEQ_7000,{2U,11U,0U}}, +{MOVEQ_7000,{2U,12U,0U}}, +{MOVEQ_7000,{2U,13U,0U}}, +{MOVEQ_7000,{2U,14U,0U}}, +{MOVEQ_7000,{2U,15U,0U}}, +{MOVEQ_7000,{2U,16U,0U}}, +{MOVEQ_7000,{2U,17U,0U}}, +{MOVEQ_7000,{2U,18U,0U}}, +{MOVEQ_7000,{2U,19U,0U}}, +{MOVEQ_7000,{2U,20U,0U}}, +{MOVEQ_7000,{2U,21U,0U}}, +{MOVEQ_7000,{2U,22U,0U}}, +{MOVEQ_7000,{2U,23U,0U}}, +{MOVEQ_7000,{2U,24U,0U}}, +{MOVEQ_7000,{2U,25U,0U}}, +{MOVEQ_7000,{2U,26U,0U}}, +{MOVEQ_7000,{2U,27U,0U}}, +{MOVEQ_7000,{2U,28U,0U}}, +{MOVEQ_7000,{2U,29U,0U}}, +{MOVEQ_7000,{2U,30U,0U}}, +{MOVEQ_7000,{2U,31U,0U}}, +{MOVEQ_7000,{2U,32U,0U}}, +{MOVEQ_7000,{2U,33U,0U}}, +{MOVEQ_7000,{2U,34U,0U}}, +{MOVEQ_7000,{2U,35U,0U}}, +{MOVEQ_7000,{2U,36U,0U}}, +{MOVEQ_7000,{2U,37U,0U}}, +{MOVEQ_7000,{2U,38U,0U}}, +{MOVEQ_7000,{2U,39U,0U}}, +{MOVEQ_7000,{2U,40U,0U}}, +{MOVEQ_7000,{2U,41U,0U}}, +{MOVEQ_7000,{2U,42U,0U}}, +{MOVEQ_7000,{2U,43U,0U}}, +{MOVEQ_7000,{2U,44U,0U}}, +{MOVEQ_7000,{2U,45U,0U}}, +{MOVEQ_7000,{2U,46U,0U}}, +{MOVEQ_7000,{2U,47U,0U}}, +{MOVEQ_7000,{2U,48U,0U}}, +{MOVEQ_7000,{2U,49U,0U}}, +{MOVEQ_7000,{2U,50U,0U}}, +{MOVEQ_7000,{2U,51U,0U}}, +{MOVEQ_7000,{2U,52U,0U}}, +{MOVEQ_7000,{2U,53U,0U}}, +{MOVEQ_7000,{2U,54U,0U}}, +{MOVEQ_7000,{2U,55U,0U}}, +{MOVEQ_7000,{2U,56U,0U}}, +{MOVEQ_7000,{2U,57U,0U}}, +{MOVEQ_7000,{2U,58U,0U}}, +{MOVEQ_7000,{2U,59U,0U}}, +{MOVEQ_7000,{2U,60U,0U}}, +{MOVEQ_7000,{2U,61U,0U}}, +{MOVEQ_7000,{2U,62U,0U}}, +{MOVEQ_7000,{2U,63U,0U}}, +{MOVEQ_7000,{2U,64U,0U}}, +{MOVEQ_7000,{2U,65U,0U}}, +{MOVEQ_7000,{2U,66U,0U}}, +{MOVEQ_7000,{2U,67U,0U}}, +{MOVEQ_7000,{2U,68U,0U}}, +{MOVEQ_7000,{2U,69U,0U}}, +{MOVEQ_7000,{2U,70U,0U}}, +{MOVEQ_7000,{2U,71U,0U}}, +{MOVEQ_7000,{2U,72U,0U}}, +{MOVEQ_7000,{2U,73U,0U}}, +{MOVEQ_7000,{2U,74U,0U}}, +{MOVEQ_7000,{2U,75U,0U}}, +{MOVEQ_7000,{2U,76U,0U}}, +{MOVEQ_7000,{2U,77U,0U}}, +{MOVEQ_7000,{2U,78U,0U}}, +{MOVEQ_7000,{2U,79U,0U}}, +{MOVEQ_7000,{2U,80U,0U}}, +{MOVEQ_7000,{2U,81U,0U}}, +{MOVEQ_7000,{2U,82U,0U}}, +{MOVEQ_7000,{2U,83U,0U}}, +{MOVEQ_7000,{2U,84U,0U}}, +{MOVEQ_7000,{2U,85U,0U}}, +{MOVEQ_7000,{2U,86U,0U}}, +{MOVEQ_7000,{2U,87U,0U}}, +{MOVEQ_7000,{2U,88U,0U}}, +{MOVEQ_7000,{2U,89U,0U}}, +{MOVEQ_7000,{2U,90U,0U}}, +{MOVEQ_7000,{2U,91U,0U}}, +{MOVEQ_7000,{2U,92U,0U}}, +{MOVEQ_7000,{2U,93U,0U}}, +{MOVEQ_7000,{2U,94U,0U}}, +{MOVEQ_7000,{2U,95U,0U}}, +{MOVEQ_7000,{2U,96U,0U}}, +{MOVEQ_7000,{2U,97U,0U}}, +{MOVEQ_7000,{2U,98U,0U}}, +{MOVEQ_7000,{2U,99U,0U}}, +{MOVEQ_7000,{2U,100U,0U}}, +{MOVEQ_7000,{2U,101U,0U}}, +{MOVEQ_7000,{2U,102U,0U}}, +{MOVEQ_7000,{2U,103U,0U}}, +{MOVEQ_7000,{2U,104U,0U}}, +{MOVEQ_7000,{2U,105U,0U}}, +{MOVEQ_7000,{2U,106U,0U}}, +{MOVEQ_7000,{2U,107U,0U}}, +{MOVEQ_7000,{2U,108U,0U}}, +{MOVEQ_7000,{2U,109U,0U}}, +{MOVEQ_7000,{2U,110U,0U}}, +{MOVEQ_7000,{2U,111U,0U}}, +{MOVEQ_7000,{2U,112U,0U}}, +{MOVEQ_7000,{2U,113U,0U}}, +{MOVEQ_7000,{2U,114U,0U}}, +{MOVEQ_7000,{2U,115U,0U}}, +{MOVEQ_7000,{2U,116U,0U}}, +{MOVEQ_7000,{2U,117U,0U}}, +{MOVEQ_7000,{2U,118U,0U}}, +{MOVEQ_7000,{2U,119U,0U}}, +{MOVEQ_7000,{2U,120U,0U}}, +{MOVEQ_7000,{2U,121U,0U}}, +{MOVEQ_7000,{2U,122U,0U}}, +{MOVEQ_7000,{2U,123U,0U}}, +{MOVEQ_7000,{2U,124U,0U}}, +{MOVEQ_7000,{2U,125U,0U}}, +{MOVEQ_7000,{2U,126U,0U}}, +{MOVEQ_7000,{2U,127U,0U}}, +{MOVEQ_7000,{2U,4294967168U,8U}}, +{MOVEQ_7000,{2U,4294967169U,8U}}, +{MOVEQ_7000,{2U,4294967170U,8U}}, +{MOVEQ_7000,{2U,4294967171U,8U}}, +{MOVEQ_7000,{2U,4294967172U,8U}}, +{MOVEQ_7000,{2U,4294967173U,8U}}, +{MOVEQ_7000,{2U,4294967174U,8U}}, +{MOVEQ_7000,{2U,4294967175U,8U}}, +{MOVEQ_7000,{2U,4294967176U,8U}}, +{MOVEQ_7000,{2U,4294967177U,8U}}, +{MOVEQ_7000,{2U,4294967178U,8U}}, +{MOVEQ_7000,{2U,4294967179U,8U}}, +{MOVEQ_7000,{2U,4294967180U,8U}}, +{MOVEQ_7000,{2U,4294967181U,8U}}, +{MOVEQ_7000,{2U,4294967182U,8U}}, +{MOVEQ_7000,{2U,4294967183U,8U}}, +{MOVEQ_7000,{2U,4294967184U,8U}}, +{MOVEQ_7000,{2U,4294967185U,8U}}, +{MOVEQ_7000,{2U,4294967186U,8U}}, +{MOVEQ_7000,{2U,4294967187U,8U}}, +{MOVEQ_7000,{2U,4294967188U,8U}}, +{MOVEQ_7000,{2U,4294967189U,8U}}, +{MOVEQ_7000,{2U,4294967190U,8U}}, +{MOVEQ_7000,{2U,4294967191U,8U}}, +{MOVEQ_7000,{2U,4294967192U,8U}}, +{MOVEQ_7000,{2U,4294967193U,8U}}, +{MOVEQ_7000,{2U,4294967194U,8U}}, +{MOVEQ_7000,{2U,4294967195U,8U}}, +{MOVEQ_7000,{2U,4294967196U,8U}}, +{MOVEQ_7000,{2U,4294967197U,8U}}, +{MOVEQ_7000,{2U,4294967198U,8U}}, +{MOVEQ_7000,{2U,4294967199U,8U}}, +{MOVEQ_7000,{2U,4294967200U,8U}}, +{MOVEQ_7000,{2U,4294967201U,8U}}, +{MOVEQ_7000,{2U,4294967202U,8U}}, +{MOVEQ_7000,{2U,4294967203U,8U}}, +{MOVEQ_7000,{2U,4294967204U,8U}}, +{MOVEQ_7000,{2U,4294967205U,8U}}, +{MOVEQ_7000,{2U,4294967206U,8U}}, +{MOVEQ_7000,{2U,4294967207U,8U}}, +{MOVEQ_7000,{2U,4294967208U,8U}}, +{MOVEQ_7000,{2U,4294967209U,8U}}, +{MOVEQ_7000,{2U,4294967210U,8U}}, +{MOVEQ_7000,{2U,4294967211U,8U}}, +{MOVEQ_7000,{2U,4294967212U,8U}}, +{MOVEQ_7000,{2U,4294967213U,8U}}, +{MOVEQ_7000,{2U,4294967214U,8U}}, +{MOVEQ_7000,{2U,4294967215U,8U}}, +{MOVEQ_7000,{2U,4294967216U,8U}}, +{MOVEQ_7000,{2U,4294967217U,8U}}, +{MOVEQ_7000,{2U,4294967218U,8U}}, +{MOVEQ_7000,{2U,4294967219U,8U}}, +{MOVEQ_7000,{2U,4294967220U,8U}}, +{MOVEQ_7000,{2U,4294967221U,8U}}, +{MOVEQ_7000,{2U,4294967222U,8U}}, +{MOVEQ_7000,{2U,4294967223U,8U}}, +{MOVEQ_7000,{2U,4294967224U,8U}}, +{MOVEQ_7000,{2U,4294967225U,8U}}, +{MOVEQ_7000,{2U,4294967226U,8U}}, +{MOVEQ_7000,{2U,4294967227U,8U}}, +{MOVEQ_7000,{2U,4294967228U,8U}}, +{MOVEQ_7000,{2U,4294967229U,8U}}, +{MOVEQ_7000,{2U,4294967230U,8U}}, +{MOVEQ_7000,{2U,4294967231U,8U}}, +{MOVEQ_7000,{2U,4294967232U,8U}}, +{MOVEQ_7000,{2U,4294967233U,8U}}, +{MOVEQ_7000,{2U,4294967234U,8U}}, +{MOVEQ_7000,{2U,4294967235U,8U}}, +{MOVEQ_7000,{2U,4294967236U,8U}}, +{MOVEQ_7000,{2U,4294967237U,8U}}, +{MOVEQ_7000,{2U,4294967238U,8U}}, +{MOVEQ_7000,{2U,4294967239U,8U}}, +{MOVEQ_7000,{2U,4294967240U,8U}}, +{MOVEQ_7000,{2U,4294967241U,8U}}, +{MOVEQ_7000,{2U,4294967242U,8U}}, +{MOVEQ_7000,{2U,4294967243U,8U}}, +{MOVEQ_7000,{2U,4294967244U,8U}}, +{MOVEQ_7000,{2U,4294967245U,8U}}, +{MOVEQ_7000,{2U,4294967246U,8U}}, +{MOVEQ_7000,{2U,4294967247U,8U}}, +{MOVEQ_7000,{2U,4294967248U,8U}}, +{MOVEQ_7000,{2U,4294967249U,8U}}, +{MOVEQ_7000,{2U,4294967250U,8U}}, +{MOVEQ_7000,{2U,4294967251U,8U}}, +{MOVEQ_7000,{2U,4294967252U,8U}}, +{MOVEQ_7000,{2U,4294967253U,8U}}, +{MOVEQ_7000,{2U,4294967254U,8U}}, +{MOVEQ_7000,{2U,4294967255U,8U}}, +{MOVEQ_7000,{2U,4294967256U,8U}}, +{MOVEQ_7000,{2U,4294967257U,8U}}, +{MOVEQ_7000,{2U,4294967258U,8U}}, +{MOVEQ_7000,{2U,4294967259U,8U}}, +{MOVEQ_7000,{2U,4294967260U,8U}}, +{MOVEQ_7000,{2U,4294967261U,8U}}, +{MOVEQ_7000,{2U,4294967262U,8U}}, +{MOVEQ_7000,{2U,4294967263U,8U}}, +{MOVEQ_7000,{2U,4294967264U,8U}}, +{MOVEQ_7000,{2U,4294967265U,8U}}, +{MOVEQ_7000,{2U,4294967266U,8U}}, +{MOVEQ_7000,{2U,4294967267U,8U}}, +{MOVEQ_7000,{2U,4294967268U,8U}}, +{MOVEQ_7000,{2U,4294967269U,8U}}, +{MOVEQ_7000,{2U,4294967270U,8U}}, +{MOVEQ_7000,{2U,4294967271U,8U}}, +{MOVEQ_7000,{2U,4294967272U,8U}}, +{MOVEQ_7000,{2U,4294967273U,8U}}, +{MOVEQ_7000,{2U,4294967274U,8U}}, +{MOVEQ_7000,{2U,4294967275U,8U}}, +{MOVEQ_7000,{2U,4294967276U,8U}}, +{MOVEQ_7000,{2U,4294967277U,8U}}, +{MOVEQ_7000,{2U,4294967278U,8U}}, +{MOVEQ_7000,{2U,4294967279U,8U}}, +{MOVEQ_7000,{2U,4294967280U,8U}}, +{MOVEQ_7000,{2U,4294967281U,8U}}, +{MOVEQ_7000,{2U,4294967282U,8U}}, +{MOVEQ_7000,{2U,4294967283U,8U}}, +{MOVEQ_7000,{2U,4294967284U,8U}}, +{MOVEQ_7000,{2U,4294967285U,8U}}, +{MOVEQ_7000,{2U,4294967286U,8U}}, +{MOVEQ_7000,{2U,4294967287U,8U}}, +{MOVEQ_7000,{2U,4294967288U,8U}}, +{MOVEQ_7000,{2U,4294967289U,8U}}, +{MOVEQ_7000,{2U,4294967290U,8U}}, +{MOVEQ_7000,{2U,4294967291U,8U}}, +{MOVEQ_7000,{2U,4294967292U,8U}}, +{MOVEQ_7000,{2U,4294967293U,8U}}, +{MOVEQ_7000,{2U,4294967294U,8U}}, +{MOVEQ_7000,{2U,4294967295U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEQ_7000,{3U,0U,4U}}, +{MOVEQ_7000,{3U,1U,0U}}, +{MOVEQ_7000,{3U,2U,0U}}, +{MOVEQ_7000,{3U,3U,0U}}, +{MOVEQ_7000,{3U,4U,0U}}, +{MOVEQ_7000,{3U,5U,0U}}, +{MOVEQ_7000,{3U,6U,0U}}, +{MOVEQ_7000,{3U,7U,0U}}, +{MOVEQ_7000,{3U,8U,0U}}, +{MOVEQ_7000,{3U,9U,0U}}, +{MOVEQ_7000,{3U,10U,0U}}, +{MOVEQ_7000,{3U,11U,0U}}, +{MOVEQ_7000,{3U,12U,0U}}, +{MOVEQ_7000,{3U,13U,0U}}, +{MOVEQ_7000,{3U,14U,0U}}, +{MOVEQ_7000,{3U,15U,0U}}, +{MOVEQ_7000,{3U,16U,0U}}, +{MOVEQ_7000,{3U,17U,0U}}, +{MOVEQ_7000,{3U,18U,0U}}, +{MOVEQ_7000,{3U,19U,0U}}, +{MOVEQ_7000,{3U,20U,0U}}, +{MOVEQ_7000,{3U,21U,0U}}, +{MOVEQ_7000,{3U,22U,0U}}, +{MOVEQ_7000,{3U,23U,0U}}, +{MOVEQ_7000,{3U,24U,0U}}, +{MOVEQ_7000,{3U,25U,0U}}, +{MOVEQ_7000,{3U,26U,0U}}, +{MOVEQ_7000,{3U,27U,0U}}, +{MOVEQ_7000,{3U,28U,0U}}, +{MOVEQ_7000,{3U,29U,0U}}, +{MOVEQ_7000,{3U,30U,0U}}, +{MOVEQ_7000,{3U,31U,0U}}, +{MOVEQ_7000,{3U,32U,0U}}, +{MOVEQ_7000,{3U,33U,0U}}, +{MOVEQ_7000,{3U,34U,0U}}, +{MOVEQ_7000,{3U,35U,0U}}, +{MOVEQ_7000,{3U,36U,0U}}, +{MOVEQ_7000,{3U,37U,0U}}, +{MOVEQ_7000,{3U,38U,0U}}, +{MOVEQ_7000,{3U,39U,0U}}, +{MOVEQ_7000,{3U,40U,0U}}, +{MOVEQ_7000,{3U,41U,0U}}, +{MOVEQ_7000,{3U,42U,0U}}, +{MOVEQ_7000,{3U,43U,0U}}, +{MOVEQ_7000,{3U,44U,0U}}, +{MOVEQ_7000,{3U,45U,0U}}, +{MOVEQ_7000,{3U,46U,0U}}, +{MOVEQ_7000,{3U,47U,0U}}, +{MOVEQ_7000,{3U,48U,0U}}, +{MOVEQ_7000,{3U,49U,0U}}, +{MOVEQ_7000,{3U,50U,0U}}, +{MOVEQ_7000,{3U,51U,0U}}, +{MOVEQ_7000,{3U,52U,0U}}, +{MOVEQ_7000,{3U,53U,0U}}, +{MOVEQ_7000,{3U,54U,0U}}, +{MOVEQ_7000,{3U,55U,0U}}, +{MOVEQ_7000,{3U,56U,0U}}, +{MOVEQ_7000,{3U,57U,0U}}, +{MOVEQ_7000,{3U,58U,0U}}, +{MOVEQ_7000,{3U,59U,0U}}, +{MOVEQ_7000,{3U,60U,0U}}, +{MOVEQ_7000,{3U,61U,0U}}, +{MOVEQ_7000,{3U,62U,0U}}, +{MOVEQ_7000,{3U,63U,0U}}, +{MOVEQ_7000,{3U,64U,0U}}, +{MOVEQ_7000,{3U,65U,0U}}, +{MOVEQ_7000,{3U,66U,0U}}, +{MOVEQ_7000,{3U,67U,0U}}, +{MOVEQ_7000,{3U,68U,0U}}, +{MOVEQ_7000,{3U,69U,0U}}, +{MOVEQ_7000,{3U,70U,0U}}, +{MOVEQ_7000,{3U,71U,0U}}, +{MOVEQ_7000,{3U,72U,0U}}, +{MOVEQ_7000,{3U,73U,0U}}, +{MOVEQ_7000,{3U,74U,0U}}, +{MOVEQ_7000,{3U,75U,0U}}, +{MOVEQ_7000,{3U,76U,0U}}, +{MOVEQ_7000,{3U,77U,0U}}, +{MOVEQ_7000,{3U,78U,0U}}, +{MOVEQ_7000,{3U,79U,0U}}, +{MOVEQ_7000,{3U,80U,0U}}, +{MOVEQ_7000,{3U,81U,0U}}, +{MOVEQ_7000,{3U,82U,0U}}, +{MOVEQ_7000,{3U,83U,0U}}, +{MOVEQ_7000,{3U,84U,0U}}, +{MOVEQ_7000,{3U,85U,0U}}, +{MOVEQ_7000,{3U,86U,0U}}, +{MOVEQ_7000,{3U,87U,0U}}, +{MOVEQ_7000,{3U,88U,0U}}, +{MOVEQ_7000,{3U,89U,0U}}, +{MOVEQ_7000,{3U,90U,0U}}, +{MOVEQ_7000,{3U,91U,0U}}, +{MOVEQ_7000,{3U,92U,0U}}, +{MOVEQ_7000,{3U,93U,0U}}, +{MOVEQ_7000,{3U,94U,0U}}, +{MOVEQ_7000,{3U,95U,0U}}, +{MOVEQ_7000,{3U,96U,0U}}, +{MOVEQ_7000,{3U,97U,0U}}, +{MOVEQ_7000,{3U,98U,0U}}, +{MOVEQ_7000,{3U,99U,0U}}, +{MOVEQ_7000,{3U,100U,0U}}, +{MOVEQ_7000,{3U,101U,0U}}, +{MOVEQ_7000,{3U,102U,0U}}, +{MOVEQ_7000,{3U,103U,0U}}, +{MOVEQ_7000,{3U,104U,0U}}, +{MOVEQ_7000,{3U,105U,0U}}, +{MOVEQ_7000,{3U,106U,0U}}, +{MOVEQ_7000,{3U,107U,0U}}, +{MOVEQ_7000,{3U,108U,0U}}, +{MOVEQ_7000,{3U,109U,0U}}, +{MOVEQ_7000,{3U,110U,0U}}, +{MOVEQ_7000,{3U,111U,0U}}, +{MOVEQ_7000,{3U,112U,0U}}, +{MOVEQ_7000,{3U,113U,0U}}, +{MOVEQ_7000,{3U,114U,0U}}, +{MOVEQ_7000,{3U,115U,0U}}, +{MOVEQ_7000,{3U,116U,0U}}, +{MOVEQ_7000,{3U,117U,0U}}, +{MOVEQ_7000,{3U,118U,0U}}, +{MOVEQ_7000,{3U,119U,0U}}, +{MOVEQ_7000,{3U,120U,0U}}, +{MOVEQ_7000,{3U,121U,0U}}, +{MOVEQ_7000,{3U,122U,0U}}, +{MOVEQ_7000,{3U,123U,0U}}, +{MOVEQ_7000,{3U,124U,0U}}, +{MOVEQ_7000,{3U,125U,0U}}, +{MOVEQ_7000,{3U,126U,0U}}, +{MOVEQ_7000,{3U,127U,0U}}, +{MOVEQ_7000,{3U,4294967168U,8U}}, +{MOVEQ_7000,{3U,4294967169U,8U}}, +{MOVEQ_7000,{3U,4294967170U,8U}}, +{MOVEQ_7000,{3U,4294967171U,8U}}, +{MOVEQ_7000,{3U,4294967172U,8U}}, +{MOVEQ_7000,{3U,4294967173U,8U}}, +{MOVEQ_7000,{3U,4294967174U,8U}}, +{MOVEQ_7000,{3U,4294967175U,8U}}, +{MOVEQ_7000,{3U,4294967176U,8U}}, +{MOVEQ_7000,{3U,4294967177U,8U}}, +{MOVEQ_7000,{3U,4294967178U,8U}}, +{MOVEQ_7000,{3U,4294967179U,8U}}, +{MOVEQ_7000,{3U,4294967180U,8U}}, +{MOVEQ_7000,{3U,4294967181U,8U}}, +{MOVEQ_7000,{3U,4294967182U,8U}}, +{MOVEQ_7000,{3U,4294967183U,8U}}, +{MOVEQ_7000,{3U,4294967184U,8U}}, +{MOVEQ_7000,{3U,4294967185U,8U}}, +{MOVEQ_7000,{3U,4294967186U,8U}}, +{MOVEQ_7000,{3U,4294967187U,8U}}, +{MOVEQ_7000,{3U,4294967188U,8U}}, +{MOVEQ_7000,{3U,4294967189U,8U}}, +{MOVEQ_7000,{3U,4294967190U,8U}}, +{MOVEQ_7000,{3U,4294967191U,8U}}, +{MOVEQ_7000,{3U,4294967192U,8U}}, +{MOVEQ_7000,{3U,4294967193U,8U}}, +{MOVEQ_7000,{3U,4294967194U,8U}}, +{MOVEQ_7000,{3U,4294967195U,8U}}, +{MOVEQ_7000,{3U,4294967196U,8U}}, +{MOVEQ_7000,{3U,4294967197U,8U}}, +{MOVEQ_7000,{3U,4294967198U,8U}}, +{MOVEQ_7000,{3U,4294967199U,8U}}, +{MOVEQ_7000,{3U,4294967200U,8U}}, +{MOVEQ_7000,{3U,4294967201U,8U}}, +{MOVEQ_7000,{3U,4294967202U,8U}}, +{MOVEQ_7000,{3U,4294967203U,8U}}, +{MOVEQ_7000,{3U,4294967204U,8U}}, +{MOVEQ_7000,{3U,4294967205U,8U}}, +{MOVEQ_7000,{3U,4294967206U,8U}}, +{MOVEQ_7000,{3U,4294967207U,8U}}, +{MOVEQ_7000,{3U,4294967208U,8U}}, +{MOVEQ_7000,{3U,4294967209U,8U}}, +{MOVEQ_7000,{3U,4294967210U,8U}}, +{MOVEQ_7000,{3U,4294967211U,8U}}, +{MOVEQ_7000,{3U,4294967212U,8U}}, +{MOVEQ_7000,{3U,4294967213U,8U}}, +{MOVEQ_7000,{3U,4294967214U,8U}}, +{MOVEQ_7000,{3U,4294967215U,8U}}, +{MOVEQ_7000,{3U,4294967216U,8U}}, +{MOVEQ_7000,{3U,4294967217U,8U}}, +{MOVEQ_7000,{3U,4294967218U,8U}}, +{MOVEQ_7000,{3U,4294967219U,8U}}, +{MOVEQ_7000,{3U,4294967220U,8U}}, +{MOVEQ_7000,{3U,4294967221U,8U}}, +{MOVEQ_7000,{3U,4294967222U,8U}}, +{MOVEQ_7000,{3U,4294967223U,8U}}, +{MOVEQ_7000,{3U,4294967224U,8U}}, +{MOVEQ_7000,{3U,4294967225U,8U}}, +{MOVEQ_7000,{3U,4294967226U,8U}}, +{MOVEQ_7000,{3U,4294967227U,8U}}, +{MOVEQ_7000,{3U,4294967228U,8U}}, +{MOVEQ_7000,{3U,4294967229U,8U}}, +{MOVEQ_7000,{3U,4294967230U,8U}}, +{MOVEQ_7000,{3U,4294967231U,8U}}, +{MOVEQ_7000,{3U,4294967232U,8U}}, +{MOVEQ_7000,{3U,4294967233U,8U}}, +{MOVEQ_7000,{3U,4294967234U,8U}}, +{MOVEQ_7000,{3U,4294967235U,8U}}, +{MOVEQ_7000,{3U,4294967236U,8U}}, +{MOVEQ_7000,{3U,4294967237U,8U}}, +{MOVEQ_7000,{3U,4294967238U,8U}}, +{MOVEQ_7000,{3U,4294967239U,8U}}, +{MOVEQ_7000,{3U,4294967240U,8U}}, +{MOVEQ_7000,{3U,4294967241U,8U}}, +{MOVEQ_7000,{3U,4294967242U,8U}}, +{MOVEQ_7000,{3U,4294967243U,8U}}, +{MOVEQ_7000,{3U,4294967244U,8U}}, +{MOVEQ_7000,{3U,4294967245U,8U}}, +{MOVEQ_7000,{3U,4294967246U,8U}}, +{MOVEQ_7000,{3U,4294967247U,8U}}, +{MOVEQ_7000,{3U,4294967248U,8U}}, +{MOVEQ_7000,{3U,4294967249U,8U}}, +{MOVEQ_7000,{3U,4294967250U,8U}}, +{MOVEQ_7000,{3U,4294967251U,8U}}, +{MOVEQ_7000,{3U,4294967252U,8U}}, +{MOVEQ_7000,{3U,4294967253U,8U}}, +{MOVEQ_7000,{3U,4294967254U,8U}}, +{MOVEQ_7000,{3U,4294967255U,8U}}, +{MOVEQ_7000,{3U,4294967256U,8U}}, +{MOVEQ_7000,{3U,4294967257U,8U}}, +{MOVEQ_7000,{3U,4294967258U,8U}}, +{MOVEQ_7000,{3U,4294967259U,8U}}, +{MOVEQ_7000,{3U,4294967260U,8U}}, +{MOVEQ_7000,{3U,4294967261U,8U}}, +{MOVEQ_7000,{3U,4294967262U,8U}}, +{MOVEQ_7000,{3U,4294967263U,8U}}, +{MOVEQ_7000,{3U,4294967264U,8U}}, +{MOVEQ_7000,{3U,4294967265U,8U}}, +{MOVEQ_7000,{3U,4294967266U,8U}}, +{MOVEQ_7000,{3U,4294967267U,8U}}, +{MOVEQ_7000,{3U,4294967268U,8U}}, +{MOVEQ_7000,{3U,4294967269U,8U}}, +{MOVEQ_7000,{3U,4294967270U,8U}}, +{MOVEQ_7000,{3U,4294967271U,8U}}, +{MOVEQ_7000,{3U,4294967272U,8U}}, +{MOVEQ_7000,{3U,4294967273U,8U}}, +{MOVEQ_7000,{3U,4294967274U,8U}}, +{MOVEQ_7000,{3U,4294967275U,8U}}, +{MOVEQ_7000,{3U,4294967276U,8U}}, +{MOVEQ_7000,{3U,4294967277U,8U}}, +{MOVEQ_7000,{3U,4294967278U,8U}}, +{MOVEQ_7000,{3U,4294967279U,8U}}, +{MOVEQ_7000,{3U,4294967280U,8U}}, +{MOVEQ_7000,{3U,4294967281U,8U}}, +{MOVEQ_7000,{3U,4294967282U,8U}}, +{MOVEQ_7000,{3U,4294967283U,8U}}, +{MOVEQ_7000,{3U,4294967284U,8U}}, +{MOVEQ_7000,{3U,4294967285U,8U}}, +{MOVEQ_7000,{3U,4294967286U,8U}}, +{MOVEQ_7000,{3U,4294967287U,8U}}, +{MOVEQ_7000,{3U,4294967288U,8U}}, +{MOVEQ_7000,{3U,4294967289U,8U}}, +{MOVEQ_7000,{3U,4294967290U,8U}}, +{MOVEQ_7000,{3U,4294967291U,8U}}, +{MOVEQ_7000,{3U,4294967292U,8U}}, +{MOVEQ_7000,{3U,4294967293U,8U}}, +{MOVEQ_7000,{3U,4294967294U,8U}}, +{MOVEQ_7000,{3U,4294967295U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEQ_7000,{4U,0U,4U}}, +{MOVEQ_7000,{4U,1U,0U}}, +{MOVEQ_7000,{4U,2U,0U}}, +{MOVEQ_7000,{4U,3U,0U}}, +{MOVEQ_7000,{4U,4U,0U}}, +{MOVEQ_7000,{4U,5U,0U}}, +{MOVEQ_7000,{4U,6U,0U}}, +{MOVEQ_7000,{4U,7U,0U}}, +{MOVEQ_7000,{4U,8U,0U}}, +{MOVEQ_7000,{4U,9U,0U}}, +{MOVEQ_7000,{4U,10U,0U}}, +{MOVEQ_7000,{4U,11U,0U}}, +{MOVEQ_7000,{4U,12U,0U}}, +{MOVEQ_7000,{4U,13U,0U}}, +{MOVEQ_7000,{4U,14U,0U}}, +{MOVEQ_7000,{4U,15U,0U}}, +{MOVEQ_7000,{4U,16U,0U}}, +{MOVEQ_7000,{4U,17U,0U}}, +{MOVEQ_7000,{4U,18U,0U}}, +{MOVEQ_7000,{4U,19U,0U}}, +{MOVEQ_7000,{4U,20U,0U}}, +{MOVEQ_7000,{4U,21U,0U}}, +{MOVEQ_7000,{4U,22U,0U}}, +{MOVEQ_7000,{4U,23U,0U}}, +{MOVEQ_7000,{4U,24U,0U}}, +{MOVEQ_7000,{4U,25U,0U}}, +{MOVEQ_7000,{4U,26U,0U}}, +{MOVEQ_7000,{4U,27U,0U}}, +{MOVEQ_7000,{4U,28U,0U}}, +{MOVEQ_7000,{4U,29U,0U}}, +{MOVEQ_7000,{4U,30U,0U}}, +{MOVEQ_7000,{4U,31U,0U}}, +{MOVEQ_7000,{4U,32U,0U}}, +{MOVEQ_7000,{4U,33U,0U}}, +{MOVEQ_7000,{4U,34U,0U}}, +{MOVEQ_7000,{4U,35U,0U}}, +{MOVEQ_7000,{4U,36U,0U}}, +{MOVEQ_7000,{4U,37U,0U}}, +{MOVEQ_7000,{4U,38U,0U}}, +{MOVEQ_7000,{4U,39U,0U}}, +{MOVEQ_7000,{4U,40U,0U}}, +{MOVEQ_7000,{4U,41U,0U}}, +{MOVEQ_7000,{4U,42U,0U}}, +{MOVEQ_7000,{4U,43U,0U}}, +{MOVEQ_7000,{4U,44U,0U}}, +{MOVEQ_7000,{4U,45U,0U}}, +{MOVEQ_7000,{4U,46U,0U}}, +{MOVEQ_7000,{4U,47U,0U}}, +{MOVEQ_7000,{4U,48U,0U}}, +{MOVEQ_7000,{4U,49U,0U}}, +{MOVEQ_7000,{4U,50U,0U}}, +{MOVEQ_7000,{4U,51U,0U}}, +{MOVEQ_7000,{4U,52U,0U}}, +{MOVEQ_7000,{4U,53U,0U}}, +{MOVEQ_7000,{4U,54U,0U}}, +{MOVEQ_7000,{4U,55U,0U}}, +{MOVEQ_7000,{4U,56U,0U}}, +{MOVEQ_7000,{4U,57U,0U}}, +{MOVEQ_7000,{4U,58U,0U}}, +{MOVEQ_7000,{4U,59U,0U}}, +{MOVEQ_7000,{4U,60U,0U}}, +{MOVEQ_7000,{4U,61U,0U}}, +{MOVEQ_7000,{4U,62U,0U}}, +{MOVEQ_7000,{4U,63U,0U}}, +{MOVEQ_7000,{4U,64U,0U}}, +{MOVEQ_7000,{4U,65U,0U}}, +{MOVEQ_7000,{4U,66U,0U}}, +{MOVEQ_7000,{4U,67U,0U}}, +{MOVEQ_7000,{4U,68U,0U}}, +{MOVEQ_7000,{4U,69U,0U}}, +{MOVEQ_7000,{4U,70U,0U}}, +{MOVEQ_7000,{4U,71U,0U}}, +{MOVEQ_7000,{4U,72U,0U}}, +{MOVEQ_7000,{4U,73U,0U}}, +{MOVEQ_7000,{4U,74U,0U}}, +{MOVEQ_7000,{4U,75U,0U}}, +{MOVEQ_7000,{4U,76U,0U}}, +{MOVEQ_7000,{4U,77U,0U}}, +{MOVEQ_7000,{4U,78U,0U}}, +{MOVEQ_7000,{4U,79U,0U}}, +{MOVEQ_7000,{4U,80U,0U}}, +{MOVEQ_7000,{4U,81U,0U}}, +{MOVEQ_7000,{4U,82U,0U}}, +{MOVEQ_7000,{4U,83U,0U}}, +{MOVEQ_7000,{4U,84U,0U}}, +{MOVEQ_7000,{4U,85U,0U}}, +{MOVEQ_7000,{4U,86U,0U}}, +{MOVEQ_7000,{4U,87U,0U}}, +{MOVEQ_7000,{4U,88U,0U}}, +{MOVEQ_7000,{4U,89U,0U}}, +{MOVEQ_7000,{4U,90U,0U}}, +{MOVEQ_7000,{4U,91U,0U}}, +{MOVEQ_7000,{4U,92U,0U}}, +{MOVEQ_7000,{4U,93U,0U}}, +{MOVEQ_7000,{4U,94U,0U}}, +{MOVEQ_7000,{4U,95U,0U}}, +{MOVEQ_7000,{4U,96U,0U}}, +{MOVEQ_7000,{4U,97U,0U}}, +{MOVEQ_7000,{4U,98U,0U}}, +{MOVEQ_7000,{4U,99U,0U}}, +{MOVEQ_7000,{4U,100U,0U}}, +{MOVEQ_7000,{4U,101U,0U}}, +{MOVEQ_7000,{4U,102U,0U}}, +{MOVEQ_7000,{4U,103U,0U}}, +{MOVEQ_7000,{4U,104U,0U}}, +{MOVEQ_7000,{4U,105U,0U}}, +{MOVEQ_7000,{4U,106U,0U}}, +{MOVEQ_7000,{4U,107U,0U}}, +{MOVEQ_7000,{4U,108U,0U}}, +{MOVEQ_7000,{4U,109U,0U}}, +{MOVEQ_7000,{4U,110U,0U}}, +{MOVEQ_7000,{4U,111U,0U}}, +{MOVEQ_7000,{4U,112U,0U}}, +{MOVEQ_7000,{4U,113U,0U}}, +{MOVEQ_7000,{4U,114U,0U}}, +{MOVEQ_7000,{4U,115U,0U}}, +{MOVEQ_7000,{4U,116U,0U}}, +{MOVEQ_7000,{4U,117U,0U}}, +{MOVEQ_7000,{4U,118U,0U}}, +{MOVEQ_7000,{4U,119U,0U}}, +{MOVEQ_7000,{4U,120U,0U}}, +{MOVEQ_7000,{4U,121U,0U}}, +{MOVEQ_7000,{4U,122U,0U}}, +{MOVEQ_7000,{4U,123U,0U}}, +{MOVEQ_7000,{4U,124U,0U}}, +{MOVEQ_7000,{4U,125U,0U}}, +{MOVEQ_7000,{4U,126U,0U}}, +{MOVEQ_7000,{4U,127U,0U}}, +{MOVEQ_7000,{4U,4294967168U,8U}}, +{MOVEQ_7000,{4U,4294967169U,8U}}, +{MOVEQ_7000,{4U,4294967170U,8U}}, +{MOVEQ_7000,{4U,4294967171U,8U}}, +{MOVEQ_7000,{4U,4294967172U,8U}}, +{MOVEQ_7000,{4U,4294967173U,8U}}, +{MOVEQ_7000,{4U,4294967174U,8U}}, +{MOVEQ_7000,{4U,4294967175U,8U}}, +{MOVEQ_7000,{4U,4294967176U,8U}}, +{MOVEQ_7000,{4U,4294967177U,8U}}, +{MOVEQ_7000,{4U,4294967178U,8U}}, +{MOVEQ_7000,{4U,4294967179U,8U}}, +{MOVEQ_7000,{4U,4294967180U,8U}}, +{MOVEQ_7000,{4U,4294967181U,8U}}, +{MOVEQ_7000,{4U,4294967182U,8U}}, +{MOVEQ_7000,{4U,4294967183U,8U}}, +{MOVEQ_7000,{4U,4294967184U,8U}}, +{MOVEQ_7000,{4U,4294967185U,8U}}, +{MOVEQ_7000,{4U,4294967186U,8U}}, +{MOVEQ_7000,{4U,4294967187U,8U}}, +{MOVEQ_7000,{4U,4294967188U,8U}}, +{MOVEQ_7000,{4U,4294967189U,8U}}, +{MOVEQ_7000,{4U,4294967190U,8U}}, +{MOVEQ_7000,{4U,4294967191U,8U}}, +{MOVEQ_7000,{4U,4294967192U,8U}}, +{MOVEQ_7000,{4U,4294967193U,8U}}, +{MOVEQ_7000,{4U,4294967194U,8U}}, +{MOVEQ_7000,{4U,4294967195U,8U}}, +{MOVEQ_7000,{4U,4294967196U,8U}}, +{MOVEQ_7000,{4U,4294967197U,8U}}, +{MOVEQ_7000,{4U,4294967198U,8U}}, +{MOVEQ_7000,{4U,4294967199U,8U}}, +{MOVEQ_7000,{4U,4294967200U,8U}}, +{MOVEQ_7000,{4U,4294967201U,8U}}, +{MOVEQ_7000,{4U,4294967202U,8U}}, +{MOVEQ_7000,{4U,4294967203U,8U}}, +{MOVEQ_7000,{4U,4294967204U,8U}}, +{MOVEQ_7000,{4U,4294967205U,8U}}, +{MOVEQ_7000,{4U,4294967206U,8U}}, +{MOVEQ_7000,{4U,4294967207U,8U}}, +{MOVEQ_7000,{4U,4294967208U,8U}}, +{MOVEQ_7000,{4U,4294967209U,8U}}, +{MOVEQ_7000,{4U,4294967210U,8U}}, +{MOVEQ_7000,{4U,4294967211U,8U}}, +{MOVEQ_7000,{4U,4294967212U,8U}}, +{MOVEQ_7000,{4U,4294967213U,8U}}, +{MOVEQ_7000,{4U,4294967214U,8U}}, +{MOVEQ_7000,{4U,4294967215U,8U}}, +{MOVEQ_7000,{4U,4294967216U,8U}}, +{MOVEQ_7000,{4U,4294967217U,8U}}, +{MOVEQ_7000,{4U,4294967218U,8U}}, +{MOVEQ_7000,{4U,4294967219U,8U}}, +{MOVEQ_7000,{4U,4294967220U,8U}}, +{MOVEQ_7000,{4U,4294967221U,8U}}, +{MOVEQ_7000,{4U,4294967222U,8U}}, +{MOVEQ_7000,{4U,4294967223U,8U}}, +{MOVEQ_7000,{4U,4294967224U,8U}}, +{MOVEQ_7000,{4U,4294967225U,8U}}, +{MOVEQ_7000,{4U,4294967226U,8U}}, +{MOVEQ_7000,{4U,4294967227U,8U}}, +{MOVEQ_7000,{4U,4294967228U,8U}}, +{MOVEQ_7000,{4U,4294967229U,8U}}, +{MOVEQ_7000,{4U,4294967230U,8U}}, +{MOVEQ_7000,{4U,4294967231U,8U}}, +{MOVEQ_7000,{4U,4294967232U,8U}}, +{MOVEQ_7000,{4U,4294967233U,8U}}, +{MOVEQ_7000,{4U,4294967234U,8U}}, +{MOVEQ_7000,{4U,4294967235U,8U}}, +{MOVEQ_7000,{4U,4294967236U,8U}}, +{MOVEQ_7000,{4U,4294967237U,8U}}, +{MOVEQ_7000,{4U,4294967238U,8U}}, +{MOVEQ_7000,{4U,4294967239U,8U}}, +{MOVEQ_7000,{4U,4294967240U,8U}}, +{MOVEQ_7000,{4U,4294967241U,8U}}, +{MOVEQ_7000,{4U,4294967242U,8U}}, +{MOVEQ_7000,{4U,4294967243U,8U}}, +{MOVEQ_7000,{4U,4294967244U,8U}}, +{MOVEQ_7000,{4U,4294967245U,8U}}, +{MOVEQ_7000,{4U,4294967246U,8U}}, +{MOVEQ_7000,{4U,4294967247U,8U}}, +{MOVEQ_7000,{4U,4294967248U,8U}}, +{MOVEQ_7000,{4U,4294967249U,8U}}, +{MOVEQ_7000,{4U,4294967250U,8U}}, +{MOVEQ_7000,{4U,4294967251U,8U}}, +{MOVEQ_7000,{4U,4294967252U,8U}}, +{MOVEQ_7000,{4U,4294967253U,8U}}, +{MOVEQ_7000,{4U,4294967254U,8U}}, +{MOVEQ_7000,{4U,4294967255U,8U}}, +{MOVEQ_7000,{4U,4294967256U,8U}}, +{MOVEQ_7000,{4U,4294967257U,8U}}, +{MOVEQ_7000,{4U,4294967258U,8U}}, +{MOVEQ_7000,{4U,4294967259U,8U}}, +{MOVEQ_7000,{4U,4294967260U,8U}}, +{MOVEQ_7000,{4U,4294967261U,8U}}, +{MOVEQ_7000,{4U,4294967262U,8U}}, +{MOVEQ_7000,{4U,4294967263U,8U}}, +{MOVEQ_7000,{4U,4294967264U,8U}}, +{MOVEQ_7000,{4U,4294967265U,8U}}, +{MOVEQ_7000,{4U,4294967266U,8U}}, +{MOVEQ_7000,{4U,4294967267U,8U}}, +{MOVEQ_7000,{4U,4294967268U,8U}}, +{MOVEQ_7000,{4U,4294967269U,8U}}, +{MOVEQ_7000,{4U,4294967270U,8U}}, +{MOVEQ_7000,{4U,4294967271U,8U}}, +{MOVEQ_7000,{4U,4294967272U,8U}}, +{MOVEQ_7000,{4U,4294967273U,8U}}, +{MOVEQ_7000,{4U,4294967274U,8U}}, +{MOVEQ_7000,{4U,4294967275U,8U}}, +{MOVEQ_7000,{4U,4294967276U,8U}}, +{MOVEQ_7000,{4U,4294967277U,8U}}, +{MOVEQ_7000,{4U,4294967278U,8U}}, +{MOVEQ_7000,{4U,4294967279U,8U}}, +{MOVEQ_7000,{4U,4294967280U,8U}}, +{MOVEQ_7000,{4U,4294967281U,8U}}, +{MOVEQ_7000,{4U,4294967282U,8U}}, +{MOVEQ_7000,{4U,4294967283U,8U}}, +{MOVEQ_7000,{4U,4294967284U,8U}}, +{MOVEQ_7000,{4U,4294967285U,8U}}, +{MOVEQ_7000,{4U,4294967286U,8U}}, +{MOVEQ_7000,{4U,4294967287U,8U}}, +{MOVEQ_7000,{4U,4294967288U,8U}}, +{MOVEQ_7000,{4U,4294967289U,8U}}, +{MOVEQ_7000,{4U,4294967290U,8U}}, +{MOVEQ_7000,{4U,4294967291U,8U}}, +{MOVEQ_7000,{4U,4294967292U,8U}}, +{MOVEQ_7000,{4U,4294967293U,8U}}, +{MOVEQ_7000,{4U,4294967294U,8U}}, +{MOVEQ_7000,{4U,4294967295U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEQ_7000,{5U,0U,4U}}, +{MOVEQ_7000,{5U,1U,0U}}, +{MOVEQ_7000,{5U,2U,0U}}, +{MOVEQ_7000,{5U,3U,0U}}, +{MOVEQ_7000,{5U,4U,0U}}, +{MOVEQ_7000,{5U,5U,0U}}, +{MOVEQ_7000,{5U,6U,0U}}, +{MOVEQ_7000,{5U,7U,0U}}, +{MOVEQ_7000,{5U,8U,0U}}, +{MOVEQ_7000,{5U,9U,0U}}, +{MOVEQ_7000,{5U,10U,0U}}, +{MOVEQ_7000,{5U,11U,0U}}, +{MOVEQ_7000,{5U,12U,0U}}, +{MOVEQ_7000,{5U,13U,0U}}, +{MOVEQ_7000,{5U,14U,0U}}, +{MOVEQ_7000,{5U,15U,0U}}, +{MOVEQ_7000,{5U,16U,0U}}, +{MOVEQ_7000,{5U,17U,0U}}, +{MOVEQ_7000,{5U,18U,0U}}, +{MOVEQ_7000,{5U,19U,0U}}, +{MOVEQ_7000,{5U,20U,0U}}, +{MOVEQ_7000,{5U,21U,0U}}, +{MOVEQ_7000,{5U,22U,0U}}, +{MOVEQ_7000,{5U,23U,0U}}, +{MOVEQ_7000,{5U,24U,0U}}, +{MOVEQ_7000,{5U,25U,0U}}, +{MOVEQ_7000,{5U,26U,0U}}, +{MOVEQ_7000,{5U,27U,0U}}, +{MOVEQ_7000,{5U,28U,0U}}, +{MOVEQ_7000,{5U,29U,0U}}, +{MOVEQ_7000,{5U,30U,0U}}, +{MOVEQ_7000,{5U,31U,0U}}, +{MOVEQ_7000,{5U,32U,0U}}, +{MOVEQ_7000,{5U,33U,0U}}, +{MOVEQ_7000,{5U,34U,0U}}, +{MOVEQ_7000,{5U,35U,0U}}, +{MOVEQ_7000,{5U,36U,0U}}, +{MOVEQ_7000,{5U,37U,0U}}, +{MOVEQ_7000,{5U,38U,0U}}, +{MOVEQ_7000,{5U,39U,0U}}, +{MOVEQ_7000,{5U,40U,0U}}, +{MOVEQ_7000,{5U,41U,0U}}, +{MOVEQ_7000,{5U,42U,0U}}, +{MOVEQ_7000,{5U,43U,0U}}, +{MOVEQ_7000,{5U,44U,0U}}, +{MOVEQ_7000,{5U,45U,0U}}, +{MOVEQ_7000,{5U,46U,0U}}, +{MOVEQ_7000,{5U,47U,0U}}, +{MOVEQ_7000,{5U,48U,0U}}, +{MOVEQ_7000,{5U,49U,0U}}, +{MOVEQ_7000,{5U,50U,0U}}, +{MOVEQ_7000,{5U,51U,0U}}, +{MOVEQ_7000,{5U,52U,0U}}, +{MOVEQ_7000,{5U,53U,0U}}, +{MOVEQ_7000,{5U,54U,0U}}, +{MOVEQ_7000,{5U,55U,0U}}, +{MOVEQ_7000,{5U,56U,0U}}, +{MOVEQ_7000,{5U,57U,0U}}, +{MOVEQ_7000,{5U,58U,0U}}, +{MOVEQ_7000,{5U,59U,0U}}, +{MOVEQ_7000,{5U,60U,0U}}, +{MOVEQ_7000,{5U,61U,0U}}, +{MOVEQ_7000,{5U,62U,0U}}, +{MOVEQ_7000,{5U,63U,0U}}, +{MOVEQ_7000,{5U,64U,0U}}, +{MOVEQ_7000,{5U,65U,0U}}, +{MOVEQ_7000,{5U,66U,0U}}, +{MOVEQ_7000,{5U,67U,0U}}, +{MOVEQ_7000,{5U,68U,0U}}, +{MOVEQ_7000,{5U,69U,0U}}, +{MOVEQ_7000,{5U,70U,0U}}, +{MOVEQ_7000,{5U,71U,0U}}, +{MOVEQ_7000,{5U,72U,0U}}, +{MOVEQ_7000,{5U,73U,0U}}, +{MOVEQ_7000,{5U,74U,0U}}, +{MOVEQ_7000,{5U,75U,0U}}, +{MOVEQ_7000,{5U,76U,0U}}, +{MOVEQ_7000,{5U,77U,0U}}, +{MOVEQ_7000,{5U,78U,0U}}, +{MOVEQ_7000,{5U,79U,0U}}, +{MOVEQ_7000,{5U,80U,0U}}, +{MOVEQ_7000,{5U,81U,0U}}, +{MOVEQ_7000,{5U,82U,0U}}, +{MOVEQ_7000,{5U,83U,0U}}, +{MOVEQ_7000,{5U,84U,0U}}, +{MOVEQ_7000,{5U,85U,0U}}, +{MOVEQ_7000,{5U,86U,0U}}, +{MOVEQ_7000,{5U,87U,0U}}, +{MOVEQ_7000,{5U,88U,0U}}, +{MOVEQ_7000,{5U,89U,0U}}, +{MOVEQ_7000,{5U,90U,0U}}, +{MOVEQ_7000,{5U,91U,0U}}, +{MOVEQ_7000,{5U,92U,0U}}, +{MOVEQ_7000,{5U,93U,0U}}, +{MOVEQ_7000,{5U,94U,0U}}, +{MOVEQ_7000,{5U,95U,0U}}, +{MOVEQ_7000,{5U,96U,0U}}, +{MOVEQ_7000,{5U,97U,0U}}, +{MOVEQ_7000,{5U,98U,0U}}, +{MOVEQ_7000,{5U,99U,0U}}, +{MOVEQ_7000,{5U,100U,0U}}, +{MOVEQ_7000,{5U,101U,0U}}, +{MOVEQ_7000,{5U,102U,0U}}, +{MOVEQ_7000,{5U,103U,0U}}, +{MOVEQ_7000,{5U,104U,0U}}, +{MOVEQ_7000,{5U,105U,0U}}, +{MOVEQ_7000,{5U,106U,0U}}, +{MOVEQ_7000,{5U,107U,0U}}, +{MOVEQ_7000,{5U,108U,0U}}, +{MOVEQ_7000,{5U,109U,0U}}, +{MOVEQ_7000,{5U,110U,0U}}, +{MOVEQ_7000,{5U,111U,0U}}, +{MOVEQ_7000,{5U,112U,0U}}, +{MOVEQ_7000,{5U,113U,0U}}, +{MOVEQ_7000,{5U,114U,0U}}, +{MOVEQ_7000,{5U,115U,0U}}, +{MOVEQ_7000,{5U,116U,0U}}, +{MOVEQ_7000,{5U,117U,0U}}, +{MOVEQ_7000,{5U,118U,0U}}, +{MOVEQ_7000,{5U,119U,0U}}, +{MOVEQ_7000,{5U,120U,0U}}, +{MOVEQ_7000,{5U,121U,0U}}, +{MOVEQ_7000,{5U,122U,0U}}, +{MOVEQ_7000,{5U,123U,0U}}, +{MOVEQ_7000,{5U,124U,0U}}, +{MOVEQ_7000,{5U,125U,0U}}, +{MOVEQ_7000,{5U,126U,0U}}, +{MOVEQ_7000,{5U,127U,0U}}, +{MOVEQ_7000,{5U,4294967168U,8U}}, +{MOVEQ_7000,{5U,4294967169U,8U}}, +{MOVEQ_7000,{5U,4294967170U,8U}}, +{MOVEQ_7000,{5U,4294967171U,8U}}, +{MOVEQ_7000,{5U,4294967172U,8U}}, +{MOVEQ_7000,{5U,4294967173U,8U}}, +{MOVEQ_7000,{5U,4294967174U,8U}}, +{MOVEQ_7000,{5U,4294967175U,8U}}, +{MOVEQ_7000,{5U,4294967176U,8U}}, +{MOVEQ_7000,{5U,4294967177U,8U}}, +{MOVEQ_7000,{5U,4294967178U,8U}}, +{MOVEQ_7000,{5U,4294967179U,8U}}, +{MOVEQ_7000,{5U,4294967180U,8U}}, +{MOVEQ_7000,{5U,4294967181U,8U}}, +{MOVEQ_7000,{5U,4294967182U,8U}}, +{MOVEQ_7000,{5U,4294967183U,8U}}, +{MOVEQ_7000,{5U,4294967184U,8U}}, +{MOVEQ_7000,{5U,4294967185U,8U}}, +{MOVEQ_7000,{5U,4294967186U,8U}}, +{MOVEQ_7000,{5U,4294967187U,8U}}, +{MOVEQ_7000,{5U,4294967188U,8U}}, +{MOVEQ_7000,{5U,4294967189U,8U}}, +{MOVEQ_7000,{5U,4294967190U,8U}}, +{MOVEQ_7000,{5U,4294967191U,8U}}, +{MOVEQ_7000,{5U,4294967192U,8U}}, +{MOVEQ_7000,{5U,4294967193U,8U}}, +{MOVEQ_7000,{5U,4294967194U,8U}}, +{MOVEQ_7000,{5U,4294967195U,8U}}, +{MOVEQ_7000,{5U,4294967196U,8U}}, +{MOVEQ_7000,{5U,4294967197U,8U}}, +{MOVEQ_7000,{5U,4294967198U,8U}}, +{MOVEQ_7000,{5U,4294967199U,8U}}, +{MOVEQ_7000,{5U,4294967200U,8U}}, +{MOVEQ_7000,{5U,4294967201U,8U}}, +{MOVEQ_7000,{5U,4294967202U,8U}}, +{MOVEQ_7000,{5U,4294967203U,8U}}, +{MOVEQ_7000,{5U,4294967204U,8U}}, +{MOVEQ_7000,{5U,4294967205U,8U}}, +{MOVEQ_7000,{5U,4294967206U,8U}}, +{MOVEQ_7000,{5U,4294967207U,8U}}, +{MOVEQ_7000,{5U,4294967208U,8U}}, +{MOVEQ_7000,{5U,4294967209U,8U}}, +{MOVEQ_7000,{5U,4294967210U,8U}}, +{MOVEQ_7000,{5U,4294967211U,8U}}, +{MOVEQ_7000,{5U,4294967212U,8U}}, +{MOVEQ_7000,{5U,4294967213U,8U}}, +{MOVEQ_7000,{5U,4294967214U,8U}}, +{MOVEQ_7000,{5U,4294967215U,8U}}, +{MOVEQ_7000,{5U,4294967216U,8U}}, +{MOVEQ_7000,{5U,4294967217U,8U}}, +{MOVEQ_7000,{5U,4294967218U,8U}}, +{MOVEQ_7000,{5U,4294967219U,8U}}, +{MOVEQ_7000,{5U,4294967220U,8U}}, +{MOVEQ_7000,{5U,4294967221U,8U}}, +{MOVEQ_7000,{5U,4294967222U,8U}}, +{MOVEQ_7000,{5U,4294967223U,8U}}, +{MOVEQ_7000,{5U,4294967224U,8U}}, +{MOVEQ_7000,{5U,4294967225U,8U}}, +{MOVEQ_7000,{5U,4294967226U,8U}}, +{MOVEQ_7000,{5U,4294967227U,8U}}, +{MOVEQ_7000,{5U,4294967228U,8U}}, +{MOVEQ_7000,{5U,4294967229U,8U}}, +{MOVEQ_7000,{5U,4294967230U,8U}}, +{MOVEQ_7000,{5U,4294967231U,8U}}, +{MOVEQ_7000,{5U,4294967232U,8U}}, +{MOVEQ_7000,{5U,4294967233U,8U}}, +{MOVEQ_7000,{5U,4294967234U,8U}}, +{MOVEQ_7000,{5U,4294967235U,8U}}, +{MOVEQ_7000,{5U,4294967236U,8U}}, +{MOVEQ_7000,{5U,4294967237U,8U}}, +{MOVEQ_7000,{5U,4294967238U,8U}}, +{MOVEQ_7000,{5U,4294967239U,8U}}, +{MOVEQ_7000,{5U,4294967240U,8U}}, +{MOVEQ_7000,{5U,4294967241U,8U}}, +{MOVEQ_7000,{5U,4294967242U,8U}}, +{MOVEQ_7000,{5U,4294967243U,8U}}, +{MOVEQ_7000,{5U,4294967244U,8U}}, +{MOVEQ_7000,{5U,4294967245U,8U}}, +{MOVEQ_7000,{5U,4294967246U,8U}}, +{MOVEQ_7000,{5U,4294967247U,8U}}, +{MOVEQ_7000,{5U,4294967248U,8U}}, +{MOVEQ_7000,{5U,4294967249U,8U}}, +{MOVEQ_7000,{5U,4294967250U,8U}}, +{MOVEQ_7000,{5U,4294967251U,8U}}, +{MOVEQ_7000,{5U,4294967252U,8U}}, +{MOVEQ_7000,{5U,4294967253U,8U}}, +{MOVEQ_7000,{5U,4294967254U,8U}}, +{MOVEQ_7000,{5U,4294967255U,8U}}, +{MOVEQ_7000,{5U,4294967256U,8U}}, +{MOVEQ_7000,{5U,4294967257U,8U}}, +{MOVEQ_7000,{5U,4294967258U,8U}}, +{MOVEQ_7000,{5U,4294967259U,8U}}, +{MOVEQ_7000,{5U,4294967260U,8U}}, +{MOVEQ_7000,{5U,4294967261U,8U}}, +{MOVEQ_7000,{5U,4294967262U,8U}}, +{MOVEQ_7000,{5U,4294967263U,8U}}, +{MOVEQ_7000,{5U,4294967264U,8U}}, +{MOVEQ_7000,{5U,4294967265U,8U}}, +{MOVEQ_7000,{5U,4294967266U,8U}}, +{MOVEQ_7000,{5U,4294967267U,8U}}, +{MOVEQ_7000,{5U,4294967268U,8U}}, +{MOVEQ_7000,{5U,4294967269U,8U}}, +{MOVEQ_7000,{5U,4294967270U,8U}}, +{MOVEQ_7000,{5U,4294967271U,8U}}, +{MOVEQ_7000,{5U,4294967272U,8U}}, +{MOVEQ_7000,{5U,4294967273U,8U}}, +{MOVEQ_7000,{5U,4294967274U,8U}}, +{MOVEQ_7000,{5U,4294967275U,8U}}, +{MOVEQ_7000,{5U,4294967276U,8U}}, +{MOVEQ_7000,{5U,4294967277U,8U}}, +{MOVEQ_7000,{5U,4294967278U,8U}}, +{MOVEQ_7000,{5U,4294967279U,8U}}, +{MOVEQ_7000,{5U,4294967280U,8U}}, +{MOVEQ_7000,{5U,4294967281U,8U}}, +{MOVEQ_7000,{5U,4294967282U,8U}}, +{MOVEQ_7000,{5U,4294967283U,8U}}, +{MOVEQ_7000,{5U,4294967284U,8U}}, +{MOVEQ_7000,{5U,4294967285U,8U}}, +{MOVEQ_7000,{5U,4294967286U,8U}}, +{MOVEQ_7000,{5U,4294967287U,8U}}, +{MOVEQ_7000,{5U,4294967288U,8U}}, +{MOVEQ_7000,{5U,4294967289U,8U}}, +{MOVEQ_7000,{5U,4294967290U,8U}}, +{MOVEQ_7000,{5U,4294967291U,8U}}, +{MOVEQ_7000,{5U,4294967292U,8U}}, +{MOVEQ_7000,{5U,4294967293U,8U}}, +{MOVEQ_7000,{5U,4294967294U,8U}}, +{MOVEQ_7000,{5U,4294967295U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEQ_7000,{6U,0U,4U}}, +{MOVEQ_7000,{6U,1U,0U}}, +{MOVEQ_7000,{6U,2U,0U}}, +{MOVEQ_7000,{6U,3U,0U}}, +{MOVEQ_7000,{6U,4U,0U}}, +{MOVEQ_7000,{6U,5U,0U}}, +{MOVEQ_7000,{6U,6U,0U}}, +{MOVEQ_7000,{6U,7U,0U}}, +{MOVEQ_7000,{6U,8U,0U}}, +{MOVEQ_7000,{6U,9U,0U}}, +{MOVEQ_7000,{6U,10U,0U}}, +{MOVEQ_7000,{6U,11U,0U}}, +{MOVEQ_7000,{6U,12U,0U}}, +{MOVEQ_7000,{6U,13U,0U}}, +{MOVEQ_7000,{6U,14U,0U}}, +{MOVEQ_7000,{6U,15U,0U}}, +{MOVEQ_7000,{6U,16U,0U}}, +{MOVEQ_7000,{6U,17U,0U}}, +{MOVEQ_7000,{6U,18U,0U}}, +{MOVEQ_7000,{6U,19U,0U}}, +{MOVEQ_7000,{6U,20U,0U}}, +{MOVEQ_7000,{6U,21U,0U}}, +{MOVEQ_7000,{6U,22U,0U}}, +{MOVEQ_7000,{6U,23U,0U}}, +{MOVEQ_7000,{6U,24U,0U}}, +{MOVEQ_7000,{6U,25U,0U}}, +{MOVEQ_7000,{6U,26U,0U}}, +{MOVEQ_7000,{6U,27U,0U}}, +{MOVEQ_7000,{6U,28U,0U}}, +{MOVEQ_7000,{6U,29U,0U}}, +{MOVEQ_7000,{6U,30U,0U}}, +{MOVEQ_7000,{6U,31U,0U}}, +{MOVEQ_7000,{6U,32U,0U}}, +{MOVEQ_7000,{6U,33U,0U}}, +{MOVEQ_7000,{6U,34U,0U}}, +{MOVEQ_7000,{6U,35U,0U}}, +{MOVEQ_7000,{6U,36U,0U}}, +{MOVEQ_7000,{6U,37U,0U}}, +{MOVEQ_7000,{6U,38U,0U}}, +{MOVEQ_7000,{6U,39U,0U}}, +{MOVEQ_7000,{6U,40U,0U}}, +{MOVEQ_7000,{6U,41U,0U}}, +{MOVEQ_7000,{6U,42U,0U}}, +{MOVEQ_7000,{6U,43U,0U}}, +{MOVEQ_7000,{6U,44U,0U}}, +{MOVEQ_7000,{6U,45U,0U}}, +{MOVEQ_7000,{6U,46U,0U}}, +{MOVEQ_7000,{6U,47U,0U}}, +{MOVEQ_7000,{6U,48U,0U}}, +{MOVEQ_7000,{6U,49U,0U}}, +{MOVEQ_7000,{6U,50U,0U}}, +{MOVEQ_7000,{6U,51U,0U}}, +{MOVEQ_7000,{6U,52U,0U}}, +{MOVEQ_7000,{6U,53U,0U}}, +{MOVEQ_7000,{6U,54U,0U}}, +{MOVEQ_7000,{6U,55U,0U}}, +{MOVEQ_7000,{6U,56U,0U}}, +{MOVEQ_7000,{6U,57U,0U}}, +{MOVEQ_7000,{6U,58U,0U}}, +{MOVEQ_7000,{6U,59U,0U}}, +{MOVEQ_7000,{6U,60U,0U}}, +{MOVEQ_7000,{6U,61U,0U}}, +{MOVEQ_7000,{6U,62U,0U}}, +{MOVEQ_7000,{6U,63U,0U}}, +{MOVEQ_7000,{6U,64U,0U}}, +{MOVEQ_7000,{6U,65U,0U}}, +{MOVEQ_7000,{6U,66U,0U}}, +{MOVEQ_7000,{6U,67U,0U}}, +{MOVEQ_7000,{6U,68U,0U}}, +{MOVEQ_7000,{6U,69U,0U}}, +{MOVEQ_7000,{6U,70U,0U}}, +{MOVEQ_7000,{6U,71U,0U}}, +{MOVEQ_7000,{6U,72U,0U}}, +{MOVEQ_7000,{6U,73U,0U}}, +{MOVEQ_7000,{6U,74U,0U}}, +{MOVEQ_7000,{6U,75U,0U}}, +{MOVEQ_7000,{6U,76U,0U}}, +{MOVEQ_7000,{6U,77U,0U}}, +{MOVEQ_7000,{6U,78U,0U}}, +{MOVEQ_7000,{6U,79U,0U}}, +{MOVEQ_7000,{6U,80U,0U}}, +{MOVEQ_7000,{6U,81U,0U}}, +{MOVEQ_7000,{6U,82U,0U}}, +{MOVEQ_7000,{6U,83U,0U}}, +{MOVEQ_7000,{6U,84U,0U}}, +{MOVEQ_7000,{6U,85U,0U}}, +{MOVEQ_7000,{6U,86U,0U}}, +{MOVEQ_7000,{6U,87U,0U}}, +{MOVEQ_7000,{6U,88U,0U}}, +{MOVEQ_7000,{6U,89U,0U}}, +{MOVEQ_7000,{6U,90U,0U}}, +{MOVEQ_7000,{6U,91U,0U}}, +{MOVEQ_7000,{6U,92U,0U}}, +{MOVEQ_7000,{6U,93U,0U}}, +{MOVEQ_7000,{6U,94U,0U}}, +{MOVEQ_7000,{6U,95U,0U}}, +{MOVEQ_7000,{6U,96U,0U}}, +{MOVEQ_7000,{6U,97U,0U}}, +{MOVEQ_7000,{6U,98U,0U}}, +{MOVEQ_7000,{6U,99U,0U}}, +{MOVEQ_7000,{6U,100U,0U}}, +{MOVEQ_7000,{6U,101U,0U}}, +{MOVEQ_7000,{6U,102U,0U}}, +{MOVEQ_7000,{6U,103U,0U}}, +{MOVEQ_7000,{6U,104U,0U}}, +{MOVEQ_7000,{6U,105U,0U}}, +{MOVEQ_7000,{6U,106U,0U}}, +{MOVEQ_7000,{6U,107U,0U}}, +{MOVEQ_7000,{6U,108U,0U}}, +{MOVEQ_7000,{6U,109U,0U}}, +{MOVEQ_7000,{6U,110U,0U}}, +{MOVEQ_7000,{6U,111U,0U}}, +{MOVEQ_7000,{6U,112U,0U}}, +{MOVEQ_7000,{6U,113U,0U}}, +{MOVEQ_7000,{6U,114U,0U}}, +{MOVEQ_7000,{6U,115U,0U}}, +{MOVEQ_7000,{6U,116U,0U}}, +{MOVEQ_7000,{6U,117U,0U}}, +{MOVEQ_7000,{6U,118U,0U}}, +{MOVEQ_7000,{6U,119U,0U}}, +{MOVEQ_7000,{6U,120U,0U}}, +{MOVEQ_7000,{6U,121U,0U}}, +{MOVEQ_7000,{6U,122U,0U}}, +{MOVEQ_7000,{6U,123U,0U}}, +{MOVEQ_7000,{6U,124U,0U}}, +{MOVEQ_7000,{6U,125U,0U}}, +{MOVEQ_7000,{6U,126U,0U}}, +{MOVEQ_7000,{6U,127U,0U}}, +{MOVEQ_7000,{6U,4294967168U,8U}}, +{MOVEQ_7000,{6U,4294967169U,8U}}, +{MOVEQ_7000,{6U,4294967170U,8U}}, +{MOVEQ_7000,{6U,4294967171U,8U}}, +{MOVEQ_7000,{6U,4294967172U,8U}}, +{MOVEQ_7000,{6U,4294967173U,8U}}, +{MOVEQ_7000,{6U,4294967174U,8U}}, +{MOVEQ_7000,{6U,4294967175U,8U}}, +{MOVEQ_7000,{6U,4294967176U,8U}}, +{MOVEQ_7000,{6U,4294967177U,8U}}, +{MOVEQ_7000,{6U,4294967178U,8U}}, +{MOVEQ_7000,{6U,4294967179U,8U}}, +{MOVEQ_7000,{6U,4294967180U,8U}}, +{MOVEQ_7000,{6U,4294967181U,8U}}, +{MOVEQ_7000,{6U,4294967182U,8U}}, +{MOVEQ_7000,{6U,4294967183U,8U}}, +{MOVEQ_7000,{6U,4294967184U,8U}}, +{MOVEQ_7000,{6U,4294967185U,8U}}, +{MOVEQ_7000,{6U,4294967186U,8U}}, +{MOVEQ_7000,{6U,4294967187U,8U}}, +{MOVEQ_7000,{6U,4294967188U,8U}}, +{MOVEQ_7000,{6U,4294967189U,8U}}, +{MOVEQ_7000,{6U,4294967190U,8U}}, +{MOVEQ_7000,{6U,4294967191U,8U}}, +{MOVEQ_7000,{6U,4294967192U,8U}}, +{MOVEQ_7000,{6U,4294967193U,8U}}, +{MOVEQ_7000,{6U,4294967194U,8U}}, +{MOVEQ_7000,{6U,4294967195U,8U}}, +{MOVEQ_7000,{6U,4294967196U,8U}}, +{MOVEQ_7000,{6U,4294967197U,8U}}, +{MOVEQ_7000,{6U,4294967198U,8U}}, +{MOVEQ_7000,{6U,4294967199U,8U}}, +{MOVEQ_7000,{6U,4294967200U,8U}}, +{MOVEQ_7000,{6U,4294967201U,8U}}, +{MOVEQ_7000,{6U,4294967202U,8U}}, +{MOVEQ_7000,{6U,4294967203U,8U}}, +{MOVEQ_7000,{6U,4294967204U,8U}}, +{MOVEQ_7000,{6U,4294967205U,8U}}, +{MOVEQ_7000,{6U,4294967206U,8U}}, +{MOVEQ_7000,{6U,4294967207U,8U}}, +{MOVEQ_7000,{6U,4294967208U,8U}}, +{MOVEQ_7000,{6U,4294967209U,8U}}, +{MOVEQ_7000,{6U,4294967210U,8U}}, +{MOVEQ_7000,{6U,4294967211U,8U}}, +{MOVEQ_7000,{6U,4294967212U,8U}}, +{MOVEQ_7000,{6U,4294967213U,8U}}, +{MOVEQ_7000,{6U,4294967214U,8U}}, +{MOVEQ_7000,{6U,4294967215U,8U}}, +{MOVEQ_7000,{6U,4294967216U,8U}}, +{MOVEQ_7000,{6U,4294967217U,8U}}, +{MOVEQ_7000,{6U,4294967218U,8U}}, +{MOVEQ_7000,{6U,4294967219U,8U}}, +{MOVEQ_7000,{6U,4294967220U,8U}}, +{MOVEQ_7000,{6U,4294967221U,8U}}, +{MOVEQ_7000,{6U,4294967222U,8U}}, +{MOVEQ_7000,{6U,4294967223U,8U}}, +{MOVEQ_7000,{6U,4294967224U,8U}}, +{MOVEQ_7000,{6U,4294967225U,8U}}, +{MOVEQ_7000,{6U,4294967226U,8U}}, +{MOVEQ_7000,{6U,4294967227U,8U}}, +{MOVEQ_7000,{6U,4294967228U,8U}}, +{MOVEQ_7000,{6U,4294967229U,8U}}, +{MOVEQ_7000,{6U,4294967230U,8U}}, +{MOVEQ_7000,{6U,4294967231U,8U}}, +{MOVEQ_7000,{6U,4294967232U,8U}}, +{MOVEQ_7000,{6U,4294967233U,8U}}, +{MOVEQ_7000,{6U,4294967234U,8U}}, +{MOVEQ_7000,{6U,4294967235U,8U}}, +{MOVEQ_7000,{6U,4294967236U,8U}}, +{MOVEQ_7000,{6U,4294967237U,8U}}, +{MOVEQ_7000,{6U,4294967238U,8U}}, +{MOVEQ_7000,{6U,4294967239U,8U}}, +{MOVEQ_7000,{6U,4294967240U,8U}}, +{MOVEQ_7000,{6U,4294967241U,8U}}, +{MOVEQ_7000,{6U,4294967242U,8U}}, +{MOVEQ_7000,{6U,4294967243U,8U}}, +{MOVEQ_7000,{6U,4294967244U,8U}}, +{MOVEQ_7000,{6U,4294967245U,8U}}, +{MOVEQ_7000,{6U,4294967246U,8U}}, +{MOVEQ_7000,{6U,4294967247U,8U}}, +{MOVEQ_7000,{6U,4294967248U,8U}}, +{MOVEQ_7000,{6U,4294967249U,8U}}, +{MOVEQ_7000,{6U,4294967250U,8U}}, +{MOVEQ_7000,{6U,4294967251U,8U}}, +{MOVEQ_7000,{6U,4294967252U,8U}}, +{MOVEQ_7000,{6U,4294967253U,8U}}, +{MOVEQ_7000,{6U,4294967254U,8U}}, +{MOVEQ_7000,{6U,4294967255U,8U}}, +{MOVEQ_7000,{6U,4294967256U,8U}}, +{MOVEQ_7000,{6U,4294967257U,8U}}, +{MOVEQ_7000,{6U,4294967258U,8U}}, +{MOVEQ_7000,{6U,4294967259U,8U}}, +{MOVEQ_7000,{6U,4294967260U,8U}}, +{MOVEQ_7000,{6U,4294967261U,8U}}, +{MOVEQ_7000,{6U,4294967262U,8U}}, +{MOVEQ_7000,{6U,4294967263U,8U}}, +{MOVEQ_7000,{6U,4294967264U,8U}}, +{MOVEQ_7000,{6U,4294967265U,8U}}, +{MOVEQ_7000,{6U,4294967266U,8U}}, +{MOVEQ_7000,{6U,4294967267U,8U}}, +{MOVEQ_7000,{6U,4294967268U,8U}}, +{MOVEQ_7000,{6U,4294967269U,8U}}, +{MOVEQ_7000,{6U,4294967270U,8U}}, +{MOVEQ_7000,{6U,4294967271U,8U}}, +{MOVEQ_7000,{6U,4294967272U,8U}}, +{MOVEQ_7000,{6U,4294967273U,8U}}, +{MOVEQ_7000,{6U,4294967274U,8U}}, +{MOVEQ_7000,{6U,4294967275U,8U}}, +{MOVEQ_7000,{6U,4294967276U,8U}}, +{MOVEQ_7000,{6U,4294967277U,8U}}, +{MOVEQ_7000,{6U,4294967278U,8U}}, +{MOVEQ_7000,{6U,4294967279U,8U}}, +{MOVEQ_7000,{6U,4294967280U,8U}}, +{MOVEQ_7000,{6U,4294967281U,8U}}, +{MOVEQ_7000,{6U,4294967282U,8U}}, +{MOVEQ_7000,{6U,4294967283U,8U}}, +{MOVEQ_7000,{6U,4294967284U,8U}}, +{MOVEQ_7000,{6U,4294967285U,8U}}, +{MOVEQ_7000,{6U,4294967286U,8U}}, +{MOVEQ_7000,{6U,4294967287U,8U}}, +{MOVEQ_7000,{6U,4294967288U,8U}}, +{MOVEQ_7000,{6U,4294967289U,8U}}, +{MOVEQ_7000,{6U,4294967290U,8U}}, +{MOVEQ_7000,{6U,4294967291U,8U}}, +{MOVEQ_7000,{6U,4294967292U,8U}}, +{MOVEQ_7000,{6U,4294967293U,8U}}, +{MOVEQ_7000,{6U,4294967294U,8U}}, +{MOVEQ_7000,{6U,4294967295U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MOVEQ_7000,{7U,0U,4U}}, +{MOVEQ_7000,{7U,1U,0U}}, +{MOVEQ_7000,{7U,2U,0U}}, +{MOVEQ_7000,{7U,3U,0U}}, +{MOVEQ_7000,{7U,4U,0U}}, +{MOVEQ_7000,{7U,5U,0U}}, +{MOVEQ_7000,{7U,6U,0U}}, +{MOVEQ_7000,{7U,7U,0U}}, +{MOVEQ_7000,{7U,8U,0U}}, +{MOVEQ_7000,{7U,9U,0U}}, +{MOVEQ_7000,{7U,10U,0U}}, +{MOVEQ_7000,{7U,11U,0U}}, +{MOVEQ_7000,{7U,12U,0U}}, +{MOVEQ_7000,{7U,13U,0U}}, +{MOVEQ_7000,{7U,14U,0U}}, +{MOVEQ_7000,{7U,15U,0U}}, +{MOVEQ_7000,{7U,16U,0U}}, +{MOVEQ_7000,{7U,17U,0U}}, +{MOVEQ_7000,{7U,18U,0U}}, +{MOVEQ_7000,{7U,19U,0U}}, +{MOVEQ_7000,{7U,20U,0U}}, +{MOVEQ_7000,{7U,21U,0U}}, +{MOVEQ_7000,{7U,22U,0U}}, +{MOVEQ_7000,{7U,23U,0U}}, +{MOVEQ_7000,{7U,24U,0U}}, +{MOVEQ_7000,{7U,25U,0U}}, +{MOVEQ_7000,{7U,26U,0U}}, +{MOVEQ_7000,{7U,27U,0U}}, +{MOVEQ_7000,{7U,28U,0U}}, +{MOVEQ_7000,{7U,29U,0U}}, +{MOVEQ_7000,{7U,30U,0U}}, +{MOVEQ_7000,{7U,31U,0U}}, +{MOVEQ_7000,{7U,32U,0U}}, +{MOVEQ_7000,{7U,33U,0U}}, +{MOVEQ_7000,{7U,34U,0U}}, +{MOVEQ_7000,{7U,35U,0U}}, +{MOVEQ_7000,{7U,36U,0U}}, +{MOVEQ_7000,{7U,37U,0U}}, +{MOVEQ_7000,{7U,38U,0U}}, +{MOVEQ_7000,{7U,39U,0U}}, +{MOVEQ_7000,{7U,40U,0U}}, +{MOVEQ_7000,{7U,41U,0U}}, +{MOVEQ_7000,{7U,42U,0U}}, +{MOVEQ_7000,{7U,43U,0U}}, +{MOVEQ_7000,{7U,44U,0U}}, +{MOVEQ_7000,{7U,45U,0U}}, +{MOVEQ_7000,{7U,46U,0U}}, +{MOVEQ_7000,{7U,47U,0U}}, +{MOVEQ_7000,{7U,48U,0U}}, +{MOVEQ_7000,{7U,49U,0U}}, +{MOVEQ_7000,{7U,50U,0U}}, +{MOVEQ_7000,{7U,51U,0U}}, +{MOVEQ_7000,{7U,52U,0U}}, +{MOVEQ_7000,{7U,53U,0U}}, +{MOVEQ_7000,{7U,54U,0U}}, +{MOVEQ_7000,{7U,55U,0U}}, +{MOVEQ_7000,{7U,56U,0U}}, +{MOVEQ_7000,{7U,57U,0U}}, +{MOVEQ_7000,{7U,58U,0U}}, +{MOVEQ_7000,{7U,59U,0U}}, +{MOVEQ_7000,{7U,60U,0U}}, +{MOVEQ_7000,{7U,61U,0U}}, +{MOVEQ_7000,{7U,62U,0U}}, +{MOVEQ_7000,{7U,63U,0U}}, +{MOVEQ_7000,{7U,64U,0U}}, +{MOVEQ_7000,{7U,65U,0U}}, +{MOVEQ_7000,{7U,66U,0U}}, +{MOVEQ_7000,{7U,67U,0U}}, +{MOVEQ_7000,{7U,68U,0U}}, +{MOVEQ_7000,{7U,69U,0U}}, +{MOVEQ_7000,{7U,70U,0U}}, +{MOVEQ_7000,{7U,71U,0U}}, +{MOVEQ_7000,{7U,72U,0U}}, +{MOVEQ_7000,{7U,73U,0U}}, +{MOVEQ_7000,{7U,74U,0U}}, +{MOVEQ_7000,{7U,75U,0U}}, +{MOVEQ_7000,{7U,76U,0U}}, +{MOVEQ_7000,{7U,77U,0U}}, +{MOVEQ_7000,{7U,78U,0U}}, +{MOVEQ_7000,{7U,79U,0U}}, +{MOVEQ_7000,{7U,80U,0U}}, +{MOVEQ_7000,{7U,81U,0U}}, +{MOVEQ_7000,{7U,82U,0U}}, +{MOVEQ_7000,{7U,83U,0U}}, +{MOVEQ_7000,{7U,84U,0U}}, +{MOVEQ_7000,{7U,85U,0U}}, +{MOVEQ_7000,{7U,86U,0U}}, +{MOVEQ_7000,{7U,87U,0U}}, +{MOVEQ_7000,{7U,88U,0U}}, +{MOVEQ_7000,{7U,89U,0U}}, +{MOVEQ_7000,{7U,90U,0U}}, +{MOVEQ_7000,{7U,91U,0U}}, +{MOVEQ_7000,{7U,92U,0U}}, +{MOVEQ_7000,{7U,93U,0U}}, +{MOVEQ_7000,{7U,94U,0U}}, +{MOVEQ_7000,{7U,95U,0U}}, +{MOVEQ_7000,{7U,96U,0U}}, +{MOVEQ_7000,{7U,97U,0U}}, +{MOVEQ_7000,{7U,98U,0U}}, +{MOVEQ_7000,{7U,99U,0U}}, +{MOVEQ_7000,{7U,100U,0U}}, +{MOVEQ_7000,{7U,101U,0U}}, +{MOVEQ_7000,{7U,102U,0U}}, +{MOVEQ_7000,{7U,103U,0U}}, +{MOVEQ_7000,{7U,104U,0U}}, +{MOVEQ_7000,{7U,105U,0U}}, +{MOVEQ_7000,{7U,106U,0U}}, +{MOVEQ_7000,{7U,107U,0U}}, +{MOVEQ_7000,{7U,108U,0U}}, +{MOVEQ_7000,{7U,109U,0U}}, +{MOVEQ_7000,{7U,110U,0U}}, +{MOVEQ_7000,{7U,111U,0U}}, +{MOVEQ_7000,{7U,112U,0U}}, +{MOVEQ_7000,{7U,113U,0U}}, +{MOVEQ_7000,{7U,114U,0U}}, +{MOVEQ_7000,{7U,115U,0U}}, +{MOVEQ_7000,{7U,116U,0U}}, +{MOVEQ_7000,{7U,117U,0U}}, +{MOVEQ_7000,{7U,118U,0U}}, +{MOVEQ_7000,{7U,119U,0U}}, +{MOVEQ_7000,{7U,120U,0U}}, +{MOVEQ_7000,{7U,121U,0U}}, +{MOVEQ_7000,{7U,122U,0U}}, +{MOVEQ_7000,{7U,123U,0U}}, +{MOVEQ_7000,{7U,124U,0U}}, +{MOVEQ_7000,{7U,125U,0U}}, +{MOVEQ_7000,{7U,126U,0U}}, +{MOVEQ_7000,{7U,127U,0U}}, +{MOVEQ_7000,{7U,4294967168U,8U}}, +{MOVEQ_7000,{7U,4294967169U,8U}}, +{MOVEQ_7000,{7U,4294967170U,8U}}, +{MOVEQ_7000,{7U,4294967171U,8U}}, +{MOVEQ_7000,{7U,4294967172U,8U}}, +{MOVEQ_7000,{7U,4294967173U,8U}}, +{MOVEQ_7000,{7U,4294967174U,8U}}, +{MOVEQ_7000,{7U,4294967175U,8U}}, +{MOVEQ_7000,{7U,4294967176U,8U}}, +{MOVEQ_7000,{7U,4294967177U,8U}}, +{MOVEQ_7000,{7U,4294967178U,8U}}, +{MOVEQ_7000,{7U,4294967179U,8U}}, +{MOVEQ_7000,{7U,4294967180U,8U}}, +{MOVEQ_7000,{7U,4294967181U,8U}}, +{MOVEQ_7000,{7U,4294967182U,8U}}, +{MOVEQ_7000,{7U,4294967183U,8U}}, +{MOVEQ_7000,{7U,4294967184U,8U}}, +{MOVEQ_7000,{7U,4294967185U,8U}}, +{MOVEQ_7000,{7U,4294967186U,8U}}, +{MOVEQ_7000,{7U,4294967187U,8U}}, +{MOVEQ_7000,{7U,4294967188U,8U}}, +{MOVEQ_7000,{7U,4294967189U,8U}}, +{MOVEQ_7000,{7U,4294967190U,8U}}, +{MOVEQ_7000,{7U,4294967191U,8U}}, +{MOVEQ_7000,{7U,4294967192U,8U}}, +{MOVEQ_7000,{7U,4294967193U,8U}}, +{MOVEQ_7000,{7U,4294967194U,8U}}, +{MOVEQ_7000,{7U,4294967195U,8U}}, +{MOVEQ_7000,{7U,4294967196U,8U}}, +{MOVEQ_7000,{7U,4294967197U,8U}}, +{MOVEQ_7000,{7U,4294967198U,8U}}, +{MOVEQ_7000,{7U,4294967199U,8U}}, +{MOVEQ_7000,{7U,4294967200U,8U}}, +{MOVEQ_7000,{7U,4294967201U,8U}}, +{MOVEQ_7000,{7U,4294967202U,8U}}, +{MOVEQ_7000,{7U,4294967203U,8U}}, +{MOVEQ_7000,{7U,4294967204U,8U}}, +{MOVEQ_7000,{7U,4294967205U,8U}}, +{MOVEQ_7000,{7U,4294967206U,8U}}, +{MOVEQ_7000,{7U,4294967207U,8U}}, +{MOVEQ_7000,{7U,4294967208U,8U}}, +{MOVEQ_7000,{7U,4294967209U,8U}}, +{MOVEQ_7000,{7U,4294967210U,8U}}, +{MOVEQ_7000,{7U,4294967211U,8U}}, +{MOVEQ_7000,{7U,4294967212U,8U}}, +{MOVEQ_7000,{7U,4294967213U,8U}}, +{MOVEQ_7000,{7U,4294967214U,8U}}, +{MOVEQ_7000,{7U,4294967215U,8U}}, +{MOVEQ_7000,{7U,4294967216U,8U}}, +{MOVEQ_7000,{7U,4294967217U,8U}}, +{MOVEQ_7000,{7U,4294967218U,8U}}, +{MOVEQ_7000,{7U,4294967219U,8U}}, +{MOVEQ_7000,{7U,4294967220U,8U}}, +{MOVEQ_7000,{7U,4294967221U,8U}}, +{MOVEQ_7000,{7U,4294967222U,8U}}, +{MOVEQ_7000,{7U,4294967223U,8U}}, +{MOVEQ_7000,{7U,4294967224U,8U}}, +{MOVEQ_7000,{7U,4294967225U,8U}}, +{MOVEQ_7000,{7U,4294967226U,8U}}, +{MOVEQ_7000,{7U,4294967227U,8U}}, +{MOVEQ_7000,{7U,4294967228U,8U}}, +{MOVEQ_7000,{7U,4294967229U,8U}}, +{MOVEQ_7000,{7U,4294967230U,8U}}, +{MOVEQ_7000,{7U,4294967231U,8U}}, +{MOVEQ_7000,{7U,4294967232U,8U}}, +{MOVEQ_7000,{7U,4294967233U,8U}}, +{MOVEQ_7000,{7U,4294967234U,8U}}, +{MOVEQ_7000,{7U,4294967235U,8U}}, +{MOVEQ_7000,{7U,4294967236U,8U}}, +{MOVEQ_7000,{7U,4294967237U,8U}}, +{MOVEQ_7000,{7U,4294967238U,8U}}, +{MOVEQ_7000,{7U,4294967239U,8U}}, +{MOVEQ_7000,{7U,4294967240U,8U}}, +{MOVEQ_7000,{7U,4294967241U,8U}}, +{MOVEQ_7000,{7U,4294967242U,8U}}, +{MOVEQ_7000,{7U,4294967243U,8U}}, +{MOVEQ_7000,{7U,4294967244U,8U}}, +{MOVEQ_7000,{7U,4294967245U,8U}}, +{MOVEQ_7000,{7U,4294967246U,8U}}, +{MOVEQ_7000,{7U,4294967247U,8U}}, +{MOVEQ_7000,{7U,4294967248U,8U}}, +{MOVEQ_7000,{7U,4294967249U,8U}}, +{MOVEQ_7000,{7U,4294967250U,8U}}, +{MOVEQ_7000,{7U,4294967251U,8U}}, +{MOVEQ_7000,{7U,4294967252U,8U}}, +{MOVEQ_7000,{7U,4294967253U,8U}}, +{MOVEQ_7000,{7U,4294967254U,8U}}, +{MOVEQ_7000,{7U,4294967255U,8U}}, +{MOVEQ_7000,{7U,4294967256U,8U}}, +{MOVEQ_7000,{7U,4294967257U,8U}}, +{MOVEQ_7000,{7U,4294967258U,8U}}, +{MOVEQ_7000,{7U,4294967259U,8U}}, +{MOVEQ_7000,{7U,4294967260U,8U}}, +{MOVEQ_7000,{7U,4294967261U,8U}}, +{MOVEQ_7000,{7U,4294967262U,8U}}, +{MOVEQ_7000,{7U,4294967263U,8U}}, +{MOVEQ_7000,{7U,4294967264U,8U}}, +{MOVEQ_7000,{7U,4294967265U,8U}}, +{MOVEQ_7000,{7U,4294967266U,8U}}, +{MOVEQ_7000,{7U,4294967267U,8U}}, +{MOVEQ_7000,{7U,4294967268U,8U}}, +{MOVEQ_7000,{7U,4294967269U,8U}}, +{MOVEQ_7000,{7U,4294967270U,8U}}, +{MOVEQ_7000,{7U,4294967271U,8U}}, +{MOVEQ_7000,{7U,4294967272U,8U}}, +{MOVEQ_7000,{7U,4294967273U,8U}}, +{MOVEQ_7000,{7U,4294967274U,8U}}, +{MOVEQ_7000,{7U,4294967275U,8U}}, +{MOVEQ_7000,{7U,4294967276U,8U}}, +{MOVEQ_7000,{7U,4294967277U,8U}}, +{MOVEQ_7000,{7U,4294967278U,8U}}, +{MOVEQ_7000,{7U,4294967279U,8U}}, +{MOVEQ_7000,{7U,4294967280U,8U}}, +{MOVEQ_7000,{7U,4294967281U,8U}}, +{MOVEQ_7000,{7U,4294967282U,8U}}, +{MOVEQ_7000,{7U,4294967283U,8U}}, +{MOVEQ_7000,{7U,4294967284U,8U}}, +{MOVEQ_7000,{7U,4294967285U,8U}}, +{MOVEQ_7000,{7U,4294967286U,8U}}, +{MOVEQ_7000,{7U,4294967287U,8U}}, +{MOVEQ_7000,{7U,4294967288U,8U}}, +{MOVEQ_7000,{7U,4294967289U,8U}}, +{MOVEQ_7000,{7U,4294967290U,8U}}, +{MOVEQ_7000,{7U,4294967291U,8U}}, +{MOVEQ_7000,{7U,4294967292U,8U}}, +{MOVEQ_7000,{7U,4294967293U,8U}}, +{MOVEQ_7000,{7U,4294967294U,8U}}, +{MOVEQ_7000,{7U,4294967295U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, 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+{DIVU_80D0,{1U,0U,74U}}, +{DIVU_80D0,{2U,0U,74U}}, +{DIVU_80D0,{3U,0U,74U}}, +{DIVU_80D0,{4U,0U,74U}}, +{DIVU_80D0,{5U,0U,74U}}, +{DIVU_80D0,{6U,0U,74U}}, +{DIVU_80D0,{7U,0U,74U}}, +{DIVU_80D8,{0U,0U,74U}}, +{DIVU_80D8,{1U,0U,74U}}, +{DIVU_80D8,{2U,0U,74U}}, +{DIVU_80D8,{3U,0U,74U}}, +{DIVU_80D8,{4U,0U,74U}}, +{DIVU_80D8,{5U,0U,74U}}, +{DIVU_80D8,{6U,0U,74U}}, +{DIVU_80D8,{7U,0U,74U}}, +{DIVU_80E0,{0U,0U,76U}}, +{DIVU_80E0,{1U,0U,76U}}, +{DIVU_80E0,{2U,0U,76U}}, +{DIVU_80E0,{3U,0U,76U}}, +{DIVU_80E0,{4U,0U,76U}}, +{DIVU_80E0,{5U,0U,76U}}, +{DIVU_80E0,{6U,0U,76U}}, +{DIVU_80E0,{7U,0U,76U}}, +{DIVU_80E8,{0U,0U,78U}}, +{DIVU_80E8,{1U,0U,78U}}, +{DIVU_80E8,{2U,0U,78U}}, +{DIVU_80E8,{3U,0U,78U}}, +{DIVU_80E8,{4U,0U,78U}}, +{DIVU_80E8,{5U,0U,78U}}, +{DIVU_80E8,{6U,0U,78U}}, +{DIVU_80E8,{7U,0U,78U}}, +{DIVU_80F0,{0U,0U,80U}}, +{DIVU_80F0,{1U,0U,80U}}, +{DIVU_80F0,{2U,0U,80U}}, +{DIVU_80F0,{3U,0U,80U}}, +{DIVU_80F0,{4U,0U,80U}}, +{DIVU_80F0,{5U,0U,80U}}, +{DIVU_80F0,{6U,0U,80U}}, +{DIVU_80F0,{7U,0U,80U}}, +{DIVU_80F8,{0U,0U,78U}}, +{DIVU_80F9,{0U,0U,82U}}, +{DIVU_80FA,{0U,0U,78U}}, +{DIVU_80FB,{0U,0U,80U}}, +{DIVU_80FC,{0U,0U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SBCD_8100,{0U,0U,0U}}, +{SBCD_8100,{1U,0U,0U}}, +{SBCD_8100,{2U,0U,0U}}, +{SBCD_8100,{3U,0U,0U}}, +{SBCD_8100,{4U,0U,0U}}, +{SBCD_8100,{5U,0U,0U}}, +{SBCD_8100,{6U,0U,0U}}, +{SBCD_8100,{7U,0U,0U}}, +{SBCD_8108,{0U,0U,0U}}, +{SBCD_8108,{1U,0U,0U}}, +{SBCD_8108,{2U,0U,0U}}, +{SBCD_8108,{3U,0U,0U}}, +{SBCD_8108,{4U,0U,0U}}, +{SBCD_8108,{5U,0U,0U}}, +{SBCD_8108,{6U,0U,0U}}, +{SBCD_8108,{7U,0U,0U}}, +{OR_8110,{0U,0U,0U}}, +{OR_8110,{1U,0U,0U}}, +{OR_8110,{2U,0U,0U}}, +{OR_8110,{3U,0U,0U}}, +{OR_8110,{4U,0U,0U}}, +{OR_8110,{5U,0U,0U}}, +{OR_8110,{6U,0U,0U}}, +{OR_8110,{7U,0U,0U}}, +{OR_8118,{0U,0U,0U}}, +{OR_8118,{1U,0U,0U}}, +{OR_8118,{2U,0U,0U}}, +{OR_8118,{3U,0U,0U}}, +{OR_8118,{4U,0U,0U}}, +{OR_8118,{5U,0U,0U}}, +{OR_8118,{6U,0U,0U}}, +{OR_8118,{7U,0U,0U}}, +{OR_8120,{0U,0U,0U}}, +{OR_8120,{1U,0U,0U}}, +{OR_8120,{2U,0U,0U}}, +{OR_8120,{3U,0U,0U}}, +{OR_8120,{4U,0U,0U}}, +{OR_8120,{5U,0U,0U}}, +{OR_8120,{6U,0U,0U}}, +{OR_8120,{7U,0U,0U}}, +{OR_8128,{0U,0U,0U}}, +{OR_8128,{1U,0U,0U}}, +{OR_8128,{2U,0U,0U}}, +{OR_8128,{3U,0U,0U}}, +{OR_8128,{4U,0U,0U}}, +{OR_8128,{5U,0U,0U}}, +{OR_8128,{6U,0U,0U}}, +{OR_8128,{7U,0U,0U}}, +{OR_8130,{0U,0U,0U}}, +{OR_8130,{1U,0U,0U}}, +{OR_8130,{2U,0U,0U}}, +{OR_8130,{3U,0U,0U}}, +{OR_8130,{4U,0U,0U}}, +{OR_8130,{5U,0U,0U}}, +{OR_8130,{6U,0U,0U}}, +{OR_8130,{7U,0U,0U}}, +{OR_8138,{0U,0U,0U}}, +{OR_8139,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PACK_8140,{0U,0U,0U}}, +{PACK_8140,{0U,1U,0U}}, +{PACK_8140,{0U,2U,0U}}, +{PACK_8140,{0U,3U,0U}}, +{PACK_8140,{0U,4U,0U}}, +{PACK_8140,{0U,5U,0U}}, +{PACK_8140,{0U,6U,0U}}, +{PACK_8140,{0U,7U,0U}}, +{PACK_8148,{0U,0U,0U}}, +{PACK_8148,{0U,1U,0U}}, +{PACK_8148,{0U,2U,0U}}, +{PACK_8148,{0U,3U,0U}}, +{PACK_8148,{0U,4U,0U}}, +{PACK_8148,{0U,5U,0U}}, +{PACK_8148,{0U,6U,0U}}, +{PACK_8148,{0U,7U,0U}}, +{OR_8150,{0U,0U,0U}}, +{OR_8150,{1U,0U,0U}}, +{OR_8150,{2U,0U,0U}}, +{OR_8150,{3U,0U,0U}}, +{OR_8150,{4U,0U,0U}}, +{OR_8150,{5U,0U,0U}}, +{OR_8150,{6U,0U,0U}}, +{OR_8150,{7U,0U,0U}}, +{OR_8158,{0U,0U,0U}}, +{OR_8158,{1U,0U,0U}}, +{OR_8158,{2U,0U,0U}}, +{OR_8158,{3U,0U,0U}}, +{OR_8158,{4U,0U,0U}}, +{OR_8158,{5U,0U,0U}}, +{OR_8158,{6U,0U,0U}}, +{OR_8158,{7U,0U,0U}}, +{OR_8160,{0U,0U,0U}}, +{OR_8160,{1U,0U,0U}}, +{OR_8160,{2U,0U,0U}}, +{OR_8160,{3U,0U,0U}}, +{OR_8160,{4U,0U,0U}}, +{OR_8160,{5U,0U,0U}}, +{OR_8160,{6U,0U,0U}}, +{OR_8160,{7U,0U,0U}}, +{OR_8168,{0U,0U,0U}}, +{OR_8168,{1U,0U,0U}}, +{OR_8168,{2U,0U,0U}}, +{OR_8168,{3U,0U,0U}}, +{OR_8168,{4U,0U,0U}}, +{OR_8168,{5U,0U,0U}}, +{OR_8168,{6U,0U,0U}}, +{OR_8168,{7U,0U,0U}}, +{OR_8170,{0U,0U,0U}}, +{OR_8170,{1U,0U,0U}}, +{OR_8170,{2U,0U,0U}}, +{OR_8170,{3U,0U,0U}}, +{OR_8170,{4U,0U,0U}}, +{OR_8170,{5U,0U,0U}}, +{OR_8170,{6U,0U,0U}}, +{OR_8170,{7U,0U,0U}}, +{OR_8178,{0U,0U,0U}}, +{OR_8179,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{UNPK_8180,{0U,0U,0U}}, +{UNPK_8180,{0U,1U,0U}}, +{UNPK_8180,{0U,2U,0U}}, +{UNPK_8180,{0U,3U,0U}}, +{UNPK_8180,{0U,4U,0U}}, +{UNPK_8180,{0U,5U,0U}}, +{UNPK_8180,{0U,6U,0U}}, +{UNPK_8180,{0U,7U,0U}}, +{UNPK_8188,{0U,0U,0U}}, +{UNPK_8188,{0U,1U,0U}}, +{UNPK_8188,{0U,2U,0U}}, +{UNPK_8188,{0U,3U,0U}}, +{UNPK_8188,{0U,4U,0U}}, +{UNPK_8188,{0U,5U,0U}}, +{UNPK_8188,{0U,6U,0U}}, +{UNPK_8188,{0U,7U,0U}}, +{OR_8190,{0U,0U,0U}}, +{OR_8190,{1U,0U,0U}}, +{OR_8190,{2U,0U,0U}}, +{OR_8190,{3U,0U,0U}}, +{OR_8190,{4U,0U,0U}}, +{OR_8190,{5U,0U,0U}}, +{OR_8190,{6U,0U,0U}}, +{OR_8190,{7U,0U,0U}}, +{OR_8198,{0U,0U,0U}}, +{OR_8198,{1U,0U,0U}}, +{OR_8198,{2U,0U,0U}}, +{OR_8198,{3U,0U,0U}}, +{OR_8198,{4U,0U,0U}}, +{OR_8198,{5U,0U,0U}}, +{OR_8198,{6U,0U,0U}}, +{OR_8198,{7U,0U,0U}}, +{OR_81A0,{0U,0U,0U}}, +{OR_81A0,{1U,0U,0U}}, +{OR_81A0,{2U,0U,0U}}, +{OR_81A0,{3U,0U,0U}}, +{OR_81A0,{4U,0U,0U}}, +{OR_81A0,{5U,0U,0U}}, +{OR_81A0,{6U,0U,0U}}, +{OR_81A0,{7U,0U,0U}}, +{OR_81A8,{0U,0U,0U}}, +{OR_81A8,{1U,0U,0U}}, +{OR_81A8,{2U,0U,0U}}, +{OR_81A8,{3U,0U,0U}}, +{OR_81A8,{4U,0U,0U}}, +{OR_81A8,{5U,0U,0U}}, +{OR_81A8,{6U,0U,0U}}, +{OR_81A8,{7U,0U,0U}}, +{OR_81B0,{0U,0U,0U}}, +{OR_81B0,{1U,0U,0U}}, +{OR_81B0,{2U,0U,0U}}, +{OR_81B0,{3U,0U,0U}}, +{OR_81B0,{4U,0U,0U}}, +{OR_81B0,{5U,0U,0U}}, +{OR_81B0,{6U,0U,0U}}, +{OR_81B0,{7U,0U,0U}}, +{OR_81B8,{0U,0U,0U}}, +{OR_81B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81C0,{0U,0U,70U}}, +{DIVS_81C0,{1U,0U,70U}}, +{DIVS_81C0,{2U,0U,70U}}, +{DIVS_81C0,{3U,0U,70U}}, +{DIVS_81C0,{4U,0U,70U}}, +{DIVS_81C0,{5U,0U,70U}}, +{DIVS_81C0,{6U,0U,70U}}, +{DIVS_81C0,{7U,0U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81D0,{0U,0U,74U}}, +{DIVS_81D0,{1U,0U,74U}}, +{DIVS_81D0,{2U,0U,74U}}, +{DIVS_81D0,{3U,0U,74U}}, +{DIVS_81D0,{4U,0U,74U}}, +{DIVS_81D0,{5U,0U,74U}}, +{DIVS_81D0,{6U,0U,74U}}, +{DIVS_81D0,{7U,0U,74U}}, +{DIVS_81D8,{0U,0U,74U}}, +{DIVS_81D8,{1U,0U,74U}}, +{DIVS_81D8,{2U,0U,74U}}, +{DIVS_81D8,{3U,0U,74U}}, +{DIVS_81D8,{4U,0U,74U}}, +{DIVS_81D8,{5U,0U,74U}}, +{DIVS_81D8,{6U,0U,74U}}, +{DIVS_81D8,{7U,0U,74U}}, +{DIVS_81E0,{0U,0U,76U}}, +{DIVS_81E0,{1U,0U,76U}}, +{DIVS_81E0,{2U,0U,76U}}, +{DIVS_81E0,{3U,0U,76U}}, +{DIVS_81E0,{4U,0U,76U}}, +{DIVS_81E0,{5U,0U,76U}}, +{DIVS_81E0,{6U,0U,76U}}, +{DIVS_81E0,{7U,0U,76U}}, +{DIVS_81E8,{0U,0U,78U}}, +{DIVS_81E8,{1U,0U,78U}}, +{DIVS_81E8,{2U,0U,78U}}, +{DIVS_81E8,{3U,0U,78U}}, +{DIVS_81E8,{4U,0U,78U}}, +{DIVS_81E8,{5U,0U,78U}}, +{DIVS_81E8,{6U,0U,78U}}, +{DIVS_81E8,{7U,0U,78U}}, +{DIVS_81F0,{0U,0U,80U}}, +{DIVS_81F0,{1U,0U,80U}}, +{DIVS_81F0,{2U,0U,80U}}, +{DIVS_81F0,{3U,0U,80U}}, +{DIVS_81F0,{4U,0U,80U}}, +{DIVS_81F0,{5U,0U,80U}}, +{DIVS_81F0,{6U,0U,80U}}, +{DIVS_81F0,{7U,0U,80U}}, +{DIVS_81F8,{0U,0U,78U}}, +{DIVS_81F9,{0U,0U,82U}}, +{DIVS_81FA,{0U,0U,78U}}, +{DIVS_81FB,{0U,0U,80U}}, +{DIVS_81FC,{0U,0U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8000,{0U,1U,0U}}, +{OR_8000,{1U,1U,0U}}, +{OR_8000,{2U,1U,0U}}, +{OR_8000,{3U,1U,0U}}, +{OR_8000,{4U,1U,0U}}, +{OR_8000,{5U,1U,0U}}, +{OR_8000,{6U,1U,0U}}, +{OR_8000,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8010,{0U,1U,0U}}, +{OR_8010,{1U,1U,0U}}, +{OR_8010,{2U,1U,0U}}, +{OR_8010,{3U,1U,0U}}, +{OR_8010,{4U,1U,0U}}, +{OR_8010,{5U,1U,0U}}, +{OR_8010,{6U,1U,0U}}, +{OR_8010,{7U,1U,0U}}, +{OR_8018,{0U,1U,0U}}, +{OR_8018,{1U,1U,0U}}, +{OR_8018,{2U,1U,0U}}, +{OR_8018,{3U,1U,0U}}, +{OR_8018,{4U,1U,0U}}, +{OR_8018,{5U,1U,0U}}, +{OR_8018,{6U,1U,0U}}, +{OR_8018,{7U,1U,0U}}, +{OR_8020,{0U,1U,0U}}, +{OR_8020,{1U,1U,0U}}, +{OR_8020,{2U,1U,0U}}, +{OR_8020,{3U,1U,0U}}, +{OR_8020,{4U,1U,0U}}, +{OR_8020,{5U,1U,0U}}, +{OR_8020,{6U,1U,0U}}, +{OR_8020,{7U,1U,0U}}, +{OR_8028,{0U,1U,0U}}, +{OR_8028,{1U,1U,0U}}, +{OR_8028,{2U,1U,0U}}, +{OR_8028,{3U,1U,0U}}, +{OR_8028,{4U,1U,0U}}, +{OR_8028,{5U,1U,0U}}, +{OR_8028,{6U,1U,0U}}, +{OR_8028,{7U,1U,0U}}, +{OR_8030,{0U,1U,0U}}, +{OR_8030,{1U,1U,0U}}, +{OR_8030,{2U,1U,0U}}, +{OR_8030,{3U,1U,0U}}, +{OR_8030,{4U,1U,0U}}, +{OR_8030,{5U,1U,0U}}, +{OR_8030,{6U,1U,0U}}, +{OR_8030,{7U,1U,0U}}, +{OR_8038,{0U,1U,0U}}, +{OR_8039,{0U,1U,0U}}, +{OR_803A,{0U,1U,0U}}, +{OR_803B,{0U,1U,0U}}, +{OR_803C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8040,{0U,1U,0U}}, +{OR_8040,{1U,1U,0U}}, +{OR_8040,{2U,1U,0U}}, +{OR_8040,{3U,1U,0U}}, +{OR_8040,{4U,1U,0U}}, +{OR_8040,{5U,1U,0U}}, +{OR_8040,{6U,1U,0U}}, +{OR_8040,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8050,{0U,1U,0U}}, +{OR_8050,{1U,1U,0U}}, +{OR_8050,{2U,1U,0U}}, +{OR_8050,{3U,1U,0U}}, +{OR_8050,{4U,1U,0U}}, +{OR_8050,{5U,1U,0U}}, +{OR_8050,{6U,1U,0U}}, +{OR_8050,{7U,1U,0U}}, +{OR_8058,{0U,1U,0U}}, +{OR_8058,{1U,1U,0U}}, +{OR_8058,{2U,1U,0U}}, +{OR_8058,{3U,1U,0U}}, +{OR_8058,{4U,1U,0U}}, +{OR_8058,{5U,1U,0U}}, +{OR_8058,{6U,1U,0U}}, +{OR_8058,{7U,1U,0U}}, +{OR_8060,{0U,1U,0U}}, +{OR_8060,{1U,1U,0U}}, +{OR_8060,{2U,1U,0U}}, +{OR_8060,{3U,1U,0U}}, +{OR_8060,{4U,1U,0U}}, +{OR_8060,{5U,1U,0U}}, +{OR_8060,{6U,1U,0U}}, +{OR_8060,{7U,1U,0U}}, +{OR_8068,{0U,1U,0U}}, +{OR_8068,{1U,1U,0U}}, +{OR_8068,{2U,1U,0U}}, +{OR_8068,{3U,1U,0U}}, +{OR_8068,{4U,1U,0U}}, +{OR_8068,{5U,1U,0U}}, +{OR_8068,{6U,1U,0U}}, +{OR_8068,{7U,1U,0U}}, +{OR_8070,{0U,1U,0U}}, +{OR_8070,{1U,1U,0U}}, +{OR_8070,{2U,1U,0U}}, +{OR_8070,{3U,1U,0U}}, +{OR_8070,{4U,1U,0U}}, +{OR_8070,{5U,1U,0U}}, +{OR_8070,{6U,1U,0U}}, +{OR_8070,{7U,1U,0U}}, +{OR_8078,{0U,1U,0U}}, +{OR_8079,{0U,1U,0U}}, +{OR_807A,{0U,1U,0U}}, +{OR_807B,{0U,1U,0U}}, +{OR_807C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8080,{0U,1U,0U}}, +{OR_8080,{1U,1U,0U}}, +{OR_8080,{2U,1U,0U}}, +{OR_8080,{3U,1U,0U}}, +{OR_8080,{4U,1U,0U}}, +{OR_8080,{5U,1U,0U}}, +{OR_8080,{6U,1U,0U}}, +{OR_8080,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8090,{0U,1U,0U}}, +{OR_8090,{1U,1U,0U}}, +{OR_8090,{2U,1U,0U}}, +{OR_8090,{3U,1U,0U}}, +{OR_8090,{4U,1U,0U}}, +{OR_8090,{5U,1U,0U}}, +{OR_8090,{6U,1U,0U}}, +{OR_8090,{7U,1U,0U}}, +{OR_8098,{0U,1U,0U}}, +{OR_8098,{1U,1U,0U}}, +{OR_8098,{2U,1U,0U}}, +{OR_8098,{3U,1U,0U}}, +{OR_8098,{4U,1U,0U}}, +{OR_8098,{5U,1U,0U}}, +{OR_8098,{6U,1U,0U}}, +{OR_8098,{7U,1U,0U}}, +{OR_80A0,{0U,1U,0U}}, +{OR_80A0,{1U,1U,0U}}, +{OR_80A0,{2U,1U,0U}}, +{OR_80A0,{3U,1U,0U}}, +{OR_80A0,{4U,1U,0U}}, +{OR_80A0,{5U,1U,0U}}, +{OR_80A0,{6U,1U,0U}}, +{OR_80A0,{7U,1U,0U}}, +{OR_80A8,{0U,1U,0U}}, +{OR_80A8,{1U,1U,0U}}, +{OR_80A8,{2U,1U,0U}}, +{OR_80A8,{3U,1U,0U}}, +{OR_80A8,{4U,1U,0U}}, +{OR_80A8,{5U,1U,0U}}, +{OR_80A8,{6U,1U,0U}}, +{OR_80A8,{7U,1U,0U}}, +{OR_80B0,{0U,1U,0U}}, +{OR_80B0,{1U,1U,0U}}, +{OR_80B0,{2U,1U,0U}}, +{OR_80B0,{3U,1U,0U}}, +{OR_80B0,{4U,1U,0U}}, +{OR_80B0,{5U,1U,0U}}, +{OR_80B0,{6U,1U,0U}}, +{OR_80B0,{7U,1U,0U}}, +{OR_80B8,{0U,1U,0U}}, +{OR_80B9,{0U,1U,0U}}, +{OR_80BA,{0U,1U,0U}}, +{OR_80BB,{0U,1U,0U}}, +{OR_80BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80C0,{0U,1U,70U}}, +{DIVU_80C0,{1U,1U,70U}}, +{DIVU_80C0,{2U,1U,70U}}, +{DIVU_80C0,{3U,1U,70U}}, +{DIVU_80C0,{4U,1U,70U}}, +{DIVU_80C0,{5U,1U,70U}}, +{DIVU_80C0,{6U,1U,70U}}, +{DIVU_80C0,{7U,1U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80D0,{0U,1U,74U}}, +{DIVU_80D0,{1U,1U,74U}}, +{DIVU_80D0,{2U,1U,74U}}, +{DIVU_80D0,{3U,1U,74U}}, +{DIVU_80D0,{4U,1U,74U}}, +{DIVU_80D0,{5U,1U,74U}}, +{DIVU_80D0,{6U,1U,74U}}, +{DIVU_80D0,{7U,1U,74U}}, +{DIVU_80D8,{0U,1U,74U}}, +{DIVU_80D8,{1U,1U,74U}}, +{DIVU_80D8,{2U,1U,74U}}, +{DIVU_80D8,{3U,1U,74U}}, +{DIVU_80D8,{4U,1U,74U}}, +{DIVU_80D8,{5U,1U,74U}}, +{DIVU_80D8,{6U,1U,74U}}, +{DIVU_80D8,{7U,1U,74U}}, +{DIVU_80E0,{0U,1U,76U}}, +{DIVU_80E0,{1U,1U,76U}}, +{DIVU_80E0,{2U,1U,76U}}, +{DIVU_80E0,{3U,1U,76U}}, +{DIVU_80E0,{4U,1U,76U}}, +{DIVU_80E0,{5U,1U,76U}}, +{DIVU_80E0,{6U,1U,76U}}, +{DIVU_80E0,{7U,1U,76U}}, +{DIVU_80E8,{0U,1U,78U}}, +{DIVU_80E8,{1U,1U,78U}}, +{DIVU_80E8,{2U,1U,78U}}, +{DIVU_80E8,{3U,1U,78U}}, +{DIVU_80E8,{4U,1U,78U}}, +{DIVU_80E8,{5U,1U,78U}}, +{DIVU_80E8,{6U,1U,78U}}, +{DIVU_80E8,{7U,1U,78U}}, +{DIVU_80F0,{0U,1U,80U}}, +{DIVU_80F0,{1U,1U,80U}}, +{DIVU_80F0,{2U,1U,80U}}, +{DIVU_80F0,{3U,1U,80U}}, +{DIVU_80F0,{4U,1U,80U}}, +{DIVU_80F0,{5U,1U,80U}}, +{DIVU_80F0,{6U,1U,80U}}, +{DIVU_80F0,{7U,1U,80U}}, +{DIVU_80F8,{0U,1U,78U}}, +{DIVU_80F9,{0U,1U,82U}}, +{DIVU_80FA,{0U,1U,78U}}, +{DIVU_80FB,{0U,1U,80U}}, +{DIVU_80FC,{0U,1U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SBCD_8100,{0U,1U,0U}}, +{SBCD_8100,{1U,1U,0U}}, +{SBCD_8100,{2U,1U,0U}}, +{SBCD_8100,{3U,1U,0U}}, +{SBCD_8100,{4U,1U,0U}}, +{SBCD_8100,{5U,1U,0U}}, +{SBCD_8100,{6U,1U,0U}}, +{SBCD_8100,{7U,1U,0U}}, +{SBCD_8108,{0U,1U,0U}}, +{SBCD_8108,{1U,1U,0U}}, +{SBCD_8108,{2U,1U,0U}}, +{SBCD_8108,{3U,1U,0U}}, +{SBCD_8108,{4U,1U,0U}}, +{SBCD_8108,{5U,1U,0U}}, +{SBCD_8108,{6U,1U,0U}}, +{SBCD_8108,{7U,1U,0U}}, +{OR_8110,{0U,1U,0U}}, +{OR_8110,{1U,1U,0U}}, +{OR_8110,{2U,1U,0U}}, +{OR_8110,{3U,1U,0U}}, +{OR_8110,{4U,1U,0U}}, +{OR_8110,{5U,1U,0U}}, +{OR_8110,{6U,1U,0U}}, +{OR_8110,{7U,1U,0U}}, +{OR_8118,{0U,1U,0U}}, +{OR_8118,{1U,1U,0U}}, +{OR_8118,{2U,1U,0U}}, +{OR_8118,{3U,1U,0U}}, +{OR_8118,{4U,1U,0U}}, +{OR_8118,{5U,1U,0U}}, +{OR_8118,{6U,1U,0U}}, +{OR_8118,{7U,1U,0U}}, +{OR_8120,{0U,1U,0U}}, +{OR_8120,{1U,1U,0U}}, +{OR_8120,{2U,1U,0U}}, +{OR_8120,{3U,1U,0U}}, +{OR_8120,{4U,1U,0U}}, +{OR_8120,{5U,1U,0U}}, +{OR_8120,{6U,1U,0U}}, +{OR_8120,{7U,1U,0U}}, +{OR_8128,{0U,1U,0U}}, +{OR_8128,{1U,1U,0U}}, +{OR_8128,{2U,1U,0U}}, +{OR_8128,{3U,1U,0U}}, +{OR_8128,{4U,1U,0U}}, +{OR_8128,{5U,1U,0U}}, +{OR_8128,{6U,1U,0U}}, +{OR_8128,{7U,1U,0U}}, +{OR_8130,{0U,1U,0U}}, +{OR_8130,{1U,1U,0U}}, +{OR_8130,{2U,1U,0U}}, +{OR_8130,{3U,1U,0U}}, +{OR_8130,{4U,1U,0U}}, +{OR_8130,{5U,1U,0U}}, +{OR_8130,{6U,1U,0U}}, +{OR_8130,{7U,1U,0U}}, +{OR_8138,{0U,1U,0U}}, +{OR_8139,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PACK_8140,{1U,0U,0U}}, +{PACK_8140,{1U,1U,0U}}, +{PACK_8140,{1U,2U,0U}}, +{PACK_8140,{1U,3U,0U}}, +{PACK_8140,{1U,4U,0U}}, +{PACK_8140,{1U,5U,0U}}, +{PACK_8140,{1U,6U,0U}}, +{PACK_8140,{1U,7U,0U}}, +{PACK_8148,{1U,0U,0U}}, +{PACK_8148,{1U,1U,0U}}, +{PACK_8148,{1U,2U,0U}}, +{PACK_8148,{1U,3U,0U}}, +{PACK_8148,{1U,4U,0U}}, +{PACK_8148,{1U,5U,0U}}, +{PACK_8148,{1U,6U,0U}}, +{PACK_8148,{1U,7U,0U}}, +{OR_8150,{0U,1U,0U}}, +{OR_8150,{1U,1U,0U}}, +{OR_8150,{2U,1U,0U}}, +{OR_8150,{3U,1U,0U}}, +{OR_8150,{4U,1U,0U}}, +{OR_8150,{5U,1U,0U}}, +{OR_8150,{6U,1U,0U}}, +{OR_8150,{7U,1U,0U}}, +{OR_8158,{0U,1U,0U}}, +{OR_8158,{1U,1U,0U}}, +{OR_8158,{2U,1U,0U}}, +{OR_8158,{3U,1U,0U}}, +{OR_8158,{4U,1U,0U}}, +{OR_8158,{5U,1U,0U}}, +{OR_8158,{6U,1U,0U}}, +{OR_8158,{7U,1U,0U}}, +{OR_8160,{0U,1U,0U}}, +{OR_8160,{1U,1U,0U}}, +{OR_8160,{2U,1U,0U}}, +{OR_8160,{3U,1U,0U}}, +{OR_8160,{4U,1U,0U}}, +{OR_8160,{5U,1U,0U}}, +{OR_8160,{6U,1U,0U}}, +{OR_8160,{7U,1U,0U}}, +{OR_8168,{0U,1U,0U}}, +{OR_8168,{1U,1U,0U}}, +{OR_8168,{2U,1U,0U}}, +{OR_8168,{3U,1U,0U}}, +{OR_8168,{4U,1U,0U}}, +{OR_8168,{5U,1U,0U}}, +{OR_8168,{6U,1U,0U}}, +{OR_8168,{7U,1U,0U}}, +{OR_8170,{0U,1U,0U}}, +{OR_8170,{1U,1U,0U}}, +{OR_8170,{2U,1U,0U}}, +{OR_8170,{3U,1U,0U}}, +{OR_8170,{4U,1U,0U}}, +{OR_8170,{5U,1U,0U}}, +{OR_8170,{6U,1U,0U}}, +{OR_8170,{7U,1U,0U}}, +{OR_8178,{0U,1U,0U}}, +{OR_8179,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{UNPK_8180,{1U,0U,0U}}, +{UNPK_8180,{1U,1U,0U}}, +{UNPK_8180,{1U,2U,0U}}, +{UNPK_8180,{1U,3U,0U}}, +{UNPK_8180,{1U,4U,0U}}, +{UNPK_8180,{1U,5U,0U}}, +{UNPK_8180,{1U,6U,0U}}, +{UNPK_8180,{1U,7U,0U}}, +{UNPK_8188,{1U,0U,0U}}, +{UNPK_8188,{1U,1U,0U}}, +{UNPK_8188,{1U,2U,0U}}, +{UNPK_8188,{1U,3U,0U}}, +{UNPK_8188,{1U,4U,0U}}, +{UNPK_8188,{1U,5U,0U}}, +{UNPK_8188,{1U,6U,0U}}, +{UNPK_8188,{1U,7U,0U}}, +{OR_8190,{0U,1U,0U}}, +{OR_8190,{1U,1U,0U}}, +{OR_8190,{2U,1U,0U}}, +{OR_8190,{3U,1U,0U}}, +{OR_8190,{4U,1U,0U}}, +{OR_8190,{5U,1U,0U}}, +{OR_8190,{6U,1U,0U}}, +{OR_8190,{7U,1U,0U}}, +{OR_8198,{0U,1U,0U}}, +{OR_8198,{1U,1U,0U}}, +{OR_8198,{2U,1U,0U}}, +{OR_8198,{3U,1U,0U}}, +{OR_8198,{4U,1U,0U}}, +{OR_8198,{5U,1U,0U}}, +{OR_8198,{6U,1U,0U}}, +{OR_8198,{7U,1U,0U}}, +{OR_81A0,{0U,1U,0U}}, +{OR_81A0,{1U,1U,0U}}, +{OR_81A0,{2U,1U,0U}}, +{OR_81A0,{3U,1U,0U}}, +{OR_81A0,{4U,1U,0U}}, +{OR_81A0,{5U,1U,0U}}, +{OR_81A0,{6U,1U,0U}}, +{OR_81A0,{7U,1U,0U}}, +{OR_81A8,{0U,1U,0U}}, +{OR_81A8,{1U,1U,0U}}, +{OR_81A8,{2U,1U,0U}}, +{OR_81A8,{3U,1U,0U}}, +{OR_81A8,{4U,1U,0U}}, +{OR_81A8,{5U,1U,0U}}, +{OR_81A8,{6U,1U,0U}}, +{OR_81A8,{7U,1U,0U}}, +{OR_81B0,{0U,1U,0U}}, +{OR_81B0,{1U,1U,0U}}, +{OR_81B0,{2U,1U,0U}}, +{OR_81B0,{3U,1U,0U}}, +{OR_81B0,{4U,1U,0U}}, +{OR_81B0,{5U,1U,0U}}, +{OR_81B0,{6U,1U,0U}}, +{OR_81B0,{7U,1U,0U}}, +{OR_81B8,{0U,1U,0U}}, +{OR_81B9,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81C0,{0U,1U,70U}}, +{DIVS_81C0,{1U,1U,70U}}, +{DIVS_81C0,{2U,1U,70U}}, +{DIVS_81C0,{3U,1U,70U}}, +{DIVS_81C0,{4U,1U,70U}}, +{DIVS_81C0,{5U,1U,70U}}, +{DIVS_81C0,{6U,1U,70U}}, +{DIVS_81C0,{7U,1U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81D0,{0U,1U,74U}}, +{DIVS_81D0,{1U,1U,74U}}, +{DIVS_81D0,{2U,1U,74U}}, +{DIVS_81D0,{3U,1U,74U}}, +{DIVS_81D0,{4U,1U,74U}}, +{DIVS_81D0,{5U,1U,74U}}, +{DIVS_81D0,{6U,1U,74U}}, +{DIVS_81D0,{7U,1U,74U}}, +{DIVS_81D8,{0U,1U,74U}}, +{DIVS_81D8,{1U,1U,74U}}, +{DIVS_81D8,{2U,1U,74U}}, +{DIVS_81D8,{3U,1U,74U}}, +{DIVS_81D8,{4U,1U,74U}}, +{DIVS_81D8,{5U,1U,74U}}, +{DIVS_81D8,{6U,1U,74U}}, +{DIVS_81D8,{7U,1U,74U}}, +{DIVS_81E0,{0U,1U,76U}}, +{DIVS_81E0,{1U,1U,76U}}, +{DIVS_81E0,{2U,1U,76U}}, +{DIVS_81E0,{3U,1U,76U}}, +{DIVS_81E0,{4U,1U,76U}}, +{DIVS_81E0,{5U,1U,76U}}, +{DIVS_81E0,{6U,1U,76U}}, +{DIVS_81E0,{7U,1U,76U}}, +{DIVS_81E8,{0U,1U,78U}}, +{DIVS_81E8,{1U,1U,78U}}, +{DIVS_81E8,{2U,1U,78U}}, +{DIVS_81E8,{3U,1U,78U}}, +{DIVS_81E8,{4U,1U,78U}}, +{DIVS_81E8,{5U,1U,78U}}, +{DIVS_81E8,{6U,1U,78U}}, +{DIVS_81E8,{7U,1U,78U}}, +{DIVS_81F0,{0U,1U,80U}}, +{DIVS_81F0,{1U,1U,80U}}, +{DIVS_81F0,{2U,1U,80U}}, +{DIVS_81F0,{3U,1U,80U}}, +{DIVS_81F0,{4U,1U,80U}}, +{DIVS_81F0,{5U,1U,80U}}, +{DIVS_81F0,{6U,1U,80U}}, +{DIVS_81F0,{7U,1U,80U}}, +{DIVS_81F8,{0U,1U,78U}}, +{DIVS_81F9,{0U,1U,82U}}, +{DIVS_81FA,{0U,1U,78U}}, +{DIVS_81FB,{0U,1U,80U}}, +{DIVS_81FC,{0U,1U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8000,{0U,2U,0U}}, +{OR_8000,{1U,2U,0U}}, +{OR_8000,{2U,2U,0U}}, +{OR_8000,{3U,2U,0U}}, +{OR_8000,{4U,2U,0U}}, +{OR_8000,{5U,2U,0U}}, +{OR_8000,{6U,2U,0U}}, +{OR_8000,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8010,{0U,2U,0U}}, +{OR_8010,{1U,2U,0U}}, +{OR_8010,{2U,2U,0U}}, +{OR_8010,{3U,2U,0U}}, +{OR_8010,{4U,2U,0U}}, +{OR_8010,{5U,2U,0U}}, +{OR_8010,{6U,2U,0U}}, +{OR_8010,{7U,2U,0U}}, +{OR_8018,{0U,2U,0U}}, +{OR_8018,{1U,2U,0U}}, +{OR_8018,{2U,2U,0U}}, +{OR_8018,{3U,2U,0U}}, +{OR_8018,{4U,2U,0U}}, +{OR_8018,{5U,2U,0U}}, +{OR_8018,{6U,2U,0U}}, +{OR_8018,{7U,2U,0U}}, +{OR_8020,{0U,2U,0U}}, +{OR_8020,{1U,2U,0U}}, +{OR_8020,{2U,2U,0U}}, +{OR_8020,{3U,2U,0U}}, +{OR_8020,{4U,2U,0U}}, +{OR_8020,{5U,2U,0U}}, +{OR_8020,{6U,2U,0U}}, +{OR_8020,{7U,2U,0U}}, +{OR_8028,{0U,2U,0U}}, +{OR_8028,{1U,2U,0U}}, +{OR_8028,{2U,2U,0U}}, +{OR_8028,{3U,2U,0U}}, +{OR_8028,{4U,2U,0U}}, +{OR_8028,{5U,2U,0U}}, +{OR_8028,{6U,2U,0U}}, +{OR_8028,{7U,2U,0U}}, +{OR_8030,{0U,2U,0U}}, +{OR_8030,{1U,2U,0U}}, +{OR_8030,{2U,2U,0U}}, +{OR_8030,{3U,2U,0U}}, +{OR_8030,{4U,2U,0U}}, +{OR_8030,{5U,2U,0U}}, +{OR_8030,{6U,2U,0U}}, +{OR_8030,{7U,2U,0U}}, +{OR_8038,{0U,2U,0U}}, +{OR_8039,{0U,2U,0U}}, +{OR_803A,{0U,2U,0U}}, +{OR_803B,{0U,2U,0U}}, +{OR_803C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8040,{0U,2U,0U}}, +{OR_8040,{1U,2U,0U}}, +{OR_8040,{2U,2U,0U}}, +{OR_8040,{3U,2U,0U}}, +{OR_8040,{4U,2U,0U}}, +{OR_8040,{5U,2U,0U}}, +{OR_8040,{6U,2U,0U}}, +{OR_8040,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8050,{0U,2U,0U}}, +{OR_8050,{1U,2U,0U}}, +{OR_8050,{2U,2U,0U}}, +{OR_8050,{3U,2U,0U}}, +{OR_8050,{4U,2U,0U}}, +{OR_8050,{5U,2U,0U}}, +{OR_8050,{6U,2U,0U}}, +{OR_8050,{7U,2U,0U}}, +{OR_8058,{0U,2U,0U}}, +{OR_8058,{1U,2U,0U}}, +{OR_8058,{2U,2U,0U}}, +{OR_8058,{3U,2U,0U}}, +{OR_8058,{4U,2U,0U}}, +{OR_8058,{5U,2U,0U}}, +{OR_8058,{6U,2U,0U}}, +{OR_8058,{7U,2U,0U}}, +{OR_8060,{0U,2U,0U}}, +{OR_8060,{1U,2U,0U}}, +{OR_8060,{2U,2U,0U}}, +{OR_8060,{3U,2U,0U}}, +{OR_8060,{4U,2U,0U}}, +{OR_8060,{5U,2U,0U}}, +{OR_8060,{6U,2U,0U}}, +{OR_8060,{7U,2U,0U}}, +{OR_8068,{0U,2U,0U}}, +{OR_8068,{1U,2U,0U}}, +{OR_8068,{2U,2U,0U}}, +{OR_8068,{3U,2U,0U}}, +{OR_8068,{4U,2U,0U}}, +{OR_8068,{5U,2U,0U}}, +{OR_8068,{6U,2U,0U}}, +{OR_8068,{7U,2U,0U}}, +{OR_8070,{0U,2U,0U}}, +{OR_8070,{1U,2U,0U}}, +{OR_8070,{2U,2U,0U}}, +{OR_8070,{3U,2U,0U}}, +{OR_8070,{4U,2U,0U}}, +{OR_8070,{5U,2U,0U}}, +{OR_8070,{6U,2U,0U}}, +{OR_8070,{7U,2U,0U}}, +{OR_8078,{0U,2U,0U}}, +{OR_8079,{0U,2U,0U}}, +{OR_807A,{0U,2U,0U}}, +{OR_807B,{0U,2U,0U}}, +{OR_807C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8080,{0U,2U,0U}}, +{OR_8080,{1U,2U,0U}}, +{OR_8080,{2U,2U,0U}}, +{OR_8080,{3U,2U,0U}}, +{OR_8080,{4U,2U,0U}}, +{OR_8080,{5U,2U,0U}}, +{OR_8080,{6U,2U,0U}}, +{OR_8080,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8090,{0U,2U,0U}}, +{OR_8090,{1U,2U,0U}}, +{OR_8090,{2U,2U,0U}}, +{OR_8090,{3U,2U,0U}}, +{OR_8090,{4U,2U,0U}}, +{OR_8090,{5U,2U,0U}}, +{OR_8090,{6U,2U,0U}}, +{OR_8090,{7U,2U,0U}}, +{OR_8098,{0U,2U,0U}}, +{OR_8098,{1U,2U,0U}}, +{OR_8098,{2U,2U,0U}}, +{OR_8098,{3U,2U,0U}}, +{OR_8098,{4U,2U,0U}}, +{OR_8098,{5U,2U,0U}}, +{OR_8098,{6U,2U,0U}}, +{OR_8098,{7U,2U,0U}}, +{OR_80A0,{0U,2U,0U}}, +{OR_80A0,{1U,2U,0U}}, +{OR_80A0,{2U,2U,0U}}, +{OR_80A0,{3U,2U,0U}}, +{OR_80A0,{4U,2U,0U}}, +{OR_80A0,{5U,2U,0U}}, +{OR_80A0,{6U,2U,0U}}, +{OR_80A0,{7U,2U,0U}}, +{OR_80A8,{0U,2U,0U}}, +{OR_80A8,{1U,2U,0U}}, +{OR_80A8,{2U,2U,0U}}, +{OR_80A8,{3U,2U,0U}}, +{OR_80A8,{4U,2U,0U}}, +{OR_80A8,{5U,2U,0U}}, +{OR_80A8,{6U,2U,0U}}, +{OR_80A8,{7U,2U,0U}}, +{OR_80B0,{0U,2U,0U}}, +{OR_80B0,{1U,2U,0U}}, +{OR_80B0,{2U,2U,0U}}, +{OR_80B0,{3U,2U,0U}}, +{OR_80B0,{4U,2U,0U}}, +{OR_80B0,{5U,2U,0U}}, +{OR_80B0,{6U,2U,0U}}, +{OR_80B0,{7U,2U,0U}}, +{OR_80B8,{0U,2U,0U}}, +{OR_80B9,{0U,2U,0U}}, +{OR_80BA,{0U,2U,0U}}, +{OR_80BB,{0U,2U,0U}}, +{OR_80BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80C0,{0U,2U,70U}}, +{DIVU_80C0,{1U,2U,70U}}, +{DIVU_80C0,{2U,2U,70U}}, +{DIVU_80C0,{3U,2U,70U}}, +{DIVU_80C0,{4U,2U,70U}}, +{DIVU_80C0,{5U,2U,70U}}, +{DIVU_80C0,{6U,2U,70U}}, +{DIVU_80C0,{7U,2U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80D0,{0U,2U,74U}}, +{DIVU_80D0,{1U,2U,74U}}, +{DIVU_80D0,{2U,2U,74U}}, +{DIVU_80D0,{3U,2U,74U}}, +{DIVU_80D0,{4U,2U,74U}}, +{DIVU_80D0,{5U,2U,74U}}, +{DIVU_80D0,{6U,2U,74U}}, +{DIVU_80D0,{7U,2U,74U}}, +{DIVU_80D8,{0U,2U,74U}}, +{DIVU_80D8,{1U,2U,74U}}, +{DIVU_80D8,{2U,2U,74U}}, +{DIVU_80D8,{3U,2U,74U}}, +{DIVU_80D8,{4U,2U,74U}}, +{DIVU_80D8,{5U,2U,74U}}, +{DIVU_80D8,{6U,2U,74U}}, +{DIVU_80D8,{7U,2U,74U}}, +{DIVU_80E0,{0U,2U,76U}}, +{DIVU_80E0,{1U,2U,76U}}, +{DIVU_80E0,{2U,2U,76U}}, +{DIVU_80E0,{3U,2U,76U}}, +{DIVU_80E0,{4U,2U,76U}}, +{DIVU_80E0,{5U,2U,76U}}, +{DIVU_80E0,{6U,2U,76U}}, +{DIVU_80E0,{7U,2U,76U}}, +{DIVU_80E8,{0U,2U,78U}}, +{DIVU_80E8,{1U,2U,78U}}, +{DIVU_80E8,{2U,2U,78U}}, +{DIVU_80E8,{3U,2U,78U}}, +{DIVU_80E8,{4U,2U,78U}}, +{DIVU_80E8,{5U,2U,78U}}, +{DIVU_80E8,{6U,2U,78U}}, +{DIVU_80E8,{7U,2U,78U}}, +{DIVU_80F0,{0U,2U,80U}}, +{DIVU_80F0,{1U,2U,80U}}, +{DIVU_80F0,{2U,2U,80U}}, +{DIVU_80F0,{3U,2U,80U}}, +{DIVU_80F0,{4U,2U,80U}}, +{DIVU_80F0,{5U,2U,80U}}, +{DIVU_80F0,{6U,2U,80U}}, +{DIVU_80F0,{7U,2U,80U}}, +{DIVU_80F8,{0U,2U,78U}}, +{DIVU_80F9,{0U,2U,82U}}, +{DIVU_80FA,{0U,2U,78U}}, +{DIVU_80FB,{0U,2U,80U}}, +{DIVU_80FC,{0U,2U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SBCD_8100,{0U,2U,0U}}, +{SBCD_8100,{1U,2U,0U}}, +{SBCD_8100,{2U,2U,0U}}, +{SBCD_8100,{3U,2U,0U}}, +{SBCD_8100,{4U,2U,0U}}, +{SBCD_8100,{5U,2U,0U}}, +{SBCD_8100,{6U,2U,0U}}, +{SBCD_8100,{7U,2U,0U}}, +{SBCD_8108,{0U,2U,0U}}, +{SBCD_8108,{1U,2U,0U}}, +{SBCD_8108,{2U,2U,0U}}, +{SBCD_8108,{3U,2U,0U}}, +{SBCD_8108,{4U,2U,0U}}, +{SBCD_8108,{5U,2U,0U}}, +{SBCD_8108,{6U,2U,0U}}, +{SBCD_8108,{7U,2U,0U}}, +{OR_8110,{0U,2U,0U}}, +{OR_8110,{1U,2U,0U}}, +{OR_8110,{2U,2U,0U}}, +{OR_8110,{3U,2U,0U}}, +{OR_8110,{4U,2U,0U}}, +{OR_8110,{5U,2U,0U}}, +{OR_8110,{6U,2U,0U}}, +{OR_8110,{7U,2U,0U}}, +{OR_8118,{0U,2U,0U}}, +{OR_8118,{1U,2U,0U}}, +{OR_8118,{2U,2U,0U}}, +{OR_8118,{3U,2U,0U}}, +{OR_8118,{4U,2U,0U}}, +{OR_8118,{5U,2U,0U}}, +{OR_8118,{6U,2U,0U}}, +{OR_8118,{7U,2U,0U}}, +{OR_8120,{0U,2U,0U}}, +{OR_8120,{1U,2U,0U}}, +{OR_8120,{2U,2U,0U}}, +{OR_8120,{3U,2U,0U}}, +{OR_8120,{4U,2U,0U}}, +{OR_8120,{5U,2U,0U}}, +{OR_8120,{6U,2U,0U}}, +{OR_8120,{7U,2U,0U}}, +{OR_8128,{0U,2U,0U}}, +{OR_8128,{1U,2U,0U}}, +{OR_8128,{2U,2U,0U}}, +{OR_8128,{3U,2U,0U}}, +{OR_8128,{4U,2U,0U}}, +{OR_8128,{5U,2U,0U}}, +{OR_8128,{6U,2U,0U}}, +{OR_8128,{7U,2U,0U}}, +{OR_8130,{0U,2U,0U}}, +{OR_8130,{1U,2U,0U}}, +{OR_8130,{2U,2U,0U}}, +{OR_8130,{3U,2U,0U}}, +{OR_8130,{4U,2U,0U}}, +{OR_8130,{5U,2U,0U}}, +{OR_8130,{6U,2U,0U}}, +{OR_8130,{7U,2U,0U}}, +{OR_8138,{0U,2U,0U}}, +{OR_8139,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PACK_8140,{2U,0U,0U}}, +{PACK_8140,{2U,1U,0U}}, +{PACK_8140,{2U,2U,0U}}, +{PACK_8140,{2U,3U,0U}}, +{PACK_8140,{2U,4U,0U}}, +{PACK_8140,{2U,5U,0U}}, +{PACK_8140,{2U,6U,0U}}, +{PACK_8140,{2U,7U,0U}}, +{PACK_8148,{2U,0U,0U}}, +{PACK_8148,{2U,1U,0U}}, +{PACK_8148,{2U,2U,0U}}, +{PACK_8148,{2U,3U,0U}}, +{PACK_8148,{2U,4U,0U}}, +{PACK_8148,{2U,5U,0U}}, +{PACK_8148,{2U,6U,0U}}, +{PACK_8148,{2U,7U,0U}}, +{OR_8150,{0U,2U,0U}}, +{OR_8150,{1U,2U,0U}}, +{OR_8150,{2U,2U,0U}}, +{OR_8150,{3U,2U,0U}}, +{OR_8150,{4U,2U,0U}}, +{OR_8150,{5U,2U,0U}}, +{OR_8150,{6U,2U,0U}}, +{OR_8150,{7U,2U,0U}}, +{OR_8158,{0U,2U,0U}}, +{OR_8158,{1U,2U,0U}}, +{OR_8158,{2U,2U,0U}}, +{OR_8158,{3U,2U,0U}}, +{OR_8158,{4U,2U,0U}}, +{OR_8158,{5U,2U,0U}}, +{OR_8158,{6U,2U,0U}}, +{OR_8158,{7U,2U,0U}}, +{OR_8160,{0U,2U,0U}}, +{OR_8160,{1U,2U,0U}}, +{OR_8160,{2U,2U,0U}}, +{OR_8160,{3U,2U,0U}}, +{OR_8160,{4U,2U,0U}}, +{OR_8160,{5U,2U,0U}}, +{OR_8160,{6U,2U,0U}}, +{OR_8160,{7U,2U,0U}}, +{OR_8168,{0U,2U,0U}}, +{OR_8168,{1U,2U,0U}}, +{OR_8168,{2U,2U,0U}}, +{OR_8168,{3U,2U,0U}}, +{OR_8168,{4U,2U,0U}}, +{OR_8168,{5U,2U,0U}}, +{OR_8168,{6U,2U,0U}}, +{OR_8168,{7U,2U,0U}}, +{OR_8170,{0U,2U,0U}}, +{OR_8170,{1U,2U,0U}}, +{OR_8170,{2U,2U,0U}}, +{OR_8170,{3U,2U,0U}}, +{OR_8170,{4U,2U,0U}}, +{OR_8170,{5U,2U,0U}}, +{OR_8170,{6U,2U,0U}}, +{OR_8170,{7U,2U,0U}}, +{OR_8178,{0U,2U,0U}}, +{OR_8179,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{UNPK_8180,{2U,0U,0U}}, +{UNPK_8180,{2U,1U,0U}}, +{UNPK_8180,{2U,2U,0U}}, +{UNPK_8180,{2U,3U,0U}}, +{UNPK_8180,{2U,4U,0U}}, +{UNPK_8180,{2U,5U,0U}}, +{UNPK_8180,{2U,6U,0U}}, +{UNPK_8180,{2U,7U,0U}}, +{UNPK_8188,{2U,0U,0U}}, +{UNPK_8188,{2U,1U,0U}}, +{UNPK_8188,{2U,2U,0U}}, +{UNPK_8188,{2U,3U,0U}}, +{UNPK_8188,{2U,4U,0U}}, +{UNPK_8188,{2U,5U,0U}}, +{UNPK_8188,{2U,6U,0U}}, +{UNPK_8188,{2U,7U,0U}}, +{OR_8190,{0U,2U,0U}}, +{OR_8190,{1U,2U,0U}}, +{OR_8190,{2U,2U,0U}}, +{OR_8190,{3U,2U,0U}}, +{OR_8190,{4U,2U,0U}}, +{OR_8190,{5U,2U,0U}}, +{OR_8190,{6U,2U,0U}}, +{OR_8190,{7U,2U,0U}}, +{OR_8198,{0U,2U,0U}}, +{OR_8198,{1U,2U,0U}}, +{OR_8198,{2U,2U,0U}}, +{OR_8198,{3U,2U,0U}}, +{OR_8198,{4U,2U,0U}}, +{OR_8198,{5U,2U,0U}}, +{OR_8198,{6U,2U,0U}}, +{OR_8198,{7U,2U,0U}}, +{OR_81A0,{0U,2U,0U}}, +{OR_81A0,{1U,2U,0U}}, +{OR_81A0,{2U,2U,0U}}, +{OR_81A0,{3U,2U,0U}}, +{OR_81A0,{4U,2U,0U}}, +{OR_81A0,{5U,2U,0U}}, +{OR_81A0,{6U,2U,0U}}, +{OR_81A0,{7U,2U,0U}}, +{OR_81A8,{0U,2U,0U}}, +{OR_81A8,{1U,2U,0U}}, +{OR_81A8,{2U,2U,0U}}, +{OR_81A8,{3U,2U,0U}}, +{OR_81A8,{4U,2U,0U}}, +{OR_81A8,{5U,2U,0U}}, +{OR_81A8,{6U,2U,0U}}, +{OR_81A8,{7U,2U,0U}}, +{OR_81B0,{0U,2U,0U}}, +{OR_81B0,{1U,2U,0U}}, +{OR_81B0,{2U,2U,0U}}, +{OR_81B0,{3U,2U,0U}}, +{OR_81B0,{4U,2U,0U}}, +{OR_81B0,{5U,2U,0U}}, +{OR_81B0,{6U,2U,0U}}, +{OR_81B0,{7U,2U,0U}}, +{OR_81B8,{0U,2U,0U}}, +{OR_81B9,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81C0,{0U,2U,70U}}, +{DIVS_81C0,{1U,2U,70U}}, +{DIVS_81C0,{2U,2U,70U}}, +{DIVS_81C0,{3U,2U,70U}}, +{DIVS_81C0,{4U,2U,70U}}, +{DIVS_81C0,{5U,2U,70U}}, +{DIVS_81C0,{6U,2U,70U}}, +{DIVS_81C0,{7U,2U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81D0,{0U,2U,74U}}, +{DIVS_81D0,{1U,2U,74U}}, +{DIVS_81D0,{2U,2U,74U}}, +{DIVS_81D0,{3U,2U,74U}}, +{DIVS_81D0,{4U,2U,74U}}, +{DIVS_81D0,{5U,2U,74U}}, +{DIVS_81D0,{6U,2U,74U}}, +{DIVS_81D0,{7U,2U,74U}}, +{DIVS_81D8,{0U,2U,74U}}, +{DIVS_81D8,{1U,2U,74U}}, +{DIVS_81D8,{2U,2U,74U}}, +{DIVS_81D8,{3U,2U,74U}}, +{DIVS_81D8,{4U,2U,74U}}, +{DIVS_81D8,{5U,2U,74U}}, +{DIVS_81D8,{6U,2U,74U}}, +{DIVS_81D8,{7U,2U,74U}}, +{DIVS_81E0,{0U,2U,76U}}, +{DIVS_81E0,{1U,2U,76U}}, +{DIVS_81E0,{2U,2U,76U}}, +{DIVS_81E0,{3U,2U,76U}}, +{DIVS_81E0,{4U,2U,76U}}, +{DIVS_81E0,{5U,2U,76U}}, +{DIVS_81E0,{6U,2U,76U}}, +{DIVS_81E0,{7U,2U,76U}}, +{DIVS_81E8,{0U,2U,78U}}, +{DIVS_81E8,{1U,2U,78U}}, +{DIVS_81E8,{2U,2U,78U}}, +{DIVS_81E8,{3U,2U,78U}}, +{DIVS_81E8,{4U,2U,78U}}, +{DIVS_81E8,{5U,2U,78U}}, +{DIVS_81E8,{6U,2U,78U}}, +{DIVS_81E8,{7U,2U,78U}}, +{DIVS_81F0,{0U,2U,80U}}, +{DIVS_81F0,{1U,2U,80U}}, +{DIVS_81F0,{2U,2U,80U}}, +{DIVS_81F0,{3U,2U,80U}}, +{DIVS_81F0,{4U,2U,80U}}, +{DIVS_81F0,{5U,2U,80U}}, +{DIVS_81F0,{6U,2U,80U}}, +{DIVS_81F0,{7U,2U,80U}}, +{DIVS_81F8,{0U,2U,78U}}, +{DIVS_81F9,{0U,2U,82U}}, +{DIVS_81FA,{0U,2U,78U}}, +{DIVS_81FB,{0U,2U,80U}}, +{DIVS_81FC,{0U,2U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8000,{0U,3U,0U}}, +{OR_8000,{1U,3U,0U}}, +{OR_8000,{2U,3U,0U}}, +{OR_8000,{3U,3U,0U}}, +{OR_8000,{4U,3U,0U}}, +{OR_8000,{5U,3U,0U}}, +{OR_8000,{6U,3U,0U}}, +{OR_8000,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8010,{0U,3U,0U}}, +{OR_8010,{1U,3U,0U}}, +{OR_8010,{2U,3U,0U}}, +{OR_8010,{3U,3U,0U}}, +{OR_8010,{4U,3U,0U}}, +{OR_8010,{5U,3U,0U}}, +{OR_8010,{6U,3U,0U}}, +{OR_8010,{7U,3U,0U}}, +{OR_8018,{0U,3U,0U}}, +{OR_8018,{1U,3U,0U}}, +{OR_8018,{2U,3U,0U}}, +{OR_8018,{3U,3U,0U}}, +{OR_8018,{4U,3U,0U}}, +{OR_8018,{5U,3U,0U}}, +{OR_8018,{6U,3U,0U}}, +{OR_8018,{7U,3U,0U}}, +{OR_8020,{0U,3U,0U}}, +{OR_8020,{1U,3U,0U}}, +{OR_8020,{2U,3U,0U}}, +{OR_8020,{3U,3U,0U}}, +{OR_8020,{4U,3U,0U}}, +{OR_8020,{5U,3U,0U}}, +{OR_8020,{6U,3U,0U}}, +{OR_8020,{7U,3U,0U}}, +{OR_8028,{0U,3U,0U}}, +{OR_8028,{1U,3U,0U}}, +{OR_8028,{2U,3U,0U}}, +{OR_8028,{3U,3U,0U}}, +{OR_8028,{4U,3U,0U}}, +{OR_8028,{5U,3U,0U}}, +{OR_8028,{6U,3U,0U}}, +{OR_8028,{7U,3U,0U}}, +{OR_8030,{0U,3U,0U}}, +{OR_8030,{1U,3U,0U}}, +{OR_8030,{2U,3U,0U}}, +{OR_8030,{3U,3U,0U}}, +{OR_8030,{4U,3U,0U}}, +{OR_8030,{5U,3U,0U}}, +{OR_8030,{6U,3U,0U}}, +{OR_8030,{7U,3U,0U}}, +{OR_8038,{0U,3U,0U}}, +{OR_8039,{0U,3U,0U}}, +{OR_803A,{0U,3U,0U}}, +{OR_803B,{0U,3U,0U}}, +{OR_803C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8040,{0U,3U,0U}}, +{OR_8040,{1U,3U,0U}}, +{OR_8040,{2U,3U,0U}}, +{OR_8040,{3U,3U,0U}}, +{OR_8040,{4U,3U,0U}}, +{OR_8040,{5U,3U,0U}}, +{OR_8040,{6U,3U,0U}}, +{OR_8040,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8050,{0U,3U,0U}}, +{OR_8050,{1U,3U,0U}}, +{OR_8050,{2U,3U,0U}}, +{OR_8050,{3U,3U,0U}}, +{OR_8050,{4U,3U,0U}}, +{OR_8050,{5U,3U,0U}}, +{OR_8050,{6U,3U,0U}}, +{OR_8050,{7U,3U,0U}}, +{OR_8058,{0U,3U,0U}}, +{OR_8058,{1U,3U,0U}}, +{OR_8058,{2U,3U,0U}}, +{OR_8058,{3U,3U,0U}}, +{OR_8058,{4U,3U,0U}}, +{OR_8058,{5U,3U,0U}}, +{OR_8058,{6U,3U,0U}}, +{OR_8058,{7U,3U,0U}}, +{OR_8060,{0U,3U,0U}}, +{OR_8060,{1U,3U,0U}}, +{OR_8060,{2U,3U,0U}}, +{OR_8060,{3U,3U,0U}}, +{OR_8060,{4U,3U,0U}}, +{OR_8060,{5U,3U,0U}}, +{OR_8060,{6U,3U,0U}}, +{OR_8060,{7U,3U,0U}}, +{OR_8068,{0U,3U,0U}}, +{OR_8068,{1U,3U,0U}}, +{OR_8068,{2U,3U,0U}}, +{OR_8068,{3U,3U,0U}}, +{OR_8068,{4U,3U,0U}}, +{OR_8068,{5U,3U,0U}}, +{OR_8068,{6U,3U,0U}}, +{OR_8068,{7U,3U,0U}}, +{OR_8070,{0U,3U,0U}}, +{OR_8070,{1U,3U,0U}}, +{OR_8070,{2U,3U,0U}}, +{OR_8070,{3U,3U,0U}}, +{OR_8070,{4U,3U,0U}}, +{OR_8070,{5U,3U,0U}}, +{OR_8070,{6U,3U,0U}}, +{OR_8070,{7U,3U,0U}}, +{OR_8078,{0U,3U,0U}}, +{OR_8079,{0U,3U,0U}}, +{OR_807A,{0U,3U,0U}}, +{OR_807B,{0U,3U,0U}}, +{OR_807C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8080,{0U,3U,0U}}, +{OR_8080,{1U,3U,0U}}, +{OR_8080,{2U,3U,0U}}, +{OR_8080,{3U,3U,0U}}, +{OR_8080,{4U,3U,0U}}, +{OR_8080,{5U,3U,0U}}, +{OR_8080,{6U,3U,0U}}, +{OR_8080,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8090,{0U,3U,0U}}, +{OR_8090,{1U,3U,0U}}, +{OR_8090,{2U,3U,0U}}, +{OR_8090,{3U,3U,0U}}, +{OR_8090,{4U,3U,0U}}, +{OR_8090,{5U,3U,0U}}, +{OR_8090,{6U,3U,0U}}, +{OR_8090,{7U,3U,0U}}, +{OR_8098,{0U,3U,0U}}, +{OR_8098,{1U,3U,0U}}, +{OR_8098,{2U,3U,0U}}, +{OR_8098,{3U,3U,0U}}, +{OR_8098,{4U,3U,0U}}, +{OR_8098,{5U,3U,0U}}, +{OR_8098,{6U,3U,0U}}, +{OR_8098,{7U,3U,0U}}, +{OR_80A0,{0U,3U,0U}}, +{OR_80A0,{1U,3U,0U}}, +{OR_80A0,{2U,3U,0U}}, +{OR_80A0,{3U,3U,0U}}, +{OR_80A0,{4U,3U,0U}}, +{OR_80A0,{5U,3U,0U}}, +{OR_80A0,{6U,3U,0U}}, +{OR_80A0,{7U,3U,0U}}, +{OR_80A8,{0U,3U,0U}}, +{OR_80A8,{1U,3U,0U}}, +{OR_80A8,{2U,3U,0U}}, +{OR_80A8,{3U,3U,0U}}, +{OR_80A8,{4U,3U,0U}}, +{OR_80A8,{5U,3U,0U}}, +{OR_80A8,{6U,3U,0U}}, +{OR_80A8,{7U,3U,0U}}, +{OR_80B0,{0U,3U,0U}}, +{OR_80B0,{1U,3U,0U}}, +{OR_80B0,{2U,3U,0U}}, +{OR_80B0,{3U,3U,0U}}, +{OR_80B0,{4U,3U,0U}}, +{OR_80B0,{5U,3U,0U}}, +{OR_80B0,{6U,3U,0U}}, +{OR_80B0,{7U,3U,0U}}, +{OR_80B8,{0U,3U,0U}}, +{OR_80B9,{0U,3U,0U}}, +{OR_80BA,{0U,3U,0U}}, +{OR_80BB,{0U,3U,0U}}, +{OR_80BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80C0,{0U,3U,70U}}, +{DIVU_80C0,{1U,3U,70U}}, +{DIVU_80C0,{2U,3U,70U}}, +{DIVU_80C0,{3U,3U,70U}}, +{DIVU_80C0,{4U,3U,70U}}, +{DIVU_80C0,{5U,3U,70U}}, +{DIVU_80C0,{6U,3U,70U}}, +{DIVU_80C0,{7U,3U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80D0,{0U,3U,74U}}, +{DIVU_80D0,{1U,3U,74U}}, +{DIVU_80D0,{2U,3U,74U}}, +{DIVU_80D0,{3U,3U,74U}}, +{DIVU_80D0,{4U,3U,74U}}, +{DIVU_80D0,{5U,3U,74U}}, +{DIVU_80D0,{6U,3U,74U}}, +{DIVU_80D0,{7U,3U,74U}}, +{DIVU_80D8,{0U,3U,74U}}, +{DIVU_80D8,{1U,3U,74U}}, +{DIVU_80D8,{2U,3U,74U}}, +{DIVU_80D8,{3U,3U,74U}}, +{DIVU_80D8,{4U,3U,74U}}, +{DIVU_80D8,{5U,3U,74U}}, +{DIVU_80D8,{6U,3U,74U}}, +{DIVU_80D8,{7U,3U,74U}}, +{DIVU_80E0,{0U,3U,76U}}, +{DIVU_80E0,{1U,3U,76U}}, +{DIVU_80E0,{2U,3U,76U}}, +{DIVU_80E0,{3U,3U,76U}}, +{DIVU_80E0,{4U,3U,76U}}, +{DIVU_80E0,{5U,3U,76U}}, +{DIVU_80E0,{6U,3U,76U}}, +{DIVU_80E0,{7U,3U,76U}}, +{DIVU_80E8,{0U,3U,78U}}, +{DIVU_80E8,{1U,3U,78U}}, +{DIVU_80E8,{2U,3U,78U}}, +{DIVU_80E8,{3U,3U,78U}}, +{DIVU_80E8,{4U,3U,78U}}, +{DIVU_80E8,{5U,3U,78U}}, +{DIVU_80E8,{6U,3U,78U}}, +{DIVU_80E8,{7U,3U,78U}}, +{DIVU_80F0,{0U,3U,80U}}, +{DIVU_80F0,{1U,3U,80U}}, +{DIVU_80F0,{2U,3U,80U}}, +{DIVU_80F0,{3U,3U,80U}}, +{DIVU_80F0,{4U,3U,80U}}, +{DIVU_80F0,{5U,3U,80U}}, +{DIVU_80F0,{6U,3U,80U}}, +{DIVU_80F0,{7U,3U,80U}}, +{DIVU_80F8,{0U,3U,78U}}, +{DIVU_80F9,{0U,3U,82U}}, +{DIVU_80FA,{0U,3U,78U}}, +{DIVU_80FB,{0U,3U,80U}}, +{DIVU_80FC,{0U,3U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SBCD_8100,{0U,3U,0U}}, +{SBCD_8100,{1U,3U,0U}}, +{SBCD_8100,{2U,3U,0U}}, +{SBCD_8100,{3U,3U,0U}}, +{SBCD_8100,{4U,3U,0U}}, +{SBCD_8100,{5U,3U,0U}}, +{SBCD_8100,{6U,3U,0U}}, +{SBCD_8100,{7U,3U,0U}}, +{SBCD_8108,{0U,3U,0U}}, +{SBCD_8108,{1U,3U,0U}}, +{SBCD_8108,{2U,3U,0U}}, +{SBCD_8108,{3U,3U,0U}}, +{SBCD_8108,{4U,3U,0U}}, +{SBCD_8108,{5U,3U,0U}}, +{SBCD_8108,{6U,3U,0U}}, +{SBCD_8108,{7U,3U,0U}}, +{OR_8110,{0U,3U,0U}}, +{OR_8110,{1U,3U,0U}}, +{OR_8110,{2U,3U,0U}}, +{OR_8110,{3U,3U,0U}}, +{OR_8110,{4U,3U,0U}}, +{OR_8110,{5U,3U,0U}}, +{OR_8110,{6U,3U,0U}}, +{OR_8110,{7U,3U,0U}}, +{OR_8118,{0U,3U,0U}}, +{OR_8118,{1U,3U,0U}}, +{OR_8118,{2U,3U,0U}}, +{OR_8118,{3U,3U,0U}}, +{OR_8118,{4U,3U,0U}}, +{OR_8118,{5U,3U,0U}}, +{OR_8118,{6U,3U,0U}}, +{OR_8118,{7U,3U,0U}}, +{OR_8120,{0U,3U,0U}}, +{OR_8120,{1U,3U,0U}}, +{OR_8120,{2U,3U,0U}}, +{OR_8120,{3U,3U,0U}}, +{OR_8120,{4U,3U,0U}}, +{OR_8120,{5U,3U,0U}}, +{OR_8120,{6U,3U,0U}}, +{OR_8120,{7U,3U,0U}}, +{OR_8128,{0U,3U,0U}}, +{OR_8128,{1U,3U,0U}}, +{OR_8128,{2U,3U,0U}}, +{OR_8128,{3U,3U,0U}}, +{OR_8128,{4U,3U,0U}}, +{OR_8128,{5U,3U,0U}}, +{OR_8128,{6U,3U,0U}}, +{OR_8128,{7U,3U,0U}}, +{OR_8130,{0U,3U,0U}}, +{OR_8130,{1U,3U,0U}}, +{OR_8130,{2U,3U,0U}}, +{OR_8130,{3U,3U,0U}}, +{OR_8130,{4U,3U,0U}}, +{OR_8130,{5U,3U,0U}}, +{OR_8130,{6U,3U,0U}}, +{OR_8130,{7U,3U,0U}}, +{OR_8138,{0U,3U,0U}}, +{OR_8139,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PACK_8140,{3U,0U,0U}}, +{PACK_8140,{3U,1U,0U}}, +{PACK_8140,{3U,2U,0U}}, +{PACK_8140,{3U,3U,0U}}, +{PACK_8140,{3U,4U,0U}}, +{PACK_8140,{3U,5U,0U}}, +{PACK_8140,{3U,6U,0U}}, +{PACK_8140,{3U,7U,0U}}, +{PACK_8148,{3U,0U,0U}}, +{PACK_8148,{3U,1U,0U}}, +{PACK_8148,{3U,2U,0U}}, +{PACK_8148,{3U,3U,0U}}, +{PACK_8148,{3U,4U,0U}}, +{PACK_8148,{3U,5U,0U}}, +{PACK_8148,{3U,6U,0U}}, +{PACK_8148,{3U,7U,0U}}, +{OR_8150,{0U,3U,0U}}, +{OR_8150,{1U,3U,0U}}, +{OR_8150,{2U,3U,0U}}, +{OR_8150,{3U,3U,0U}}, +{OR_8150,{4U,3U,0U}}, +{OR_8150,{5U,3U,0U}}, +{OR_8150,{6U,3U,0U}}, +{OR_8150,{7U,3U,0U}}, +{OR_8158,{0U,3U,0U}}, +{OR_8158,{1U,3U,0U}}, +{OR_8158,{2U,3U,0U}}, +{OR_8158,{3U,3U,0U}}, +{OR_8158,{4U,3U,0U}}, +{OR_8158,{5U,3U,0U}}, +{OR_8158,{6U,3U,0U}}, +{OR_8158,{7U,3U,0U}}, +{OR_8160,{0U,3U,0U}}, +{OR_8160,{1U,3U,0U}}, +{OR_8160,{2U,3U,0U}}, +{OR_8160,{3U,3U,0U}}, +{OR_8160,{4U,3U,0U}}, +{OR_8160,{5U,3U,0U}}, +{OR_8160,{6U,3U,0U}}, +{OR_8160,{7U,3U,0U}}, +{OR_8168,{0U,3U,0U}}, +{OR_8168,{1U,3U,0U}}, +{OR_8168,{2U,3U,0U}}, +{OR_8168,{3U,3U,0U}}, +{OR_8168,{4U,3U,0U}}, +{OR_8168,{5U,3U,0U}}, +{OR_8168,{6U,3U,0U}}, +{OR_8168,{7U,3U,0U}}, +{OR_8170,{0U,3U,0U}}, +{OR_8170,{1U,3U,0U}}, +{OR_8170,{2U,3U,0U}}, +{OR_8170,{3U,3U,0U}}, +{OR_8170,{4U,3U,0U}}, +{OR_8170,{5U,3U,0U}}, +{OR_8170,{6U,3U,0U}}, +{OR_8170,{7U,3U,0U}}, +{OR_8178,{0U,3U,0U}}, +{OR_8179,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{UNPK_8180,{3U,0U,0U}}, +{UNPK_8180,{3U,1U,0U}}, +{UNPK_8180,{3U,2U,0U}}, +{UNPK_8180,{3U,3U,0U}}, +{UNPK_8180,{3U,4U,0U}}, +{UNPK_8180,{3U,5U,0U}}, +{UNPK_8180,{3U,6U,0U}}, +{UNPK_8180,{3U,7U,0U}}, +{UNPK_8188,{3U,0U,0U}}, +{UNPK_8188,{3U,1U,0U}}, +{UNPK_8188,{3U,2U,0U}}, +{UNPK_8188,{3U,3U,0U}}, +{UNPK_8188,{3U,4U,0U}}, +{UNPK_8188,{3U,5U,0U}}, +{UNPK_8188,{3U,6U,0U}}, +{UNPK_8188,{3U,7U,0U}}, +{OR_8190,{0U,3U,0U}}, +{OR_8190,{1U,3U,0U}}, +{OR_8190,{2U,3U,0U}}, +{OR_8190,{3U,3U,0U}}, +{OR_8190,{4U,3U,0U}}, +{OR_8190,{5U,3U,0U}}, +{OR_8190,{6U,3U,0U}}, +{OR_8190,{7U,3U,0U}}, +{OR_8198,{0U,3U,0U}}, +{OR_8198,{1U,3U,0U}}, +{OR_8198,{2U,3U,0U}}, +{OR_8198,{3U,3U,0U}}, +{OR_8198,{4U,3U,0U}}, +{OR_8198,{5U,3U,0U}}, +{OR_8198,{6U,3U,0U}}, +{OR_8198,{7U,3U,0U}}, +{OR_81A0,{0U,3U,0U}}, +{OR_81A0,{1U,3U,0U}}, +{OR_81A0,{2U,3U,0U}}, +{OR_81A0,{3U,3U,0U}}, +{OR_81A0,{4U,3U,0U}}, +{OR_81A0,{5U,3U,0U}}, +{OR_81A0,{6U,3U,0U}}, +{OR_81A0,{7U,3U,0U}}, +{OR_81A8,{0U,3U,0U}}, +{OR_81A8,{1U,3U,0U}}, +{OR_81A8,{2U,3U,0U}}, +{OR_81A8,{3U,3U,0U}}, +{OR_81A8,{4U,3U,0U}}, +{OR_81A8,{5U,3U,0U}}, +{OR_81A8,{6U,3U,0U}}, +{OR_81A8,{7U,3U,0U}}, +{OR_81B0,{0U,3U,0U}}, +{OR_81B0,{1U,3U,0U}}, +{OR_81B0,{2U,3U,0U}}, +{OR_81B0,{3U,3U,0U}}, +{OR_81B0,{4U,3U,0U}}, +{OR_81B0,{5U,3U,0U}}, +{OR_81B0,{6U,3U,0U}}, +{OR_81B0,{7U,3U,0U}}, +{OR_81B8,{0U,3U,0U}}, +{OR_81B9,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81C0,{0U,3U,70U}}, +{DIVS_81C0,{1U,3U,70U}}, +{DIVS_81C0,{2U,3U,70U}}, +{DIVS_81C0,{3U,3U,70U}}, +{DIVS_81C0,{4U,3U,70U}}, +{DIVS_81C0,{5U,3U,70U}}, +{DIVS_81C0,{6U,3U,70U}}, +{DIVS_81C0,{7U,3U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81D0,{0U,3U,74U}}, +{DIVS_81D0,{1U,3U,74U}}, +{DIVS_81D0,{2U,3U,74U}}, +{DIVS_81D0,{3U,3U,74U}}, +{DIVS_81D0,{4U,3U,74U}}, +{DIVS_81D0,{5U,3U,74U}}, +{DIVS_81D0,{6U,3U,74U}}, +{DIVS_81D0,{7U,3U,74U}}, +{DIVS_81D8,{0U,3U,74U}}, +{DIVS_81D8,{1U,3U,74U}}, +{DIVS_81D8,{2U,3U,74U}}, +{DIVS_81D8,{3U,3U,74U}}, +{DIVS_81D8,{4U,3U,74U}}, +{DIVS_81D8,{5U,3U,74U}}, +{DIVS_81D8,{6U,3U,74U}}, +{DIVS_81D8,{7U,3U,74U}}, +{DIVS_81E0,{0U,3U,76U}}, +{DIVS_81E0,{1U,3U,76U}}, +{DIVS_81E0,{2U,3U,76U}}, +{DIVS_81E0,{3U,3U,76U}}, +{DIVS_81E0,{4U,3U,76U}}, +{DIVS_81E0,{5U,3U,76U}}, +{DIVS_81E0,{6U,3U,76U}}, +{DIVS_81E0,{7U,3U,76U}}, +{DIVS_81E8,{0U,3U,78U}}, +{DIVS_81E8,{1U,3U,78U}}, +{DIVS_81E8,{2U,3U,78U}}, +{DIVS_81E8,{3U,3U,78U}}, +{DIVS_81E8,{4U,3U,78U}}, +{DIVS_81E8,{5U,3U,78U}}, +{DIVS_81E8,{6U,3U,78U}}, +{DIVS_81E8,{7U,3U,78U}}, +{DIVS_81F0,{0U,3U,80U}}, +{DIVS_81F0,{1U,3U,80U}}, +{DIVS_81F0,{2U,3U,80U}}, +{DIVS_81F0,{3U,3U,80U}}, +{DIVS_81F0,{4U,3U,80U}}, +{DIVS_81F0,{5U,3U,80U}}, +{DIVS_81F0,{6U,3U,80U}}, +{DIVS_81F0,{7U,3U,80U}}, +{DIVS_81F8,{0U,3U,78U}}, +{DIVS_81F9,{0U,3U,82U}}, +{DIVS_81FA,{0U,3U,78U}}, +{DIVS_81FB,{0U,3U,80U}}, +{DIVS_81FC,{0U,3U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8000,{0U,4U,0U}}, +{OR_8000,{1U,4U,0U}}, +{OR_8000,{2U,4U,0U}}, +{OR_8000,{3U,4U,0U}}, +{OR_8000,{4U,4U,0U}}, +{OR_8000,{5U,4U,0U}}, +{OR_8000,{6U,4U,0U}}, +{OR_8000,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8010,{0U,4U,0U}}, +{OR_8010,{1U,4U,0U}}, +{OR_8010,{2U,4U,0U}}, +{OR_8010,{3U,4U,0U}}, +{OR_8010,{4U,4U,0U}}, +{OR_8010,{5U,4U,0U}}, +{OR_8010,{6U,4U,0U}}, +{OR_8010,{7U,4U,0U}}, +{OR_8018,{0U,4U,0U}}, +{OR_8018,{1U,4U,0U}}, +{OR_8018,{2U,4U,0U}}, +{OR_8018,{3U,4U,0U}}, +{OR_8018,{4U,4U,0U}}, +{OR_8018,{5U,4U,0U}}, +{OR_8018,{6U,4U,0U}}, +{OR_8018,{7U,4U,0U}}, +{OR_8020,{0U,4U,0U}}, +{OR_8020,{1U,4U,0U}}, +{OR_8020,{2U,4U,0U}}, +{OR_8020,{3U,4U,0U}}, +{OR_8020,{4U,4U,0U}}, +{OR_8020,{5U,4U,0U}}, +{OR_8020,{6U,4U,0U}}, +{OR_8020,{7U,4U,0U}}, +{OR_8028,{0U,4U,0U}}, +{OR_8028,{1U,4U,0U}}, +{OR_8028,{2U,4U,0U}}, +{OR_8028,{3U,4U,0U}}, +{OR_8028,{4U,4U,0U}}, +{OR_8028,{5U,4U,0U}}, +{OR_8028,{6U,4U,0U}}, +{OR_8028,{7U,4U,0U}}, +{OR_8030,{0U,4U,0U}}, +{OR_8030,{1U,4U,0U}}, +{OR_8030,{2U,4U,0U}}, +{OR_8030,{3U,4U,0U}}, +{OR_8030,{4U,4U,0U}}, +{OR_8030,{5U,4U,0U}}, +{OR_8030,{6U,4U,0U}}, +{OR_8030,{7U,4U,0U}}, +{OR_8038,{0U,4U,0U}}, +{OR_8039,{0U,4U,0U}}, +{OR_803A,{0U,4U,0U}}, +{OR_803B,{0U,4U,0U}}, +{OR_803C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8040,{0U,4U,0U}}, +{OR_8040,{1U,4U,0U}}, +{OR_8040,{2U,4U,0U}}, +{OR_8040,{3U,4U,0U}}, +{OR_8040,{4U,4U,0U}}, +{OR_8040,{5U,4U,0U}}, +{OR_8040,{6U,4U,0U}}, +{OR_8040,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8050,{0U,4U,0U}}, +{OR_8050,{1U,4U,0U}}, +{OR_8050,{2U,4U,0U}}, +{OR_8050,{3U,4U,0U}}, +{OR_8050,{4U,4U,0U}}, +{OR_8050,{5U,4U,0U}}, +{OR_8050,{6U,4U,0U}}, +{OR_8050,{7U,4U,0U}}, +{OR_8058,{0U,4U,0U}}, +{OR_8058,{1U,4U,0U}}, +{OR_8058,{2U,4U,0U}}, +{OR_8058,{3U,4U,0U}}, +{OR_8058,{4U,4U,0U}}, +{OR_8058,{5U,4U,0U}}, +{OR_8058,{6U,4U,0U}}, +{OR_8058,{7U,4U,0U}}, +{OR_8060,{0U,4U,0U}}, +{OR_8060,{1U,4U,0U}}, +{OR_8060,{2U,4U,0U}}, +{OR_8060,{3U,4U,0U}}, +{OR_8060,{4U,4U,0U}}, +{OR_8060,{5U,4U,0U}}, +{OR_8060,{6U,4U,0U}}, +{OR_8060,{7U,4U,0U}}, +{OR_8068,{0U,4U,0U}}, +{OR_8068,{1U,4U,0U}}, +{OR_8068,{2U,4U,0U}}, +{OR_8068,{3U,4U,0U}}, +{OR_8068,{4U,4U,0U}}, +{OR_8068,{5U,4U,0U}}, +{OR_8068,{6U,4U,0U}}, +{OR_8068,{7U,4U,0U}}, +{OR_8070,{0U,4U,0U}}, +{OR_8070,{1U,4U,0U}}, +{OR_8070,{2U,4U,0U}}, +{OR_8070,{3U,4U,0U}}, +{OR_8070,{4U,4U,0U}}, +{OR_8070,{5U,4U,0U}}, +{OR_8070,{6U,4U,0U}}, +{OR_8070,{7U,4U,0U}}, +{OR_8078,{0U,4U,0U}}, +{OR_8079,{0U,4U,0U}}, +{OR_807A,{0U,4U,0U}}, +{OR_807B,{0U,4U,0U}}, +{OR_807C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8080,{0U,4U,0U}}, +{OR_8080,{1U,4U,0U}}, +{OR_8080,{2U,4U,0U}}, +{OR_8080,{3U,4U,0U}}, +{OR_8080,{4U,4U,0U}}, +{OR_8080,{5U,4U,0U}}, +{OR_8080,{6U,4U,0U}}, +{OR_8080,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8090,{0U,4U,0U}}, +{OR_8090,{1U,4U,0U}}, +{OR_8090,{2U,4U,0U}}, +{OR_8090,{3U,4U,0U}}, +{OR_8090,{4U,4U,0U}}, +{OR_8090,{5U,4U,0U}}, +{OR_8090,{6U,4U,0U}}, +{OR_8090,{7U,4U,0U}}, +{OR_8098,{0U,4U,0U}}, +{OR_8098,{1U,4U,0U}}, +{OR_8098,{2U,4U,0U}}, +{OR_8098,{3U,4U,0U}}, +{OR_8098,{4U,4U,0U}}, +{OR_8098,{5U,4U,0U}}, +{OR_8098,{6U,4U,0U}}, +{OR_8098,{7U,4U,0U}}, +{OR_80A0,{0U,4U,0U}}, +{OR_80A0,{1U,4U,0U}}, +{OR_80A0,{2U,4U,0U}}, +{OR_80A0,{3U,4U,0U}}, +{OR_80A0,{4U,4U,0U}}, +{OR_80A0,{5U,4U,0U}}, +{OR_80A0,{6U,4U,0U}}, +{OR_80A0,{7U,4U,0U}}, +{OR_80A8,{0U,4U,0U}}, +{OR_80A8,{1U,4U,0U}}, +{OR_80A8,{2U,4U,0U}}, +{OR_80A8,{3U,4U,0U}}, +{OR_80A8,{4U,4U,0U}}, +{OR_80A8,{5U,4U,0U}}, +{OR_80A8,{6U,4U,0U}}, +{OR_80A8,{7U,4U,0U}}, +{OR_80B0,{0U,4U,0U}}, +{OR_80B0,{1U,4U,0U}}, +{OR_80B0,{2U,4U,0U}}, +{OR_80B0,{3U,4U,0U}}, +{OR_80B0,{4U,4U,0U}}, +{OR_80B0,{5U,4U,0U}}, +{OR_80B0,{6U,4U,0U}}, +{OR_80B0,{7U,4U,0U}}, +{OR_80B8,{0U,4U,0U}}, +{OR_80B9,{0U,4U,0U}}, +{OR_80BA,{0U,4U,0U}}, +{OR_80BB,{0U,4U,0U}}, +{OR_80BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80C0,{0U,4U,70U}}, +{DIVU_80C0,{1U,4U,70U}}, +{DIVU_80C0,{2U,4U,70U}}, +{DIVU_80C0,{3U,4U,70U}}, +{DIVU_80C0,{4U,4U,70U}}, +{DIVU_80C0,{5U,4U,70U}}, +{DIVU_80C0,{6U,4U,70U}}, +{DIVU_80C0,{7U,4U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80D0,{0U,4U,74U}}, +{DIVU_80D0,{1U,4U,74U}}, +{DIVU_80D0,{2U,4U,74U}}, +{DIVU_80D0,{3U,4U,74U}}, +{DIVU_80D0,{4U,4U,74U}}, +{DIVU_80D0,{5U,4U,74U}}, +{DIVU_80D0,{6U,4U,74U}}, +{DIVU_80D0,{7U,4U,74U}}, +{DIVU_80D8,{0U,4U,74U}}, +{DIVU_80D8,{1U,4U,74U}}, +{DIVU_80D8,{2U,4U,74U}}, +{DIVU_80D8,{3U,4U,74U}}, +{DIVU_80D8,{4U,4U,74U}}, +{DIVU_80D8,{5U,4U,74U}}, +{DIVU_80D8,{6U,4U,74U}}, +{DIVU_80D8,{7U,4U,74U}}, +{DIVU_80E0,{0U,4U,76U}}, +{DIVU_80E0,{1U,4U,76U}}, +{DIVU_80E0,{2U,4U,76U}}, +{DIVU_80E0,{3U,4U,76U}}, +{DIVU_80E0,{4U,4U,76U}}, +{DIVU_80E0,{5U,4U,76U}}, +{DIVU_80E0,{6U,4U,76U}}, +{DIVU_80E0,{7U,4U,76U}}, +{DIVU_80E8,{0U,4U,78U}}, +{DIVU_80E8,{1U,4U,78U}}, +{DIVU_80E8,{2U,4U,78U}}, +{DIVU_80E8,{3U,4U,78U}}, +{DIVU_80E8,{4U,4U,78U}}, +{DIVU_80E8,{5U,4U,78U}}, +{DIVU_80E8,{6U,4U,78U}}, +{DIVU_80E8,{7U,4U,78U}}, +{DIVU_80F0,{0U,4U,80U}}, +{DIVU_80F0,{1U,4U,80U}}, +{DIVU_80F0,{2U,4U,80U}}, +{DIVU_80F0,{3U,4U,80U}}, +{DIVU_80F0,{4U,4U,80U}}, +{DIVU_80F0,{5U,4U,80U}}, +{DIVU_80F0,{6U,4U,80U}}, +{DIVU_80F0,{7U,4U,80U}}, +{DIVU_80F8,{0U,4U,78U}}, +{DIVU_80F9,{0U,4U,82U}}, +{DIVU_80FA,{0U,4U,78U}}, +{DIVU_80FB,{0U,4U,80U}}, +{DIVU_80FC,{0U,4U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SBCD_8100,{0U,4U,0U}}, +{SBCD_8100,{1U,4U,0U}}, +{SBCD_8100,{2U,4U,0U}}, +{SBCD_8100,{3U,4U,0U}}, +{SBCD_8100,{4U,4U,0U}}, +{SBCD_8100,{5U,4U,0U}}, +{SBCD_8100,{6U,4U,0U}}, +{SBCD_8100,{7U,4U,0U}}, +{SBCD_8108,{0U,4U,0U}}, +{SBCD_8108,{1U,4U,0U}}, +{SBCD_8108,{2U,4U,0U}}, +{SBCD_8108,{3U,4U,0U}}, +{SBCD_8108,{4U,4U,0U}}, +{SBCD_8108,{5U,4U,0U}}, +{SBCD_8108,{6U,4U,0U}}, +{SBCD_8108,{7U,4U,0U}}, +{OR_8110,{0U,4U,0U}}, +{OR_8110,{1U,4U,0U}}, +{OR_8110,{2U,4U,0U}}, +{OR_8110,{3U,4U,0U}}, +{OR_8110,{4U,4U,0U}}, +{OR_8110,{5U,4U,0U}}, +{OR_8110,{6U,4U,0U}}, +{OR_8110,{7U,4U,0U}}, +{OR_8118,{0U,4U,0U}}, +{OR_8118,{1U,4U,0U}}, +{OR_8118,{2U,4U,0U}}, +{OR_8118,{3U,4U,0U}}, +{OR_8118,{4U,4U,0U}}, +{OR_8118,{5U,4U,0U}}, +{OR_8118,{6U,4U,0U}}, +{OR_8118,{7U,4U,0U}}, +{OR_8120,{0U,4U,0U}}, +{OR_8120,{1U,4U,0U}}, +{OR_8120,{2U,4U,0U}}, +{OR_8120,{3U,4U,0U}}, +{OR_8120,{4U,4U,0U}}, +{OR_8120,{5U,4U,0U}}, +{OR_8120,{6U,4U,0U}}, +{OR_8120,{7U,4U,0U}}, +{OR_8128,{0U,4U,0U}}, +{OR_8128,{1U,4U,0U}}, +{OR_8128,{2U,4U,0U}}, +{OR_8128,{3U,4U,0U}}, +{OR_8128,{4U,4U,0U}}, +{OR_8128,{5U,4U,0U}}, +{OR_8128,{6U,4U,0U}}, +{OR_8128,{7U,4U,0U}}, +{OR_8130,{0U,4U,0U}}, +{OR_8130,{1U,4U,0U}}, +{OR_8130,{2U,4U,0U}}, +{OR_8130,{3U,4U,0U}}, +{OR_8130,{4U,4U,0U}}, +{OR_8130,{5U,4U,0U}}, +{OR_8130,{6U,4U,0U}}, +{OR_8130,{7U,4U,0U}}, +{OR_8138,{0U,4U,0U}}, +{OR_8139,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PACK_8140,{4U,0U,0U}}, +{PACK_8140,{4U,1U,0U}}, +{PACK_8140,{4U,2U,0U}}, +{PACK_8140,{4U,3U,0U}}, +{PACK_8140,{4U,4U,0U}}, +{PACK_8140,{4U,5U,0U}}, +{PACK_8140,{4U,6U,0U}}, +{PACK_8140,{4U,7U,0U}}, +{PACK_8148,{4U,0U,0U}}, +{PACK_8148,{4U,1U,0U}}, +{PACK_8148,{4U,2U,0U}}, +{PACK_8148,{4U,3U,0U}}, +{PACK_8148,{4U,4U,0U}}, +{PACK_8148,{4U,5U,0U}}, +{PACK_8148,{4U,6U,0U}}, +{PACK_8148,{4U,7U,0U}}, +{OR_8150,{0U,4U,0U}}, +{OR_8150,{1U,4U,0U}}, +{OR_8150,{2U,4U,0U}}, +{OR_8150,{3U,4U,0U}}, +{OR_8150,{4U,4U,0U}}, +{OR_8150,{5U,4U,0U}}, +{OR_8150,{6U,4U,0U}}, +{OR_8150,{7U,4U,0U}}, +{OR_8158,{0U,4U,0U}}, +{OR_8158,{1U,4U,0U}}, +{OR_8158,{2U,4U,0U}}, +{OR_8158,{3U,4U,0U}}, +{OR_8158,{4U,4U,0U}}, +{OR_8158,{5U,4U,0U}}, +{OR_8158,{6U,4U,0U}}, +{OR_8158,{7U,4U,0U}}, +{OR_8160,{0U,4U,0U}}, +{OR_8160,{1U,4U,0U}}, +{OR_8160,{2U,4U,0U}}, +{OR_8160,{3U,4U,0U}}, +{OR_8160,{4U,4U,0U}}, +{OR_8160,{5U,4U,0U}}, +{OR_8160,{6U,4U,0U}}, +{OR_8160,{7U,4U,0U}}, +{OR_8168,{0U,4U,0U}}, +{OR_8168,{1U,4U,0U}}, +{OR_8168,{2U,4U,0U}}, +{OR_8168,{3U,4U,0U}}, +{OR_8168,{4U,4U,0U}}, +{OR_8168,{5U,4U,0U}}, +{OR_8168,{6U,4U,0U}}, +{OR_8168,{7U,4U,0U}}, +{OR_8170,{0U,4U,0U}}, +{OR_8170,{1U,4U,0U}}, +{OR_8170,{2U,4U,0U}}, +{OR_8170,{3U,4U,0U}}, +{OR_8170,{4U,4U,0U}}, +{OR_8170,{5U,4U,0U}}, +{OR_8170,{6U,4U,0U}}, +{OR_8170,{7U,4U,0U}}, +{OR_8178,{0U,4U,0U}}, +{OR_8179,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{UNPK_8180,{4U,0U,0U}}, +{UNPK_8180,{4U,1U,0U}}, +{UNPK_8180,{4U,2U,0U}}, +{UNPK_8180,{4U,3U,0U}}, +{UNPK_8180,{4U,4U,0U}}, +{UNPK_8180,{4U,5U,0U}}, +{UNPK_8180,{4U,6U,0U}}, +{UNPK_8180,{4U,7U,0U}}, +{UNPK_8188,{4U,0U,0U}}, +{UNPK_8188,{4U,1U,0U}}, +{UNPK_8188,{4U,2U,0U}}, +{UNPK_8188,{4U,3U,0U}}, +{UNPK_8188,{4U,4U,0U}}, +{UNPK_8188,{4U,5U,0U}}, +{UNPK_8188,{4U,6U,0U}}, +{UNPK_8188,{4U,7U,0U}}, +{OR_8190,{0U,4U,0U}}, +{OR_8190,{1U,4U,0U}}, +{OR_8190,{2U,4U,0U}}, +{OR_8190,{3U,4U,0U}}, +{OR_8190,{4U,4U,0U}}, +{OR_8190,{5U,4U,0U}}, +{OR_8190,{6U,4U,0U}}, +{OR_8190,{7U,4U,0U}}, +{OR_8198,{0U,4U,0U}}, +{OR_8198,{1U,4U,0U}}, +{OR_8198,{2U,4U,0U}}, +{OR_8198,{3U,4U,0U}}, +{OR_8198,{4U,4U,0U}}, +{OR_8198,{5U,4U,0U}}, +{OR_8198,{6U,4U,0U}}, +{OR_8198,{7U,4U,0U}}, +{OR_81A0,{0U,4U,0U}}, +{OR_81A0,{1U,4U,0U}}, +{OR_81A0,{2U,4U,0U}}, +{OR_81A0,{3U,4U,0U}}, +{OR_81A0,{4U,4U,0U}}, +{OR_81A0,{5U,4U,0U}}, +{OR_81A0,{6U,4U,0U}}, +{OR_81A0,{7U,4U,0U}}, +{OR_81A8,{0U,4U,0U}}, +{OR_81A8,{1U,4U,0U}}, +{OR_81A8,{2U,4U,0U}}, +{OR_81A8,{3U,4U,0U}}, +{OR_81A8,{4U,4U,0U}}, +{OR_81A8,{5U,4U,0U}}, +{OR_81A8,{6U,4U,0U}}, +{OR_81A8,{7U,4U,0U}}, +{OR_81B0,{0U,4U,0U}}, +{OR_81B0,{1U,4U,0U}}, +{OR_81B0,{2U,4U,0U}}, +{OR_81B0,{3U,4U,0U}}, +{OR_81B0,{4U,4U,0U}}, +{OR_81B0,{5U,4U,0U}}, +{OR_81B0,{6U,4U,0U}}, +{OR_81B0,{7U,4U,0U}}, +{OR_81B8,{0U,4U,0U}}, +{OR_81B9,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81C0,{0U,4U,70U}}, +{DIVS_81C0,{1U,4U,70U}}, +{DIVS_81C0,{2U,4U,70U}}, +{DIVS_81C0,{3U,4U,70U}}, +{DIVS_81C0,{4U,4U,70U}}, +{DIVS_81C0,{5U,4U,70U}}, +{DIVS_81C0,{6U,4U,70U}}, +{DIVS_81C0,{7U,4U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81D0,{0U,4U,74U}}, +{DIVS_81D0,{1U,4U,74U}}, +{DIVS_81D0,{2U,4U,74U}}, +{DIVS_81D0,{3U,4U,74U}}, +{DIVS_81D0,{4U,4U,74U}}, +{DIVS_81D0,{5U,4U,74U}}, +{DIVS_81D0,{6U,4U,74U}}, +{DIVS_81D0,{7U,4U,74U}}, +{DIVS_81D8,{0U,4U,74U}}, +{DIVS_81D8,{1U,4U,74U}}, +{DIVS_81D8,{2U,4U,74U}}, +{DIVS_81D8,{3U,4U,74U}}, +{DIVS_81D8,{4U,4U,74U}}, +{DIVS_81D8,{5U,4U,74U}}, +{DIVS_81D8,{6U,4U,74U}}, +{DIVS_81D8,{7U,4U,74U}}, +{DIVS_81E0,{0U,4U,76U}}, +{DIVS_81E0,{1U,4U,76U}}, +{DIVS_81E0,{2U,4U,76U}}, +{DIVS_81E0,{3U,4U,76U}}, +{DIVS_81E0,{4U,4U,76U}}, +{DIVS_81E0,{5U,4U,76U}}, +{DIVS_81E0,{6U,4U,76U}}, +{DIVS_81E0,{7U,4U,76U}}, +{DIVS_81E8,{0U,4U,78U}}, +{DIVS_81E8,{1U,4U,78U}}, +{DIVS_81E8,{2U,4U,78U}}, +{DIVS_81E8,{3U,4U,78U}}, +{DIVS_81E8,{4U,4U,78U}}, +{DIVS_81E8,{5U,4U,78U}}, +{DIVS_81E8,{6U,4U,78U}}, +{DIVS_81E8,{7U,4U,78U}}, +{DIVS_81F0,{0U,4U,80U}}, +{DIVS_81F0,{1U,4U,80U}}, +{DIVS_81F0,{2U,4U,80U}}, +{DIVS_81F0,{3U,4U,80U}}, +{DIVS_81F0,{4U,4U,80U}}, +{DIVS_81F0,{5U,4U,80U}}, +{DIVS_81F0,{6U,4U,80U}}, +{DIVS_81F0,{7U,4U,80U}}, +{DIVS_81F8,{0U,4U,78U}}, +{DIVS_81F9,{0U,4U,82U}}, +{DIVS_81FA,{0U,4U,78U}}, +{DIVS_81FB,{0U,4U,80U}}, +{DIVS_81FC,{0U,4U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8000,{0U,5U,0U}}, +{OR_8000,{1U,5U,0U}}, +{OR_8000,{2U,5U,0U}}, +{OR_8000,{3U,5U,0U}}, +{OR_8000,{4U,5U,0U}}, +{OR_8000,{5U,5U,0U}}, +{OR_8000,{6U,5U,0U}}, +{OR_8000,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8010,{0U,5U,0U}}, +{OR_8010,{1U,5U,0U}}, +{OR_8010,{2U,5U,0U}}, +{OR_8010,{3U,5U,0U}}, +{OR_8010,{4U,5U,0U}}, +{OR_8010,{5U,5U,0U}}, +{OR_8010,{6U,5U,0U}}, +{OR_8010,{7U,5U,0U}}, +{OR_8018,{0U,5U,0U}}, +{OR_8018,{1U,5U,0U}}, +{OR_8018,{2U,5U,0U}}, +{OR_8018,{3U,5U,0U}}, +{OR_8018,{4U,5U,0U}}, +{OR_8018,{5U,5U,0U}}, +{OR_8018,{6U,5U,0U}}, +{OR_8018,{7U,5U,0U}}, +{OR_8020,{0U,5U,0U}}, +{OR_8020,{1U,5U,0U}}, +{OR_8020,{2U,5U,0U}}, +{OR_8020,{3U,5U,0U}}, +{OR_8020,{4U,5U,0U}}, +{OR_8020,{5U,5U,0U}}, +{OR_8020,{6U,5U,0U}}, +{OR_8020,{7U,5U,0U}}, +{OR_8028,{0U,5U,0U}}, +{OR_8028,{1U,5U,0U}}, +{OR_8028,{2U,5U,0U}}, +{OR_8028,{3U,5U,0U}}, +{OR_8028,{4U,5U,0U}}, +{OR_8028,{5U,5U,0U}}, +{OR_8028,{6U,5U,0U}}, +{OR_8028,{7U,5U,0U}}, +{OR_8030,{0U,5U,0U}}, +{OR_8030,{1U,5U,0U}}, +{OR_8030,{2U,5U,0U}}, +{OR_8030,{3U,5U,0U}}, +{OR_8030,{4U,5U,0U}}, +{OR_8030,{5U,5U,0U}}, +{OR_8030,{6U,5U,0U}}, +{OR_8030,{7U,5U,0U}}, +{OR_8038,{0U,5U,0U}}, +{OR_8039,{0U,5U,0U}}, +{OR_803A,{0U,5U,0U}}, +{OR_803B,{0U,5U,0U}}, +{OR_803C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8040,{0U,5U,0U}}, +{OR_8040,{1U,5U,0U}}, +{OR_8040,{2U,5U,0U}}, +{OR_8040,{3U,5U,0U}}, +{OR_8040,{4U,5U,0U}}, +{OR_8040,{5U,5U,0U}}, +{OR_8040,{6U,5U,0U}}, +{OR_8040,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8050,{0U,5U,0U}}, +{OR_8050,{1U,5U,0U}}, +{OR_8050,{2U,5U,0U}}, +{OR_8050,{3U,5U,0U}}, +{OR_8050,{4U,5U,0U}}, +{OR_8050,{5U,5U,0U}}, +{OR_8050,{6U,5U,0U}}, +{OR_8050,{7U,5U,0U}}, +{OR_8058,{0U,5U,0U}}, +{OR_8058,{1U,5U,0U}}, +{OR_8058,{2U,5U,0U}}, +{OR_8058,{3U,5U,0U}}, +{OR_8058,{4U,5U,0U}}, +{OR_8058,{5U,5U,0U}}, +{OR_8058,{6U,5U,0U}}, +{OR_8058,{7U,5U,0U}}, +{OR_8060,{0U,5U,0U}}, +{OR_8060,{1U,5U,0U}}, +{OR_8060,{2U,5U,0U}}, +{OR_8060,{3U,5U,0U}}, +{OR_8060,{4U,5U,0U}}, +{OR_8060,{5U,5U,0U}}, +{OR_8060,{6U,5U,0U}}, +{OR_8060,{7U,5U,0U}}, +{OR_8068,{0U,5U,0U}}, +{OR_8068,{1U,5U,0U}}, +{OR_8068,{2U,5U,0U}}, +{OR_8068,{3U,5U,0U}}, +{OR_8068,{4U,5U,0U}}, +{OR_8068,{5U,5U,0U}}, +{OR_8068,{6U,5U,0U}}, +{OR_8068,{7U,5U,0U}}, +{OR_8070,{0U,5U,0U}}, +{OR_8070,{1U,5U,0U}}, +{OR_8070,{2U,5U,0U}}, +{OR_8070,{3U,5U,0U}}, +{OR_8070,{4U,5U,0U}}, +{OR_8070,{5U,5U,0U}}, +{OR_8070,{6U,5U,0U}}, +{OR_8070,{7U,5U,0U}}, +{OR_8078,{0U,5U,0U}}, +{OR_8079,{0U,5U,0U}}, +{OR_807A,{0U,5U,0U}}, +{OR_807B,{0U,5U,0U}}, +{OR_807C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8080,{0U,5U,0U}}, +{OR_8080,{1U,5U,0U}}, +{OR_8080,{2U,5U,0U}}, +{OR_8080,{3U,5U,0U}}, +{OR_8080,{4U,5U,0U}}, +{OR_8080,{5U,5U,0U}}, +{OR_8080,{6U,5U,0U}}, +{OR_8080,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8090,{0U,5U,0U}}, +{OR_8090,{1U,5U,0U}}, +{OR_8090,{2U,5U,0U}}, +{OR_8090,{3U,5U,0U}}, +{OR_8090,{4U,5U,0U}}, +{OR_8090,{5U,5U,0U}}, +{OR_8090,{6U,5U,0U}}, +{OR_8090,{7U,5U,0U}}, +{OR_8098,{0U,5U,0U}}, +{OR_8098,{1U,5U,0U}}, +{OR_8098,{2U,5U,0U}}, +{OR_8098,{3U,5U,0U}}, +{OR_8098,{4U,5U,0U}}, +{OR_8098,{5U,5U,0U}}, +{OR_8098,{6U,5U,0U}}, +{OR_8098,{7U,5U,0U}}, +{OR_80A0,{0U,5U,0U}}, +{OR_80A0,{1U,5U,0U}}, +{OR_80A0,{2U,5U,0U}}, +{OR_80A0,{3U,5U,0U}}, +{OR_80A0,{4U,5U,0U}}, +{OR_80A0,{5U,5U,0U}}, +{OR_80A0,{6U,5U,0U}}, +{OR_80A0,{7U,5U,0U}}, +{OR_80A8,{0U,5U,0U}}, +{OR_80A8,{1U,5U,0U}}, +{OR_80A8,{2U,5U,0U}}, +{OR_80A8,{3U,5U,0U}}, +{OR_80A8,{4U,5U,0U}}, +{OR_80A8,{5U,5U,0U}}, +{OR_80A8,{6U,5U,0U}}, +{OR_80A8,{7U,5U,0U}}, +{OR_80B0,{0U,5U,0U}}, +{OR_80B0,{1U,5U,0U}}, +{OR_80B0,{2U,5U,0U}}, +{OR_80B0,{3U,5U,0U}}, +{OR_80B0,{4U,5U,0U}}, +{OR_80B0,{5U,5U,0U}}, +{OR_80B0,{6U,5U,0U}}, +{OR_80B0,{7U,5U,0U}}, +{OR_80B8,{0U,5U,0U}}, +{OR_80B9,{0U,5U,0U}}, +{OR_80BA,{0U,5U,0U}}, +{OR_80BB,{0U,5U,0U}}, +{OR_80BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80C0,{0U,5U,70U}}, +{DIVU_80C0,{1U,5U,70U}}, +{DIVU_80C0,{2U,5U,70U}}, +{DIVU_80C0,{3U,5U,70U}}, +{DIVU_80C0,{4U,5U,70U}}, +{DIVU_80C0,{5U,5U,70U}}, +{DIVU_80C0,{6U,5U,70U}}, +{DIVU_80C0,{7U,5U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80D0,{0U,5U,74U}}, +{DIVU_80D0,{1U,5U,74U}}, +{DIVU_80D0,{2U,5U,74U}}, +{DIVU_80D0,{3U,5U,74U}}, +{DIVU_80D0,{4U,5U,74U}}, +{DIVU_80D0,{5U,5U,74U}}, +{DIVU_80D0,{6U,5U,74U}}, +{DIVU_80D0,{7U,5U,74U}}, +{DIVU_80D8,{0U,5U,74U}}, +{DIVU_80D8,{1U,5U,74U}}, +{DIVU_80D8,{2U,5U,74U}}, +{DIVU_80D8,{3U,5U,74U}}, +{DIVU_80D8,{4U,5U,74U}}, +{DIVU_80D8,{5U,5U,74U}}, +{DIVU_80D8,{6U,5U,74U}}, +{DIVU_80D8,{7U,5U,74U}}, +{DIVU_80E0,{0U,5U,76U}}, +{DIVU_80E0,{1U,5U,76U}}, +{DIVU_80E0,{2U,5U,76U}}, +{DIVU_80E0,{3U,5U,76U}}, +{DIVU_80E0,{4U,5U,76U}}, +{DIVU_80E0,{5U,5U,76U}}, +{DIVU_80E0,{6U,5U,76U}}, +{DIVU_80E0,{7U,5U,76U}}, +{DIVU_80E8,{0U,5U,78U}}, +{DIVU_80E8,{1U,5U,78U}}, +{DIVU_80E8,{2U,5U,78U}}, +{DIVU_80E8,{3U,5U,78U}}, +{DIVU_80E8,{4U,5U,78U}}, +{DIVU_80E8,{5U,5U,78U}}, +{DIVU_80E8,{6U,5U,78U}}, +{DIVU_80E8,{7U,5U,78U}}, +{DIVU_80F0,{0U,5U,80U}}, +{DIVU_80F0,{1U,5U,80U}}, +{DIVU_80F0,{2U,5U,80U}}, +{DIVU_80F0,{3U,5U,80U}}, +{DIVU_80F0,{4U,5U,80U}}, +{DIVU_80F0,{5U,5U,80U}}, +{DIVU_80F0,{6U,5U,80U}}, +{DIVU_80F0,{7U,5U,80U}}, +{DIVU_80F8,{0U,5U,78U}}, +{DIVU_80F9,{0U,5U,82U}}, +{DIVU_80FA,{0U,5U,78U}}, +{DIVU_80FB,{0U,5U,80U}}, +{DIVU_80FC,{0U,5U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SBCD_8100,{0U,5U,0U}}, +{SBCD_8100,{1U,5U,0U}}, +{SBCD_8100,{2U,5U,0U}}, +{SBCD_8100,{3U,5U,0U}}, +{SBCD_8100,{4U,5U,0U}}, +{SBCD_8100,{5U,5U,0U}}, +{SBCD_8100,{6U,5U,0U}}, +{SBCD_8100,{7U,5U,0U}}, +{SBCD_8108,{0U,5U,0U}}, +{SBCD_8108,{1U,5U,0U}}, +{SBCD_8108,{2U,5U,0U}}, +{SBCD_8108,{3U,5U,0U}}, +{SBCD_8108,{4U,5U,0U}}, +{SBCD_8108,{5U,5U,0U}}, +{SBCD_8108,{6U,5U,0U}}, +{SBCD_8108,{7U,5U,0U}}, +{OR_8110,{0U,5U,0U}}, +{OR_8110,{1U,5U,0U}}, +{OR_8110,{2U,5U,0U}}, +{OR_8110,{3U,5U,0U}}, +{OR_8110,{4U,5U,0U}}, +{OR_8110,{5U,5U,0U}}, +{OR_8110,{6U,5U,0U}}, +{OR_8110,{7U,5U,0U}}, +{OR_8118,{0U,5U,0U}}, +{OR_8118,{1U,5U,0U}}, +{OR_8118,{2U,5U,0U}}, +{OR_8118,{3U,5U,0U}}, +{OR_8118,{4U,5U,0U}}, +{OR_8118,{5U,5U,0U}}, +{OR_8118,{6U,5U,0U}}, +{OR_8118,{7U,5U,0U}}, +{OR_8120,{0U,5U,0U}}, +{OR_8120,{1U,5U,0U}}, +{OR_8120,{2U,5U,0U}}, +{OR_8120,{3U,5U,0U}}, +{OR_8120,{4U,5U,0U}}, +{OR_8120,{5U,5U,0U}}, +{OR_8120,{6U,5U,0U}}, +{OR_8120,{7U,5U,0U}}, +{OR_8128,{0U,5U,0U}}, +{OR_8128,{1U,5U,0U}}, +{OR_8128,{2U,5U,0U}}, +{OR_8128,{3U,5U,0U}}, +{OR_8128,{4U,5U,0U}}, +{OR_8128,{5U,5U,0U}}, +{OR_8128,{6U,5U,0U}}, +{OR_8128,{7U,5U,0U}}, +{OR_8130,{0U,5U,0U}}, +{OR_8130,{1U,5U,0U}}, +{OR_8130,{2U,5U,0U}}, +{OR_8130,{3U,5U,0U}}, +{OR_8130,{4U,5U,0U}}, +{OR_8130,{5U,5U,0U}}, +{OR_8130,{6U,5U,0U}}, +{OR_8130,{7U,5U,0U}}, +{OR_8138,{0U,5U,0U}}, +{OR_8139,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PACK_8140,{5U,0U,0U}}, +{PACK_8140,{5U,1U,0U}}, +{PACK_8140,{5U,2U,0U}}, +{PACK_8140,{5U,3U,0U}}, +{PACK_8140,{5U,4U,0U}}, +{PACK_8140,{5U,5U,0U}}, +{PACK_8140,{5U,6U,0U}}, +{PACK_8140,{5U,7U,0U}}, +{PACK_8148,{5U,0U,0U}}, +{PACK_8148,{5U,1U,0U}}, +{PACK_8148,{5U,2U,0U}}, +{PACK_8148,{5U,3U,0U}}, +{PACK_8148,{5U,4U,0U}}, +{PACK_8148,{5U,5U,0U}}, +{PACK_8148,{5U,6U,0U}}, +{PACK_8148,{5U,7U,0U}}, +{OR_8150,{0U,5U,0U}}, +{OR_8150,{1U,5U,0U}}, +{OR_8150,{2U,5U,0U}}, +{OR_8150,{3U,5U,0U}}, +{OR_8150,{4U,5U,0U}}, +{OR_8150,{5U,5U,0U}}, +{OR_8150,{6U,5U,0U}}, +{OR_8150,{7U,5U,0U}}, +{OR_8158,{0U,5U,0U}}, +{OR_8158,{1U,5U,0U}}, +{OR_8158,{2U,5U,0U}}, +{OR_8158,{3U,5U,0U}}, +{OR_8158,{4U,5U,0U}}, +{OR_8158,{5U,5U,0U}}, +{OR_8158,{6U,5U,0U}}, +{OR_8158,{7U,5U,0U}}, +{OR_8160,{0U,5U,0U}}, +{OR_8160,{1U,5U,0U}}, +{OR_8160,{2U,5U,0U}}, +{OR_8160,{3U,5U,0U}}, +{OR_8160,{4U,5U,0U}}, +{OR_8160,{5U,5U,0U}}, +{OR_8160,{6U,5U,0U}}, +{OR_8160,{7U,5U,0U}}, +{OR_8168,{0U,5U,0U}}, +{OR_8168,{1U,5U,0U}}, +{OR_8168,{2U,5U,0U}}, +{OR_8168,{3U,5U,0U}}, +{OR_8168,{4U,5U,0U}}, +{OR_8168,{5U,5U,0U}}, +{OR_8168,{6U,5U,0U}}, +{OR_8168,{7U,5U,0U}}, +{OR_8170,{0U,5U,0U}}, +{OR_8170,{1U,5U,0U}}, +{OR_8170,{2U,5U,0U}}, +{OR_8170,{3U,5U,0U}}, +{OR_8170,{4U,5U,0U}}, +{OR_8170,{5U,5U,0U}}, +{OR_8170,{6U,5U,0U}}, +{OR_8170,{7U,5U,0U}}, +{OR_8178,{0U,5U,0U}}, +{OR_8179,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{UNPK_8180,{5U,0U,0U}}, +{UNPK_8180,{5U,1U,0U}}, +{UNPK_8180,{5U,2U,0U}}, +{UNPK_8180,{5U,3U,0U}}, +{UNPK_8180,{5U,4U,0U}}, +{UNPK_8180,{5U,5U,0U}}, +{UNPK_8180,{5U,6U,0U}}, +{UNPK_8180,{5U,7U,0U}}, +{UNPK_8188,{5U,0U,0U}}, +{UNPK_8188,{5U,1U,0U}}, +{UNPK_8188,{5U,2U,0U}}, +{UNPK_8188,{5U,3U,0U}}, +{UNPK_8188,{5U,4U,0U}}, +{UNPK_8188,{5U,5U,0U}}, +{UNPK_8188,{5U,6U,0U}}, +{UNPK_8188,{5U,7U,0U}}, +{OR_8190,{0U,5U,0U}}, +{OR_8190,{1U,5U,0U}}, +{OR_8190,{2U,5U,0U}}, +{OR_8190,{3U,5U,0U}}, +{OR_8190,{4U,5U,0U}}, +{OR_8190,{5U,5U,0U}}, +{OR_8190,{6U,5U,0U}}, +{OR_8190,{7U,5U,0U}}, +{OR_8198,{0U,5U,0U}}, +{OR_8198,{1U,5U,0U}}, +{OR_8198,{2U,5U,0U}}, +{OR_8198,{3U,5U,0U}}, +{OR_8198,{4U,5U,0U}}, +{OR_8198,{5U,5U,0U}}, +{OR_8198,{6U,5U,0U}}, +{OR_8198,{7U,5U,0U}}, +{OR_81A0,{0U,5U,0U}}, +{OR_81A0,{1U,5U,0U}}, +{OR_81A0,{2U,5U,0U}}, +{OR_81A0,{3U,5U,0U}}, +{OR_81A0,{4U,5U,0U}}, +{OR_81A0,{5U,5U,0U}}, +{OR_81A0,{6U,5U,0U}}, +{OR_81A0,{7U,5U,0U}}, +{OR_81A8,{0U,5U,0U}}, +{OR_81A8,{1U,5U,0U}}, +{OR_81A8,{2U,5U,0U}}, +{OR_81A8,{3U,5U,0U}}, +{OR_81A8,{4U,5U,0U}}, +{OR_81A8,{5U,5U,0U}}, +{OR_81A8,{6U,5U,0U}}, +{OR_81A8,{7U,5U,0U}}, +{OR_81B0,{0U,5U,0U}}, +{OR_81B0,{1U,5U,0U}}, +{OR_81B0,{2U,5U,0U}}, +{OR_81B0,{3U,5U,0U}}, +{OR_81B0,{4U,5U,0U}}, +{OR_81B0,{5U,5U,0U}}, +{OR_81B0,{6U,5U,0U}}, +{OR_81B0,{7U,5U,0U}}, +{OR_81B8,{0U,5U,0U}}, +{OR_81B9,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81C0,{0U,5U,70U}}, +{DIVS_81C0,{1U,5U,70U}}, +{DIVS_81C0,{2U,5U,70U}}, +{DIVS_81C0,{3U,5U,70U}}, +{DIVS_81C0,{4U,5U,70U}}, +{DIVS_81C0,{5U,5U,70U}}, +{DIVS_81C0,{6U,5U,70U}}, +{DIVS_81C0,{7U,5U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81D0,{0U,5U,74U}}, +{DIVS_81D0,{1U,5U,74U}}, +{DIVS_81D0,{2U,5U,74U}}, +{DIVS_81D0,{3U,5U,74U}}, +{DIVS_81D0,{4U,5U,74U}}, +{DIVS_81D0,{5U,5U,74U}}, +{DIVS_81D0,{6U,5U,74U}}, +{DIVS_81D0,{7U,5U,74U}}, +{DIVS_81D8,{0U,5U,74U}}, +{DIVS_81D8,{1U,5U,74U}}, +{DIVS_81D8,{2U,5U,74U}}, +{DIVS_81D8,{3U,5U,74U}}, +{DIVS_81D8,{4U,5U,74U}}, +{DIVS_81D8,{5U,5U,74U}}, +{DIVS_81D8,{6U,5U,74U}}, +{DIVS_81D8,{7U,5U,74U}}, +{DIVS_81E0,{0U,5U,76U}}, +{DIVS_81E0,{1U,5U,76U}}, +{DIVS_81E0,{2U,5U,76U}}, +{DIVS_81E0,{3U,5U,76U}}, +{DIVS_81E0,{4U,5U,76U}}, +{DIVS_81E0,{5U,5U,76U}}, +{DIVS_81E0,{6U,5U,76U}}, +{DIVS_81E0,{7U,5U,76U}}, +{DIVS_81E8,{0U,5U,78U}}, +{DIVS_81E8,{1U,5U,78U}}, +{DIVS_81E8,{2U,5U,78U}}, +{DIVS_81E8,{3U,5U,78U}}, +{DIVS_81E8,{4U,5U,78U}}, +{DIVS_81E8,{5U,5U,78U}}, +{DIVS_81E8,{6U,5U,78U}}, +{DIVS_81E8,{7U,5U,78U}}, +{DIVS_81F0,{0U,5U,80U}}, +{DIVS_81F0,{1U,5U,80U}}, +{DIVS_81F0,{2U,5U,80U}}, +{DIVS_81F0,{3U,5U,80U}}, +{DIVS_81F0,{4U,5U,80U}}, +{DIVS_81F0,{5U,5U,80U}}, +{DIVS_81F0,{6U,5U,80U}}, +{DIVS_81F0,{7U,5U,80U}}, +{DIVS_81F8,{0U,5U,78U}}, +{DIVS_81F9,{0U,5U,82U}}, +{DIVS_81FA,{0U,5U,78U}}, +{DIVS_81FB,{0U,5U,80U}}, +{DIVS_81FC,{0U,5U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8000,{0U,6U,0U}}, +{OR_8000,{1U,6U,0U}}, +{OR_8000,{2U,6U,0U}}, +{OR_8000,{3U,6U,0U}}, +{OR_8000,{4U,6U,0U}}, +{OR_8000,{5U,6U,0U}}, +{OR_8000,{6U,6U,0U}}, +{OR_8000,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8010,{0U,6U,0U}}, +{OR_8010,{1U,6U,0U}}, +{OR_8010,{2U,6U,0U}}, +{OR_8010,{3U,6U,0U}}, +{OR_8010,{4U,6U,0U}}, +{OR_8010,{5U,6U,0U}}, +{OR_8010,{6U,6U,0U}}, +{OR_8010,{7U,6U,0U}}, +{OR_8018,{0U,6U,0U}}, +{OR_8018,{1U,6U,0U}}, +{OR_8018,{2U,6U,0U}}, +{OR_8018,{3U,6U,0U}}, +{OR_8018,{4U,6U,0U}}, +{OR_8018,{5U,6U,0U}}, +{OR_8018,{6U,6U,0U}}, +{OR_8018,{7U,6U,0U}}, +{OR_8020,{0U,6U,0U}}, +{OR_8020,{1U,6U,0U}}, +{OR_8020,{2U,6U,0U}}, +{OR_8020,{3U,6U,0U}}, +{OR_8020,{4U,6U,0U}}, +{OR_8020,{5U,6U,0U}}, +{OR_8020,{6U,6U,0U}}, +{OR_8020,{7U,6U,0U}}, +{OR_8028,{0U,6U,0U}}, +{OR_8028,{1U,6U,0U}}, +{OR_8028,{2U,6U,0U}}, +{OR_8028,{3U,6U,0U}}, +{OR_8028,{4U,6U,0U}}, +{OR_8028,{5U,6U,0U}}, +{OR_8028,{6U,6U,0U}}, +{OR_8028,{7U,6U,0U}}, +{OR_8030,{0U,6U,0U}}, +{OR_8030,{1U,6U,0U}}, +{OR_8030,{2U,6U,0U}}, +{OR_8030,{3U,6U,0U}}, +{OR_8030,{4U,6U,0U}}, +{OR_8030,{5U,6U,0U}}, +{OR_8030,{6U,6U,0U}}, +{OR_8030,{7U,6U,0U}}, +{OR_8038,{0U,6U,0U}}, +{OR_8039,{0U,6U,0U}}, +{OR_803A,{0U,6U,0U}}, +{OR_803B,{0U,6U,0U}}, +{OR_803C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8040,{0U,6U,0U}}, +{OR_8040,{1U,6U,0U}}, +{OR_8040,{2U,6U,0U}}, +{OR_8040,{3U,6U,0U}}, +{OR_8040,{4U,6U,0U}}, +{OR_8040,{5U,6U,0U}}, +{OR_8040,{6U,6U,0U}}, +{OR_8040,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8050,{0U,6U,0U}}, +{OR_8050,{1U,6U,0U}}, +{OR_8050,{2U,6U,0U}}, +{OR_8050,{3U,6U,0U}}, +{OR_8050,{4U,6U,0U}}, +{OR_8050,{5U,6U,0U}}, +{OR_8050,{6U,6U,0U}}, +{OR_8050,{7U,6U,0U}}, +{OR_8058,{0U,6U,0U}}, +{OR_8058,{1U,6U,0U}}, +{OR_8058,{2U,6U,0U}}, +{OR_8058,{3U,6U,0U}}, +{OR_8058,{4U,6U,0U}}, +{OR_8058,{5U,6U,0U}}, +{OR_8058,{6U,6U,0U}}, +{OR_8058,{7U,6U,0U}}, +{OR_8060,{0U,6U,0U}}, +{OR_8060,{1U,6U,0U}}, +{OR_8060,{2U,6U,0U}}, +{OR_8060,{3U,6U,0U}}, +{OR_8060,{4U,6U,0U}}, +{OR_8060,{5U,6U,0U}}, +{OR_8060,{6U,6U,0U}}, +{OR_8060,{7U,6U,0U}}, +{OR_8068,{0U,6U,0U}}, +{OR_8068,{1U,6U,0U}}, +{OR_8068,{2U,6U,0U}}, +{OR_8068,{3U,6U,0U}}, +{OR_8068,{4U,6U,0U}}, +{OR_8068,{5U,6U,0U}}, +{OR_8068,{6U,6U,0U}}, +{OR_8068,{7U,6U,0U}}, +{OR_8070,{0U,6U,0U}}, +{OR_8070,{1U,6U,0U}}, +{OR_8070,{2U,6U,0U}}, +{OR_8070,{3U,6U,0U}}, +{OR_8070,{4U,6U,0U}}, +{OR_8070,{5U,6U,0U}}, +{OR_8070,{6U,6U,0U}}, +{OR_8070,{7U,6U,0U}}, +{OR_8078,{0U,6U,0U}}, +{OR_8079,{0U,6U,0U}}, +{OR_807A,{0U,6U,0U}}, +{OR_807B,{0U,6U,0U}}, +{OR_807C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8080,{0U,6U,0U}}, +{OR_8080,{1U,6U,0U}}, +{OR_8080,{2U,6U,0U}}, +{OR_8080,{3U,6U,0U}}, +{OR_8080,{4U,6U,0U}}, +{OR_8080,{5U,6U,0U}}, +{OR_8080,{6U,6U,0U}}, +{OR_8080,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8090,{0U,6U,0U}}, +{OR_8090,{1U,6U,0U}}, +{OR_8090,{2U,6U,0U}}, +{OR_8090,{3U,6U,0U}}, +{OR_8090,{4U,6U,0U}}, +{OR_8090,{5U,6U,0U}}, +{OR_8090,{6U,6U,0U}}, +{OR_8090,{7U,6U,0U}}, +{OR_8098,{0U,6U,0U}}, +{OR_8098,{1U,6U,0U}}, +{OR_8098,{2U,6U,0U}}, +{OR_8098,{3U,6U,0U}}, +{OR_8098,{4U,6U,0U}}, +{OR_8098,{5U,6U,0U}}, +{OR_8098,{6U,6U,0U}}, +{OR_8098,{7U,6U,0U}}, +{OR_80A0,{0U,6U,0U}}, +{OR_80A0,{1U,6U,0U}}, +{OR_80A0,{2U,6U,0U}}, +{OR_80A0,{3U,6U,0U}}, +{OR_80A0,{4U,6U,0U}}, +{OR_80A0,{5U,6U,0U}}, +{OR_80A0,{6U,6U,0U}}, +{OR_80A0,{7U,6U,0U}}, +{OR_80A8,{0U,6U,0U}}, +{OR_80A8,{1U,6U,0U}}, +{OR_80A8,{2U,6U,0U}}, +{OR_80A8,{3U,6U,0U}}, +{OR_80A8,{4U,6U,0U}}, +{OR_80A8,{5U,6U,0U}}, +{OR_80A8,{6U,6U,0U}}, +{OR_80A8,{7U,6U,0U}}, +{OR_80B0,{0U,6U,0U}}, +{OR_80B0,{1U,6U,0U}}, +{OR_80B0,{2U,6U,0U}}, +{OR_80B0,{3U,6U,0U}}, +{OR_80B0,{4U,6U,0U}}, +{OR_80B0,{5U,6U,0U}}, +{OR_80B0,{6U,6U,0U}}, +{OR_80B0,{7U,6U,0U}}, +{OR_80B8,{0U,6U,0U}}, +{OR_80B9,{0U,6U,0U}}, +{OR_80BA,{0U,6U,0U}}, +{OR_80BB,{0U,6U,0U}}, +{OR_80BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80C0,{0U,6U,70U}}, +{DIVU_80C0,{1U,6U,70U}}, +{DIVU_80C0,{2U,6U,70U}}, +{DIVU_80C0,{3U,6U,70U}}, +{DIVU_80C0,{4U,6U,70U}}, +{DIVU_80C0,{5U,6U,70U}}, +{DIVU_80C0,{6U,6U,70U}}, +{DIVU_80C0,{7U,6U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80D0,{0U,6U,74U}}, +{DIVU_80D0,{1U,6U,74U}}, +{DIVU_80D0,{2U,6U,74U}}, +{DIVU_80D0,{3U,6U,74U}}, +{DIVU_80D0,{4U,6U,74U}}, +{DIVU_80D0,{5U,6U,74U}}, +{DIVU_80D0,{6U,6U,74U}}, +{DIVU_80D0,{7U,6U,74U}}, +{DIVU_80D8,{0U,6U,74U}}, +{DIVU_80D8,{1U,6U,74U}}, +{DIVU_80D8,{2U,6U,74U}}, +{DIVU_80D8,{3U,6U,74U}}, +{DIVU_80D8,{4U,6U,74U}}, +{DIVU_80D8,{5U,6U,74U}}, +{DIVU_80D8,{6U,6U,74U}}, +{DIVU_80D8,{7U,6U,74U}}, +{DIVU_80E0,{0U,6U,76U}}, +{DIVU_80E0,{1U,6U,76U}}, +{DIVU_80E0,{2U,6U,76U}}, +{DIVU_80E0,{3U,6U,76U}}, +{DIVU_80E0,{4U,6U,76U}}, +{DIVU_80E0,{5U,6U,76U}}, +{DIVU_80E0,{6U,6U,76U}}, +{DIVU_80E0,{7U,6U,76U}}, +{DIVU_80E8,{0U,6U,78U}}, +{DIVU_80E8,{1U,6U,78U}}, +{DIVU_80E8,{2U,6U,78U}}, +{DIVU_80E8,{3U,6U,78U}}, +{DIVU_80E8,{4U,6U,78U}}, +{DIVU_80E8,{5U,6U,78U}}, +{DIVU_80E8,{6U,6U,78U}}, +{DIVU_80E8,{7U,6U,78U}}, +{DIVU_80F0,{0U,6U,80U}}, +{DIVU_80F0,{1U,6U,80U}}, +{DIVU_80F0,{2U,6U,80U}}, +{DIVU_80F0,{3U,6U,80U}}, +{DIVU_80F0,{4U,6U,80U}}, +{DIVU_80F0,{5U,6U,80U}}, +{DIVU_80F0,{6U,6U,80U}}, +{DIVU_80F0,{7U,6U,80U}}, +{DIVU_80F8,{0U,6U,78U}}, +{DIVU_80F9,{0U,6U,82U}}, +{DIVU_80FA,{0U,6U,78U}}, +{DIVU_80FB,{0U,6U,80U}}, +{DIVU_80FC,{0U,6U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SBCD_8100,{0U,6U,0U}}, +{SBCD_8100,{1U,6U,0U}}, +{SBCD_8100,{2U,6U,0U}}, +{SBCD_8100,{3U,6U,0U}}, +{SBCD_8100,{4U,6U,0U}}, +{SBCD_8100,{5U,6U,0U}}, +{SBCD_8100,{6U,6U,0U}}, +{SBCD_8100,{7U,6U,0U}}, +{SBCD_8108,{0U,6U,0U}}, +{SBCD_8108,{1U,6U,0U}}, +{SBCD_8108,{2U,6U,0U}}, +{SBCD_8108,{3U,6U,0U}}, +{SBCD_8108,{4U,6U,0U}}, +{SBCD_8108,{5U,6U,0U}}, +{SBCD_8108,{6U,6U,0U}}, +{SBCD_8108,{7U,6U,0U}}, +{OR_8110,{0U,6U,0U}}, +{OR_8110,{1U,6U,0U}}, +{OR_8110,{2U,6U,0U}}, +{OR_8110,{3U,6U,0U}}, +{OR_8110,{4U,6U,0U}}, +{OR_8110,{5U,6U,0U}}, +{OR_8110,{6U,6U,0U}}, +{OR_8110,{7U,6U,0U}}, +{OR_8118,{0U,6U,0U}}, +{OR_8118,{1U,6U,0U}}, +{OR_8118,{2U,6U,0U}}, +{OR_8118,{3U,6U,0U}}, +{OR_8118,{4U,6U,0U}}, +{OR_8118,{5U,6U,0U}}, +{OR_8118,{6U,6U,0U}}, +{OR_8118,{7U,6U,0U}}, +{OR_8120,{0U,6U,0U}}, +{OR_8120,{1U,6U,0U}}, +{OR_8120,{2U,6U,0U}}, +{OR_8120,{3U,6U,0U}}, +{OR_8120,{4U,6U,0U}}, +{OR_8120,{5U,6U,0U}}, +{OR_8120,{6U,6U,0U}}, +{OR_8120,{7U,6U,0U}}, +{OR_8128,{0U,6U,0U}}, +{OR_8128,{1U,6U,0U}}, +{OR_8128,{2U,6U,0U}}, +{OR_8128,{3U,6U,0U}}, +{OR_8128,{4U,6U,0U}}, +{OR_8128,{5U,6U,0U}}, +{OR_8128,{6U,6U,0U}}, +{OR_8128,{7U,6U,0U}}, +{OR_8130,{0U,6U,0U}}, +{OR_8130,{1U,6U,0U}}, +{OR_8130,{2U,6U,0U}}, +{OR_8130,{3U,6U,0U}}, +{OR_8130,{4U,6U,0U}}, +{OR_8130,{5U,6U,0U}}, +{OR_8130,{6U,6U,0U}}, +{OR_8130,{7U,6U,0U}}, +{OR_8138,{0U,6U,0U}}, +{OR_8139,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PACK_8140,{6U,0U,0U}}, +{PACK_8140,{6U,1U,0U}}, +{PACK_8140,{6U,2U,0U}}, +{PACK_8140,{6U,3U,0U}}, +{PACK_8140,{6U,4U,0U}}, +{PACK_8140,{6U,5U,0U}}, +{PACK_8140,{6U,6U,0U}}, +{PACK_8140,{6U,7U,0U}}, +{PACK_8148,{6U,0U,0U}}, +{PACK_8148,{6U,1U,0U}}, +{PACK_8148,{6U,2U,0U}}, +{PACK_8148,{6U,3U,0U}}, +{PACK_8148,{6U,4U,0U}}, +{PACK_8148,{6U,5U,0U}}, +{PACK_8148,{6U,6U,0U}}, +{PACK_8148,{6U,7U,0U}}, +{OR_8150,{0U,6U,0U}}, +{OR_8150,{1U,6U,0U}}, +{OR_8150,{2U,6U,0U}}, +{OR_8150,{3U,6U,0U}}, +{OR_8150,{4U,6U,0U}}, +{OR_8150,{5U,6U,0U}}, +{OR_8150,{6U,6U,0U}}, +{OR_8150,{7U,6U,0U}}, +{OR_8158,{0U,6U,0U}}, +{OR_8158,{1U,6U,0U}}, +{OR_8158,{2U,6U,0U}}, +{OR_8158,{3U,6U,0U}}, +{OR_8158,{4U,6U,0U}}, +{OR_8158,{5U,6U,0U}}, +{OR_8158,{6U,6U,0U}}, +{OR_8158,{7U,6U,0U}}, +{OR_8160,{0U,6U,0U}}, +{OR_8160,{1U,6U,0U}}, +{OR_8160,{2U,6U,0U}}, +{OR_8160,{3U,6U,0U}}, +{OR_8160,{4U,6U,0U}}, +{OR_8160,{5U,6U,0U}}, +{OR_8160,{6U,6U,0U}}, +{OR_8160,{7U,6U,0U}}, +{OR_8168,{0U,6U,0U}}, +{OR_8168,{1U,6U,0U}}, +{OR_8168,{2U,6U,0U}}, +{OR_8168,{3U,6U,0U}}, +{OR_8168,{4U,6U,0U}}, +{OR_8168,{5U,6U,0U}}, +{OR_8168,{6U,6U,0U}}, +{OR_8168,{7U,6U,0U}}, +{OR_8170,{0U,6U,0U}}, +{OR_8170,{1U,6U,0U}}, +{OR_8170,{2U,6U,0U}}, +{OR_8170,{3U,6U,0U}}, +{OR_8170,{4U,6U,0U}}, +{OR_8170,{5U,6U,0U}}, +{OR_8170,{6U,6U,0U}}, +{OR_8170,{7U,6U,0U}}, +{OR_8178,{0U,6U,0U}}, +{OR_8179,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{UNPK_8180,{6U,0U,0U}}, +{UNPK_8180,{6U,1U,0U}}, +{UNPK_8180,{6U,2U,0U}}, +{UNPK_8180,{6U,3U,0U}}, +{UNPK_8180,{6U,4U,0U}}, +{UNPK_8180,{6U,5U,0U}}, +{UNPK_8180,{6U,6U,0U}}, +{UNPK_8180,{6U,7U,0U}}, +{UNPK_8188,{6U,0U,0U}}, +{UNPK_8188,{6U,1U,0U}}, +{UNPK_8188,{6U,2U,0U}}, +{UNPK_8188,{6U,3U,0U}}, +{UNPK_8188,{6U,4U,0U}}, +{UNPK_8188,{6U,5U,0U}}, +{UNPK_8188,{6U,6U,0U}}, +{UNPK_8188,{6U,7U,0U}}, +{OR_8190,{0U,6U,0U}}, +{OR_8190,{1U,6U,0U}}, +{OR_8190,{2U,6U,0U}}, +{OR_8190,{3U,6U,0U}}, +{OR_8190,{4U,6U,0U}}, +{OR_8190,{5U,6U,0U}}, +{OR_8190,{6U,6U,0U}}, +{OR_8190,{7U,6U,0U}}, +{OR_8198,{0U,6U,0U}}, +{OR_8198,{1U,6U,0U}}, +{OR_8198,{2U,6U,0U}}, +{OR_8198,{3U,6U,0U}}, +{OR_8198,{4U,6U,0U}}, +{OR_8198,{5U,6U,0U}}, +{OR_8198,{6U,6U,0U}}, +{OR_8198,{7U,6U,0U}}, +{OR_81A0,{0U,6U,0U}}, +{OR_81A0,{1U,6U,0U}}, +{OR_81A0,{2U,6U,0U}}, +{OR_81A0,{3U,6U,0U}}, +{OR_81A0,{4U,6U,0U}}, +{OR_81A0,{5U,6U,0U}}, +{OR_81A0,{6U,6U,0U}}, +{OR_81A0,{7U,6U,0U}}, +{OR_81A8,{0U,6U,0U}}, +{OR_81A8,{1U,6U,0U}}, +{OR_81A8,{2U,6U,0U}}, +{OR_81A8,{3U,6U,0U}}, +{OR_81A8,{4U,6U,0U}}, +{OR_81A8,{5U,6U,0U}}, +{OR_81A8,{6U,6U,0U}}, +{OR_81A8,{7U,6U,0U}}, +{OR_81B0,{0U,6U,0U}}, +{OR_81B0,{1U,6U,0U}}, +{OR_81B0,{2U,6U,0U}}, +{OR_81B0,{3U,6U,0U}}, +{OR_81B0,{4U,6U,0U}}, +{OR_81B0,{5U,6U,0U}}, +{OR_81B0,{6U,6U,0U}}, +{OR_81B0,{7U,6U,0U}}, +{OR_81B8,{0U,6U,0U}}, +{OR_81B9,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81C0,{0U,6U,70U}}, +{DIVS_81C0,{1U,6U,70U}}, +{DIVS_81C0,{2U,6U,70U}}, +{DIVS_81C0,{3U,6U,70U}}, +{DIVS_81C0,{4U,6U,70U}}, +{DIVS_81C0,{5U,6U,70U}}, +{DIVS_81C0,{6U,6U,70U}}, +{DIVS_81C0,{7U,6U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81D0,{0U,6U,74U}}, +{DIVS_81D0,{1U,6U,74U}}, +{DIVS_81D0,{2U,6U,74U}}, +{DIVS_81D0,{3U,6U,74U}}, +{DIVS_81D0,{4U,6U,74U}}, +{DIVS_81D0,{5U,6U,74U}}, +{DIVS_81D0,{6U,6U,74U}}, +{DIVS_81D0,{7U,6U,74U}}, +{DIVS_81D8,{0U,6U,74U}}, +{DIVS_81D8,{1U,6U,74U}}, +{DIVS_81D8,{2U,6U,74U}}, +{DIVS_81D8,{3U,6U,74U}}, +{DIVS_81D8,{4U,6U,74U}}, +{DIVS_81D8,{5U,6U,74U}}, +{DIVS_81D8,{6U,6U,74U}}, +{DIVS_81D8,{7U,6U,74U}}, +{DIVS_81E0,{0U,6U,76U}}, +{DIVS_81E0,{1U,6U,76U}}, +{DIVS_81E0,{2U,6U,76U}}, +{DIVS_81E0,{3U,6U,76U}}, +{DIVS_81E0,{4U,6U,76U}}, +{DIVS_81E0,{5U,6U,76U}}, +{DIVS_81E0,{6U,6U,76U}}, +{DIVS_81E0,{7U,6U,76U}}, +{DIVS_81E8,{0U,6U,78U}}, +{DIVS_81E8,{1U,6U,78U}}, +{DIVS_81E8,{2U,6U,78U}}, +{DIVS_81E8,{3U,6U,78U}}, +{DIVS_81E8,{4U,6U,78U}}, +{DIVS_81E8,{5U,6U,78U}}, +{DIVS_81E8,{6U,6U,78U}}, +{DIVS_81E8,{7U,6U,78U}}, +{DIVS_81F0,{0U,6U,80U}}, +{DIVS_81F0,{1U,6U,80U}}, +{DIVS_81F0,{2U,6U,80U}}, +{DIVS_81F0,{3U,6U,80U}}, +{DIVS_81F0,{4U,6U,80U}}, +{DIVS_81F0,{5U,6U,80U}}, +{DIVS_81F0,{6U,6U,80U}}, +{DIVS_81F0,{7U,6U,80U}}, +{DIVS_81F8,{0U,6U,78U}}, +{DIVS_81F9,{0U,6U,82U}}, +{DIVS_81FA,{0U,6U,78U}}, +{DIVS_81FB,{0U,6U,80U}}, +{DIVS_81FC,{0U,6U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8000,{0U,7U,0U}}, +{OR_8000,{1U,7U,0U}}, +{OR_8000,{2U,7U,0U}}, +{OR_8000,{3U,7U,0U}}, +{OR_8000,{4U,7U,0U}}, +{OR_8000,{5U,7U,0U}}, +{OR_8000,{6U,7U,0U}}, +{OR_8000,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8010,{0U,7U,0U}}, +{OR_8010,{1U,7U,0U}}, +{OR_8010,{2U,7U,0U}}, +{OR_8010,{3U,7U,0U}}, +{OR_8010,{4U,7U,0U}}, +{OR_8010,{5U,7U,0U}}, +{OR_8010,{6U,7U,0U}}, +{OR_8010,{7U,7U,0U}}, +{OR_8018,{0U,7U,0U}}, +{OR_8018,{1U,7U,0U}}, +{OR_8018,{2U,7U,0U}}, +{OR_8018,{3U,7U,0U}}, +{OR_8018,{4U,7U,0U}}, +{OR_8018,{5U,7U,0U}}, +{OR_8018,{6U,7U,0U}}, +{OR_8018,{7U,7U,0U}}, +{OR_8020,{0U,7U,0U}}, +{OR_8020,{1U,7U,0U}}, +{OR_8020,{2U,7U,0U}}, +{OR_8020,{3U,7U,0U}}, +{OR_8020,{4U,7U,0U}}, +{OR_8020,{5U,7U,0U}}, +{OR_8020,{6U,7U,0U}}, +{OR_8020,{7U,7U,0U}}, +{OR_8028,{0U,7U,0U}}, +{OR_8028,{1U,7U,0U}}, +{OR_8028,{2U,7U,0U}}, +{OR_8028,{3U,7U,0U}}, +{OR_8028,{4U,7U,0U}}, +{OR_8028,{5U,7U,0U}}, +{OR_8028,{6U,7U,0U}}, +{OR_8028,{7U,7U,0U}}, +{OR_8030,{0U,7U,0U}}, +{OR_8030,{1U,7U,0U}}, +{OR_8030,{2U,7U,0U}}, +{OR_8030,{3U,7U,0U}}, +{OR_8030,{4U,7U,0U}}, +{OR_8030,{5U,7U,0U}}, +{OR_8030,{6U,7U,0U}}, +{OR_8030,{7U,7U,0U}}, +{OR_8038,{0U,7U,0U}}, +{OR_8039,{0U,7U,0U}}, +{OR_803A,{0U,7U,0U}}, +{OR_803B,{0U,7U,0U}}, +{OR_803C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8040,{0U,7U,0U}}, +{OR_8040,{1U,7U,0U}}, +{OR_8040,{2U,7U,0U}}, +{OR_8040,{3U,7U,0U}}, +{OR_8040,{4U,7U,0U}}, +{OR_8040,{5U,7U,0U}}, +{OR_8040,{6U,7U,0U}}, +{OR_8040,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8050,{0U,7U,0U}}, +{OR_8050,{1U,7U,0U}}, +{OR_8050,{2U,7U,0U}}, +{OR_8050,{3U,7U,0U}}, +{OR_8050,{4U,7U,0U}}, +{OR_8050,{5U,7U,0U}}, +{OR_8050,{6U,7U,0U}}, +{OR_8050,{7U,7U,0U}}, +{OR_8058,{0U,7U,0U}}, +{OR_8058,{1U,7U,0U}}, +{OR_8058,{2U,7U,0U}}, +{OR_8058,{3U,7U,0U}}, +{OR_8058,{4U,7U,0U}}, +{OR_8058,{5U,7U,0U}}, +{OR_8058,{6U,7U,0U}}, +{OR_8058,{7U,7U,0U}}, +{OR_8060,{0U,7U,0U}}, +{OR_8060,{1U,7U,0U}}, +{OR_8060,{2U,7U,0U}}, +{OR_8060,{3U,7U,0U}}, +{OR_8060,{4U,7U,0U}}, +{OR_8060,{5U,7U,0U}}, +{OR_8060,{6U,7U,0U}}, +{OR_8060,{7U,7U,0U}}, +{OR_8068,{0U,7U,0U}}, +{OR_8068,{1U,7U,0U}}, +{OR_8068,{2U,7U,0U}}, +{OR_8068,{3U,7U,0U}}, +{OR_8068,{4U,7U,0U}}, +{OR_8068,{5U,7U,0U}}, +{OR_8068,{6U,7U,0U}}, +{OR_8068,{7U,7U,0U}}, +{OR_8070,{0U,7U,0U}}, +{OR_8070,{1U,7U,0U}}, +{OR_8070,{2U,7U,0U}}, +{OR_8070,{3U,7U,0U}}, +{OR_8070,{4U,7U,0U}}, +{OR_8070,{5U,7U,0U}}, +{OR_8070,{6U,7U,0U}}, +{OR_8070,{7U,7U,0U}}, +{OR_8078,{0U,7U,0U}}, +{OR_8079,{0U,7U,0U}}, +{OR_807A,{0U,7U,0U}}, +{OR_807B,{0U,7U,0U}}, +{OR_807C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8080,{0U,7U,0U}}, +{OR_8080,{1U,7U,0U}}, +{OR_8080,{2U,7U,0U}}, +{OR_8080,{3U,7U,0U}}, +{OR_8080,{4U,7U,0U}}, +{OR_8080,{5U,7U,0U}}, +{OR_8080,{6U,7U,0U}}, +{OR_8080,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{OR_8090,{0U,7U,0U}}, +{OR_8090,{1U,7U,0U}}, +{OR_8090,{2U,7U,0U}}, +{OR_8090,{3U,7U,0U}}, +{OR_8090,{4U,7U,0U}}, +{OR_8090,{5U,7U,0U}}, +{OR_8090,{6U,7U,0U}}, +{OR_8090,{7U,7U,0U}}, +{OR_8098,{0U,7U,0U}}, +{OR_8098,{1U,7U,0U}}, +{OR_8098,{2U,7U,0U}}, +{OR_8098,{3U,7U,0U}}, +{OR_8098,{4U,7U,0U}}, +{OR_8098,{5U,7U,0U}}, +{OR_8098,{6U,7U,0U}}, +{OR_8098,{7U,7U,0U}}, +{OR_80A0,{0U,7U,0U}}, +{OR_80A0,{1U,7U,0U}}, +{OR_80A0,{2U,7U,0U}}, +{OR_80A0,{3U,7U,0U}}, +{OR_80A0,{4U,7U,0U}}, +{OR_80A0,{5U,7U,0U}}, +{OR_80A0,{6U,7U,0U}}, +{OR_80A0,{7U,7U,0U}}, +{OR_80A8,{0U,7U,0U}}, +{OR_80A8,{1U,7U,0U}}, +{OR_80A8,{2U,7U,0U}}, +{OR_80A8,{3U,7U,0U}}, +{OR_80A8,{4U,7U,0U}}, +{OR_80A8,{5U,7U,0U}}, +{OR_80A8,{6U,7U,0U}}, +{OR_80A8,{7U,7U,0U}}, +{OR_80B0,{0U,7U,0U}}, +{OR_80B0,{1U,7U,0U}}, +{OR_80B0,{2U,7U,0U}}, +{OR_80B0,{3U,7U,0U}}, +{OR_80B0,{4U,7U,0U}}, +{OR_80B0,{5U,7U,0U}}, +{OR_80B0,{6U,7U,0U}}, +{OR_80B0,{7U,7U,0U}}, +{OR_80B8,{0U,7U,0U}}, +{OR_80B9,{0U,7U,0U}}, +{OR_80BA,{0U,7U,0U}}, +{OR_80BB,{0U,7U,0U}}, +{OR_80BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80C0,{0U,7U,70U}}, +{DIVU_80C0,{1U,7U,70U}}, +{DIVU_80C0,{2U,7U,70U}}, +{DIVU_80C0,{3U,7U,70U}}, +{DIVU_80C0,{4U,7U,70U}}, +{DIVU_80C0,{5U,7U,70U}}, +{DIVU_80C0,{6U,7U,70U}}, +{DIVU_80C0,{7U,7U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVU_80D0,{0U,7U,74U}}, +{DIVU_80D0,{1U,7U,74U}}, +{DIVU_80D0,{2U,7U,74U}}, +{DIVU_80D0,{3U,7U,74U}}, +{DIVU_80D0,{4U,7U,74U}}, +{DIVU_80D0,{5U,7U,74U}}, +{DIVU_80D0,{6U,7U,74U}}, +{DIVU_80D0,{7U,7U,74U}}, +{DIVU_80D8,{0U,7U,74U}}, +{DIVU_80D8,{1U,7U,74U}}, +{DIVU_80D8,{2U,7U,74U}}, +{DIVU_80D8,{3U,7U,74U}}, +{DIVU_80D8,{4U,7U,74U}}, +{DIVU_80D8,{5U,7U,74U}}, +{DIVU_80D8,{6U,7U,74U}}, +{DIVU_80D8,{7U,7U,74U}}, +{DIVU_80E0,{0U,7U,76U}}, +{DIVU_80E0,{1U,7U,76U}}, +{DIVU_80E0,{2U,7U,76U}}, +{DIVU_80E0,{3U,7U,76U}}, +{DIVU_80E0,{4U,7U,76U}}, +{DIVU_80E0,{5U,7U,76U}}, +{DIVU_80E0,{6U,7U,76U}}, +{DIVU_80E0,{7U,7U,76U}}, +{DIVU_80E8,{0U,7U,78U}}, +{DIVU_80E8,{1U,7U,78U}}, +{DIVU_80E8,{2U,7U,78U}}, +{DIVU_80E8,{3U,7U,78U}}, +{DIVU_80E8,{4U,7U,78U}}, +{DIVU_80E8,{5U,7U,78U}}, +{DIVU_80E8,{6U,7U,78U}}, +{DIVU_80E8,{7U,7U,78U}}, +{DIVU_80F0,{0U,7U,80U}}, +{DIVU_80F0,{1U,7U,80U}}, +{DIVU_80F0,{2U,7U,80U}}, +{DIVU_80F0,{3U,7U,80U}}, +{DIVU_80F0,{4U,7U,80U}}, +{DIVU_80F0,{5U,7U,80U}}, +{DIVU_80F0,{6U,7U,80U}}, +{DIVU_80F0,{7U,7U,80U}}, +{DIVU_80F8,{0U,7U,78U}}, +{DIVU_80F9,{0U,7U,82U}}, +{DIVU_80FA,{0U,7U,78U}}, +{DIVU_80FB,{0U,7U,80U}}, +{DIVU_80FC,{0U,7U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SBCD_8100,{0U,7U,0U}}, +{SBCD_8100,{1U,7U,0U}}, +{SBCD_8100,{2U,7U,0U}}, +{SBCD_8100,{3U,7U,0U}}, +{SBCD_8100,{4U,7U,0U}}, +{SBCD_8100,{5U,7U,0U}}, +{SBCD_8100,{6U,7U,0U}}, +{SBCD_8100,{7U,7U,0U}}, +{SBCD_8108,{0U,7U,0U}}, +{SBCD_8108,{1U,7U,0U}}, +{SBCD_8108,{2U,7U,0U}}, +{SBCD_8108,{3U,7U,0U}}, +{SBCD_8108,{4U,7U,0U}}, +{SBCD_8108,{5U,7U,0U}}, +{SBCD_8108,{6U,7U,0U}}, +{SBCD_8108,{7U,7U,0U}}, +{OR_8110,{0U,7U,0U}}, +{OR_8110,{1U,7U,0U}}, +{OR_8110,{2U,7U,0U}}, +{OR_8110,{3U,7U,0U}}, +{OR_8110,{4U,7U,0U}}, +{OR_8110,{5U,7U,0U}}, +{OR_8110,{6U,7U,0U}}, +{OR_8110,{7U,7U,0U}}, +{OR_8118,{0U,7U,0U}}, +{OR_8118,{1U,7U,0U}}, +{OR_8118,{2U,7U,0U}}, +{OR_8118,{3U,7U,0U}}, +{OR_8118,{4U,7U,0U}}, +{OR_8118,{5U,7U,0U}}, +{OR_8118,{6U,7U,0U}}, +{OR_8118,{7U,7U,0U}}, +{OR_8120,{0U,7U,0U}}, +{OR_8120,{1U,7U,0U}}, +{OR_8120,{2U,7U,0U}}, +{OR_8120,{3U,7U,0U}}, +{OR_8120,{4U,7U,0U}}, +{OR_8120,{5U,7U,0U}}, +{OR_8120,{6U,7U,0U}}, +{OR_8120,{7U,7U,0U}}, +{OR_8128,{0U,7U,0U}}, +{OR_8128,{1U,7U,0U}}, +{OR_8128,{2U,7U,0U}}, +{OR_8128,{3U,7U,0U}}, +{OR_8128,{4U,7U,0U}}, +{OR_8128,{5U,7U,0U}}, +{OR_8128,{6U,7U,0U}}, +{OR_8128,{7U,7U,0U}}, +{OR_8130,{0U,7U,0U}}, +{OR_8130,{1U,7U,0U}}, +{OR_8130,{2U,7U,0U}}, +{OR_8130,{3U,7U,0U}}, +{OR_8130,{4U,7U,0U}}, +{OR_8130,{5U,7U,0U}}, +{OR_8130,{6U,7U,0U}}, +{OR_8130,{7U,7U,0U}}, +{OR_8138,{0U,7U,0U}}, +{OR_8139,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PACK_8140,{7U,0U,0U}}, +{PACK_8140,{7U,1U,0U}}, +{PACK_8140,{7U,2U,0U}}, +{PACK_8140,{7U,3U,0U}}, +{PACK_8140,{7U,4U,0U}}, +{PACK_8140,{7U,5U,0U}}, +{PACK_8140,{7U,6U,0U}}, +{PACK_8140,{7U,7U,0U}}, +{PACK_8148,{7U,0U,0U}}, +{PACK_8148,{7U,1U,0U}}, +{PACK_8148,{7U,2U,0U}}, +{PACK_8148,{7U,3U,0U}}, +{PACK_8148,{7U,4U,0U}}, +{PACK_8148,{7U,5U,0U}}, +{PACK_8148,{7U,6U,0U}}, +{PACK_8148,{7U,7U,0U}}, +{OR_8150,{0U,7U,0U}}, +{OR_8150,{1U,7U,0U}}, +{OR_8150,{2U,7U,0U}}, +{OR_8150,{3U,7U,0U}}, +{OR_8150,{4U,7U,0U}}, +{OR_8150,{5U,7U,0U}}, +{OR_8150,{6U,7U,0U}}, +{OR_8150,{7U,7U,0U}}, +{OR_8158,{0U,7U,0U}}, +{OR_8158,{1U,7U,0U}}, +{OR_8158,{2U,7U,0U}}, +{OR_8158,{3U,7U,0U}}, +{OR_8158,{4U,7U,0U}}, +{OR_8158,{5U,7U,0U}}, +{OR_8158,{6U,7U,0U}}, +{OR_8158,{7U,7U,0U}}, +{OR_8160,{0U,7U,0U}}, +{OR_8160,{1U,7U,0U}}, +{OR_8160,{2U,7U,0U}}, +{OR_8160,{3U,7U,0U}}, +{OR_8160,{4U,7U,0U}}, +{OR_8160,{5U,7U,0U}}, +{OR_8160,{6U,7U,0U}}, +{OR_8160,{7U,7U,0U}}, +{OR_8168,{0U,7U,0U}}, +{OR_8168,{1U,7U,0U}}, +{OR_8168,{2U,7U,0U}}, +{OR_8168,{3U,7U,0U}}, +{OR_8168,{4U,7U,0U}}, +{OR_8168,{5U,7U,0U}}, +{OR_8168,{6U,7U,0U}}, +{OR_8168,{7U,7U,0U}}, +{OR_8170,{0U,7U,0U}}, +{OR_8170,{1U,7U,0U}}, +{OR_8170,{2U,7U,0U}}, +{OR_8170,{3U,7U,0U}}, +{OR_8170,{4U,7U,0U}}, +{OR_8170,{5U,7U,0U}}, +{OR_8170,{6U,7U,0U}}, +{OR_8170,{7U,7U,0U}}, +{OR_8178,{0U,7U,0U}}, +{OR_8179,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{UNPK_8180,{7U,0U,0U}}, +{UNPK_8180,{7U,1U,0U}}, +{UNPK_8180,{7U,2U,0U}}, +{UNPK_8180,{7U,3U,0U}}, +{UNPK_8180,{7U,4U,0U}}, +{UNPK_8180,{7U,5U,0U}}, +{UNPK_8180,{7U,6U,0U}}, +{UNPK_8180,{7U,7U,0U}}, +{UNPK_8188,{7U,0U,0U}}, +{UNPK_8188,{7U,1U,0U}}, +{UNPK_8188,{7U,2U,0U}}, +{UNPK_8188,{7U,3U,0U}}, +{UNPK_8188,{7U,4U,0U}}, +{UNPK_8188,{7U,5U,0U}}, +{UNPK_8188,{7U,6U,0U}}, +{UNPK_8188,{7U,7U,0U}}, +{OR_8190,{0U,7U,0U}}, +{OR_8190,{1U,7U,0U}}, +{OR_8190,{2U,7U,0U}}, +{OR_8190,{3U,7U,0U}}, +{OR_8190,{4U,7U,0U}}, +{OR_8190,{5U,7U,0U}}, +{OR_8190,{6U,7U,0U}}, +{OR_8190,{7U,7U,0U}}, +{OR_8198,{0U,7U,0U}}, +{OR_8198,{1U,7U,0U}}, +{OR_8198,{2U,7U,0U}}, +{OR_8198,{3U,7U,0U}}, +{OR_8198,{4U,7U,0U}}, +{OR_8198,{5U,7U,0U}}, +{OR_8198,{6U,7U,0U}}, +{OR_8198,{7U,7U,0U}}, +{OR_81A0,{0U,7U,0U}}, +{OR_81A0,{1U,7U,0U}}, +{OR_81A0,{2U,7U,0U}}, +{OR_81A0,{3U,7U,0U}}, +{OR_81A0,{4U,7U,0U}}, +{OR_81A0,{5U,7U,0U}}, +{OR_81A0,{6U,7U,0U}}, +{OR_81A0,{7U,7U,0U}}, +{OR_81A8,{0U,7U,0U}}, +{OR_81A8,{1U,7U,0U}}, +{OR_81A8,{2U,7U,0U}}, +{OR_81A8,{3U,7U,0U}}, +{OR_81A8,{4U,7U,0U}}, +{OR_81A8,{5U,7U,0U}}, +{OR_81A8,{6U,7U,0U}}, +{OR_81A8,{7U,7U,0U}}, +{OR_81B0,{0U,7U,0U}}, +{OR_81B0,{1U,7U,0U}}, +{OR_81B0,{2U,7U,0U}}, +{OR_81B0,{3U,7U,0U}}, +{OR_81B0,{4U,7U,0U}}, +{OR_81B0,{5U,7U,0U}}, +{OR_81B0,{6U,7U,0U}}, +{OR_81B0,{7U,7U,0U}}, +{OR_81B8,{0U,7U,0U}}, +{OR_81B9,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81C0,{0U,7U,70U}}, +{DIVS_81C0,{1U,7U,70U}}, +{DIVS_81C0,{2U,7U,70U}}, +{DIVS_81C0,{3U,7U,70U}}, +{DIVS_81C0,{4U,7U,70U}}, +{DIVS_81C0,{5U,7U,70U}}, +{DIVS_81C0,{6U,7U,70U}}, +{DIVS_81C0,{7U,7U,70U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{DIVS_81D0,{0U,7U,74U}}, +{DIVS_81D0,{1U,7U,74U}}, +{DIVS_81D0,{2U,7U,74U}}, +{DIVS_81D0,{3U,7U,74U}}, +{DIVS_81D0,{4U,7U,74U}}, +{DIVS_81D0,{5U,7U,74U}}, +{DIVS_81D0,{6U,7U,74U}}, +{DIVS_81D0,{7U,7U,74U}}, +{DIVS_81D8,{0U,7U,74U}}, +{DIVS_81D8,{1U,7U,74U}}, +{DIVS_81D8,{2U,7U,74U}}, +{DIVS_81D8,{3U,7U,74U}}, +{DIVS_81D8,{4U,7U,74U}}, +{DIVS_81D8,{5U,7U,74U}}, +{DIVS_81D8,{6U,7U,74U}}, +{DIVS_81D8,{7U,7U,74U}}, +{DIVS_81E0,{0U,7U,76U}}, +{DIVS_81E0,{1U,7U,76U}}, +{DIVS_81E0,{2U,7U,76U}}, +{DIVS_81E0,{3U,7U,76U}}, +{DIVS_81E0,{4U,7U,76U}}, +{DIVS_81E0,{5U,7U,76U}}, +{DIVS_81E0,{6U,7U,76U}}, +{DIVS_81E0,{7U,7U,76U}}, +{DIVS_81E8,{0U,7U,78U}}, +{DIVS_81E8,{1U,7U,78U}}, +{DIVS_81E8,{2U,7U,78U}}, +{DIVS_81E8,{3U,7U,78U}}, +{DIVS_81E8,{4U,7U,78U}}, +{DIVS_81E8,{5U,7U,78U}}, +{DIVS_81E8,{6U,7U,78U}}, +{DIVS_81E8,{7U,7U,78U}}, +{DIVS_81F0,{0U,7U,80U}}, +{DIVS_81F0,{1U,7U,80U}}, +{DIVS_81F0,{2U,7U,80U}}, +{DIVS_81F0,{3U,7U,80U}}, +{DIVS_81F0,{4U,7U,80U}}, +{DIVS_81F0,{5U,7U,80U}}, +{DIVS_81F0,{6U,7U,80U}}, +{DIVS_81F0,{7U,7U,80U}}, +{DIVS_81F8,{0U,7U,78U}}, +{DIVS_81F9,{0U,7U,82U}}, +{DIVS_81FA,{0U,7U,78U}}, +{DIVS_81FB,{0U,7U,80U}}, +{DIVS_81FC,{0U,7U,74U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9000,{0U,0U,0U}}, +{SUB_9000,{1U,0U,0U}}, +{SUB_9000,{2U,0U,0U}}, +{SUB_9000,{3U,0U,0U}}, +{SUB_9000,{4U,0U,0U}}, +{SUB_9000,{5U,0U,0U}}, +{SUB_9000,{6U,0U,0U}}, +{SUB_9000,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9010,{0U,0U,0U}}, +{SUB_9010,{1U,0U,0U}}, +{SUB_9010,{2U,0U,0U}}, +{SUB_9010,{3U,0U,0U}}, +{SUB_9010,{4U,0U,0U}}, +{SUB_9010,{5U,0U,0U}}, +{SUB_9010,{6U,0U,0U}}, +{SUB_9010,{7U,0U,0U}}, +{SUB_9018,{0U,0U,0U}}, +{SUB_9018,{1U,0U,0U}}, +{SUB_9018,{2U,0U,0U}}, +{SUB_9018,{3U,0U,0U}}, +{SUB_9018,{4U,0U,0U}}, +{SUB_9018,{5U,0U,0U}}, +{SUB_9018,{6U,0U,0U}}, +{SUB_9018,{7U,0U,0U}}, +{SUB_9020,{0U,0U,0U}}, +{SUB_9020,{1U,0U,0U}}, +{SUB_9020,{2U,0U,0U}}, +{SUB_9020,{3U,0U,0U}}, +{SUB_9020,{4U,0U,0U}}, +{SUB_9020,{5U,0U,0U}}, +{SUB_9020,{6U,0U,0U}}, +{SUB_9020,{7U,0U,0U}}, +{SUB_9028,{0U,0U,0U}}, +{SUB_9028,{1U,0U,0U}}, +{SUB_9028,{2U,0U,0U}}, +{SUB_9028,{3U,0U,0U}}, +{SUB_9028,{4U,0U,0U}}, +{SUB_9028,{5U,0U,0U}}, +{SUB_9028,{6U,0U,0U}}, +{SUB_9028,{7U,0U,0U}}, +{SUB_9030,{0U,0U,0U}}, +{SUB_9030,{1U,0U,0U}}, +{SUB_9030,{2U,0U,0U}}, +{SUB_9030,{3U,0U,0U}}, +{SUB_9030,{4U,0U,0U}}, +{SUB_9030,{5U,0U,0U}}, +{SUB_9030,{6U,0U,0U}}, +{SUB_9030,{7U,0U,0U}}, +{SUB_9038,{0U,0U,0U}}, +{SUB_9039,{0U,0U,0U}}, +{SUB_903A,{0U,0U,0U}}, +{SUB_903B,{0U,0U,0U}}, +{SUB_903C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9040,{0U,0U,0U}}, +{SUB_9040,{1U,0U,0U}}, +{SUB_9040,{2U,0U,0U}}, +{SUB_9040,{3U,0U,0U}}, +{SUB_9040,{4U,0U,0U}}, +{SUB_9040,{5U,0U,0U}}, +{SUB_9040,{6U,0U,0U}}, +{SUB_9040,{7U,0U,0U}}, +{SUB_9048,{0U,0U,0U}}, +{SUB_9048,{1U,0U,0U}}, +{SUB_9048,{2U,0U,0U}}, +{SUB_9048,{3U,0U,0U}}, +{SUB_9048,{4U,0U,0U}}, +{SUB_9048,{5U,0U,0U}}, +{SUB_9048,{6U,0U,0U}}, +{SUB_9048,{7U,0U,0U}}, +{SUB_9050,{0U,0U,0U}}, +{SUB_9050,{1U,0U,0U}}, +{SUB_9050,{2U,0U,0U}}, +{SUB_9050,{3U,0U,0U}}, +{SUB_9050,{4U,0U,0U}}, +{SUB_9050,{5U,0U,0U}}, +{SUB_9050,{6U,0U,0U}}, +{SUB_9050,{7U,0U,0U}}, +{SUB_9058,{0U,0U,0U}}, +{SUB_9058,{1U,0U,0U}}, +{SUB_9058,{2U,0U,0U}}, +{SUB_9058,{3U,0U,0U}}, +{SUB_9058,{4U,0U,0U}}, +{SUB_9058,{5U,0U,0U}}, +{SUB_9058,{6U,0U,0U}}, +{SUB_9058,{7U,0U,0U}}, +{SUB_9060,{0U,0U,0U}}, +{SUB_9060,{1U,0U,0U}}, +{SUB_9060,{2U,0U,0U}}, +{SUB_9060,{3U,0U,0U}}, +{SUB_9060,{4U,0U,0U}}, +{SUB_9060,{5U,0U,0U}}, +{SUB_9060,{6U,0U,0U}}, +{SUB_9060,{7U,0U,0U}}, +{SUB_9068,{0U,0U,0U}}, +{SUB_9068,{1U,0U,0U}}, +{SUB_9068,{2U,0U,0U}}, +{SUB_9068,{3U,0U,0U}}, +{SUB_9068,{4U,0U,0U}}, +{SUB_9068,{5U,0U,0U}}, +{SUB_9068,{6U,0U,0U}}, +{SUB_9068,{7U,0U,0U}}, +{SUB_9070,{0U,0U,0U}}, +{SUB_9070,{1U,0U,0U}}, +{SUB_9070,{2U,0U,0U}}, +{SUB_9070,{3U,0U,0U}}, +{SUB_9070,{4U,0U,0U}}, +{SUB_9070,{5U,0U,0U}}, +{SUB_9070,{6U,0U,0U}}, +{SUB_9070,{7U,0U,0U}}, +{SUB_9078,{0U,0U,0U}}, +{SUB_9079,{0U,0U,0U}}, +{SUB_907A,{0U,0U,0U}}, +{SUB_907B,{0U,0U,0U}}, +{SUB_907C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9080,{0U,0U,0U}}, +{SUB_9080,{1U,0U,0U}}, +{SUB_9080,{2U,0U,0U}}, +{SUB_9080,{3U,0U,0U}}, +{SUB_9080,{4U,0U,0U}}, +{SUB_9080,{5U,0U,0U}}, +{SUB_9080,{6U,0U,0U}}, +{SUB_9080,{7U,0U,0U}}, +{SUB_9088,{0U,0U,0U}}, +{SUB_9088,{1U,0U,0U}}, +{SUB_9088,{2U,0U,0U}}, +{SUB_9088,{3U,0U,0U}}, +{SUB_9088,{4U,0U,0U}}, +{SUB_9088,{5U,0U,0U}}, +{SUB_9088,{6U,0U,0U}}, +{SUB_9088,{7U,0U,0U}}, +{SUB_9090,{0U,0U,0U}}, +{SUB_9090,{1U,0U,0U}}, +{SUB_9090,{2U,0U,0U}}, +{SUB_9090,{3U,0U,0U}}, +{SUB_9090,{4U,0U,0U}}, +{SUB_9090,{5U,0U,0U}}, +{SUB_9090,{6U,0U,0U}}, +{SUB_9090,{7U,0U,0U}}, +{SUB_9098,{0U,0U,0U}}, +{SUB_9098,{1U,0U,0U}}, +{SUB_9098,{2U,0U,0U}}, +{SUB_9098,{3U,0U,0U}}, +{SUB_9098,{4U,0U,0U}}, +{SUB_9098,{5U,0U,0U}}, +{SUB_9098,{6U,0U,0U}}, +{SUB_9098,{7U,0U,0U}}, +{SUB_90A0,{0U,0U,0U}}, +{SUB_90A0,{1U,0U,0U}}, +{SUB_90A0,{2U,0U,0U}}, +{SUB_90A0,{3U,0U,0U}}, +{SUB_90A0,{4U,0U,0U}}, +{SUB_90A0,{5U,0U,0U}}, +{SUB_90A0,{6U,0U,0U}}, +{SUB_90A0,{7U,0U,0U}}, +{SUB_90A8,{0U,0U,0U}}, +{SUB_90A8,{1U,0U,0U}}, +{SUB_90A8,{2U,0U,0U}}, +{SUB_90A8,{3U,0U,0U}}, +{SUB_90A8,{4U,0U,0U}}, +{SUB_90A8,{5U,0U,0U}}, +{SUB_90A8,{6U,0U,0U}}, +{SUB_90A8,{7U,0U,0U}}, +{SUB_90B0,{0U,0U,0U}}, +{SUB_90B0,{1U,0U,0U}}, +{SUB_90B0,{2U,0U,0U}}, +{SUB_90B0,{3U,0U,0U}}, +{SUB_90B0,{4U,0U,0U}}, +{SUB_90B0,{5U,0U,0U}}, +{SUB_90B0,{6U,0U,0U}}, +{SUB_90B0,{7U,0U,0U}}, +{SUB_90B8,{0U,0U,0U}}, +{SUB_90B9,{0U,0U,0U}}, +{SUB_90BA,{0U,0U,0U}}, +{SUB_90BB,{0U,0U,0U}}, +{SUB_90BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_90C0,{0U,0U,0U}}, +{SUBA_90C0,{1U,0U,0U}}, +{SUBA_90C0,{2U,0U,0U}}, +{SUBA_90C0,{3U,0U,0U}}, +{SUBA_90C0,{4U,0U,0U}}, +{SUBA_90C0,{5U,0U,0U}}, +{SUBA_90C0,{6U,0U,0U}}, +{SUBA_90C0,{7U,0U,0U}}, +{SUBA_90C8,{0U,0U,0U}}, +{SUBA_90C8,{1U,0U,0U}}, +{SUBA_90C8,{2U,0U,0U}}, +{SUBA_90C8,{3U,0U,0U}}, +{SUBA_90C8,{4U,0U,0U}}, +{SUBA_90C8,{5U,0U,0U}}, +{SUBA_90C8,{6U,0U,0U}}, +{SUBA_90C8,{7U,0U,0U}}, +{SUBA_90D0,{0U,0U,0U}}, +{SUBA_90D0,{1U,0U,0U}}, +{SUBA_90D0,{2U,0U,0U}}, +{SUBA_90D0,{3U,0U,0U}}, +{SUBA_90D0,{4U,0U,0U}}, +{SUBA_90D0,{5U,0U,0U}}, +{SUBA_90D0,{6U,0U,0U}}, +{SUBA_90D0,{7U,0U,0U}}, +{SUBA_90D8,{0U,0U,0U}}, +{SUBA_90D8,{1U,0U,0U}}, +{SUBA_90D8,{2U,0U,0U}}, +{SUBA_90D8,{3U,0U,0U}}, +{SUBA_90D8,{4U,0U,0U}}, +{SUBA_90D8,{5U,0U,0U}}, +{SUBA_90D8,{6U,0U,0U}}, +{SUBA_90D8,{7U,0U,0U}}, +{SUBA_90E0,{0U,0U,0U}}, +{SUBA_90E0,{1U,0U,0U}}, +{SUBA_90E0,{2U,0U,0U}}, +{SUBA_90E0,{3U,0U,0U}}, +{SUBA_90E0,{4U,0U,0U}}, +{SUBA_90E0,{5U,0U,0U}}, +{SUBA_90E0,{6U,0U,0U}}, +{SUBA_90E0,{7U,0U,0U}}, +{SUBA_90E8,{0U,0U,0U}}, +{SUBA_90E8,{1U,0U,0U}}, +{SUBA_90E8,{2U,0U,0U}}, +{SUBA_90E8,{3U,0U,0U}}, +{SUBA_90E8,{4U,0U,0U}}, +{SUBA_90E8,{5U,0U,0U}}, +{SUBA_90E8,{6U,0U,0U}}, +{SUBA_90E8,{7U,0U,0U}}, +{SUBA_90F0,{0U,0U,0U}}, +{SUBA_90F0,{1U,0U,0U}}, +{SUBA_90F0,{2U,0U,0U}}, +{SUBA_90F0,{3U,0U,0U}}, +{SUBA_90F0,{4U,0U,0U}}, +{SUBA_90F0,{5U,0U,0U}}, +{SUBA_90F0,{6U,0U,0U}}, +{SUBA_90F0,{7U,0U,0U}}, +{SUBA_90F8,{0U,0U,0U}}, +{SUBA_90F9,{0U,0U,0U}}, +{SUBA_90FA,{0U,0U,0U}}, +{SUBA_90FB,{0U,0U,0U}}, +{SUBA_90FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9100,{0U,0U,0U}}, +{SUBX_9100,{1U,0U,0U}}, +{SUBX_9100,{2U,0U,0U}}, +{SUBX_9100,{3U,0U,0U}}, +{SUBX_9100,{4U,0U,0U}}, +{SUBX_9100,{5U,0U,0U}}, +{SUBX_9100,{6U,0U,0U}}, +{SUBX_9100,{7U,0U,0U}}, +{SUBX_9108,{0U,0U,0U}}, +{SUBX_9108,{1U,0U,0U}}, +{SUBX_9108,{2U,0U,0U}}, +{SUBX_9108,{3U,0U,0U}}, +{SUBX_9108,{4U,0U,0U}}, +{SUBX_9108,{5U,0U,0U}}, +{SUBX_9108,{6U,0U,0U}}, +{SUBX_9108,{7U,0U,0U}}, +{SUB_9110,{0U,0U,0U}}, +{SUB_9110,{1U,0U,0U}}, +{SUB_9110,{2U,0U,0U}}, +{SUB_9110,{3U,0U,0U}}, +{SUB_9110,{4U,0U,0U}}, +{SUB_9110,{5U,0U,0U}}, +{SUB_9110,{6U,0U,0U}}, +{SUB_9110,{7U,0U,0U}}, +{SUB_9118,{0U,0U,0U}}, +{SUB_9118,{1U,0U,0U}}, +{SUB_9118,{2U,0U,0U}}, +{SUB_9118,{3U,0U,0U}}, +{SUB_9118,{4U,0U,0U}}, +{SUB_9118,{5U,0U,0U}}, +{SUB_9118,{6U,0U,0U}}, +{SUB_9118,{7U,0U,0U}}, +{SUB_9120,{0U,0U,0U}}, +{SUB_9120,{1U,0U,0U}}, +{SUB_9120,{2U,0U,0U}}, +{SUB_9120,{3U,0U,0U}}, +{SUB_9120,{4U,0U,0U}}, +{SUB_9120,{5U,0U,0U}}, +{SUB_9120,{6U,0U,0U}}, +{SUB_9120,{7U,0U,0U}}, +{SUB_9128,{0U,0U,0U}}, +{SUB_9128,{1U,0U,0U}}, +{SUB_9128,{2U,0U,0U}}, +{SUB_9128,{3U,0U,0U}}, +{SUB_9128,{4U,0U,0U}}, +{SUB_9128,{5U,0U,0U}}, +{SUB_9128,{6U,0U,0U}}, +{SUB_9128,{7U,0U,0U}}, +{SUB_9130,{0U,0U,0U}}, +{SUB_9130,{1U,0U,0U}}, +{SUB_9130,{2U,0U,0U}}, +{SUB_9130,{3U,0U,0U}}, +{SUB_9130,{4U,0U,0U}}, +{SUB_9130,{5U,0U,0U}}, +{SUB_9130,{6U,0U,0U}}, +{SUB_9130,{7U,0U,0U}}, +{SUB_9138,{0U,0U,0U}}, +{SUB_9139,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9140,{0U,0U,0U}}, +{SUBX_9140,{1U,0U,0U}}, +{SUBX_9140,{2U,0U,0U}}, +{SUBX_9140,{3U,0U,0U}}, +{SUBX_9140,{4U,0U,0U}}, +{SUBX_9140,{5U,0U,0U}}, +{SUBX_9140,{6U,0U,0U}}, +{SUBX_9140,{7U,0U,0U}}, +{SUBX_9148,{0U,0U,0U}}, +{SUBX_9148,{1U,0U,0U}}, +{SUBX_9148,{2U,0U,0U}}, +{SUBX_9148,{3U,0U,0U}}, +{SUBX_9148,{4U,0U,0U}}, +{SUBX_9148,{5U,0U,0U}}, +{SUBX_9148,{6U,0U,0U}}, +{SUBX_9148,{7U,0U,0U}}, +{SUB_9150,{0U,0U,0U}}, +{SUB_9150,{1U,0U,0U}}, +{SUB_9150,{2U,0U,0U}}, +{SUB_9150,{3U,0U,0U}}, +{SUB_9150,{4U,0U,0U}}, +{SUB_9150,{5U,0U,0U}}, +{SUB_9150,{6U,0U,0U}}, +{SUB_9150,{7U,0U,0U}}, +{SUB_9158,{0U,0U,0U}}, +{SUB_9158,{1U,0U,0U}}, +{SUB_9158,{2U,0U,0U}}, +{SUB_9158,{3U,0U,0U}}, +{SUB_9158,{4U,0U,0U}}, +{SUB_9158,{5U,0U,0U}}, +{SUB_9158,{6U,0U,0U}}, +{SUB_9158,{7U,0U,0U}}, +{SUB_9160,{0U,0U,0U}}, +{SUB_9160,{1U,0U,0U}}, +{SUB_9160,{2U,0U,0U}}, +{SUB_9160,{3U,0U,0U}}, +{SUB_9160,{4U,0U,0U}}, +{SUB_9160,{5U,0U,0U}}, +{SUB_9160,{6U,0U,0U}}, +{SUB_9160,{7U,0U,0U}}, +{SUB_9168,{0U,0U,0U}}, +{SUB_9168,{1U,0U,0U}}, +{SUB_9168,{2U,0U,0U}}, +{SUB_9168,{3U,0U,0U}}, +{SUB_9168,{4U,0U,0U}}, +{SUB_9168,{5U,0U,0U}}, +{SUB_9168,{6U,0U,0U}}, +{SUB_9168,{7U,0U,0U}}, +{SUB_9170,{0U,0U,0U}}, +{SUB_9170,{1U,0U,0U}}, +{SUB_9170,{2U,0U,0U}}, +{SUB_9170,{3U,0U,0U}}, +{SUB_9170,{4U,0U,0U}}, +{SUB_9170,{5U,0U,0U}}, +{SUB_9170,{6U,0U,0U}}, +{SUB_9170,{7U,0U,0U}}, +{SUB_9178,{0U,0U,0U}}, +{SUB_9179,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9180,{0U,0U,0U}}, +{SUBX_9180,{1U,0U,0U}}, +{SUBX_9180,{2U,0U,0U}}, +{SUBX_9180,{3U,0U,0U}}, +{SUBX_9180,{4U,0U,0U}}, +{SUBX_9180,{5U,0U,0U}}, +{SUBX_9180,{6U,0U,0U}}, +{SUBX_9180,{7U,0U,0U}}, +{SUBX_9188,{0U,0U,0U}}, +{SUBX_9188,{1U,0U,0U}}, +{SUBX_9188,{2U,0U,0U}}, +{SUBX_9188,{3U,0U,0U}}, +{SUBX_9188,{4U,0U,0U}}, +{SUBX_9188,{5U,0U,0U}}, +{SUBX_9188,{6U,0U,0U}}, +{SUBX_9188,{7U,0U,0U}}, +{SUB_9190,{0U,0U,0U}}, +{SUB_9190,{1U,0U,0U}}, +{SUB_9190,{2U,0U,0U}}, +{SUB_9190,{3U,0U,0U}}, +{SUB_9190,{4U,0U,0U}}, +{SUB_9190,{5U,0U,0U}}, +{SUB_9190,{6U,0U,0U}}, +{SUB_9190,{7U,0U,0U}}, +{SUB_9198,{0U,0U,0U}}, +{SUB_9198,{1U,0U,0U}}, +{SUB_9198,{2U,0U,0U}}, +{SUB_9198,{3U,0U,0U}}, +{SUB_9198,{4U,0U,0U}}, +{SUB_9198,{5U,0U,0U}}, +{SUB_9198,{6U,0U,0U}}, +{SUB_9198,{7U,0U,0U}}, +{SUB_91A0,{0U,0U,0U}}, +{SUB_91A0,{1U,0U,0U}}, +{SUB_91A0,{2U,0U,0U}}, +{SUB_91A0,{3U,0U,0U}}, +{SUB_91A0,{4U,0U,0U}}, +{SUB_91A0,{5U,0U,0U}}, +{SUB_91A0,{6U,0U,0U}}, +{SUB_91A0,{7U,0U,0U}}, +{SUB_91A8,{0U,0U,0U}}, +{SUB_91A8,{1U,0U,0U}}, +{SUB_91A8,{2U,0U,0U}}, +{SUB_91A8,{3U,0U,0U}}, +{SUB_91A8,{4U,0U,0U}}, +{SUB_91A8,{5U,0U,0U}}, +{SUB_91A8,{6U,0U,0U}}, +{SUB_91A8,{7U,0U,0U}}, +{SUB_91B0,{0U,0U,0U}}, +{SUB_91B0,{1U,0U,0U}}, +{SUB_91B0,{2U,0U,0U}}, +{SUB_91B0,{3U,0U,0U}}, +{SUB_91B0,{4U,0U,0U}}, +{SUB_91B0,{5U,0U,0U}}, +{SUB_91B0,{6U,0U,0U}}, +{SUB_91B0,{7U,0U,0U}}, +{SUB_91B8,{0U,0U,0U}}, +{SUB_91B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_91C0,{0U,0U,0U}}, +{SUBA_91C0,{1U,0U,0U}}, +{SUBA_91C0,{2U,0U,0U}}, +{SUBA_91C0,{3U,0U,0U}}, +{SUBA_91C0,{4U,0U,0U}}, +{SUBA_91C0,{5U,0U,0U}}, +{SUBA_91C0,{6U,0U,0U}}, +{SUBA_91C0,{7U,0U,0U}}, +{SUBA_91C8,{0U,0U,0U}}, +{SUBA_91C8,{1U,0U,0U}}, +{SUBA_91C8,{2U,0U,0U}}, +{SUBA_91C8,{3U,0U,0U}}, +{SUBA_91C8,{4U,0U,0U}}, +{SUBA_91C8,{5U,0U,0U}}, +{SUBA_91C8,{6U,0U,0U}}, +{SUBA_91C8,{7U,0U,0U}}, +{SUBA_91D0,{0U,0U,0U}}, +{SUBA_91D0,{1U,0U,0U}}, +{SUBA_91D0,{2U,0U,0U}}, +{SUBA_91D0,{3U,0U,0U}}, +{SUBA_91D0,{4U,0U,0U}}, +{SUBA_91D0,{5U,0U,0U}}, +{SUBA_91D0,{6U,0U,0U}}, +{SUBA_91D0,{7U,0U,0U}}, +{SUBA_91D8,{0U,0U,0U}}, +{SUBA_91D8,{1U,0U,0U}}, +{SUBA_91D8,{2U,0U,0U}}, +{SUBA_91D8,{3U,0U,0U}}, +{SUBA_91D8,{4U,0U,0U}}, +{SUBA_91D8,{5U,0U,0U}}, +{SUBA_91D8,{6U,0U,0U}}, +{SUBA_91D8,{7U,0U,0U}}, +{SUBA_91E0,{0U,0U,0U}}, +{SUBA_91E0,{1U,0U,0U}}, +{SUBA_91E0,{2U,0U,0U}}, +{SUBA_91E0,{3U,0U,0U}}, +{SUBA_91E0,{4U,0U,0U}}, +{SUBA_91E0,{5U,0U,0U}}, +{SUBA_91E0,{6U,0U,0U}}, +{SUBA_91E0,{7U,0U,0U}}, +{SUBA_91E8,{0U,0U,0U}}, +{SUBA_91E8,{1U,0U,0U}}, +{SUBA_91E8,{2U,0U,0U}}, +{SUBA_91E8,{3U,0U,0U}}, +{SUBA_91E8,{4U,0U,0U}}, +{SUBA_91E8,{5U,0U,0U}}, +{SUBA_91E8,{6U,0U,0U}}, +{SUBA_91E8,{7U,0U,0U}}, +{SUBA_91F0,{0U,0U,0U}}, +{SUBA_91F0,{1U,0U,0U}}, +{SUBA_91F0,{2U,0U,0U}}, +{SUBA_91F0,{3U,0U,0U}}, +{SUBA_91F0,{4U,0U,0U}}, +{SUBA_91F0,{5U,0U,0U}}, +{SUBA_91F0,{6U,0U,0U}}, +{SUBA_91F0,{7U,0U,0U}}, +{SUBA_91F8,{0U,0U,0U}}, +{SUBA_91F9,{0U,0U,0U}}, +{SUBA_91FA,{0U,0U,0U}}, +{SUBA_91FB,{0U,0U,0U}}, +{SUBA_91FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9000,{0U,1U,0U}}, +{SUB_9000,{1U,1U,0U}}, +{SUB_9000,{2U,1U,0U}}, +{SUB_9000,{3U,1U,0U}}, +{SUB_9000,{4U,1U,0U}}, +{SUB_9000,{5U,1U,0U}}, +{SUB_9000,{6U,1U,0U}}, +{SUB_9000,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9010,{0U,1U,0U}}, +{SUB_9010,{1U,1U,0U}}, +{SUB_9010,{2U,1U,0U}}, +{SUB_9010,{3U,1U,0U}}, +{SUB_9010,{4U,1U,0U}}, +{SUB_9010,{5U,1U,0U}}, +{SUB_9010,{6U,1U,0U}}, +{SUB_9010,{7U,1U,0U}}, +{SUB_9018,{0U,1U,0U}}, +{SUB_9018,{1U,1U,0U}}, +{SUB_9018,{2U,1U,0U}}, +{SUB_9018,{3U,1U,0U}}, +{SUB_9018,{4U,1U,0U}}, +{SUB_9018,{5U,1U,0U}}, +{SUB_9018,{6U,1U,0U}}, +{SUB_9018,{7U,1U,0U}}, +{SUB_9020,{0U,1U,0U}}, +{SUB_9020,{1U,1U,0U}}, +{SUB_9020,{2U,1U,0U}}, +{SUB_9020,{3U,1U,0U}}, +{SUB_9020,{4U,1U,0U}}, +{SUB_9020,{5U,1U,0U}}, +{SUB_9020,{6U,1U,0U}}, +{SUB_9020,{7U,1U,0U}}, +{SUB_9028,{0U,1U,0U}}, +{SUB_9028,{1U,1U,0U}}, +{SUB_9028,{2U,1U,0U}}, +{SUB_9028,{3U,1U,0U}}, +{SUB_9028,{4U,1U,0U}}, +{SUB_9028,{5U,1U,0U}}, +{SUB_9028,{6U,1U,0U}}, +{SUB_9028,{7U,1U,0U}}, +{SUB_9030,{0U,1U,0U}}, +{SUB_9030,{1U,1U,0U}}, +{SUB_9030,{2U,1U,0U}}, +{SUB_9030,{3U,1U,0U}}, +{SUB_9030,{4U,1U,0U}}, +{SUB_9030,{5U,1U,0U}}, +{SUB_9030,{6U,1U,0U}}, +{SUB_9030,{7U,1U,0U}}, +{SUB_9038,{0U,1U,0U}}, +{SUB_9039,{0U,1U,0U}}, +{SUB_903A,{0U,1U,0U}}, +{SUB_903B,{0U,1U,0U}}, +{SUB_903C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9040,{0U,1U,0U}}, +{SUB_9040,{1U,1U,0U}}, +{SUB_9040,{2U,1U,0U}}, +{SUB_9040,{3U,1U,0U}}, +{SUB_9040,{4U,1U,0U}}, +{SUB_9040,{5U,1U,0U}}, +{SUB_9040,{6U,1U,0U}}, +{SUB_9040,{7U,1U,0U}}, +{SUB_9048,{0U,1U,0U}}, +{SUB_9048,{1U,1U,0U}}, +{SUB_9048,{2U,1U,0U}}, +{SUB_9048,{3U,1U,0U}}, +{SUB_9048,{4U,1U,0U}}, +{SUB_9048,{5U,1U,0U}}, +{SUB_9048,{6U,1U,0U}}, +{SUB_9048,{7U,1U,0U}}, +{SUB_9050,{0U,1U,0U}}, +{SUB_9050,{1U,1U,0U}}, +{SUB_9050,{2U,1U,0U}}, +{SUB_9050,{3U,1U,0U}}, +{SUB_9050,{4U,1U,0U}}, +{SUB_9050,{5U,1U,0U}}, +{SUB_9050,{6U,1U,0U}}, +{SUB_9050,{7U,1U,0U}}, +{SUB_9058,{0U,1U,0U}}, +{SUB_9058,{1U,1U,0U}}, +{SUB_9058,{2U,1U,0U}}, +{SUB_9058,{3U,1U,0U}}, +{SUB_9058,{4U,1U,0U}}, +{SUB_9058,{5U,1U,0U}}, +{SUB_9058,{6U,1U,0U}}, +{SUB_9058,{7U,1U,0U}}, +{SUB_9060,{0U,1U,0U}}, +{SUB_9060,{1U,1U,0U}}, +{SUB_9060,{2U,1U,0U}}, +{SUB_9060,{3U,1U,0U}}, +{SUB_9060,{4U,1U,0U}}, +{SUB_9060,{5U,1U,0U}}, +{SUB_9060,{6U,1U,0U}}, +{SUB_9060,{7U,1U,0U}}, +{SUB_9068,{0U,1U,0U}}, +{SUB_9068,{1U,1U,0U}}, +{SUB_9068,{2U,1U,0U}}, +{SUB_9068,{3U,1U,0U}}, +{SUB_9068,{4U,1U,0U}}, +{SUB_9068,{5U,1U,0U}}, +{SUB_9068,{6U,1U,0U}}, +{SUB_9068,{7U,1U,0U}}, +{SUB_9070,{0U,1U,0U}}, +{SUB_9070,{1U,1U,0U}}, +{SUB_9070,{2U,1U,0U}}, +{SUB_9070,{3U,1U,0U}}, +{SUB_9070,{4U,1U,0U}}, +{SUB_9070,{5U,1U,0U}}, +{SUB_9070,{6U,1U,0U}}, +{SUB_9070,{7U,1U,0U}}, +{SUB_9078,{0U,1U,0U}}, +{SUB_9079,{0U,1U,0U}}, +{SUB_907A,{0U,1U,0U}}, +{SUB_907B,{0U,1U,0U}}, +{SUB_907C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9080,{0U,1U,0U}}, +{SUB_9080,{1U,1U,0U}}, +{SUB_9080,{2U,1U,0U}}, +{SUB_9080,{3U,1U,0U}}, +{SUB_9080,{4U,1U,0U}}, +{SUB_9080,{5U,1U,0U}}, +{SUB_9080,{6U,1U,0U}}, +{SUB_9080,{7U,1U,0U}}, +{SUB_9088,{0U,1U,0U}}, +{SUB_9088,{1U,1U,0U}}, +{SUB_9088,{2U,1U,0U}}, +{SUB_9088,{3U,1U,0U}}, +{SUB_9088,{4U,1U,0U}}, +{SUB_9088,{5U,1U,0U}}, +{SUB_9088,{6U,1U,0U}}, +{SUB_9088,{7U,1U,0U}}, +{SUB_9090,{0U,1U,0U}}, +{SUB_9090,{1U,1U,0U}}, +{SUB_9090,{2U,1U,0U}}, +{SUB_9090,{3U,1U,0U}}, +{SUB_9090,{4U,1U,0U}}, +{SUB_9090,{5U,1U,0U}}, +{SUB_9090,{6U,1U,0U}}, +{SUB_9090,{7U,1U,0U}}, +{SUB_9098,{0U,1U,0U}}, +{SUB_9098,{1U,1U,0U}}, +{SUB_9098,{2U,1U,0U}}, +{SUB_9098,{3U,1U,0U}}, +{SUB_9098,{4U,1U,0U}}, +{SUB_9098,{5U,1U,0U}}, +{SUB_9098,{6U,1U,0U}}, +{SUB_9098,{7U,1U,0U}}, +{SUB_90A0,{0U,1U,0U}}, +{SUB_90A0,{1U,1U,0U}}, +{SUB_90A0,{2U,1U,0U}}, +{SUB_90A0,{3U,1U,0U}}, +{SUB_90A0,{4U,1U,0U}}, +{SUB_90A0,{5U,1U,0U}}, +{SUB_90A0,{6U,1U,0U}}, +{SUB_90A0,{7U,1U,0U}}, +{SUB_90A8,{0U,1U,0U}}, +{SUB_90A8,{1U,1U,0U}}, +{SUB_90A8,{2U,1U,0U}}, +{SUB_90A8,{3U,1U,0U}}, +{SUB_90A8,{4U,1U,0U}}, +{SUB_90A8,{5U,1U,0U}}, +{SUB_90A8,{6U,1U,0U}}, +{SUB_90A8,{7U,1U,0U}}, +{SUB_90B0,{0U,1U,0U}}, +{SUB_90B0,{1U,1U,0U}}, +{SUB_90B0,{2U,1U,0U}}, +{SUB_90B0,{3U,1U,0U}}, +{SUB_90B0,{4U,1U,0U}}, +{SUB_90B0,{5U,1U,0U}}, +{SUB_90B0,{6U,1U,0U}}, +{SUB_90B0,{7U,1U,0U}}, +{SUB_90B8,{0U,1U,0U}}, +{SUB_90B9,{0U,1U,0U}}, +{SUB_90BA,{0U,1U,0U}}, +{SUB_90BB,{0U,1U,0U}}, +{SUB_90BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_90C0,{0U,1U,0U}}, +{SUBA_90C0,{1U,1U,0U}}, +{SUBA_90C0,{2U,1U,0U}}, +{SUBA_90C0,{3U,1U,0U}}, +{SUBA_90C0,{4U,1U,0U}}, +{SUBA_90C0,{5U,1U,0U}}, +{SUBA_90C0,{6U,1U,0U}}, +{SUBA_90C0,{7U,1U,0U}}, +{SUBA_90C8,{0U,1U,0U}}, +{SUBA_90C8,{1U,1U,0U}}, +{SUBA_90C8,{2U,1U,0U}}, +{SUBA_90C8,{3U,1U,0U}}, +{SUBA_90C8,{4U,1U,0U}}, +{SUBA_90C8,{5U,1U,0U}}, +{SUBA_90C8,{6U,1U,0U}}, +{SUBA_90C8,{7U,1U,0U}}, +{SUBA_90D0,{0U,1U,0U}}, +{SUBA_90D0,{1U,1U,0U}}, +{SUBA_90D0,{2U,1U,0U}}, +{SUBA_90D0,{3U,1U,0U}}, +{SUBA_90D0,{4U,1U,0U}}, +{SUBA_90D0,{5U,1U,0U}}, +{SUBA_90D0,{6U,1U,0U}}, +{SUBA_90D0,{7U,1U,0U}}, +{SUBA_90D8,{0U,1U,0U}}, +{SUBA_90D8,{1U,1U,0U}}, +{SUBA_90D8,{2U,1U,0U}}, +{SUBA_90D8,{3U,1U,0U}}, +{SUBA_90D8,{4U,1U,0U}}, +{SUBA_90D8,{5U,1U,0U}}, +{SUBA_90D8,{6U,1U,0U}}, +{SUBA_90D8,{7U,1U,0U}}, +{SUBA_90E0,{0U,1U,0U}}, +{SUBA_90E0,{1U,1U,0U}}, +{SUBA_90E0,{2U,1U,0U}}, +{SUBA_90E0,{3U,1U,0U}}, +{SUBA_90E0,{4U,1U,0U}}, +{SUBA_90E0,{5U,1U,0U}}, +{SUBA_90E0,{6U,1U,0U}}, +{SUBA_90E0,{7U,1U,0U}}, +{SUBA_90E8,{0U,1U,0U}}, +{SUBA_90E8,{1U,1U,0U}}, +{SUBA_90E8,{2U,1U,0U}}, +{SUBA_90E8,{3U,1U,0U}}, +{SUBA_90E8,{4U,1U,0U}}, +{SUBA_90E8,{5U,1U,0U}}, +{SUBA_90E8,{6U,1U,0U}}, +{SUBA_90E8,{7U,1U,0U}}, +{SUBA_90F0,{0U,1U,0U}}, +{SUBA_90F0,{1U,1U,0U}}, +{SUBA_90F0,{2U,1U,0U}}, +{SUBA_90F0,{3U,1U,0U}}, +{SUBA_90F0,{4U,1U,0U}}, +{SUBA_90F0,{5U,1U,0U}}, +{SUBA_90F0,{6U,1U,0U}}, +{SUBA_90F0,{7U,1U,0U}}, +{SUBA_90F8,{0U,1U,0U}}, +{SUBA_90F9,{0U,1U,0U}}, +{SUBA_90FA,{0U,1U,0U}}, +{SUBA_90FB,{0U,1U,0U}}, +{SUBA_90FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9100,{0U,1U,0U}}, +{SUBX_9100,{1U,1U,0U}}, +{SUBX_9100,{2U,1U,0U}}, +{SUBX_9100,{3U,1U,0U}}, +{SUBX_9100,{4U,1U,0U}}, +{SUBX_9100,{5U,1U,0U}}, +{SUBX_9100,{6U,1U,0U}}, +{SUBX_9100,{7U,1U,0U}}, +{SUBX_9108,{0U,1U,0U}}, +{SUBX_9108,{1U,1U,0U}}, +{SUBX_9108,{2U,1U,0U}}, +{SUBX_9108,{3U,1U,0U}}, +{SUBX_9108,{4U,1U,0U}}, +{SUBX_9108,{5U,1U,0U}}, +{SUBX_9108,{6U,1U,0U}}, +{SUBX_9108,{7U,1U,0U}}, +{SUB_9110,{0U,1U,0U}}, +{SUB_9110,{1U,1U,0U}}, +{SUB_9110,{2U,1U,0U}}, +{SUB_9110,{3U,1U,0U}}, +{SUB_9110,{4U,1U,0U}}, +{SUB_9110,{5U,1U,0U}}, +{SUB_9110,{6U,1U,0U}}, +{SUB_9110,{7U,1U,0U}}, +{SUB_9118,{0U,1U,0U}}, +{SUB_9118,{1U,1U,0U}}, +{SUB_9118,{2U,1U,0U}}, +{SUB_9118,{3U,1U,0U}}, +{SUB_9118,{4U,1U,0U}}, +{SUB_9118,{5U,1U,0U}}, +{SUB_9118,{6U,1U,0U}}, +{SUB_9118,{7U,1U,0U}}, +{SUB_9120,{0U,1U,0U}}, +{SUB_9120,{1U,1U,0U}}, +{SUB_9120,{2U,1U,0U}}, +{SUB_9120,{3U,1U,0U}}, +{SUB_9120,{4U,1U,0U}}, +{SUB_9120,{5U,1U,0U}}, +{SUB_9120,{6U,1U,0U}}, +{SUB_9120,{7U,1U,0U}}, +{SUB_9128,{0U,1U,0U}}, +{SUB_9128,{1U,1U,0U}}, +{SUB_9128,{2U,1U,0U}}, +{SUB_9128,{3U,1U,0U}}, +{SUB_9128,{4U,1U,0U}}, +{SUB_9128,{5U,1U,0U}}, +{SUB_9128,{6U,1U,0U}}, +{SUB_9128,{7U,1U,0U}}, +{SUB_9130,{0U,1U,0U}}, +{SUB_9130,{1U,1U,0U}}, +{SUB_9130,{2U,1U,0U}}, +{SUB_9130,{3U,1U,0U}}, +{SUB_9130,{4U,1U,0U}}, +{SUB_9130,{5U,1U,0U}}, +{SUB_9130,{6U,1U,0U}}, +{SUB_9130,{7U,1U,0U}}, +{SUB_9138,{0U,1U,0U}}, +{SUB_9139,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9140,{0U,1U,0U}}, +{SUBX_9140,{1U,1U,0U}}, +{SUBX_9140,{2U,1U,0U}}, +{SUBX_9140,{3U,1U,0U}}, +{SUBX_9140,{4U,1U,0U}}, +{SUBX_9140,{5U,1U,0U}}, +{SUBX_9140,{6U,1U,0U}}, +{SUBX_9140,{7U,1U,0U}}, +{SUBX_9148,{0U,1U,0U}}, +{SUBX_9148,{1U,1U,0U}}, +{SUBX_9148,{2U,1U,0U}}, +{SUBX_9148,{3U,1U,0U}}, +{SUBX_9148,{4U,1U,0U}}, +{SUBX_9148,{5U,1U,0U}}, +{SUBX_9148,{6U,1U,0U}}, +{SUBX_9148,{7U,1U,0U}}, +{SUB_9150,{0U,1U,0U}}, +{SUB_9150,{1U,1U,0U}}, +{SUB_9150,{2U,1U,0U}}, +{SUB_9150,{3U,1U,0U}}, +{SUB_9150,{4U,1U,0U}}, +{SUB_9150,{5U,1U,0U}}, +{SUB_9150,{6U,1U,0U}}, +{SUB_9150,{7U,1U,0U}}, +{SUB_9158,{0U,1U,0U}}, +{SUB_9158,{1U,1U,0U}}, +{SUB_9158,{2U,1U,0U}}, +{SUB_9158,{3U,1U,0U}}, +{SUB_9158,{4U,1U,0U}}, +{SUB_9158,{5U,1U,0U}}, +{SUB_9158,{6U,1U,0U}}, +{SUB_9158,{7U,1U,0U}}, +{SUB_9160,{0U,1U,0U}}, +{SUB_9160,{1U,1U,0U}}, +{SUB_9160,{2U,1U,0U}}, +{SUB_9160,{3U,1U,0U}}, +{SUB_9160,{4U,1U,0U}}, +{SUB_9160,{5U,1U,0U}}, +{SUB_9160,{6U,1U,0U}}, +{SUB_9160,{7U,1U,0U}}, +{SUB_9168,{0U,1U,0U}}, +{SUB_9168,{1U,1U,0U}}, +{SUB_9168,{2U,1U,0U}}, +{SUB_9168,{3U,1U,0U}}, +{SUB_9168,{4U,1U,0U}}, +{SUB_9168,{5U,1U,0U}}, +{SUB_9168,{6U,1U,0U}}, +{SUB_9168,{7U,1U,0U}}, +{SUB_9170,{0U,1U,0U}}, +{SUB_9170,{1U,1U,0U}}, +{SUB_9170,{2U,1U,0U}}, +{SUB_9170,{3U,1U,0U}}, +{SUB_9170,{4U,1U,0U}}, +{SUB_9170,{5U,1U,0U}}, +{SUB_9170,{6U,1U,0U}}, +{SUB_9170,{7U,1U,0U}}, +{SUB_9178,{0U,1U,0U}}, +{SUB_9179,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9180,{0U,1U,0U}}, +{SUBX_9180,{1U,1U,0U}}, +{SUBX_9180,{2U,1U,0U}}, +{SUBX_9180,{3U,1U,0U}}, +{SUBX_9180,{4U,1U,0U}}, +{SUBX_9180,{5U,1U,0U}}, +{SUBX_9180,{6U,1U,0U}}, +{SUBX_9180,{7U,1U,0U}}, +{SUBX_9188,{0U,1U,0U}}, +{SUBX_9188,{1U,1U,0U}}, +{SUBX_9188,{2U,1U,0U}}, +{SUBX_9188,{3U,1U,0U}}, +{SUBX_9188,{4U,1U,0U}}, +{SUBX_9188,{5U,1U,0U}}, +{SUBX_9188,{6U,1U,0U}}, +{SUBX_9188,{7U,1U,0U}}, +{SUB_9190,{0U,1U,0U}}, +{SUB_9190,{1U,1U,0U}}, +{SUB_9190,{2U,1U,0U}}, +{SUB_9190,{3U,1U,0U}}, +{SUB_9190,{4U,1U,0U}}, +{SUB_9190,{5U,1U,0U}}, +{SUB_9190,{6U,1U,0U}}, +{SUB_9190,{7U,1U,0U}}, +{SUB_9198,{0U,1U,0U}}, +{SUB_9198,{1U,1U,0U}}, +{SUB_9198,{2U,1U,0U}}, +{SUB_9198,{3U,1U,0U}}, +{SUB_9198,{4U,1U,0U}}, +{SUB_9198,{5U,1U,0U}}, +{SUB_9198,{6U,1U,0U}}, +{SUB_9198,{7U,1U,0U}}, +{SUB_91A0,{0U,1U,0U}}, +{SUB_91A0,{1U,1U,0U}}, +{SUB_91A0,{2U,1U,0U}}, +{SUB_91A0,{3U,1U,0U}}, +{SUB_91A0,{4U,1U,0U}}, +{SUB_91A0,{5U,1U,0U}}, +{SUB_91A0,{6U,1U,0U}}, +{SUB_91A0,{7U,1U,0U}}, +{SUB_91A8,{0U,1U,0U}}, +{SUB_91A8,{1U,1U,0U}}, +{SUB_91A8,{2U,1U,0U}}, +{SUB_91A8,{3U,1U,0U}}, +{SUB_91A8,{4U,1U,0U}}, +{SUB_91A8,{5U,1U,0U}}, +{SUB_91A8,{6U,1U,0U}}, +{SUB_91A8,{7U,1U,0U}}, +{SUB_91B0,{0U,1U,0U}}, +{SUB_91B0,{1U,1U,0U}}, +{SUB_91B0,{2U,1U,0U}}, +{SUB_91B0,{3U,1U,0U}}, +{SUB_91B0,{4U,1U,0U}}, +{SUB_91B0,{5U,1U,0U}}, +{SUB_91B0,{6U,1U,0U}}, +{SUB_91B0,{7U,1U,0U}}, +{SUB_91B8,{0U,1U,0U}}, +{SUB_91B9,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_91C0,{0U,1U,0U}}, +{SUBA_91C0,{1U,1U,0U}}, +{SUBA_91C0,{2U,1U,0U}}, +{SUBA_91C0,{3U,1U,0U}}, +{SUBA_91C0,{4U,1U,0U}}, +{SUBA_91C0,{5U,1U,0U}}, +{SUBA_91C0,{6U,1U,0U}}, +{SUBA_91C0,{7U,1U,0U}}, +{SUBA_91C8,{0U,1U,0U}}, +{SUBA_91C8,{1U,1U,0U}}, +{SUBA_91C8,{2U,1U,0U}}, +{SUBA_91C8,{3U,1U,0U}}, +{SUBA_91C8,{4U,1U,0U}}, +{SUBA_91C8,{5U,1U,0U}}, +{SUBA_91C8,{6U,1U,0U}}, +{SUBA_91C8,{7U,1U,0U}}, +{SUBA_91D0,{0U,1U,0U}}, +{SUBA_91D0,{1U,1U,0U}}, +{SUBA_91D0,{2U,1U,0U}}, +{SUBA_91D0,{3U,1U,0U}}, +{SUBA_91D0,{4U,1U,0U}}, +{SUBA_91D0,{5U,1U,0U}}, +{SUBA_91D0,{6U,1U,0U}}, +{SUBA_91D0,{7U,1U,0U}}, +{SUBA_91D8,{0U,1U,0U}}, +{SUBA_91D8,{1U,1U,0U}}, +{SUBA_91D8,{2U,1U,0U}}, +{SUBA_91D8,{3U,1U,0U}}, +{SUBA_91D8,{4U,1U,0U}}, +{SUBA_91D8,{5U,1U,0U}}, +{SUBA_91D8,{6U,1U,0U}}, +{SUBA_91D8,{7U,1U,0U}}, +{SUBA_91E0,{0U,1U,0U}}, +{SUBA_91E0,{1U,1U,0U}}, +{SUBA_91E0,{2U,1U,0U}}, +{SUBA_91E0,{3U,1U,0U}}, +{SUBA_91E0,{4U,1U,0U}}, +{SUBA_91E0,{5U,1U,0U}}, +{SUBA_91E0,{6U,1U,0U}}, +{SUBA_91E0,{7U,1U,0U}}, +{SUBA_91E8,{0U,1U,0U}}, +{SUBA_91E8,{1U,1U,0U}}, +{SUBA_91E8,{2U,1U,0U}}, +{SUBA_91E8,{3U,1U,0U}}, +{SUBA_91E8,{4U,1U,0U}}, +{SUBA_91E8,{5U,1U,0U}}, +{SUBA_91E8,{6U,1U,0U}}, +{SUBA_91E8,{7U,1U,0U}}, +{SUBA_91F0,{0U,1U,0U}}, +{SUBA_91F0,{1U,1U,0U}}, +{SUBA_91F0,{2U,1U,0U}}, +{SUBA_91F0,{3U,1U,0U}}, +{SUBA_91F0,{4U,1U,0U}}, +{SUBA_91F0,{5U,1U,0U}}, +{SUBA_91F0,{6U,1U,0U}}, +{SUBA_91F0,{7U,1U,0U}}, +{SUBA_91F8,{0U,1U,0U}}, +{SUBA_91F9,{0U,1U,0U}}, +{SUBA_91FA,{0U,1U,0U}}, +{SUBA_91FB,{0U,1U,0U}}, +{SUBA_91FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9000,{0U,2U,0U}}, +{SUB_9000,{1U,2U,0U}}, +{SUB_9000,{2U,2U,0U}}, +{SUB_9000,{3U,2U,0U}}, +{SUB_9000,{4U,2U,0U}}, +{SUB_9000,{5U,2U,0U}}, +{SUB_9000,{6U,2U,0U}}, +{SUB_9000,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9010,{0U,2U,0U}}, +{SUB_9010,{1U,2U,0U}}, +{SUB_9010,{2U,2U,0U}}, +{SUB_9010,{3U,2U,0U}}, +{SUB_9010,{4U,2U,0U}}, +{SUB_9010,{5U,2U,0U}}, +{SUB_9010,{6U,2U,0U}}, +{SUB_9010,{7U,2U,0U}}, +{SUB_9018,{0U,2U,0U}}, +{SUB_9018,{1U,2U,0U}}, +{SUB_9018,{2U,2U,0U}}, +{SUB_9018,{3U,2U,0U}}, +{SUB_9018,{4U,2U,0U}}, +{SUB_9018,{5U,2U,0U}}, +{SUB_9018,{6U,2U,0U}}, +{SUB_9018,{7U,2U,0U}}, +{SUB_9020,{0U,2U,0U}}, +{SUB_9020,{1U,2U,0U}}, +{SUB_9020,{2U,2U,0U}}, +{SUB_9020,{3U,2U,0U}}, +{SUB_9020,{4U,2U,0U}}, +{SUB_9020,{5U,2U,0U}}, +{SUB_9020,{6U,2U,0U}}, +{SUB_9020,{7U,2U,0U}}, +{SUB_9028,{0U,2U,0U}}, +{SUB_9028,{1U,2U,0U}}, +{SUB_9028,{2U,2U,0U}}, +{SUB_9028,{3U,2U,0U}}, +{SUB_9028,{4U,2U,0U}}, +{SUB_9028,{5U,2U,0U}}, +{SUB_9028,{6U,2U,0U}}, +{SUB_9028,{7U,2U,0U}}, +{SUB_9030,{0U,2U,0U}}, +{SUB_9030,{1U,2U,0U}}, +{SUB_9030,{2U,2U,0U}}, +{SUB_9030,{3U,2U,0U}}, +{SUB_9030,{4U,2U,0U}}, +{SUB_9030,{5U,2U,0U}}, +{SUB_9030,{6U,2U,0U}}, +{SUB_9030,{7U,2U,0U}}, +{SUB_9038,{0U,2U,0U}}, +{SUB_9039,{0U,2U,0U}}, +{SUB_903A,{0U,2U,0U}}, +{SUB_903B,{0U,2U,0U}}, +{SUB_903C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9040,{0U,2U,0U}}, +{SUB_9040,{1U,2U,0U}}, +{SUB_9040,{2U,2U,0U}}, +{SUB_9040,{3U,2U,0U}}, +{SUB_9040,{4U,2U,0U}}, +{SUB_9040,{5U,2U,0U}}, +{SUB_9040,{6U,2U,0U}}, +{SUB_9040,{7U,2U,0U}}, +{SUB_9048,{0U,2U,0U}}, +{SUB_9048,{1U,2U,0U}}, +{SUB_9048,{2U,2U,0U}}, +{SUB_9048,{3U,2U,0U}}, +{SUB_9048,{4U,2U,0U}}, +{SUB_9048,{5U,2U,0U}}, +{SUB_9048,{6U,2U,0U}}, +{SUB_9048,{7U,2U,0U}}, +{SUB_9050,{0U,2U,0U}}, +{SUB_9050,{1U,2U,0U}}, +{SUB_9050,{2U,2U,0U}}, +{SUB_9050,{3U,2U,0U}}, +{SUB_9050,{4U,2U,0U}}, +{SUB_9050,{5U,2U,0U}}, +{SUB_9050,{6U,2U,0U}}, +{SUB_9050,{7U,2U,0U}}, +{SUB_9058,{0U,2U,0U}}, +{SUB_9058,{1U,2U,0U}}, +{SUB_9058,{2U,2U,0U}}, +{SUB_9058,{3U,2U,0U}}, +{SUB_9058,{4U,2U,0U}}, +{SUB_9058,{5U,2U,0U}}, +{SUB_9058,{6U,2U,0U}}, +{SUB_9058,{7U,2U,0U}}, +{SUB_9060,{0U,2U,0U}}, +{SUB_9060,{1U,2U,0U}}, +{SUB_9060,{2U,2U,0U}}, +{SUB_9060,{3U,2U,0U}}, +{SUB_9060,{4U,2U,0U}}, +{SUB_9060,{5U,2U,0U}}, +{SUB_9060,{6U,2U,0U}}, +{SUB_9060,{7U,2U,0U}}, +{SUB_9068,{0U,2U,0U}}, +{SUB_9068,{1U,2U,0U}}, +{SUB_9068,{2U,2U,0U}}, +{SUB_9068,{3U,2U,0U}}, +{SUB_9068,{4U,2U,0U}}, +{SUB_9068,{5U,2U,0U}}, +{SUB_9068,{6U,2U,0U}}, +{SUB_9068,{7U,2U,0U}}, +{SUB_9070,{0U,2U,0U}}, +{SUB_9070,{1U,2U,0U}}, +{SUB_9070,{2U,2U,0U}}, +{SUB_9070,{3U,2U,0U}}, +{SUB_9070,{4U,2U,0U}}, +{SUB_9070,{5U,2U,0U}}, +{SUB_9070,{6U,2U,0U}}, +{SUB_9070,{7U,2U,0U}}, +{SUB_9078,{0U,2U,0U}}, +{SUB_9079,{0U,2U,0U}}, +{SUB_907A,{0U,2U,0U}}, +{SUB_907B,{0U,2U,0U}}, +{SUB_907C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9080,{0U,2U,0U}}, +{SUB_9080,{1U,2U,0U}}, +{SUB_9080,{2U,2U,0U}}, +{SUB_9080,{3U,2U,0U}}, +{SUB_9080,{4U,2U,0U}}, +{SUB_9080,{5U,2U,0U}}, +{SUB_9080,{6U,2U,0U}}, +{SUB_9080,{7U,2U,0U}}, +{SUB_9088,{0U,2U,0U}}, +{SUB_9088,{1U,2U,0U}}, +{SUB_9088,{2U,2U,0U}}, +{SUB_9088,{3U,2U,0U}}, +{SUB_9088,{4U,2U,0U}}, +{SUB_9088,{5U,2U,0U}}, +{SUB_9088,{6U,2U,0U}}, +{SUB_9088,{7U,2U,0U}}, +{SUB_9090,{0U,2U,0U}}, +{SUB_9090,{1U,2U,0U}}, +{SUB_9090,{2U,2U,0U}}, +{SUB_9090,{3U,2U,0U}}, +{SUB_9090,{4U,2U,0U}}, +{SUB_9090,{5U,2U,0U}}, +{SUB_9090,{6U,2U,0U}}, +{SUB_9090,{7U,2U,0U}}, +{SUB_9098,{0U,2U,0U}}, +{SUB_9098,{1U,2U,0U}}, +{SUB_9098,{2U,2U,0U}}, +{SUB_9098,{3U,2U,0U}}, +{SUB_9098,{4U,2U,0U}}, +{SUB_9098,{5U,2U,0U}}, +{SUB_9098,{6U,2U,0U}}, +{SUB_9098,{7U,2U,0U}}, +{SUB_90A0,{0U,2U,0U}}, +{SUB_90A0,{1U,2U,0U}}, +{SUB_90A0,{2U,2U,0U}}, +{SUB_90A0,{3U,2U,0U}}, +{SUB_90A0,{4U,2U,0U}}, +{SUB_90A0,{5U,2U,0U}}, +{SUB_90A0,{6U,2U,0U}}, +{SUB_90A0,{7U,2U,0U}}, +{SUB_90A8,{0U,2U,0U}}, +{SUB_90A8,{1U,2U,0U}}, +{SUB_90A8,{2U,2U,0U}}, +{SUB_90A8,{3U,2U,0U}}, +{SUB_90A8,{4U,2U,0U}}, +{SUB_90A8,{5U,2U,0U}}, +{SUB_90A8,{6U,2U,0U}}, +{SUB_90A8,{7U,2U,0U}}, +{SUB_90B0,{0U,2U,0U}}, +{SUB_90B0,{1U,2U,0U}}, +{SUB_90B0,{2U,2U,0U}}, +{SUB_90B0,{3U,2U,0U}}, +{SUB_90B0,{4U,2U,0U}}, +{SUB_90B0,{5U,2U,0U}}, +{SUB_90B0,{6U,2U,0U}}, +{SUB_90B0,{7U,2U,0U}}, +{SUB_90B8,{0U,2U,0U}}, +{SUB_90B9,{0U,2U,0U}}, +{SUB_90BA,{0U,2U,0U}}, +{SUB_90BB,{0U,2U,0U}}, +{SUB_90BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_90C0,{0U,2U,0U}}, +{SUBA_90C0,{1U,2U,0U}}, +{SUBA_90C0,{2U,2U,0U}}, +{SUBA_90C0,{3U,2U,0U}}, +{SUBA_90C0,{4U,2U,0U}}, +{SUBA_90C0,{5U,2U,0U}}, +{SUBA_90C0,{6U,2U,0U}}, +{SUBA_90C0,{7U,2U,0U}}, +{SUBA_90C8,{0U,2U,0U}}, +{SUBA_90C8,{1U,2U,0U}}, +{SUBA_90C8,{2U,2U,0U}}, +{SUBA_90C8,{3U,2U,0U}}, +{SUBA_90C8,{4U,2U,0U}}, +{SUBA_90C8,{5U,2U,0U}}, +{SUBA_90C8,{6U,2U,0U}}, +{SUBA_90C8,{7U,2U,0U}}, +{SUBA_90D0,{0U,2U,0U}}, +{SUBA_90D0,{1U,2U,0U}}, +{SUBA_90D0,{2U,2U,0U}}, +{SUBA_90D0,{3U,2U,0U}}, +{SUBA_90D0,{4U,2U,0U}}, +{SUBA_90D0,{5U,2U,0U}}, +{SUBA_90D0,{6U,2U,0U}}, +{SUBA_90D0,{7U,2U,0U}}, +{SUBA_90D8,{0U,2U,0U}}, +{SUBA_90D8,{1U,2U,0U}}, +{SUBA_90D8,{2U,2U,0U}}, +{SUBA_90D8,{3U,2U,0U}}, +{SUBA_90D8,{4U,2U,0U}}, +{SUBA_90D8,{5U,2U,0U}}, +{SUBA_90D8,{6U,2U,0U}}, +{SUBA_90D8,{7U,2U,0U}}, +{SUBA_90E0,{0U,2U,0U}}, +{SUBA_90E0,{1U,2U,0U}}, +{SUBA_90E0,{2U,2U,0U}}, +{SUBA_90E0,{3U,2U,0U}}, +{SUBA_90E0,{4U,2U,0U}}, +{SUBA_90E0,{5U,2U,0U}}, +{SUBA_90E0,{6U,2U,0U}}, +{SUBA_90E0,{7U,2U,0U}}, +{SUBA_90E8,{0U,2U,0U}}, +{SUBA_90E8,{1U,2U,0U}}, +{SUBA_90E8,{2U,2U,0U}}, +{SUBA_90E8,{3U,2U,0U}}, +{SUBA_90E8,{4U,2U,0U}}, +{SUBA_90E8,{5U,2U,0U}}, +{SUBA_90E8,{6U,2U,0U}}, +{SUBA_90E8,{7U,2U,0U}}, +{SUBA_90F0,{0U,2U,0U}}, +{SUBA_90F0,{1U,2U,0U}}, +{SUBA_90F0,{2U,2U,0U}}, +{SUBA_90F0,{3U,2U,0U}}, +{SUBA_90F0,{4U,2U,0U}}, +{SUBA_90F0,{5U,2U,0U}}, +{SUBA_90F0,{6U,2U,0U}}, +{SUBA_90F0,{7U,2U,0U}}, +{SUBA_90F8,{0U,2U,0U}}, +{SUBA_90F9,{0U,2U,0U}}, +{SUBA_90FA,{0U,2U,0U}}, +{SUBA_90FB,{0U,2U,0U}}, +{SUBA_90FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9100,{0U,2U,0U}}, +{SUBX_9100,{1U,2U,0U}}, +{SUBX_9100,{2U,2U,0U}}, +{SUBX_9100,{3U,2U,0U}}, +{SUBX_9100,{4U,2U,0U}}, +{SUBX_9100,{5U,2U,0U}}, +{SUBX_9100,{6U,2U,0U}}, +{SUBX_9100,{7U,2U,0U}}, +{SUBX_9108,{0U,2U,0U}}, +{SUBX_9108,{1U,2U,0U}}, +{SUBX_9108,{2U,2U,0U}}, +{SUBX_9108,{3U,2U,0U}}, +{SUBX_9108,{4U,2U,0U}}, +{SUBX_9108,{5U,2U,0U}}, +{SUBX_9108,{6U,2U,0U}}, +{SUBX_9108,{7U,2U,0U}}, +{SUB_9110,{0U,2U,0U}}, +{SUB_9110,{1U,2U,0U}}, +{SUB_9110,{2U,2U,0U}}, +{SUB_9110,{3U,2U,0U}}, +{SUB_9110,{4U,2U,0U}}, +{SUB_9110,{5U,2U,0U}}, +{SUB_9110,{6U,2U,0U}}, +{SUB_9110,{7U,2U,0U}}, +{SUB_9118,{0U,2U,0U}}, +{SUB_9118,{1U,2U,0U}}, +{SUB_9118,{2U,2U,0U}}, +{SUB_9118,{3U,2U,0U}}, +{SUB_9118,{4U,2U,0U}}, +{SUB_9118,{5U,2U,0U}}, +{SUB_9118,{6U,2U,0U}}, +{SUB_9118,{7U,2U,0U}}, +{SUB_9120,{0U,2U,0U}}, +{SUB_9120,{1U,2U,0U}}, +{SUB_9120,{2U,2U,0U}}, +{SUB_9120,{3U,2U,0U}}, +{SUB_9120,{4U,2U,0U}}, +{SUB_9120,{5U,2U,0U}}, +{SUB_9120,{6U,2U,0U}}, +{SUB_9120,{7U,2U,0U}}, +{SUB_9128,{0U,2U,0U}}, +{SUB_9128,{1U,2U,0U}}, +{SUB_9128,{2U,2U,0U}}, +{SUB_9128,{3U,2U,0U}}, +{SUB_9128,{4U,2U,0U}}, +{SUB_9128,{5U,2U,0U}}, +{SUB_9128,{6U,2U,0U}}, +{SUB_9128,{7U,2U,0U}}, +{SUB_9130,{0U,2U,0U}}, +{SUB_9130,{1U,2U,0U}}, +{SUB_9130,{2U,2U,0U}}, +{SUB_9130,{3U,2U,0U}}, +{SUB_9130,{4U,2U,0U}}, +{SUB_9130,{5U,2U,0U}}, +{SUB_9130,{6U,2U,0U}}, +{SUB_9130,{7U,2U,0U}}, +{SUB_9138,{0U,2U,0U}}, +{SUB_9139,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9140,{0U,2U,0U}}, +{SUBX_9140,{1U,2U,0U}}, +{SUBX_9140,{2U,2U,0U}}, +{SUBX_9140,{3U,2U,0U}}, +{SUBX_9140,{4U,2U,0U}}, +{SUBX_9140,{5U,2U,0U}}, +{SUBX_9140,{6U,2U,0U}}, +{SUBX_9140,{7U,2U,0U}}, +{SUBX_9148,{0U,2U,0U}}, +{SUBX_9148,{1U,2U,0U}}, +{SUBX_9148,{2U,2U,0U}}, +{SUBX_9148,{3U,2U,0U}}, +{SUBX_9148,{4U,2U,0U}}, +{SUBX_9148,{5U,2U,0U}}, +{SUBX_9148,{6U,2U,0U}}, +{SUBX_9148,{7U,2U,0U}}, +{SUB_9150,{0U,2U,0U}}, +{SUB_9150,{1U,2U,0U}}, +{SUB_9150,{2U,2U,0U}}, +{SUB_9150,{3U,2U,0U}}, +{SUB_9150,{4U,2U,0U}}, +{SUB_9150,{5U,2U,0U}}, +{SUB_9150,{6U,2U,0U}}, +{SUB_9150,{7U,2U,0U}}, +{SUB_9158,{0U,2U,0U}}, +{SUB_9158,{1U,2U,0U}}, +{SUB_9158,{2U,2U,0U}}, +{SUB_9158,{3U,2U,0U}}, +{SUB_9158,{4U,2U,0U}}, +{SUB_9158,{5U,2U,0U}}, +{SUB_9158,{6U,2U,0U}}, +{SUB_9158,{7U,2U,0U}}, +{SUB_9160,{0U,2U,0U}}, +{SUB_9160,{1U,2U,0U}}, +{SUB_9160,{2U,2U,0U}}, +{SUB_9160,{3U,2U,0U}}, +{SUB_9160,{4U,2U,0U}}, +{SUB_9160,{5U,2U,0U}}, +{SUB_9160,{6U,2U,0U}}, +{SUB_9160,{7U,2U,0U}}, +{SUB_9168,{0U,2U,0U}}, +{SUB_9168,{1U,2U,0U}}, +{SUB_9168,{2U,2U,0U}}, +{SUB_9168,{3U,2U,0U}}, +{SUB_9168,{4U,2U,0U}}, +{SUB_9168,{5U,2U,0U}}, +{SUB_9168,{6U,2U,0U}}, +{SUB_9168,{7U,2U,0U}}, +{SUB_9170,{0U,2U,0U}}, +{SUB_9170,{1U,2U,0U}}, +{SUB_9170,{2U,2U,0U}}, +{SUB_9170,{3U,2U,0U}}, +{SUB_9170,{4U,2U,0U}}, +{SUB_9170,{5U,2U,0U}}, +{SUB_9170,{6U,2U,0U}}, +{SUB_9170,{7U,2U,0U}}, +{SUB_9178,{0U,2U,0U}}, +{SUB_9179,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9180,{0U,2U,0U}}, +{SUBX_9180,{1U,2U,0U}}, +{SUBX_9180,{2U,2U,0U}}, +{SUBX_9180,{3U,2U,0U}}, +{SUBX_9180,{4U,2U,0U}}, +{SUBX_9180,{5U,2U,0U}}, +{SUBX_9180,{6U,2U,0U}}, +{SUBX_9180,{7U,2U,0U}}, +{SUBX_9188,{0U,2U,0U}}, +{SUBX_9188,{1U,2U,0U}}, +{SUBX_9188,{2U,2U,0U}}, +{SUBX_9188,{3U,2U,0U}}, +{SUBX_9188,{4U,2U,0U}}, +{SUBX_9188,{5U,2U,0U}}, +{SUBX_9188,{6U,2U,0U}}, +{SUBX_9188,{7U,2U,0U}}, +{SUB_9190,{0U,2U,0U}}, +{SUB_9190,{1U,2U,0U}}, +{SUB_9190,{2U,2U,0U}}, +{SUB_9190,{3U,2U,0U}}, +{SUB_9190,{4U,2U,0U}}, +{SUB_9190,{5U,2U,0U}}, +{SUB_9190,{6U,2U,0U}}, +{SUB_9190,{7U,2U,0U}}, +{SUB_9198,{0U,2U,0U}}, +{SUB_9198,{1U,2U,0U}}, +{SUB_9198,{2U,2U,0U}}, +{SUB_9198,{3U,2U,0U}}, +{SUB_9198,{4U,2U,0U}}, +{SUB_9198,{5U,2U,0U}}, +{SUB_9198,{6U,2U,0U}}, +{SUB_9198,{7U,2U,0U}}, +{SUB_91A0,{0U,2U,0U}}, +{SUB_91A0,{1U,2U,0U}}, +{SUB_91A0,{2U,2U,0U}}, +{SUB_91A0,{3U,2U,0U}}, +{SUB_91A0,{4U,2U,0U}}, +{SUB_91A0,{5U,2U,0U}}, +{SUB_91A0,{6U,2U,0U}}, +{SUB_91A0,{7U,2U,0U}}, +{SUB_91A8,{0U,2U,0U}}, +{SUB_91A8,{1U,2U,0U}}, +{SUB_91A8,{2U,2U,0U}}, +{SUB_91A8,{3U,2U,0U}}, +{SUB_91A8,{4U,2U,0U}}, +{SUB_91A8,{5U,2U,0U}}, +{SUB_91A8,{6U,2U,0U}}, +{SUB_91A8,{7U,2U,0U}}, +{SUB_91B0,{0U,2U,0U}}, +{SUB_91B0,{1U,2U,0U}}, +{SUB_91B0,{2U,2U,0U}}, +{SUB_91B0,{3U,2U,0U}}, +{SUB_91B0,{4U,2U,0U}}, +{SUB_91B0,{5U,2U,0U}}, +{SUB_91B0,{6U,2U,0U}}, +{SUB_91B0,{7U,2U,0U}}, +{SUB_91B8,{0U,2U,0U}}, +{SUB_91B9,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_91C0,{0U,2U,0U}}, +{SUBA_91C0,{1U,2U,0U}}, +{SUBA_91C0,{2U,2U,0U}}, +{SUBA_91C0,{3U,2U,0U}}, +{SUBA_91C0,{4U,2U,0U}}, +{SUBA_91C0,{5U,2U,0U}}, +{SUBA_91C0,{6U,2U,0U}}, +{SUBA_91C0,{7U,2U,0U}}, +{SUBA_91C8,{0U,2U,0U}}, +{SUBA_91C8,{1U,2U,0U}}, +{SUBA_91C8,{2U,2U,0U}}, +{SUBA_91C8,{3U,2U,0U}}, +{SUBA_91C8,{4U,2U,0U}}, +{SUBA_91C8,{5U,2U,0U}}, +{SUBA_91C8,{6U,2U,0U}}, +{SUBA_91C8,{7U,2U,0U}}, +{SUBA_91D0,{0U,2U,0U}}, +{SUBA_91D0,{1U,2U,0U}}, +{SUBA_91D0,{2U,2U,0U}}, +{SUBA_91D0,{3U,2U,0U}}, +{SUBA_91D0,{4U,2U,0U}}, +{SUBA_91D0,{5U,2U,0U}}, +{SUBA_91D0,{6U,2U,0U}}, +{SUBA_91D0,{7U,2U,0U}}, +{SUBA_91D8,{0U,2U,0U}}, +{SUBA_91D8,{1U,2U,0U}}, +{SUBA_91D8,{2U,2U,0U}}, +{SUBA_91D8,{3U,2U,0U}}, +{SUBA_91D8,{4U,2U,0U}}, +{SUBA_91D8,{5U,2U,0U}}, +{SUBA_91D8,{6U,2U,0U}}, +{SUBA_91D8,{7U,2U,0U}}, +{SUBA_91E0,{0U,2U,0U}}, +{SUBA_91E0,{1U,2U,0U}}, +{SUBA_91E0,{2U,2U,0U}}, +{SUBA_91E0,{3U,2U,0U}}, +{SUBA_91E0,{4U,2U,0U}}, +{SUBA_91E0,{5U,2U,0U}}, +{SUBA_91E0,{6U,2U,0U}}, +{SUBA_91E0,{7U,2U,0U}}, +{SUBA_91E8,{0U,2U,0U}}, +{SUBA_91E8,{1U,2U,0U}}, +{SUBA_91E8,{2U,2U,0U}}, +{SUBA_91E8,{3U,2U,0U}}, +{SUBA_91E8,{4U,2U,0U}}, +{SUBA_91E8,{5U,2U,0U}}, +{SUBA_91E8,{6U,2U,0U}}, +{SUBA_91E8,{7U,2U,0U}}, +{SUBA_91F0,{0U,2U,0U}}, +{SUBA_91F0,{1U,2U,0U}}, +{SUBA_91F0,{2U,2U,0U}}, +{SUBA_91F0,{3U,2U,0U}}, +{SUBA_91F0,{4U,2U,0U}}, +{SUBA_91F0,{5U,2U,0U}}, +{SUBA_91F0,{6U,2U,0U}}, +{SUBA_91F0,{7U,2U,0U}}, +{SUBA_91F8,{0U,2U,0U}}, +{SUBA_91F9,{0U,2U,0U}}, +{SUBA_91FA,{0U,2U,0U}}, +{SUBA_91FB,{0U,2U,0U}}, +{SUBA_91FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9000,{0U,3U,0U}}, +{SUB_9000,{1U,3U,0U}}, +{SUB_9000,{2U,3U,0U}}, +{SUB_9000,{3U,3U,0U}}, +{SUB_9000,{4U,3U,0U}}, +{SUB_9000,{5U,3U,0U}}, +{SUB_9000,{6U,3U,0U}}, +{SUB_9000,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9010,{0U,3U,0U}}, +{SUB_9010,{1U,3U,0U}}, +{SUB_9010,{2U,3U,0U}}, +{SUB_9010,{3U,3U,0U}}, +{SUB_9010,{4U,3U,0U}}, +{SUB_9010,{5U,3U,0U}}, +{SUB_9010,{6U,3U,0U}}, +{SUB_9010,{7U,3U,0U}}, +{SUB_9018,{0U,3U,0U}}, +{SUB_9018,{1U,3U,0U}}, +{SUB_9018,{2U,3U,0U}}, +{SUB_9018,{3U,3U,0U}}, +{SUB_9018,{4U,3U,0U}}, +{SUB_9018,{5U,3U,0U}}, +{SUB_9018,{6U,3U,0U}}, +{SUB_9018,{7U,3U,0U}}, +{SUB_9020,{0U,3U,0U}}, +{SUB_9020,{1U,3U,0U}}, +{SUB_9020,{2U,3U,0U}}, +{SUB_9020,{3U,3U,0U}}, +{SUB_9020,{4U,3U,0U}}, +{SUB_9020,{5U,3U,0U}}, +{SUB_9020,{6U,3U,0U}}, +{SUB_9020,{7U,3U,0U}}, +{SUB_9028,{0U,3U,0U}}, +{SUB_9028,{1U,3U,0U}}, +{SUB_9028,{2U,3U,0U}}, +{SUB_9028,{3U,3U,0U}}, +{SUB_9028,{4U,3U,0U}}, +{SUB_9028,{5U,3U,0U}}, +{SUB_9028,{6U,3U,0U}}, +{SUB_9028,{7U,3U,0U}}, +{SUB_9030,{0U,3U,0U}}, +{SUB_9030,{1U,3U,0U}}, +{SUB_9030,{2U,3U,0U}}, +{SUB_9030,{3U,3U,0U}}, +{SUB_9030,{4U,3U,0U}}, +{SUB_9030,{5U,3U,0U}}, +{SUB_9030,{6U,3U,0U}}, +{SUB_9030,{7U,3U,0U}}, +{SUB_9038,{0U,3U,0U}}, +{SUB_9039,{0U,3U,0U}}, +{SUB_903A,{0U,3U,0U}}, +{SUB_903B,{0U,3U,0U}}, +{SUB_903C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9040,{0U,3U,0U}}, +{SUB_9040,{1U,3U,0U}}, +{SUB_9040,{2U,3U,0U}}, +{SUB_9040,{3U,3U,0U}}, +{SUB_9040,{4U,3U,0U}}, +{SUB_9040,{5U,3U,0U}}, +{SUB_9040,{6U,3U,0U}}, +{SUB_9040,{7U,3U,0U}}, +{SUB_9048,{0U,3U,0U}}, +{SUB_9048,{1U,3U,0U}}, +{SUB_9048,{2U,3U,0U}}, +{SUB_9048,{3U,3U,0U}}, +{SUB_9048,{4U,3U,0U}}, +{SUB_9048,{5U,3U,0U}}, +{SUB_9048,{6U,3U,0U}}, +{SUB_9048,{7U,3U,0U}}, +{SUB_9050,{0U,3U,0U}}, +{SUB_9050,{1U,3U,0U}}, +{SUB_9050,{2U,3U,0U}}, +{SUB_9050,{3U,3U,0U}}, +{SUB_9050,{4U,3U,0U}}, +{SUB_9050,{5U,3U,0U}}, +{SUB_9050,{6U,3U,0U}}, +{SUB_9050,{7U,3U,0U}}, +{SUB_9058,{0U,3U,0U}}, +{SUB_9058,{1U,3U,0U}}, +{SUB_9058,{2U,3U,0U}}, +{SUB_9058,{3U,3U,0U}}, +{SUB_9058,{4U,3U,0U}}, +{SUB_9058,{5U,3U,0U}}, +{SUB_9058,{6U,3U,0U}}, +{SUB_9058,{7U,3U,0U}}, +{SUB_9060,{0U,3U,0U}}, +{SUB_9060,{1U,3U,0U}}, +{SUB_9060,{2U,3U,0U}}, +{SUB_9060,{3U,3U,0U}}, +{SUB_9060,{4U,3U,0U}}, +{SUB_9060,{5U,3U,0U}}, +{SUB_9060,{6U,3U,0U}}, +{SUB_9060,{7U,3U,0U}}, +{SUB_9068,{0U,3U,0U}}, +{SUB_9068,{1U,3U,0U}}, +{SUB_9068,{2U,3U,0U}}, +{SUB_9068,{3U,3U,0U}}, +{SUB_9068,{4U,3U,0U}}, +{SUB_9068,{5U,3U,0U}}, +{SUB_9068,{6U,3U,0U}}, +{SUB_9068,{7U,3U,0U}}, +{SUB_9070,{0U,3U,0U}}, +{SUB_9070,{1U,3U,0U}}, +{SUB_9070,{2U,3U,0U}}, +{SUB_9070,{3U,3U,0U}}, +{SUB_9070,{4U,3U,0U}}, +{SUB_9070,{5U,3U,0U}}, +{SUB_9070,{6U,3U,0U}}, +{SUB_9070,{7U,3U,0U}}, +{SUB_9078,{0U,3U,0U}}, +{SUB_9079,{0U,3U,0U}}, +{SUB_907A,{0U,3U,0U}}, +{SUB_907B,{0U,3U,0U}}, +{SUB_907C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9080,{0U,3U,0U}}, +{SUB_9080,{1U,3U,0U}}, +{SUB_9080,{2U,3U,0U}}, +{SUB_9080,{3U,3U,0U}}, +{SUB_9080,{4U,3U,0U}}, +{SUB_9080,{5U,3U,0U}}, +{SUB_9080,{6U,3U,0U}}, +{SUB_9080,{7U,3U,0U}}, +{SUB_9088,{0U,3U,0U}}, +{SUB_9088,{1U,3U,0U}}, +{SUB_9088,{2U,3U,0U}}, +{SUB_9088,{3U,3U,0U}}, +{SUB_9088,{4U,3U,0U}}, +{SUB_9088,{5U,3U,0U}}, +{SUB_9088,{6U,3U,0U}}, +{SUB_9088,{7U,3U,0U}}, +{SUB_9090,{0U,3U,0U}}, +{SUB_9090,{1U,3U,0U}}, +{SUB_9090,{2U,3U,0U}}, +{SUB_9090,{3U,3U,0U}}, +{SUB_9090,{4U,3U,0U}}, +{SUB_9090,{5U,3U,0U}}, +{SUB_9090,{6U,3U,0U}}, +{SUB_9090,{7U,3U,0U}}, +{SUB_9098,{0U,3U,0U}}, +{SUB_9098,{1U,3U,0U}}, +{SUB_9098,{2U,3U,0U}}, +{SUB_9098,{3U,3U,0U}}, +{SUB_9098,{4U,3U,0U}}, +{SUB_9098,{5U,3U,0U}}, +{SUB_9098,{6U,3U,0U}}, +{SUB_9098,{7U,3U,0U}}, +{SUB_90A0,{0U,3U,0U}}, +{SUB_90A0,{1U,3U,0U}}, +{SUB_90A0,{2U,3U,0U}}, +{SUB_90A0,{3U,3U,0U}}, +{SUB_90A0,{4U,3U,0U}}, +{SUB_90A0,{5U,3U,0U}}, +{SUB_90A0,{6U,3U,0U}}, +{SUB_90A0,{7U,3U,0U}}, +{SUB_90A8,{0U,3U,0U}}, +{SUB_90A8,{1U,3U,0U}}, +{SUB_90A8,{2U,3U,0U}}, +{SUB_90A8,{3U,3U,0U}}, +{SUB_90A8,{4U,3U,0U}}, +{SUB_90A8,{5U,3U,0U}}, +{SUB_90A8,{6U,3U,0U}}, +{SUB_90A8,{7U,3U,0U}}, +{SUB_90B0,{0U,3U,0U}}, +{SUB_90B0,{1U,3U,0U}}, +{SUB_90B0,{2U,3U,0U}}, +{SUB_90B0,{3U,3U,0U}}, +{SUB_90B0,{4U,3U,0U}}, +{SUB_90B0,{5U,3U,0U}}, +{SUB_90B0,{6U,3U,0U}}, +{SUB_90B0,{7U,3U,0U}}, +{SUB_90B8,{0U,3U,0U}}, +{SUB_90B9,{0U,3U,0U}}, +{SUB_90BA,{0U,3U,0U}}, +{SUB_90BB,{0U,3U,0U}}, +{SUB_90BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_90C0,{0U,3U,0U}}, +{SUBA_90C0,{1U,3U,0U}}, +{SUBA_90C0,{2U,3U,0U}}, +{SUBA_90C0,{3U,3U,0U}}, +{SUBA_90C0,{4U,3U,0U}}, +{SUBA_90C0,{5U,3U,0U}}, +{SUBA_90C0,{6U,3U,0U}}, +{SUBA_90C0,{7U,3U,0U}}, +{SUBA_90C8,{0U,3U,0U}}, +{SUBA_90C8,{1U,3U,0U}}, +{SUBA_90C8,{2U,3U,0U}}, +{SUBA_90C8,{3U,3U,0U}}, +{SUBA_90C8,{4U,3U,0U}}, +{SUBA_90C8,{5U,3U,0U}}, +{SUBA_90C8,{6U,3U,0U}}, +{SUBA_90C8,{7U,3U,0U}}, +{SUBA_90D0,{0U,3U,0U}}, +{SUBA_90D0,{1U,3U,0U}}, +{SUBA_90D0,{2U,3U,0U}}, +{SUBA_90D0,{3U,3U,0U}}, +{SUBA_90D0,{4U,3U,0U}}, +{SUBA_90D0,{5U,3U,0U}}, +{SUBA_90D0,{6U,3U,0U}}, +{SUBA_90D0,{7U,3U,0U}}, +{SUBA_90D8,{0U,3U,0U}}, +{SUBA_90D8,{1U,3U,0U}}, +{SUBA_90D8,{2U,3U,0U}}, +{SUBA_90D8,{3U,3U,0U}}, +{SUBA_90D8,{4U,3U,0U}}, +{SUBA_90D8,{5U,3U,0U}}, +{SUBA_90D8,{6U,3U,0U}}, +{SUBA_90D8,{7U,3U,0U}}, +{SUBA_90E0,{0U,3U,0U}}, +{SUBA_90E0,{1U,3U,0U}}, +{SUBA_90E0,{2U,3U,0U}}, +{SUBA_90E0,{3U,3U,0U}}, +{SUBA_90E0,{4U,3U,0U}}, +{SUBA_90E0,{5U,3U,0U}}, +{SUBA_90E0,{6U,3U,0U}}, +{SUBA_90E0,{7U,3U,0U}}, +{SUBA_90E8,{0U,3U,0U}}, +{SUBA_90E8,{1U,3U,0U}}, +{SUBA_90E8,{2U,3U,0U}}, +{SUBA_90E8,{3U,3U,0U}}, +{SUBA_90E8,{4U,3U,0U}}, +{SUBA_90E8,{5U,3U,0U}}, +{SUBA_90E8,{6U,3U,0U}}, +{SUBA_90E8,{7U,3U,0U}}, +{SUBA_90F0,{0U,3U,0U}}, +{SUBA_90F0,{1U,3U,0U}}, +{SUBA_90F0,{2U,3U,0U}}, +{SUBA_90F0,{3U,3U,0U}}, +{SUBA_90F0,{4U,3U,0U}}, +{SUBA_90F0,{5U,3U,0U}}, +{SUBA_90F0,{6U,3U,0U}}, +{SUBA_90F0,{7U,3U,0U}}, +{SUBA_90F8,{0U,3U,0U}}, +{SUBA_90F9,{0U,3U,0U}}, +{SUBA_90FA,{0U,3U,0U}}, +{SUBA_90FB,{0U,3U,0U}}, +{SUBA_90FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9100,{0U,3U,0U}}, +{SUBX_9100,{1U,3U,0U}}, +{SUBX_9100,{2U,3U,0U}}, +{SUBX_9100,{3U,3U,0U}}, +{SUBX_9100,{4U,3U,0U}}, +{SUBX_9100,{5U,3U,0U}}, +{SUBX_9100,{6U,3U,0U}}, +{SUBX_9100,{7U,3U,0U}}, +{SUBX_9108,{0U,3U,0U}}, +{SUBX_9108,{1U,3U,0U}}, +{SUBX_9108,{2U,3U,0U}}, +{SUBX_9108,{3U,3U,0U}}, +{SUBX_9108,{4U,3U,0U}}, +{SUBX_9108,{5U,3U,0U}}, +{SUBX_9108,{6U,3U,0U}}, +{SUBX_9108,{7U,3U,0U}}, +{SUB_9110,{0U,3U,0U}}, +{SUB_9110,{1U,3U,0U}}, +{SUB_9110,{2U,3U,0U}}, +{SUB_9110,{3U,3U,0U}}, +{SUB_9110,{4U,3U,0U}}, +{SUB_9110,{5U,3U,0U}}, +{SUB_9110,{6U,3U,0U}}, +{SUB_9110,{7U,3U,0U}}, +{SUB_9118,{0U,3U,0U}}, +{SUB_9118,{1U,3U,0U}}, +{SUB_9118,{2U,3U,0U}}, +{SUB_9118,{3U,3U,0U}}, +{SUB_9118,{4U,3U,0U}}, +{SUB_9118,{5U,3U,0U}}, +{SUB_9118,{6U,3U,0U}}, +{SUB_9118,{7U,3U,0U}}, +{SUB_9120,{0U,3U,0U}}, +{SUB_9120,{1U,3U,0U}}, +{SUB_9120,{2U,3U,0U}}, +{SUB_9120,{3U,3U,0U}}, +{SUB_9120,{4U,3U,0U}}, +{SUB_9120,{5U,3U,0U}}, +{SUB_9120,{6U,3U,0U}}, +{SUB_9120,{7U,3U,0U}}, +{SUB_9128,{0U,3U,0U}}, +{SUB_9128,{1U,3U,0U}}, +{SUB_9128,{2U,3U,0U}}, +{SUB_9128,{3U,3U,0U}}, +{SUB_9128,{4U,3U,0U}}, +{SUB_9128,{5U,3U,0U}}, +{SUB_9128,{6U,3U,0U}}, +{SUB_9128,{7U,3U,0U}}, +{SUB_9130,{0U,3U,0U}}, +{SUB_9130,{1U,3U,0U}}, +{SUB_9130,{2U,3U,0U}}, +{SUB_9130,{3U,3U,0U}}, +{SUB_9130,{4U,3U,0U}}, +{SUB_9130,{5U,3U,0U}}, +{SUB_9130,{6U,3U,0U}}, +{SUB_9130,{7U,3U,0U}}, +{SUB_9138,{0U,3U,0U}}, +{SUB_9139,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9140,{0U,3U,0U}}, +{SUBX_9140,{1U,3U,0U}}, +{SUBX_9140,{2U,3U,0U}}, +{SUBX_9140,{3U,3U,0U}}, +{SUBX_9140,{4U,3U,0U}}, +{SUBX_9140,{5U,3U,0U}}, +{SUBX_9140,{6U,3U,0U}}, +{SUBX_9140,{7U,3U,0U}}, +{SUBX_9148,{0U,3U,0U}}, +{SUBX_9148,{1U,3U,0U}}, +{SUBX_9148,{2U,3U,0U}}, +{SUBX_9148,{3U,3U,0U}}, +{SUBX_9148,{4U,3U,0U}}, +{SUBX_9148,{5U,3U,0U}}, +{SUBX_9148,{6U,3U,0U}}, +{SUBX_9148,{7U,3U,0U}}, +{SUB_9150,{0U,3U,0U}}, +{SUB_9150,{1U,3U,0U}}, +{SUB_9150,{2U,3U,0U}}, +{SUB_9150,{3U,3U,0U}}, +{SUB_9150,{4U,3U,0U}}, +{SUB_9150,{5U,3U,0U}}, +{SUB_9150,{6U,3U,0U}}, +{SUB_9150,{7U,3U,0U}}, +{SUB_9158,{0U,3U,0U}}, +{SUB_9158,{1U,3U,0U}}, +{SUB_9158,{2U,3U,0U}}, +{SUB_9158,{3U,3U,0U}}, +{SUB_9158,{4U,3U,0U}}, +{SUB_9158,{5U,3U,0U}}, +{SUB_9158,{6U,3U,0U}}, +{SUB_9158,{7U,3U,0U}}, +{SUB_9160,{0U,3U,0U}}, +{SUB_9160,{1U,3U,0U}}, +{SUB_9160,{2U,3U,0U}}, +{SUB_9160,{3U,3U,0U}}, +{SUB_9160,{4U,3U,0U}}, +{SUB_9160,{5U,3U,0U}}, +{SUB_9160,{6U,3U,0U}}, +{SUB_9160,{7U,3U,0U}}, +{SUB_9168,{0U,3U,0U}}, +{SUB_9168,{1U,3U,0U}}, +{SUB_9168,{2U,3U,0U}}, +{SUB_9168,{3U,3U,0U}}, +{SUB_9168,{4U,3U,0U}}, +{SUB_9168,{5U,3U,0U}}, +{SUB_9168,{6U,3U,0U}}, +{SUB_9168,{7U,3U,0U}}, +{SUB_9170,{0U,3U,0U}}, +{SUB_9170,{1U,3U,0U}}, +{SUB_9170,{2U,3U,0U}}, +{SUB_9170,{3U,3U,0U}}, +{SUB_9170,{4U,3U,0U}}, +{SUB_9170,{5U,3U,0U}}, +{SUB_9170,{6U,3U,0U}}, +{SUB_9170,{7U,3U,0U}}, +{SUB_9178,{0U,3U,0U}}, +{SUB_9179,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9180,{0U,3U,0U}}, +{SUBX_9180,{1U,3U,0U}}, +{SUBX_9180,{2U,3U,0U}}, +{SUBX_9180,{3U,3U,0U}}, +{SUBX_9180,{4U,3U,0U}}, +{SUBX_9180,{5U,3U,0U}}, +{SUBX_9180,{6U,3U,0U}}, +{SUBX_9180,{7U,3U,0U}}, +{SUBX_9188,{0U,3U,0U}}, +{SUBX_9188,{1U,3U,0U}}, +{SUBX_9188,{2U,3U,0U}}, +{SUBX_9188,{3U,3U,0U}}, +{SUBX_9188,{4U,3U,0U}}, +{SUBX_9188,{5U,3U,0U}}, +{SUBX_9188,{6U,3U,0U}}, +{SUBX_9188,{7U,3U,0U}}, +{SUB_9190,{0U,3U,0U}}, +{SUB_9190,{1U,3U,0U}}, +{SUB_9190,{2U,3U,0U}}, +{SUB_9190,{3U,3U,0U}}, +{SUB_9190,{4U,3U,0U}}, +{SUB_9190,{5U,3U,0U}}, +{SUB_9190,{6U,3U,0U}}, +{SUB_9190,{7U,3U,0U}}, +{SUB_9198,{0U,3U,0U}}, +{SUB_9198,{1U,3U,0U}}, +{SUB_9198,{2U,3U,0U}}, +{SUB_9198,{3U,3U,0U}}, +{SUB_9198,{4U,3U,0U}}, +{SUB_9198,{5U,3U,0U}}, +{SUB_9198,{6U,3U,0U}}, +{SUB_9198,{7U,3U,0U}}, +{SUB_91A0,{0U,3U,0U}}, +{SUB_91A0,{1U,3U,0U}}, +{SUB_91A0,{2U,3U,0U}}, +{SUB_91A0,{3U,3U,0U}}, +{SUB_91A0,{4U,3U,0U}}, +{SUB_91A0,{5U,3U,0U}}, +{SUB_91A0,{6U,3U,0U}}, +{SUB_91A0,{7U,3U,0U}}, +{SUB_91A8,{0U,3U,0U}}, +{SUB_91A8,{1U,3U,0U}}, +{SUB_91A8,{2U,3U,0U}}, +{SUB_91A8,{3U,3U,0U}}, +{SUB_91A8,{4U,3U,0U}}, +{SUB_91A8,{5U,3U,0U}}, +{SUB_91A8,{6U,3U,0U}}, +{SUB_91A8,{7U,3U,0U}}, +{SUB_91B0,{0U,3U,0U}}, +{SUB_91B0,{1U,3U,0U}}, +{SUB_91B0,{2U,3U,0U}}, +{SUB_91B0,{3U,3U,0U}}, +{SUB_91B0,{4U,3U,0U}}, +{SUB_91B0,{5U,3U,0U}}, +{SUB_91B0,{6U,3U,0U}}, +{SUB_91B0,{7U,3U,0U}}, +{SUB_91B8,{0U,3U,0U}}, +{SUB_91B9,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_91C0,{0U,3U,0U}}, +{SUBA_91C0,{1U,3U,0U}}, +{SUBA_91C0,{2U,3U,0U}}, +{SUBA_91C0,{3U,3U,0U}}, +{SUBA_91C0,{4U,3U,0U}}, +{SUBA_91C0,{5U,3U,0U}}, +{SUBA_91C0,{6U,3U,0U}}, +{SUBA_91C0,{7U,3U,0U}}, +{SUBA_91C8,{0U,3U,0U}}, +{SUBA_91C8,{1U,3U,0U}}, +{SUBA_91C8,{2U,3U,0U}}, +{SUBA_91C8,{3U,3U,0U}}, +{SUBA_91C8,{4U,3U,0U}}, +{SUBA_91C8,{5U,3U,0U}}, +{SUBA_91C8,{6U,3U,0U}}, +{SUBA_91C8,{7U,3U,0U}}, +{SUBA_91D0,{0U,3U,0U}}, +{SUBA_91D0,{1U,3U,0U}}, +{SUBA_91D0,{2U,3U,0U}}, +{SUBA_91D0,{3U,3U,0U}}, +{SUBA_91D0,{4U,3U,0U}}, +{SUBA_91D0,{5U,3U,0U}}, +{SUBA_91D0,{6U,3U,0U}}, +{SUBA_91D0,{7U,3U,0U}}, +{SUBA_91D8,{0U,3U,0U}}, +{SUBA_91D8,{1U,3U,0U}}, +{SUBA_91D8,{2U,3U,0U}}, +{SUBA_91D8,{3U,3U,0U}}, +{SUBA_91D8,{4U,3U,0U}}, +{SUBA_91D8,{5U,3U,0U}}, +{SUBA_91D8,{6U,3U,0U}}, +{SUBA_91D8,{7U,3U,0U}}, +{SUBA_91E0,{0U,3U,0U}}, +{SUBA_91E0,{1U,3U,0U}}, +{SUBA_91E0,{2U,3U,0U}}, +{SUBA_91E0,{3U,3U,0U}}, +{SUBA_91E0,{4U,3U,0U}}, +{SUBA_91E0,{5U,3U,0U}}, +{SUBA_91E0,{6U,3U,0U}}, +{SUBA_91E0,{7U,3U,0U}}, +{SUBA_91E8,{0U,3U,0U}}, +{SUBA_91E8,{1U,3U,0U}}, +{SUBA_91E8,{2U,3U,0U}}, +{SUBA_91E8,{3U,3U,0U}}, +{SUBA_91E8,{4U,3U,0U}}, +{SUBA_91E8,{5U,3U,0U}}, +{SUBA_91E8,{6U,3U,0U}}, +{SUBA_91E8,{7U,3U,0U}}, +{SUBA_91F0,{0U,3U,0U}}, +{SUBA_91F0,{1U,3U,0U}}, +{SUBA_91F0,{2U,3U,0U}}, +{SUBA_91F0,{3U,3U,0U}}, +{SUBA_91F0,{4U,3U,0U}}, +{SUBA_91F0,{5U,3U,0U}}, +{SUBA_91F0,{6U,3U,0U}}, +{SUBA_91F0,{7U,3U,0U}}, +{SUBA_91F8,{0U,3U,0U}}, +{SUBA_91F9,{0U,3U,0U}}, +{SUBA_91FA,{0U,3U,0U}}, +{SUBA_91FB,{0U,3U,0U}}, +{SUBA_91FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9000,{0U,4U,0U}}, +{SUB_9000,{1U,4U,0U}}, +{SUB_9000,{2U,4U,0U}}, +{SUB_9000,{3U,4U,0U}}, +{SUB_9000,{4U,4U,0U}}, +{SUB_9000,{5U,4U,0U}}, +{SUB_9000,{6U,4U,0U}}, +{SUB_9000,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9010,{0U,4U,0U}}, +{SUB_9010,{1U,4U,0U}}, +{SUB_9010,{2U,4U,0U}}, +{SUB_9010,{3U,4U,0U}}, +{SUB_9010,{4U,4U,0U}}, +{SUB_9010,{5U,4U,0U}}, +{SUB_9010,{6U,4U,0U}}, +{SUB_9010,{7U,4U,0U}}, +{SUB_9018,{0U,4U,0U}}, +{SUB_9018,{1U,4U,0U}}, +{SUB_9018,{2U,4U,0U}}, +{SUB_9018,{3U,4U,0U}}, +{SUB_9018,{4U,4U,0U}}, +{SUB_9018,{5U,4U,0U}}, +{SUB_9018,{6U,4U,0U}}, +{SUB_9018,{7U,4U,0U}}, +{SUB_9020,{0U,4U,0U}}, +{SUB_9020,{1U,4U,0U}}, +{SUB_9020,{2U,4U,0U}}, +{SUB_9020,{3U,4U,0U}}, +{SUB_9020,{4U,4U,0U}}, +{SUB_9020,{5U,4U,0U}}, +{SUB_9020,{6U,4U,0U}}, +{SUB_9020,{7U,4U,0U}}, +{SUB_9028,{0U,4U,0U}}, +{SUB_9028,{1U,4U,0U}}, +{SUB_9028,{2U,4U,0U}}, +{SUB_9028,{3U,4U,0U}}, +{SUB_9028,{4U,4U,0U}}, +{SUB_9028,{5U,4U,0U}}, +{SUB_9028,{6U,4U,0U}}, +{SUB_9028,{7U,4U,0U}}, +{SUB_9030,{0U,4U,0U}}, +{SUB_9030,{1U,4U,0U}}, +{SUB_9030,{2U,4U,0U}}, +{SUB_9030,{3U,4U,0U}}, +{SUB_9030,{4U,4U,0U}}, +{SUB_9030,{5U,4U,0U}}, +{SUB_9030,{6U,4U,0U}}, +{SUB_9030,{7U,4U,0U}}, +{SUB_9038,{0U,4U,0U}}, +{SUB_9039,{0U,4U,0U}}, +{SUB_903A,{0U,4U,0U}}, +{SUB_903B,{0U,4U,0U}}, +{SUB_903C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9040,{0U,4U,0U}}, +{SUB_9040,{1U,4U,0U}}, +{SUB_9040,{2U,4U,0U}}, +{SUB_9040,{3U,4U,0U}}, +{SUB_9040,{4U,4U,0U}}, +{SUB_9040,{5U,4U,0U}}, +{SUB_9040,{6U,4U,0U}}, +{SUB_9040,{7U,4U,0U}}, +{SUB_9048,{0U,4U,0U}}, +{SUB_9048,{1U,4U,0U}}, +{SUB_9048,{2U,4U,0U}}, +{SUB_9048,{3U,4U,0U}}, +{SUB_9048,{4U,4U,0U}}, +{SUB_9048,{5U,4U,0U}}, +{SUB_9048,{6U,4U,0U}}, +{SUB_9048,{7U,4U,0U}}, +{SUB_9050,{0U,4U,0U}}, +{SUB_9050,{1U,4U,0U}}, +{SUB_9050,{2U,4U,0U}}, +{SUB_9050,{3U,4U,0U}}, +{SUB_9050,{4U,4U,0U}}, +{SUB_9050,{5U,4U,0U}}, +{SUB_9050,{6U,4U,0U}}, +{SUB_9050,{7U,4U,0U}}, +{SUB_9058,{0U,4U,0U}}, +{SUB_9058,{1U,4U,0U}}, +{SUB_9058,{2U,4U,0U}}, +{SUB_9058,{3U,4U,0U}}, +{SUB_9058,{4U,4U,0U}}, +{SUB_9058,{5U,4U,0U}}, +{SUB_9058,{6U,4U,0U}}, +{SUB_9058,{7U,4U,0U}}, +{SUB_9060,{0U,4U,0U}}, +{SUB_9060,{1U,4U,0U}}, +{SUB_9060,{2U,4U,0U}}, +{SUB_9060,{3U,4U,0U}}, +{SUB_9060,{4U,4U,0U}}, +{SUB_9060,{5U,4U,0U}}, +{SUB_9060,{6U,4U,0U}}, +{SUB_9060,{7U,4U,0U}}, +{SUB_9068,{0U,4U,0U}}, +{SUB_9068,{1U,4U,0U}}, +{SUB_9068,{2U,4U,0U}}, +{SUB_9068,{3U,4U,0U}}, +{SUB_9068,{4U,4U,0U}}, +{SUB_9068,{5U,4U,0U}}, +{SUB_9068,{6U,4U,0U}}, +{SUB_9068,{7U,4U,0U}}, +{SUB_9070,{0U,4U,0U}}, +{SUB_9070,{1U,4U,0U}}, +{SUB_9070,{2U,4U,0U}}, +{SUB_9070,{3U,4U,0U}}, +{SUB_9070,{4U,4U,0U}}, +{SUB_9070,{5U,4U,0U}}, +{SUB_9070,{6U,4U,0U}}, +{SUB_9070,{7U,4U,0U}}, +{SUB_9078,{0U,4U,0U}}, +{SUB_9079,{0U,4U,0U}}, +{SUB_907A,{0U,4U,0U}}, +{SUB_907B,{0U,4U,0U}}, +{SUB_907C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9080,{0U,4U,0U}}, +{SUB_9080,{1U,4U,0U}}, +{SUB_9080,{2U,4U,0U}}, +{SUB_9080,{3U,4U,0U}}, +{SUB_9080,{4U,4U,0U}}, +{SUB_9080,{5U,4U,0U}}, +{SUB_9080,{6U,4U,0U}}, +{SUB_9080,{7U,4U,0U}}, +{SUB_9088,{0U,4U,0U}}, +{SUB_9088,{1U,4U,0U}}, +{SUB_9088,{2U,4U,0U}}, +{SUB_9088,{3U,4U,0U}}, +{SUB_9088,{4U,4U,0U}}, +{SUB_9088,{5U,4U,0U}}, +{SUB_9088,{6U,4U,0U}}, +{SUB_9088,{7U,4U,0U}}, +{SUB_9090,{0U,4U,0U}}, +{SUB_9090,{1U,4U,0U}}, +{SUB_9090,{2U,4U,0U}}, +{SUB_9090,{3U,4U,0U}}, +{SUB_9090,{4U,4U,0U}}, +{SUB_9090,{5U,4U,0U}}, +{SUB_9090,{6U,4U,0U}}, +{SUB_9090,{7U,4U,0U}}, +{SUB_9098,{0U,4U,0U}}, +{SUB_9098,{1U,4U,0U}}, +{SUB_9098,{2U,4U,0U}}, +{SUB_9098,{3U,4U,0U}}, +{SUB_9098,{4U,4U,0U}}, +{SUB_9098,{5U,4U,0U}}, +{SUB_9098,{6U,4U,0U}}, +{SUB_9098,{7U,4U,0U}}, +{SUB_90A0,{0U,4U,0U}}, +{SUB_90A0,{1U,4U,0U}}, +{SUB_90A0,{2U,4U,0U}}, +{SUB_90A0,{3U,4U,0U}}, +{SUB_90A0,{4U,4U,0U}}, +{SUB_90A0,{5U,4U,0U}}, +{SUB_90A0,{6U,4U,0U}}, +{SUB_90A0,{7U,4U,0U}}, +{SUB_90A8,{0U,4U,0U}}, +{SUB_90A8,{1U,4U,0U}}, +{SUB_90A8,{2U,4U,0U}}, +{SUB_90A8,{3U,4U,0U}}, +{SUB_90A8,{4U,4U,0U}}, +{SUB_90A8,{5U,4U,0U}}, +{SUB_90A8,{6U,4U,0U}}, +{SUB_90A8,{7U,4U,0U}}, +{SUB_90B0,{0U,4U,0U}}, +{SUB_90B0,{1U,4U,0U}}, +{SUB_90B0,{2U,4U,0U}}, +{SUB_90B0,{3U,4U,0U}}, +{SUB_90B0,{4U,4U,0U}}, +{SUB_90B0,{5U,4U,0U}}, +{SUB_90B0,{6U,4U,0U}}, +{SUB_90B0,{7U,4U,0U}}, +{SUB_90B8,{0U,4U,0U}}, +{SUB_90B9,{0U,4U,0U}}, +{SUB_90BA,{0U,4U,0U}}, +{SUB_90BB,{0U,4U,0U}}, +{SUB_90BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_90C0,{0U,4U,0U}}, +{SUBA_90C0,{1U,4U,0U}}, +{SUBA_90C0,{2U,4U,0U}}, +{SUBA_90C0,{3U,4U,0U}}, +{SUBA_90C0,{4U,4U,0U}}, +{SUBA_90C0,{5U,4U,0U}}, +{SUBA_90C0,{6U,4U,0U}}, +{SUBA_90C0,{7U,4U,0U}}, +{SUBA_90C8,{0U,4U,0U}}, +{SUBA_90C8,{1U,4U,0U}}, +{SUBA_90C8,{2U,4U,0U}}, +{SUBA_90C8,{3U,4U,0U}}, +{SUBA_90C8,{4U,4U,0U}}, +{SUBA_90C8,{5U,4U,0U}}, +{SUBA_90C8,{6U,4U,0U}}, +{SUBA_90C8,{7U,4U,0U}}, +{SUBA_90D0,{0U,4U,0U}}, +{SUBA_90D0,{1U,4U,0U}}, +{SUBA_90D0,{2U,4U,0U}}, +{SUBA_90D0,{3U,4U,0U}}, +{SUBA_90D0,{4U,4U,0U}}, +{SUBA_90D0,{5U,4U,0U}}, +{SUBA_90D0,{6U,4U,0U}}, +{SUBA_90D0,{7U,4U,0U}}, +{SUBA_90D8,{0U,4U,0U}}, +{SUBA_90D8,{1U,4U,0U}}, +{SUBA_90D8,{2U,4U,0U}}, +{SUBA_90D8,{3U,4U,0U}}, +{SUBA_90D8,{4U,4U,0U}}, +{SUBA_90D8,{5U,4U,0U}}, +{SUBA_90D8,{6U,4U,0U}}, +{SUBA_90D8,{7U,4U,0U}}, +{SUBA_90E0,{0U,4U,0U}}, +{SUBA_90E0,{1U,4U,0U}}, +{SUBA_90E0,{2U,4U,0U}}, +{SUBA_90E0,{3U,4U,0U}}, +{SUBA_90E0,{4U,4U,0U}}, +{SUBA_90E0,{5U,4U,0U}}, +{SUBA_90E0,{6U,4U,0U}}, +{SUBA_90E0,{7U,4U,0U}}, +{SUBA_90E8,{0U,4U,0U}}, +{SUBA_90E8,{1U,4U,0U}}, +{SUBA_90E8,{2U,4U,0U}}, +{SUBA_90E8,{3U,4U,0U}}, +{SUBA_90E8,{4U,4U,0U}}, +{SUBA_90E8,{5U,4U,0U}}, +{SUBA_90E8,{6U,4U,0U}}, +{SUBA_90E8,{7U,4U,0U}}, +{SUBA_90F0,{0U,4U,0U}}, +{SUBA_90F0,{1U,4U,0U}}, +{SUBA_90F0,{2U,4U,0U}}, +{SUBA_90F0,{3U,4U,0U}}, +{SUBA_90F0,{4U,4U,0U}}, +{SUBA_90F0,{5U,4U,0U}}, +{SUBA_90F0,{6U,4U,0U}}, +{SUBA_90F0,{7U,4U,0U}}, +{SUBA_90F8,{0U,4U,0U}}, +{SUBA_90F9,{0U,4U,0U}}, +{SUBA_90FA,{0U,4U,0U}}, +{SUBA_90FB,{0U,4U,0U}}, +{SUBA_90FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9100,{0U,4U,0U}}, +{SUBX_9100,{1U,4U,0U}}, +{SUBX_9100,{2U,4U,0U}}, +{SUBX_9100,{3U,4U,0U}}, +{SUBX_9100,{4U,4U,0U}}, +{SUBX_9100,{5U,4U,0U}}, +{SUBX_9100,{6U,4U,0U}}, +{SUBX_9100,{7U,4U,0U}}, +{SUBX_9108,{0U,4U,0U}}, +{SUBX_9108,{1U,4U,0U}}, +{SUBX_9108,{2U,4U,0U}}, +{SUBX_9108,{3U,4U,0U}}, +{SUBX_9108,{4U,4U,0U}}, +{SUBX_9108,{5U,4U,0U}}, +{SUBX_9108,{6U,4U,0U}}, +{SUBX_9108,{7U,4U,0U}}, +{SUB_9110,{0U,4U,0U}}, +{SUB_9110,{1U,4U,0U}}, +{SUB_9110,{2U,4U,0U}}, +{SUB_9110,{3U,4U,0U}}, +{SUB_9110,{4U,4U,0U}}, +{SUB_9110,{5U,4U,0U}}, +{SUB_9110,{6U,4U,0U}}, +{SUB_9110,{7U,4U,0U}}, +{SUB_9118,{0U,4U,0U}}, +{SUB_9118,{1U,4U,0U}}, +{SUB_9118,{2U,4U,0U}}, +{SUB_9118,{3U,4U,0U}}, +{SUB_9118,{4U,4U,0U}}, +{SUB_9118,{5U,4U,0U}}, +{SUB_9118,{6U,4U,0U}}, +{SUB_9118,{7U,4U,0U}}, +{SUB_9120,{0U,4U,0U}}, +{SUB_9120,{1U,4U,0U}}, +{SUB_9120,{2U,4U,0U}}, +{SUB_9120,{3U,4U,0U}}, +{SUB_9120,{4U,4U,0U}}, +{SUB_9120,{5U,4U,0U}}, +{SUB_9120,{6U,4U,0U}}, +{SUB_9120,{7U,4U,0U}}, +{SUB_9128,{0U,4U,0U}}, +{SUB_9128,{1U,4U,0U}}, +{SUB_9128,{2U,4U,0U}}, +{SUB_9128,{3U,4U,0U}}, +{SUB_9128,{4U,4U,0U}}, +{SUB_9128,{5U,4U,0U}}, +{SUB_9128,{6U,4U,0U}}, +{SUB_9128,{7U,4U,0U}}, +{SUB_9130,{0U,4U,0U}}, +{SUB_9130,{1U,4U,0U}}, +{SUB_9130,{2U,4U,0U}}, +{SUB_9130,{3U,4U,0U}}, +{SUB_9130,{4U,4U,0U}}, +{SUB_9130,{5U,4U,0U}}, +{SUB_9130,{6U,4U,0U}}, +{SUB_9130,{7U,4U,0U}}, +{SUB_9138,{0U,4U,0U}}, +{SUB_9139,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9140,{0U,4U,0U}}, +{SUBX_9140,{1U,4U,0U}}, +{SUBX_9140,{2U,4U,0U}}, +{SUBX_9140,{3U,4U,0U}}, +{SUBX_9140,{4U,4U,0U}}, +{SUBX_9140,{5U,4U,0U}}, +{SUBX_9140,{6U,4U,0U}}, +{SUBX_9140,{7U,4U,0U}}, +{SUBX_9148,{0U,4U,0U}}, +{SUBX_9148,{1U,4U,0U}}, +{SUBX_9148,{2U,4U,0U}}, +{SUBX_9148,{3U,4U,0U}}, +{SUBX_9148,{4U,4U,0U}}, +{SUBX_9148,{5U,4U,0U}}, +{SUBX_9148,{6U,4U,0U}}, +{SUBX_9148,{7U,4U,0U}}, +{SUB_9150,{0U,4U,0U}}, +{SUB_9150,{1U,4U,0U}}, +{SUB_9150,{2U,4U,0U}}, +{SUB_9150,{3U,4U,0U}}, +{SUB_9150,{4U,4U,0U}}, +{SUB_9150,{5U,4U,0U}}, +{SUB_9150,{6U,4U,0U}}, +{SUB_9150,{7U,4U,0U}}, +{SUB_9158,{0U,4U,0U}}, +{SUB_9158,{1U,4U,0U}}, +{SUB_9158,{2U,4U,0U}}, +{SUB_9158,{3U,4U,0U}}, +{SUB_9158,{4U,4U,0U}}, +{SUB_9158,{5U,4U,0U}}, +{SUB_9158,{6U,4U,0U}}, +{SUB_9158,{7U,4U,0U}}, +{SUB_9160,{0U,4U,0U}}, +{SUB_9160,{1U,4U,0U}}, +{SUB_9160,{2U,4U,0U}}, +{SUB_9160,{3U,4U,0U}}, +{SUB_9160,{4U,4U,0U}}, +{SUB_9160,{5U,4U,0U}}, +{SUB_9160,{6U,4U,0U}}, +{SUB_9160,{7U,4U,0U}}, +{SUB_9168,{0U,4U,0U}}, +{SUB_9168,{1U,4U,0U}}, +{SUB_9168,{2U,4U,0U}}, +{SUB_9168,{3U,4U,0U}}, +{SUB_9168,{4U,4U,0U}}, +{SUB_9168,{5U,4U,0U}}, +{SUB_9168,{6U,4U,0U}}, +{SUB_9168,{7U,4U,0U}}, +{SUB_9170,{0U,4U,0U}}, +{SUB_9170,{1U,4U,0U}}, +{SUB_9170,{2U,4U,0U}}, +{SUB_9170,{3U,4U,0U}}, +{SUB_9170,{4U,4U,0U}}, +{SUB_9170,{5U,4U,0U}}, +{SUB_9170,{6U,4U,0U}}, +{SUB_9170,{7U,4U,0U}}, +{SUB_9178,{0U,4U,0U}}, +{SUB_9179,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9180,{0U,4U,0U}}, +{SUBX_9180,{1U,4U,0U}}, +{SUBX_9180,{2U,4U,0U}}, +{SUBX_9180,{3U,4U,0U}}, +{SUBX_9180,{4U,4U,0U}}, +{SUBX_9180,{5U,4U,0U}}, +{SUBX_9180,{6U,4U,0U}}, +{SUBX_9180,{7U,4U,0U}}, +{SUBX_9188,{0U,4U,0U}}, +{SUBX_9188,{1U,4U,0U}}, +{SUBX_9188,{2U,4U,0U}}, +{SUBX_9188,{3U,4U,0U}}, +{SUBX_9188,{4U,4U,0U}}, +{SUBX_9188,{5U,4U,0U}}, +{SUBX_9188,{6U,4U,0U}}, +{SUBX_9188,{7U,4U,0U}}, +{SUB_9190,{0U,4U,0U}}, +{SUB_9190,{1U,4U,0U}}, +{SUB_9190,{2U,4U,0U}}, +{SUB_9190,{3U,4U,0U}}, +{SUB_9190,{4U,4U,0U}}, +{SUB_9190,{5U,4U,0U}}, +{SUB_9190,{6U,4U,0U}}, +{SUB_9190,{7U,4U,0U}}, +{SUB_9198,{0U,4U,0U}}, +{SUB_9198,{1U,4U,0U}}, +{SUB_9198,{2U,4U,0U}}, +{SUB_9198,{3U,4U,0U}}, +{SUB_9198,{4U,4U,0U}}, +{SUB_9198,{5U,4U,0U}}, +{SUB_9198,{6U,4U,0U}}, +{SUB_9198,{7U,4U,0U}}, +{SUB_91A0,{0U,4U,0U}}, +{SUB_91A0,{1U,4U,0U}}, +{SUB_91A0,{2U,4U,0U}}, +{SUB_91A0,{3U,4U,0U}}, +{SUB_91A0,{4U,4U,0U}}, +{SUB_91A0,{5U,4U,0U}}, +{SUB_91A0,{6U,4U,0U}}, +{SUB_91A0,{7U,4U,0U}}, +{SUB_91A8,{0U,4U,0U}}, +{SUB_91A8,{1U,4U,0U}}, +{SUB_91A8,{2U,4U,0U}}, +{SUB_91A8,{3U,4U,0U}}, +{SUB_91A8,{4U,4U,0U}}, +{SUB_91A8,{5U,4U,0U}}, +{SUB_91A8,{6U,4U,0U}}, +{SUB_91A8,{7U,4U,0U}}, +{SUB_91B0,{0U,4U,0U}}, +{SUB_91B0,{1U,4U,0U}}, +{SUB_91B0,{2U,4U,0U}}, +{SUB_91B0,{3U,4U,0U}}, +{SUB_91B0,{4U,4U,0U}}, +{SUB_91B0,{5U,4U,0U}}, +{SUB_91B0,{6U,4U,0U}}, +{SUB_91B0,{7U,4U,0U}}, +{SUB_91B8,{0U,4U,0U}}, +{SUB_91B9,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_91C0,{0U,4U,0U}}, +{SUBA_91C0,{1U,4U,0U}}, +{SUBA_91C0,{2U,4U,0U}}, +{SUBA_91C0,{3U,4U,0U}}, +{SUBA_91C0,{4U,4U,0U}}, +{SUBA_91C0,{5U,4U,0U}}, +{SUBA_91C0,{6U,4U,0U}}, +{SUBA_91C0,{7U,4U,0U}}, +{SUBA_91C8,{0U,4U,0U}}, +{SUBA_91C8,{1U,4U,0U}}, +{SUBA_91C8,{2U,4U,0U}}, +{SUBA_91C8,{3U,4U,0U}}, +{SUBA_91C8,{4U,4U,0U}}, +{SUBA_91C8,{5U,4U,0U}}, +{SUBA_91C8,{6U,4U,0U}}, +{SUBA_91C8,{7U,4U,0U}}, +{SUBA_91D0,{0U,4U,0U}}, +{SUBA_91D0,{1U,4U,0U}}, +{SUBA_91D0,{2U,4U,0U}}, +{SUBA_91D0,{3U,4U,0U}}, +{SUBA_91D0,{4U,4U,0U}}, +{SUBA_91D0,{5U,4U,0U}}, +{SUBA_91D0,{6U,4U,0U}}, +{SUBA_91D0,{7U,4U,0U}}, +{SUBA_91D8,{0U,4U,0U}}, +{SUBA_91D8,{1U,4U,0U}}, +{SUBA_91D8,{2U,4U,0U}}, +{SUBA_91D8,{3U,4U,0U}}, +{SUBA_91D8,{4U,4U,0U}}, +{SUBA_91D8,{5U,4U,0U}}, +{SUBA_91D8,{6U,4U,0U}}, +{SUBA_91D8,{7U,4U,0U}}, +{SUBA_91E0,{0U,4U,0U}}, +{SUBA_91E0,{1U,4U,0U}}, +{SUBA_91E0,{2U,4U,0U}}, +{SUBA_91E0,{3U,4U,0U}}, +{SUBA_91E0,{4U,4U,0U}}, +{SUBA_91E0,{5U,4U,0U}}, +{SUBA_91E0,{6U,4U,0U}}, +{SUBA_91E0,{7U,4U,0U}}, +{SUBA_91E8,{0U,4U,0U}}, +{SUBA_91E8,{1U,4U,0U}}, +{SUBA_91E8,{2U,4U,0U}}, +{SUBA_91E8,{3U,4U,0U}}, +{SUBA_91E8,{4U,4U,0U}}, +{SUBA_91E8,{5U,4U,0U}}, +{SUBA_91E8,{6U,4U,0U}}, +{SUBA_91E8,{7U,4U,0U}}, +{SUBA_91F0,{0U,4U,0U}}, +{SUBA_91F0,{1U,4U,0U}}, +{SUBA_91F0,{2U,4U,0U}}, +{SUBA_91F0,{3U,4U,0U}}, +{SUBA_91F0,{4U,4U,0U}}, +{SUBA_91F0,{5U,4U,0U}}, +{SUBA_91F0,{6U,4U,0U}}, +{SUBA_91F0,{7U,4U,0U}}, +{SUBA_91F8,{0U,4U,0U}}, +{SUBA_91F9,{0U,4U,0U}}, +{SUBA_91FA,{0U,4U,0U}}, +{SUBA_91FB,{0U,4U,0U}}, +{SUBA_91FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9000,{0U,5U,0U}}, +{SUB_9000,{1U,5U,0U}}, +{SUB_9000,{2U,5U,0U}}, +{SUB_9000,{3U,5U,0U}}, +{SUB_9000,{4U,5U,0U}}, +{SUB_9000,{5U,5U,0U}}, +{SUB_9000,{6U,5U,0U}}, +{SUB_9000,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9010,{0U,5U,0U}}, +{SUB_9010,{1U,5U,0U}}, +{SUB_9010,{2U,5U,0U}}, +{SUB_9010,{3U,5U,0U}}, +{SUB_9010,{4U,5U,0U}}, +{SUB_9010,{5U,5U,0U}}, +{SUB_9010,{6U,5U,0U}}, +{SUB_9010,{7U,5U,0U}}, +{SUB_9018,{0U,5U,0U}}, +{SUB_9018,{1U,5U,0U}}, +{SUB_9018,{2U,5U,0U}}, +{SUB_9018,{3U,5U,0U}}, +{SUB_9018,{4U,5U,0U}}, +{SUB_9018,{5U,5U,0U}}, +{SUB_9018,{6U,5U,0U}}, +{SUB_9018,{7U,5U,0U}}, +{SUB_9020,{0U,5U,0U}}, +{SUB_9020,{1U,5U,0U}}, +{SUB_9020,{2U,5U,0U}}, +{SUB_9020,{3U,5U,0U}}, +{SUB_9020,{4U,5U,0U}}, +{SUB_9020,{5U,5U,0U}}, +{SUB_9020,{6U,5U,0U}}, +{SUB_9020,{7U,5U,0U}}, +{SUB_9028,{0U,5U,0U}}, +{SUB_9028,{1U,5U,0U}}, +{SUB_9028,{2U,5U,0U}}, +{SUB_9028,{3U,5U,0U}}, +{SUB_9028,{4U,5U,0U}}, +{SUB_9028,{5U,5U,0U}}, +{SUB_9028,{6U,5U,0U}}, +{SUB_9028,{7U,5U,0U}}, +{SUB_9030,{0U,5U,0U}}, +{SUB_9030,{1U,5U,0U}}, +{SUB_9030,{2U,5U,0U}}, +{SUB_9030,{3U,5U,0U}}, +{SUB_9030,{4U,5U,0U}}, +{SUB_9030,{5U,5U,0U}}, +{SUB_9030,{6U,5U,0U}}, +{SUB_9030,{7U,5U,0U}}, +{SUB_9038,{0U,5U,0U}}, +{SUB_9039,{0U,5U,0U}}, +{SUB_903A,{0U,5U,0U}}, +{SUB_903B,{0U,5U,0U}}, +{SUB_903C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9040,{0U,5U,0U}}, +{SUB_9040,{1U,5U,0U}}, +{SUB_9040,{2U,5U,0U}}, +{SUB_9040,{3U,5U,0U}}, +{SUB_9040,{4U,5U,0U}}, +{SUB_9040,{5U,5U,0U}}, +{SUB_9040,{6U,5U,0U}}, +{SUB_9040,{7U,5U,0U}}, +{SUB_9048,{0U,5U,0U}}, +{SUB_9048,{1U,5U,0U}}, +{SUB_9048,{2U,5U,0U}}, +{SUB_9048,{3U,5U,0U}}, +{SUB_9048,{4U,5U,0U}}, +{SUB_9048,{5U,5U,0U}}, +{SUB_9048,{6U,5U,0U}}, +{SUB_9048,{7U,5U,0U}}, +{SUB_9050,{0U,5U,0U}}, +{SUB_9050,{1U,5U,0U}}, +{SUB_9050,{2U,5U,0U}}, +{SUB_9050,{3U,5U,0U}}, +{SUB_9050,{4U,5U,0U}}, +{SUB_9050,{5U,5U,0U}}, +{SUB_9050,{6U,5U,0U}}, +{SUB_9050,{7U,5U,0U}}, +{SUB_9058,{0U,5U,0U}}, +{SUB_9058,{1U,5U,0U}}, +{SUB_9058,{2U,5U,0U}}, +{SUB_9058,{3U,5U,0U}}, +{SUB_9058,{4U,5U,0U}}, +{SUB_9058,{5U,5U,0U}}, +{SUB_9058,{6U,5U,0U}}, +{SUB_9058,{7U,5U,0U}}, +{SUB_9060,{0U,5U,0U}}, +{SUB_9060,{1U,5U,0U}}, +{SUB_9060,{2U,5U,0U}}, +{SUB_9060,{3U,5U,0U}}, +{SUB_9060,{4U,5U,0U}}, +{SUB_9060,{5U,5U,0U}}, +{SUB_9060,{6U,5U,0U}}, +{SUB_9060,{7U,5U,0U}}, +{SUB_9068,{0U,5U,0U}}, +{SUB_9068,{1U,5U,0U}}, +{SUB_9068,{2U,5U,0U}}, +{SUB_9068,{3U,5U,0U}}, +{SUB_9068,{4U,5U,0U}}, +{SUB_9068,{5U,5U,0U}}, +{SUB_9068,{6U,5U,0U}}, +{SUB_9068,{7U,5U,0U}}, +{SUB_9070,{0U,5U,0U}}, +{SUB_9070,{1U,5U,0U}}, +{SUB_9070,{2U,5U,0U}}, +{SUB_9070,{3U,5U,0U}}, +{SUB_9070,{4U,5U,0U}}, +{SUB_9070,{5U,5U,0U}}, +{SUB_9070,{6U,5U,0U}}, +{SUB_9070,{7U,5U,0U}}, +{SUB_9078,{0U,5U,0U}}, +{SUB_9079,{0U,5U,0U}}, +{SUB_907A,{0U,5U,0U}}, +{SUB_907B,{0U,5U,0U}}, +{SUB_907C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9080,{0U,5U,0U}}, +{SUB_9080,{1U,5U,0U}}, +{SUB_9080,{2U,5U,0U}}, +{SUB_9080,{3U,5U,0U}}, +{SUB_9080,{4U,5U,0U}}, +{SUB_9080,{5U,5U,0U}}, +{SUB_9080,{6U,5U,0U}}, +{SUB_9080,{7U,5U,0U}}, +{SUB_9088,{0U,5U,0U}}, +{SUB_9088,{1U,5U,0U}}, +{SUB_9088,{2U,5U,0U}}, +{SUB_9088,{3U,5U,0U}}, +{SUB_9088,{4U,5U,0U}}, +{SUB_9088,{5U,5U,0U}}, +{SUB_9088,{6U,5U,0U}}, +{SUB_9088,{7U,5U,0U}}, +{SUB_9090,{0U,5U,0U}}, +{SUB_9090,{1U,5U,0U}}, +{SUB_9090,{2U,5U,0U}}, +{SUB_9090,{3U,5U,0U}}, +{SUB_9090,{4U,5U,0U}}, +{SUB_9090,{5U,5U,0U}}, +{SUB_9090,{6U,5U,0U}}, +{SUB_9090,{7U,5U,0U}}, +{SUB_9098,{0U,5U,0U}}, +{SUB_9098,{1U,5U,0U}}, +{SUB_9098,{2U,5U,0U}}, +{SUB_9098,{3U,5U,0U}}, +{SUB_9098,{4U,5U,0U}}, +{SUB_9098,{5U,5U,0U}}, +{SUB_9098,{6U,5U,0U}}, +{SUB_9098,{7U,5U,0U}}, +{SUB_90A0,{0U,5U,0U}}, +{SUB_90A0,{1U,5U,0U}}, +{SUB_90A0,{2U,5U,0U}}, +{SUB_90A0,{3U,5U,0U}}, +{SUB_90A0,{4U,5U,0U}}, +{SUB_90A0,{5U,5U,0U}}, +{SUB_90A0,{6U,5U,0U}}, +{SUB_90A0,{7U,5U,0U}}, +{SUB_90A8,{0U,5U,0U}}, +{SUB_90A8,{1U,5U,0U}}, +{SUB_90A8,{2U,5U,0U}}, +{SUB_90A8,{3U,5U,0U}}, +{SUB_90A8,{4U,5U,0U}}, +{SUB_90A8,{5U,5U,0U}}, +{SUB_90A8,{6U,5U,0U}}, +{SUB_90A8,{7U,5U,0U}}, +{SUB_90B0,{0U,5U,0U}}, +{SUB_90B0,{1U,5U,0U}}, +{SUB_90B0,{2U,5U,0U}}, +{SUB_90B0,{3U,5U,0U}}, +{SUB_90B0,{4U,5U,0U}}, +{SUB_90B0,{5U,5U,0U}}, +{SUB_90B0,{6U,5U,0U}}, +{SUB_90B0,{7U,5U,0U}}, +{SUB_90B8,{0U,5U,0U}}, +{SUB_90B9,{0U,5U,0U}}, +{SUB_90BA,{0U,5U,0U}}, +{SUB_90BB,{0U,5U,0U}}, +{SUB_90BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_90C0,{0U,5U,0U}}, +{SUBA_90C0,{1U,5U,0U}}, +{SUBA_90C0,{2U,5U,0U}}, +{SUBA_90C0,{3U,5U,0U}}, +{SUBA_90C0,{4U,5U,0U}}, +{SUBA_90C0,{5U,5U,0U}}, +{SUBA_90C0,{6U,5U,0U}}, +{SUBA_90C0,{7U,5U,0U}}, +{SUBA_90C8,{0U,5U,0U}}, +{SUBA_90C8,{1U,5U,0U}}, +{SUBA_90C8,{2U,5U,0U}}, +{SUBA_90C8,{3U,5U,0U}}, +{SUBA_90C8,{4U,5U,0U}}, +{SUBA_90C8,{5U,5U,0U}}, +{SUBA_90C8,{6U,5U,0U}}, +{SUBA_90C8,{7U,5U,0U}}, +{SUBA_90D0,{0U,5U,0U}}, +{SUBA_90D0,{1U,5U,0U}}, +{SUBA_90D0,{2U,5U,0U}}, +{SUBA_90D0,{3U,5U,0U}}, +{SUBA_90D0,{4U,5U,0U}}, +{SUBA_90D0,{5U,5U,0U}}, +{SUBA_90D0,{6U,5U,0U}}, +{SUBA_90D0,{7U,5U,0U}}, +{SUBA_90D8,{0U,5U,0U}}, +{SUBA_90D8,{1U,5U,0U}}, +{SUBA_90D8,{2U,5U,0U}}, +{SUBA_90D8,{3U,5U,0U}}, +{SUBA_90D8,{4U,5U,0U}}, +{SUBA_90D8,{5U,5U,0U}}, +{SUBA_90D8,{6U,5U,0U}}, +{SUBA_90D8,{7U,5U,0U}}, +{SUBA_90E0,{0U,5U,0U}}, +{SUBA_90E0,{1U,5U,0U}}, +{SUBA_90E0,{2U,5U,0U}}, +{SUBA_90E0,{3U,5U,0U}}, +{SUBA_90E0,{4U,5U,0U}}, +{SUBA_90E0,{5U,5U,0U}}, +{SUBA_90E0,{6U,5U,0U}}, +{SUBA_90E0,{7U,5U,0U}}, +{SUBA_90E8,{0U,5U,0U}}, +{SUBA_90E8,{1U,5U,0U}}, +{SUBA_90E8,{2U,5U,0U}}, +{SUBA_90E8,{3U,5U,0U}}, +{SUBA_90E8,{4U,5U,0U}}, +{SUBA_90E8,{5U,5U,0U}}, +{SUBA_90E8,{6U,5U,0U}}, +{SUBA_90E8,{7U,5U,0U}}, +{SUBA_90F0,{0U,5U,0U}}, +{SUBA_90F0,{1U,5U,0U}}, +{SUBA_90F0,{2U,5U,0U}}, +{SUBA_90F0,{3U,5U,0U}}, +{SUBA_90F0,{4U,5U,0U}}, +{SUBA_90F0,{5U,5U,0U}}, +{SUBA_90F0,{6U,5U,0U}}, +{SUBA_90F0,{7U,5U,0U}}, +{SUBA_90F8,{0U,5U,0U}}, +{SUBA_90F9,{0U,5U,0U}}, +{SUBA_90FA,{0U,5U,0U}}, +{SUBA_90FB,{0U,5U,0U}}, +{SUBA_90FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9100,{0U,5U,0U}}, +{SUBX_9100,{1U,5U,0U}}, +{SUBX_9100,{2U,5U,0U}}, +{SUBX_9100,{3U,5U,0U}}, +{SUBX_9100,{4U,5U,0U}}, +{SUBX_9100,{5U,5U,0U}}, +{SUBX_9100,{6U,5U,0U}}, +{SUBX_9100,{7U,5U,0U}}, +{SUBX_9108,{0U,5U,0U}}, +{SUBX_9108,{1U,5U,0U}}, +{SUBX_9108,{2U,5U,0U}}, +{SUBX_9108,{3U,5U,0U}}, +{SUBX_9108,{4U,5U,0U}}, +{SUBX_9108,{5U,5U,0U}}, +{SUBX_9108,{6U,5U,0U}}, +{SUBX_9108,{7U,5U,0U}}, +{SUB_9110,{0U,5U,0U}}, +{SUB_9110,{1U,5U,0U}}, +{SUB_9110,{2U,5U,0U}}, +{SUB_9110,{3U,5U,0U}}, +{SUB_9110,{4U,5U,0U}}, +{SUB_9110,{5U,5U,0U}}, +{SUB_9110,{6U,5U,0U}}, +{SUB_9110,{7U,5U,0U}}, +{SUB_9118,{0U,5U,0U}}, +{SUB_9118,{1U,5U,0U}}, +{SUB_9118,{2U,5U,0U}}, +{SUB_9118,{3U,5U,0U}}, +{SUB_9118,{4U,5U,0U}}, +{SUB_9118,{5U,5U,0U}}, +{SUB_9118,{6U,5U,0U}}, +{SUB_9118,{7U,5U,0U}}, +{SUB_9120,{0U,5U,0U}}, +{SUB_9120,{1U,5U,0U}}, +{SUB_9120,{2U,5U,0U}}, +{SUB_9120,{3U,5U,0U}}, +{SUB_9120,{4U,5U,0U}}, +{SUB_9120,{5U,5U,0U}}, +{SUB_9120,{6U,5U,0U}}, +{SUB_9120,{7U,5U,0U}}, +{SUB_9128,{0U,5U,0U}}, +{SUB_9128,{1U,5U,0U}}, +{SUB_9128,{2U,5U,0U}}, +{SUB_9128,{3U,5U,0U}}, +{SUB_9128,{4U,5U,0U}}, +{SUB_9128,{5U,5U,0U}}, +{SUB_9128,{6U,5U,0U}}, +{SUB_9128,{7U,5U,0U}}, +{SUB_9130,{0U,5U,0U}}, +{SUB_9130,{1U,5U,0U}}, +{SUB_9130,{2U,5U,0U}}, +{SUB_9130,{3U,5U,0U}}, +{SUB_9130,{4U,5U,0U}}, +{SUB_9130,{5U,5U,0U}}, +{SUB_9130,{6U,5U,0U}}, +{SUB_9130,{7U,5U,0U}}, +{SUB_9138,{0U,5U,0U}}, +{SUB_9139,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9140,{0U,5U,0U}}, +{SUBX_9140,{1U,5U,0U}}, +{SUBX_9140,{2U,5U,0U}}, +{SUBX_9140,{3U,5U,0U}}, +{SUBX_9140,{4U,5U,0U}}, +{SUBX_9140,{5U,5U,0U}}, +{SUBX_9140,{6U,5U,0U}}, +{SUBX_9140,{7U,5U,0U}}, +{SUBX_9148,{0U,5U,0U}}, +{SUBX_9148,{1U,5U,0U}}, +{SUBX_9148,{2U,5U,0U}}, +{SUBX_9148,{3U,5U,0U}}, +{SUBX_9148,{4U,5U,0U}}, +{SUBX_9148,{5U,5U,0U}}, +{SUBX_9148,{6U,5U,0U}}, +{SUBX_9148,{7U,5U,0U}}, +{SUB_9150,{0U,5U,0U}}, +{SUB_9150,{1U,5U,0U}}, +{SUB_9150,{2U,5U,0U}}, +{SUB_9150,{3U,5U,0U}}, +{SUB_9150,{4U,5U,0U}}, +{SUB_9150,{5U,5U,0U}}, +{SUB_9150,{6U,5U,0U}}, +{SUB_9150,{7U,5U,0U}}, +{SUB_9158,{0U,5U,0U}}, +{SUB_9158,{1U,5U,0U}}, +{SUB_9158,{2U,5U,0U}}, +{SUB_9158,{3U,5U,0U}}, +{SUB_9158,{4U,5U,0U}}, +{SUB_9158,{5U,5U,0U}}, +{SUB_9158,{6U,5U,0U}}, +{SUB_9158,{7U,5U,0U}}, +{SUB_9160,{0U,5U,0U}}, +{SUB_9160,{1U,5U,0U}}, +{SUB_9160,{2U,5U,0U}}, +{SUB_9160,{3U,5U,0U}}, +{SUB_9160,{4U,5U,0U}}, +{SUB_9160,{5U,5U,0U}}, +{SUB_9160,{6U,5U,0U}}, +{SUB_9160,{7U,5U,0U}}, +{SUB_9168,{0U,5U,0U}}, +{SUB_9168,{1U,5U,0U}}, +{SUB_9168,{2U,5U,0U}}, +{SUB_9168,{3U,5U,0U}}, +{SUB_9168,{4U,5U,0U}}, +{SUB_9168,{5U,5U,0U}}, +{SUB_9168,{6U,5U,0U}}, +{SUB_9168,{7U,5U,0U}}, +{SUB_9170,{0U,5U,0U}}, +{SUB_9170,{1U,5U,0U}}, +{SUB_9170,{2U,5U,0U}}, +{SUB_9170,{3U,5U,0U}}, +{SUB_9170,{4U,5U,0U}}, +{SUB_9170,{5U,5U,0U}}, +{SUB_9170,{6U,5U,0U}}, +{SUB_9170,{7U,5U,0U}}, +{SUB_9178,{0U,5U,0U}}, +{SUB_9179,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9180,{0U,5U,0U}}, +{SUBX_9180,{1U,5U,0U}}, +{SUBX_9180,{2U,5U,0U}}, +{SUBX_9180,{3U,5U,0U}}, +{SUBX_9180,{4U,5U,0U}}, +{SUBX_9180,{5U,5U,0U}}, +{SUBX_9180,{6U,5U,0U}}, +{SUBX_9180,{7U,5U,0U}}, +{SUBX_9188,{0U,5U,0U}}, +{SUBX_9188,{1U,5U,0U}}, +{SUBX_9188,{2U,5U,0U}}, +{SUBX_9188,{3U,5U,0U}}, +{SUBX_9188,{4U,5U,0U}}, +{SUBX_9188,{5U,5U,0U}}, +{SUBX_9188,{6U,5U,0U}}, +{SUBX_9188,{7U,5U,0U}}, +{SUB_9190,{0U,5U,0U}}, +{SUB_9190,{1U,5U,0U}}, +{SUB_9190,{2U,5U,0U}}, +{SUB_9190,{3U,5U,0U}}, +{SUB_9190,{4U,5U,0U}}, +{SUB_9190,{5U,5U,0U}}, +{SUB_9190,{6U,5U,0U}}, +{SUB_9190,{7U,5U,0U}}, +{SUB_9198,{0U,5U,0U}}, +{SUB_9198,{1U,5U,0U}}, +{SUB_9198,{2U,5U,0U}}, +{SUB_9198,{3U,5U,0U}}, +{SUB_9198,{4U,5U,0U}}, +{SUB_9198,{5U,5U,0U}}, +{SUB_9198,{6U,5U,0U}}, +{SUB_9198,{7U,5U,0U}}, +{SUB_91A0,{0U,5U,0U}}, +{SUB_91A0,{1U,5U,0U}}, +{SUB_91A0,{2U,5U,0U}}, +{SUB_91A0,{3U,5U,0U}}, +{SUB_91A0,{4U,5U,0U}}, +{SUB_91A0,{5U,5U,0U}}, +{SUB_91A0,{6U,5U,0U}}, +{SUB_91A0,{7U,5U,0U}}, +{SUB_91A8,{0U,5U,0U}}, +{SUB_91A8,{1U,5U,0U}}, +{SUB_91A8,{2U,5U,0U}}, +{SUB_91A8,{3U,5U,0U}}, +{SUB_91A8,{4U,5U,0U}}, +{SUB_91A8,{5U,5U,0U}}, +{SUB_91A8,{6U,5U,0U}}, +{SUB_91A8,{7U,5U,0U}}, +{SUB_91B0,{0U,5U,0U}}, +{SUB_91B0,{1U,5U,0U}}, +{SUB_91B0,{2U,5U,0U}}, +{SUB_91B0,{3U,5U,0U}}, +{SUB_91B0,{4U,5U,0U}}, +{SUB_91B0,{5U,5U,0U}}, +{SUB_91B0,{6U,5U,0U}}, +{SUB_91B0,{7U,5U,0U}}, +{SUB_91B8,{0U,5U,0U}}, +{SUB_91B9,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_91C0,{0U,5U,0U}}, +{SUBA_91C0,{1U,5U,0U}}, +{SUBA_91C0,{2U,5U,0U}}, +{SUBA_91C0,{3U,5U,0U}}, +{SUBA_91C0,{4U,5U,0U}}, +{SUBA_91C0,{5U,5U,0U}}, +{SUBA_91C0,{6U,5U,0U}}, +{SUBA_91C0,{7U,5U,0U}}, +{SUBA_91C8,{0U,5U,0U}}, +{SUBA_91C8,{1U,5U,0U}}, +{SUBA_91C8,{2U,5U,0U}}, +{SUBA_91C8,{3U,5U,0U}}, +{SUBA_91C8,{4U,5U,0U}}, +{SUBA_91C8,{5U,5U,0U}}, +{SUBA_91C8,{6U,5U,0U}}, +{SUBA_91C8,{7U,5U,0U}}, +{SUBA_91D0,{0U,5U,0U}}, +{SUBA_91D0,{1U,5U,0U}}, +{SUBA_91D0,{2U,5U,0U}}, +{SUBA_91D0,{3U,5U,0U}}, +{SUBA_91D0,{4U,5U,0U}}, +{SUBA_91D0,{5U,5U,0U}}, +{SUBA_91D0,{6U,5U,0U}}, +{SUBA_91D0,{7U,5U,0U}}, +{SUBA_91D8,{0U,5U,0U}}, +{SUBA_91D8,{1U,5U,0U}}, +{SUBA_91D8,{2U,5U,0U}}, +{SUBA_91D8,{3U,5U,0U}}, +{SUBA_91D8,{4U,5U,0U}}, +{SUBA_91D8,{5U,5U,0U}}, +{SUBA_91D8,{6U,5U,0U}}, +{SUBA_91D8,{7U,5U,0U}}, +{SUBA_91E0,{0U,5U,0U}}, +{SUBA_91E0,{1U,5U,0U}}, +{SUBA_91E0,{2U,5U,0U}}, +{SUBA_91E0,{3U,5U,0U}}, +{SUBA_91E0,{4U,5U,0U}}, +{SUBA_91E0,{5U,5U,0U}}, +{SUBA_91E0,{6U,5U,0U}}, +{SUBA_91E0,{7U,5U,0U}}, +{SUBA_91E8,{0U,5U,0U}}, +{SUBA_91E8,{1U,5U,0U}}, +{SUBA_91E8,{2U,5U,0U}}, +{SUBA_91E8,{3U,5U,0U}}, +{SUBA_91E8,{4U,5U,0U}}, +{SUBA_91E8,{5U,5U,0U}}, +{SUBA_91E8,{6U,5U,0U}}, +{SUBA_91E8,{7U,5U,0U}}, +{SUBA_91F0,{0U,5U,0U}}, +{SUBA_91F0,{1U,5U,0U}}, +{SUBA_91F0,{2U,5U,0U}}, +{SUBA_91F0,{3U,5U,0U}}, +{SUBA_91F0,{4U,5U,0U}}, +{SUBA_91F0,{5U,5U,0U}}, +{SUBA_91F0,{6U,5U,0U}}, +{SUBA_91F0,{7U,5U,0U}}, +{SUBA_91F8,{0U,5U,0U}}, +{SUBA_91F9,{0U,5U,0U}}, +{SUBA_91FA,{0U,5U,0U}}, +{SUBA_91FB,{0U,5U,0U}}, +{SUBA_91FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9000,{0U,6U,0U}}, +{SUB_9000,{1U,6U,0U}}, +{SUB_9000,{2U,6U,0U}}, +{SUB_9000,{3U,6U,0U}}, +{SUB_9000,{4U,6U,0U}}, +{SUB_9000,{5U,6U,0U}}, +{SUB_9000,{6U,6U,0U}}, +{SUB_9000,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9010,{0U,6U,0U}}, +{SUB_9010,{1U,6U,0U}}, +{SUB_9010,{2U,6U,0U}}, +{SUB_9010,{3U,6U,0U}}, +{SUB_9010,{4U,6U,0U}}, +{SUB_9010,{5U,6U,0U}}, +{SUB_9010,{6U,6U,0U}}, +{SUB_9010,{7U,6U,0U}}, +{SUB_9018,{0U,6U,0U}}, +{SUB_9018,{1U,6U,0U}}, +{SUB_9018,{2U,6U,0U}}, +{SUB_9018,{3U,6U,0U}}, +{SUB_9018,{4U,6U,0U}}, +{SUB_9018,{5U,6U,0U}}, +{SUB_9018,{6U,6U,0U}}, +{SUB_9018,{7U,6U,0U}}, +{SUB_9020,{0U,6U,0U}}, +{SUB_9020,{1U,6U,0U}}, +{SUB_9020,{2U,6U,0U}}, +{SUB_9020,{3U,6U,0U}}, +{SUB_9020,{4U,6U,0U}}, +{SUB_9020,{5U,6U,0U}}, +{SUB_9020,{6U,6U,0U}}, +{SUB_9020,{7U,6U,0U}}, +{SUB_9028,{0U,6U,0U}}, +{SUB_9028,{1U,6U,0U}}, +{SUB_9028,{2U,6U,0U}}, +{SUB_9028,{3U,6U,0U}}, +{SUB_9028,{4U,6U,0U}}, +{SUB_9028,{5U,6U,0U}}, +{SUB_9028,{6U,6U,0U}}, +{SUB_9028,{7U,6U,0U}}, +{SUB_9030,{0U,6U,0U}}, +{SUB_9030,{1U,6U,0U}}, +{SUB_9030,{2U,6U,0U}}, +{SUB_9030,{3U,6U,0U}}, +{SUB_9030,{4U,6U,0U}}, +{SUB_9030,{5U,6U,0U}}, +{SUB_9030,{6U,6U,0U}}, +{SUB_9030,{7U,6U,0U}}, +{SUB_9038,{0U,6U,0U}}, +{SUB_9039,{0U,6U,0U}}, +{SUB_903A,{0U,6U,0U}}, +{SUB_903B,{0U,6U,0U}}, +{SUB_903C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9040,{0U,6U,0U}}, +{SUB_9040,{1U,6U,0U}}, +{SUB_9040,{2U,6U,0U}}, +{SUB_9040,{3U,6U,0U}}, +{SUB_9040,{4U,6U,0U}}, +{SUB_9040,{5U,6U,0U}}, +{SUB_9040,{6U,6U,0U}}, +{SUB_9040,{7U,6U,0U}}, +{SUB_9048,{0U,6U,0U}}, +{SUB_9048,{1U,6U,0U}}, +{SUB_9048,{2U,6U,0U}}, +{SUB_9048,{3U,6U,0U}}, +{SUB_9048,{4U,6U,0U}}, +{SUB_9048,{5U,6U,0U}}, +{SUB_9048,{6U,6U,0U}}, +{SUB_9048,{7U,6U,0U}}, +{SUB_9050,{0U,6U,0U}}, +{SUB_9050,{1U,6U,0U}}, +{SUB_9050,{2U,6U,0U}}, +{SUB_9050,{3U,6U,0U}}, +{SUB_9050,{4U,6U,0U}}, +{SUB_9050,{5U,6U,0U}}, +{SUB_9050,{6U,6U,0U}}, +{SUB_9050,{7U,6U,0U}}, +{SUB_9058,{0U,6U,0U}}, +{SUB_9058,{1U,6U,0U}}, +{SUB_9058,{2U,6U,0U}}, +{SUB_9058,{3U,6U,0U}}, +{SUB_9058,{4U,6U,0U}}, +{SUB_9058,{5U,6U,0U}}, +{SUB_9058,{6U,6U,0U}}, +{SUB_9058,{7U,6U,0U}}, +{SUB_9060,{0U,6U,0U}}, +{SUB_9060,{1U,6U,0U}}, +{SUB_9060,{2U,6U,0U}}, +{SUB_9060,{3U,6U,0U}}, +{SUB_9060,{4U,6U,0U}}, +{SUB_9060,{5U,6U,0U}}, +{SUB_9060,{6U,6U,0U}}, +{SUB_9060,{7U,6U,0U}}, +{SUB_9068,{0U,6U,0U}}, +{SUB_9068,{1U,6U,0U}}, +{SUB_9068,{2U,6U,0U}}, +{SUB_9068,{3U,6U,0U}}, +{SUB_9068,{4U,6U,0U}}, +{SUB_9068,{5U,6U,0U}}, +{SUB_9068,{6U,6U,0U}}, +{SUB_9068,{7U,6U,0U}}, +{SUB_9070,{0U,6U,0U}}, +{SUB_9070,{1U,6U,0U}}, +{SUB_9070,{2U,6U,0U}}, +{SUB_9070,{3U,6U,0U}}, +{SUB_9070,{4U,6U,0U}}, +{SUB_9070,{5U,6U,0U}}, +{SUB_9070,{6U,6U,0U}}, +{SUB_9070,{7U,6U,0U}}, +{SUB_9078,{0U,6U,0U}}, +{SUB_9079,{0U,6U,0U}}, +{SUB_907A,{0U,6U,0U}}, +{SUB_907B,{0U,6U,0U}}, +{SUB_907C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9080,{0U,6U,0U}}, +{SUB_9080,{1U,6U,0U}}, +{SUB_9080,{2U,6U,0U}}, +{SUB_9080,{3U,6U,0U}}, +{SUB_9080,{4U,6U,0U}}, +{SUB_9080,{5U,6U,0U}}, +{SUB_9080,{6U,6U,0U}}, +{SUB_9080,{7U,6U,0U}}, +{SUB_9088,{0U,6U,0U}}, +{SUB_9088,{1U,6U,0U}}, +{SUB_9088,{2U,6U,0U}}, +{SUB_9088,{3U,6U,0U}}, +{SUB_9088,{4U,6U,0U}}, +{SUB_9088,{5U,6U,0U}}, +{SUB_9088,{6U,6U,0U}}, +{SUB_9088,{7U,6U,0U}}, +{SUB_9090,{0U,6U,0U}}, +{SUB_9090,{1U,6U,0U}}, +{SUB_9090,{2U,6U,0U}}, +{SUB_9090,{3U,6U,0U}}, +{SUB_9090,{4U,6U,0U}}, +{SUB_9090,{5U,6U,0U}}, +{SUB_9090,{6U,6U,0U}}, +{SUB_9090,{7U,6U,0U}}, +{SUB_9098,{0U,6U,0U}}, +{SUB_9098,{1U,6U,0U}}, +{SUB_9098,{2U,6U,0U}}, +{SUB_9098,{3U,6U,0U}}, +{SUB_9098,{4U,6U,0U}}, +{SUB_9098,{5U,6U,0U}}, +{SUB_9098,{6U,6U,0U}}, +{SUB_9098,{7U,6U,0U}}, +{SUB_90A0,{0U,6U,0U}}, +{SUB_90A0,{1U,6U,0U}}, +{SUB_90A0,{2U,6U,0U}}, +{SUB_90A0,{3U,6U,0U}}, +{SUB_90A0,{4U,6U,0U}}, +{SUB_90A0,{5U,6U,0U}}, +{SUB_90A0,{6U,6U,0U}}, +{SUB_90A0,{7U,6U,0U}}, +{SUB_90A8,{0U,6U,0U}}, +{SUB_90A8,{1U,6U,0U}}, +{SUB_90A8,{2U,6U,0U}}, +{SUB_90A8,{3U,6U,0U}}, +{SUB_90A8,{4U,6U,0U}}, +{SUB_90A8,{5U,6U,0U}}, +{SUB_90A8,{6U,6U,0U}}, +{SUB_90A8,{7U,6U,0U}}, +{SUB_90B0,{0U,6U,0U}}, +{SUB_90B0,{1U,6U,0U}}, +{SUB_90B0,{2U,6U,0U}}, +{SUB_90B0,{3U,6U,0U}}, +{SUB_90B0,{4U,6U,0U}}, +{SUB_90B0,{5U,6U,0U}}, +{SUB_90B0,{6U,6U,0U}}, +{SUB_90B0,{7U,6U,0U}}, +{SUB_90B8,{0U,6U,0U}}, +{SUB_90B9,{0U,6U,0U}}, +{SUB_90BA,{0U,6U,0U}}, +{SUB_90BB,{0U,6U,0U}}, +{SUB_90BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_90C0,{0U,6U,0U}}, +{SUBA_90C0,{1U,6U,0U}}, +{SUBA_90C0,{2U,6U,0U}}, +{SUBA_90C0,{3U,6U,0U}}, +{SUBA_90C0,{4U,6U,0U}}, +{SUBA_90C0,{5U,6U,0U}}, +{SUBA_90C0,{6U,6U,0U}}, +{SUBA_90C0,{7U,6U,0U}}, +{SUBA_90C8,{0U,6U,0U}}, +{SUBA_90C8,{1U,6U,0U}}, +{SUBA_90C8,{2U,6U,0U}}, +{SUBA_90C8,{3U,6U,0U}}, +{SUBA_90C8,{4U,6U,0U}}, +{SUBA_90C8,{5U,6U,0U}}, +{SUBA_90C8,{6U,6U,0U}}, +{SUBA_90C8,{7U,6U,0U}}, +{SUBA_90D0,{0U,6U,0U}}, +{SUBA_90D0,{1U,6U,0U}}, +{SUBA_90D0,{2U,6U,0U}}, +{SUBA_90D0,{3U,6U,0U}}, +{SUBA_90D0,{4U,6U,0U}}, +{SUBA_90D0,{5U,6U,0U}}, +{SUBA_90D0,{6U,6U,0U}}, +{SUBA_90D0,{7U,6U,0U}}, +{SUBA_90D8,{0U,6U,0U}}, +{SUBA_90D8,{1U,6U,0U}}, +{SUBA_90D8,{2U,6U,0U}}, +{SUBA_90D8,{3U,6U,0U}}, +{SUBA_90D8,{4U,6U,0U}}, +{SUBA_90D8,{5U,6U,0U}}, +{SUBA_90D8,{6U,6U,0U}}, +{SUBA_90D8,{7U,6U,0U}}, +{SUBA_90E0,{0U,6U,0U}}, +{SUBA_90E0,{1U,6U,0U}}, +{SUBA_90E0,{2U,6U,0U}}, +{SUBA_90E0,{3U,6U,0U}}, +{SUBA_90E0,{4U,6U,0U}}, +{SUBA_90E0,{5U,6U,0U}}, +{SUBA_90E0,{6U,6U,0U}}, +{SUBA_90E0,{7U,6U,0U}}, +{SUBA_90E8,{0U,6U,0U}}, +{SUBA_90E8,{1U,6U,0U}}, +{SUBA_90E8,{2U,6U,0U}}, +{SUBA_90E8,{3U,6U,0U}}, +{SUBA_90E8,{4U,6U,0U}}, +{SUBA_90E8,{5U,6U,0U}}, +{SUBA_90E8,{6U,6U,0U}}, +{SUBA_90E8,{7U,6U,0U}}, +{SUBA_90F0,{0U,6U,0U}}, +{SUBA_90F0,{1U,6U,0U}}, +{SUBA_90F0,{2U,6U,0U}}, +{SUBA_90F0,{3U,6U,0U}}, +{SUBA_90F0,{4U,6U,0U}}, +{SUBA_90F0,{5U,6U,0U}}, +{SUBA_90F0,{6U,6U,0U}}, +{SUBA_90F0,{7U,6U,0U}}, +{SUBA_90F8,{0U,6U,0U}}, +{SUBA_90F9,{0U,6U,0U}}, +{SUBA_90FA,{0U,6U,0U}}, +{SUBA_90FB,{0U,6U,0U}}, +{SUBA_90FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9100,{0U,6U,0U}}, +{SUBX_9100,{1U,6U,0U}}, +{SUBX_9100,{2U,6U,0U}}, +{SUBX_9100,{3U,6U,0U}}, +{SUBX_9100,{4U,6U,0U}}, +{SUBX_9100,{5U,6U,0U}}, +{SUBX_9100,{6U,6U,0U}}, +{SUBX_9100,{7U,6U,0U}}, +{SUBX_9108,{0U,6U,0U}}, +{SUBX_9108,{1U,6U,0U}}, +{SUBX_9108,{2U,6U,0U}}, +{SUBX_9108,{3U,6U,0U}}, +{SUBX_9108,{4U,6U,0U}}, +{SUBX_9108,{5U,6U,0U}}, +{SUBX_9108,{6U,6U,0U}}, +{SUBX_9108,{7U,6U,0U}}, +{SUB_9110,{0U,6U,0U}}, +{SUB_9110,{1U,6U,0U}}, +{SUB_9110,{2U,6U,0U}}, +{SUB_9110,{3U,6U,0U}}, +{SUB_9110,{4U,6U,0U}}, +{SUB_9110,{5U,6U,0U}}, +{SUB_9110,{6U,6U,0U}}, +{SUB_9110,{7U,6U,0U}}, +{SUB_9118,{0U,6U,0U}}, +{SUB_9118,{1U,6U,0U}}, +{SUB_9118,{2U,6U,0U}}, +{SUB_9118,{3U,6U,0U}}, +{SUB_9118,{4U,6U,0U}}, +{SUB_9118,{5U,6U,0U}}, +{SUB_9118,{6U,6U,0U}}, +{SUB_9118,{7U,6U,0U}}, +{SUB_9120,{0U,6U,0U}}, +{SUB_9120,{1U,6U,0U}}, +{SUB_9120,{2U,6U,0U}}, +{SUB_9120,{3U,6U,0U}}, +{SUB_9120,{4U,6U,0U}}, +{SUB_9120,{5U,6U,0U}}, +{SUB_9120,{6U,6U,0U}}, +{SUB_9120,{7U,6U,0U}}, +{SUB_9128,{0U,6U,0U}}, +{SUB_9128,{1U,6U,0U}}, +{SUB_9128,{2U,6U,0U}}, +{SUB_9128,{3U,6U,0U}}, +{SUB_9128,{4U,6U,0U}}, +{SUB_9128,{5U,6U,0U}}, +{SUB_9128,{6U,6U,0U}}, +{SUB_9128,{7U,6U,0U}}, +{SUB_9130,{0U,6U,0U}}, +{SUB_9130,{1U,6U,0U}}, +{SUB_9130,{2U,6U,0U}}, +{SUB_9130,{3U,6U,0U}}, +{SUB_9130,{4U,6U,0U}}, +{SUB_9130,{5U,6U,0U}}, +{SUB_9130,{6U,6U,0U}}, +{SUB_9130,{7U,6U,0U}}, +{SUB_9138,{0U,6U,0U}}, +{SUB_9139,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9140,{0U,6U,0U}}, +{SUBX_9140,{1U,6U,0U}}, +{SUBX_9140,{2U,6U,0U}}, +{SUBX_9140,{3U,6U,0U}}, +{SUBX_9140,{4U,6U,0U}}, +{SUBX_9140,{5U,6U,0U}}, +{SUBX_9140,{6U,6U,0U}}, +{SUBX_9140,{7U,6U,0U}}, +{SUBX_9148,{0U,6U,0U}}, +{SUBX_9148,{1U,6U,0U}}, +{SUBX_9148,{2U,6U,0U}}, +{SUBX_9148,{3U,6U,0U}}, +{SUBX_9148,{4U,6U,0U}}, +{SUBX_9148,{5U,6U,0U}}, +{SUBX_9148,{6U,6U,0U}}, +{SUBX_9148,{7U,6U,0U}}, +{SUB_9150,{0U,6U,0U}}, +{SUB_9150,{1U,6U,0U}}, +{SUB_9150,{2U,6U,0U}}, +{SUB_9150,{3U,6U,0U}}, +{SUB_9150,{4U,6U,0U}}, +{SUB_9150,{5U,6U,0U}}, +{SUB_9150,{6U,6U,0U}}, +{SUB_9150,{7U,6U,0U}}, +{SUB_9158,{0U,6U,0U}}, +{SUB_9158,{1U,6U,0U}}, +{SUB_9158,{2U,6U,0U}}, +{SUB_9158,{3U,6U,0U}}, +{SUB_9158,{4U,6U,0U}}, +{SUB_9158,{5U,6U,0U}}, +{SUB_9158,{6U,6U,0U}}, +{SUB_9158,{7U,6U,0U}}, +{SUB_9160,{0U,6U,0U}}, +{SUB_9160,{1U,6U,0U}}, +{SUB_9160,{2U,6U,0U}}, +{SUB_9160,{3U,6U,0U}}, +{SUB_9160,{4U,6U,0U}}, +{SUB_9160,{5U,6U,0U}}, +{SUB_9160,{6U,6U,0U}}, +{SUB_9160,{7U,6U,0U}}, +{SUB_9168,{0U,6U,0U}}, +{SUB_9168,{1U,6U,0U}}, +{SUB_9168,{2U,6U,0U}}, +{SUB_9168,{3U,6U,0U}}, +{SUB_9168,{4U,6U,0U}}, +{SUB_9168,{5U,6U,0U}}, +{SUB_9168,{6U,6U,0U}}, +{SUB_9168,{7U,6U,0U}}, +{SUB_9170,{0U,6U,0U}}, +{SUB_9170,{1U,6U,0U}}, +{SUB_9170,{2U,6U,0U}}, +{SUB_9170,{3U,6U,0U}}, +{SUB_9170,{4U,6U,0U}}, +{SUB_9170,{5U,6U,0U}}, +{SUB_9170,{6U,6U,0U}}, +{SUB_9170,{7U,6U,0U}}, +{SUB_9178,{0U,6U,0U}}, +{SUB_9179,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9180,{0U,6U,0U}}, +{SUBX_9180,{1U,6U,0U}}, +{SUBX_9180,{2U,6U,0U}}, +{SUBX_9180,{3U,6U,0U}}, +{SUBX_9180,{4U,6U,0U}}, +{SUBX_9180,{5U,6U,0U}}, +{SUBX_9180,{6U,6U,0U}}, +{SUBX_9180,{7U,6U,0U}}, +{SUBX_9188,{0U,6U,0U}}, +{SUBX_9188,{1U,6U,0U}}, +{SUBX_9188,{2U,6U,0U}}, +{SUBX_9188,{3U,6U,0U}}, +{SUBX_9188,{4U,6U,0U}}, +{SUBX_9188,{5U,6U,0U}}, +{SUBX_9188,{6U,6U,0U}}, +{SUBX_9188,{7U,6U,0U}}, +{SUB_9190,{0U,6U,0U}}, +{SUB_9190,{1U,6U,0U}}, +{SUB_9190,{2U,6U,0U}}, +{SUB_9190,{3U,6U,0U}}, +{SUB_9190,{4U,6U,0U}}, +{SUB_9190,{5U,6U,0U}}, +{SUB_9190,{6U,6U,0U}}, +{SUB_9190,{7U,6U,0U}}, +{SUB_9198,{0U,6U,0U}}, +{SUB_9198,{1U,6U,0U}}, +{SUB_9198,{2U,6U,0U}}, +{SUB_9198,{3U,6U,0U}}, +{SUB_9198,{4U,6U,0U}}, +{SUB_9198,{5U,6U,0U}}, +{SUB_9198,{6U,6U,0U}}, +{SUB_9198,{7U,6U,0U}}, +{SUB_91A0,{0U,6U,0U}}, +{SUB_91A0,{1U,6U,0U}}, +{SUB_91A0,{2U,6U,0U}}, +{SUB_91A0,{3U,6U,0U}}, +{SUB_91A0,{4U,6U,0U}}, +{SUB_91A0,{5U,6U,0U}}, +{SUB_91A0,{6U,6U,0U}}, +{SUB_91A0,{7U,6U,0U}}, +{SUB_91A8,{0U,6U,0U}}, +{SUB_91A8,{1U,6U,0U}}, +{SUB_91A8,{2U,6U,0U}}, +{SUB_91A8,{3U,6U,0U}}, +{SUB_91A8,{4U,6U,0U}}, +{SUB_91A8,{5U,6U,0U}}, +{SUB_91A8,{6U,6U,0U}}, +{SUB_91A8,{7U,6U,0U}}, +{SUB_91B0,{0U,6U,0U}}, +{SUB_91B0,{1U,6U,0U}}, +{SUB_91B0,{2U,6U,0U}}, +{SUB_91B0,{3U,6U,0U}}, +{SUB_91B0,{4U,6U,0U}}, +{SUB_91B0,{5U,6U,0U}}, +{SUB_91B0,{6U,6U,0U}}, +{SUB_91B0,{7U,6U,0U}}, +{SUB_91B8,{0U,6U,0U}}, +{SUB_91B9,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_91C0,{0U,6U,0U}}, +{SUBA_91C0,{1U,6U,0U}}, +{SUBA_91C0,{2U,6U,0U}}, +{SUBA_91C0,{3U,6U,0U}}, +{SUBA_91C0,{4U,6U,0U}}, +{SUBA_91C0,{5U,6U,0U}}, +{SUBA_91C0,{6U,6U,0U}}, +{SUBA_91C0,{7U,6U,0U}}, +{SUBA_91C8,{0U,6U,0U}}, +{SUBA_91C8,{1U,6U,0U}}, +{SUBA_91C8,{2U,6U,0U}}, +{SUBA_91C8,{3U,6U,0U}}, +{SUBA_91C8,{4U,6U,0U}}, +{SUBA_91C8,{5U,6U,0U}}, +{SUBA_91C8,{6U,6U,0U}}, +{SUBA_91C8,{7U,6U,0U}}, +{SUBA_91D0,{0U,6U,0U}}, +{SUBA_91D0,{1U,6U,0U}}, +{SUBA_91D0,{2U,6U,0U}}, +{SUBA_91D0,{3U,6U,0U}}, +{SUBA_91D0,{4U,6U,0U}}, +{SUBA_91D0,{5U,6U,0U}}, +{SUBA_91D0,{6U,6U,0U}}, +{SUBA_91D0,{7U,6U,0U}}, +{SUBA_91D8,{0U,6U,0U}}, +{SUBA_91D8,{1U,6U,0U}}, +{SUBA_91D8,{2U,6U,0U}}, +{SUBA_91D8,{3U,6U,0U}}, +{SUBA_91D8,{4U,6U,0U}}, +{SUBA_91D8,{5U,6U,0U}}, +{SUBA_91D8,{6U,6U,0U}}, +{SUBA_91D8,{7U,6U,0U}}, +{SUBA_91E0,{0U,6U,0U}}, +{SUBA_91E0,{1U,6U,0U}}, +{SUBA_91E0,{2U,6U,0U}}, +{SUBA_91E0,{3U,6U,0U}}, +{SUBA_91E0,{4U,6U,0U}}, +{SUBA_91E0,{5U,6U,0U}}, +{SUBA_91E0,{6U,6U,0U}}, +{SUBA_91E0,{7U,6U,0U}}, +{SUBA_91E8,{0U,6U,0U}}, +{SUBA_91E8,{1U,6U,0U}}, +{SUBA_91E8,{2U,6U,0U}}, +{SUBA_91E8,{3U,6U,0U}}, +{SUBA_91E8,{4U,6U,0U}}, +{SUBA_91E8,{5U,6U,0U}}, +{SUBA_91E8,{6U,6U,0U}}, +{SUBA_91E8,{7U,6U,0U}}, +{SUBA_91F0,{0U,6U,0U}}, +{SUBA_91F0,{1U,6U,0U}}, +{SUBA_91F0,{2U,6U,0U}}, +{SUBA_91F0,{3U,6U,0U}}, +{SUBA_91F0,{4U,6U,0U}}, +{SUBA_91F0,{5U,6U,0U}}, +{SUBA_91F0,{6U,6U,0U}}, +{SUBA_91F0,{7U,6U,0U}}, +{SUBA_91F8,{0U,6U,0U}}, +{SUBA_91F9,{0U,6U,0U}}, +{SUBA_91FA,{0U,6U,0U}}, +{SUBA_91FB,{0U,6U,0U}}, +{SUBA_91FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9000,{0U,7U,0U}}, +{SUB_9000,{1U,7U,0U}}, +{SUB_9000,{2U,7U,0U}}, +{SUB_9000,{3U,7U,0U}}, +{SUB_9000,{4U,7U,0U}}, +{SUB_9000,{5U,7U,0U}}, +{SUB_9000,{6U,7U,0U}}, +{SUB_9000,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9010,{0U,7U,0U}}, +{SUB_9010,{1U,7U,0U}}, +{SUB_9010,{2U,7U,0U}}, +{SUB_9010,{3U,7U,0U}}, +{SUB_9010,{4U,7U,0U}}, +{SUB_9010,{5U,7U,0U}}, +{SUB_9010,{6U,7U,0U}}, +{SUB_9010,{7U,7U,0U}}, +{SUB_9018,{0U,7U,0U}}, +{SUB_9018,{1U,7U,0U}}, +{SUB_9018,{2U,7U,0U}}, +{SUB_9018,{3U,7U,0U}}, +{SUB_9018,{4U,7U,0U}}, +{SUB_9018,{5U,7U,0U}}, +{SUB_9018,{6U,7U,0U}}, +{SUB_9018,{7U,7U,0U}}, +{SUB_9020,{0U,7U,0U}}, +{SUB_9020,{1U,7U,0U}}, +{SUB_9020,{2U,7U,0U}}, +{SUB_9020,{3U,7U,0U}}, +{SUB_9020,{4U,7U,0U}}, +{SUB_9020,{5U,7U,0U}}, +{SUB_9020,{6U,7U,0U}}, +{SUB_9020,{7U,7U,0U}}, +{SUB_9028,{0U,7U,0U}}, +{SUB_9028,{1U,7U,0U}}, +{SUB_9028,{2U,7U,0U}}, +{SUB_9028,{3U,7U,0U}}, +{SUB_9028,{4U,7U,0U}}, +{SUB_9028,{5U,7U,0U}}, +{SUB_9028,{6U,7U,0U}}, +{SUB_9028,{7U,7U,0U}}, +{SUB_9030,{0U,7U,0U}}, +{SUB_9030,{1U,7U,0U}}, +{SUB_9030,{2U,7U,0U}}, +{SUB_9030,{3U,7U,0U}}, +{SUB_9030,{4U,7U,0U}}, +{SUB_9030,{5U,7U,0U}}, +{SUB_9030,{6U,7U,0U}}, +{SUB_9030,{7U,7U,0U}}, +{SUB_9038,{0U,7U,0U}}, +{SUB_9039,{0U,7U,0U}}, +{SUB_903A,{0U,7U,0U}}, +{SUB_903B,{0U,7U,0U}}, +{SUB_903C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9040,{0U,7U,0U}}, +{SUB_9040,{1U,7U,0U}}, +{SUB_9040,{2U,7U,0U}}, +{SUB_9040,{3U,7U,0U}}, +{SUB_9040,{4U,7U,0U}}, +{SUB_9040,{5U,7U,0U}}, +{SUB_9040,{6U,7U,0U}}, +{SUB_9040,{7U,7U,0U}}, +{SUB_9048,{0U,7U,0U}}, +{SUB_9048,{1U,7U,0U}}, +{SUB_9048,{2U,7U,0U}}, +{SUB_9048,{3U,7U,0U}}, +{SUB_9048,{4U,7U,0U}}, +{SUB_9048,{5U,7U,0U}}, +{SUB_9048,{6U,7U,0U}}, +{SUB_9048,{7U,7U,0U}}, +{SUB_9050,{0U,7U,0U}}, +{SUB_9050,{1U,7U,0U}}, +{SUB_9050,{2U,7U,0U}}, +{SUB_9050,{3U,7U,0U}}, +{SUB_9050,{4U,7U,0U}}, +{SUB_9050,{5U,7U,0U}}, +{SUB_9050,{6U,7U,0U}}, +{SUB_9050,{7U,7U,0U}}, +{SUB_9058,{0U,7U,0U}}, +{SUB_9058,{1U,7U,0U}}, +{SUB_9058,{2U,7U,0U}}, +{SUB_9058,{3U,7U,0U}}, +{SUB_9058,{4U,7U,0U}}, +{SUB_9058,{5U,7U,0U}}, +{SUB_9058,{6U,7U,0U}}, +{SUB_9058,{7U,7U,0U}}, +{SUB_9060,{0U,7U,0U}}, +{SUB_9060,{1U,7U,0U}}, +{SUB_9060,{2U,7U,0U}}, +{SUB_9060,{3U,7U,0U}}, +{SUB_9060,{4U,7U,0U}}, +{SUB_9060,{5U,7U,0U}}, +{SUB_9060,{6U,7U,0U}}, +{SUB_9060,{7U,7U,0U}}, +{SUB_9068,{0U,7U,0U}}, +{SUB_9068,{1U,7U,0U}}, +{SUB_9068,{2U,7U,0U}}, +{SUB_9068,{3U,7U,0U}}, +{SUB_9068,{4U,7U,0U}}, +{SUB_9068,{5U,7U,0U}}, +{SUB_9068,{6U,7U,0U}}, +{SUB_9068,{7U,7U,0U}}, +{SUB_9070,{0U,7U,0U}}, +{SUB_9070,{1U,7U,0U}}, +{SUB_9070,{2U,7U,0U}}, +{SUB_9070,{3U,7U,0U}}, +{SUB_9070,{4U,7U,0U}}, +{SUB_9070,{5U,7U,0U}}, +{SUB_9070,{6U,7U,0U}}, +{SUB_9070,{7U,7U,0U}}, +{SUB_9078,{0U,7U,0U}}, +{SUB_9079,{0U,7U,0U}}, +{SUB_907A,{0U,7U,0U}}, +{SUB_907B,{0U,7U,0U}}, +{SUB_907C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUB_9080,{0U,7U,0U}}, +{SUB_9080,{1U,7U,0U}}, +{SUB_9080,{2U,7U,0U}}, +{SUB_9080,{3U,7U,0U}}, +{SUB_9080,{4U,7U,0U}}, +{SUB_9080,{5U,7U,0U}}, +{SUB_9080,{6U,7U,0U}}, +{SUB_9080,{7U,7U,0U}}, +{SUB_9088,{0U,7U,0U}}, +{SUB_9088,{1U,7U,0U}}, +{SUB_9088,{2U,7U,0U}}, +{SUB_9088,{3U,7U,0U}}, +{SUB_9088,{4U,7U,0U}}, +{SUB_9088,{5U,7U,0U}}, +{SUB_9088,{6U,7U,0U}}, +{SUB_9088,{7U,7U,0U}}, +{SUB_9090,{0U,7U,0U}}, +{SUB_9090,{1U,7U,0U}}, +{SUB_9090,{2U,7U,0U}}, +{SUB_9090,{3U,7U,0U}}, +{SUB_9090,{4U,7U,0U}}, +{SUB_9090,{5U,7U,0U}}, +{SUB_9090,{6U,7U,0U}}, +{SUB_9090,{7U,7U,0U}}, +{SUB_9098,{0U,7U,0U}}, +{SUB_9098,{1U,7U,0U}}, +{SUB_9098,{2U,7U,0U}}, +{SUB_9098,{3U,7U,0U}}, +{SUB_9098,{4U,7U,0U}}, +{SUB_9098,{5U,7U,0U}}, +{SUB_9098,{6U,7U,0U}}, +{SUB_9098,{7U,7U,0U}}, +{SUB_90A0,{0U,7U,0U}}, +{SUB_90A0,{1U,7U,0U}}, +{SUB_90A0,{2U,7U,0U}}, +{SUB_90A0,{3U,7U,0U}}, +{SUB_90A0,{4U,7U,0U}}, +{SUB_90A0,{5U,7U,0U}}, +{SUB_90A0,{6U,7U,0U}}, +{SUB_90A0,{7U,7U,0U}}, +{SUB_90A8,{0U,7U,0U}}, +{SUB_90A8,{1U,7U,0U}}, +{SUB_90A8,{2U,7U,0U}}, +{SUB_90A8,{3U,7U,0U}}, +{SUB_90A8,{4U,7U,0U}}, +{SUB_90A8,{5U,7U,0U}}, +{SUB_90A8,{6U,7U,0U}}, +{SUB_90A8,{7U,7U,0U}}, +{SUB_90B0,{0U,7U,0U}}, +{SUB_90B0,{1U,7U,0U}}, +{SUB_90B0,{2U,7U,0U}}, +{SUB_90B0,{3U,7U,0U}}, +{SUB_90B0,{4U,7U,0U}}, +{SUB_90B0,{5U,7U,0U}}, +{SUB_90B0,{6U,7U,0U}}, +{SUB_90B0,{7U,7U,0U}}, +{SUB_90B8,{0U,7U,0U}}, +{SUB_90B9,{0U,7U,0U}}, +{SUB_90BA,{0U,7U,0U}}, +{SUB_90BB,{0U,7U,0U}}, +{SUB_90BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBA_90C0,{0U,7U,0U}}, +{SUBA_90C0,{1U,7U,0U}}, +{SUBA_90C0,{2U,7U,0U}}, +{SUBA_90C0,{3U,7U,0U}}, +{SUBA_90C0,{4U,7U,0U}}, +{SUBA_90C0,{5U,7U,0U}}, +{SUBA_90C0,{6U,7U,0U}}, +{SUBA_90C0,{7U,7U,0U}}, +{SUBA_90C8,{0U,7U,0U}}, +{SUBA_90C8,{1U,7U,0U}}, +{SUBA_90C8,{2U,7U,0U}}, +{SUBA_90C8,{3U,7U,0U}}, +{SUBA_90C8,{4U,7U,0U}}, +{SUBA_90C8,{5U,7U,0U}}, +{SUBA_90C8,{6U,7U,0U}}, +{SUBA_90C8,{7U,7U,0U}}, +{SUBA_90D0,{0U,7U,0U}}, +{SUBA_90D0,{1U,7U,0U}}, +{SUBA_90D0,{2U,7U,0U}}, +{SUBA_90D0,{3U,7U,0U}}, +{SUBA_90D0,{4U,7U,0U}}, +{SUBA_90D0,{5U,7U,0U}}, +{SUBA_90D0,{6U,7U,0U}}, +{SUBA_90D0,{7U,7U,0U}}, +{SUBA_90D8,{0U,7U,0U}}, +{SUBA_90D8,{1U,7U,0U}}, +{SUBA_90D8,{2U,7U,0U}}, +{SUBA_90D8,{3U,7U,0U}}, +{SUBA_90D8,{4U,7U,0U}}, +{SUBA_90D8,{5U,7U,0U}}, +{SUBA_90D8,{6U,7U,0U}}, +{SUBA_90D8,{7U,7U,0U}}, +{SUBA_90E0,{0U,7U,0U}}, +{SUBA_90E0,{1U,7U,0U}}, +{SUBA_90E0,{2U,7U,0U}}, +{SUBA_90E0,{3U,7U,0U}}, +{SUBA_90E0,{4U,7U,0U}}, +{SUBA_90E0,{5U,7U,0U}}, +{SUBA_90E0,{6U,7U,0U}}, +{SUBA_90E0,{7U,7U,0U}}, +{SUBA_90E8,{0U,7U,0U}}, +{SUBA_90E8,{1U,7U,0U}}, +{SUBA_90E8,{2U,7U,0U}}, +{SUBA_90E8,{3U,7U,0U}}, +{SUBA_90E8,{4U,7U,0U}}, +{SUBA_90E8,{5U,7U,0U}}, +{SUBA_90E8,{6U,7U,0U}}, +{SUBA_90E8,{7U,7U,0U}}, +{SUBA_90F0,{0U,7U,0U}}, +{SUBA_90F0,{1U,7U,0U}}, +{SUBA_90F0,{2U,7U,0U}}, +{SUBA_90F0,{3U,7U,0U}}, +{SUBA_90F0,{4U,7U,0U}}, +{SUBA_90F0,{5U,7U,0U}}, +{SUBA_90F0,{6U,7U,0U}}, +{SUBA_90F0,{7U,7U,0U}}, +{SUBA_90F8,{0U,7U,0U}}, +{SUBA_90F9,{0U,7U,0U}}, +{SUBA_90FA,{0U,7U,0U}}, +{SUBA_90FB,{0U,7U,0U}}, +{SUBA_90FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9100,{0U,7U,0U}}, +{SUBX_9100,{1U,7U,0U}}, +{SUBX_9100,{2U,7U,0U}}, +{SUBX_9100,{3U,7U,0U}}, +{SUBX_9100,{4U,7U,0U}}, +{SUBX_9100,{5U,7U,0U}}, +{SUBX_9100,{6U,7U,0U}}, +{SUBX_9100,{7U,7U,0U}}, +{SUBX_9108,{0U,7U,0U}}, +{SUBX_9108,{1U,7U,0U}}, +{SUBX_9108,{2U,7U,0U}}, +{SUBX_9108,{3U,7U,0U}}, +{SUBX_9108,{4U,7U,0U}}, +{SUBX_9108,{5U,7U,0U}}, +{SUBX_9108,{6U,7U,0U}}, +{SUBX_9108,{7U,7U,0U}}, +{SUB_9110,{0U,7U,0U}}, +{SUB_9110,{1U,7U,0U}}, +{SUB_9110,{2U,7U,0U}}, +{SUB_9110,{3U,7U,0U}}, +{SUB_9110,{4U,7U,0U}}, +{SUB_9110,{5U,7U,0U}}, +{SUB_9110,{6U,7U,0U}}, +{SUB_9110,{7U,7U,0U}}, +{SUB_9118,{0U,7U,0U}}, +{SUB_9118,{1U,7U,0U}}, +{SUB_9118,{2U,7U,0U}}, +{SUB_9118,{3U,7U,0U}}, +{SUB_9118,{4U,7U,0U}}, +{SUB_9118,{5U,7U,0U}}, +{SUB_9118,{6U,7U,0U}}, +{SUB_9118,{7U,7U,0U}}, +{SUB_9120,{0U,7U,0U}}, +{SUB_9120,{1U,7U,0U}}, +{SUB_9120,{2U,7U,0U}}, +{SUB_9120,{3U,7U,0U}}, +{SUB_9120,{4U,7U,0U}}, +{SUB_9120,{5U,7U,0U}}, +{SUB_9120,{6U,7U,0U}}, +{SUB_9120,{7U,7U,0U}}, +{SUB_9128,{0U,7U,0U}}, +{SUB_9128,{1U,7U,0U}}, +{SUB_9128,{2U,7U,0U}}, +{SUB_9128,{3U,7U,0U}}, +{SUB_9128,{4U,7U,0U}}, +{SUB_9128,{5U,7U,0U}}, +{SUB_9128,{6U,7U,0U}}, +{SUB_9128,{7U,7U,0U}}, +{SUB_9130,{0U,7U,0U}}, +{SUB_9130,{1U,7U,0U}}, +{SUB_9130,{2U,7U,0U}}, +{SUB_9130,{3U,7U,0U}}, +{SUB_9130,{4U,7U,0U}}, +{SUB_9130,{5U,7U,0U}}, +{SUB_9130,{6U,7U,0U}}, +{SUB_9130,{7U,7U,0U}}, +{SUB_9138,{0U,7U,0U}}, +{SUB_9139,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9140,{0U,7U,0U}}, +{SUBX_9140,{1U,7U,0U}}, +{SUBX_9140,{2U,7U,0U}}, +{SUBX_9140,{3U,7U,0U}}, +{SUBX_9140,{4U,7U,0U}}, +{SUBX_9140,{5U,7U,0U}}, +{SUBX_9140,{6U,7U,0U}}, +{SUBX_9140,{7U,7U,0U}}, +{SUBX_9148,{0U,7U,0U}}, +{SUBX_9148,{1U,7U,0U}}, +{SUBX_9148,{2U,7U,0U}}, +{SUBX_9148,{3U,7U,0U}}, +{SUBX_9148,{4U,7U,0U}}, +{SUBX_9148,{5U,7U,0U}}, +{SUBX_9148,{6U,7U,0U}}, +{SUBX_9148,{7U,7U,0U}}, +{SUB_9150,{0U,7U,0U}}, +{SUB_9150,{1U,7U,0U}}, +{SUB_9150,{2U,7U,0U}}, +{SUB_9150,{3U,7U,0U}}, +{SUB_9150,{4U,7U,0U}}, +{SUB_9150,{5U,7U,0U}}, +{SUB_9150,{6U,7U,0U}}, +{SUB_9150,{7U,7U,0U}}, +{SUB_9158,{0U,7U,0U}}, +{SUB_9158,{1U,7U,0U}}, +{SUB_9158,{2U,7U,0U}}, +{SUB_9158,{3U,7U,0U}}, +{SUB_9158,{4U,7U,0U}}, +{SUB_9158,{5U,7U,0U}}, +{SUB_9158,{6U,7U,0U}}, +{SUB_9158,{7U,7U,0U}}, +{SUB_9160,{0U,7U,0U}}, +{SUB_9160,{1U,7U,0U}}, +{SUB_9160,{2U,7U,0U}}, +{SUB_9160,{3U,7U,0U}}, +{SUB_9160,{4U,7U,0U}}, +{SUB_9160,{5U,7U,0U}}, +{SUB_9160,{6U,7U,0U}}, +{SUB_9160,{7U,7U,0U}}, +{SUB_9168,{0U,7U,0U}}, +{SUB_9168,{1U,7U,0U}}, +{SUB_9168,{2U,7U,0U}}, +{SUB_9168,{3U,7U,0U}}, +{SUB_9168,{4U,7U,0U}}, +{SUB_9168,{5U,7U,0U}}, +{SUB_9168,{6U,7U,0U}}, +{SUB_9168,{7U,7U,0U}}, +{SUB_9170,{0U,7U,0U}}, +{SUB_9170,{1U,7U,0U}}, +{SUB_9170,{2U,7U,0U}}, +{SUB_9170,{3U,7U,0U}}, +{SUB_9170,{4U,7U,0U}}, +{SUB_9170,{5U,7U,0U}}, +{SUB_9170,{6U,7U,0U}}, +{SUB_9170,{7U,7U,0U}}, +{SUB_9178,{0U,7U,0U}}, +{SUB_9179,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{SUBX_9180,{0U,7U,0U}}, +{SUBX_9180,{1U,7U,0U}}, +{SUBX_9180,{2U,7U,0U}}, +{SUBX_9180,{3U,7U,0U}}, +{SUBX_9180,{4U,7U,0U}}, +{SUBX_9180,{5U,7U,0U}}, +{SUBX_9180,{6U,7U,0U}}, +{SUBX_9180,{7U,7U,0U}}, +{SUBX_9188,{0U,7U,0U}}, +{SUBX_9188,{1U,7U,0U}}, +{SUBX_9188,{2U,7U,0U}}, +{SUBX_9188,{3U,7U,0U}}, +{SUBX_9188,{4U,7U,0U}}, +{SUBX_9188,{5U,7U,0U}}, +{SUBX_9188,{6U,7U,0U}}, +{SUBX_9188,{7U,7U,0U}}, +{SUB_9190,{0U,7U,0U}}, +{SUB_9190,{1U,7U,0U}}, +{SUB_9190,{2U,7U,0U}}, +{SUB_9190,{3U,7U,0U}}, +{SUB_9190,{4U,7U,0U}}, +{SUB_9190,{5U,7U,0U}}, +{SUB_9190,{6U,7U,0U}}, +{SUB_9190,{7U,7U,0U}}, +{SUB_9198,{0U,7U,0U}}, +{SUB_9198,{1U,7U,0U}}, +{SUB_9198,{2U,7U,0U}}, +{SUB_9198,{3U,7U,0U}}, +{SUB_9198,{4U,7U,0U}}, +{SUB_9198,{5U,7U,0U}}, +{SUB_9198,{6U,7U,0U}}, +{SUB_9198,{7U,7U,0U}}, +{SUB_91A0,{0U,7U,0U}}, +{SUB_91A0,{1U,7U,0U}}, +{SUB_91A0,{2U,7U,0U}}, +{SUB_91A0,{3U,7U,0U}}, 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+{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B000,{0U,0U,0U}}, +{CMP_B000,{1U,0U,0U}}, +{CMP_B000,{2U,0U,0U}}, +{CMP_B000,{3U,0U,0U}}, +{CMP_B000,{4U,0U,0U}}, +{CMP_B000,{5U,0U,0U}}, +{CMP_B000,{6U,0U,0U}}, +{CMP_B000,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B010,{0U,0U,0U}}, +{CMP_B010,{1U,0U,0U}}, +{CMP_B010,{2U,0U,0U}}, +{CMP_B010,{3U,0U,0U}}, +{CMP_B010,{4U,0U,0U}}, +{CMP_B010,{5U,0U,0U}}, +{CMP_B010,{6U,0U,0U}}, +{CMP_B010,{7U,0U,0U}}, +{CMP_B018,{0U,0U,0U}}, +{CMP_B018,{1U,0U,0U}}, +{CMP_B018,{2U,0U,0U}}, +{CMP_B018,{3U,0U,0U}}, +{CMP_B018,{4U,0U,0U}}, +{CMP_B018,{5U,0U,0U}}, +{CMP_B018,{6U,0U,0U}}, +{CMP_B018,{7U,0U,0U}}, +{CMP_B020,{0U,0U,0U}}, +{CMP_B020,{1U,0U,0U}}, +{CMP_B020,{2U,0U,0U}}, +{CMP_B020,{3U,0U,0U}}, +{CMP_B020,{4U,0U,0U}}, +{CMP_B020,{5U,0U,0U}}, +{CMP_B020,{6U,0U,0U}}, +{CMP_B020,{7U,0U,0U}}, +{CMP_B028,{0U,0U,0U}}, +{CMP_B028,{1U,0U,0U}}, +{CMP_B028,{2U,0U,0U}}, +{CMP_B028,{3U,0U,0U}}, +{CMP_B028,{4U,0U,0U}}, +{CMP_B028,{5U,0U,0U}}, +{CMP_B028,{6U,0U,0U}}, +{CMP_B028,{7U,0U,0U}}, +{CMP_B030,{0U,0U,0U}}, +{CMP_B030,{1U,0U,0U}}, +{CMP_B030,{2U,0U,0U}}, +{CMP_B030,{3U,0U,0U}}, +{CMP_B030,{4U,0U,0U}}, +{CMP_B030,{5U,0U,0U}}, +{CMP_B030,{6U,0U,0U}}, +{CMP_B030,{7U,0U,0U}}, +{CMP_B038,{0U,0U,0U}}, +{CMP_B039,{0U,0U,0U}}, +{CMP_B03A,{0U,0U,0U}}, +{CMP_B03B,{0U,0U,0U}}, +{CMP_B03C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B040,{0U,0U,0U}}, +{CMP_B040,{1U,0U,0U}}, +{CMP_B040,{2U,0U,0U}}, +{CMP_B040,{3U,0U,0U}}, +{CMP_B040,{4U,0U,0U}}, +{CMP_B040,{5U,0U,0U}}, +{CMP_B040,{6U,0U,0U}}, +{CMP_B040,{7U,0U,0U}}, +{CMP_B048,{0U,0U,0U}}, +{CMP_B048,{1U,0U,0U}}, +{CMP_B048,{2U,0U,0U}}, +{CMP_B048,{3U,0U,0U}}, +{CMP_B048,{4U,0U,0U}}, +{CMP_B048,{5U,0U,0U}}, +{CMP_B048,{6U,0U,0U}}, +{CMP_B048,{7U,0U,0U}}, +{CMP_B050,{0U,0U,0U}}, +{CMP_B050,{1U,0U,0U}}, +{CMP_B050,{2U,0U,0U}}, +{CMP_B050,{3U,0U,0U}}, +{CMP_B050,{4U,0U,0U}}, +{CMP_B050,{5U,0U,0U}}, +{CMP_B050,{6U,0U,0U}}, +{CMP_B050,{7U,0U,0U}}, +{CMP_B058,{0U,0U,0U}}, +{CMP_B058,{1U,0U,0U}}, +{CMP_B058,{2U,0U,0U}}, +{CMP_B058,{3U,0U,0U}}, +{CMP_B058,{4U,0U,0U}}, +{CMP_B058,{5U,0U,0U}}, +{CMP_B058,{6U,0U,0U}}, +{CMP_B058,{7U,0U,0U}}, +{CMP_B060,{0U,0U,0U}}, +{CMP_B060,{1U,0U,0U}}, +{CMP_B060,{2U,0U,0U}}, +{CMP_B060,{3U,0U,0U}}, +{CMP_B060,{4U,0U,0U}}, +{CMP_B060,{5U,0U,0U}}, +{CMP_B060,{6U,0U,0U}}, +{CMP_B060,{7U,0U,0U}}, +{CMP_B068,{0U,0U,0U}}, +{CMP_B068,{1U,0U,0U}}, +{CMP_B068,{2U,0U,0U}}, +{CMP_B068,{3U,0U,0U}}, +{CMP_B068,{4U,0U,0U}}, +{CMP_B068,{5U,0U,0U}}, +{CMP_B068,{6U,0U,0U}}, +{CMP_B068,{7U,0U,0U}}, +{CMP_B070,{0U,0U,0U}}, +{CMP_B070,{1U,0U,0U}}, +{CMP_B070,{2U,0U,0U}}, +{CMP_B070,{3U,0U,0U}}, +{CMP_B070,{4U,0U,0U}}, +{CMP_B070,{5U,0U,0U}}, +{CMP_B070,{6U,0U,0U}}, +{CMP_B070,{7U,0U,0U}}, +{CMP_B078,{0U,0U,0U}}, +{CMP_B079,{0U,0U,0U}}, +{CMP_B07A,{0U,0U,0U}}, +{CMP_B07B,{0U,0U,0U}}, +{CMP_B07C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B080,{0U,0U,0U}}, +{CMP_B080,{1U,0U,0U}}, +{CMP_B080,{2U,0U,0U}}, +{CMP_B080,{3U,0U,0U}}, +{CMP_B080,{4U,0U,0U}}, +{CMP_B080,{5U,0U,0U}}, +{CMP_B080,{6U,0U,0U}}, +{CMP_B080,{7U,0U,0U}}, +{CMP_B088,{0U,0U,0U}}, +{CMP_B088,{1U,0U,0U}}, +{CMP_B088,{2U,0U,0U}}, +{CMP_B088,{3U,0U,0U}}, +{CMP_B088,{4U,0U,0U}}, +{CMP_B088,{5U,0U,0U}}, +{CMP_B088,{6U,0U,0U}}, +{CMP_B088,{7U,0U,0U}}, +{CMP_B090,{0U,0U,0U}}, +{CMP_B090,{1U,0U,0U}}, +{CMP_B090,{2U,0U,0U}}, +{CMP_B090,{3U,0U,0U}}, +{CMP_B090,{4U,0U,0U}}, +{CMP_B090,{5U,0U,0U}}, +{CMP_B090,{6U,0U,0U}}, +{CMP_B090,{7U,0U,0U}}, +{CMP_B098,{0U,0U,0U}}, +{CMP_B098,{1U,0U,0U}}, +{CMP_B098,{2U,0U,0U}}, +{CMP_B098,{3U,0U,0U}}, +{CMP_B098,{4U,0U,0U}}, +{CMP_B098,{5U,0U,0U}}, +{CMP_B098,{6U,0U,0U}}, +{CMP_B098,{7U,0U,0U}}, +{CMP_B0A0,{0U,0U,0U}}, +{CMP_B0A0,{1U,0U,0U}}, +{CMP_B0A0,{2U,0U,0U}}, +{CMP_B0A0,{3U,0U,0U}}, +{CMP_B0A0,{4U,0U,0U}}, +{CMP_B0A0,{5U,0U,0U}}, +{CMP_B0A0,{6U,0U,0U}}, +{CMP_B0A0,{7U,0U,0U}}, +{CMP_B0A8,{0U,0U,0U}}, +{CMP_B0A8,{1U,0U,0U}}, +{CMP_B0A8,{2U,0U,0U}}, +{CMP_B0A8,{3U,0U,0U}}, +{CMP_B0A8,{4U,0U,0U}}, +{CMP_B0A8,{5U,0U,0U}}, +{CMP_B0A8,{6U,0U,0U}}, +{CMP_B0A8,{7U,0U,0U}}, +{CMP_B0B0,{0U,0U,0U}}, +{CMP_B0B0,{1U,0U,0U}}, +{CMP_B0B0,{2U,0U,0U}}, +{CMP_B0B0,{3U,0U,0U}}, +{CMP_B0B0,{4U,0U,0U}}, +{CMP_B0B0,{5U,0U,0U}}, +{CMP_B0B0,{6U,0U,0U}}, +{CMP_B0B0,{7U,0U,0U}}, +{CMP_B0B8,{0U,0U,0U}}, +{CMP_B0B9,{0U,0U,0U}}, +{CMP_B0BA,{0U,0U,0U}}, +{CMP_B0BB,{0U,0U,0U}}, +{CMP_B0BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B0C0,{0U,0U,0U}}, +{CMPA_B0C0,{1U,0U,0U}}, +{CMPA_B0C0,{2U,0U,0U}}, +{CMPA_B0C0,{3U,0U,0U}}, +{CMPA_B0C0,{4U,0U,0U}}, +{CMPA_B0C0,{5U,0U,0U}}, +{CMPA_B0C0,{6U,0U,0U}}, +{CMPA_B0C0,{7U,0U,0U}}, +{CMPA_B0C8,{0U,0U,0U}}, +{CMPA_B0C8,{1U,0U,0U}}, +{CMPA_B0C8,{2U,0U,0U}}, +{CMPA_B0C8,{3U,0U,0U}}, +{CMPA_B0C8,{4U,0U,0U}}, +{CMPA_B0C8,{5U,0U,0U}}, +{CMPA_B0C8,{6U,0U,0U}}, +{CMPA_B0C8,{7U,0U,0U}}, +{CMPA_B0D0,{0U,0U,0U}}, +{CMPA_B0D0,{1U,0U,0U}}, +{CMPA_B0D0,{2U,0U,0U}}, +{CMPA_B0D0,{3U,0U,0U}}, +{CMPA_B0D0,{4U,0U,0U}}, +{CMPA_B0D0,{5U,0U,0U}}, +{CMPA_B0D0,{6U,0U,0U}}, +{CMPA_B0D0,{7U,0U,0U}}, +{CMPA_B0D8,{0U,0U,0U}}, +{CMPA_B0D8,{1U,0U,0U}}, +{CMPA_B0D8,{2U,0U,0U}}, +{CMPA_B0D8,{3U,0U,0U}}, +{CMPA_B0D8,{4U,0U,0U}}, +{CMPA_B0D8,{5U,0U,0U}}, +{CMPA_B0D8,{6U,0U,0U}}, +{CMPA_B0D8,{7U,0U,0U}}, +{CMPA_B0E0,{0U,0U,0U}}, +{CMPA_B0E0,{1U,0U,0U}}, +{CMPA_B0E0,{2U,0U,0U}}, +{CMPA_B0E0,{3U,0U,0U}}, +{CMPA_B0E0,{4U,0U,0U}}, +{CMPA_B0E0,{5U,0U,0U}}, +{CMPA_B0E0,{6U,0U,0U}}, +{CMPA_B0E0,{7U,0U,0U}}, +{CMPA_B0E8,{0U,0U,0U}}, +{CMPA_B0E8,{1U,0U,0U}}, +{CMPA_B0E8,{2U,0U,0U}}, +{CMPA_B0E8,{3U,0U,0U}}, +{CMPA_B0E8,{4U,0U,0U}}, +{CMPA_B0E8,{5U,0U,0U}}, +{CMPA_B0E8,{6U,0U,0U}}, +{CMPA_B0E8,{7U,0U,0U}}, +{CMPA_B0F0,{0U,0U,0U}}, +{CMPA_B0F0,{1U,0U,0U}}, +{CMPA_B0F0,{2U,0U,0U}}, +{CMPA_B0F0,{3U,0U,0U}}, +{CMPA_B0F0,{4U,0U,0U}}, +{CMPA_B0F0,{5U,0U,0U}}, +{CMPA_B0F0,{6U,0U,0U}}, +{CMPA_B0F0,{7U,0U,0U}}, +{CMPA_B0F8,{0U,0U,0U}}, +{CMPA_B0F9,{0U,0U,0U}}, +{CMPA_B0FA,{0U,0U,0U}}, +{CMPA_B0FB,{0U,0U,0U}}, +{CMPA_B0FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B100,{0U,0U,0U}}, +{EOR_B100,{1U,0U,0U}}, +{EOR_B100,{2U,0U,0U}}, +{EOR_B100,{3U,0U,0U}}, +{EOR_B100,{4U,0U,0U}}, +{EOR_B100,{5U,0U,0U}}, +{EOR_B100,{6U,0U,0U}}, +{EOR_B100,{7U,0U,0U}}, +{CMPM_B108,{0U,0U,0U}}, +{CMPM_B108,{0U,1U,0U}}, +{CMPM_B108,{0U,2U,0U}}, +{CMPM_B108,{0U,3U,0U}}, +{CMPM_B108,{0U,4U,0U}}, +{CMPM_B108,{0U,5U,0U}}, +{CMPM_B108,{0U,6U,0U}}, +{CMPM_B108,{0U,7U,0U}}, +{EOR_B110,{0U,0U,0U}}, +{EOR_B110,{1U,0U,0U}}, +{EOR_B110,{2U,0U,0U}}, +{EOR_B110,{3U,0U,0U}}, +{EOR_B110,{4U,0U,0U}}, +{EOR_B110,{5U,0U,0U}}, +{EOR_B110,{6U,0U,0U}}, +{EOR_B110,{7U,0U,0U}}, +{EOR_B118,{0U,0U,0U}}, +{EOR_B118,{1U,0U,0U}}, +{EOR_B118,{2U,0U,0U}}, +{EOR_B118,{3U,0U,0U}}, +{EOR_B118,{4U,0U,0U}}, +{EOR_B118,{5U,0U,0U}}, +{EOR_B118,{6U,0U,0U}}, +{EOR_B118,{7U,0U,0U}}, +{EOR_B120,{0U,0U,0U}}, +{EOR_B120,{1U,0U,0U}}, +{EOR_B120,{2U,0U,0U}}, +{EOR_B120,{3U,0U,0U}}, +{EOR_B120,{4U,0U,0U}}, +{EOR_B120,{5U,0U,0U}}, +{EOR_B120,{6U,0U,0U}}, +{EOR_B120,{7U,0U,0U}}, +{EOR_B128,{0U,0U,0U}}, +{EOR_B128,{1U,0U,0U}}, +{EOR_B128,{2U,0U,0U}}, +{EOR_B128,{3U,0U,0U}}, +{EOR_B128,{4U,0U,0U}}, +{EOR_B128,{5U,0U,0U}}, +{EOR_B128,{6U,0U,0U}}, +{EOR_B128,{7U,0U,0U}}, +{EOR_B130,{0U,0U,0U}}, +{EOR_B130,{1U,0U,0U}}, +{EOR_B130,{2U,0U,0U}}, +{EOR_B130,{3U,0U,0U}}, +{EOR_B130,{4U,0U,0U}}, +{EOR_B130,{5U,0U,0U}}, +{EOR_B130,{6U,0U,0U}}, +{EOR_B130,{7U,0U,0U}}, +{EOR_B138,{0U,0U,0U}}, +{EOR_B139,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B140,{0U,0U,0U}}, +{EOR_B140,{1U,0U,0U}}, +{EOR_B140,{2U,0U,0U}}, +{EOR_B140,{3U,0U,0U}}, +{EOR_B140,{4U,0U,0U}}, +{EOR_B140,{5U,0U,0U}}, +{EOR_B140,{6U,0U,0U}}, +{EOR_B140,{7U,0U,0U}}, +{CMPM_B148,{0U,0U,0U}}, +{CMPM_B148,{0U,1U,0U}}, +{CMPM_B148,{0U,2U,0U}}, +{CMPM_B148,{0U,3U,0U}}, +{CMPM_B148,{0U,4U,0U}}, +{CMPM_B148,{0U,5U,0U}}, +{CMPM_B148,{0U,6U,0U}}, +{CMPM_B148,{0U,7U,0U}}, +{EOR_B150,{0U,0U,0U}}, +{EOR_B150,{1U,0U,0U}}, +{EOR_B150,{2U,0U,0U}}, +{EOR_B150,{3U,0U,0U}}, +{EOR_B150,{4U,0U,0U}}, +{EOR_B150,{5U,0U,0U}}, +{EOR_B150,{6U,0U,0U}}, +{EOR_B150,{7U,0U,0U}}, +{EOR_B158,{0U,0U,0U}}, +{EOR_B158,{1U,0U,0U}}, +{EOR_B158,{2U,0U,0U}}, +{EOR_B158,{3U,0U,0U}}, +{EOR_B158,{4U,0U,0U}}, +{EOR_B158,{5U,0U,0U}}, +{EOR_B158,{6U,0U,0U}}, +{EOR_B158,{7U,0U,0U}}, +{EOR_B160,{0U,0U,0U}}, +{EOR_B160,{1U,0U,0U}}, +{EOR_B160,{2U,0U,0U}}, +{EOR_B160,{3U,0U,0U}}, +{EOR_B160,{4U,0U,0U}}, +{EOR_B160,{5U,0U,0U}}, +{EOR_B160,{6U,0U,0U}}, +{EOR_B160,{7U,0U,0U}}, +{EOR_B168,{0U,0U,0U}}, +{EOR_B168,{1U,0U,0U}}, +{EOR_B168,{2U,0U,0U}}, +{EOR_B168,{3U,0U,0U}}, +{EOR_B168,{4U,0U,0U}}, +{EOR_B168,{5U,0U,0U}}, +{EOR_B168,{6U,0U,0U}}, +{EOR_B168,{7U,0U,0U}}, +{EOR_B170,{0U,0U,0U}}, +{EOR_B170,{1U,0U,0U}}, +{EOR_B170,{2U,0U,0U}}, +{EOR_B170,{3U,0U,0U}}, +{EOR_B170,{4U,0U,0U}}, +{EOR_B170,{5U,0U,0U}}, +{EOR_B170,{6U,0U,0U}}, +{EOR_B170,{7U,0U,0U}}, +{EOR_B178,{0U,0U,0U}}, +{EOR_B179,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B180,{0U,0U,0U}}, +{EOR_B180,{1U,0U,0U}}, +{EOR_B180,{2U,0U,0U}}, +{EOR_B180,{3U,0U,0U}}, +{EOR_B180,{4U,0U,0U}}, +{EOR_B180,{5U,0U,0U}}, +{EOR_B180,{6U,0U,0U}}, +{EOR_B180,{7U,0U,0U}}, +{CMPM_B188,{0U,0U,0U}}, +{CMPM_B188,{0U,1U,0U}}, +{CMPM_B188,{0U,2U,0U}}, +{CMPM_B188,{0U,3U,0U}}, +{CMPM_B188,{0U,4U,0U}}, +{CMPM_B188,{0U,5U,0U}}, +{CMPM_B188,{0U,6U,0U}}, +{CMPM_B188,{0U,7U,0U}}, +{EOR_B190,{0U,0U,0U}}, +{EOR_B190,{1U,0U,0U}}, +{EOR_B190,{2U,0U,0U}}, +{EOR_B190,{3U,0U,0U}}, +{EOR_B190,{4U,0U,0U}}, +{EOR_B190,{5U,0U,0U}}, +{EOR_B190,{6U,0U,0U}}, +{EOR_B190,{7U,0U,0U}}, +{EOR_B198,{0U,0U,0U}}, +{EOR_B198,{1U,0U,0U}}, +{EOR_B198,{2U,0U,0U}}, +{EOR_B198,{3U,0U,0U}}, +{EOR_B198,{4U,0U,0U}}, +{EOR_B198,{5U,0U,0U}}, +{EOR_B198,{6U,0U,0U}}, +{EOR_B198,{7U,0U,0U}}, +{EOR_B1A0,{0U,0U,0U}}, +{EOR_B1A0,{1U,0U,0U}}, +{EOR_B1A0,{2U,0U,0U}}, +{EOR_B1A0,{3U,0U,0U}}, +{EOR_B1A0,{4U,0U,0U}}, +{EOR_B1A0,{5U,0U,0U}}, +{EOR_B1A0,{6U,0U,0U}}, +{EOR_B1A0,{7U,0U,0U}}, +{EOR_B1A8,{0U,0U,0U}}, +{EOR_B1A8,{1U,0U,0U}}, +{EOR_B1A8,{2U,0U,0U}}, +{EOR_B1A8,{3U,0U,0U}}, +{EOR_B1A8,{4U,0U,0U}}, +{EOR_B1A8,{5U,0U,0U}}, +{EOR_B1A8,{6U,0U,0U}}, +{EOR_B1A8,{7U,0U,0U}}, +{EOR_B1B0,{0U,0U,0U}}, +{EOR_B1B0,{1U,0U,0U}}, +{EOR_B1B0,{2U,0U,0U}}, +{EOR_B1B0,{3U,0U,0U}}, +{EOR_B1B0,{4U,0U,0U}}, +{EOR_B1B0,{5U,0U,0U}}, +{EOR_B1B0,{6U,0U,0U}}, +{EOR_B1B0,{7U,0U,0U}}, +{EOR_B1B8,{0U,0U,0U}}, +{EOR_B1B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B1C0,{0U,0U,0U}}, +{CMPA_B1C0,{1U,0U,0U}}, +{CMPA_B1C0,{2U,0U,0U}}, +{CMPA_B1C0,{3U,0U,0U}}, +{CMPA_B1C0,{4U,0U,0U}}, +{CMPA_B1C0,{5U,0U,0U}}, +{CMPA_B1C0,{6U,0U,0U}}, +{CMPA_B1C0,{7U,0U,0U}}, +{CMPA_B1C8,{0U,0U,0U}}, +{CMPA_B1C8,{1U,0U,0U}}, +{CMPA_B1C8,{2U,0U,0U}}, +{CMPA_B1C8,{3U,0U,0U}}, +{CMPA_B1C8,{4U,0U,0U}}, +{CMPA_B1C8,{5U,0U,0U}}, +{CMPA_B1C8,{6U,0U,0U}}, +{CMPA_B1C8,{7U,0U,0U}}, +{CMPA_B1D0,{0U,0U,0U}}, +{CMPA_B1D0,{1U,0U,0U}}, +{CMPA_B1D0,{2U,0U,0U}}, +{CMPA_B1D0,{3U,0U,0U}}, +{CMPA_B1D0,{4U,0U,0U}}, +{CMPA_B1D0,{5U,0U,0U}}, +{CMPA_B1D0,{6U,0U,0U}}, +{CMPA_B1D0,{7U,0U,0U}}, +{CMPA_B1D8,{0U,0U,0U}}, +{CMPA_B1D8,{1U,0U,0U}}, +{CMPA_B1D8,{2U,0U,0U}}, +{CMPA_B1D8,{3U,0U,0U}}, +{CMPA_B1D8,{4U,0U,0U}}, +{CMPA_B1D8,{5U,0U,0U}}, +{CMPA_B1D8,{6U,0U,0U}}, +{CMPA_B1D8,{7U,0U,0U}}, +{CMPA_B1E0,{0U,0U,0U}}, +{CMPA_B1E0,{1U,0U,0U}}, +{CMPA_B1E0,{2U,0U,0U}}, +{CMPA_B1E0,{3U,0U,0U}}, +{CMPA_B1E0,{4U,0U,0U}}, +{CMPA_B1E0,{5U,0U,0U}}, +{CMPA_B1E0,{6U,0U,0U}}, +{CMPA_B1E0,{7U,0U,0U}}, +{CMPA_B1E8,{0U,0U,0U}}, +{CMPA_B1E8,{1U,0U,0U}}, +{CMPA_B1E8,{2U,0U,0U}}, +{CMPA_B1E8,{3U,0U,0U}}, +{CMPA_B1E8,{4U,0U,0U}}, +{CMPA_B1E8,{5U,0U,0U}}, +{CMPA_B1E8,{6U,0U,0U}}, +{CMPA_B1E8,{7U,0U,0U}}, +{CMPA_B1F0,{0U,0U,0U}}, +{CMPA_B1F0,{1U,0U,0U}}, +{CMPA_B1F0,{2U,0U,0U}}, +{CMPA_B1F0,{3U,0U,0U}}, +{CMPA_B1F0,{4U,0U,0U}}, +{CMPA_B1F0,{5U,0U,0U}}, +{CMPA_B1F0,{6U,0U,0U}}, +{CMPA_B1F0,{7U,0U,0U}}, +{CMPA_B1F8,{0U,0U,0U}}, +{CMPA_B1F9,{0U,0U,0U}}, +{CMPA_B1FA,{0U,0U,0U}}, +{CMPA_B1FB,{0U,0U,0U}}, +{CMPA_B1FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B000,{0U,1U,0U}}, +{CMP_B000,{1U,1U,0U}}, +{CMP_B000,{2U,1U,0U}}, +{CMP_B000,{3U,1U,0U}}, +{CMP_B000,{4U,1U,0U}}, +{CMP_B000,{5U,1U,0U}}, +{CMP_B000,{6U,1U,0U}}, +{CMP_B000,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B010,{0U,1U,0U}}, +{CMP_B010,{1U,1U,0U}}, +{CMP_B010,{2U,1U,0U}}, +{CMP_B010,{3U,1U,0U}}, +{CMP_B010,{4U,1U,0U}}, +{CMP_B010,{5U,1U,0U}}, +{CMP_B010,{6U,1U,0U}}, +{CMP_B010,{7U,1U,0U}}, +{CMP_B018,{0U,1U,0U}}, +{CMP_B018,{1U,1U,0U}}, +{CMP_B018,{2U,1U,0U}}, +{CMP_B018,{3U,1U,0U}}, +{CMP_B018,{4U,1U,0U}}, +{CMP_B018,{5U,1U,0U}}, +{CMP_B018,{6U,1U,0U}}, +{CMP_B018,{7U,1U,0U}}, +{CMP_B020,{0U,1U,0U}}, +{CMP_B020,{1U,1U,0U}}, +{CMP_B020,{2U,1U,0U}}, +{CMP_B020,{3U,1U,0U}}, +{CMP_B020,{4U,1U,0U}}, +{CMP_B020,{5U,1U,0U}}, +{CMP_B020,{6U,1U,0U}}, +{CMP_B020,{7U,1U,0U}}, +{CMP_B028,{0U,1U,0U}}, +{CMP_B028,{1U,1U,0U}}, +{CMP_B028,{2U,1U,0U}}, +{CMP_B028,{3U,1U,0U}}, +{CMP_B028,{4U,1U,0U}}, +{CMP_B028,{5U,1U,0U}}, +{CMP_B028,{6U,1U,0U}}, +{CMP_B028,{7U,1U,0U}}, +{CMP_B030,{0U,1U,0U}}, +{CMP_B030,{1U,1U,0U}}, +{CMP_B030,{2U,1U,0U}}, +{CMP_B030,{3U,1U,0U}}, +{CMP_B030,{4U,1U,0U}}, +{CMP_B030,{5U,1U,0U}}, +{CMP_B030,{6U,1U,0U}}, +{CMP_B030,{7U,1U,0U}}, +{CMP_B038,{0U,1U,0U}}, +{CMP_B039,{0U,1U,0U}}, +{CMP_B03A,{0U,1U,0U}}, +{CMP_B03B,{0U,1U,0U}}, +{CMP_B03C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B040,{0U,1U,0U}}, +{CMP_B040,{1U,1U,0U}}, +{CMP_B040,{2U,1U,0U}}, +{CMP_B040,{3U,1U,0U}}, +{CMP_B040,{4U,1U,0U}}, +{CMP_B040,{5U,1U,0U}}, +{CMP_B040,{6U,1U,0U}}, +{CMP_B040,{7U,1U,0U}}, +{CMP_B048,{0U,1U,0U}}, +{CMP_B048,{1U,1U,0U}}, +{CMP_B048,{2U,1U,0U}}, +{CMP_B048,{3U,1U,0U}}, +{CMP_B048,{4U,1U,0U}}, +{CMP_B048,{5U,1U,0U}}, +{CMP_B048,{6U,1U,0U}}, +{CMP_B048,{7U,1U,0U}}, +{CMP_B050,{0U,1U,0U}}, +{CMP_B050,{1U,1U,0U}}, +{CMP_B050,{2U,1U,0U}}, +{CMP_B050,{3U,1U,0U}}, +{CMP_B050,{4U,1U,0U}}, +{CMP_B050,{5U,1U,0U}}, +{CMP_B050,{6U,1U,0U}}, +{CMP_B050,{7U,1U,0U}}, +{CMP_B058,{0U,1U,0U}}, +{CMP_B058,{1U,1U,0U}}, +{CMP_B058,{2U,1U,0U}}, +{CMP_B058,{3U,1U,0U}}, +{CMP_B058,{4U,1U,0U}}, +{CMP_B058,{5U,1U,0U}}, +{CMP_B058,{6U,1U,0U}}, +{CMP_B058,{7U,1U,0U}}, +{CMP_B060,{0U,1U,0U}}, +{CMP_B060,{1U,1U,0U}}, +{CMP_B060,{2U,1U,0U}}, +{CMP_B060,{3U,1U,0U}}, +{CMP_B060,{4U,1U,0U}}, +{CMP_B060,{5U,1U,0U}}, +{CMP_B060,{6U,1U,0U}}, +{CMP_B060,{7U,1U,0U}}, +{CMP_B068,{0U,1U,0U}}, +{CMP_B068,{1U,1U,0U}}, +{CMP_B068,{2U,1U,0U}}, +{CMP_B068,{3U,1U,0U}}, +{CMP_B068,{4U,1U,0U}}, +{CMP_B068,{5U,1U,0U}}, +{CMP_B068,{6U,1U,0U}}, +{CMP_B068,{7U,1U,0U}}, +{CMP_B070,{0U,1U,0U}}, +{CMP_B070,{1U,1U,0U}}, +{CMP_B070,{2U,1U,0U}}, +{CMP_B070,{3U,1U,0U}}, +{CMP_B070,{4U,1U,0U}}, +{CMP_B070,{5U,1U,0U}}, +{CMP_B070,{6U,1U,0U}}, +{CMP_B070,{7U,1U,0U}}, +{CMP_B078,{0U,1U,0U}}, +{CMP_B079,{0U,1U,0U}}, +{CMP_B07A,{0U,1U,0U}}, +{CMP_B07B,{0U,1U,0U}}, +{CMP_B07C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B080,{0U,1U,0U}}, +{CMP_B080,{1U,1U,0U}}, +{CMP_B080,{2U,1U,0U}}, +{CMP_B080,{3U,1U,0U}}, +{CMP_B080,{4U,1U,0U}}, +{CMP_B080,{5U,1U,0U}}, +{CMP_B080,{6U,1U,0U}}, +{CMP_B080,{7U,1U,0U}}, +{CMP_B088,{0U,1U,0U}}, +{CMP_B088,{1U,1U,0U}}, +{CMP_B088,{2U,1U,0U}}, +{CMP_B088,{3U,1U,0U}}, +{CMP_B088,{4U,1U,0U}}, +{CMP_B088,{5U,1U,0U}}, +{CMP_B088,{6U,1U,0U}}, +{CMP_B088,{7U,1U,0U}}, +{CMP_B090,{0U,1U,0U}}, +{CMP_B090,{1U,1U,0U}}, +{CMP_B090,{2U,1U,0U}}, +{CMP_B090,{3U,1U,0U}}, +{CMP_B090,{4U,1U,0U}}, +{CMP_B090,{5U,1U,0U}}, +{CMP_B090,{6U,1U,0U}}, +{CMP_B090,{7U,1U,0U}}, +{CMP_B098,{0U,1U,0U}}, +{CMP_B098,{1U,1U,0U}}, +{CMP_B098,{2U,1U,0U}}, +{CMP_B098,{3U,1U,0U}}, +{CMP_B098,{4U,1U,0U}}, +{CMP_B098,{5U,1U,0U}}, +{CMP_B098,{6U,1U,0U}}, +{CMP_B098,{7U,1U,0U}}, +{CMP_B0A0,{0U,1U,0U}}, +{CMP_B0A0,{1U,1U,0U}}, +{CMP_B0A0,{2U,1U,0U}}, +{CMP_B0A0,{3U,1U,0U}}, +{CMP_B0A0,{4U,1U,0U}}, +{CMP_B0A0,{5U,1U,0U}}, +{CMP_B0A0,{6U,1U,0U}}, +{CMP_B0A0,{7U,1U,0U}}, +{CMP_B0A8,{0U,1U,0U}}, +{CMP_B0A8,{1U,1U,0U}}, +{CMP_B0A8,{2U,1U,0U}}, +{CMP_B0A8,{3U,1U,0U}}, +{CMP_B0A8,{4U,1U,0U}}, +{CMP_B0A8,{5U,1U,0U}}, +{CMP_B0A8,{6U,1U,0U}}, +{CMP_B0A8,{7U,1U,0U}}, +{CMP_B0B0,{0U,1U,0U}}, +{CMP_B0B0,{1U,1U,0U}}, +{CMP_B0B0,{2U,1U,0U}}, +{CMP_B0B0,{3U,1U,0U}}, +{CMP_B0B0,{4U,1U,0U}}, +{CMP_B0B0,{5U,1U,0U}}, +{CMP_B0B0,{6U,1U,0U}}, +{CMP_B0B0,{7U,1U,0U}}, +{CMP_B0B8,{0U,1U,0U}}, +{CMP_B0B9,{0U,1U,0U}}, +{CMP_B0BA,{0U,1U,0U}}, +{CMP_B0BB,{0U,1U,0U}}, +{CMP_B0BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B0C0,{0U,1U,0U}}, +{CMPA_B0C0,{1U,1U,0U}}, +{CMPA_B0C0,{2U,1U,0U}}, +{CMPA_B0C0,{3U,1U,0U}}, +{CMPA_B0C0,{4U,1U,0U}}, +{CMPA_B0C0,{5U,1U,0U}}, +{CMPA_B0C0,{6U,1U,0U}}, +{CMPA_B0C0,{7U,1U,0U}}, +{CMPA_B0C8,{0U,1U,0U}}, +{CMPA_B0C8,{1U,1U,0U}}, +{CMPA_B0C8,{2U,1U,0U}}, +{CMPA_B0C8,{3U,1U,0U}}, +{CMPA_B0C8,{4U,1U,0U}}, +{CMPA_B0C8,{5U,1U,0U}}, +{CMPA_B0C8,{6U,1U,0U}}, +{CMPA_B0C8,{7U,1U,0U}}, +{CMPA_B0D0,{0U,1U,0U}}, +{CMPA_B0D0,{1U,1U,0U}}, +{CMPA_B0D0,{2U,1U,0U}}, +{CMPA_B0D0,{3U,1U,0U}}, +{CMPA_B0D0,{4U,1U,0U}}, +{CMPA_B0D0,{5U,1U,0U}}, +{CMPA_B0D0,{6U,1U,0U}}, +{CMPA_B0D0,{7U,1U,0U}}, +{CMPA_B0D8,{0U,1U,0U}}, +{CMPA_B0D8,{1U,1U,0U}}, +{CMPA_B0D8,{2U,1U,0U}}, +{CMPA_B0D8,{3U,1U,0U}}, +{CMPA_B0D8,{4U,1U,0U}}, +{CMPA_B0D8,{5U,1U,0U}}, +{CMPA_B0D8,{6U,1U,0U}}, +{CMPA_B0D8,{7U,1U,0U}}, +{CMPA_B0E0,{0U,1U,0U}}, +{CMPA_B0E0,{1U,1U,0U}}, +{CMPA_B0E0,{2U,1U,0U}}, +{CMPA_B0E0,{3U,1U,0U}}, +{CMPA_B0E0,{4U,1U,0U}}, +{CMPA_B0E0,{5U,1U,0U}}, +{CMPA_B0E0,{6U,1U,0U}}, +{CMPA_B0E0,{7U,1U,0U}}, +{CMPA_B0E8,{0U,1U,0U}}, +{CMPA_B0E8,{1U,1U,0U}}, +{CMPA_B0E8,{2U,1U,0U}}, +{CMPA_B0E8,{3U,1U,0U}}, +{CMPA_B0E8,{4U,1U,0U}}, +{CMPA_B0E8,{5U,1U,0U}}, +{CMPA_B0E8,{6U,1U,0U}}, +{CMPA_B0E8,{7U,1U,0U}}, +{CMPA_B0F0,{0U,1U,0U}}, +{CMPA_B0F0,{1U,1U,0U}}, +{CMPA_B0F0,{2U,1U,0U}}, +{CMPA_B0F0,{3U,1U,0U}}, +{CMPA_B0F0,{4U,1U,0U}}, +{CMPA_B0F0,{5U,1U,0U}}, +{CMPA_B0F0,{6U,1U,0U}}, +{CMPA_B0F0,{7U,1U,0U}}, +{CMPA_B0F8,{0U,1U,0U}}, +{CMPA_B0F9,{0U,1U,0U}}, +{CMPA_B0FA,{0U,1U,0U}}, +{CMPA_B0FB,{0U,1U,0U}}, +{CMPA_B0FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B100,{0U,1U,0U}}, +{EOR_B100,{1U,1U,0U}}, +{EOR_B100,{2U,1U,0U}}, +{EOR_B100,{3U,1U,0U}}, +{EOR_B100,{4U,1U,0U}}, +{EOR_B100,{5U,1U,0U}}, +{EOR_B100,{6U,1U,0U}}, +{EOR_B100,{7U,1U,0U}}, +{CMPM_B108,{1U,0U,0U}}, +{CMPM_B108,{1U,1U,0U}}, +{CMPM_B108,{1U,2U,0U}}, +{CMPM_B108,{1U,3U,0U}}, +{CMPM_B108,{1U,4U,0U}}, +{CMPM_B108,{1U,5U,0U}}, +{CMPM_B108,{1U,6U,0U}}, +{CMPM_B108,{1U,7U,0U}}, +{EOR_B110,{0U,1U,0U}}, +{EOR_B110,{1U,1U,0U}}, +{EOR_B110,{2U,1U,0U}}, +{EOR_B110,{3U,1U,0U}}, +{EOR_B110,{4U,1U,0U}}, +{EOR_B110,{5U,1U,0U}}, +{EOR_B110,{6U,1U,0U}}, +{EOR_B110,{7U,1U,0U}}, +{EOR_B118,{0U,1U,0U}}, +{EOR_B118,{1U,1U,0U}}, +{EOR_B118,{2U,1U,0U}}, +{EOR_B118,{3U,1U,0U}}, +{EOR_B118,{4U,1U,0U}}, +{EOR_B118,{5U,1U,0U}}, +{EOR_B118,{6U,1U,0U}}, +{EOR_B118,{7U,1U,0U}}, +{EOR_B120,{0U,1U,0U}}, +{EOR_B120,{1U,1U,0U}}, +{EOR_B120,{2U,1U,0U}}, +{EOR_B120,{3U,1U,0U}}, +{EOR_B120,{4U,1U,0U}}, +{EOR_B120,{5U,1U,0U}}, +{EOR_B120,{6U,1U,0U}}, +{EOR_B120,{7U,1U,0U}}, +{EOR_B128,{0U,1U,0U}}, +{EOR_B128,{1U,1U,0U}}, +{EOR_B128,{2U,1U,0U}}, +{EOR_B128,{3U,1U,0U}}, +{EOR_B128,{4U,1U,0U}}, +{EOR_B128,{5U,1U,0U}}, +{EOR_B128,{6U,1U,0U}}, +{EOR_B128,{7U,1U,0U}}, +{EOR_B130,{0U,1U,0U}}, +{EOR_B130,{1U,1U,0U}}, +{EOR_B130,{2U,1U,0U}}, +{EOR_B130,{3U,1U,0U}}, +{EOR_B130,{4U,1U,0U}}, +{EOR_B130,{5U,1U,0U}}, +{EOR_B130,{6U,1U,0U}}, +{EOR_B130,{7U,1U,0U}}, +{EOR_B138,{0U,1U,0U}}, +{EOR_B139,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B140,{0U,1U,0U}}, +{EOR_B140,{1U,1U,0U}}, +{EOR_B140,{2U,1U,0U}}, +{EOR_B140,{3U,1U,0U}}, +{EOR_B140,{4U,1U,0U}}, +{EOR_B140,{5U,1U,0U}}, +{EOR_B140,{6U,1U,0U}}, +{EOR_B140,{7U,1U,0U}}, +{CMPM_B148,{1U,0U,0U}}, +{CMPM_B148,{1U,1U,0U}}, +{CMPM_B148,{1U,2U,0U}}, +{CMPM_B148,{1U,3U,0U}}, +{CMPM_B148,{1U,4U,0U}}, +{CMPM_B148,{1U,5U,0U}}, +{CMPM_B148,{1U,6U,0U}}, +{CMPM_B148,{1U,7U,0U}}, +{EOR_B150,{0U,1U,0U}}, +{EOR_B150,{1U,1U,0U}}, +{EOR_B150,{2U,1U,0U}}, +{EOR_B150,{3U,1U,0U}}, +{EOR_B150,{4U,1U,0U}}, +{EOR_B150,{5U,1U,0U}}, +{EOR_B150,{6U,1U,0U}}, +{EOR_B150,{7U,1U,0U}}, +{EOR_B158,{0U,1U,0U}}, +{EOR_B158,{1U,1U,0U}}, +{EOR_B158,{2U,1U,0U}}, +{EOR_B158,{3U,1U,0U}}, +{EOR_B158,{4U,1U,0U}}, +{EOR_B158,{5U,1U,0U}}, +{EOR_B158,{6U,1U,0U}}, +{EOR_B158,{7U,1U,0U}}, +{EOR_B160,{0U,1U,0U}}, +{EOR_B160,{1U,1U,0U}}, +{EOR_B160,{2U,1U,0U}}, +{EOR_B160,{3U,1U,0U}}, +{EOR_B160,{4U,1U,0U}}, +{EOR_B160,{5U,1U,0U}}, +{EOR_B160,{6U,1U,0U}}, +{EOR_B160,{7U,1U,0U}}, +{EOR_B168,{0U,1U,0U}}, +{EOR_B168,{1U,1U,0U}}, +{EOR_B168,{2U,1U,0U}}, +{EOR_B168,{3U,1U,0U}}, +{EOR_B168,{4U,1U,0U}}, +{EOR_B168,{5U,1U,0U}}, +{EOR_B168,{6U,1U,0U}}, +{EOR_B168,{7U,1U,0U}}, +{EOR_B170,{0U,1U,0U}}, +{EOR_B170,{1U,1U,0U}}, +{EOR_B170,{2U,1U,0U}}, +{EOR_B170,{3U,1U,0U}}, +{EOR_B170,{4U,1U,0U}}, +{EOR_B170,{5U,1U,0U}}, +{EOR_B170,{6U,1U,0U}}, +{EOR_B170,{7U,1U,0U}}, +{EOR_B178,{0U,1U,0U}}, +{EOR_B179,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B180,{0U,1U,0U}}, +{EOR_B180,{1U,1U,0U}}, +{EOR_B180,{2U,1U,0U}}, +{EOR_B180,{3U,1U,0U}}, +{EOR_B180,{4U,1U,0U}}, +{EOR_B180,{5U,1U,0U}}, +{EOR_B180,{6U,1U,0U}}, +{EOR_B180,{7U,1U,0U}}, +{CMPM_B188,{1U,0U,0U}}, +{CMPM_B188,{1U,1U,0U}}, +{CMPM_B188,{1U,2U,0U}}, +{CMPM_B188,{1U,3U,0U}}, +{CMPM_B188,{1U,4U,0U}}, +{CMPM_B188,{1U,5U,0U}}, +{CMPM_B188,{1U,6U,0U}}, +{CMPM_B188,{1U,7U,0U}}, +{EOR_B190,{0U,1U,0U}}, +{EOR_B190,{1U,1U,0U}}, +{EOR_B190,{2U,1U,0U}}, +{EOR_B190,{3U,1U,0U}}, +{EOR_B190,{4U,1U,0U}}, +{EOR_B190,{5U,1U,0U}}, +{EOR_B190,{6U,1U,0U}}, +{EOR_B190,{7U,1U,0U}}, +{EOR_B198,{0U,1U,0U}}, +{EOR_B198,{1U,1U,0U}}, +{EOR_B198,{2U,1U,0U}}, +{EOR_B198,{3U,1U,0U}}, +{EOR_B198,{4U,1U,0U}}, +{EOR_B198,{5U,1U,0U}}, +{EOR_B198,{6U,1U,0U}}, +{EOR_B198,{7U,1U,0U}}, +{EOR_B1A0,{0U,1U,0U}}, +{EOR_B1A0,{1U,1U,0U}}, +{EOR_B1A0,{2U,1U,0U}}, +{EOR_B1A0,{3U,1U,0U}}, +{EOR_B1A0,{4U,1U,0U}}, +{EOR_B1A0,{5U,1U,0U}}, +{EOR_B1A0,{6U,1U,0U}}, +{EOR_B1A0,{7U,1U,0U}}, +{EOR_B1A8,{0U,1U,0U}}, +{EOR_B1A8,{1U,1U,0U}}, +{EOR_B1A8,{2U,1U,0U}}, +{EOR_B1A8,{3U,1U,0U}}, +{EOR_B1A8,{4U,1U,0U}}, +{EOR_B1A8,{5U,1U,0U}}, +{EOR_B1A8,{6U,1U,0U}}, +{EOR_B1A8,{7U,1U,0U}}, +{EOR_B1B0,{0U,1U,0U}}, +{EOR_B1B0,{1U,1U,0U}}, +{EOR_B1B0,{2U,1U,0U}}, +{EOR_B1B0,{3U,1U,0U}}, +{EOR_B1B0,{4U,1U,0U}}, +{EOR_B1B0,{5U,1U,0U}}, +{EOR_B1B0,{6U,1U,0U}}, +{EOR_B1B0,{7U,1U,0U}}, +{EOR_B1B8,{0U,1U,0U}}, +{EOR_B1B9,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B1C0,{0U,1U,0U}}, +{CMPA_B1C0,{1U,1U,0U}}, +{CMPA_B1C0,{2U,1U,0U}}, +{CMPA_B1C0,{3U,1U,0U}}, +{CMPA_B1C0,{4U,1U,0U}}, +{CMPA_B1C0,{5U,1U,0U}}, +{CMPA_B1C0,{6U,1U,0U}}, +{CMPA_B1C0,{7U,1U,0U}}, +{CMPA_B1C8,{0U,1U,0U}}, +{CMPA_B1C8,{1U,1U,0U}}, +{CMPA_B1C8,{2U,1U,0U}}, +{CMPA_B1C8,{3U,1U,0U}}, +{CMPA_B1C8,{4U,1U,0U}}, +{CMPA_B1C8,{5U,1U,0U}}, +{CMPA_B1C8,{6U,1U,0U}}, +{CMPA_B1C8,{7U,1U,0U}}, +{CMPA_B1D0,{0U,1U,0U}}, +{CMPA_B1D0,{1U,1U,0U}}, +{CMPA_B1D0,{2U,1U,0U}}, +{CMPA_B1D0,{3U,1U,0U}}, +{CMPA_B1D0,{4U,1U,0U}}, +{CMPA_B1D0,{5U,1U,0U}}, +{CMPA_B1D0,{6U,1U,0U}}, +{CMPA_B1D0,{7U,1U,0U}}, +{CMPA_B1D8,{0U,1U,0U}}, +{CMPA_B1D8,{1U,1U,0U}}, +{CMPA_B1D8,{2U,1U,0U}}, +{CMPA_B1D8,{3U,1U,0U}}, +{CMPA_B1D8,{4U,1U,0U}}, +{CMPA_B1D8,{5U,1U,0U}}, +{CMPA_B1D8,{6U,1U,0U}}, +{CMPA_B1D8,{7U,1U,0U}}, +{CMPA_B1E0,{0U,1U,0U}}, +{CMPA_B1E0,{1U,1U,0U}}, +{CMPA_B1E0,{2U,1U,0U}}, +{CMPA_B1E0,{3U,1U,0U}}, +{CMPA_B1E0,{4U,1U,0U}}, +{CMPA_B1E0,{5U,1U,0U}}, +{CMPA_B1E0,{6U,1U,0U}}, +{CMPA_B1E0,{7U,1U,0U}}, +{CMPA_B1E8,{0U,1U,0U}}, +{CMPA_B1E8,{1U,1U,0U}}, +{CMPA_B1E8,{2U,1U,0U}}, +{CMPA_B1E8,{3U,1U,0U}}, +{CMPA_B1E8,{4U,1U,0U}}, +{CMPA_B1E8,{5U,1U,0U}}, +{CMPA_B1E8,{6U,1U,0U}}, +{CMPA_B1E8,{7U,1U,0U}}, +{CMPA_B1F0,{0U,1U,0U}}, +{CMPA_B1F0,{1U,1U,0U}}, +{CMPA_B1F0,{2U,1U,0U}}, +{CMPA_B1F0,{3U,1U,0U}}, +{CMPA_B1F0,{4U,1U,0U}}, +{CMPA_B1F0,{5U,1U,0U}}, +{CMPA_B1F0,{6U,1U,0U}}, +{CMPA_B1F0,{7U,1U,0U}}, +{CMPA_B1F8,{0U,1U,0U}}, +{CMPA_B1F9,{0U,1U,0U}}, +{CMPA_B1FA,{0U,1U,0U}}, +{CMPA_B1FB,{0U,1U,0U}}, +{CMPA_B1FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B000,{0U,2U,0U}}, +{CMP_B000,{1U,2U,0U}}, +{CMP_B000,{2U,2U,0U}}, +{CMP_B000,{3U,2U,0U}}, +{CMP_B000,{4U,2U,0U}}, +{CMP_B000,{5U,2U,0U}}, +{CMP_B000,{6U,2U,0U}}, +{CMP_B000,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B010,{0U,2U,0U}}, +{CMP_B010,{1U,2U,0U}}, +{CMP_B010,{2U,2U,0U}}, +{CMP_B010,{3U,2U,0U}}, +{CMP_B010,{4U,2U,0U}}, +{CMP_B010,{5U,2U,0U}}, +{CMP_B010,{6U,2U,0U}}, +{CMP_B010,{7U,2U,0U}}, +{CMP_B018,{0U,2U,0U}}, +{CMP_B018,{1U,2U,0U}}, +{CMP_B018,{2U,2U,0U}}, +{CMP_B018,{3U,2U,0U}}, +{CMP_B018,{4U,2U,0U}}, +{CMP_B018,{5U,2U,0U}}, +{CMP_B018,{6U,2U,0U}}, +{CMP_B018,{7U,2U,0U}}, +{CMP_B020,{0U,2U,0U}}, +{CMP_B020,{1U,2U,0U}}, +{CMP_B020,{2U,2U,0U}}, +{CMP_B020,{3U,2U,0U}}, +{CMP_B020,{4U,2U,0U}}, +{CMP_B020,{5U,2U,0U}}, +{CMP_B020,{6U,2U,0U}}, +{CMP_B020,{7U,2U,0U}}, +{CMP_B028,{0U,2U,0U}}, +{CMP_B028,{1U,2U,0U}}, +{CMP_B028,{2U,2U,0U}}, +{CMP_B028,{3U,2U,0U}}, +{CMP_B028,{4U,2U,0U}}, +{CMP_B028,{5U,2U,0U}}, +{CMP_B028,{6U,2U,0U}}, +{CMP_B028,{7U,2U,0U}}, +{CMP_B030,{0U,2U,0U}}, +{CMP_B030,{1U,2U,0U}}, +{CMP_B030,{2U,2U,0U}}, +{CMP_B030,{3U,2U,0U}}, +{CMP_B030,{4U,2U,0U}}, +{CMP_B030,{5U,2U,0U}}, +{CMP_B030,{6U,2U,0U}}, +{CMP_B030,{7U,2U,0U}}, +{CMP_B038,{0U,2U,0U}}, +{CMP_B039,{0U,2U,0U}}, +{CMP_B03A,{0U,2U,0U}}, +{CMP_B03B,{0U,2U,0U}}, +{CMP_B03C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B040,{0U,2U,0U}}, +{CMP_B040,{1U,2U,0U}}, +{CMP_B040,{2U,2U,0U}}, +{CMP_B040,{3U,2U,0U}}, +{CMP_B040,{4U,2U,0U}}, +{CMP_B040,{5U,2U,0U}}, +{CMP_B040,{6U,2U,0U}}, +{CMP_B040,{7U,2U,0U}}, +{CMP_B048,{0U,2U,0U}}, +{CMP_B048,{1U,2U,0U}}, +{CMP_B048,{2U,2U,0U}}, +{CMP_B048,{3U,2U,0U}}, +{CMP_B048,{4U,2U,0U}}, +{CMP_B048,{5U,2U,0U}}, +{CMP_B048,{6U,2U,0U}}, +{CMP_B048,{7U,2U,0U}}, +{CMP_B050,{0U,2U,0U}}, +{CMP_B050,{1U,2U,0U}}, +{CMP_B050,{2U,2U,0U}}, +{CMP_B050,{3U,2U,0U}}, +{CMP_B050,{4U,2U,0U}}, +{CMP_B050,{5U,2U,0U}}, +{CMP_B050,{6U,2U,0U}}, +{CMP_B050,{7U,2U,0U}}, +{CMP_B058,{0U,2U,0U}}, +{CMP_B058,{1U,2U,0U}}, +{CMP_B058,{2U,2U,0U}}, +{CMP_B058,{3U,2U,0U}}, +{CMP_B058,{4U,2U,0U}}, +{CMP_B058,{5U,2U,0U}}, +{CMP_B058,{6U,2U,0U}}, +{CMP_B058,{7U,2U,0U}}, +{CMP_B060,{0U,2U,0U}}, +{CMP_B060,{1U,2U,0U}}, +{CMP_B060,{2U,2U,0U}}, +{CMP_B060,{3U,2U,0U}}, +{CMP_B060,{4U,2U,0U}}, +{CMP_B060,{5U,2U,0U}}, +{CMP_B060,{6U,2U,0U}}, +{CMP_B060,{7U,2U,0U}}, +{CMP_B068,{0U,2U,0U}}, +{CMP_B068,{1U,2U,0U}}, +{CMP_B068,{2U,2U,0U}}, +{CMP_B068,{3U,2U,0U}}, +{CMP_B068,{4U,2U,0U}}, +{CMP_B068,{5U,2U,0U}}, +{CMP_B068,{6U,2U,0U}}, +{CMP_B068,{7U,2U,0U}}, +{CMP_B070,{0U,2U,0U}}, +{CMP_B070,{1U,2U,0U}}, +{CMP_B070,{2U,2U,0U}}, +{CMP_B070,{3U,2U,0U}}, +{CMP_B070,{4U,2U,0U}}, +{CMP_B070,{5U,2U,0U}}, +{CMP_B070,{6U,2U,0U}}, +{CMP_B070,{7U,2U,0U}}, +{CMP_B078,{0U,2U,0U}}, +{CMP_B079,{0U,2U,0U}}, +{CMP_B07A,{0U,2U,0U}}, +{CMP_B07B,{0U,2U,0U}}, +{CMP_B07C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B080,{0U,2U,0U}}, +{CMP_B080,{1U,2U,0U}}, +{CMP_B080,{2U,2U,0U}}, +{CMP_B080,{3U,2U,0U}}, +{CMP_B080,{4U,2U,0U}}, +{CMP_B080,{5U,2U,0U}}, +{CMP_B080,{6U,2U,0U}}, +{CMP_B080,{7U,2U,0U}}, +{CMP_B088,{0U,2U,0U}}, +{CMP_B088,{1U,2U,0U}}, +{CMP_B088,{2U,2U,0U}}, +{CMP_B088,{3U,2U,0U}}, +{CMP_B088,{4U,2U,0U}}, +{CMP_B088,{5U,2U,0U}}, +{CMP_B088,{6U,2U,0U}}, +{CMP_B088,{7U,2U,0U}}, +{CMP_B090,{0U,2U,0U}}, +{CMP_B090,{1U,2U,0U}}, +{CMP_B090,{2U,2U,0U}}, +{CMP_B090,{3U,2U,0U}}, +{CMP_B090,{4U,2U,0U}}, +{CMP_B090,{5U,2U,0U}}, +{CMP_B090,{6U,2U,0U}}, +{CMP_B090,{7U,2U,0U}}, +{CMP_B098,{0U,2U,0U}}, +{CMP_B098,{1U,2U,0U}}, +{CMP_B098,{2U,2U,0U}}, +{CMP_B098,{3U,2U,0U}}, +{CMP_B098,{4U,2U,0U}}, +{CMP_B098,{5U,2U,0U}}, +{CMP_B098,{6U,2U,0U}}, +{CMP_B098,{7U,2U,0U}}, +{CMP_B0A0,{0U,2U,0U}}, +{CMP_B0A0,{1U,2U,0U}}, +{CMP_B0A0,{2U,2U,0U}}, +{CMP_B0A0,{3U,2U,0U}}, +{CMP_B0A0,{4U,2U,0U}}, +{CMP_B0A0,{5U,2U,0U}}, +{CMP_B0A0,{6U,2U,0U}}, +{CMP_B0A0,{7U,2U,0U}}, +{CMP_B0A8,{0U,2U,0U}}, +{CMP_B0A8,{1U,2U,0U}}, +{CMP_B0A8,{2U,2U,0U}}, +{CMP_B0A8,{3U,2U,0U}}, +{CMP_B0A8,{4U,2U,0U}}, +{CMP_B0A8,{5U,2U,0U}}, +{CMP_B0A8,{6U,2U,0U}}, +{CMP_B0A8,{7U,2U,0U}}, +{CMP_B0B0,{0U,2U,0U}}, +{CMP_B0B0,{1U,2U,0U}}, +{CMP_B0B0,{2U,2U,0U}}, +{CMP_B0B0,{3U,2U,0U}}, +{CMP_B0B0,{4U,2U,0U}}, +{CMP_B0B0,{5U,2U,0U}}, +{CMP_B0B0,{6U,2U,0U}}, +{CMP_B0B0,{7U,2U,0U}}, +{CMP_B0B8,{0U,2U,0U}}, +{CMP_B0B9,{0U,2U,0U}}, +{CMP_B0BA,{0U,2U,0U}}, +{CMP_B0BB,{0U,2U,0U}}, +{CMP_B0BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B0C0,{0U,2U,0U}}, +{CMPA_B0C0,{1U,2U,0U}}, +{CMPA_B0C0,{2U,2U,0U}}, +{CMPA_B0C0,{3U,2U,0U}}, +{CMPA_B0C0,{4U,2U,0U}}, +{CMPA_B0C0,{5U,2U,0U}}, +{CMPA_B0C0,{6U,2U,0U}}, +{CMPA_B0C0,{7U,2U,0U}}, +{CMPA_B0C8,{0U,2U,0U}}, +{CMPA_B0C8,{1U,2U,0U}}, +{CMPA_B0C8,{2U,2U,0U}}, +{CMPA_B0C8,{3U,2U,0U}}, +{CMPA_B0C8,{4U,2U,0U}}, +{CMPA_B0C8,{5U,2U,0U}}, +{CMPA_B0C8,{6U,2U,0U}}, +{CMPA_B0C8,{7U,2U,0U}}, +{CMPA_B0D0,{0U,2U,0U}}, +{CMPA_B0D0,{1U,2U,0U}}, +{CMPA_B0D0,{2U,2U,0U}}, +{CMPA_B0D0,{3U,2U,0U}}, +{CMPA_B0D0,{4U,2U,0U}}, +{CMPA_B0D0,{5U,2U,0U}}, +{CMPA_B0D0,{6U,2U,0U}}, +{CMPA_B0D0,{7U,2U,0U}}, +{CMPA_B0D8,{0U,2U,0U}}, +{CMPA_B0D8,{1U,2U,0U}}, +{CMPA_B0D8,{2U,2U,0U}}, +{CMPA_B0D8,{3U,2U,0U}}, +{CMPA_B0D8,{4U,2U,0U}}, +{CMPA_B0D8,{5U,2U,0U}}, +{CMPA_B0D8,{6U,2U,0U}}, +{CMPA_B0D8,{7U,2U,0U}}, +{CMPA_B0E0,{0U,2U,0U}}, +{CMPA_B0E0,{1U,2U,0U}}, +{CMPA_B0E0,{2U,2U,0U}}, +{CMPA_B0E0,{3U,2U,0U}}, +{CMPA_B0E0,{4U,2U,0U}}, +{CMPA_B0E0,{5U,2U,0U}}, +{CMPA_B0E0,{6U,2U,0U}}, +{CMPA_B0E0,{7U,2U,0U}}, +{CMPA_B0E8,{0U,2U,0U}}, +{CMPA_B0E8,{1U,2U,0U}}, +{CMPA_B0E8,{2U,2U,0U}}, +{CMPA_B0E8,{3U,2U,0U}}, +{CMPA_B0E8,{4U,2U,0U}}, +{CMPA_B0E8,{5U,2U,0U}}, +{CMPA_B0E8,{6U,2U,0U}}, +{CMPA_B0E8,{7U,2U,0U}}, +{CMPA_B0F0,{0U,2U,0U}}, +{CMPA_B0F0,{1U,2U,0U}}, +{CMPA_B0F0,{2U,2U,0U}}, +{CMPA_B0F0,{3U,2U,0U}}, +{CMPA_B0F0,{4U,2U,0U}}, +{CMPA_B0F0,{5U,2U,0U}}, +{CMPA_B0F0,{6U,2U,0U}}, +{CMPA_B0F0,{7U,2U,0U}}, +{CMPA_B0F8,{0U,2U,0U}}, +{CMPA_B0F9,{0U,2U,0U}}, +{CMPA_B0FA,{0U,2U,0U}}, +{CMPA_B0FB,{0U,2U,0U}}, +{CMPA_B0FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B100,{0U,2U,0U}}, +{EOR_B100,{1U,2U,0U}}, +{EOR_B100,{2U,2U,0U}}, +{EOR_B100,{3U,2U,0U}}, +{EOR_B100,{4U,2U,0U}}, +{EOR_B100,{5U,2U,0U}}, +{EOR_B100,{6U,2U,0U}}, +{EOR_B100,{7U,2U,0U}}, +{CMPM_B108,{2U,0U,0U}}, +{CMPM_B108,{2U,1U,0U}}, +{CMPM_B108,{2U,2U,0U}}, +{CMPM_B108,{2U,3U,0U}}, +{CMPM_B108,{2U,4U,0U}}, +{CMPM_B108,{2U,5U,0U}}, +{CMPM_B108,{2U,6U,0U}}, +{CMPM_B108,{2U,7U,0U}}, +{EOR_B110,{0U,2U,0U}}, +{EOR_B110,{1U,2U,0U}}, +{EOR_B110,{2U,2U,0U}}, +{EOR_B110,{3U,2U,0U}}, +{EOR_B110,{4U,2U,0U}}, +{EOR_B110,{5U,2U,0U}}, +{EOR_B110,{6U,2U,0U}}, +{EOR_B110,{7U,2U,0U}}, +{EOR_B118,{0U,2U,0U}}, +{EOR_B118,{1U,2U,0U}}, +{EOR_B118,{2U,2U,0U}}, +{EOR_B118,{3U,2U,0U}}, +{EOR_B118,{4U,2U,0U}}, +{EOR_B118,{5U,2U,0U}}, +{EOR_B118,{6U,2U,0U}}, +{EOR_B118,{7U,2U,0U}}, +{EOR_B120,{0U,2U,0U}}, +{EOR_B120,{1U,2U,0U}}, +{EOR_B120,{2U,2U,0U}}, +{EOR_B120,{3U,2U,0U}}, +{EOR_B120,{4U,2U,0U}}, +{EOR_B120,{5U,2U,0U}}, +{EOR_B120,{6U,2U,0U}}, +{EOR_B120,{7U,2U,0U}}, +{EOR_B128,{0U,2U,0U}}, +{EOR_B128,{1U,2U,0U}}, +{EOR_B128,{2U,2U,0U}}, +{EOR_B128,{3U,2U,0U}}, +{EOR_B128,{4U,2U,0U}}, +{EOR_B128,{5U,2U,0U}}, +{EOR_B128,{6U,2U,0U}}, +{EOR_B128,{7U,2U,0U}}, +{EOR_B130,{0U,2U,0U}}, +{EOR_B130,{1U,2U,0U}}, +{EOR_B130,{2U,2U,0U}}, +{EOR_B130,{3U,2U,0U}}, +{EOR_B130,{4U,2U,0U}}, +{EOR_B130,{5U,2U,0U}}, +{EOR_B130,{6U,2U,0U}}, +{EOR_B130,{7U,2U,0U}}, +{EOR_B138,{0U,2U,0U}}, +{EOR_B139,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B140,{0U,2U,0U}}, +{EOR_B140,{1U,2U,0U}}, +{EOR_B140,{2U,2U,0U}}, +{EOR_B140,{3U,2U,0U}}, +{EOR_B140,{4U,2U,0U}}, +{EOR_B140,{5U,2U,0U}}, +{EOR_B140,{6U,2U,0U}}, +{EOR_B140,{7U,2U,0U}}, +{CMPM_B148,{2U,0U,0U}}, +{CMPM_B148,{2U,1U,0U}}, +{CMPM_B148,{2U,2U,0U}}, +{CMPM_B148,{2U,3U,0U}}, +{CMPM_B148,{2U,4U,0U}}, +{CMPM_B148,{2U,5U,0U}}, +{CMPM_B148,{2U,6U,0U}}, +{CMPM_B148,{2U,7U,0U}}, +{EOR_B150,{0U,2U,0U}}, +{EOR_B150,{1U,2U,0U}}, +{EOR_B150,{2U,2U,0U}}, +{EOR_B150,{3U,2U,0U}}, +{EOR_B150,{4U,2U,0U}}, +{EOR_B150,{5U,2U,0U}}, +{EOR_B150,{6U,2U,0U}}, +{EOR_B150,{7U,2U,0U}}, +{EOR_B158,{0U,2U,0U}}, +{EOR_B158,{1U,2U,0U}}, +{EOR_B158,{2U,2U,0U}}, +{EOR_B158,{3U,2U,0U}}, +{EOR_B158,{4U,2U,0U}}, +{EOR_B158,{5U,2U,0U}}, +{EOR_B158,{6U,2U,0U}}, +{EOR_B158,{7U,2U,0U}}, +{EOR_B160,{0U,2U,0U}}, +{EOR_B160,{1U,2U,0U}}, +{EOR_B160,{2U,2U,0U}}, +{EOR_B160,{3U,2U,0U}}, +{EOR_B160,{4U,2U,0U}}, +{EOR_B160,{5U,2U,0U}}, +{EOR_B160,{6U,2U,0U}}, +{EOR_B160,{7U,2U,0U}}, +{EOR_B168,{0U,2U,0U}}, +{EOR_B168,{1U,2U,0U}}, +{EOR_B168,{2U,2U,0U}}, +{EOR_B168,{3U,2U,0U}}, +{EOR_B168,{4U,2U,0U}}, +{EOR_B168,{5U,2U,0U}}, +{EOR_B168,{6U,2U,0U}}, +{EOR_B168,{7U,2U,0U}}, +{EOR_B170,{0U,2U,0U}}, +{EOR_B170,{1U,2U,0U}}, +{EOR_B170,{2U,2U,0U}}, +{EOR_B170,{3U,2U,0U}}, +{EOR_B170,{4U,2U,0U}}, +{EOR_B170,{5U,2U,0U}}, +{EOR_B170,{6U,2U,0U}}, +{EOR_B170,{7U,2U,0U}}, +{EOR_B178,{0U,2U,0U}}, +{EOR_B179,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B180,{0U,2U,0U}}, +{EOR_B180,{1U,2U,0U}}, +{EOR_B180,{2U,2U,0U}}, +{EOR_B180,{3U,2U,0U}}, +{EOR_B180,{4U,2U,0U}}, +{EOR_B180,{5U,2U,0U}}, +{EOR_B180,{6U,2U,0U}}, +{EOR_B180,{7U,2U,0U}}, +{CMPM_B188,{2U,0U,0U}}, +{CMPM_B188,{2U,1U,0U}}, +{CMPM_B188,{2U,2U,0U}}, +{CMPM_B188,{2U,3U,0U}}, +{CMPM_B188,{2U,4U,0U}}, +{CMPM_B188,{2U,5U,0U}}, +{CMPM_B188,{2U,6U,0U}}, +{CMPM_B188,{2U,7U,0U}}, +{EOR_B190,{0U,2U,0U}}, +{EOR_B190,{1U,2U,0U}}, +{EOR_B190,{2U,2U,0U}}, +{EOR_B190,{3U,2U,0U}}, +{EOR_B190,{4U,2U,0U}}, +{EOR_B190,{5U,2U,0U}}, +{EOR_B190,{6U,2U,0U}}, +{EOR_B190,{7U,2U,0U}}, +{EOR_B198,{0U,2U,0U}}, +{EOR_B198,{1U,2U,0U}}, +{EOR_B198,{2U,2U,0U}}, +{EOR_B198,{3U,2U,0U}}, +{EOR_B198,{4U,2U,0U}}, +{EOR_B198,{5U,2U,0U}}, +{EOR_B198,{6U,2U,0U}}, +{EOR_B198,{7U,2U,0U}}, +{EOR_B1A0,{0U,2U,0U}}, +{EOR_B1A0,{1U,2U,0U}}, +{EOR_B1A0,{2U,2U,0U}}, +{EOR_B1A0,{3U,2U,0U}}, +{EOR_B1A0,{4U,2U,0U}}, +{EOR_B1A0,{5U,2U,0U}}, +{EOR_B1A0,{6U,2U,0U}}, +{EOR_B1A0,{7U,2U,0U}}, +{EOR_B1A8,{0U,2U,0U}}, +{EOR_B1A8,{1U,2U,0U}}, +{EOR_B1A8,{2U,2U,0U}}, +{EOR_B1A8,{3U,2U,0U}}, +{EOR_B1A8,{4U,2U,0U}}, +{EOR_B1A8,{5U,2U,0U}}, +{EOR_B1A8,{6U,2U,0U}}, +{EOR_B1A8,{7U,2U,0U}}, +{EOR_B1B0,{0U,2U,0U}}, +{EOR_B1B0,{1U,2U,0U}}, +{EOR_B1B0,{2U,2U,0U}}, +{EOR_B1B0,{3U,2U,0U}}, +{EOR_B1B0,{4U,2U,0U}}, +{EOR_B1B0,{5U,2U,0U}}, +{EOR_B1B0,{6U,2U,0U}}, +{EOR_B1B0,{7U,2U,0U}}, +{EOR_B1B8,{0U,2U,0U}}, +{EOR_B1B9,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B1C0,{0U,2U,0U}}, +{CMPA_B1C0,{1U,2U,0U}}, +{CMPA_B1C0,{2U,2U,0U}}, +{CMPA_B1C0,{3U,2U,0U}}, +{CMPA_B1C0,{4U,2U,0U}}, +{CMPA_B1C0,{5U,2U,0U}}, +{CMPA_B1C0,{6U,2U,0U}}, +{CMPA_B1C0,{7U,2U,0U}}, +{CMPA_B1C8,{0U,2U,0U}}, +{CMPA_B1C8,{1U,2U,0U}}, +{CMPA_B1C8,{2U,2U,0U}}, +{CMPA_B1C8,{3U,2U,0U}}, +{CMPA_B1C8,{4U,2U,0U}}, +{CMPA_B1C8,{5U,2U,0U}}, +{CMPA_B1C8,{6U,2U,0U}}, +{CMPA_B1C8,{7U,2U,0U}}, +{CMPA_B1D0,{0U,2U,0U}}, +{CMPA_B1D0,{1U,2U,0U}}, +{CMPA_B1D0,{2U,2U,0U}}, +{CMPA_B1D0,{3U,2U,0U}}, +{CMPA_B1D0,{4U,2U,0U}}, +{CMPA_B1D0,{5U,2U,0U}}, +{CMPA_B1D0,{6U,2U,0U}}, +{CMPA_B1D0,{7U,2U,0U}}, +{CMPA_B1D8,{0U,2U,0U}}, +{CMPA_B1D8,{1U,2U,0U}}, +{CMPA_B1D8,{2U,2U,0U}}, +{CMPA_B1D8,{3U,2U,0U}}, +{CMPA_B1D8,{4U,2U,0U}}, +{CMPA_B1D8,{5U,2U,0U}}, +{CMPA_B1D8,{6U,2U,0U}}, +{CMPA_B1D8,{7U,2U,0U}}, +{CMPA_B1E0,{0U,2U,0U}}, +{CMPA_B1E0,{1U,2U,0U}}, +{CMPA_B1E0,{2U,2U,0U}}, +{CMPA_B1E0,{3U,2U,0U}}, +{CMPA_B1E0,{4U,2U,0U}}, +{CMPA_B1E0,{5U,2U,0U}}, +{CMPA_B1E0,{6U,2U,0U}}, +{CMPA_B1E0,{7U,2U,0U}}, +{CMPA_B1E8,{0U,2U,0U}}, +{CMPA_B1E8,{1U,2U,0U}}, +{CMPA_B1E8,{2U,2U,0U}}, +{CMPA_B1E8,{3U,2U,0U}}, +{CMPA_B1E8,{4U,2U,0U}}, +{CMPA_B1E8,{5U,2U,0U}}, +{CMPA_B1E8,{6U,2U,0U}}, +{CMPA_B1E8,{7U,2U,0U}}, +{CMPA_B1F0,{0U,2U,0U}}, +{CMPA_B1F0,{1U,2U,0U}}, +{CMPA_B1F0,{2U,2U,0U}}, +{CMPA_B1F0,{3U,2U,0U}}, +{CMPA_B1F0,{4U,2U,0U}}, +{CMPA_B1F0,{5U,2U,0U}}, +{CMPA_B1F0,{6U,2U,0U}}, +{CMPA_B1F0,{7U,2U,0U}}, +{CMPA_B1F8,{0U,2U,0U}}, +{CMPA_B1F9,{0U,2U,0U}}, +{CMPA_B1FA,{0U,2U,0U}}, +{CMPA_B1FB,{0U,2U,0U}}, +{CMPA_B1FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B000,{0U,3U,0U}}, +{CMP_B000,{1U,3U,0U}}, +{CMP_B000,{2U,3U,0U}}, +{CMP_B000,{3U,3U,0U}}, +{CMP_B000,{4U,3U,0U}}, +{CMP_B000,{5U,3U,0U}}, +{CMP_B000,{6U,3U,0U}}, +{CMP_B000,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B010,{0U,3U,0U}}, +{CMP_B010,{1U,3U,0U}}, +{CMP_B010,{2U,3U,0U}}, +{CMP_B010,{3U,3U,0U}}, +{CMP_B010,{4U,3U,0U}}, +{CMP_B010,{5U,3U,0U}}, +{CMP_B010,{6U,3U,0U}}, +{CMP_B010,{7U,3U,0U}}, +{CMP_B018,{0U,3U,0U}}, +{CMP_B018,{1U,3U,0U}}, +{CMP_B018,{2U,3U,0U}}, +{CMP_B018,{3U,3U,0U}}, +{CMP_B018,{4U,3U,0U}}, +{CMP_B018,{5U,3U,0U}}, +{CMP_B018,{6U,3U,0U}}, +{CMP_B018,{7U,3U,0U}}, +{CMP_B020,{0U,3U,0U}}, +{CMP_B020,{1U,3U,0U}}, +{CMP_B020,{2U,3U,0U}}, +{CMP_B020,{3U,3U,0U}}, +{CMP_B020,{4U,3U,0U}}, +{CMP_B020,{5U,3U,0U}}, +{CMP_B020,{6U,3U,0U}}, +{CMP_B020,{7U,3U,0U}}, +{CMP_B028,{0U,3U,0U}}, +{CMP_B028,{1U,3U,0U}}, +{CMP_B028,{2U,3U,0U}}, +{CMP_B028,{3U,3U,0U}}, +{CMP_B028,{4U,3U,0U}}, +{CMP_B028,{5U,3U,0U}}, +{CMP_B028,{6U,3U,0U}}, +{CMP_B028,{7U,3U,0U}}, +{CMP_B030,{0U,3U,0U}}, +{CMP_B030,{1U,3U,0U}}, +{CMP_B030,{2U,3U,0U}}, +{CMP_B030,{3U,3U,0U}}, +{CMP_B030,{4U,3U,0U}}, +{CMP_B030,{5U,3U,0U}}, +{CMP_B030,{6U,3U,0U}}, +{CMP_B030,{7U,3U,0U}}, +{CMP_B038,{0U,3U,0U}}, +{CMP_B039,{0U,3U,0U}}, +{CMP_B03A,{0U,3U,0U}}, +{CMP_B03B,{0U,3U,0U}}, +{CMP_B03C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B040,{0U,3U,0U}}, +{CMP_B040,{1U,3U,0U}}, +{CMP_B040,{2U,3U,0U}}, +{CMP_B040,{3U,3U,0U}}, +{CMP_B040,{4U,3U,0U}}, +{CMP_B040,{5U,3U,0U}}, +{CMP_B040,{6U,3U,0U}}, +{CMP_B040,{7U,3U,0U}}, +{CMP_B048,{0U,3U,0U}}, +{CMP_B048,{1U,3U,0U}}, +{CMP_B048,{2U,3U,0U}}, +{CMP_B048,{3U,3U,0U}}, +{CMP_B048,{4U,3U,0U}}, +{CMP_B048,{5U,3U,0U}}, +{CMP_B048,{6U,3U,0U}}, +{CMP_B048,{7U,3U,0U}}, +{CMP_B050,{0U,3U,0U}}, +{CMP_B050,{1U,3U,0U}}, +{CMP_B050,{2U,3U,0U}}, +{CMP_B050,{3U,3U,0U}}, +{CMP_B050,{4U,3U,0U}}, +{CMP_B050,{5U,3U,0U}}, +{CMP_B050,{6U,3U,0U}}, +{CMP_B050,{7U,3U,0U}}, +{CMP_B058,{0U,3U,0U}}, +{CMP_B058,{1U,3U,0U}}, +{CMP_B058,{2U,3U,0U}}, +{CMP_B058,{3U,3U,0U}}, +{CMP_B058,{4U,3U,0U}}, +{CMP_B058,{5U,3U,0U}}, +{CMP_B058,{6U,3U,0U}}, +{CMP_B058,{7U,3U,0U}}, +{CMP_B060,{0U,3U,0U}}, +{CMP_B060,{1U,3U,0U}}, +{CMP_B060,{2U,3U,0U}}, +{CMP_B060,{3U,3U,0U}}, +{CMP_B060,{4U,3U,0U}}, +{CMP_B060,{5U,3U,0U}}, +{CMP_B060,{6U,3U,0U}}, +{CMP_B060,{7U,3U,0U}}, +{CMP_B068,{0U,3U,0U}}, +{CMP_B068,{1U,3U,0U}}, +{CMP_B068,{2U,3U,0U}}, +{CMP_B068,{3U,3U,0U}}, +{CMP_B068,{4U,3U,0U}}, +{CMP_B068,{5U,3U,0U}}, +{CMP_B068,{6U,3U,0U}}, +{CMP_B068,{7U,3U,0U}}, +{CMP_B070,{0U,3U,0U}}, +{CMP_B070,{1U,3U,0U}}, +{CMP_B070,{2U,3U,0U}}, +{CMP_B070,{3U,3U,0U}}, +{CMP_B070,{4U,3U,0U}}, +{CMP_B070,{5U,3U,0U}}, +{CMP_B070,{6U,3U,0U}}, +{CMP_B070,{7U,3U,0U}}, +{CMP_B078,{0U,3U,0U}}, +{CMP_B079,{0U,3U,0U}}, +{CMP_B07A,{0U,3U,0U}}, +{CMP_B07B,{0U,3U,0U}}, +{CMP_B07C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B080,{0U,3U,0U}}, +{CMP_B080,{1U,3U,0U}}, +{CMP_B080,{2U,3U,0U}}, +{CMP_B080,{3U,3U,0U}}, +{CMP_B080,{4U,3U,0U}}, +{CMP_B080,{5U,3U,0U}}, +{CMP_B080,{6U,3U,0U}}, +{CMP_B080,{7U,3U,0U}}, +{CMP_B088,{0U,3U,0U}}, +{CMP_B088,{1U,3U,0U}}, +{CMP_B088,{2U,3U,0U}}, +{CMP_B088,{3U,3U,0U}}, +{CMP_B088,{4U,3U,0U}}, +{CMP_B088,{5U,3U,0U}}, +{CMP_B088,{6U,3U,0U}}, +{CMP_B088,{7U,3U,0U}}, +{CMP_B090,{0U,3U,0U}}, +{CMP_B090,{1U,3U,0U}}, +{CMP_B090,{2U,3U,0U}}, +{CMP_B090,{3U,3U,0U}}, +{CMP_B090,{4U,3U,0U}}, +{CMP_B090,{5U,3U,0U}}, +{CMP_B090,{6U,3U,0U}}, +{CMP_B090,{7U,3U,0U}}, +{CMP_B098,{0U,3U,0U}}, +{CMP_B098,{1U,3U,0U}}, +{CMP_B098,{2U,3U,0U}}, +{CMP_B098,{3U,3U,0U}}, +{CMP_B098,{4U,3U,0U}}, +{CMP_B098,{5U,3U,0U}}, +{CMP_B098,{6U,3U,0U}}, +{CMP_B098,{7U,3U,0U}}, +{CMP_B0A0,{0U,3U,0U}}, +{CMP_B0A0,{1U,3U,0U}}, +{CMP_B0A0,{2U,3U,0U}}, +{CMP_B0A0,{3U,3U,0U}}, +{CMP_B0A0,{4U,3U,0U}}, +{CMP_B0A0,{5U,3U,0U}}, +{CMP_B0A0,{6U,3U,0U}}, +{CMP_B0A0,{7U,3U,0U}}, +{CMP_B0A8,{0U,3U,0U}}, +{CMP_B0A8,{1U,3U,0U}}, +{CMP_B0A8,{2U,3U,0U}}, +{CMP_B0A8,{3U,3U,0U}}, +{CMP_B0A8,{4U,3U,0U}}, +{CMP_B0A8,{5U,3U,0U}}, +{CMP_B0A8,{6U,3U,0U}}, +{CMP_B0A8,{7U,3U,0U}}, +{CMP_B0B0,{0U,3U,0U}}, +{CMP_B0B0,{1U,3U,0U}}, +{CMP_B0B0,{2U,3U,0U}}, +{CMP_B0B0,{3U,3U,0U}}, +{CMP_B0B0,{4U,3U,0U}}, +{CMP_B0B0,{5U,3U,0U}}, +{CMP_B0B0,{6U,3U,0U}}, +{CMP_B0B0,{7U,3U,0U}}, +{CMP_B0B8,{0U,3U,0U}}, +{CMP_B0B9,{0U,3U,0U}}, +{CMP_B0BA,{0U,3U,0U}}, +{CMP_B0BB,{0U,3U,0U}}, +{CMP_B0BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B0C0,{0U,3U,0U}}, +{CMPA_B0C0,{1U,3U,0U}}, +{CMPA_B0C0,{2U,3U,0U}}, +{CMPA_B0C0,{3U,3U,0U}}, +{CMPA_B0C0,{4U,3U,0U}}, +{CMPA_B0C0,{5U,3U,0U}}, +{CMPA_B0C0,{6U,3U,0U}}, +{CMPA_B0C0,{7U,3U,0U}}, +{CMPA_B0C8,{0U,3U,0U}}, +{CMPA_B0C8,{1U,3U,0U}}, +{CMPA_B0C8,{2U,3U,0U}}, +{CMPA_B0C8,{3U,3U,0U}}, +{CMPA_B0C8,{4U,3U,0U}}, +{CMPA_B0C8,{5U,3U,0U}}, +{CMPA_B0C8,{6U,3U,0U}}, +{CMPA_B0C8,{7U,3U,0U}}, +{CMPA_B0D0,{0U,3U,0U}}, +{CMPA_B0D0,{1U,3U,0U}}, +{CMPA_B0D0,{2U,3U,0U}}, +{CMPA_B0D0,{3U,3U,0U}}, +{CMPA_B0D0,{4U,3U,0U}}, +{CMPA_B0D0,{5U,3U,0U}}, +{CMPA_B0D0,{6U,3U,0U}}, +{CMPA_B0D0,{7U,3U,0U}}, +{CMPA_B0D8,{0U,3U,0U}}, +{CMPA_B0D8,{1U,3U,0U}}, +{CMPA_B0D8,{2U,3U,0U}}, +{CMPA_B0D8,{3U,3U,0U}}, +{CMPA_B0D8,{4U,3U,0U}}, +{CMPA_B0D8,{5U,3U,0U}}, +{CMPA_B0D8,{6U,3U,0U}}, +{CMPA_B0D8,{7U,3U,0U}}, +{CMPA_B0E0,{0U,3U,0U}}, +{CMPA_B0E0,{1U,3U,0U}}, +{CMPA_B0E0,{2U,3U,0U}}, +{CMPA_B0E0,{3U,3U,0U}}, +{CMPA_B0E0,{4U,3U,0U}}, +{CMPA_B0E0,{5U,3U,0U}}, +{CMPA_B0E0,{6U,3U,0U}}, +{CMPA_B0E0,{7U,3U,0U}}, +{CMPA_B0E8,{0U,3U,0U}}, +{CMPA_B0E8,{1U,3U,0U}}, +{CMPA_B0E8,{2U,3U,0U}}, +{CMPA_B0E8,{3U,3U,0U}}, +{CMPA_B0E8,{4U,3U,0U}}, +{CMPA_B0E8,{5U,3U,0U}}, +{CMPA_B0E8,{6U,3U,0U}}, +{CMPA_B0E8,{7U,3U,0U}}, +{CMPA_B0F0,{0U,3U,0U}}, +{CMPA_B0F0,{1U,3U,0U}}, +{CMPA_B0F0,{2U,3U,0U}}, +{CMPA_B0F0,{3U,3U,0U}}, +{CMPA_B0F0,{4U,3U,0U}}, +{CMPA_B0F0,{5U,3U,0U}}, +{CMPA_B0F0,{6U,3U,0U}}, +{CMPA_B0F0,{7U,3U,0U}}, +{CMPA_B0F8,{0U,3U,0U}}, +{CMPA_B0F9,{0U,3U,0U}}, +{CMPA_B0FA,{0U,3U,0U}}, +{CMPA_B0FB,{0U,3U,0U}}, +{CMPA_B0FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B100,{0U,3U,0U}}, +{EOR_B100,{1U,3U,0U}}, +{EOR_B100,{2U,3U,0U}}, +{EOR_B100,{3U,3U,0U}}, +{EOR_B100,{4U,3U,0U}}, +{EOR_B100,{5U,3U,0U}}, +{EOR_B100,{6U,3U,0U}}, +{EOR_B100,{7U,3U,0U}}, +{CMPM_B108,{3U,0U,0U}}, +{CMPM_B108,{3U,1U,0U}}, +{CMPM_B108,{3U,2U,0U}}, +{CMPM_B108,{3U,3U,0U}}, +{CMPM_B108,{3U,4U,0U}}, +{CMPM_B108,{3U,5U,0U}}, +{CMPM_B108,{3U,6U,0U}}, +{CMPM_B108,{3U,7U,0U}}, +{EOR_B110,{0U,3U,0U}}, +{EOR_B110,{1U,3U,0U}}, +{EOR_B110,{2U,3U,0U}}, +{EOR_B110,{3U,3U,0U}}, +{EOR_B110,{4U,3U,0U}}, +{EOR_B110,{5U,3U,0U}}, +{EOR_B110,{6U,3U,0U}}, +{EOR_B110,{7U,3U,0U}}, +{EOR_B118,{0U,3U,0U}}, +{EOR_B118,{1U,3U,0U}}, +{EOR_B118,{2U,3U,0U}}, +{EOR_B118,{3U,3U,0U}}, +{EOR_B118,{4U,3U,0U}}, +{EOR_B118,{5U,3U,0U}}, +{EOR_B118,{6U,3U,0U}}, +{EOR_B118,{7U,3U,0U}}, +{EOR_B120,{0U,3U,0U}}, +{EOR_B120,{1U,3U,0U}}, +{EOR_B120,{2U,3U,0U}}, +{EOR_B120,{3U,3U,0U}}, +{EOR_B120,{4U,3U,0U}}, +{EOR_B120,{5U,3U,0U}}, +{EOR_B120,{6U,3U,0U}}, +{EOR_B120,{7U,3U,0U}}, +{EOR_B128,{0U,3U,0U}}, +{EOR_B128,{1U,3U,0U}}, +{EOR_B128,{2U,3U,0U}}, +{EOR_B128,{3U,3U,0U}}, +{EOR_B128,{4U,3U,0U}}, +{EOR_B128,{5U,3U,0U}}, +{EOR_B128,{6U,3U,0U}}, +{EOR_B128,{7U,3U,0U}}, +{EOR_B130,{0U,3U,0U}}, +{EOR_B130,{1U,3U,0U}}, +{EOR_B130,{2U,3U,0U}}, +{EOR_B130,{3U,3U,0U}}, +{EOR_B130,{4U,3U,0U}}, +{EOR_B130,{5U,3U,0U}}, +{EOR_B130,{6U,3U,0U}}, +{EOR_B130,{7U,3U,0U}}, +{EOR_B138,{0U,3U,0U}}, +{EOR_B139,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B140,{0U,3U,0U}}, +{EOR_B140,{1U,3U,0U}}, +{EOR_B140,{2U,3U,0U}}, +{EOR_B140,{3U,3U,0U}}, +{EOR_B140,{4U,3U,0U}}, +{EOR_B140,{5U,3U,0U}}, +{EOR_B140,{6U,3U,0U}}, +{EOR_B140,{7U,3U,0U}}, +{CMPM_B148,{3U,0U,0U}}, +{CMPM_B148,{3U,1U,0U}}, +{CMPM_B148,{3U,2U,0U}}, +{CMPM_B148,{3U,3U,0U}}, +{CMPM_B148,{3U,4U,0U}}, +{CMPM_B148,{3U,5U,0U}}, +{CMPM_B148,{3U,6U,0U}}, +{CMPM_B148,{3U,7U,0U}}, +{EOR_B150,{0U,3U,0U}}, +{EOR_B150,{1U,3U,0U}}, +{EOR_B150,{2U,3U,0U}}, +{EOR_B150,{3U,3U,0U}}, +{EOR_B150,{4U,3U,0U}}, +{EOR_B150,{5U,3U,0U}}, +{EOR_B150,{6U,3U,0U}}, +{EOR_B150,{7U,3U,0U}}, +{EOR_B158,{0U,3U,0U}}, +{EOR_B158,{1U,3U,0U}}, +{EOR_B158,{2U,3U,0U}}, +{EOR_B158,{3U,3U,0U}}, +{EOR_B158,{4U,3U,0U}}, +{EOR_B158,{5U,3U,0U}}, +{EOR_B158,{6U,3U,0U}}, +{EOR_B158,{7U,3U,0U}}, +{EOR_B160,{0U,3U,0U}}, +{EOR_B160,{1U,3U,0U}}, +{EOR_B160,{2U,3U,0U}}, +{EOR_B160,{3U,3U,0U}}, +{EOR_B160,{4U,3U,0U}}, +{EOR_B160,{5U,3U,0U}}, +{EOR_B160,{6U,3U,0U}}, +{EOR_B160,{7U,3U,0U}}, +{EOR_B168,{0U,3U,0U}}, +{EOR_B168,{1U,3U,0U}}, +{EOR_B168,{2U,3U,0U}}, +{EOR_B168,{3U,3U,0U}}, +{EOR_B168,{4U,3U,0U}}, +{EOR_B168,{5U,3U,0U}}, +{EOR_B168,{6U,3U,0U}}, +{EOR_B168,{7U,3U,0U}}, +{EOR_B170,{0U,3U,0U}}, +{EOR_B170,{1U,3U,0U}}, +{EOR_B170,{2U,3U,0U}}, +{EOR_B170,{3U,3U,0U}}, +{EOR_B170,{4U,3U,0U}}, +{EOR_B170,{5U,3U,0U}}, +{EOR_B170,{6U,3U,0U}}, +{EOR_B170,{7U,3U,0U}}, +{EOR_B178,{0U,3U,0U}}, +{EOR_B179,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B180,{0U,3U,0U}}, +{EOR_B180,{1U,3U,0U}}, +{EOR_B180,{2U,3U,0U}}, +{EOR_B180,{3U,3U,0U}}, +{EOR_B180,{4U,3U,0U}}, +{EOR_B180,{5U,3U,0U}}, +{EOR_B180,{6U,3U,0U}}, +{EOR_B180,{7U,3U,0U}}, +{CMPM_B188,{3U,0U,0U}}, +{CMPM_B188,{3U,1U,0U}}, +{CMPM_B188,{3U,2U,0U}}, +{CMPM_B188,{3U,3U,0U}}, +{CMPM_B188,{3U,4U,0U}}, +{CMPM_B188,{3U,5U,0U}}, +{CMPM_B188,{3U,6U,0U}}, +{CMPM_B188,{3U,7U,0U}}, +{EOR_B190,{0U,3U,0U}}, +{EOR_B190,{1U,3U,0U}}, +{EOR_B190,{2U,3U,0U}}, +{EOR_B190,{3U,3U,0U}}, +{EOR_B190,{4U,3U,0U}}, +{EOR_B190,{5U,3U,0U}}, +{EOR_B190,{6U,3U,0U}}, +{EOR_B190,{7U,3U,0U}}, +{EOR_B198,{0U,3U,0U}}, +{EOR_B198,{1U,3U,0U}}, +{EOR_B198,{2U,3U,0U}}, +{EOR_B198,{3U,3U,0U}}, +{EOR_B198,{4U,3U,0U}}, +{EOR_B198,{5U,3U,0U}}, +{EOR_B198,{6U,3U,0U}}, +{EOR_B198,{7U,3U,0U}}, +{EOR_B1A0,{0U,3U,0U}}, +{EOR_B1A0,{1U,3U,0U}}, +{EOR_B1A0,{2U,3U,0U}}, +{EOR_B1A0,{3U,3U,0U}}, +{EOR_B1A0,{4U,3U,0U}}, +{EOR_B1A0,{5U,3U,0U}}, +{EOR_B1A0,{6U,3U,0U}}, +{EOR_B1A0,{7U,3U,0U}}, +{EOR_B1A8,{0U,3U,0U}}, +{EOR_B1A8,{1U,3U,0U}}, +{EOR_B1A8,{2U,3U,0U}}, +{EOR_B1A8,{3U,3U,0U}}, +{EOR_B1A8,{4U,3U,0U}}, +{EOR_B1A8,{5U,3U,0U}}, +{EOR_B1A8,{6U,3U,0U}}, +{EOR_B1A8,{7U,3U,0U}}, +{EOR_B1B0,{0U,3U,0U}}, +{EOR_B1B0,{1U,3U,0U}}, +{EOR_B1B0,{2U,3U,0U}}, +{EOR_B1B0,{3U,3U,0U}}, +{EOR_B1B0,{4U,3U,0U}}, +{EOR_B1B0,{5U,3U,0U}}, +{EOR_B1B0,{6U,3U,0U}}, +{EOR_B1B0,{7U,3U,0U}}, +{EOR_B1B8,{0U,3U,0U}}, +{EOR_B1B9,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B1C0,{0U,3U,0U}}, +{CMPA_B1C0,{1U,3U,0U}}, +{CMPA_B1C0,{2U,3U,0U}}, +{CMPA_B1C0,{3U,3U,0U}}, +{CMPA_B1C0,{4U,3U,0U}}, +{CMPA_B1C0,{5U,3U,0U}}, +{CMPA_B1C0,{6U,3U,0U}}, +{CMPA_B1C0,{7U,3U,0U}}, +{CMPA_B1C8,{0U,3U,0U}}, +{CMPA_B1C8,{1U,3U,0U}}, +{CMPA_B1C8,{2U,3U,0U}}, +{CMPA_B1C8,{3U,3U,0U}}, +{CMPA_B1C8,{4U,3U,0U}}, +{CMPA_B1C8,{5U,3U,0U}}, +{CMPA_B1C8,{6U,3U,0U}}, +{CMPA_B1C8,{7U,3U,0U}}, +{CMPA_B1D0,{0U,3U,0U}}, +{CMPA_B1D0,{1U,3U,0U}}, +{CMPA_B1D0,{2U,3U,0U}}, +{CMPA_B1D0,{3U,3U,0U}}, +{CMPA_B1D0,{4U,3U,0U}}, +{CMPA_B1D0,{5U,3U,0U}}, +{CMPA_B1D0,{6U,3U,0U}}, +{CMPA_B1D0,{7U,3U,0U}}, +{CMPA_B1D8,{0U,3U,0U}}, +{CMPA_B1D8,{1U,3U,0U}}, +{CMPA_B1D8,{2U,3U,0U}}, +{CMPA_B1D8,{3U,3U,0U}}, +{CMPA_B1D8,{4U,3U,0U}}, +{CMPA_B1D8,{5U,3U,0U}}, +{CMPA_B1D8,{6U,3U,0U}}, +{CMPA_B1D8,{7U,3U,0U}}, +{CMPA_B1E0,{0U,3U,0U}}, +{CMPA_B1E0,{1U,3U,0U}}, +{CMPA_B1E0,{2U,3U,0U}}, +{CMPA_B1E0,{3U,3U,0U}}, +{CMPA_B1E0,{4U,3U,0U}}, +{CMPA_B1E0,{5U,3U,0U}}, +{CMPA_B1E0,{6U,3U,0U}}, +{CMPA_B1E0,{7U,3U,0U}}, +{CMPA_B1E8,{0U,3U,0U}}, +{CMPA_B1E8,{1U,3U,0U}}, +{CMPA_B1E8,{2U,3U,0U}}, +{CMPA_B1E8,{3U,3U,0U}}, +{CMPA_B1E8,{4U,3U,0U}}, +{CMPA_B1E8,{5U,3U,0U}}, +{CMPA_B1E8,{6U,3U,0U}}, +{CMPA_B1E8,{7U,3U,0U}}, +{CMPA_B1F0,{0U,3U,0U}}, +{CMPA_B1F0,{1U,3U,0U}}, +{CMPA_B1F0,{2U,3U,0U}}, +{CMPA_B1F0,{3U,3U,0U}}, +{CMPA_B1F0,{4U,3U,0U}}, +{CMPA_B1F0,{5U,3U,0U}}, +{CMPA_B1F0,{6U,3U,0U}}, +{CMPA_B1F0,{7U,3U,0U}}, +{CMPA_B1F8,{0U,3U,0U}}, +{CMPA_B1F9,{0U,3U,0U}}, +{CMPA_B1FA,{0U,3U,0U}}, +{CMPA_B1FB,{0U,3U,0U}}, +{CMPA_B1FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B000,{0U,4U,0U}}, +{CMP_B000,{1U,4U,0U}}, +{CMP_B000,{2U,4U,0U}}, +{CMP_B000,{3U,4U,0U}}, +{CMP_B000,{4U,4U,0U}}, +{CMP_B000,{5U,4U,0U}}, +{CMP_B000,{6U,4U,0U}}, +{CMP_B000,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B010,{0U,4U,0U}}, +{CMP_B010,{1U,4U,0U}}, +{CMP_B010,{2U,4U,0U}}, +{CMP_B010,{3U,4U,0U}}, +{CMP_B010,{4U,4U,0U}}, +{CMP_B010,{5U,4U,0U}}, +{CMP_B010,{6U,4U,0U}}, +{CMP_B010,{7U,4U,0U}}, +{CMP_B018,{0U,4U,0U}}, +{CMP_B018,{1U,4U,0U}}, +{CMP_B018,{2U,4U,0U}}, +{CMP_B018,{3U,4U,0U}}, +{CMP_B018,{4U,4U,0U}}, +{CMP_B018,{5U,4U,0U}}, +{CMP_B018,{6U,4U,0U}}, +{CMP_B018,{7U,4U,0U}}, +{CMP_B020,{0U,4U,0U}}, +{CMP_B020,{1U,4U,0U}}, +{CMP_B020,{2U,4U,0U}}, +{CMP_B020,{3U,4U,0U}}, +{CMP_B020,{4U,4U,0U}}, +{CMP_B020,{5U,4U,0U}}, +{CMP_B020,{6U,4U,0U}}, +{CMP_B020,{7U,4U,0U}}, +{CMP_B028,{0U,4U,0U}}, +{CMP_B028,{1U,4U,0U}}, +{CMP_B028,{2U,4U,0U}}, +{CMP_B028,{3U,4U,0U}}, +{CMP_B028,{4U,4U,0U}}, +{CMP_B028,{5U,4U,0U}}, +{CMP_B028,{6U,4U,0U}}, +{CMP_B028,{7U,4U,0U}}, +{CMP_B030,{0U,4U,0U}}, +{CMP_B030,{1U,4U,0U}}, +{CMP_B030,{2U,4U,0U}}, +{CMP_B030,{3U,4U,0U}}, +{CMP_B030,{4U,4U,0U}}, +{CMP_B030,{5U,4U,0U}}, +{CMP_B030,{6U,4U,0U}}, +{CMP_B030,{7U,4U,0U}}, +{CMP_B038,{0U,4U,0U}}, +{CMP_B039,{0U,4U,0U}}, +{CMP_B03A,{0U,4U,0U}}, +{CMP_B03B,{0U,4U,0U}}, +{CMP_B03C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B040,{0U,4U,0U}}, +{CMP_B040,{1U,4U,0U}}, +{CMP_B040,{2U,4U,0U}}, +{CMP_B040,{3U,4U,0U}}, +{CMP_B040,{4U,4U,0U}}, +{CMP_B040,{5U,4U,0U}}, +{CMP_B040,{6U,4U,0U}}, +{CMP_B040,{7U,4U,0U}}, +{CMP_B048,{0U,4U,0U}}, +{CMP_B048,{1U,4U,0U}}, +{CMP_B048,{2U,4U,0U}}, +{CMP_B048,{3U,4U,0U}}, +{CMP_B048,{4U,4U,0U}}, +{CMP_B048,{5U,4U,0U}}, +{CMP_B048,{6U,4U,0U}}, +{CMP_B048,{7U,4U,0U}}, +{CMP_B050,{0U,4U,0U}}, +{CMP_B050,{1U,4U,0U}}, +{CMP_B050,{2U,4U,0U}}, +{CMP_B050,{3U,4U,0U}}, +{CMP_B050,{4U,4U,0U}}, +{CMP_B050,{5U,4U,0U}}, +{CMP_B050,{6U,4U,0U}}, +{CMP_B050,{7U,4U,0U}}, +{CMP_B058,{0U,4U,0U}}, +{CMP_B058,{1U,4U,0U}}, +{CMP_B058,{2U,4U,0U}}, +{CMP_B058,{3U,4U,0U}}, +{CMP_B058,{4U,4U,0U}}, +{CMP_B058,{5U,4U,0U}}, +{CMP_B058,{6U,4U,0U}}, +{CMP_B058,{7U,4U,0U}}, +{CMP_B060,{0U,4U,0U}}, +{CMP_B060,{1U,4U,0U}}, +{CMP_B060,{2U,4U,0U}}, +{CMP_B060,{3U,4U,0U}}, +{CMP_B060,{4U,4U,0U}}, +{CMP_B060,{5U,4U,0U}}, +{CMP_B060,{6U,4U,0U}}, +{CMP_B060,{7U,4U,0U}}, +{CMP_B068,{0U,4U,0U}}, +{CMP_B068,{1U,4U,0U}}, +{CMP_B068,{2U,4U,0U}}, +{CMP_B068,{3U,4U,0U}}, +{CMP_B068,{4U,4U,0U}}, +{CMP_B068,{5U,4U,0U}}, +{CMP_B068,{6U,4U,0U}}, +{CMP_B068,{7U,4U,0U}}, +{CMP_B070,{0U,4U,0U}}, +{CMP_B070,{1U,4U,0U}}, +{CMP_B070,{2U,4U,0U}}, +{CMP_B070,{3U,4U,0U}}, +{CMP_B070,{4U,4U,0U}}, +{CMP_B070,{5U,4U,0U}}, +{CMP_B070,{6U,4U,0U}}, +{CMP_B070,{7U,4U,0U}}, +{CMP_B078,{0U,4U,0U}}, +{CMP_B079,{0U,4U,0U}}, +{CMP_B07A,{0U,4U,0U}}, +{CMP_B07B,{0U,4U,0U}}, +{CMP_B07C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B080,{0U,4U,0U}}, +{CMP_B080,{1U,4U,0U}}, +{CMP_B080,{2U,4U,0U}}, +{CMP_B080,{3U,4U,0U}}, +{CMP_B080,{4U,4U,0U}}, +{CMP_B080,{5U,4U,0U}}, +{CMP_B080,{6U,4U,0U}}, +{CMP_B080,{7U,4U,0U}}, +{CMP_B088,{0U,4U,0U}}, +{CMP_B088,{1U,4U,0U}}, +{CMP_B088,{2U,4U,0U}}, +{CMP_B088,{3U,4U,0U}}, +{CMP_B088,{4U,4U,0U}}, +{CMP_B088,{5U,4U,0U}}, +{CMP_B088,{6U,4U,0U}}, +{CMP_B088,{7U,4U,0U}}, +{CMP_B090,{0U,4U,0U}}, +{CMP_B090,{1U,4U,0U}}, +{CMP_B090,{2U,4U,0U}}, +{CMP_B090,{3U,4U,0U}}, +{CMP_B090,{4U,4U,0U}}, +{CMP_B090,{5U,4U,0U}}, +{CMP_B090,{6U,4U,0U}}, +{CMP_B090,{7U,4U,0U}}, +{CMP_B098,{0U,4U,0U}}, +{CMP_B098,{1U,4U,0U}}, +{CMP_B098,{2U,4U,0U}}, +{CMP_B098,{3U,4U,0U}}, +{CMP_B098,{4U,4U,0U}}, +{CMP_B098,{5U,4U,0U}}, +{CMP_B098,{6U,4U,0U}}, +{CMP_B098,{7U,4U,0U}}, +{CMP_B0A0,{0U,4U,0U}}, +{CMP_B0A0,{1U,4U,0U}}, +{CMP_B0A0,{2U,4U,0U}}, +{CMP_B0A0,{3U,4U,0U}}, +{CMP_B0A0,{4U,4U,0U}}, +{CMP_B0A0,{5U,4U,0U}}, +{CMP_B0A0,{6U,4U,0U}}, +{CMP_B0A0,{7U,4U,0U}}, +{CMP_B0A8,{0U,4U,0U}}, +{CMP_B0A8,{1U,4U,0U}}, +{CMP_B0A8,{2U,4U,0U}}, +{CMP_B0A8,{3U,4U,0U}}, +{CMP_B0A8,{4U,4U,0U}}, +{CMP_B0A8,{5U,4U,0U}}, +{CMP_B0A8,{6U,4U,0U}}, +{CMP_B0A8,{7U,4U,0U}}, +{CMP_B0B0,{0U,4U,0U}}, +{CMP_B0B0,{1U,4U,0U}}, +{CMP_B0B0,{2U,4U,0U}}, +{CMP_B0B0,{3U,4U,0U}}, +{CMP_B0B0,{4U,4U,0U}}, +{CMP_B0B0,{5U,4U,0U}}, +{CMP_B0B0,{6U,4U,0U}}, +{CMP_B0B0,{7U,4U,0U}}, +{CMP_B0B8,{0U,4U,0U}}, +{CMP_B0B9,{0U,4U,0U}}, +{CMP_B0BA,{0U,4U,0U}}, +{CMP_B0BB,{0U,4U,0U}}, +{CMP_B0BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B0C0,{0U,4U,0U}}, +{CMPA_B0C0,{1U,4U,0U}}, +{CMPA_B0C0,{2U,4U,0U}}, +{CMPA_B0C0,{3U,4U,0U}}, +{CMPA_B0C0,{4U,4U,0U}}, +{CMPA_B0C0,{5U,4U,0U}}, +{CMPA_B0C0,{6U,4U,0U}}, +{CMPA_B0C0,{7U,4U,0U}}, +{CMPA_B0C8,{0U,4U,0U}}, +{CMPA_B0C8,{1U,4U,0U}}, +{CMPA_B0C8,{2U,4U,0U}}, +{CMPA_B0C8,{3U,4U,0U}}, +{CMPA_B0C8,{4U,4U,0U}}, +{CMPA_B0C8,{5U,4U,0U}}, +{CMPA_B0C8,{6U,4U,0U}}, +{CMPA_B0C8,{7U,4U,0U}}, +{CMPA_B0D0,{0U,4U,0U}}, +{CMPA_B0D0,{1U,4U,0U}}, +{CMPA_B0D0,{2U,4U,0U}}, +{CMPA_B0D0,{3U,4U,0U}}, +{CMPA_B0D0,{4U,4U,0U}}, +{CMPA_B0D0,{5U,4U,0U}}, +{CMPA_B0D0,{6U,4U,0U}}, +{CMPA_B0D0,{7U,4U,0U}}, +{CMPA_B0D8,{0U,4U,0U}}, +{CMPA_B0D8,{1U,4U,0U}}, +{CMPA_B0D8,{2U,4U,0U}}, +{CMPA_B0D8,{3U,4U,0U}}, +{CMPA_B0D8,{4U,4U,0U}}, +{CMPA_B0D8,{5U,4U,0U}}, +{CMPA_B0D8,{6U,4U,0U}}, +{CMPA_B0D8,{7U,4U,0U}}, +{CMPA_B0E0,{0U,4U,0U}}, +{CMPA_B0E0,{1U,4U,0U}}, +{CMPA_B0E0,{2U,4U,0U}}, +{CMPA_B0E0,{3U,4U,0U}}, +{CMPA_B0E0,{4U,4U,0U}}, +{CMPA_B0E0,{5U,4U,0U}}, +{CMPA_B0E0,{6U,4U,0U}}, +{CMPA_B0E0,{7U,4U,0U}}, +{CMPA_B0E8,{0U,4U,0U}}, +{CMPA_B0E8,{1U,4U,0U}}, +{CMPA_B0E8,{2U,4U,0U}}, +{CMPA_B0E8,{3U,4U,0U}}, +{CMPA_B0E8,{4U,4U,0U}}, +{CMPA_B0E8,{5U,4U,0U}}, +{CMPA_B0E8,{6U,4U,0U}}, +{CMPA_B0E8,{7U,4U,0U}}, +{CMPA_B0F0,{0U,4U,0U}}, +{CMPA_B0F0,{1U,4U,0U}}, +{CMPA_B0F0,{2U,4U,0U}}, +{CMPA_B0F0,{3U,4U,0U}}, +{CMPA_B0F0,{4U,4U,0U}}, +{CMPA_B0F0,{5U,4U,0U}}, +{CMPA_B0F0,{6U,4U,0U}}, +{CMPA_B0F0,{7U,4U,0U}}, +{CMPA_B0F8,{0U,4U,0U}}, +{CMPA_B0F9,{0U,4U,0U}}, +{CMPA_B0FA,{0U,4U,0U}}, +{CMPA_B0FB,{0U,4U,0U}}, +{CMPA_B0FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B100,{0U,4U,0U}}, +{EOR_B100,{1U,4U,0U}}, +{EOR_B100,{2U,4U,0U}}, +{EOR_B100,{3U,4U,0U}}, +{EOR_B100,{4U,4U,0U}}, +{EOR_B100,{5U,4U,0U}}, +{EOR_B100,{6U,4U,0U}}, +{EOR_B100,{7U,4U,0U}}, +{CMPM_B108,{4U,0U,0U}}, +{CMPM_B108,{4U,1U,0U}}, +{CMPM_B108,{4U,2U,0U}}, +{CMPM_B108,{4U,3U,0U}}, +{CMPM_B108,{4U,4U,0U}}, +{CMPM_B108,{4U,5U,0U}}, +{CMPM_B108,{4U,6U,0U}}, +{CMPM_B108,{4U,7U,0U}}, +{EOR_B110,{0U,4U,0U}}, +{EOR_B110,{1U,4U,0U}}, +{EOR_B110,{2U,4U,0U}}, +{EOR_B110,{3U,4U,0U}}, +{EOR_B110,{4U,4U,0U}}, +{EOR_B110,{5U,4U,0U}}, +{EOR_B110,{6U,4U,0U}}, +{EOR_B110,{7U,4U,0U}}, +{EOR_B118,{0U,4U,0U}}, +{EOR_B118,{1U,4U,0U}}, +{EOR_B118,{2U,4U,0U}}, +{EOR_B118,{3U,4U,0U}}, +{EOR_B118,{4U,4U,0U}}, +{EOR_B118,{5U,4U,0U}}, +{EOR_B118,{6U,4U,0U}}, +{EOR_B118,{7U,4U,0U}}, +{EOR_B120,{0U,4U,0U}}, +{EOR_B120,{1U,4U,0U}}, +{EOR_B120,{2U,4U,0U}}, +{EOR_B120,{3U,4U,0U}}, +{EOR_B120,{4U,4U,0U}}, +{EOR_B120,{5U,4U,0U}}, +{EOR_B120,{6U,4U,0U}}, +{EOR_B120,{7U,4U,0U}}, +{EOR_B128,{0U,4U,0U}}, +{EOR_B128,{1U,4U,0U}}, +{EOR_B128,{2U,4U,0U}}, +{EOR_B128,{3U,4U,0U}}, +{EOR_B128,{4U,4U,0U}}, +{EOR_B128,{5U,4U,0U}}, +{EOR_B128,{6U,4U,0U}}, +{EOR_B128,{7U,4U,0U}}, +{EOR_B130,{0U,4U,0U}}, +{EOR_B130,{1U,4U,0U}}, +{EOR_B130,{2U,4U,0U}}, +{EOR_B130,{3U,4U,0U}}, +{EOR_B130,{4U,4U,0U}}, +{EOR_B130,{5U,4U,0U}}, +{EOR_B130,{6U,4U,0U}}, +{EOR_B130,{7U,4U,0U}}, +{EOR_B138,{0U,4U,0U}}, +{EOR_B139,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B140,{0U,4U,0U}}, +{EOR_B140,{1U,4U,0U}}, +{EOR_B140,{2U,4U,0U}}, +{EOR_B140,{3U,4U,0U}}, +{EOR_B140,{4U,4U,0U}}, +{EOR_B140,{5U,4U,0U}}, +{EOR_B140,{6U,4U,0U}}, +{EOR_B140,{7U,4U,0U}}, +{CMPM_B148,{4U,0U,0U}}, +{CMPM_B148,{4U,1U,0U}}, +{CMPM_B148,{4U,2U,0U}}, +{CMPM_B148,{4U,3U,0U}}, +{CMPM_B148,{4U,4U,0U}}, +{CMPM_B148,{4U,5U,0U}}, +{CMPM_B148,{4U,6U,0U}}, +{CMPM_B148,{4U,7U,0U}}, +{EOR_B150,{0U,4U,0U}}, +{EOR_B150,{1U,4U,0U}}, +{EOR_B150,{2U,4U,0U}}, +{EOR_B150,{3U,4U,0U}}, +{EOR_B150,{4U,4U,0U}}, +{EOR_B150,{5U,4U,0U}}, +{EOR_B150,{6U,4U,0U}}, +{EOR_B150,{7U,4U,0U}}, +{EOR_B158,{0U,4U,0U}}, +{EOR_B158,{1U,4U,0U}}, +{EOR_B158,{2U,4U,0U}}, +{EOR_B158,{3U,4U,0U}}, +{EOR_B158,{4U,4U,0U}}, +{EOR_B158,{5U,4U,0U}}, +{EOR_B158,{6U,4U,0U}}, +{EOR_B158,{7U,4U,0U}}, +{EOR_B160,{0U,4U,0U}}, +{EOR_B160,{1U,4U,0U}}, +{EOR_B160,{2U,4U,0U}}, +{EOR_B160,{3U,4U,0U}}, +{EOR_B160,{4U,4U,0U}}, +{EOR_B160,{5U,4U,0U}}, +{EOR_B160,{6U,4U,0U}}, +{EOR_B160,{7U,4U,0U}}, +{EOR_B168,{0U,4U,0U}}, +{EOR_B168,{1U,4U,0U}}, +{EOR_B168,{2U,4U,0U}}, +{EOR_B168,{3U,4U,0U}}, +{EOR_B168,{4U,4U,0U}}, +{EOR_B168,{5U,4U,0U}}, +{EOR_B168,{6U,4U,0U}}, +{EOR_B168,{7U,4U,0U}}, +{EOR_B170,{0U,4U,0U}}, +{EOR_B170,{1U,4U,0U}}, +{EOR_B170,{2U,4U,0U}}, +{EOR_B170,{3U,4U,0U}}, +{EOR_B170,{4U,4U,0U}}, +{EOR_B170,{5U,4U,0U}}, +{EOR_B170,{6U,4U,0U}}, +{EOR_B170,{7U,4U,0U}}, +{EOR_B178,{0U,4U,0U}}, +{EOR_B179,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B180,{0U,4U,0U}}, +{EOR_B180,{1U,4U,0U}}, +{EOR_B180,{2U,4U,0U}}, +{EOR_B180,{3U,4U,0U}}, +{EOR_B180,{4U,4U,0U}}, +{EOR_B180,{5U,4U,0U}}, +{EOR_B180,{6U,4U,0U}}, +{EOR_B180,{7U,4U,0U}}, +{CMPM_B188,{4U,0U,0U}}, +{CMPM_B188,{4U,1U,0U}}, +{CMPM_B188,{4U,2U,0U}}, +{CMPM_B188,{4U,3U,0U}}, +{CMPM_B188,{4U,4U,0U}}, +{CMPM_B188,{4U,5U,0U}}, +{CMPM_B188,{4U,6U,0U}}, +{CMPM_B188,{4U,7U,0U}}, +{EOR_B190,{0U,4U,0U}}, +{EOR_B190,{1U,4U,0U}}, +{EOR_B190,{2U,4U,0U}}, +{EOR_B190,{3U,4U,0U}}, +{EOR_B190,{4U,4U,0U}}, +{EOR_B190,{5U,4U,0U}}, +{EOR_B190,{6U,4U,0U}}, +{EOR_B190,{7U,4U,0U}}, +{EOR_B198,{0U,4U,0U}}, +{EOR_B198,{1U,4U,0U}}, +{EOR_B198,{2U,4U,0U}}, +{EOR_B198,{3U,4U,0U}}, +{EOR_B198,{4U,4U,0U}}, +{EOR_B198,{5U,4U,0U}}, +{EOR_B198,{6U,4U,0U}}, +{EOR_B198,{7U,4U,0U}}, +{EOR_B1A0,{0U,4U,0U}}, +{EOR_B1A0,{1U,4U,0U}}, +{EOR_B1A0,{2U,4U,0U}}, +{EOR_B1A0,{3U,4U,0U}}, +{EOR_B1A0,{4U,4U,0U}}, +{EOR_B1A0,{5U,4U,0U}}, +{EOR_B1A0,{6U,4U,0U}}, +{EOR_B1A0,{7U,4U,0U}}, +{EOR_B1A8,{0U,4U,0U}}, +{EOR_B1A8,{1U,4U,0U}}, +{EOR_B1A8,{2U,4U,0U}}, +{EOR_B1A8,{3U,4U,0U}}, +{EOR_B1A8,{4U,4U,0U}}, +{EOR_B1A8,{5U,4U,0U}}, +{EOR_B1A8,{6U,4U,0U}}, +{EOR_B1A8,{7U,4U,0U}}, +{EOR_B1B0,{0U,4U,0U}}, +{EOR_B1B0,{1U,4U,0U}}, +{EOR_B1B0,{2U,4U,0U}}, +{EOR_B1B0,{3U,4U,0U}}, +{EOR_B1B0,{4U,4U,0U}}, +{EOR_B1B0,{5U,4U,0U}}, +{EOR_B1B0,{6U,4U,0U}}, +{EOR_B1B0,{7U,4U,0U}}, +{EOR_B1B8,{0U,4U,0U}}, +{EOR_B1B9,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B1C0,{0U,4U,0U}}, +{CMPA_B1C0,{1U,4U,0U}}, +{CMPA_B1C0,{2U,4U,0U}}, +{CMPA_B1C0,{3U,4U,0U}}, +{CMPA_B1C0,{4U,4U,0U}}, +{CMPA_B1C0,{5U,4U,0U}}, +{CMPA_B1C0,{6U,4U,0U}}, +{CMPA_B1C0,{7U,4U,0U}}, +{CMPA_B1C8,{0U,4U,0U}}, +{CMPA_B1C8,{1U,4U,0U}}, +{CMPA_B1C8,{2U,4U,0U}}, +{CMPA_B1C8,{3U,4U,0U}}, +{CMPA_B1C8,{4U,4U,0U}}, +{CMPA_B1C8,{5U,4U,0U}}, +{CMPA_B1C8,{6U,4U,0U}}, +{CMPA_B1C8,{7U,4U,0U}}, +{CMPA_B1D0,{0U,4U,0U}}, +{CMPA_B1D0,{1U,4U,0U}}, +{CMPA_B1D0,{2U,4U,0U}}, +{CMPA_B1D0,{3U,4U,0U}}, +{CMPA_B1D0,{4U,4U,0U}}, +{CMPA_B1D0,{5U,4U,0U}}, +{CMPA_B1D0,{6U,4U,0U}}, +{CMPA_B1D0,{7U,4U,0U}}, +{CMPA_B1D8,{0U,4U,0U}}, +{CMPA_B1D8,{1U,4U,0U}}, +{CMPA_B1D8,{2U,4U,0U}}, +{CMPA_B1D8,{3U,4U,0U}}, +{CMPA_B1D8,{4U,4U,0U}}, +{CMPA_B1D8,{5U,4U,0U}}, +{CMPA_B1D8,{6U,4U,0U}}, +{CMPA_B1D8,{7U,4U,0U}}, +{CMPA_B1E0,{0U,4U,0U}}, +{CMPA_B1E0,{1U,4U,0U}}, +{CMPA_B1E0,{2U,4U,0U}}, +{CMPA_B1E0,{3U,4U,0U}}, +{CMPA_B1E0,{4U,4U,0U}}, +{CMPA_B1E0,{5U,4U,0U}}, +{CMPA_B1E0,{6U,4U,0U}}, +{CMPA_B1E0,{7U,4U,0U}}, +{CMPA_B1E8,{0U,4U,0U}}, +{CMPA_B1E8,{1U,4U,0U}}, +{CMPA_B1E8,{2U,4U,0U}}, +{CMPA_B1E8,{3U,4U,0U}}, +{CMPA_B1E8,{4U,4U,0U}}, +{CMPA_B1E8,{5U,4U,0U}}, +{CMPA_B1E8,{6U,4U,0U}}, +{CMPA_B1E8,{7U,4U,0U}}, +{CMPA_B1F0,{0U,4U,0U}}, +{CMPA_B1F0,{1U,4U,0U}}, +{CMPA_B1F0,{2U,4U,0U}}, +{CMPA_B1F0,{3U,4U,0U}}, +{CMPA_B1F0,{4U,4U,0U}}, +{CMPA_B1F0,{5U,4U,0U}}, +{CMPA_B1F0,{6U,4U,0U}}, +{CMPA_B1F0,{7U,4U,0U}}, +{CMPA_B1F8,{0U,4U,0U}}, +{CMPA_B1F9,{0U,4U,0U}}, +{CMPA_B1FA,{0U,4U,0U}}, +{CMPA_B1FB,{0U,4U,0U}}, +{CMPA_B1FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B000,{0U,5U,0U}}, +{CMP_B000,{1U,5U,0U}}, +{CMP_B000,{2U,5U,0U}}, +{CMP_B000,{3U,5U,0U}}, +{CMP_B000,{4U,5U,0U}}, +{CMP_B000,{5U,5U,0U}}, +{CMP_B000,{6U,5U,0U}}, +{CMP_B000,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B010,{0U,5U,0U}}, +{CMP_B010,{1U,5U,0U}}, +{CMP_B010,{2U,5U,0U}}, +{CMP_B010,{3U,5U,0U}}, +{CMP_B010,{4U,5U,0U}}, +{CMP_B010,{5U,5U,0U}}, +{CMP_B010,{6U,5U,0U}}, +{CMP_B010,{7U,5U,0U}}, +{CMP_B018,{0U,5U,0U}}, +{CMP_B018,{1U,5U,0U}}, +{CMP_B018,{2U,5U,0U}}, +{CMP_B018,{3U,5U,0U}}, +{CMP_B018,{4U,5U,0U}}, +{CMP_B018,{5U,5U,0U}}, +{CMP_B018,{6U,5U,0U}}, +{CMP_B018,{7U,5U,0U}}, +{CMP_B020,{0U,5U,0U}}, +{CMP_B020,{1U,5U,0U}}, +{CMP_B020,{2U,5U,0U}}, +{CMP_B020,{3U,5U,0U}}, +{CMP_B020,{4U,5U,0U}}, +{CMP_B020,{5U,5U,0U}}, +{CMP_B020,{6U,5U,0U}}, +{CMP_B020,{7U,5U,0U}}, +{CMP_B028,{0U,5U,0U}}, +{CMP_B028,{1U,5U,0U}}, +{CMP_B028,{2U,5U,0U}}, +{CMP_B028,{3U,5U,0U}}, +{CMP_B028,{4U,5U,0U}}, +{CMP_B028,{5U,5U,0U}}, +{CMP_B028,{6U,5U,0U}}, +{CMP_B028,{7U,5U,0U}}, +{CMP_B030,{0U,5U,0U}}, +{CMP_B030,{1U,5U,0U}}, +{CMP_B030,{2U,5U,0U}}, +{CMP_B030,{3U,5U,0U}}, +{CMP_B030,{4U,5U,0U}}, +{CMP_B030,{5U,5U,0U}}, +{CMP_B030,{6U,5U,0U}}, +{CMP_B030,{7U,5U,0U}}, +{CMP_B038,{0U,5U,0U}}, +{CMP_B039,{0U,5U,0U}}, +{CMP_B03A,{0U,5U,0U}}, +{CMP_B03B,{0U,5U,0U}}, +{CMP_B03C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B040,{0U,5U,0U}}, +{CMP_B040,{1U,5U,0U}}, +{CMP_B040,{2U,5U,0U}}, +{CMP_B040,{3U,5U,0U}}, +{CMP_B040,{4U,5U,0U}}, +{CMP_B040,{5U,5U,0U}}, +{CMP_B040,{6U,5U,0U}}, +{CMP_B040,{7U,5U,0U}}, +{CMP_B048,{0U,5U,0U}}, +{CMP_B048,{1U,5U,0U}}, +{CMP_B048,{2U,5U,0U}}, +{CMP_B048,{3U,5U,0U}}, +{CMP_B048,{4U,5U,0U}}, +{CMP_B048,{5U,5U,0U}}, +{CMP_B048,{6U,5U,0U}}, +{CMP_B048,{7U,5U,0U}}, +{CMP_B050,{0U,5U,0U}}, +{CMP_B050,{1U,5U,0U}}, +{CMP_B050,{2U,5U,0U}}, +{CMP_B050,{3U,5U,0U}}, +{CMP_B050,{4U,5U,0U}}, +{CMP_B050,{5U,5U,0U}}, +{CMP_B050,{6U,5U,0U}}, +{CMP_B050,{7U,5U,0U}}, +{CMP_B058,{0U,5U,0U}}, +{CMP_B058,{1U,5U,0U}}, +{CMP_B058,{2U,5U,0U}}, +{CMP_B058,{3U,5U,0U}}, +{CMP_B058,{4U,5U,0U}}, +{CMP_B058,{5U,5U,0U}}, +{CMP_B058,{6U,5U,0U}}, +{CMP_B058,{7U,5U,0U}}, +{CMP_B060,{0U,5U,0U}}, +{CMP_B060,{1U,5U,0U}}, +{CMP_B060,{2U,5U,0U}}, +{CMP_B060,{3U,5U,0U}}, +{CMP_B060,{4U,5U,0U}}, +{CMP_B060,{5U,5U,0U}}, +{CMP_B060,{6U,5U,0U}}, +{CMP_B060,{7U,5U,0U}}, +{CMP_B068,{0U,5U,0U}}, +{CMP_B068,{1U,5U,0U}}, +{CMP_B068,{2U,5U,0U}}, +{CMP_B068,{3U,5U,0U}}, +{CMP_B068,{4U,5U,0U}}, +{CMP_B068,{5U,5U,0U}}, +{CMP_B068,{6U,5U,0U}}, +{CMP_B068,{7U,5U,0U}}, +{CMP_B070,{0U,5U,0U}}, +{CMP_B070,{1U,5U,0U}}, +{CMP_B070,{2U,5U,0U}}, +{CMP_B070,{3U,5U,0U}}, +{CMP_B070,{4U,5U,0U}}, +{CMP_B070,{5U,5U,0U}}, +{CMP_B070,{6U,5U,0U}}, +{CMP_B070,{7U,5U,0U}}, +{CMP_B078,{0U,5U,0U}}, +{CMP_B079,{0U,5U,0U}}, +{CMP_B07A,{0U,5U,0U}}, +{CMP_B07B,{0U,5U,0U}}, +{CMP_B07C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B080,{0U,5U,0U}}, +{CMP_B080,{1U,5U,0U}}, +{CMP_B080,{2U,5U,0U}}, +{CMP_B080,{3U,5U,0U}}, +{CMP_B080,{4U,5U,0U}}, +{CMP_B080,{5U,5U,0U}}, +{CMP_B080,{6U,5U,0U}}, +{CMP_B080,{7U,5U,0U}}, +{CMP_B088,{0U,5U,0U}}, +{CMP_B088,{1U,5U,0U}}, +{CMP_B088,{2U,5U,0U}}, +{CMP_B088,{3U,5U,0U}}, +{CMP_B088,{4U,5U,0U}}, +{CMP_B088,{5U,5U,0U}}, +{CMP_B088,{6U,5U,0U}}, +{CMP_B088,{7U,5U,0U}}, +{CMP_B090,{0U,5U,0U}}, +{CMP_B090,{1U,5U,0U}}, +{CMP_B090,{2U,5U,0U}}, +{CMP_B090,{3U,5U,0U}}, +{CMP_B090,{4U,5U,0U}}, +{CMP_B090,{5U,5U,0U}}, +{CMP_B090,{6U,5U,0U}}, +{CMP_B090,{7U,5U,0U}}, +{CMP_B098,{0U,5U,0U}}, +{CMP_B098,{1U,5U,0U}}, +{CMP_B098,{2U,5U,0U}}, +{CMP_B098,{3U,5U,0U}}, +{CMP_B098,{4U,5U,0U}}, +{CMP_B098,{5U,5U,0U}}, +{CMP_B098,{6U,5U,0U}}, +{CMP_B098,{7U,5U,0U}}, +{CMP_B0A0,{0U,5U,0U}}, +{CMP_B0A0,{1U,5U,0U}}, +{CMP_B0A0,{2U,5U,0U}}, +{CMP_B0A0,{3U,5U,0U}}, +{CMP_B0A0,{4U,5U,0U}}, +{CMP_B0A0,{5U,5U,0U}}, +{CMP_B0A0,{6U,5U,0U}}, +{CMP_B0A0,{7U,5U,0U}}, +{CMP_B0A8,{0U,5U,0U}}, +{CMP_B0A8,{1U,5U,0U}}, +{CMP_B0A8,{2U,5U,0U}}, +{CMP_B0A8,{3U,5U,0U}}, +{CMP_B0A8,{4U,5U,0U}}, +{CMP_B0A8,{5U,5U,0U}}, +{CMP_B0A8,{6U,5U,0U}}, +{CMP_B0A8,{7U,5U,0U}}, +{CMP_B0B0,{0U,5U,0U}}, +{CMP_B0B0,{1U,5U,0U}}, +{CMP_B0B0,{2U,5U,0U}}, +{CMP_B0B0,{3U,5U,0U}}, +{CMP_B0B0,{4U,5U,0U}}, +{CMP_B0B0,{5U,5U,0U}}, +{CMP_B0B0,{6U,5U,0U}}, +{CMP_B0B0,{7U,5U,0U}}, +{CMP_B0B8,{0U,5U,0U}}, +{CMP_B0B9,{0U,5U,0U}}, +{CMP_B0BA,{0U,5U,0U}}, +{CMP_B0BB,{0U,5U,0U}}, +{CMP_B0BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B0C0,{0U,5U,0U}}, +{CMPA_B0C0,{1U,5U,0U}}, +{CMPA_B0C0,{2U,5U,0U}}, +{CMPA_B0C0,{3U,5U,0U}}, +{CMPA_B0C0,{4U,5U,0U}}, +{CMPA_B0C0,{5U,5U,0U}}, +{CMPA_B0C0,{6U,5U,0U}}, +{CMPA_B0C0,{7U,5U,0U}}, +{CMPA_B0C8,{0U,5U,0U}}, +{CMPA_B0C8,{1U,5U,0U}}, +{CMPA_B0C8,{2U,5U,0U}}, +{CMPA_B0C8,{3U,5U,0U}}, +{CMPA_B0C8,{4U,5U,0U}}, +{CMPA_B0C8,{5U,5U,0U}}, +{CMPA_B0C8,{6U,5U,0U}}, +{CMPA_B0C8,{7U,5U,0U}}, +{CMPA_B0D0,{0U,5U,0U}}, +{CMPA_B0D0,{1U,5U,0U}}, +{CMPA_B0D0,{2U,5U,0U}}, +{CMPA_B0D0,{3U,5U,0U}}, +{CMPA_B0D0,{4U,5U,0U}}, +{CMPA_B0D0,{5U,5U,0U}}, +{CMPA_B0D0,{6U,5U,0U}}, +{CMPA_B0D0,{7U,5U,0U}}, +{CMPA_B0D8,{0U,5U,0U}}, +{CMPA_B0D8,{1U,5U,0U}}, +{CMPA_B0D8,{2U,5U,0U}}, +{CMPA_B0D8,{3U,5U,0U}}, +{CMPA_B0D8,{4U,5U,0U}}, +{CMPA_B0D8,{5U,5U,0U}}, +{CMPA_B0D8,{6U,5U,0U}}, +{CMPA_B0D8,{7U,5U,0U}}, +{CMPA_B0E0,{0U,5U,0U}}, +{CMPA_B0E0,{1U,5U,0U}}, +{CMPA_B0E0,{2U,5U,0U}}, +{CMPA_B0E0,{3U,5U,0U}}, +{CMPA_B0E0,{4U,5U,0U}}, +{CMPA_B0E0,{5U,5U,0U}}, +{CMPA_B0E0,{6U,5U,0U}}, +{CMPA_B0E0,{7U,5U,0U}}, +{CMPA_B0E8,{0U,5U,0U}}, +{CMPA_B0E8,{1U,5U,0U}}, +{CMPA_B0E8,{2U,5U,0U}}, +{CMPA_B0E8,{3U,5U,0U}}, +{CMPA_B0E8,{4U,5U,0U}}, +{CMPA_B0E8,{5U,5U,0U}}, +{CMPA_B0E8,{6U,5U,0U}}, +{CMPA_B0E8,{7U,5U,0U}}, +{CMPA_B0F0,{0U,5U,0U}}, +{CMPA_B0F0,{1U,5U,0U}}, +{CMPA_B0F0,{2U,5U,0U}}, +{CMPA_B0F0,{3U,5U,0U}}, +{CMPA_B0F0,{4U,5U,0U}}, +{CMPA_B0F0,{5U,5U,0U}}, +{CMPA_B0F0,{6U,5U,0U}}, +{CMPA_B0F0,{7U,5U,0U}}, +{CMPA_B0F8,{0U,5U,0U}}, +{CMPA_B0F9,{0U,5U,0U}}, +{CMPA_B0FA,{0U,5U,0U}}, +{CMPA_B0FB,{0U,5U,0U}}, +{CMPA_B0FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B100,{0U,5U,0U}}, +{EOR_B100,{1U,5U,0U}}, +{EOR_B100,{2U,5U,0U}}, +{EOR_B100,{3U,5U,0U}}, +{EOR_B100,{4U,5U,0U}}, +{EOR_B100,{5U,5U,0U}}, +{EOR_B100,{6U,5U,0U}}, +{EOR_B100,{7U,5U,0U}}, +{CMPM_B108,{5U,0U,0U}}, +{CMPM_B108,{5U,1U,0U}}, +{CMPM_B108,{5U,2U,0U}}, +{CMPM_B108,{5U,3U,0U}}, +{CMPM_B108,{5U,4U,0U}}, +{CMPM_B108,{5U,5U,0U}}, +{CMPM_B108,{5U,6U,0U}}, +{CMPM_B108,{5U,7U,0U}}, +{EOR_B110,{0U,5U,0U}}, +{EOR_B110,{1U,5U,0U}}, +{EOR_B110,{2U,5U,0U}}, +{EOR_B110,{3U,5U,0U}}, +{EOR_B110,{4U,5U,0U}}, +{EOR_B110,{5U,5U,0U}}, +{EOR_B110,{6U,5U,0U}}, +{EOR_B110,{7U,5U,0U}}, +{EOR_B118,{0U,5U,0U}}, +{EOR_B118,{1U,5U,0U}}, +{EOR_B118,{2U,5U,0U}}, +{EOR_B118,{3U,5U,0U}}, +{EOR_B118,{4U,5U,0U}}, +{EOR_B118,{5U,5U,0U}}, +{EOR_B118,{6U,5U,0U}}, +{EOR_B118,{7U,5U,0U}}, +{EOR_B120,{0U,5U,0U}}, +{EOR_B120,{1U,5U,0U}}, +{EOR_B120,{2U,5U,0U}}, +{EOR_B120,{3U,5U,0U}}, +{EOR_B120,{4U,5U,0U}}, +{EOR_B120,{5U,5U,0U}}, +{EOR_B120,{6U,5U,0U}}, +{EOR_B120,{7U,5U,0U}}, +{EOR_B128,{0U,5U,0U}}, +{EOR_B128,{1U,5U,0U}}, +{EOR_B128,{2U,5U,0U}}, +{EOR_B128,{3U,5U,0U}}, +{EOR_B128,{4U,5U,0U}}, +{EOR_B128,{5U,5U,0U}}, +{EOR_B128,{6U,5U,0U}}, +{EOR_B128,{7U,5U,0U}}, +{EOR_B130,{0U,5U,0U}}, +{EOR_B130,{1U,5U,0U}}, +{EOR_B130,{2U,5U,0U}}, +{EOR_B130,{3U,5U,0U}}, +{EOR_B130,{4U,5U,0U}}, +{EOR_B130,{5U,5U,0U}}, +{EOR_B130,{6U,5U,0U}}, +{EOR_B130,{7U,5U,0U}}, +{EOR_B138,{0U,5U,0U}}, +{EOR_B139,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B140,{0U,5U,0U}}, +{EOR_B140,{1U,5U,0U}}, +{EOR_B140,{2U,5U,0U}}, +{EOR_B140,{3U,5U,0U}}, +{EOR_B140,{4U,5U,0U}}, +{EOR_B140,{5U,5U,0U}}, +{EOR_B140,{6U,5U,0U}}, +{EOR_B140,{7U,5U,0U}}, +{CMPM_B148,{5U,0U,0U}}, +{CMPM_B148,{5U,1U,0U}}, +{CMPM_B148,{5U,2U,0U}}, +{CMPM_B148,{5U,3U,0U}}, +{CMPM_B148,{5U,4U,0U}}, +{CMPM_B148,{5U,5U,0U}}, +{CMPM_B148,{5U,6U,0U}}, +{CMPM_B148,{5U,7U,0U}}, +{EOR_B150,{0U,5U,0U}}, +{EOR_B150,{1U,5U,0U}}, +{EOR_B150,{2U,5U,0U}}, +{EOR_B150,{3U,5U,0U}}, +{EOR_B150,{4U,5U,0U}}, +{EOR_B150,{5U,5U,0U}}, +{EOR_B150,{6U,5U,0U}}, +{EOR_B150,{7U,5U,0U}}, +{EOR_B158,{0U,5U,0U}}, +{EOR_B158,{1U,5U,0U}}, +{EOR_B158,{2U,5U,0U}}, +{EOR_B158,{3U,5U,0U}}, +{EOR_B158,{4U,5U,0U}}, +{EOR_B158,{5U,5U,0U}}, +{EOR_B158,{6U,5U,0U}}, +{EOR_B158,{7U,5U,0U}}, +{EOR_B160,{0U,5U,0U}}, +{EOR_B160,{1U,5U,0U}}, +{EOR_B160,{2U,5U,0U}}, +{EOR_B160,{3U,5U,0U}}, +{EOR_B160,{4U,5U,0U}}, +{EOR_B160,{5U,5U,0U}}, +{EOR_B160,{6U,5U,0U}}, +{EOR_B160,{7U,5U,0U}}, +{EOR_B168,{0U,5U,0U}}, +{EOR_B168,{1U,5U,0U}}, +{EOR_B168,{2U,5U,0U}}, +{EOR_B168,{3U,5U,0U}}, +{EOR_B168,{4U,5U,0U}}, +{EOR_B168,{5U,5U,0U}}, +{EOR_B168,{6U,5U,0U}}, +{EOR_B168,{7U,5U,0U}}, +{EOR_B170,{0U,5U,0U}}, +{EOR_B170,{1U,5U,0U}}, +{EOR_B170,{2U,5U,0U}}, +{EOR_B170,{3U,5U,0U}}, +{EOR_B170,{4U,5U,0U}}, +{EOR_B170,{5U,5U,0U}}, +{EOR_B170,{6U,5U,0U}}, +{EOR_B170,{7U,5U,0U}}, +{EOR_B178,{0U,5U,0U}}, +{EOR_B179,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B180,{0U,5U,0U}}, +{EOR_B180,{1U,5U,0U}}, +{EOR_B180,{2U,5U,0U}}, +{EOR_B180,{3U,5U,0U}}, +{EOR_B180,{4U,5U,0U}}, +{EOR_B180,{5U,5U,0U}}, +{EOR_B180,{6U,5U,0U}}, +{EOR_B180,{7U,5U,0U}}, +{CMPM_B188,{5U,0U,0U}}, +{CMPM_B188,{5U,1U,0U}}, +{CMPM_B188,{5U,2U,0U}}, +{CMPM_B188,{5U,3U,0U}}, +{CMPM_B188,{5U,4U,0U}}, +{CMPM_B188,{5U,5U,0U}}, +{CMPM_B188,{5U,6U,0U}}, +{CMPM_B188,{5U,7U,0U}}, +{EOR_B190,{0U,5U,0U}}, +{EOR_B190,{1U,5U,0U}}, +{EOR_B190,{2U,5U,0U}}, +{EOR_B190,{3U,5U,0U}}, +{EOR_B190,{4U,5U,0U}}, +{EOR_B190,{5U,5U,0U}}, +{EOR_B190,{6U,5U,0U}}, +{EOR_B190,{7U,5U,0U}}, +{EOR_B198,{0U,5U,0U}}, +{EOR_B198,{1U,5U,0U}}, +{EOR_B198,{2U,5U,0U}}, +{EOR_B198,{3U,5U,0U}}, +{EOR_B198,{4U,5U,0U}}, +{EOR_B198,{5U,5U,0U}}, +{EOR_B198,{6U,5U,0U}}, +{EOR_B198,{7U,5U,0U}}, +{EOR_B1A0,{0U,5U,0U}}, +{EOR_B1A0,{1U,5U,0U}}, +{EOR_B1A0,{2U,5U,0U}}, +{EOR_B1A0,{3U,5U,0U}}, +{EOR_B1A0,{4U,5U,0U}}, +{EOR_B1A0,{5U,5U,0U}}, +{EOR_B1A0,{6U,5U,0U}}, +{EOR_B1A0,{7U,5U,0U}}, +{EOR_B1A8,{0U,5U,0U}}, +{EOR_B1A8,{1U,5U,0U}}, +{EOR_B1A8,{2U,5U,0U}}, +{EOR_B1A8,{3U,5U,0U}}, +{EOR_B1A8,{4U,5U,0U}}, +{EOR_B1A8,{5U,5U,0U}}, +{EOR_B1A8,{6U,5U,0U}}, +{EOR_B1A8,{7U,5U,0U}}, +{EOR_B1B0,{0U,5U,0U}}, +{EOR_B1B0,{1U,5U,0U}}, +{EOR_B1B0,{2U,5U,0U}}, +{EOR_B1B0,{3U,5U,0U}}, +{EOR_B1B0,{4U,5U,0U}}, +{EOR_B1B0,{5U,5U,0U}}, +{EOR_B1B0,{6U,5U,0U}}, +{EOR_B1B0,{7U,5U,0U}}, +{EOR_B1B8,{0U,5U,0U}}, +{EOR_B1B9,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B1C0,{0U,5U,0U}}, +{CMPA_B1C0,{1U,5U,0U}}, +{CMPA_B1C0,{2U,5U,0U}}, +{CMPA_B1C0,{3U,5U,0U}}, +{CMPA_B1C0,{4U,5U,0U}}, +{CMPA_B1C0,{5U,5U,0U}}, +{CMPA_B1C0,{6U,5U,0U}}, +{CMPA_B1C0,{7U,5U,0U}}, +{CMPA_B1C8,{0U,5U,0U}}, +{CMPA_B1C8,{1U,5U,0U}}, +{CMPA_B1C8,{2U,5U,0U}}, +{CMPA_B1C8,{3U,5U,0U}}, +{CMPA_B1C8,{4U,5U,0U}}, +{CMPA_B1C8,{5U,5U,0U}}, +{CMPA_B1C8,{6U,5U,0U}}, +{CMPA_B1C8,{7U,5U,0U}}, +{CMPA_B1D0,{0U,5U,0U}}, +{CMPA_B1D0,{1U,5U,0U}}, +{CMPA_B1D0,{2U,5U,0U}}, +{CMPA_B1D0,{3U,5U,0U}}, +{CMPA_B1D0,{4U,5U,0U}}, +{CMPA_B1D0,{5U,5U,0U}}, +{CMPA_B1D0,{6U,5U,0U}}, +{CMPA_B1D0,{7U,5U,0U}}, +{CMPA_B1D8,{0U,5U,0U}}, +{CMPA_B1D8,{1U,5U,0U}}, +{CMPA_B1D8,{2U,5U,0U}}, +{CMPA_B1D8,{3U,5U,0U}}, +{CMPA_B1D8,{4U,5U,0U}}, +{CMPA_B1D8,{5U,5U,0U}}, +{CMPA_B1D8,{6U,5U,0U}}, +{CMPA_B1D8,{7U,5U,0U}}, +{CMPA_B1E0,{0U,5U,0U}}, +{CMPA_B1E0,{1U,5U,0U}}, +{CMPA_B1E0,{2U,5U,0U}}, +{CMPA_B1E0,{3U,5U,0U}}, +{CMPA_B1E0,{4U,5U,0U}}, +{CMPA_B1E0,{5U,5U,0U}}, +{CMPA_B1E0,{6U,5U,0U}}, +{CMPA_B1E0,{7U,5U,0U}}, +{CMPA_B1E8,{0U,5U,0U}}, +{CMPA_B1E8,{1U,5U,0U}}, +{CMPA_B1E8,{2U,5U,0U}}, +{CMPA_B1E8,{3U,5U,0U}}, +{CMPA_B1E8,{4U,5U,0U}}, +{CMPA_B1E8,{5U,5U,0U}}, +{CMPA_B1E8,{6U,5U,0U}}, +{CMPA_B1E8,{7U,5U,0U}}, +{CMPA_B1F0,{0U,5U,0U}}, +{CMPA_B1F0,{1U,5U,0U}}, +{CMPA_B1F0,{2U,5U,0U}}, +{CMPA_B1F0,{3U,5U,0U}}, +{CMPA_B1F0,{4U,5U,0U}}, +{CMPA_B1F0,{5U,5U,0U}}, +{CMPA_B1F0,{6U,5U,0U}}, +{CMPA_B1F0,{7U,5U,0U}}, +{CMPA_B1F8,{0U,5U,0U}}, +{CMPA_B1F9,{0U,5U,0U}}, +{CMPA_B1FA,{0U,5U,0U}}, +{CMPA_B1FB,{0U,5U,0U}}, +{CMPA_B1FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B000,{0U,6U,0U}}, +{CMP_B000,{1U,6U,0U}}, +{CMP_B000,{2U,6U,0U}}, +{CMP_B000,{3U,6U,0U}}, +{CMP_B000,{4U,6U,0U}}, +{CMP_B000,{5U,6U,0U}}, +{CMP_B000,{6U,6U,0U}}, +{CMP_B000,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B010,{0U,6U,0U}}, +{CMP_B010,{1U,6U,0U}}, +{CMP_B010,{2U,6U,0U}}, +{CMP_B010,{3U,6U,0U}}, +{CMP_B010,{4U,6U,0U}}, +{CMP_B010,{5U,6U,0U}}, +{CMP_B010,{6U,6U,0U}}, +{CMP_B010,{7U,6U,0U}}, +{CMP_B018,{0U,6U,0U}}, +{CMP_B018,{1U,6U,0U}}, +{CMP_B018,{2U,6U,0U}}, +{CMP_B018,{3U,6U,0U}}, +{CMP_B018,{4U,6U,0U}}, +{CMP_B018,{5U,6U,0U}}, +{CMP_B018,{6U,6U,0U}}, +{CMP_B018,{7U,6U,0U}}, +{CMP_B020,{0U,6U,0U}}, +{CMP_B020,{1U,6U,0U}}, +{CMP_B020,{2U,6U,0U}}, +{CMP_B020,{3U,6U,0U}}, +{CMP_B020,{4U,6U,0U}}, +{CMP_B020,{5U,6U,0U}}, +{CMP_B020,{6U,6U,0U}}, +{CMP_B020,{7U,6U,0U}}, +{CMP_B028,{0U,6U,0U}}, +{CMP_B028,{1U,6U,0U}}, +{CMP_B028,{2U,6U,0U}}, +{CMP_B028,{3U,6U,0U}}, +{CMP_B028,{4U,6U,0U}}, +{CMP_B028,{5U,6U,0U}}, +{CMP_B028,{6U,6U,0U}}, +{CMP_B028,{7U,6U,0U}}, +{CMP_B030,{0U,6U,0U}}, +{CMP_B030,{1U,6U,0U}}, +{CMP_B030,{2U,6U,0U}}, +{CMP_B030,{3U,6U,0U}}, +{CMP_B030,{4U,6U,0U}}, +{CMP_B030,{5U,6U,0U}}, +{CMP_B030,{6U,6U,0U}}, +{CMP_B030,{7U,6U,0U}}, +{CMP_B038,{0U,6U,0U}}, +{CMP_B039,{0U,6U,0U}}, +{CMP_B03A,{0U,6U,0U}}, +{CMP_B03B,{0U,6U,0U}}, +{CMP_B03C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B040,{0U,6U,0U}}, +{CMP_B040,{1U,6U,0U}}, +{CMP_B040,{2U,6U,0U}}, +{CMP_B040,{3U,6U,0U}}, +{CMP_B040,{4U,6U,0U}}, +{CMP_B040,{5U,6U,0U}}, +{CMP_B040,{6U,6U,0U}}, +{CMP_B040,{7U,6U,0U}}, +{CMP_B048,{0U,6U,0U}}, +{CMP_B048,{1U,6U,0U}}, +{CMP_B048,{2U,6U,0U}}, +{CMP_B048,{3U,6U,0U}}, +{CMP_B048,{4U,6U,0U}}, +{CMP_B048,{5U,6U,0U}}, +{CMP_B048,{6U,6U,0U}}, +{CMP_B048,{7U,6U,0U}}, +{CMP_B050,{0U,6U,0U}}, +{CMP_B050,{1U,6U,0U}}, +{CMP_B050,{2U,6U,0U}}, +{CMP_B050,{3U,6U,0U}}, +{CMP_B050,{4U,6U,0U}}, +{CMP_B050,{5U,6U,0U}}, +{CMP_B050,{6U,6U,0U}}, +{CMP_B050,{7U,6U,0U}}, +{CMP_B058,{0U,6U,0U}}, +{CMP_B058,{1U,6U,0U}}, +{CMP_B058,{2U,6U,0U}}, +{CMP_B058,{3U,6U,0U}}, +{CMP_B058,{4U,6U,0U}}, +{CMP_B058,{5U,6U,0U}}, +{CMP_B058,{6U,6U,0U}}, +{CMP_B058,{7U,6U,0U}}, +{CMP_B060,{0U,6U,0U}}, +{CMP_B060,{1U,6U,0U}}, +{CMP_B060,{2U,6U,0U}}, +{CMP_B060,{3U,6U,0U}}, +{CMP_B060,{4U,6U,0U}}, +{CMP_B060,{5U,6U,0U}}, +{CMP_B060,{6U,6U,0U}}, +{CMP_B060,{7U,6U,0U}}, +{CMP_B068,{0U,6U,0U}}, +{CMP_B068,{1U,6U,0U}}, +{CMP_B068,{2U,6U,0U}}, +{CMP_B068,{3U,6U,0U}}, +{CMP_B068,{4U,6U,0U}}, +{CMP_B068,{5U,6U,0U}}, +{CMP_B068,{6U,6U,0U}}, +{CMP_B068,{7U,6U,0U}}, +{CMP_B070,{0U,6U,0U}}, +{CMP_B070,{1U,6U,0U}}, +{CMP_B070,{2U,6U,0U}}, +{CMP_B070,{3U,6U,0U}}, +{CMP_B070,{4U,6U,0U}}, +{CMP_B070,{5U,6U,0U}}, +{CMP_B070,{6U,6U,0U}}, +{CMP_B070,{7U,6U,0U}}, +{CMP_B078,{0U,6U,0U}}, +{CMP_B079,{0U,6U,0U}}, +{CMP_B07A,{0U,6U,0U}}, +{CMP_B07B,{0U,6U,0U}}, +{CMP_B07C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B080,{0U,6U,0U}}, +{CMP_B080,{1U,6U,0U}}, +{CMP_B080,{2U,6U,0U}}, +{CMP_B080,{3U,6U,0U}}, +{CMP_B080,{4U,6U,0U}}, +{CMP_B080,{5U,6U,0U}}, +{CMP_B080,{6U,6U,0U}}, +{CMP_B080,{7U,6U,0U}}, +{CMP_B088,{0U,6U,0U}}, +{CMP_B088,{1U,6U,0U}}, +{CMP_B088,{2U,6U,0U}}, +{CMP_B088,{3U,6U,0U}}, +{CMP_B088,{4U,6U,0U}}, +{CMP_B088,{5U,6U,0U}}, +{CMP_B088,{6U,6U,0U}}, +{CMP_B088,{7U,6U,0U}}, +{CMP_B090,{0U,6U,0U}}, +{CMP_B090,{1U,6U,0U}}, +{CMP_B090,{2U,6U,0U}}, +{CMP_B090,{3U,6U,0U}}, +{CMP_B090,{4U,6U,0U}}, +{CMP_B090,{5U,6U,0U}}, +{CMP_B090,{6U,6U,0U}}, +{CMP_B090,{7U,6U,0U}}, +{CMP_B098,{0U,6U,0U}}, +{CMP_B098,{1U,6U,0U}}, +{CMP_B098,{2U,6U,0U}}, +{CMP_B098,{3U,6U,0U}}, +{CMP_B098,{4U,6U,0U}}, +{CMP_B098,{5U,6U,0U}}, +{CMP_B098,{6U,6U,0U}}, +{CMP_B098,{7U,6U,0U}}, +{CMP_B0A0,{0U,6U,0U}}, +{CMP_B0A0,{1U,6U,0U}}, +{CMP_B0A0,{2U,6U,0U}}, +{CMP_B0A0,{3U,6U,0U}}, +{CMP_B0A0,{4U,6U,0U}}, +{CMP_B0A0,{5U,6U,0U}}, +{CMP_B0A0,{6U,6U,0U}}, +{CMP_B0A0,{7U,6U,0U}}, +{CMP_B0A8,{0U,6U,0U}}, +{CMP_B0A8,{1U,6U,0U}}, +{CMP_B0A8,{2U,6U,0U}}, +{CMP_B0A8,{3U,6U,0U}}, +{CMP_B0A8,{4U,6U,0U}}, +{CMP_B0A8,{5U,6U,0U}}, +{CMP_B0A8,{6U,6U,0U}}, +{CMP_B0A8,{7U,6U,0U}}, +{CMP_B0B0,{0U,6U,0U}}, +{CMP_B0B0,{1U,6U,0U}}, +{CMP_B0B0,{2U,6U,0U}}, +{CMP_B0B0,{3U,6U,0U}}, +{CMP_B0B0,{4U,6U,0U}}, +{CMP_B0B0,{5U,6U,0U}}, +{CMP_B0B0,{6U,6U,0U}}, +{CMP_B0B0,{7U,6U,0U}}, +{CMP_B0B8,{0U,6U,0U}}, +{CMP_B0B9,{0U,6U,0U}}, +{CMP_B0BA,{0U,6U,0U}}, +{CMP_B0BB,{0U,6U,0U}}, +{CMP_B0BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B0C0,{0U,6U,0U}}, +{CMPA_B0C0,{1U,6U,0U}}, +{CMPA_B0C0,{2U,6U,0U}}, +{CMPA_B0C0,{3U,6U,0U}}, +{CMPA_B0C0,{4U,6U,0U}}, +{CMPA_B0C0,{5U,6U,0U}}, +{CMPA_B0C0,{6U,6U,0U}}, +{CMPA_B0C0,{7U,6U,0U}}, +{CMPA_B0C8,{0U,6U,0U}}, +{CMPA_B0C8,{1U,6U,0U}}, +{CMPA_B0C8,{2U,6U,0U}}, +{CMPA_B0C8,{3U,6U,0U}}, +{CMPA_B0C8,{4U,6U,0U}}, +{CMPA_B0C8,{5U,6U,0U}}, +{CMPA_B0C8,{6U,6U,0U}}, +{CMPA_B0C8,{7U,6U,0U}}, +{CMPA_B0D0,{0U,6U,0U}}, +{CMPA_B0D0,{1U,6U,0U}}, +{CMPA_B0D0,{2U,6U,0U}}, +{CMPA_B0D0,{3U,6U,0U}}, +{CMPA_B0D0,{4U,6U,0U}}, +{CMPA_B0D0,{5U,6U,0U}}, +{CMPA_B0D0,{6U,6U,0U}}, +{CMPA_B0D0,{7U,6U,0U}}, +{CMPA_B0D8,{0U,6U,0U}}, +{CMPA_B0D8,{1U,6U,0U}}, +{CMPA_B0D8,{2U,6U,0U}}, +{CMPA_B0D8,{3U,6U,0U}}, +{CMPA_B0D8,{4U,6U,0U}}, +{CMPA_B0D8,{5U,6U,0U}}, +{CMPA_B0D8,{6U,6U,0U}}, +{CMPA_B0D8,{7U,6U,0U}}, +{CMPA_B0E0,{0U,6U,0U}}, +{CMPA_B0E0,{1U,6U,0U}}, +{CMPA_B0E0,{2U,6U,0U}}, +{CMPA_B0E0,{3U,6U,0U}}, +{CMPA_B0E0,{4U,6U,0U}}, +{CMPA_B0E0,{5U,6U,0U}}, +{CMPA_B0E0,{6U,6U,0U}}, +{CMPA_B0E0,{7U,6U,0U}}, +{CMPA_B0E8,{0U,6U,0U}}, +{CMPA_B0E8,{1U,6U,0U}}, +{CMPA_B0E8,{2U,6U,0U}}, +{CMPA_B0E8,{3U,6U,0U}}, +{CMPA_B0E8,{4U,6U,0U}}, +{CMPA_B0E8,{5U,6U,0U}}, +{CMPA_B0E8,{6U,6U,0U}}, +{CMPA_B0E8,{7U,6U,0U}}, +{CMPA_B0F0,{0U,6U,0U}}, +{CMPA_B0F0,{1U,6U,0U}}, +{CMPA_B0F0,{2U,6U,0U}}, +{CMPA_B0F0,{3U,6U,0U}}, +{CMPA_B0F0,{4U,6U,0U}}, +{CMPA_B0F0,{5U,6U,0U}}, +{CMPA_B0F0,{6U,6U,0U}}, +{CMPA_B0F0,{7U,6U,0U}}, +{CMPA_B0F8,{0U,6U,0U}}, +{CMPA_B0F9,{0U,6U,0U}}, +{CMPA_B0FA,{0U,6U,0U}}, +{CMPA_B0FB,{0U,6U,0U}}, +{CMPA_B0FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B100,{0U,6U,0U}}, +{EOR_B100,{1U,6U,0U}}, +{EOR_B100,{2U,6U,0U}}, +{EOR_B100,{3U,6U,0U}}, +{EOR_B100,{4U,6U,0U}}, +{EOR_B100,{5U,6U,0U}}, +{EOR_B100,{6U,6U,0U}}, +{EOR_B100,{7U,6U,0U}}, +{CMPM_B108,{6U,0U,0U}}, +{CMPM_B108,{6U,1U,0U}}, +{CMPM_B108,{6U,2U,0U}}, +{CMPM_B108,{6U,3U,0U}}, +{CMPM_B108,{6U,4U,0U}}, +{CMPM_B108,{6U,5U,0U}}, +{CMPM_B108,{6U,6U,0U}}, +{CMPM_B108,{6U,7U,0U}}, +{EOR_B110,{0U,6U,0U}}, +{EOR_B110,{1U,6U,0U}}, +{EOR_B110,{2U,6U,0U}}, +{EOR_B110,{3U,6U,0U}}, +{EOR_B110,{4U,6U,0U}}, +{EOR_B110,{5U,6U,0U}}, +{EOR_B110,{6U,6U,0U}}, +{EOR_B110,{7U,6U,0U}}, +{EOR_B118,{0U,6U,0U}}, +{EOR_B118,{1U,6U,0U}}, +{EOR_B118,{2U,6U,0U}}, +{EOR_B118,{3U,6U,0U}}, +{EOR_B118,{4U,6U,0U}}, +{EOR_B118,{5U,6U,0U}}, +{EOR_B118,{6U,6U,0U}}, +{EOR_B118,{7U,6U,0U}}, +{EOR_B120,{0U,6U,0U}}, +{EOR_B120,{1U,6U,0U}}, +{EOR_B120,{2U,6U,0U}}, +{EOR_B120,{3U,6U,0U}}, +{EOR_B120,{4U,6U,0U}}, +{EOR_B120,{5U,6U,0U}}, +{EOR_B120,{6U,6U,0U}}, +{EOR_B120,{7U,6U,0U}}, +{EOR_B128,{0U,6U,0U}}, +{EOR_B128,{1U,6U,0U}}, +{EOR_B128,{2U,6U,0U}}, +{EOR_B128,{3U,6U,0U}}, +{EOR_B128,{4U,6U,0U}}, +{EOR_B128,{5U,6U,0U}}, +{EOR_B128,{6U,6U,0U}}, +{EOR_B128,{7U,6U,0U}}, +{EOR_B130,{0U,6U,0U}}, +{EOR_B130,{1U,6U,0U}}, +{EOR_B130,{2U,6U,0U}}, +{EOR_B130,{3U,6U,0U}}, +{EOR_B130,{4U,6U,0U}}, +{EOR_B130,{5U,6U,0U}}, +{EOR_B130,{6U,6U,0U}}, +{EOR_B130,{7U,6U,0U}}, +{EOR_B138,{0U,6U,0U}}, +{EOR_B139,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B140,{0U,6U,0U}}, +{EOR_B140,{1U,6U,0U}}, +{EOR_B140,{2U,6U,0U}}, +{EOR_B140,{3U,6U,0U}}, +{EOR_B140,{4U,6U,0U}}, +{EOR_B140,{5U,6U,0U}}, +{EOR_B140,{6U,6U,0U}}, +{EOR_B140,{7U,6U,0U}}, +{CMPM_B148,{6U,0U,0U}}, +{CMPM_B148,{6U,1U,0U}}, +{CMPM_B148,{6U,2U,0U}}, +{CMPM_B148,{6U,3U,0U}}, +{CMPM_B148,{6U,4U,0U}}, +{CMPM_B148,{6U,5U,0U}}, +{CMPM_B148,{6U,6U,0U}}, +{CMPM_B148,{6U,7U,0U}}, +{EOR_B150,{0U,6U,0U}}, +{EOR_B150,{1U,6U,0U}}, +{EOR_B150,{2U,6U,0U}}, +{EOR_B150,{3U,6U,0U}}, +{EOR_B150,{4U,6U,0U}}, +{EOR_B150,{5U,6U,0U}}, +{EOR_B150,{6U,6U,0U}}, +{EOR_B150,{7U,6U,0U}}, +{EOR_B158,{0U,6U,0U}}, +{EOR_B158,{1U,6U,0U}}, +{EOR_B158,{2U,6U,0U}}, +{EOR_B158,{3U,6U,0U}}, +{EOR_B158,{4U,6U,0U}}, +{EOR_B158,{5U,6U,0U}}, +{EOR_B158,{6U,6U,0U}}, +{EOR_B158,{7U,6U,0U}}, +{EOR_B160,{0U,6U,0U}}, +{EOR_B160,{1U,6U,0U}}, +{EOR_B160,{2U,6U,0U}}, +{EOR_B160,{3U,6U,0U}}, +{EOR_B160,{4U,6U,0U}}, +{EOR_B160,{5U,6U,0U}}, +{EOR_B160,{6U,6U,0U}}, +{EOR_B160,{7U,6U,0U}}, +{EOR_B168,{0U,6U,0U}}, +{EOR_B168,{1U,6U,0U}}, +{EOR_B168,{2U,6U,0U}}, +{EOR_B168,{3U,6U,0U}}, +{EOR_B168,{4U,6U,0U}}, +{EOR_B168,{5U,6U,0U}}, +{EOR_B168,{6U,6U,0U}}, +{EOR_B168,{7U,6U,0U}}, +{EOR_B170,{0U,6U,0U}}, +{EOR_B170,{1U,6U,0U}}, +{EOR_B170,{2U,6U,0U}}, +{EOR_B170,{3U,6U,0U}}, +{EOR_B170,{4U,6U,0U}}, +{EOR_B170,{5U,6U,0U}}, +{EOR_B170,{6U,6U,0U}}, +{EOR_B170,{7U,6U,0U}}, +{EOR_B178,{0U,6U,0U}}, +{EOR_B179,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B180,{0U,6U,0U}}, +{EOR_B180,{1U,6U,0U}}, +{EOR_B180,{2U,6U,0U}}, +{EOR_B180,{3U,6U,0U}}, +{EOR_B180,{4U,6U,0U}}, +{EOR_B180,{5U,6U,0U}}, +{EOR_B180,{6U,6U,0U}}, +{EOR_B180,{7U,6U,0U}}, +{CMPM_B188,{6U,0U,0U}}, +{CMPM_B188,{6U,1U,0U}}, +{CMPM_B188,{6U,2U,0U}}, +{CMPM_B188,{6U,3U,0U}}, +{CMPM_B188,{6U,4U,0U}}, +{CMPM_B188,{6U,5U,0U}}, +{CMPM_B188,{6U,6U,0U}}, +{CMPM_B188,{6U,7U,0U}}, +{EOR_B190,{0U,6U,0U}}, +{EOR_B190,{1U,6U,0U}}, +{EOR_B190,{2U,6U,0U}}, +{EOR_B190,{3U,6U,0U}}, +{EOR_B190,{4U,6U,0U}}, +{EOR_B190,{5U,6U,0U}}, +{EOR_B190,{6U,6U,0U}}, +{EOR_B190,{7U,6U,0U}}, +{EOR_B198,{0U,6U,0U}}, +{EOR_B198,{1U,6U,0U}}, +{EOR_B198,{2U,6U,0U}}, +{EOR_B198,{3U,6U,0U}}, +{EOR_B198,{4U,6U,0U}}, +{EOR_B198,{5U,6U,0U}}, +{EOR_B198,{6U,6U,0U}}, +{EOR_B198,{7U,6U,0U}}, +{EOR_B1A0,{0U,6U,0U}}, +{EOR_B1A0,{1U,6U,0U}}, +{EOR_B1A0,{2U,6U,0U}}, +{EOR_B1A0,{3U,6U,0U}}, +{EOR_B1A0,{4U,6U,0U}}, +{EOR_B1A0,{5U,6U,0U}}, +{EOR_B1A0,{6U,6U,0U}}, +{EOR_B1A0,{7U,6U,0U}}, +{EOR_B1A8,{0U,6U,0U}}, +{EOR_B1A8,{1U,6U,0U}}, +{EOR_B1A8,{2U,6U,0U}}, +{EOR_B1A8,{3U,6U,0U}}, +{EOR_B1A8,{4U,6U,0U}}, +{EOR_B1A8,{5U,6U,0U}}, +{EOR_B1A8,{6U,6U,0U}}, +{EOR_B1A8,{7U,6U,0U}}, +{EOR_B1B0,{0U,6U,0U}}, +{EOR_B1B0,{1U,6U,0U}}, +{EOR_B1B0,{2U,6U,0U}}, +{EOR_B1B0,{3U,6U,0U}}, +{EOR_B1B0,{4U,6U,0U}}, +{EOR_B1B0,{5U,6U,0U}}, +{EOR_B1B0,{6U,6U,0U}}, +{EOR_B1B0,{7U,6U,0U}}, +{EOR_B1B8,{0U,6U,0U}}, +{EOR_B1B9,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B1C0,{0U,6U,0U}}, +{CMPA_B1C0,{1U,6U,0U}}, +{CMPA_B1C0,{2U,6U,0U}}, +{CMPA_B1C0,{3U,6U,0U}}, +{CMPA_B1C0,{4U,6U,0U}}, +{CMPA_B1C0,{5U,6U,0U}}, +{CMPA_B1C0,{6U,6U,0U}}, +{CMPA_B1C0,{7U,6U,0U}}, +{CMPA_B1C8,{0U,6U,0U}}, +{CMPA_B1C8,{1U,6U,0U}}, +{CMPA_B1C8,{2U,6U,0U}}, +{CMPA_B1C8,{3U,6U,0U}}, +{CMPA_B1C8,{4U,6U,0U}}, +{CMPA_B1C8,{5U,6U,0U}}, +{CMPA_B1C8,{6U,6U,0U}}, +{CMPA_B1C8,{7U,6U,0U}}, +{CMPA_B1D0,{0U,6U,0U}}, +{CMPA_B1D0,{1U,6U,0U}}, +{CMPA_B1D0,{2U,6U,0U}}, +{CMPA_B1D0,{3U,6U,0U}}, +{CMPA_B1D0,{4U,6U,0U}}, +{CMPA_B1D0,{5U,6U,0U}}, +{CMPA_B1D0,{6U,6U,0U}}, +{CMPA_B1D0,{7U,6U,0U}}, +{CMPA_B1D8,{0U,6U,0U}}, +{CMPA_B1D8,{1U,6U,0U}}, +{CMPA_B1D8,{2U,6U,0U}}, +{CMPA_B1D8,{3U,6U,0U}}, +{CMPA_B1D8,{4U,6U,0U}}, +{CMPA_B1D8,{5U,6U,0U}}, +{CMPA_B1D8,{6U,6U,0U}}, +{CMPA_B1D8,{7U,6U,0U}}, +{CMPA_B1E0,{0U,6U,0U}}, +{CMPA_B1E0,{1U,6U,0U}}, +{CMPA_B1E0,{2U,6U,0U}}, +{CMPA_B1E0,{3U,6U,0U}}, +{CMPA_B1E0,{4U,6U,0U}}, +{CMPA_B1E0,{5U,6U,0U}}, +{CMPA_B1E0,{6U,6U,0U}}, +{CMPA_B1E0,{7U,6U,0U}}, +{CMPA_B1E8,{0U,6U,0U}}, +{CMPA_B1E8,{1U,6U,0U}}, +{CMPA_B1E8,{2U,6U,0U}}, +{CMPA_B1E8,{3U,6U,0U}}, +{CMPA_B1E8,{4U,6U,0U}}, +{CMPA_B1E8,{5U,6U,0U}}, +{CMPA_B1E8,{6U,6U,0U}}, +{CMPA_B1E8,{7U,6U,0U}}, +{CMPA_B1F0,{0U,6U,0U}}, +{CMPA_B1F0,{1U,6U,0U}}, +{CMPA_B1F0,{2U,6U,0U}}, +{CMPA_B1F0,{3U,6U,0U}}, +{CMPA_B1F0,{4U,6U,0U}}, +{CMPA_B1F0,{5U,6U,0U}}, +{CMPA_B1F0,{6U,6U,0U}}, +{CMPA_B1F0,{7U,6U,0U}}, +{CMPA_B1F8,{0U,6U,0U}}, +{CMPA_B1F9,{0U,6U,0U}}, +{CMPA_B1FA,{0U,6U,0U}}, +{CMPA_B1FB,{0U,6U,0U}}, +{CMPA_B1FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B000,{0U,7U,0U}}, +{CMP_B000,{1U,7U,0U}}, +{CMP_B000,{2U,7U,0U}}, +{CMP_B000,{3U,7U,0U}}, +{CMP_B000,{4U,7U,0U}}, +{CMP_B000,{5U,7U,0U}}, +{CMP_B000,{6U,7U,0U}}, +{CMP_B000,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B010,{0U,7U,0U}}, +{CMP_B010,{1U,7U,0U}}, +{CMP_B010,{2U,7U,0U}}, +{CMP_B010,{3U,7U,0U}}, +{CMP_B010,{4U,7U,0U}}, +{CMP_B010,{5U,7U,0U}}, +{CMP_B010,{6U,7U,0U}}, +{CMP_B010,{7U,7U,0U}}, +{CMP_B018,{0U,7U,0U}}, +{CMP_B018,{1U,7U,0U}}, +{CMP_B018,{2U,7U,0U}}, +{CMP_B018,{3U,7U,0U}}, +{CMP_B018,{4U,7U,0U}}, +{CMP_B018,{5U,7U,0U}}, +{CMP_B018,{6U,7U,0U}}, +{CMP_B018,{7U,7U,0U}}, +{CMP_B020,{0U,7U,0U}}, +{CMP_B020,{1U,7U,0U}}, +{CMP_B020,{2U,7U,0U}}, +{CMP_B020,{3U,7U,0U}}, +{CMP_B020,{4U,7U,0U}}, +{CMP_B020,{5U,7U,0U}}, +{CMP_B020,{6U,7U,0U}}, +{CMP_B020,{7U,7U,0U}}, +{CMP_B028,{0U,7U,0U}}, +{CMP_B028,{1U,7U,0U}}, +{CMP_B028,{2U,7U,0U}}, +{CMP_B028,{3U,7U,0U}}, +{CMP_B028,{4U,7U,0U}}, +{CMP_B028,{5U,7U,0U}}, +{CMP_B028,{6U,7U,0U}}, +{CMP_B028,{7U,7U,0U}}, +{CMP_B030,{0U,7U,0U}}, +{CMP_B030,{1U,7U,0U}}, +{CMP_B030,{2U,7U,0U}}, +{CMP_B030,{3U,7U,0U}}, +{CMP_B030,{4U,7U,0U}}, +{CMP_B030,{5U,7U,0U}}, +{CMP_B030,{6U,7U,0U}}, +{CMP_B030,{7U,7U,0U}}, +{CMP_B038,{0U,7U,0U}}, +{CMP_B039,{0U,7U,0U}}, +{CMP_B03A,{0U,7U,0U}}, +{CMP_B03B,{0U,7U,0U}}, +{CMP_B03C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B040,{0U,7U,0U}}, +{CMP_B040,{1U,7U,0U}}, +{CMP_B040,{2U,7U,0U}}, +{CMP_B040,{3U,7U,0U}}, +{CMP_B040,{4U,7U,0U}}, +{CMP_B040,{5U,7U,0U}}, +{CMP_B040,{6U,7U,0U}}, +{CMP_B040,{7U,7U,0U}}, +{CMP_B048,{0U,7U,0U}}, +{CMP_B048,{1U,7U,0U}}, +{CMP_B048,{2U,7U,0U}}, +{CMP_B048,{3U,7U,0U}}, +{CMP_B048,{4U,7U,0U}}, +{CMP_B048,{5U,7U,0U}}, +{CMP_B048,{6U,7U,0U}}, +{CMP_B048,{7U,7U,0U}}, +{CMP_B050,{0U,7U,0U}}, +{CMP_B050,{1U,7U,0U}}, +{CMP_B050,{2U,7U,0U}}, +{CMP_B050,{3U,7U,0U}}, +{CMP_B050,{4U,7U,0U}}, +{CMP_B050,{5U,7U,0U}}, +{CMP_B050,{6U,7U,0U}}, +{CMP_B050,{7U,7U,0U}}, +{CMP_B058,{0U,7U,0U}}, +{CMP_B058,{1U,7U,0U}}, +{CMP_B058,{2U,7U,0U}}, +{CMP_B058,{3U,7U,0U}}, +{CMP_B058,{4U,7U,0U}}, +{CMP_B058,{5U,7U,0U}}, +{CMP_B058,{6U,7U,0U}}, +{CMP_B058,{7U,7U,0U}}, +{CMP_B060,{0U,7U,0U}}, +{CMP_B060,{1U,7U,0U}}, +{CMP_B060,{2U,7U,0U}}, +{CMP_B060,{3U,7U,0U}}, +{CMP_B060,{4U,7U,0U}}, +{CMP_B060,{5U,7U,0U}}, +{CMP_B060,{6U,7U,0U}}, +{CMP_B060,{7U,7U,0U}}, +{CMP_B068,{0U,7U,0U}}, +{CMP_B068,{1U,7U,0U}}, +{CMP_B068,{2U,7U,0U}}, +{CMP_B068,{3U,7U,0U}}, +{CMP_B068,{4U,7U,0U}}, +{CMP_B068,{5U,7U,0U}}, +{CMP_B068,{6U,7U,0U}}, +{CMP_B068,{7U,7U,0U}}, +{CMP_B070,{0U,7U,0U}}, +{CMP_B070,{1U,7U,0U}}, +{CMP_B070,{2U,7U,0U}}, +{CMP_B070,{3U,7U,0U}}, +{CMP_B070,{4U,7U,0U}}, +{CMP_B070,{5U,7U,0U}}, +{CMP_B070,{6U,7U,0U}}, +{CMP_B070,{7U,7U,0U}}, +{CMP_B078,{0U,7U,0U}}, +{CMP_B079,{0U,7U,0U}}, +{CMP_B07A,{0U,7U,0U}}, +{CMP_B07B,{0U,7U,0U}}, +{CMP_B07C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMP_B080,{0U,7U,0U}}, +{CMP_B080,{1U,7U,0U}}, +{CMP_B080,{2U,7U,0U}}, +{CMP_B080,{3U,7U,0U}}, +{CMP_B080,{4U,7U,0U}}, +{CMP_B080,{5U,7U,0U}}, +{CMP_B080,{6U,7U,0U}}, +{CMP_B080,{7U,7U,0U}}, +{CMP_B088,{0U,7U,0U}}, +{CMP_B088,{1U,7U,0U}}, +{CMP_B088,{2U,7U,0U}}, +{CMP_B088,{3U,7U,0U}}, +{CMP_B088,{4U,7U,0U}}, +{CMP_B088,{5U,7U,0U}}, +{CMP_B088,{6U,7U,0U}}, +{CMP_B088,{7U,7U,0U}}, +{CMP_B090,{0U,7U,0U}}, +{CMP_B090,{1U,7U,0U}}, +{CMP_B090,{2U,7U,0U}}, +{CMP_B090,{3U,7U,0U}}, +{CMP_B090,{4U,7U,0U}}, +{CMP_B090,{5U,7U,0U}}, +{CMP_B090,{6U,7U,0U}}, +{CMP_B090,{7U,7U,0U}}, +{CMP_B098,{0U,7U,0U}}, +{CMP_B098,{1U,7U,0U}}, +{CMP_B098,{2U,7U,0U}}, +{CMP_B098,{3U,7U,0U}}, +{CMP_B098,{4U,7U,0U}}, +{CMP_B098,{5U,7U,0U}}, +{CMP_B098,{6U,7U,0U}}, +{CMP_B098,{7U,7U,0U}}, +{CMP_B0A0,{0U,7U,0U}}, +{CMP_B0A0,{1U,7U,0U}}, +{CMP_B0A0,{2U,7U,0U}}, +{CMP_B0A0,{3U,7U,0U}}, +{CMP_B0A0,{4U,7U,0U}}, +{CMP_B0A0,{5U,7U,0U}}, +{CMP_B0A0,{6U,7U,0U}}, +{CMP_B0A0,{7U,7U,0U}}, +{CMP_B0A8,{0U,7U,0U}}, +{CMP_B0A8,{1U,7U,0U}}, +{CMP_B0A8,{2U,7U,0U}}, +{CMP_B0A8,{3U,7U,0U}}, +{CMP_B0A8,{4U,7U,0U}}, +{CMP_B0A8,{5U,7U,0U}}, +{CMP_B0A8,{6U,7U,0U}}, +{CMP_B0A8,{7U,7U,0U}}, +{CMP_B0B0,{0U,7U,0U}}, +{CMP_B0B0,{1U,7U,0U}}, +{CMP_B0B0,{2U,7U,0U}}, +{CMP_B0B0,{3U,7U,0U}}, +{CMP_B0B0,{4U,7U,0U}}, +{CMP_B0B0,{5U,7U,0U}}, +{CMP_B0B0,{6U,7U,0U}}, +{CMP_B0B0,{7U,7U,0U}}, +{CMP_B0B8,{0U,7U,0U}}, +{CMP_B0B9,{0U,7U,0U}}, +{CMP_B0BA,{0U,7U,0U}}, +{CMP_B0BB,{0U,7U,0U}}, +{CMP_B0BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B0C0,{0U,7U,0U}}, +{CMPA_B0C0,{1U,7U,0U}}, +{CMPA_B0C0,{2U,7U,0U}}, +{CMPA_B0C0,{3U,7U,0U}}, +{CMPA_B0C0,{4U,7U,0U}}, +{CMPA_B0C0,{5U,7U,0U}}, +{CMPA_B0C0,{6U,7U,0U}}, +{CMPA_B0C0,{7U,7U,0U}}, +{CMPA_B0C8,{0U,7U,0U}}, +{CMPA_B0C8,{1U,7U,0U}}, +{CMPA_B0C8,{2U,7U,0U}}, +{CMPA_B0C8,{3U,7U,0U}}, +{CMPA_B0C8,{4U,7U,0U}}, +{CMPA_B0C8,{5U,7U,0U}}, +{CMPA_B0C8,{6U,7U,0U}}, +{CMPA_B0C8,{7U,7U,0U}}, +{CMPA_B0D0,{0U,7U,0U}}, +{CMPA_B0D0,{1U,7U,0U}}, +{CMPA_B0D0,{2U,7U,0U}}, +{CMPA_B0D0,{3U,7U,0U}}, +{CMPA_B0D0,{4U,7U,0U}}, +{CMPA_B0D0,{5U,7U,0U}}, +{CMPA_B0D0,{6U,7U,0U}}, +{CMPA_B0D0,{7U,7U,0U}}, +{CMPA_B0D8,{0U,7U,0U}}, +{CMPA_B0D8,{1U,7U,0U}}, +{CMPA_B0D8,{2U,7U,0U}}, +{CMPA_B0D8,{3U,7U,0U}}, +{CMPA_B0D8,{4U,7U,0U}}, +{CMPA_B0D8,{5U,7U,0U}}, +{CMPA_B0D8,{6U,7U,0U}}, +{CMPA_B0D8,{7U,7U,0U}}, +{CMPA_B0E0,{0U,7U,0U}}, +{CMPA_B0E0,{1U,7U,0U}}, +{CMPA_B0E0,{2U,7U,0U}}, +{CMPA_B0E0,{3U,7U,0U}}, +{CMPA_B0E0,{4U,7U,0U}}, +{CMPA_B0E0,{5U,7U,0U}}, +{CMPA_B0E0,{6U,7U,0U}}, +{CMPA_B0E0,{7U,7U,0U}}, +{CMPA_B0E8,{0U,7U,0U}}, +{CMPA_B0E8,{1U,7U,0U}}, +{CMPA_B0E8,{2U,7U,0U}}, +{CMPA_B0E8,{3U,7U,0U}}, +{CMPA_B0E8,{4U,7U,0U}}, +{CMPA_B0E8,{5U,7U,0U}}, +{CMPA_B0E8,{6U,7U,0U}}, +{CMPA_B0E8,{7U,7U,0U}}, +{CMPA_B0F0,{0U,7U,0U}}, +{CMPA_B0F0,{1U,7U,0U}}, +{CMPA_B0F0,{2U,7U,0U}}, +{CMPA_B0F0,{3U,7U,0U}}, +{CMPA_B0F0,{4U,7U,0U}}, +{CMPA_B0F0,{5U,7U,0U}}, +{CMPA_B0F0,{6U,7U,0U}}, +{CMPA_B0F0,{7U,7U,0U}}, +{CMPA_B0F8,{0U,7U,0U}}, +{CMPA_B0F9,{0U,7U,0U}}, +{CMPA_B0FA,{0U,7U,0U}}, +{CMPA_B0FB,{0U,7U,0U}}, +{CMPA_B0FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B100,{0U,7U,0U}}, +{EOR_B100,{1U,7U,0U}}, +{EOR_B100,{2U,7U,0U}}, +{EOR_B100,{3U,7U,0U}}, +{EOR_B100,{4U,7U,0U}}, +{EOR_B100,{5U,7U,0U}}, +{EOR_B100,{6U,7U,0U}}, +{EOR_B100,{7U,7U,0U}}, +{CMPM_B108,{7U,0U,0U}}, +{CMPM_B108,{7U,1U,0U}}, +{CMPM_B108,{7U,2U,0U}}, +{CMPM_B108,{7U,3U,0U}}, +{CMPM_B108,{7U,4U,0U}}, +{CMPM_B108,{7U,5U,0U}}, +{CMPM_B108,{7U,6U,0U}}, +{CMPM_B108,{7U,7U,0U}}, +{EOR_B110,{0U,7U,0U}}, +{EOR_B110,{1U,7U,0U}}, +{EOR_B110,{2U,7U,0U}}, +{EOR_B110,{3U,7U,0U}}, +{EOR_B110,{4U,7U,0U}}, +{EOR_B110,{5U,7U,0U}}, +{EOR_B110,{6U,7U,0U}}, +{EOR_B110,{7U,7U,0U}}, +{EOR_B118,{0U,7U,0U}}, +{EOR_B118,{1U,7U,0U}}, +{EOR_B118,{2U,7U,0U}}, +{EOR_B118,{3U,7U,0U}}, +{EOR_B118,{4U,7U,0U}}, +{EOR_B118,{5U,7U,0U}}, +{EOR_B118,{6U,7U,0U}}, +{EOR_B118,{7U,7U,0U}}, +{EOR_B120,{0U,7U,0U}}, +{EOR_B120,{1U,7U,0U}}, +{EOR_B120,{2U,7U,0U}}, +{EOR_B120,{3U,7U,0U}}, +{EOR_B120,{4U,7U,0U}}, +{EOR_B120,{5U,7U,0U}}, +{EOR_B120,{6U,7U,0U}}, +{EOR_B120,{7U,7U,0U}}, +{EOR_B128,{0U,7U,0U}}, +{EOR_B128,{1U,7U,0U}}, +{EOR_B128,{2U,7U,0U}}, +{EOR_B128,{3U,7U,0U}}, +{EOR_B128,{4U,7U,0U}}, +{EOR_B128,{5U,7U,0U}}, +{EOR_B128,{6U,7U,0U}}, +{EOR_B128,{7U,7U,0U}}, +{EOR_B130,{0U,7U,0U}}, +{EOR_B130,{1U,7U,0U}}, +{EOR_B130,{2U,7U,0U}}, +{EOR_B130,{3U,7U,0U}}, +{EOR_B130,{4U,7U,0U}}, +{EOR_B130,{5U,7U,0U}}, +{EOR_B130,{6U,7U,0U}}, +{EOR_B130,{7U,7U,0U}}, +{EOR_B138,{0U,7U,0U}}, +{EOR_B139,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B140,{0U,7U,0U}}, +{EOR_B140,{1U,7U,0U}}, +{EOR_B140,{2U,7U,0U}}, +{EOR_B140,{3U,7U,0U}}, +{EOR_B140,{4U,7U,0U}}, +{EOR_B140,{5U,7U,0U}}, +{EOR_B140,{6U,7U,0U}}, +{EOR_B140,{7U,7U,0U}}, +{CMPM_B148,{7U,0U,0U}}, +{CMPM_B148,{7U,1U,0U}}, +{CMPM_B148,{7U,2U,0U}}, +{CMPM_B148,{7U,3U,0U}}, +{CMPM_B148,{7U,4U,0U}}, +{CMPM_B148,{7U,5U,0U}}, +{CMPM_B148,{7U,6U,0U}}, +{CMPM_B148,{7U,7U,0U}}, +{EOR_B150,{0U,7U,0U}}, +{EOR_B150,{1U,7U,0U}}, +{EOR_B150,{2U,7U,0U}}, +{EOR_B150,{3U,7U,0U}}, +{EOR_B150,{4U,7U,0U}}, +{EOR_B150,{5U,7U,0U}}, +{EOR_B150,{6U,7U,0U}}, +{EOR_B150,{7U,7U,0U}}, +{EOR_B158,{0U,7U,0U}}, +{EOR_B158,{1U,7U,0U}}, +{EOR_B158,{2U,7U,0U}}, +{EOR_B158,{3U,7U,0U}}, +{EOR_B158,{4U,7U,0U}}, +{EOR_B158,{5U,7U,0U}}, +{EOR_B158,{6U,7U,0U}}, +{EOR_B158,{7U,7U,0U}}, +{EOR_B160,{0U,7U,0U}}, +{EOR_B160,{1U,7U,0U}}, +{EOR_B160,{2U,7U,0U}}, +{EOR_B160,{3U,7U,0U}}, +{EOR_B160,{4U,7U,0U}}, +{EOR_B160,{5U,7U,0U}}, +{EOR_B160,{6U,7U,0U}}, +{EOR_B160,{7U,7U,0U}}, +{EOR_B168,{0U,7U,0U}}, +{EOR_B168,{1U,7U,0U}}, +{EOR_B168,{2U,7U,0U}}, +{EOR_B168,{3U,7U,0U}}, +{EOR_B168,{4U,7U,0U}}, +{EOR_B168,{5U,7U,0U}}, +{EOR_B168,{6U,7U,0U}}, +{EOR_B168,{7U,7U,0U}}, +{EOR_B170,{0U,7U,0U}}, +{EOR_B170,{1U,7U,0U}}, +{EOR_B170,{2U,7U,0U}}, +{EOR_B170,{3U,7U,0U}}, +{EOR_B170,{4U,7U,0U}}, +{EOR_B170,{5U,7U,0U}}, +{EOR_B170,{6U,7U,0U}}, +{EOR_B170,{7U,7U,0U}}, +{EOR_B178,{0U,7U,0U}}, +{EOR_B179,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EOR_B180,{0U,7U,0U}}, +{EOR_B180,{1U,7U,0U}}, +{EOR_B180,{2U,7U,0U}}, +{EOR_B180,{3U,7U,0U}}, +{EOR_B180,{4U,7U,0U}}, +{EOR_B180,{5U,7U,0U}}, +{EOR_B180,{6U,7U,0U}}, +{EOR_B180,{7U,7U,0U}}, +{CMPM_B188,{7U,0U,0U}}, +{CMPM_B188,{7U,1U,0U}}, +{CMPM_B188,{7U,2U,0U}}, +{CMPM_B188,{7U,3U,0U}}, +{CMPM_B188,{7U,4U,0U}}, +{CMPM_B188,{7U,5U,0U}}, +{CMPM_B188,{7U,6U,0U}}, +{CMPM_B188,{7U,7U,0U}}, +{EOR_B190,{0U,7U,0U}}, +{EOR_B190,{1U,7U,0U}}, +{EOR_B190,{2U,7U,0U}}, +{EOR_B190,{3U,7U,0U}}, +{EOR_B190,{4U,7U,0U}}, +{EOR_B190,{5U,7U,0U}}, +{EOR_B190,{6U,7U,0U}}, +{EOR_B190,{7U,7U,0U}}, +{EOR_B198,{0U,7U,0U}}, +{EOR_B198,{1U,7U,0U}}, +{EOR_B198,{2U,7U,0U}}, +{EOR_B198,{3U,7U,0U}}, +{EOR_B198,{4U,7U,0U}}, +{EOR_B198,{5U,7U,0U}}, +{EOR_B198,{6U,7U,0U}}, +{EOR_B198,{7U,7U,0U}}, +{EOR_B1A0,{0U,7U,0U}}, +{EOR_B1A0,{1U,7U,0U}}, +{EOR_B1A0,{2U,7U,0U}}, +{EOR_B1A0,{3U,7U,0U}}, +{EOR_B1A0,{4U,7U,0U}}, +{EOR_B1A0,{5U,7U,0U}}, +{EOR_B1A0,{6U,7U,0U}}, +{EOR_B1A0,{7U,7U,0U}}, +{EOR_B1A8,{0U,7U,0U}}, +{EOR_B1A8,{1U,7U,0U}}, +{EOR_B1A8,{2U,7U,0U}}, +{EOR_B1A8,{3U,7U,0U}}, +{EOR_B1A8,{4U,7U,0U}}, +{EOR_B1A8,{5U,7U,0U}}, +{EOR_B1A8,{6U,7U,0U}}, +{EOR_B1A8,{7U,7U,0U}}, +{EOR_B1B0,{0U,7U,0U}}, +{EOR_B1B0,{1U,7U,0U}}, +{EOR_B1B0,{2U,7U,0U}}, +{EOR_B1B0,{3U,7U,0U}}, +{EOR_B1B0,{4U,7U,0U}}, +{EOR_B1B0,{5U,7U,0U}}, +{EOR_B1B0,{6U,7U,0U}}, +{EOR_B1B0,{7U,7U,0U}}, +{EOR_B1B8,{0U,7U,0U}}, +{EOR_B1B9,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{CMPA_B1C0,{0U,7U,0U}}, +{CMPA_B1C0,{1U,7U,0U}}, +{CMPA_B1C0,{2U,7U,0U}}, +{CMPA_B1C0,{3U,7U,0U}}, +{CMPA_B1C0,{4U,7U,0U}}, +{CMPA_B1C0,{5U,7U,0U}}, +{CMPA_B1C0,{6U,7U,0U}}, +{CMPA_B1C0,{7U,7U,0U}}, +{CMPA_B1C8,{0U,7U,0U}}, +{CMPA_B1C8,{1U,7U,0U}}, +{CMPA_B1C8,{2U,7U,0U}}, +{CMPA_B1C8,{3U,7U,0U}}, +{CMPA_B1C8,{4U,7U,0U}}, +{CMPA_B1C8,{5U,7U,0U}}, +{CMPA_B1C8,{6U,7U,0U}}, +{CMPA_B1C8,{7U,7U,0U}}, +{CMPA_B1D0,{0U,7U,0U}}, +{CMPA_B1D0,{1U,7U,0U}}, +{CMPA_B1D0,{2U,7U,0U}}, +{CMPA_B1D0,{3U,7U,0U}}, +{CMPA_B1D0,{4U,7U,0U}}, +{CMPA_B1D0,{5U,7U,0U}}, +{CMPA_B1D0,{6U,7U,0U}}, +{CMPA_B1D0,{7U,7U,0U}}, +{CMPA_B1D8,{0U,7U,0U}}, +{CMPA_B1D8,{1U,7U,0U}}, +{CMPA_B1D8,{2U,7U,0U}}, +{CMPA_B1D8,{3U,7U,0U}}, +{CMPA_B1D8,{4U,7U,0U}}, +{CMPA_B1D8,{5U,7U,0U}}, +{CMPA_B1D8,{6U,7U,0U}}, +{CMPA_B1D8,{7U,7U,0U}}, +{CMPA_B1E0,{0U,7U,0U}}, +{CMPA_B1E0,{1U,7U,0U}}, +{CMPA_B1E0,{2U,7U,0U}}, +{CMPA_B1E0,{3U,7U,0U}}, +{CMPA_B1E0,{4U,7U,0U}}, +{CMPA_B1E0,{5U,7U,0U}}, +{CMPA_B1E0,{6U,7U,0U}}, +{CMPA_B1E0,{7U,7U,0U}}, +{CMPA_B1E8,{0U,7U,0U}}, +{CMPA_B1E8,{1U,7U,0U}}, +{CMPA_B1E8,{2U,7U,0U}}, +{CMPA_B1E8,{3U,7U,0U}}, +{CMPA_B1E8,{4U,7U,0U}}, +{CMPA_B1E8,{5U,7U,0U}}, +{CMPA_B1E8,{6U,7U,0U}}, +{CMPA_B1E8,{7U,7U,0U}}, +{CMPA_B1F0,{0U,7U,0U}}, +{CMPA_B1F0,{1U,7U,0U}}, +{CMPA_B1F0,{2U,7U,0U}}, +{CMPA_B1F0,{3U,7U,0U}}, +{CMPA_B1F0,{4U,7U,0U}}, +{CMPA_B1F0,{5U,7U,0U}}, +{CMPA_B1F0,{6U,7U,0U}}, +{CMPA_B1F0,{7U,7U,0U}}, +{CMPA_B1F8,{0U,7U,0U}}, +{CMPA_B1F9,{0U,7U,0U}}, +{CMPA_B1FA,{0U,7U,0U}}, +{CMPA_B1FB,{0U,7U,0U}}, +{CMPA_B1FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C000,{0U,0U,0U}}, +{AND_C000,{1U,0U,0U}}, +{AND_C000,{2U,0U,0U}}, +{AND_C000,{3U,0U,0U}}, +{AND_C000,{4U,0U,0U}}, +{AND_C000,{5U,0U,0U}}, +{AND_C000,{6U,0U,0U}}, +{AND_C000,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C010,{0U,0U,0U}}, +{AND_C010,{1U,0U,0U}}, +{AND_C010,{2U,0U,0U}}, +{AND_C010,{3U,0U,0U}}, +{AND_C010,{4U,0U,0U}}, +{AND_C010,{5U,0U,0U}}, +{AND_C010,{6U,0U,0U}}, +{AND_C010,{7U,0U,0U}}, +{AND_C018,{0U,0U,0U}}, +{AND_C018,{1U,0U,0U}}, +{AND_C018,{2U,0U,0U}}, +{AND_C018,{3U,0U,0U}}, +{AND_C018,{4U,0U,0U}}, +{AND_C018,{5U,0U,0U}}, +{AND_C018,{6U,0U,0U}}, +{AND_C018,{7U,0U,0U}}, +{AND_C020,{0U,0U,0U}}, +{AND_C020,{1U,0U,0U}}, +{AND_C020,{2U,0U,0U}}, +{AND_C020,{3U,0U,0U}}, +{AND_C020,{4U,0U,0U}}, +{AND_C020,{5U,0U,0U}}, +{AND_C020,{6U,0U,0U}}, +{AND_C020,{7U,0U,0U}}, +{AND_C028,{0U,0U,0U}}, +{AND_C028,{1U,0U,0U}}, +{AND_C028,{2U,0U,0U}}, +{AND_C028,{3U,0U,0U}}, +{AND_C028,{4U,0U,0U}}, +{AND_C028,{5U,0U,0U}}, +{AND_C028,{6U,0U,0U}}, +{AND_C028,{7U,0U,0U}}, +{AND_C030,{0U,0U,0U}}, +{AND_C030,{1U,0U,0U}}, +{AND_C030,{2U,0U,0U}}, +{AND_C030,{3U,0U,0U}}, +{AND_C030,{4U,0U,0U}}, +{AND_C030,{5U,0U,0U}}, +{AND_C030,{6U,0U,0U}}, +{AND_C030,{7U,0U,0U}}, +{AND_C038,{0U,0U,0U}}, +{AND_C039,{0U,0U,0U}}, +{AND_C03A,{0U,0U,0U}}, +{AND_C03B,{0U,0U,0U}}, +{AND_C03C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C040,{0U,0U,0U}}, +{AND_C040,{1U,0U,0U}}, +{AND_C040,{2U,0U,0U}}, +{AND_C040,{3U,0U,0U}}, +{AND_C040,{4U,0U,0U}}, +{AND_C040,{5U,0U,0U}}, +{AND_C040,{6U,0U,0U}}, +{AND_C040,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C050,{0U,0U,0U}}, +{AND_C050,{1U,0U,0U}}, +{AND_C050,{2U,0U,0U}}, +{AND_C050,{3U,0U,0U}}, +{AND_C050,{4U,0U,0U}}, +{AND_C050,{5U,0U,0U}}, +{AND_C050,{6U,0U,0U}}, +{AND_C050,{7U,0U,0U}}, +{AND_C058,{0U,0U,0U}}, +{AND_C058,{1U,0U,0U}}, +{AND_C058,{2U,0U,0U}}, +{AND_C058,{3U,0U,0U}}, +{AND_C058,{4U,0U,0U}}, +{AND_C058,{5U,0U,0U}}, +{AND_C058,{6U,0U,0U}}, +{AND_C058,{7U,0U,0U}}, +{AND_C060,{0U,0U,0U}}, +{AND_C060,{1U,0U,0U}}, +{AND_C060,{2U,0U,0U}}, +{AND_C060,{3U,0U,0U}}, +{AND_C060,{4U,0U,0U}}, +{AND_C060,{5U,0U,0U}}, +{AND_C060,{6U,0U,0U}}, +{AND_C060,{7U,0U,0U}}, +{AND_C068,{0U,0U,0U}}, +{AND_C068,{1U,0U,0U}}, +{AND_C068,{2U,0U,0U}}, +{AND_C068,{3U,0U,0U}}, +{AND_C068,{4U,0U,0U}}, +{AND_C068,{5U,0U,0U}}, +{AND_C068,{6U,0U,0U}}, +{AND_C068,{7U,0U,0U}}, +{AND_C070,{0U,0U,0U}}, +{AND_C070,{1U,0U,0U}}, +{AND_C070,{2U,0U,0U}}, +{AND_C070,{3U,0U,0U}}, +{AND_C070,{4U,0U,0U}}, +{AND_C070,{5U,0U,0U}}, +{AND_C070,{6U,0U,0U}}, +{AND_C070,{7U,0U,0U}}, +{AND_C078,{0U,0U,0U}}, +{AND_C079,{0U,0U,0U}}, +{AND_C07A,{0U,0U,0U}}, +{AND_C07B,{0U,0U,0U}}, +{AND_C07C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C080,{0U,0U,0U}}, +{AND_C080,{1U,0U,0U}}, +{AND_C080,{2U,0U,0U}}, +{AND_C080,{3U,0U,0U}}, +{AND_C080,{4U,0U,0U}}, +{AND_C080,{5U,0U,0U}}, +{AND_C080,{6U,0U,0U}}, +{AND_C080,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C090,{0U,0U,0U}}, +{AND_C090,{1U,0U,0U}}, +{AND_C090,{2U,0U,0U}}, +{AND_C090,{3U,0U,0U}}, +{AND_C090,{4U,0U,0U}}, +{AND_C090,{5U,0U,0U}}, +{AND_C090,{6U,0U,0U}}, +{AND_C090,{7U,0U,0U}}, +{AND_C098,{0U,0U,0U}}, +{AND_C098,{1U,0U,0U}}, +{AND_C098,{2U,0U,0U}}, +{AND_C098,{3U,0U,0U}}, +{AND_C098,{4U,0U,0U}}, +{AND_C098,{5U,0U,0U}}, +{AND_C098,{6U,0U,0U}}, +{AND_C098,{7U,0U,0U}}, +{AND_C0A0,{0U,0U,0U}}, +{AND_C0A0,{1U,0U,0U}}, +{AND_C0A0,{2U,0U,0U}}, +{AND_C0A0,{3U,0U,0U}}, +{AND_C0A0,{4U,0U,0U}}, +{AND_C0A0,{5U,0U,0U}}, +{AND_C0A0,{6U,0U,0U}}, +{AND_C0A0,{7U,0U,0U}}, +{AND_C0A8,{0U,0U,0U}}, +{AND_C0A8,{1U,0U,0U}}, +{AND_C0A8,{2U,0U,0U}}, +{AND_C0A8,{3U,0U,0U}}, +{AND_C0A8,{4U,0U,0U}}, +{AND_C0A8,{5U,0U,0U}}, +{AND_C0A8,{6U,0U,0U}}, +{AND_C0A8,{7U,0U,0U}}, +{AND_C0B0,{0U,0U,0U}}, +{AND_C0B0,{1U,0U,0U}}, +{AND_C0B0,{2U,0U,0U}}, +{AND_C0B0,{3U,0U,0U}}, +{AND_C0B0,{4U,0U,0U}}, +{AND_C0B0,{5U,0U,0U}}, +{AND_C0B0,{6U,0U,0U}}, +{AND_C0B0,{7U,0U,0U}}, +{AND_C0B8,{0U,0U,0U}}, +{AND_C0B9,{0U,0U,0U}}, +{AND_C0BA,{0U,0U,0U}}, +{AND_C0BB,{0U,0U,0U}}, +{AND_C0BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0C0,{0U,0U,0U}}, +{MULU_C0C0,{1U,0U,0U}}, +{MULU_C0C0,{2U,0U,0U}}, +{MULU_C0C0,{3U,0U,0U}}, +{MULU_C0C0,{4U,0U,0U}}, +{MULU_C0C0,{5U,0U,0U}}, +{MULU_C0C0,{6U,0U,0U}}, +{MULU_C0C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0D0,{0U,0U,0U}}, +{MULU_C0D0,{1U,0U,0U}}, +{MULU_C0D0,{2U,0U,0U}}, +{MULU_C0D0,{3U,0U,0U}}, +{MULU_C0D0,{4U,0U,0U}}, +{MULU_C0D0,{5U,0U,0U}}, +{MULU_C0D0,{6U,0U,0U}}, +{MULU_C0D0,{7U,0U,0U}}, +{MULU_C0D8,{0U,0U,0U}}, +{MULU_C0D8,{1U,0U,0U}}, +{MULU_C0D8,{2U,0U,0U}}, +{MULU_C0D8,{3U,0U,0U}}, +{MULU_C0D8,{4U,0U,0U}}, +{MULU_C0D8,{5U,0U,0U}}, +{MULU_C0D8,{6U,0U,0U}}, +{MULU_C0D8,{7U,0U,0U}}, +{MULU_C0E0,{0U,0U,0U}}, +{MULU_C0E0,{1U,0U,0U}}, +{MULU_C0E0,{2U,0U,0U}}, +{MULU_C0E0,{3U,0U,0U}}, +{MULU_C0E0,{4U,0U,0U}}, +{MULU_C0E0,{5U,0U,0U}}, +{MULU_C0E0,{6U,0U,0U}}, +{MULU_C0E0,{7U,0U,0U}}, +{MULU_C0E8,{0U,0U,0U}}, +{MULU_C0E8,{1U,0U,0U}}, +{MULU_C0E8,{2U,0U,0U}}, +{MULU_C0E8,{3U,0U,0U}}, +{MULU_C0E8,{4U,0U,0U}}, +{MULU_C0E8,{5U,0U,0U}}, +{MULU_C0E8,{6U,0U,0U}}, +{MULU_C0E8,{7U,0U,0U}}, +{MULU_C0F0,{0U,0U,0U}}, +{MULU_C0F0,{1U,0U,0U}}, +{MULU_C0F0,{2U,0U,0U}}, +{MULU_C0F0,{3U,0U,0U}}, +{MULU_C0F0,{4U,0U,0U}}, +{MULU_C0F0,{5U,0U,0U}}, +{MULU_C0F0,{6U,0U,0U}}, +{MULU_C0F0,{7U,0U,0U}}, +{MULU_C0F8,{0U,0U,0U}}, +{MULU_C0F9,{0U,0U,0U}}, +{MULU_C0FA,{0U,0U,0U}}, +{MULU_C0FB,{0U,0U,0U}}, +{MULU_C0FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ABCD_C100,{0U,0U,0U}}, +{ABCD_C100,{1U,0U,0U}}, +{ABCD_C100,{2U,0U,0U}}, +{ABCD_C100,{3U,0U,0U}}, +{ABCD_C100,{4U,0U,0U}}, +{ABCD_C100,{5U,0U,0U}}, +{ABCD_C100,{6U,0U,0U}}, +{ABCD_C100,{7U,0U,0U}}, +{ABCD_C108,{0U,0U,0U}}, +{ABCD_C108,{1U,0U,0U}}, +{ABCD_C108,{2U,0U,0U}}, +{ABCD_C108,{3U,0U,0U}}, +{ABCD_C108,{4U,0U,0U}}, +{ABCD_C108,{5U,0U,0U}}, +{ABCD_C108,{6U,0U,0U}}, +{ABCD_C108,{7U,0U,0U}}, +{AND_C110,{0U,0U,0U}}, +{AND_C110,{1U,0U,0U}}, +{AND_C110,{2U,0U,0U}}, +{AND_C110,{3U,0U,0U}}, +{AND_C110,{4U,0U,0U}}, +{AND_C110,{5U,0U,0U}}, +{AND_C110,{6U,0U,0U}}, +{AND_C110,{7U,0U,0U}}, +{AND_C118,{0U,0U,0U}}, +{AND_C118,{1U,0U,0U}}, +{AND_C118,{2U,0U,0U}}, +{AND_C118,{3U,0U,0U}}, +{AND_C118,{4U,0U,0U}}, +{AND_C118,{5U,0U,0U}}, +{AND_C118,{6U,0U,0U}}, +{AND_C118,{7U,0U,0U}}, +{AND_C120,{0U,0U,0U}}, +{AND_C120,{1U,0U,0U}}, +{AND_C120,{2U,0U,0U}}, +{AND_C120,{3U,0U,0U}}, +{AND_C120,{4U,0U,0U}}, +{AND_C120,{5U,0U,0U}}, +{AND_C120,{6U,0U,0U}}, +{AND_C120,{7U,0U,0U}}, +{AND_C128,{0U,0U,0U}}, +{AND_C128,{1U,0U,0U}}, +{AND_C128,{2U,0U,0U}}, +{AND_C128,{3U,0U,0U}}, +{AND_C128,{4U,0U,0U}}, +{AND_C128,{5U,0U,0U}}, +{AND_C128,{6U,0U,0U}}, +{AND_C128,{7U,0U,0U}}, +{AND_C130,{0U,0U,0U}}, +{AND_C130,{1U,0U,0U}}, +{AND_C130,{2U,0U,0U}}, +{AND_C130,{3U,0U,0U}}, +{AND_C130,{4U,0U,0U}}, +{AND_C130,{5U,0U,0U}}, +{AND_C130,{6U,0U,0U}}, +{AND_C130,{7U,0U,0U}}, +{AND_C138,{0U,0U,0U}}, +{AND_C139,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C140,{0U,0U,0U}}, +{EXG_C140,{0U,1U,0U}}, +{EXG_C140,{0U,2U,0U}}, +{EXG_C140,{0U,3U,0U}}, +{EXG_C140,{0U,4U,0U}}, +{EXG_C140,{0U,5U,0U}}, +{EXG_C140,{0U,6U,0U}}, +{EXG_C140,{0U,7U,0U}}, +{EXG_C148,{0U,0U,0U}}, +{EXG_C148,{0U,1U,0U}}, +{EXG_C148,{0U,2U,0U}}, +{EXG_C148,{0U,3U,0U}}, +{EXG_C148,{0U,4U,0U}}, +{EXG_C148,{0U,5U,0U}}, +{EXG_C148,{0U,6U,0U}}, +{EXG_C148,{0U,7U,0U}}, +{AND_C150,{0U,0U,0U}}, +{AND_C150,{1U,0U,0U}}, +{AND_C150,{2U,0U,0U}}, +{AND_C150,{3U,0U,0U}}, +{AND_C150,{4U,0U,0U}}, +{AND_C150,{5U,0U,0U}}, +{AND_C150,{6U,0U,0U}}, +{AND_C150,{7U,0U,0U}}, +{AND_C158,{0U,0U,0U}}, +{AND_C158,{1U,0U,0U}}, +{AND_C158,{2U,0U,0U}}, +{AND_C158,{3U,0U,0U}}, +{AND_C158,{4U,0U,0U}}, +{AND_C158,{5U,0U,0U}}, +{AND_C158,{6U,0U,0U}}, +{AND_C158,{7U,0U,0U}}, +{AND_C160,{0U,0U,0U}}, +{AND_C160,{1U,0U,0U}}, +{AND_C160,{2U,0U,0U}}, +{AND_C160,{3U,0U,0U}}, +{AND_C160,{4U,0U,0U}}, +{AND_C160,{5U,0U,0U}}, +{AND_C160,{6U,0U,0U}}, +{AND_C160,{7U,0U,0U}}, +{AND_C168,{0U,0U,0U}}, +{AND_C168,{1U,0U,0U}}, +{AND_C168,{2U,0U,0U}}, +{AND_C168,{3U,0U,0U}}, +{AND_C168,{4U,0U,0U}}, +{AND_C168,{5U,0U,0U}}, +{AND_C168,{6U,0U,0U}}, +{AND_C168,{7U,0U,0U}}, +{AND_C170,{0U,0U,0U}}, +{AND_C170,{1U,0U,0U}}, +{AND_C170,{2U,0U,0U}}, +{AND_C170,{3U,0U,0U}}, +{AND_C170,{4U,0U,0U}}, +{AND_C170,{5U,0U,0U}}, +{AND_C170,{6U,0U,0U}}, +{AND_C170,{7U,0U,0U}}, +{AND_C178,{0U,0U,0U}}, +{AND_C179,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C188,{0U,0U,0U}}, +{EXG_C188,{0U,1U,0U}}, +{EXG_C188,{0U,2U,0U}}, +{EXG_C188,{0U,3U,0U}}, +{EXG_C188,{0U,4U,0U}}, +{EXG_C188,{0U,5U,0U}}, +{EXG_C188,{0U,6U,0U}}, +{EXG_C188,{0U,7U,0U}}, +{AND_C190,{0U,0U,0U}}, +{AND_C190,{1U,0U,0U}}, +{AND_C190,{2U,0U,0U}}, +{AND_C190,{3U,0U,0U}}, +{AND_C190,{4U,0U,0U}}, +{AND_C190,{5U,0U,0U}}, +{AND_C190,{6U,0U,0U}}, +{AND_C190,{7U,0U,0U}}, +{AND_C198,{0U,0U,0U}}, +{AND_C198,{1U,0U,0U}}, +{AND_C198,{2U,0U,0U}}, +{AND_C198,{3U,0U,0U}}, +{AND_C198,{4U,0U,0U}}, +{AND_C198,{5U,0U,0U}}, +{AND_C198,{6U,0U,0U}}, +{AND_C198,{7U,0U,0U}}, +{AND_C1A0,{0U,0U,0U}}, +{AND_C1A0,{1U,0U,0U}}, +{AND_C1A0,{2U,0U,0U}}, +{AND_C1A0,{3U,0U,0U}}, +{AND_C1A0,{4U,0U,0U}}, +{AND_C1A0,{5U,0U,0U}}, +{AND_C1A0,{6U,0U,0U}}, +{AND_C1A0,{7U,0U,0U}}, +{AND_C1A8,{0U,0U,0U}}, +{AND_C1A8,{1U,0U,0U}}, +{AND_C1A8,{2U,0U,0U}}, +{AND_C1A8,{3U,0U,0U}}, +{AND_C1A8,{4U,0U,0U}}, +{AND_C1A8,{5U,0U,0U}}, +{AND_C1A8,{6U,0U,0U}}, +{AND_C1A8,{7U,0U,0U}}, +{AND_C1B0,{0U,0U,0U}}, +{AND_C1B0,{1U,0U,0U}}, +{AND_C1B0,{2U,0U,0U}}, +{AND_C1B0,{3U,0U,0U}}, +{AND_C1B0,{4U,0U,0U}}, +{AND_C1B0,{5U,0U,0U}}, +{AND_C1B0,{6U,0U,0U}}, +{AND_C1B0,{7U,0U,0U}}, +{AND_C1B8,{0U,0U,0U}}, +{AND_C1B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1C0,{0U,0U,0U}}, +{MULS_C1C0,{1U,0U,0U}}, +{MULS_C1C0,{2U,0U,0U}}, +{MULS_C1C0,{3U,0U,0U}}, +{MULS_C1C0,{4U,0U,0U}}, +{MULS_C1C0,{5U,0U,0U}}, +{MULS_C1C0,{6U,0U,0U}}, +{MULS_C1C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1D0,{0U,0U,0U}}, +{MULS_C1D0,{1U,0U,0U}}, +{MULS_C1D0,{2U,0U,0U}}, +{MULS_C1D0,{3U,0U,0U}}, +{MULS_C1D0,{4U,0U,0U}}, +{MULS_C1D0,{5U,0U,0U}}, +{MULS_C1D0,{6U,0U,0U}}, +{MULS_C1D0,{7U,0U,0U}}, +{MULS_C1D8,{0U,0U,0U}}, +{MULS_C1D8,{1U,0U,0U}}, +{MULS_C1D8,{2U,0U,0U}}, +{MULS_C1D8,{3U,0U,0U}}, +{MULS_C1D8,{4U,0U,0U}}, +{MULS_C1D8,{5U,0U,0U}}, +{MULS_C1D8,{6U,0U,0U}}, +{MULS_C1D8,{7U,0U,0U}}, +{MULS_C1E0,{0U,0U,0U}}, +{MULS_C1E0,{1U,0U,0U}}, +{MULS_C1E0,{2U,0U,0U}}, +{MULS_C1E0,{3U,0U,0U}}, +{MULS_C1E0,{4U,0U,0U}}, +{MULS_C1E0,{5U,0U,0U}}, +{MULS_C1E0,{6U,0U,0U}}, +{MULS_C1E0,{7U,0U,0U}}, +{MULS_C1E8,{0U,0U,0U}}, +{MULS_C1E8,{1U,0U,0U}}, +{MULS_C1E8,{2U,0U,0U}}, +{MULS_C1E8,{3U,0U,0U}}, +{MULS_C1E8,{4U,0U,0U}}, +{MULS_C1E8,{5U,0U,0U}}, +{MULS_C1E8,{6U,0U,0U}}, +{MULS_C1E8,{7U,0U,0U}}, +{MULS_C1F0,{0U,0U,0U}}, +{MULS_C1F0,{1U,0U,0U}}, +{MULS_C1F0,{2U,0U,0U}}, +{MULS_C1F0,{3U,0U,0U}}, +{MULS_C1F0,{4U,0U,0U}}, +{MULS_C1F0,{5U,0U,0U}}, +{MULS_C1F0,{6U,0U,0U}}, +{MULS_C1F0,{7U,0U,0U}}, +{MULS_C1F8,{0U,0U,0U}}, +{MULS_C1F9,{0U,0U,0U}}, +{MULS_C1FA,{0U,0U,0U}}, +{MULS_C1FB,{0U,0U,0U}}, +{MULS_C1FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C000,{0U,1U,0U}}, +{AND_C000,{1U,1U,0U}}, +{AND_C000,{2U,1U,0U}}, +{AND_C000,{3U,1U,0U}}, +{AND_C000,{4U,1U,0U}}, +{AND_C000,{5U,1U,0U}}, +{AND_C000,{6U,1U,0U}}, +{AND_C000,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C010,{0U,1U,0U}}, +{AND_C010,{1U,1U,0U}}, +{AND_C010,{2U,1U,0U}}, +{AND_C010,{3U,1U,0U}}, +{AND_C010,{4U,1U,0U}}, +{AND_C010,{5U,1U,0U}}, +{AND_C010,{6U,1U,0U}}, +{AND_C010,{7U,1U,0U}}, +{AND_C018,{0U,1U,0U}}, +{AND_C018,{1U,1U,0U}}, +{AND_C018,{2U,1U,0U}}, +{AND_C018,{3U,1U,0U}}, +{AND_C018,{4U,1U,0U}}, +{AND_C018,{5U,1U,0U}}, +{AND_C018,{6U,1U,0U}}, +{AND_C018,{7U,1U,0U}}, +{AND_C020,{0U,1U,0U}}, +{AND_C020,{1U,1U,0U}}, +{AND_C020,{2U,1U,0U}}, +{AND_C020,{3U,1U,0U}}, +{AND_C020,{4U,1U,0U}}, +{AND_C020,{5U,1U,0U}}, +{AND_C020,{6U,1U,0U}}, +{AND_C020,{7U,1U,0U}}, +{AND_C028,{0U,1U,0U}}, +{AND_C028,{1U,1U,0U}}, +{AND_C028,{2U,1U,0U}}, +{AND_C028,{3U,1U,0U}}, +{AND_C028,{4U,1U,0U}}, +{AND_C028,{5U,1U,0U}}, +{AND_C028,{6U,1U,0U}}, +{AND_C028,{7U,1U,0U}}, +{AND_C030,{0U,1U,0U}}, +{AND_C030,{1U,1U,0U}}, +{AND_C030,{2U,1U,0U}}, +{AND_C030,{3U,1U,0U}}, +{AND_C030,{4U,1U,0U}}, +{AND_C030,{5U,1U,0U}}, +{AND_C030,{6U,1U,0U}}, +{AND_C030,{7U,1U,0U}}, +{AND_C038,{0U,1U,0U}}, +{AND_C039,{0U,1U,0U}}, +{AND_C03A,{0U,1U,0U}}, +{AND_C03B,{0U,1U,0U}}, +{AND_C03C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C040,{0U,1U,0U}}, +{AND_C040,{1U,1U,0U}}, +{AND_C040,{2U,1U,0U}}, +{AND_C040,{3U,1U,0U}}, +{AND_C040,{4U,1U,0U}}, +{AND_C040,{5U,1U,0U}}, +{AND_C040,{6U,1U,0U}}, +{AND_C040,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C050,{0U,1U,0U}}, +{AND_C050,{1U,1U,0U}}, +{AND_C050,{2U,1U,0U}}, +{AND_C050,{3U,1U,0U}}, +{AND_C050,{4U,1U,0U}}, +{AND_C050,{5U,1U,0U}}, +{AND_C050,{6U,1U,0U}}, +{AND_C050,{7U,1U,0U}}, +{AND_C058,{0U,1U,0U}}, +{AND_C058,{1U,1U,0U}}, +{AND_C058,{2U,1U,0U}}, +{AND_C058,{3U,1U,0U}}, +{AND_C058,{4U,1U,0U}}, +{AND_C058,{5U,1U,0U}}, +{AND_C058,{6U,1U,0U}}, +{AND_C058,{7U,1U,0U}}, +{AND_C060,{0U,1U,0U}}, +{AND_C060,{1U,1U,0U}}, +{AND_C060,{2U,1U,0U}}, +{AND_C060,{3U,1U,0U}}, +{AND_C060,{4U,1U,0U}}, +{AND_C060,{5U,1U,0U}}, +{AND_C060,{6U,1U,0U}}, +{AND_C060,{7U,1U,0U}}, +{AND_C068,{0U,1U,0U}}, +{AND_C068,{1U,1U,0U}}, +{AND_C068,{2U,1U,0U}}, +{AND_C068,{3U,1U,0U}}, +{AND_C068,{4U,1U,0U}}, +{AND_C068,{5U,1U,0U}}, +{AND_C068,{6U,1U,0U}}, +{AND_C068,{7U,1U,0U}}, +{AND_C070,{0U,1U,0U}}, +{AND_C070,{1U,1U,0U}}, +{AND_C070,{2U,1U,0U}}, +{AND_C070,{3U,1U,0U}}, +{AND_C070,{4U,1U,0U}}, +{AND_C070,{5U,1U,0U}}, +{AND_C070,{6U,1U,0U}}, +{AND_C070,{7U,1U,0U}}, +{AND_C078,{0U,1U,0U}}, +{AND_C079,{0U,1U,0U}}, +{AND_C07A,{0U,1U,0U}}, +{AND_C07B,{0U,1U,0U}}, +{AND_C07C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C080,{0U,1U,0U}}, +{AND_C080,{1U,1U,0U}}, +{AND_C080,{2U,1U,0U}}, +{AND_C080,{3U,1U,0U}}, +{AND_C080,{4U,1U,0U}}, +{AND_C080,{5U,1U,0U}}, +{AND_C080,{6U,1U,0U}}, +{AND_C080,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C090,{0U,1U,0U}}, +{AND_C090,{1U,1U,0U}}, +{AND_C090,{2U,1U,0U}}, +{AND_C090,{3U,1U,0U}}, +{AND_C090,{4U,1U,0U}}, +{AND_C090,{5U,1U,0U}}, +{AND_C090,{6U,1U,0U}}, +{AND_C090,{7U,1U,0U}}, +{AND_C098,{0U,1U,0U}}, +{AND_C098,{1U,1U,0U}}, +{AND_C098,{2U,1U,0U}}, +{AND_C098,{3U,1U,0U}}, +{AND_C098,{4U,1U,0U}}, +{AND_C098,{5U,1U,0U}}, +{AND_C098,{6U,1U,0U}}, +{AND_C098,{7U,1U,0U}}, +{AND_C0A0,{0U,1U,0U}}, +{AND_C0A0,{1U,1U,0U}}, +{AND_C0A0,{2U,1U,0U}}, +{AND_C0A0,{3U,1U,0U}}, +{AND_C0A0,{4U,1U,0U}}, +{AND_C0A0,{5U,1U,0U}}, +{AND_C0A0,{6U,1U,0U}}, +{AND_C0A0,{7U,1U,0U}}, +{AND_C0A8,{0U,1U,0U}}, +{AND_C0A8,{1U,1U,0U}}, +{AND_C0A8,{2U,1U,0U}}, +{AND_C0A8,{3U,1U,0U}}, +{AND_C0A8,{4U,1U,0U}}, +{AND_C0A8,{5U,1U,0U}}, +{AND_C0A8,{6U,1U,0U}}, +{AND_C0A8,{7U,1U,0U}}, +{AND_C0B0,{0U,1U,0U}}, +{AND_C0B0,{1U,1U,0U}}, +{AND_C0B0,{2U,1U,0U}}, +{AND_C0B0,{3U,1U,0U}}, +{AND_C0B0,{4U,1U,0U}}, +{AND_C0B0,{5U,1U,0U}}, +{AND_C0B0,{6U,1U,0U}}, +{AND_C0B0,{7U,1U,0U}}, +{AND_C0B8,{0U,1U,0U}}, +{AND_C0B9,{0U,1U,0U}}, +{AND_C0BA,{0U,1U,0U}}, +{AND_C0BB,{0U,1U,0U}}, +{AND_C0BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0C0,{0U,1U,0U}}, +{MULU_C0C0,{1U,1U,0U}}, +{MULU_C0C0,{2U,1U,0U}}, +{MULU_C0C0,{3U,1U,0U}}, +{MULU_C0C0,{4U,1U,0U}}, +{MULU_C0C0,{5U,1U,0U}}, +{MULU_C0C0,{6U,1U,0U}}, +{MULU_C0C0,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0D0,{0U,1U,0U}}, +{MULU_C0D0,{1U,1U,0U}}, +{MULU_C0D0,{2U,1U,0U}}, +{MULU_C0D0,{3U,1U,0U}}, +{MULU_C0D0,{4U,1U,0U}}, +{MULU_C0D0,{5U,1U,0U}}, +{MULU_C0D0,{6U,1U,0U}}, +{MULU_C0D0,{7U,1U,0U}}, +{MULU_C0D8,{0U,1U,0U}}, +{MULU_C0D8,{1U,1U,0U}}, +{MULU_C0D8,{2U,1U,0U}}, +{MULU_C0D8,{3U,1U,0U}}, +{MULU_C0D8,{4U,1U,0U}}, +{MULU_C0D8,{5U,1U,0U}}, +{MULU_C0D8,{6U,1U,0U}}, +{MULU_C0D8,{7U,1U,0U}}, +{MULU_C0E0,{0U,1U,0U}}, +{MULU_C0E0,{1U,1U,0U}}, +{MULU_C0E0,{2U,1U,0U}}, +{MULU_C0E0,{3U,1U,0U}}, +{MULU_C0E0,{4U,1U,0U}}, +{MULU_C0E0,{5U,1U,0U}}, +{MULU_C0E0,{6U,1U,0U}}, +{MULU_C0E0,{7U,1U,0U}}, +{MULU_C0E8,{0U,1U,0U}}, +{MULU_C0E8,{1U,1U,0U}}, +{MULU_C0E8,{2U,1U,0U}}, +{MULU_C0E8,{3U,1U,0U}}, +{MULU_C0E8,{4U,1U,0U}}, +{MULU_C0E8,{5U,1U,0U}}, +{MULU_C0E8,{6U,1U,0U}}, +{MULU_C0E8,{7U,1U,0U}}, +{MULU_C0F0,{0U,1U,0U}}, +{MULU_C0F0,{1U,1U,0U}}, +{MULU_C0F0,{2U,1U,0U}}, +{MULU_C0F0,{3U,1U,0U}}, +{MULU_C0F0,{4U,1U,0U}}, +{MULU_C0F0,{5U,1U,0U}}, +{MULU_C0F0,{6U,1U,0U}}, +{MULU_C0F0,{7U,1U,0U}}, +{MULU_C0F8,{0U,1U,0U}}, +{MULU_C0F9,{0U,1U,0U}}, +{MULU_C0FA,{0U,1U,0U}}, +{MULU_C0FB,{0U,1U,0U}}, +{MULU_C0FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ABCD_C100,{0U,1U,0U}}, +{ABCD_C100,{1U,1U,0U}}, +{ABCD_C100,{2U,1U,0U}}, +{ABCD_C100,{3U,1U,0U}}, +{ABCD_C100,{4U,1U,0U}}, +{ABCD_C100,{5U,1U,0U}}, +{ABCD_C100,{6U,1U,0U}}, +{ABCD_C100,{7U,1U,0U}}, +{ABCD_C108,{0U,1U,0U}}, +{ABCD_C108,{1U,1U,0U}}, +{ABCD_C108,{2U,1U,0U}}, +{ABCD_C108,{3U,1U,0U}}, +{ABCD_C108,{4U,1U,0U}}, +{ABCD_C108,{5U,1U,0U}}, +{ABCD_C108,{6U,1U,0U}}, +{ABCD_C108,{7U,1U,0U}}, +{AND_C110,{0U,1U,0U}}, +{AND_C110,{1U,1U,0U}}, +{AND_C110,{2U,1U,0U}}, +{AND_C110,{3U,1U,0U}}, +{AND_C110,{4U,1U,0U}}, +{AND_C110,{5U,1U,0U}}, +{AND_C110,{6U,1U,0U}}, +{AND_C110,{7U,1U,0U}}, +{AND_C118,{0U,1U,0U}}, +{AND_C118,{1U,1U,0U}}, +{AND_C118,{2U,1U,0U}}, +{AND_C118,{3U,1U,0U}}, +{AND_C118,{4U,1U,0U}}, +{AND_C118,{5U,1U,0U}}, +{AND_C118,{6U,1U,0U}}, +{AND_C118,{7U,1U,0U}}, +{AND_C120,{0U,1U,0U}}, +{AND_C120,{1U,1U,0U}}, +{AND_C120,{2U,1U,0U}}, +{AND_C120,{3U,1U,0U}}, +{AND_C120,{4U,1U,0U}}, +{AND_C120,{5U,1U,0U}}, +{AND_C120,{6U,1U,0U}}, +{AND_C120,{7U,1U,0U}}, +{AND_C128,{0U,1U,0U}}, +{AND_C128,{1U,1U,0U}}, +{AND_C128,{2U,1U,0U}}, +{AND_C128,{3U,1U,0U}}, +{AND_C128,{4U,1U,0U}}, +{AND_C128,{5U,1U,0U}}, +{AND_C128,{6U,1U,0U}}, +{AND_C128,{7U,1U,0U}}, +{AND_C130,{0U,1U,0U}}, +{AND_C130,{1U,1U,0U}}, +{AND_C130,{2U,1U,0U}}, +{AND_C130,{3U,1U,0U}}, +{AND_C130,{4U,1U,0U}}, +{AND_C130,{5U,1U,0U}}, +{AND_C130,{6U,1U,0U}}, +{AND_C130,{7U,1U,0U}}, +{AND_C138,{0U,1U,0U}}, +{AND_C139,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C140,{1U,0U,0U}}, +{EXG_C140,{1U,1U,0U}}, +{EXG_C140,{1U,2U,0U}}, +{EXG_C140,{1U,3U,0U}}, +{EXG_C140,{1U,4U,0U}}, +{EXG_C140,{1U,5U,0U}}, +{EXG_C140,{1U,6U,0U}}, +{EXG_C140,{1U,7U,0U}}, +{EXG_C148,{1U,0U,0U}}, +{EXG_C148,{1U,1U,0U}}, +{EXG_C148,{1U,2U,0U}}, +{EXG_C148,{1U,3U,0U}}, +{EXG_C148,{1U,4U,0U}}, +{EXG_C148,{1U,5U,0U}}, +{EXG_C148,{1U,6U,0U}}, +{EXG_C148,{1U,7U,0U}}, +{AND_C150,{0U,1U,0U}}, +{AND_C150,{1U,1U,0U}}, +{AND_C150,{2U,1U,0U}}, +{AND_C150,{3U,1U,0U}}, +{AND_C150,{4U,1U,0U}}, +{AND_C150,{5U,1U,0U}}, +{AND_C150,{6U,1U,0U}}, +{AND_C150,{7U,1U,0U}}, +{AND_C158,{0U,1U,0U}}, +{AND_C158,{1U,1U,0U}}, +{AND_C158,{2U,1U,0U}}, +{AND_C158,{3U,1U,0U}}, +{AND_C158,{4U,1U,0U}}, +{AND_C158,{5U,1U,0U}}, +{AND_C158,{6U,1U,0U}}, +{AND_C158,{7U,1U,0U}}, +{AND_C160,{0U,1U,0U}}, +{AND_C160,{1U,1U,0U}}, +{AND_C160,{2U,1U,0U}}, +{AND_C160,{3U,1U,0U}}, +{AND_C160,{4U,1U,0U}}, +{AND_C160,{5U,1U,0U}}, +{AND_C160,{6U,1U,0U}}, +{AND_C160,{7U,1U,0U}}, +{AND_C168,{0U,1U,0U}}, +{AND_C168,{1U,1U,0U}}, +{AND_C168,{2U,1U,0U}}, +{AND_C168,{3U,1U,0U}}, +{AND_C168,{4U,1U,0U}}, +{AND_C168,{5U,1U,0U}}, +{AND_C168,{6U,1U,0U}}, +{AND_C168,{7U,1U,0U}}, +{AND_C170,{0U,1U,0U}}, +{AND_C170,{1U,1U,0U}}, +{AND_C170,{2U,1U,0U}}, +{AND_C170,{3U,1U,0U}}, +{AND_C170,{4U,1U,0U}}, +{AND_C170,{5U,1U,0U}}, +{AND_C170,{6U,1U,0U}}, +{AND_C170,{7U,1U,0U}}, +{AND_C178,{0U,1U,0U}}, +{AND_C179,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C188,{1U,0U,0U}}, +{EXG_C188,{1U,1U,0U}}, +{EXG_C188,{1U,2U,0U}}, +{EXG_C188,{1U,3U,0U}}, +{EXG_C188,{1U,4U,0U}}, +{EXG_C188,{1U,5U,0U}}, +{EXG_C188,{1U,6U,0U}}, +{EXG_C188,{1U,7U,0U}}, +{AND_C190,{0U,1U,0U}}, +{AND_C190,{1U,1U,0U}}, +{AND_C190,{2U,1U,0U}}, +{AND_C190,{3U,1U,0U}}, +{AND_C190,{4U,1U,0U}}, +{AND_C190,{5U,1U,0U}}, +{AND_C190,{6U,1U,0U}}, +{AND_C190,{7U,1U,0U}}, +{AND_C198,{0U,1U,0U}}, +{AND_C198,{1U,1U,0U}}, +{AND_C198,{2U,1U,0U}}, +{AND_C198,{3U,1U,0U}}, +{AND_C198,{4U,1U,0U}}, +{AND_C198,{5U,1U,0U}}, +{AND_C198,{6U,1U,0U}}, +{AND_C198,{7U,1U,0U}}, +{AND_C1A0,{0U,1U,0U}}, +{AND_C1A0,{1U,1U,0U}}, +{AND_C1A0,{2U,1U,0U}}, +{AND_C1A0,{3U,1U,0U}}, +{AND_C1A0,{4U,1U,0U}}, +{AND_C1A0,{5U,1U,0U}}, +{AND_C1A0,{6U,1U,0U}}, +{AND_C1A0,{7U,1U,0U}}, +{AND_C1A8,{0U,1U,0U}}, +{AND_C1A8,{1U,1U,0U}}, +{AND_C1A8,{2U,1U,0U}}, +{AND_C1A8,{3U,1U,0U}}, +{AND_C1A8,{4U,1U,0U}}, +{AND_C1A8,{5U,1U,0U}}, +{AND_C1A8,{6U,1U,0U}}, +{AND_C1A8,{7U,1U,0U}}, +{AND_C1B0,{0U,1U,0U}}, +{AND_C1B0,{1U,1U,0U}}, +{AND_C1B0,{2U,1U,0U}}, +{AND_C1B0,{3U,1U,0U}}, +{AND_C1B0,{4U,1U,0U}}, +{AND_C1B0,{5U,1U,0U}}, +{AND_C1B0,{6U,1U,0U}}, +{AND_C1B0,{7U,1U,0U}}, +{AND_C1B8,{0U,1U,0U}}, +{AND_C1B9,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1C0,{0U,1U,0U}}, +{MULS_C1C0,{1U,1U,0U}}, +{MULS_C1C0,{2U,1U,0U}}, +{MULS_C1C0,{3U,1U,0U}}, +{MULS_C1C0,{4U,1U,0U}}, +{MULS_C1C0,{5U,1U,0U}}, +{MULS_C1C0,{6U,1U,0U}}, +{MULS_C1C0,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1D0,{0U,1U,0U}}, +{MULS_C1D0,{1U,1U,0U}}, +{MULS_C1D0,{2U,1U,0U}}, +{MULS_C1D0,{3U,1U,0U}}, +{MULS_C1D0,{4U,1U,0U}}, +{MULS_C1D0,{5U,1U,0U}}, +{MULS_C1D0,{6U,1U,0U}}, +{MULS_C1D0,{7U,1U,0U}}, +{MULS_C1D8,{0U,1U,0U}}, +{MULS_C1D8,{1U,1U,0U}}, +{MULS_C1D8,{2U,1U,0U}}, +{MULS_C1D8,{3U,1U,0U}}, +{MULS_C1D8,{4U,1U,0U}}, +{MULS_C1D8,{5U,1U,0U}}, +{MULS_C1D8,{6U,1U,0U}}, +{MULS_C1D8,{7U,1U,0U}}, +{MULS_C1E0,{0U,1U,0U}}, +{MULS_C1E0,{1U,1U,0U}}, +{MULS_C1E0,{2U,1U,0U}}, +{MULS_C1E0,{3U,1U,0U}}, +{MULS_C1E0,{4U,1U,0U}}, +{MULS_C1E0,{5U,1U,0U}}, +{MULS_C1E0,{6U,1U,0U}}, +{MULS_C1E0,{7U,1U,0U}}, +{MULS_C1E8,{0U,1U,0U}}, +{MULS_C1E8,{1U,1U,0U}}, +{MULS_C1E8,{2U,1U,0U}}, +{MULS_C1E8,{3U,1U,0U}}, +{MULS_C1E8,{4U,1U,0U}}, +{MULS_C1E8,{5U,1U,0U}}, +{MULS_C1E8,{6U,1U,0U}}, +{MULS_C1E8,{7U,1U,0U}}, +{MULS_C1F0,{0U,1U,0U}}, +{MULS_C1F0,{1U,1U,0U}}, +{MULS_C1F0,{2U,1U,0U}}, +{MULS_C1F0,{3U,1U,0U}}, +{MULS_C1F0,{4U,1U,0U}}, +{MULS_C1F0,{5U,1U,0U}}, +{MULS_C1F0,{6U,1U,0U}}, +{MULS_C1F0,{7U,1U,0U}}, +{MULS_C1F8,{0U,1U,0U}}, +{MULS_C1F9,{0U,1U,0U}}, +{MULS_C1FA,{0U,1U,0U}}, +{MULS_C1FB,{0U,1U,0U}}, +{MULS_C1FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C000,{0U,2U,0U}}, +{AND_C000,{1U,2U,0U}}, +{AND_C000,{2U,2U,0U}}, +{AND_C000,{3U,2U,0U}}, +{AND_C000,{4U,2U,0U}}, +{AND_C000,{5U,2U,0U}}, +{AND_C000,{6U,2U,0U}}, +{AND_C000,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C010,{0U,2U,0U}}, +{AND_C010,{1U,2U,0U}}, +{AND_C010,{2U,2U,0U}}, +{AND_C010,{3U,2U,0U}}, +{AND_C010,{4U,2U,0U}}, +{AND_C010,{5U,2U,0U}}, +{AND_C010,{6U,2U,0U}}, +{AND_C010,{7U,2U,0U}}, +{AND_C018,{0U,2U,0U}}, +{AND_C018,{1U,2U,0U}}, +{AND_C018,{2U,2U,0U}}, +{AND_C018,{3U,2U,0U}}, +{AND_C018,{4U,2U,0U}}, +{AND_C018,{5U,2U,0U}}, +{AND_C018,{6U,2U,0U}}, +{AND_C018,{7U,2U,0U}}, +{AND_C020,{0U,2U,0U}}, +{AND_C020,{1U,2U,0U}}, +{AND_C020,{2U,2U,0U}}, +{AND_C020,{3U,2U,0U}}, +{AND_C020,{4U,2U,0U}}, +{AND_C020,{5U,2U,0U}}, +{AND_C020,{6U,2U,0U}}, +{AND_C020,{7U,2U,0U}}, +{AND_C028,{0U,2U,0U}}, +{AND_C028,{1U,2U,0U}}, +{AND_C028,{2U,2U,0U}}, +{AND_C028,{3U,2U,0U}}, +{AND_C028,{4U,2U,0U}}, +{AND_C028,{5U,2U,0U}}, +{AND_C028,{6U,2U,0U}}, +{AND_C028,{7U,2U,0U}}, +{AND_C030,{0U,2U,0U}}, +{AND_C030,{1U,2U,0U}}, +{AND_C030,{2U,2U,0U}}, +{AND_C030,{3U,2U,0U}}, +{AND_C030,{4U,2U,0U}}, +{AND_C030,{5U,2U,0U}}, +{AND_C030,{6U,2U,0U}}, +{AND_C030,{7U,2U,0U}}, +{AND_C038,{0U,2U,0U}}, +{AND_C039,{0U,2U,0U}}, +{AND_C03A,{0U,2U,0U}}, +{AND_C03B,{0U,2U,0U}}, +{AND_C03C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C040,{0U,2U,0U}}, +{AND_C040,{1U,2U,0U}}, +{AND_C040,{2U,2U,0U}}, +{AND_C040,{3U,2U,0U}}, +{AND_C040,{4U,2U,0U}}, +{AND_C040,{5U,2U,0U}}, +{AND_C040,{6U,2U,0U}}, +{AND_C040,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C050,{0U,2U,0U}}, +{AND_C050,{1U,2U,0U}}, +{AND_C050,{2U,2U,0U}}, +{AND_C050,{3U,2U,0U}}, +{AND_C050,{4U,2U,0U}}, +{AND_C050,{5U,2U,0U}}, +{AND_C050,{6U,2U,0U}}, +{AND_C050,{7U,2U,0U}}, +{AND_C058,{0U,2U,0U}}, +{AND_C058,{1U,2U,0U}}, +{AND_C058,{2U,2U,0U}}, +{AND_C058,{3U,2U,0U}}, +{AND_C058,{4U,2U,0U}}, +{AND_C058,{5U,2U,0U}}, +{AND_C058,{6U,2U,0U}}, +{AND_C058,{7U,2U,0U}}, +{AND_C060,{0U,2U,0U}}, +{AND_C060,{1U,2U,0U}}, +{AND_C060,{2U,2U,0U}}, +{AND_C060,{3U,2U,0U}}, +{AND_C060,{4U,2U,0U}}, +{AND_C060,{5U,2U,0U}}, +{AND_C060,{6U,2U,0U}}, +{AND_C060,{7U,2U,0U}}, +{AND_C068,{0U,2U,0U}}, +{AND_C068,{1U,2U,0U}}, +{AND_C068,{2U,2U,0U}}, +{AND_C068,{3U,2U,0U}}, +{AND_C068,{4U,2U,0U}}, +{AND_C068,{5U,2U,0U}}, +{AND_C068,{6U,2U,0U}}, +{AND_C068,{7U,2U,0U}}, +{AND_C070,{0U,2U,0U}}, +{AND_C070,{1U,2U,0U}}, +{AND_C070,{2U,2U,0U}}, +{AND_C070,{3U,2U,0U}}, +{AND_C070,{4U,2U,0U}}, +{AND_C070,{5U,2U,0U}}, +{AND_C070,{6U,2U,0U}}, +{AND_C070,{7U,2U,0U}}, +{AND_C078,{0U,2U,0U}}, +{AND_C079,{0U,2U,0U}}, +{AND_C07A,{0U,2U,0U}}, +{AND_C07B,{0U,2U,0U}}, +{AND_C07C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C080,{0U,2U,0U}}, +{AND_C080,{1U,2U,0U}}, +{AND_C080,{2U,2U,0U}}, +{AND_C080,{3U,2U,0U}}, +{AND_C080,{4U,2U,0U}}, +{AND_C080,{5U,2U,0U}}, +{AND_C080,{6U,2U,0U}}, +{AND_C080,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C090,{0U,2U,0U}}, +{AND_C090,{1U,2U,0U}}, +{AND_C090,{2U,2U,0U}}, +{AND_C090,{3U,2U,0U}}, +{AND_C090,{4U,2U,0U}}, +{AND_C090,{5U,2U,0U}}, +{AND_C090,{6U,2U,0U}}, +{AND_C090,{7U,2U,0U}}, +{AND_C098,{0U,2U,0U}}, +{AND_C098,{1U,2U,0U}}, +{AND_C098,{2U,2U,0U}}, +{AND_C098,{3U,2U,0U}}, +{AND_C098,{4U,2U,0U}}, +{AND_C098,{5U,2U,0U}}, +{AND_C098,{6U,2U,0U}}, +{AND_C098,{7U,2U,0U}}, +{AND_C0A0,{0U,2U,0U}}, +{AND_C0A0,{1U,2U,0U}}, +{AND_C0A0,{2U,2U,0U}}, +{AND_C0A0,{3U,2U,0U}}, +{AND_C0A0,{4U,2U,0U}}, +{AND_C0A0,{5U,2U,0U}}, +{AND_C0A0,{6U,2U,0U}}, +{AND_C0A0,{7U,2U,0U}}, +{AND_C0A8,{0U,2U,0U}}, +{AND_C0A8,{1U,2U,0U}}, +{AND_C0A8,{2U,2U,0U}}, +{AND_C0A8,{3U,2U,0U}}, +{AND_C0A8,{4U,2U,0U}}, +{AND_C0A8,{5U,2U,0U}}, +{AND_C0A8,{6U,2U,0U}}, +{AND_C0A8,{7U,2U,0U}}, +{AND_C0B0,{0U,2U,0U}}, +{AND_C0B0,{1U,2U,0U}}, +{AND_C0B0,{2U,2U,0U}}, +{AND_C0B0,{3U,2U,0U}}, +{AND_C0B0,{4U,2U,0U}}, +{AND_C0B0,{5U,2U,0U}}, +{AND_C0B0,{6U,2U,0U}}, +{AND_C0B0,{7U,2U,0U}}, +{AND_C0B8,{0U,2U,0U}}, +{AND_C0B9,{0U,2U,0U}}, +{AND_C0BA,{0U,2U,0U}}, +{AND_C0BB,{0U,2U,0U}}, +{AND_C0BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0C0,{0U,2U,0U}}, +{MULU_C0C0,{1U,2U,0U}}, +{MULU_C0C0,{2U,2U,0U}}, +{MULU_C0C0,{3U,2U,0U}}, +{MULU_C0C0,{4U,2U,0U}}, +{MULU_C0C0,{5U,2U,0U}}, +{MULU_C0C0,{6U,2U,0U}}, +{MULU_C0C0,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0D0,{0U,2U,0U}}, +{MULU_C0D0,{1U,2U,0U}}, +{MULU_C0D0,{2U,2U,0U}}, +{MULU_C0D0,{3U,2U,0U}}, +{MULU_C0D0,{4U,2U,0U}}, +{MULU_C0D0,{5U,2U,0U}}, +{MULU_C0D0,{6U,2U,0U}}, +{MULU_C0D0,{7U,2U,0U}}, +{MULU_C0D8,{0U,2U,0U}}, +{MULU_C0D8,{1U,2U,0U}}, +{MULU_C0D8,{2U,2U,0U}}, +{MULU_C0D8,{3U,2U,0U}}, +{MULU_C0D8,{4U,2U,0U}}, +{MULU_C0D8,{5U,2U,0U}}, +{MULU_C0D8,{6U,2U,0U}}, +{MULU_C0D8,{7U,2U,0U}}, +{MULU_C0E0,{0U,2U,0U}}, +{MULU_C0E0,{1U,2U,0U}}, +{MULU_C0E0,{2U,2U,0U}}, +{MULU_C0E0,{3U,2U,0U}}, +{MULU_C0E0,{4U,2U,0U}}, +{MULU_C0E0,{5U,2U,0U}}, +{MULU_C0E0,{6U,2U,0U}}, +{MULU_C0E0,{7U,2U,0U}}, +{MULU_C0E8,{0U,2U,0U}}, +{MULU_C0E8,{1U,2U,0U}}, +{MULU_C0E8,{2U,2U,0U}}, +{MULU_C0E8,{3U,2U,0U}}, +{MULU_C0E8,{4U,2U,0U}}, +{MULU_C0E8,{5U,2U,0U}}, +{MULU_C0E8,{6U,2U,0U}}, +{MULU_C0E8,{7U,2U,0U}}, +{MULU_C0F0,{0U,2U,0U}}, +{MULU_C0F0,{1U,2U,0U}}, +{MULU_C0F0,{2U,2U,0U}}, +{MULU_C0F0,{3U,2U,0U}}, +{MULU_C0F0,{4U,2U,0U}}, +{MULU_C0F0,{5U,2U,0U}}, +{MULU_C0F0,{6U,2U,0U}}, +{MULU_C0F0,{7U,2U,0U}}, +{MULU_C0F8,{0U,2U,0U}}, +{MULU_C0F9,{0U,2U,0U}}, +{MULU_C0FA,{0U,2U,0U}}, +{MULU_C0FB,{0U,2U,0U}}, +{MULU_C0FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ABCD_C100,{0U,2U,0U}}, +{ABCD_C100,{1U,2U,0U}}, +{ABCD_C100,{2U,2U,0U}}, +{ABCD_C100,{3U,2U,0U}}, +{ABCD_C100,{4U,2U,0U}}, +{ABCD_C100,{5U,2U,0U}}, +{ABCD_C100,{6U,2U,0U}}, +{ABCD_C100,{7U,2U,0U}}, +{ABCD_C108,{0U,2U,0U}}, +{ABCD_C108,{1U,2U,0U}}, +{ABCD_C108,{2U,2U,0U}}, +{ABCD_C108,{3U,2U,0U}}, +{ABCD_C108,{4U,2U,0U}}, +{ABCD_C108,{5U,2U,0U}}, +{ABCD_C108,{6U,2U,0U}}, +{ABCD_C108,{7U,2U,0U}}, +{AND_C110,{0U,2U,0U}}, +{AND_C110,{1U,2U,0U}}, +{AND_C110,{2U,2U,0U}}, +{AND_C110,{3U,2U,0U}}, +{AND_C110,{4U,2U,0U}}, +{AND_C110,{5U,2U,0U}}, +{AND_C110,{6U,2U,0U}}, +{AND_C110,{7U,2U,0U}}, +{AND_C118,{0U,2U,0U}}, +{AND_C118,{1U,2U,0U}}, +{AND_C118,{2U,2U,0U}}, +{AND_C118,{3U,2U,0U}}, +{AND_C118,{4U,2U,0U}}, +{AND_C118,{5U,2U,0U}}, +{AND_C118,{6U,2U,0U}}, +{AND_C118,{7U,2U,0U}}, +{AND_C120,{0U,2U,0U}}, +{AND_C120,{1U,2U,0U}}, +{AND_C120,{2U,2U,0U}}, +{AND_C120,{3U,2U,0U}}, +{AND_C120,{4U,2U,0U}}, +{AND_C120,{5U,2U,0U}}, +{AND_C120,{6U,2U,0U}}, +{AND_C120,{7U,2U,0U}}, +{AND_C128,{0U,2U,0U}}, +{AND_C128,{1U,2U,0U}}, +{AND_C128,{2U,2U,0U}}, +{AND_C128,{3U,2U,0U}}, +{AND_C128,{4U,2U,0U}}, +{AND_C128,{5U,2U,0U}}, +{AND_C128,{6U,2U,0U}}, +{AND_C128,{7U,2U,0U}}, +{AND_C130,{0U,2U,0U}}, +{AND_C130,{1U,2U,0U}}, +{AND_C130,{2U,2U,0U}}, +{AND_C130,{3U,2U,0U}}, +{AND_C130,{4U,2U,0U}}, +{AND_C130,{5U,2U,0U}}, +{AND_C130,{6U,2U,0U}}, +{AND_C130,{7U,2U,0U}}, +{AND_C138,{0U,2U,0U}}, +{AND_C139,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C140,{2U,0U,0U}}, +{EXG_C140,{2U,1U,0U}}, +{EXG_C140,{2U,2U,0U}}, +{EXG_C140,{2U,3U,0U}}, +{EXG_C140,{2U,4U,0U}}, +{EXG_C140,{2U,5U,0U}}, +{EXG_C140,{2U,6U,0U}}, +{EXG_C140,{2U,7U,0U}}, +{EXG_C148,{2U,0U,0U}}, +{EXG_C148,{2U,1U,0U}}, +{EXG_C148,{2U,2U,0U}}, +{EXG_C148,{2U,3U,0U}}, +{EXG_C148,{2U,4U,0U}}, +{EXG_C148,{2U,5U,0U}}, +{EXG_C148,{2U,6U,0U}}, +{EXG_C148,{2U,7U,0U}}, +{AND_C150,{0U,2U,0U}}, +{AND_C150,{1U,2U,0U}}, +{AND_C150,{2U,2U,0U}}, +{AND_C150,{3U,2U,0U}}, +{AND_C150,{4U,2U,0U}}, +{AND_C150,{5U,2U,0U}}, +{AND_C150,{6U,2U,0U}}, +{AND_C150,{7U,2U,0U}}, +{AND_C158,{0U,2U,0U}}, +{AND_C158,{1U,2U,0U}}, +{AND_C158,{2U,2U,0U}}, +{AND_C158,{3U,2U,0U}}, +{AND_C158,{4U,2U,0U}}, +{AND_C158,{5U,2U,0U}}, +{AND_C158,{6U,2U,0U}}, +{AND_C158,{7U,2U,0U}}, +{AND_C160,{0U,2U,0U}}, +{AND_C160,{1U,2U,0U}}, +{AND_C160,{2U,2U,0U}}, +{AND_C160,{3U,2U,0U}}, +{AND_C160,{4U,2U,0U}}, +{AND_C160,{5U,2U,0U}}, +{AND_C160,{6U,2U,0U}}, +{AND_C160,{7U,2U,0U}}, +{AND_C168,{0U,2U,0U}}, +{AND_C168,{1U,2U,0U}}, +{AND_C168,{2U,2U,0U}}, +{AND_C168,{3U,2U,0U}}, +{AND_C168,{4U,2U,0U}}, +{AND_C168,{5U,2U,0U}}, +{AND_C168,{6U,2U,0U}}, +{AND_C168,{7U,2U,0U}}, +{AND_C170,{0U,2U,0U}}, +{AND_C170,{1U,2U,0U}}, +{AND_C170,{2U,2U,0U}}, +{AND_C170,{3U,2U,0U}}, +{AND_C170,{4U,2U,0U}}, +{AND_C170,{5U,2U,0U}}, +{AND_C170,{6U,2U,0U}}, +{AND_C170,{7U,2U,0U}}, +{AND_C178,{0U,2U,0U}}, +{AND_C179,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C188,{2U,0U,0U}}, +{EXG_C188,{2U,1U,0U}}, +{EXG_C188,{2U,2U,0U}}, +{EXG_C188,{2U,3U,0U}}, +{EXG_C188,{2U,4U,0U}}, +{EXG_C188,{2U,5U,0U}}, +{EXG_C188,{2U,6U,0U}}, +{EXG_C188,{2U,7U,0U}}, +{AND_C190,{0U,2U,0U}}, +{AND_C190,{1U,2U,0U}}, +{AND_C190,{2U,2U,0U}}, +{AND_C190,{3U,2U,0U}}, +{AND_C190,{4U,2U,0U}}, +{AND_C190,{5U,2U,0U}}, +{AND_C190,{6U,2U,0U}}, +{AND_C190,{7U,2U,0U}}, +{AND_C198,{0U,2U,0U}}, +{AND_C198,{1U,2U,0U}}, +{AND_C198,{2U,2U,0U}}, +{AND_C198,{3U,2U,0U}}, +{AND_C198,{4U,2U,0U}}, +{AND_C198,{5U,2U,0U}}, +{AND_C198,{6U,2U,0U}}, +{AND_C198,{7U,2U,0U}}, +{AND_C1A0,{0U,2U,0U}}, +{AND_C1A0,{1U,2U,0U}}, +{AND_C1A0,{2U,2U,0U}}, +{AND_C1A0,{3U,2U,0U}}, +{AND_C1A0,{4U,2U,0U}}, +{AND_C1A0,{5U,2U,0U}}, +{AND_C1A0,{6U,2U,0U}}, +{AND_C1A0,{7U,2U,0U}}, +{AND_C1A8,{0U,2U,0U}}, +{AND_C1A8,{1U,2U,0U}}, +{AND_C1A8,{2U,2U,0U}}, +{AND_C1A8,{3U,2U,0U}}, +{AND_C1A8,{4U,2U,0U}}, +{AND_C1A8,{5U,2U,0U}}, +{AND_C1A8,{6U,2U,0U}}, +{AND_C1A8,{7U,2U,0U}}, +{AND_C1B0,{0U,2U,0U}}, +{AND_C1B0,{1U,2U,0U}}, +{AND_C1B0,{2U,2U,0U}}, +{AND_C1B0,{3U,2U,0U}}, +{AND_C1B0,{4U,2U,0U}}, +{AND_C1B0,{5U,2U,0U}}, +{AND_C1B0,{6U,2U,0U}}, +{AND_C1B0,{7U,2U,0U}}, +{AND_C1B8,{0U,2U,0U}}, +{AND_C1B9,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1C0,{0U,2U,0U}}, +{MULS_C1C0,{1U,2U,0U}}, +{MULS_C1C0,{2U,2U,0U}}, +{MULS_C1C0,{3U,2U,0U}}, +{MULS_C1C0,{4U,2U,0U}}, +{MULS_C1C0,{5U,2U,0U}}, +{MULS_C1C0,{6U,2U,0U}}, +{MULS_C1C0,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1D0,{0U,2U,0U}}, +{MULS_C1D0,{1U,2U,0U}}, +{MULS_C1D0,{2U,2U,0U}}, +{MULS_C1D0,{3U,2U,0U}}, +{MULS_C1D0,{4U,2U,0U}}, +{MULS_C1D0,{5U,2U,0U}}, +{MULS_C1D0,{6U,2U,0U}}, +{MULS_C1D0,{7U,2U,0U}}, +{MULS_C1D8,{0U,2U,0U}}, +{MULS_C1D8,{1U,2U,0U}}, +{MULS_C1D8,{2U,2U,0U}}, +{MULS_C1D8,{3U,2U,0U}}, +{MULS_C1D8,{4U,2U,0U}}, +{MULS_C1D8,{5U,2U,0U}}, +{MULS_C1D8,{6U,2U,0U}}, +{MULS_C1D8,{7U,2U,0U}}, +{MULS_C1E0,{0U,2U,0U}}, +{MULS_C1E0,{1U,2U,0U}}, +{MULS_C1E0,{2U,2U,0U}}, +{MULS_C1E0,{3U,2U,0U}}, +{MULS_C1E0,{4U,2U,0U}}, +{MULS_C1E0,{5U,2U,0U}}, +{MULS_C1E0,{6U,2U,0U}}, +{MULS_C1E0,{7U,2U,0U}}, +{MULS_C1E8,{0U,2U,0U}}, +{MULS_C1E8,{1U,2U,0U}}, +{MULS_C1E8,{2U,2U,0U}}, +{MULS_C1E8,{3U,2U,0U}}, +{MULS_C1E8,{4U,2U,0U}}, +{MULS_C1E8,{5U,2U,0U}}, +{MULS_C1E8,{6U,2U,0U}}, +{MULS_C1E8,{7U,2U,0U}}, +{MULS_C1F0,{0U,2U,0U}}, +{MULS_C1F0,{1U,2U,0U}}, +{MULS_C1F0,{2U,2U,0U}}, +{MULS_C1F0,{3U,2U,0U}}, +{MULS_C1F0,{4U,2U,0U}}, +{MULS_C1F0,{5U,2U,0U}}, +{MULS_C1F0,{6U,2U,0U}}, +{MULS_C1F0,{7U,2U,0U}}, +{MULS_C1F8,{0U,2U,0U}}, +{MULS_C1F9,{0U,2U,0U}}, +{MULS_C1FA,{0U,2U,0U}}, +{MULS_C1FB,{0U,2U,0U}}, +{MULS_C1FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C000,{0U,3U,0U}}, +{AND_C000,{1U,3U,0U}}, +{AND_C000,{2U,3U,0U}}, +{AND_C000,{3U,3U,0U}}, +{AND_C000,{4U,3U,0U}}, +{AND_C000,{5U,3U,0U}}, +{AND_C000,{6U,3U,0U}}, +{AND_C000,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C010,{0U,3U,0U}}, +{AND_C010,{1U,3U,0U}}, +{AND_C010,{2U,3U,0U}}, +{AND_C010,{3U,3U,0U}}, +{AND_C010,{4U,3U,0U}}, +{AND_C010,{5U,3U,0U}}, +{AND_C010,{6U,3U,0U}}, +{AND_C010,{7U,3U,0U}}, +{AND_C018,{0U,3U,0U}}, +{AND_C018,{1U,3U,0U}}, +{AND_C018,{2U,3U,0U}}, +{AND_C018,{3U,3U,0U}}, +{AND_C018,{4U,3U,0U}}, +{AND_C018,{5U,3U,0U}}, +{AND_C018,{6U,3U,0U}}, +{AND_C018,{7U,3U,0U}}, +{AND_C020,{0U,3U,0U}}, +{AND_C020,{1U,3U,0U}}, +{AND_C020,{2U,3U,0U}}, +{AND_C020,{3U,3U,0U}}, +{AND_C020,{4U,3U,0U}}, +{AND_C020,{5U,3U,0U}}, +{AND_C020,{6U,3U,0U}}, +{AND_C020,{7U,3U,0U}}, +{AND_C028,{0U,3U,0U}}, +{AND_C028,{1U,3U,0U}}, +{AND_C028,{2U,3U,0U}}, +{AND_C028,{3U,3U,0U}}, +{AND_C028,{4U,3U,0U}}, +{AND_C028,{5U,3U,0U}}, +{AND_C028,{6U,3U,0U}}, +{AND_C028,{7U,3U,0U}}, +{AND_C030,{0U,3U,0U}}, +{AND_C030,{1U,3U,0U}}, +{AND_C030,{2U,3U,0U}}, +{AND_C030,{3U,3U,0U}}, +{AND_C030,{4U,3U,0U}}, +{AND_C030,{5U,3U,0U}}, +{AND_C030,{6U,3U,0U}}, +{AND_C030,{7U,3U,0U}}, +{AND_C038,{0U,3U,0U}}, +{AND_C039,{0U,3U,0U}}, +{AND_C03A,{0U,3U,0U}}, +{AND_C03B,{0U,3U,0U}}, +{AND_C03C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C040,{0U,3U,0U}}, +{AND_C040,{1U,3U,0U}}, +{AND_C040,{2U,3U,0U}}, +{AND_C040,{3U,3U,0U}}, +{AND_C040,{4U,3U,0U}}, +{AND_C040,{5U,3U,0U}}, +{AND_C040,{6U,3U,0U}}, +{AND_C040,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C050,{0U,3U,0U}}, +{AND_C050,{1U,3U,0U}}, +{AND_C050,{2U,3U,0U}}, +{AND_C050,{3U,3U,0U}}, +{AND_C050,{4U,3U,0U}}, +{AND_C050,{5U,3U,0U}}, +{AND_C050,{6U,3U,0U}}, +{AND_C050,{7U,3U,0U}}, +{AND_C058,{0U,3U,0U}}, +{AND_C058,{1U,3U,0U}}, +{AND_C058,{2U,3U,0U}}, +{AND_C058,{3U,3U,0U}}, +{AND_C058,{4U,3U,0U}}, +{AND_C058,{5U,3U,0U}}, +{AND_C058,{6U,3U,0U}}, +{AND_C058,{7U,3U,0U}}, +{AND_C060,{0U,3U,0U}}, +{AND_C060,{1U,3U,0U}}, +{AND_C060,{2U,3U,0U}}, +{AND_C060,{3U,3U,0U}}, +{AND_C060,{4U,3U,0U}}, +{AND_C060,{5U,3U,0U}}, +{AND_C060,{6U,3U,0U}}, +{AND_C060,{7U,3U,0U}}, +{AND_C068,{0U,3U,0U}}, +{AND_C068,{1U,3U,0U}}, +{AND_C068,{2U,3U,0U}}, +{AND_C068,{3U,3U,0U}}, +{AND_C068,{4U,3U,0U}}, +{AND_C068,{5U,3U,0U}}, +{AND_C068,{6U,3U,0U}}, +{AND_C068,{7U,3U,0U}}, +{AND_C070,{0U,3U,0U}}, +{AND_C070,{1U,3U,0U}}, +{AND_C070,{2U,3U,0U}}, +{AND_C070,{3U,3U,0U}}, +{AND_C070,{4U,3U,0U}}, +{AND_C070,{5U,3U,0U}}, +{AND_C070,{6U,3U,0U}}, +{AND_C070,{7U,3U,0U}}, +{AND_C078,{0U,3U,0U}}, +{AND_C079,{0U,3U,0U}}, +{AND_C07A,{0U,3U,0U}}, +{AND_C07B,{0U,3U,0U}}, +{AND_C07C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C080,{0U,3U,0U}}, +{AND_C080,{1U,3U,0U}}, +{AND_C080,{2U,3U,0U}}, +{AND_C080,{3U,3U,0U}}, +{AND_C080,{4U,3U,0U}}, +{AND_C080,{5U,3U,0U}}, +{AND_C080,{6U,3U,0U}}, +{AND_C080,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C090,{0U,3U,0U}}, +{AND_C090,{1U,3U,0U}}, +{AND_C090,{2U,3U,0U}}, +{AND_C090,{3U,3U,0U}}, +{AND_C090,{4U,3U,0U}}, +{AND_C090,{5U,3U,0U}}, +{AND_C090,{6U,3U,0U}}, +{AND_C090,{7U,3U,0U}}, +{AND_C098,{0U,3U,0U}}, +{AND_C098,{1U,3U,0U}}, +{AND_C098,{2U,3U,0U}}, +{AND_C098,{3U,3U,0U}}, +{AND_C098,{4U,3U,0U}}, +{AND_C098,{5U,3U,0U}}, +{AND_C098,{6U,3U,0U}}, +{AND_C098,{7U,3U,0U}}, +{AND_C0A0,{0U,3U,0U}}, +{AND_C0A0,{1U,3U,0U}}, +{AND_C0A0,{2U,3U,0U}}, +{AND_C0A0,{3U,3U,0U}}, +{AND_C0A0,{4U,3U,0U}}, +{AND_C0A0,{5U,3U,0U}}, +{AND_C0A0,{6U,3U,0U}}, +{AND_C0A0,{7U,3U,0U}}, +{AND_C0A8,{0U,3U,0U}}, +{AND_C0A8,{1U,3U,0U}}, +{AND_C0A8,{2U,3U,0U}}, +{AND_C0A8,{3U,3U,0U}}, +{AND_C0A8,{4U,3U,0U}}, +{AND_C0A8,{5U,3U,0U}}, +{AND_C0A8,{6U,3U,0U}}, +{AND_C0A8,{7U,3U,0U}}, +{AND_C0B0,{0U,3U,0U}}, +{AND_C0B0,{1U,3U,0U}}, +{AND_C0B0,{2U,3U,0U}}, +{AND_C0B0,{3U,3U,0U}}, +{AND_C0B0,{4U,3U,0U}}, +{AND_C0B0,{5U,3U,0U}}, +{AND_C0B0,{6U,3U,0U}}, +{AND_C0B0,{7U,3U,0U}}, +{AND_C0B8,{0U,3U,0U}}, +{AND_C0B9,{0U,3U,0U}}, +{AND_C0BA,{0U,3U,0U}}, +{AND_C0BB,{0U,3U,0U}}, +{AND_C0BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0C0,{0U,3U,0U}}, +{MULU_C0C0,{1U,3U,0U}}, +{MULU_C0C0,{2U,3U,0U}}, +{MULU_C0C0,{3U,3U,0U}}, +{MULU_C0C0,{4U,3U,0U}}, +{MULU_C0C0,{5U,3U,0U}}, +{MULU_C0C0,{6U,3U,0U}}, +{MULU_C0C0,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0D0,{0U,3U,0U}}, +{MULU_C0D0,{1U,3U,0U}}, +{MULU_C0D0,{2U,3U,0U}}, +{MULU_C0D0,{3U,3U,0U}}, +{MULU_C0D0,{4U,3U,0U}}, +{MULU_C0D0,{5U,3U,0U}}, +{MULU_C0D0,{6U,3U,0U}}, +{MULU_C0D0,{7U,3U,0U}}, +{MULU_C0D8,{0U,3U,0U}}, +{MULU_C0D8,{1U,3U,0U}}, +{MULU_C0D8,{2U,3U,0U}}, +{MULU_C0D8,{3U,3U,0U}}, +{MULU_C0D8,{4U,3U,0U}}, +{MULU_C0D8,{5U,3U,0U}}, +{MULU_C0D8,{6U,3U,0U}}, +{MULU_C0D8,{7U,3U,0U}}, +{MULU_C0E0,{0U,3U,0U}}, +{MULU_C0E0,{1U,3U,0U}}, +{MULU_C0E0,{2U,3U,0U}}, +{MULU_C0E0,{3U,3U,0U}}, +{MULU_C0E0,{4U,3U,0U}}, +{MULU_C0E0,{5U,3U,0U}}, +{MULU_C0E0,{6U,3U,0U}}, +{MULU_C0E0,{7U,3U,0U}}, +{MULU_C0E8,{0U,3U,0U}}, +{MULU_C0E8,{1U,3U,0U}}, +{MULU_C0E8,{2U,3U,0U}}, +{MULU_C0E8,{3U,3U,0U}}, +{MULU_C0E8,{4U,3U,0U}}, +{MULU_C0E8,{5U,3U,0U}}, +{MULU_C0E8,{6U,3U,0U}}, +{MULU_C0E8,{7U,3U,0U}}, +{MULU_C0F0,{0U,3U,0U}}, +{MULU_C0F0,{1U,3U,0U}}, +{MULU_C0F0,{2U,3U,0U}}, +{MULU_C0F0,{3U,3U,0U}}, +{MULU_C0F0,{4U,3U,0U}}, +{MULU_C0F0,{5U,3U,0U}}, +{MULU_C0F0,{6U,3U,0U}}, +{MULU_C0F0,{7U,3U,0U}}, +{MULU_C0F8,{0U,3U,0U}}, +{MULU_C0F9,{0U,3U,0U}}, +{MULU_C0FA,{0U,3U,0U}}, +{MULU_C0FB,{0U,3U,0U}}, +{MULU_C0FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ABCD_C100,{0U,3U,0U}}, +{ABCD_C100,{1U,3U,0U}}, +{ABCD_C100,{2U,3U,0U}}, +{ABCD_C100,{3U,3U,0U}}, +{ABCD_C100,{4U,3U,0U}}, +{ABCD_C100,{5U,3U,0U}}, +{ABCD_C100,{6U,3U,0U}}, +{ABCD_C100,{7U,3U,0U}}, +{ABCD_C108,{0U,3U,0U}}, +{ABCD_C108,{1U,3U,0U}}, +{ABCD_C108,{2U,3U,0U}}, +{ABCD_C108,{3U,3U,0U}}, +{ABCD_C108,{4U,3U,0U}}, +{ABCD_C108,{5U,3U,0U}}, +{ABCD_C108,{6U,3U,0U}}, +{ABCD_C108,{7U,3U,0U}}, +{AND_C110,{0U,3U,0U}}, +{AND_C110,{1U,3U,0U}}, +{AND_C110,{2U,3U,0U}}, +{AND_C110,{3U,3U,0U}}, +{AND_C110,{4U,3U,0U}}, +{AND_C110,{5U,3U,0U}}, +{AND_C110,{6U,3U,0U}}, +{AND_C110,{7U,3U,0U}}, +{AND_C118,{0U,3U,0U}}, +{AND_C118,{1U,3U,0U}}, +{AND_C118,{2U,3U,0U}}, +{AND_C118,{3U,3U,0U}}, +{AND_C118,{4U,3U,0U}}, +{AND_C118,{5U,3U,0U}}, +{AND_C118,{6U,3U,0U}}, +{AND_C118,{7U,3U,0U}}, +{AND_C120,{0U,3U,0U}}, +{AND_C120,{1U,3U,0U}}, +{AND_C120,{2U,3U,0U}}, +{AND_C120,{3U,3U,0U}}, +{AND_C120,{4U,3U,0U}}, +{AND_C120,{5U,3U,0U}}, +{AND_C120,{6U,3U,0U}}, +{AND_C120,{7U,3U,0U}}, +{AND_C128,{0U,3U,0U}}, +{AND_C128,{1U,3U,0U}}, +{AND_C128,{2U,3U,0U}}, +{AND_C128,{3U,3U,0U}}, +{AND_C128,{4U,3U,0U}}, +{AND_C128,{5U,3U,0U}}, +{AND_C128,{6U,3U,0U}}, +{AND_C128,{7U,3U,0U}}, +{AND_C130,{0U,3U,0U}}, +{AND_C130,{1U,3U,0U}}, +{AND_C130,{2U,3U,0U}}, +{AND_C130,{3U,3U,0U}}, +{AND_C130,{4U,3U,0U}}, +{AND_C130,{5U,3U,0U}}, +{AND_C130,{6U,3U,0U}}, +{AND_C130,{7U,3U,0U}}, +{AND_C138,{0U,3U,0U}}, +{AND_C139,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C140,{3U,0U,0U}}, +{EXG_C140,{3U,1U,0U}}, +{EXG_C140,{3U,2U,0U}}, +{EXG_C140,{3U,3U,0U}}, +{EXG_C140,{3U,4U,0U}}, +{EXG_C140,{3U,5U,0U}}, +{EXG_C140,{3U,6U,0U}}, +{EXG_C140,{3U,7U,0U}}, +{EXG_C148,{3U,0U,0U}}, +{EXG_C148,{3U,1U,0U}}, +{EXG_C148,{3U,2U,0U}}, +{EXG_C148,{3U,3U,0U}}, +{EXG_C148,{3U,4U,0U}}, +{EXG_C148,{3U,5U,0U}}, +{EXG_C148,{3U,6U,0U}}, +{EXG_C148,{3U,7U,0U}}, +{AND_C150,{0U,3U,0U}}, +{AND_C150,{1U,3U,0U}}, +{AND_C150,{2U,3U,0U}}, +{AND_C150,{3U,3U,0U}}, +{AND_C150,{4U,3U,0U}}, +{AND_C150,{5U,3U,0U}}, +{AND_C150,{6U,3U,0U}}, +{AND_C150,{7U,3U,0U}}, +{AND_C158,{0U,3U,0U}}, +{AND_C158,{1U,3U,0U}}, +{AND_C158,{2U,3U,0U}}, +{AND_C158,{3U,3U,0U}}, +{AND_C158,{4U,3U,0U}}, +{AND_C158,{5U,3U,0U}}, +{AND_C158,{6U,3U,0U}}, +{AND_C158,{7U,3U,0U}}, +{AND_C160,{0U,3U,0U}}, +{AND_C160,{1U,3U,0U}}, +{AND_C160,{2U,3U,0U}}, +{AND_C160,{3U,3U,0U}}, +{AND_C160,{4U,3U,0U}}, +{AND_C160,{5U,3U,0U}}, +{AND_C160,{6U,3U,0U}}, +{AND_C160,{7U,3U,0U}}, +{AND_C168,{0U,3U,0U}}, +{AND_C168,{1U,3U,0U}}, +{AND_C168,{2U,3U,0U}}, +{AND_C168,{3U,3U,0U}}, +{AND_C168,{4U,3U,0U}}, +{AND_C168,{5U,3U,0U}}, +{AND_C168,{6U,3U,0U}}, +{AND_C168,{7U,3U,0U}}, +{AND_C170,{0U,3U,0U}}, +{AND_C170,{1U,3U,0U}}, +{AND_C170,{2U,3U,0U}}, +{AND_C170,{3U,3U,0U}}, +{AND_C170,{4U,3U,0U}}, +{AND_C170,{5U,3U,0U}}, +{AND_C170,{6U,3U,0U}}, +{AND_C170,{7U,3U,0U}}, +{AND_C178,{0U,3U,0U}}, +{AND_C179,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C188,{3U,0U,0U}}, +{EXG_C188,{3U,1U,0U}}, +{EXG_C188,{3U,2U,0U}}, +{EXG_C188,{3U,3U,0U}}, +{EXG_C188,{3U,4U,0U}}, +{EXG_C188,{3U,5U,0U}}, +{EXG_C188,{3U,6U,0U}}, +{EXG_C188,{3U,7U,0U}}, +{AND_C190,{0U,3U,0U}}, +{AND_C190,{1U,3U,0U}}, +{AND_C190,{2U,3U,0U}}, +{AND_C190,{3U,3U,0U}}, +{AND_C190,{4U,3U,0U}}, +{AND_C190,{5U,3U,0U}}, +{AND_C190,{6U,3U,0U}}, +{AND_C190,{7U,3U,0U}}, +{AND_C198,{0U,3U,0U}}, +{AND_C198,{1U,3U,0U}}, +{AND_C198,{2U,3U,0U}}, +{AND_C198,{3U,3U,0U}}, +{AND_C198,{4U,3U,0U}}, +{AND_C198,{5U,3U,0U}}, +{AND_C198,{6U,3U,0U}}, +{AND_C198,{7U,3U,0U}}, +{AND_C1A0,{0U,3U,0U}}, +{AND_C1A0,{1U,3U,0U}}, +{AND_C1A0,{2U,3U,0U}}, +{AND_C1A0,{3U,3U,0U}}, +{AND_C1A0,{4U,3U,0U}}, +{AND_C1A0,{5U,3U,0U}}, +{AND_C1A0,{6U,3U,0U}}, +{AND_C1A0,{7U,3U,0U}}, +{AND_C1A8,{0U,3U,0U}}, +{AND_C1A8,{1U,3U,0U}}, +{AND_C1A8,{2U,3U,0U}}, +{AND_C1A8,{3U,3U,0U}}, +{AND_C1A8,{4U,3U,0U}}, +{AND_C1A8,{5U,3U,0U}}, +{AND_C1A8,{6U,3U,0U}}, +{AND_C1A8,{7U,3U,0U}}, +{AND_C1B0,{0U,3U,0U}}, +{AND_C1B0,{1U,3U,0U}}, +{AND_C1B0,{2U,3U,0U}}, +{AND_C1B0,{3U,3U,0U}}, +{AND_C1B0,{4U,3U,0U}}, +{AND_C1B0,{5U,3U,0U}}, +{AND_C1B0,{6U,3U,0U}}, +{AND_C1B0,{7U,3U,0U}}, +{AND_C1B8,{0U,3U,0U}}, +{AND_C1B9,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1C0,{0U,3U,0U}}, +{MULS_C1C0,{1U,3U,0U}}, +{MULS_C1C0,{2U,3U,0U}}, +{MULS_C1C0,{3U,3U,0U}}, +{MULS_C1C0,{4U,3U,0U}}, +{MULS_C1C0,{5U,3U,0U}}, +{MULS_C1C0,{6U,3U,0U}}, +{MULS_C1C0,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1D0,{0U,3U,0U}}, +{MULS_C1D0,{1U,3U,0U}}, +{MULS_C1D0,{2U,3U,0U}}, +{MULS_C1D0,{3U,3U,0U}}, +{MULS_C1D0,{4U,3U,0U}}, +{MULS_C1D0,{5U,3U,0U}}, +{MULS_C1D0,{6U,3U,0U}}, +{MULS_C1D0,{7U,3U,0U}}, +{MULS_C1D8,{0U,3U,0U}}, +{MULS_C1D8,{1U,3U,0U}}, +{MULS_C1D8,{2U,3U,0U}}, +{MULS_C1D8,{3U,3U,0U}}, +{MULS_C1D8,{4U,3U,0U}}, +{MULS_C1D8,{5U,3U,0U}}, +{MULS_C1D8,{6U,3U,0U}}, +{MULS_C1D8,{7U,3U,0U}}, +{MULS_C1E0,{0U,3U,0U}}, +{MULS_C1E0,{1U,3U,0U}}, +{MULS_C1E0,{2U,3U,0U}}, +{MULS_C1E0,{3U,3U,0U}}, +{MULS_C1E0,{4U,3U,0U}}, +{MULS_C1E0,{5U,3U,0U}}, +{MULS_C1E0,{6U,3U,0U}}, +{MULS_C1E0,{7U,3U,0U}}, +{MULS_C1E8,{0U,3U,0U}}, +{MULS_C1E8,{1U,3U,0U}}, +{MULS_C1E8,{2U,3U,0U}}, +{MULS_C1E8,{3U,3U,0U}}, +{MULS_C1E8,{4U,3U,0U}}, +{MULS_C1E8,{5U,3U,0U}}, +{MULS_C1E8,{6U,3U,0U}}, +{MULS_C1E8,{7U,3U,0U}}, +{MULS_C1F0,{0U,3U,0U}}, +{MULS_C1F0,{1U,3U,0U}}, +{MULS_C1F0,{2U,3U,0U}}, +{MULS_C1F0,{3U,3U,0U}}, +{MULS_C1F0,{4U,3U,0U}}, +{MULS_C1F0,{5U,3U,0U}}, +{MULS_C1F0,{6U,3U,0U}}, +{MULS_C1F0,{7U,3U,0U}}, +{MULS_C1F8,{0U,3U,0U}}, +{MULS_C1F9,{0U,3U,0U}}, +{MULS_C1FA,{0U,3U,0U}}, +{MULS_C1FB,{0U,3U,0U}}, +{MULS_C1FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C000,{0U,4U,0U}}, +{AND_C000,{1U,4U,0U}}, +{AND_C000,{2U,4U,0U}}, +{AND_C000,{3U,4U,0U}}, +{AND_C000,{4U,4U,0U}}, +{AND_C000,{5U,4U,0U}}, +{AND_C000,{6U,4U,0U}}, +{AND_C000,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C010,{0U,4U,0U}}, +{AND_C010,{1U,4U,0U}}, +{AND_C010,{2U,4U,0U}}, +{AND_C010,{3U,4U,0U}}, +{AND_C010,{4U,4U,0U}}, +{AND_C010,{5U,4U,0U}}, +{AND_C010,{6U,4U,0U}}, +{AND_C010,{7U,4U,0U}}, +{AND_C018,{0U,4U,0U}}, +{AND_C018,{1U,4U,0U}}, +{AND_C018,{2U,4U,0U}}, +{AND_C018,{3U,4U,0U}}, +{AND_C018,{4U,4U,0U}}, +{AND_C018,{5U,4U,0U}}, +{AND_C018,{6U,4U,0U}}, +{AND_C018,{7U,4U,0U}}, +{AND_C020,{0U,4U,0U}}, +{AND_C020,{1U,4U,0U}}, +{AND_C020,{2U,4U,0U}}, +{AND_C020,{3U,4U,0U}}, +{AND_C020,{4U,4U,0U}}, +{AND_C020,{5U,4U,0U}}, +{AND_C020,{6U,4U,0U}}, +{AND_C020,{7U,4U,0U}}, +{AND_C028,{0U,4U,0U}}, +{AND_C028,{1U,4U,0U}}, +{AND_C028,{2U,4U,0U}}, +{AND_C028,{3U,4U,0U}}, +{AND_C028,{4U,4U,0U}}, +{AND_C028,{5U,4U,0U}}, +{AND_C028,{6U,4U,0U}}, +{AND_C028,{7U,4U,0U}}, +{AND_C030,{0U,4U,0U}}, +{AND_C030,{1U,4U,0U}}, +{AND_C030,{2U,4U,0U}}, +{AND_C030,{3U,4U,0U}}, +{AND_C030,{4U,4U,0U}}, +{AND_C030,{5U,4U,0U}}, +{AND_C030,{6U,4U,0U}}, +{AND_C030,{7U,4U,0U}}, +{AND_C038,{0U,4U,0U}}, +{AND_C039,{0U,4U,0U}}, +{AND_C03A,{0U,4U,0U}}, +{AND_C03B,{0U,4U,0U}}, +{AND_C03C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C040,{0U,4U,0U}}, +{AND_C040,{1U,4U,0U}}, +{AND_C040,{2U,4U,0U}}, +{AND_C040,{3U,4U,0U}}, +{AND_C040,{4U,4U,0U}}, +{AND_C040,{5U,4U,0U}}, +{AND_C040,{6U,4U,0U}}, +{AND_C040,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C050,{0U,4U,0U}}, +{AND_C050,{1U,4U,0U}}, +{AND_C050,{2U,4U,0U}}, +{AND_C050,{3U,4U,0U}}, +{AND_C050,{4U,4U,0U}}, +{AND_C050,{5U,4U,0U}}, +{AND_C050,{6U,4U,0U}}, +{AND_C050,{7U,4U,0U}}, +{AND_C058,{0U,4U,0U}}, +{AND_C058,{1U,4U,0U}}, +{AND_C058,{2U,4U,0U}}, +{AND_C058,{3U,4U,0U}}, +{AND_C058,{4U,4U,0U}}, +{AND_C058,{5U,4U,0U}}, +{AND_C058,{6U,4U,0U}}, +{AND_C058,{7U,4U,0U}}, +{AND_C060,{0U,4U,0U}}, +{AND_C060,{1U,4U,0U}}, +{AND_C060,{2U,4U,0U}}, +{AND_C060,{3U,4U,0U}}, +{AND_C060,{4U,4U,0U}}, +{AND_C060,{5U,4U,0U}}, +{AND_C060,{6U,4U,0U}}, +{AND_C060,{7U,4U,0U}}, +{AND_C068,{0U,4U,0U}}, +{AND_C068,{1U,4U,0U}}, +{AND_C068,{2U,4U,0U}}, +{AND_C068,{3U,4U,0U}}, +{AND_C068,{4U,4U,0U}}, +{AND_C068,{5U,4U,0U}}, +{AND_C068,{6U,4U,0U}}, +{AND_C068,{7U,4U,0U}}, +{AND_C070,{0U,4U,0U}}, +{AND_C070,{1U,4U,0U}}, +{AND_C070,{2U,4U,0U}}, +{AND_C070,{3U,4U,0U}}, +{AND_C070,{4U,4U,0U}}, +{AND_C070,{5U,4U,0U}}, +{AND_C070,{6U,4U,0U}}, +{AND_C070,{7U,4U,0U}}, +{AND_C078,{0U,4U,0U}}, +{AND_C079,{0U,4U,0U}}, +{AND_C07A,{0U,4U,0U}}, +{AND_C07B,{0U,4U,0U}}, +{AND_C07C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C080,{0U,4U,0U}}, +{AND_C080,{1U,4U,0U}}, +{AND_C080,{2U,4U,0U}}, +{AND_C080,{3U,4U,0U}}, +{AND_C080,{4U,4U,0U}}, +{AND_C080,{5U,4U,0U}}, +{AND_C080,{6U,4U,0U}}, +{AND_C080,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C090,{0U,4U,0U}}, +{AND_C090,{1U,4U,0U}}, +{AND_C090,{2U,4U,0U}}, +{AND_C090,{3U,4U,0U}}, +{AND_C090,{4U,4U,0U}}, +{AND_C090,{5U,4U,0U}}, +{AND_C090,{6U,4U,0U}}, +{AND_C090,{7U,4U,0U}}, +{AND_C098,{0U,4U,0U}}, +{AND_C098,{1U,4U,0U}}, +{AND_C098,{2U,4U,0U}}, +{AND_C098,{3U,4U,0U}}, +{AND_C098,{4U,4U,0U}}, +{AND_C098,{5U,4U,0U}}, +{AND_C098,{6U,4U,0U}}, +{AND_C098,{7U,4U,0U}}, +{AND_C0A0,{0U,4U,0U}}, +{AND_C0A0,{1U,4U,0U}}, +{AND_C0A0,{2U,4U,0U}}, +{AND_C0A0,{3U,4U,0U}}, +{AND_C0A0,{4U,4U,0U}}, +{AND_C0A0,{5U,4U,0U}}, +{AND_C0A0,{6U,4U,0U}}, +{AND_C0A0,{7U,4U,0U}}, +{AND_C0A8,{0U,4U,0U}}, +{AND_C0A8,{1U,4U,0U}}, +{AND_C0A8,{2U,4U,0U}}, +{AND_C0A8,{3U,4U,0U}}, +{AND_C0A8,{4U,4U,0U}}, +{AND_C0A8,{5U,4U,0U}}, +{AND_C0A8,{6U,4U,0U}}, +{AND_C0A8,{7U,4U,0U}}, +{AND_C0B0,{0U,4U,0U}}, +{AND_C0B0,{1U,4U,0U}}, +{AND_C0B0,{2U,4U,0U}}, +{AND_C0B0,{3U,4U,0U}}, +{AND_C0B0,{4U,4U,0U}}, +{AND_C0B0,{5U,4U,0U}}, +{AND_C0B0,{6U,4U,0U}}, +{AND_C0B0,{7U,4U,0U}}, +{AND_C0B8,{0U,4U,0U}}, +{AND_C0B9,{0U,4U,0U}}, +{AND_C0BA,{0U,4U,0U}}, +{AND_C0BB,{0U,4U,0U}}, +{AND_C0BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0C0,{0U,4U,0U}}, +{MULU_C0C0,{1U,4U,0U}}, +{MULU_C0C0,{2U,4U,0U}}, +{MULU_C0C0,{3U,4U,0U}}, +{MULU_C0C0,{4U,4U,0U}}, +{MULU_C0C0,{5U,4U,0U}}, +{MULU_C0C0,{6U,4U,0U}}, +{MULU_C0C0,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0D0,{0U,4U,0U}}, +{MULU_C0D0,{1U,4U,0U}}, +{MULU_C0D0,{2U,4U,0U}}, +{MULU_C0D0,{3U,4U,0U}}, +{MULU_C0D0,{4U,4U,0U}}, +{MULU_C0D0,{5U,4U,0U}}, +{MULU_C0D0,{6U,4U,0U}}, +{MULU_C0D0,{7U,4U,0U}}, +{MULU_C0D8,{0U,4U,0U}}, +{MULU_C0D8,{1U,4U,0U}}, +{MULU_C0D8,{2U,4U,0U}}, +{MULU_C0D8,{3U,4U,0U}}, +{MULU_C0D8,{4U,4U,0U}}, +{MULU_C0D8,{5U,4U,0U}}, +{MULU_C0D8,{6U,4U,0U}}, +{MULU_C0D8,{7U,4U,0U}}, +{MULU_C0E0,{0U,4U,0U}}, +{MULU_C0E0,{1U,4U,0U}}, +{MULU_C0E0,{2U,4U,0U}}, +{MULU_C0E0,{3U,4U,0U}}, +{MULU_C0E0,{4U,4U,0U}}, +{MULU_C0E0,{5U,4U,0U}}, +{MULU_C0E0,{6U,4U,0U}}, +{MULU_C0E0,{7U,4U,0U}}, +{MULU_C0E8,{0U,4U,0U}}, +{MULU_C0E8,{1U,4U,0U}}, +{MULU_C0E8,{2U,4U,0U}}, +{MULU_C0E8,{3U,4U,0U}}, +{MULU_C0E8,{4U,4U,0U}}, +{MULU_C0E8,{5U,4U,0U}}, +{MULU_C0E8,{6U,4U,0U}}, +{MULU_C0E8,{7U,4U,0U}}, +{MULU_C0F0,{0U,4U,0U}}, +{MULU_C0F0,{1U,4U,0U}}, +{MULU_C0F0,{2U,4U,0U}}, +{MULU_C0F0,{3U,4U,0U}}, +{MULU_C0F0,{4U,4U,0U}}, +{MULU_C0F0,{5U,4U,0U}}, +{MULU_C0F0,{6U,4U,0U}}, +{MULU_C0F0,{7U,4U,0U}}, +{MULU_C0F8,{0U,4U,0U}}, +{MULU_C0F9,{0U,4U,0U}}, +{MULU_C0FA,{0U,4U,0U}}, +{MULU_C0FB,{0U,4U,0U}}, +{MULU_C0FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ABCD_C100,{0U,4U,0U}}, +{ABCD_C100,{1U,4U,0U}}, +{ABCD_C100,{2U,4U,0U}}, +{ABCD_C100,{3U,4U,0U}}, +{ABCD_C100,{4U,4U,0U}}, +{ABCD_C100,{5U,4U,0U}}, +{ABCD_C100,{6U,4U,0U}}, +{ABCD_C100,{7U,4U,0U}}, +{ABCD_C108,{0U,4U,0U}}, +{ABCD_C108,{1U,4U,0U}}, +{ABCD_C108,{2U,4U,0U}}, +{ABCD_C108,{3U,4U,0U}}, +{ABCD_C108,{4U,4U,0U}}, +{ABCD_C108,{5U,4U,0U}}, +{ABCD_C108,{6U,4U,0U}}, +{ABCD_C108,{7U,4U,0U}}, +{AND_C110,{0U,4U,0U}}, +{AND_C110,{1U,4U,0U}}, +{AND_C110,{2U,4U,0U}}, +{AND_C110,{3U,4U,0U}}, +{AND_C110,{4U,4U,0U}}, +{AND_C110,{5U,4U,0U}}, +{AND_C110,{6U,4U,0U}}, +{AND_C110,{7U,4U,0U}}, +{AND_C118,{0U,4U,0U}}, +{AND_C118,{1U,4U,0U}}, +{AND_C118,{2U,4U,0U}}, +{AND_C118,{3U,4U,0U}}, +{AND_C118,{4U,4U,0U}}, +{AND_C118,{5U,4U,0U}}, +{AND_C118,{6U,4U,0U}}, +{AND_C118,{7U,4U,0U}}, +{AND_C120,{0U,4U,0U}}, +{AND_C120,{1U,4U,0U}}, +{AND_C120,{2U,4U,0U}}, +{AND_C120,{3U,4U,0U}}, +{AND_C120,{4U,4U,0U}}, +{AND_C120,{5U,4U,0U}}, +{AND_C120,{6U,4U,0U}}, +{AND_C120,{7U,4U,0U}}, +{AND_C128,{0U,4U,0U}}, +{AND_C128,{1U,4U,0U}}, +{AND_C128,{2U,4U,0U}}, +{AND_C128,{3U,4U,0U}}, +{AND_C128,{4U,4U,0U}}, +{AND_C128,{5U,4U,0U}}, +{AND_C128,{6U,4U,0U}}, +{AND_C128,{7U,4U,0U}}, +{AND_C130,{0U,4U,0U}}, +{AND_C130,{1U,4U,0U}}, +{AND_C130,{2U,4U,0U}}, +{AND_C130,{3U,4U,0U}}, +{AND_C130,{4U,4U,0U}}, +{AND_C130,{5U,4U,0U}}, +{AND_C130,{6U,4U,0U}}, +{AND_C130,{7U,4U,0U}}, +{AND_C138,{0U,4U,0U}}, +{AND_C139,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C140,{4U,0U,0U}}, +{EXG_C140,{4U,1U,0U}}, +{EXG_C140,{4U,2U,0U}}, +{EXG_C140,{4U,3U,0U}}, +{EXG_C140,{4U,4U,0U}}, +{EXG_C140,{4U,5U,0U}}, +{EXG_C140,{4U,6U,0U}}, +{EXG_C140,{4U,7U,0U}}, +{EXG_C148,{4U,0U,0U}}, +{EXG_C148,{4U,1U,0U}}, +{EXG_C148,{4U,2U,0U}}, +{EXG_C148,{4U,3U,0U}}, +{EXG_C148,{4U,4U,0U}}, +{EXG_C148,{4U,5U,0U}}, +{EXG_C148,{4U,6U,0U}}, +{EXG_C148,{4U,7U,0U}}, +{AND_C150,{0U,4U,0U}}, +{AND_C150,{1U,4U,0U}}, +{AND_C150,{2U,4U,0U}}, +{AND_C150,{3U,4U,0U}}, +{AND_C150,{4U,4U,0U}}, +{AND_C150,{5U,4U,0U}}, +{AND_C150,{6U,4U,0U}}, +{AND_C150,{7U,4U,0U}}, +{AND_C158,{0U,4U,0U}}, +{AND_C158,{1U,4U,0U}}, +{AND_C158,{2U,4U,0U}}, +{AND_C158,{3U,4U,0U}}, +{AND_C158,{4U,4U,0U}}, +{AND_C158,{5U,4U,0U}}, +{AND_C158,{6U,4U,0U}}, +{AND_C158,{7U,4U,0U}}, +{AND_C160,{0U,4U,0U}}, +{AND_C160,{1U,4U,0U}}, +{AND_C160,{2U,4U,0U}}, +{AND_C160,{3U,4U,0U}}, +{AND_C160,{4U,4U,0U}}, +{AND_C160,{5U,4U,0U}}, +{AND_C160,{6U,4U,0U}}, +{AND_C160,{7U,4U,0U}}, +{AND_C168,{0U,4U,0U}}, +{AND_C168,{1U,4U,0U}}, +{AND_C168,{2U,4U,0U}}, +{AND_C168,{3U,4U,0U}}, +{AND_C168,{4U,4U,0U}}, +{AND_C168,{5U,4U,0U}}, +{AND_C168,{6U,4U,0U}}, +{AND_C168,{7U,4U,0U}}, +{AND_C170,{0U,4U,0U}}, +{AND_C170,{1U,4U,0U}}, +{AND_C170,{2U,4U,0U}}, +{AND_C170,{3U,4U,0U}}, +{AND_C170,{4U,4U,0U}}, +{AND_C170,{5U,4U,0U}}, +{AND_C170,{6U,4U,0U}}, +{AND_C170,{7U,4U,0U}}, +{AND_C178,{0U,4U,0U}}, +{AND_C179,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C188,{4U,0U,0U}}, +{EXG_C188,{4U,1U,0U}}, +{EXG_C188,{4U,2U,0U}}, +{EXG_C188,{4U,3U,0U}}, +{EXG_C188,{4U,4U,0U}}, +{EXG_C188,{4U,5U,0U}}, +{EXG_C188,{4U,6U,0U}}, +{EXG_C188,{4U,7U,0U}}, +{AND_C190,{0U,4U,0U}}, +{AND_C190,{1U,4U,0U}}, +{AND_C190,{2U,4U,0U}}, +{AND_C190,{3U,4U,0U}}, +{AND_C190,{4U,4U,0U}}, +{AND_C190,{5U,4U,0U}}, +{AND_C190,{6U,4U,0U}}, +{AND_C190,{7U,4U,0U}}, +{AND_C198,{0U,4U,0U}}, +{AND_C198,{1U,4U,0U}}, +{AND_C198,{2U,4U,0U}}, +{AND_C198,{3U,4U,0U}}, +{AND_C198,{4U,4U,0U}}, +{AND_C198,{5U,4U,0U}}, +{AND_C198,{6U,4U,0U}}, +{AND_C198,{7U,4U,0U}}, +{AND_C1A0,{0U,4U,0U}}, +{AND_C1A0,{1U,4U,0U}}, +{AND_C1A0,{2U,4U,0U}}, +{AND_C1A0,{3U,4U,0U}}, +{AND_C1A0,{4U,4U,0U}}, +{AND_C1A0,{5U,4U,0U}}, +{AND_C1A0,{6U,4U,0U}}, +{AND_C1A0,{7U,4U,0U}}, +{AND_C1A8,{0U,4U,0U}}, +{AND_C1A8,{1U,4U,0U}}, +{AND_C1A8,{2U,4U,0U}}, +{AND_C1A8,{3U,4U,0U}}, +{AND_C1A8,{4U,4U,0U}}, +{AND_C1A8,{5U,4U,0U}}, +{AND_C1A8,{6U,4U,0U}}, +{AND_C1A8,{7U,4U,0U}}, +{AND_C1B0,{0U,4U,0U}}, +{AND_C1B0,{1U,4U,0U}}, +{AND_C1B0,{2U,4U,0U}}, +{AND_C1B0,{3U,4U,0U}}, +{AND_C1B0,{4U,4U,0U}}, +{AND_C1B0,{5U,4U,0U}}, +{AND_C1B0,{6U,4U,0U}}, +{AND_C1B0,{7U,4U,0U}}, +{AND_C1B8,{0U,4U,0U}}, +{AND_C1B9,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1C0,{0U,4U,0U}}, +{MULS_C1C0,{1U,4U,0U}}, +{MULS_C1C0,{2U,4U,0U}}, +{MULS_C1C0,{3U,4U,0U}}, +{MULS_C1C0,{4U,4U,0U}}, +{MULS_C1C0,{5U,4U,0U}}, +{MULS_C1C0,{6U,4U,0U}}, +{MULS_C1C0,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1D0,{0U,4U,0U}}, +{MULS_C1D0,{1U,4U,0U}}, +{MULS_C1D0,{2U,4U,0U}}, +{MULS_C1D0,{3U,4U,0U}}, +{MULS_C1D0,{4U,4U,0U}}, +{MULS_C1D0,{5U,4U,0U}}, +{MULS_C1D0,{6U,4U,0U}}, +{MULS_C1D0,{7U,4U,0U}}, +{MULS_C1D8,{0U,4U,0U}}, +{MULS_C1D8,{1U,4U,0U}}, +{MULS_C1D8,{2U,4U,0U}}, +{MULS_C1D8,{3U,4U,0U}}, +{MULS_C1D8,{4U,4U,0U}}, +{MULS_C1D8,{5U,4U,0U}}, +{MULS_C1D8,{6U,4U,0U}}, +{MULS_C1D8,{7U,4U,0U}}, +{MULS_C1E0,{0U,4U,0U}}, +{MULS_C1E0,{1U,4U,0U}}, +{MULS_C1E0,{2U,4U,0U}}, +{MULS_C1E0,{3U,4U,0U}}, +{MULS_C1E0,{4U,4U,0U}}, +{MULS_C1E0,{5U,4U,0U}}, +{MULS_C1E0,{6U,4U,0U}}, +{MULS_C1E0,{7U,4U,0U}}, +{MULS_C1E8,{0U,4U,0U}}, +{MULS_C1E8,{1U,4U,0U}}, +{MULS_C1E8,{2U,4U,0U}}, +{MULS_C1E8,{3U,4U,0U}}, +{MULS_C1E8,{4U,4U,0U}}, +{MULS_C1E8,{5U,4U,0U}}, +{MULS_C1E8,{6U,4U,0U}}, +{MULS_C1E8,{7U,4U,0U}}, +{MULS_C1F0,{0U,4U,0U}}, +{MULS_C1F0,{1U,4U,0U}}, +{MULS_C1F0,{2U,4U,0U}}, +{MULS_C1F0,{3U,4U,0U}}, +{MULS_C1F0,{4U,4U,0U}}, +{MULS_C1F0,{5U,4U,0U}}, +{MULS_C1F0,{6U,4U,0U}}, +{MULS_C1F0,{7U,4U,0U}}, +{MULS_C1F8,{0U,4U,0U}}, +{MULS_C1F9,{0U,4U,0U}}, +{MULS_C1FA,{0U,4U,0U}}, +{MULS_C1FB,{0U,4U,0U}}, +{MULS_C1FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C000,{0U,5U,0U}}, +{AND_C000,{1U,5U,0U}}, +{AND_C000,{2U,5U,0U}}, +{AND_C000,{3U,5U,0U}}, +{AND_C000,{4U,5U,0U}}, +{AND_C000,{5U,5U,0U}}, +{AND_C000,{6U,5U,0U}}, +{AND_C000,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C010,{0U,5U,0U}}, +{AND_C010,{1U,5U,0U}}, +{AND_C010,{2U,5U,0U}}, +{AND_C010,{3U,5U,0U}}, +{AND_C010,{4U,5U,0U}}, +{AND_C010,{5U,5U,0U}}, +{AND_C010,{6U,5U,0U}}, +{AND_C010,{7U,5U,0U}}, +{AND_C018,{0U,5U,0U}}, +{AND_C018,{1U,5U,0U}}, +{AND_C018,{2U,5U,0U}}, +{AND_C018,{3U,5U,0U}}, +{AND_C018,{4U,5U,0U}}, +{AND_C018,{5U,5U,0U}}, +{AND_C018,{6U,5U,0U}}, +{AND_C018,{7U,5U,0U}}, +{AND_C020,{0U,5U,0U}}, +{AND_C020,{1U,5U,0U}}, +{AND_C020,{2U,5U,0U}}, +{AND_C020,{3U,5U,0U}}, +{AND_C020,{4U,5U,0U}}, +{AND_C020,{5U,5U,0U}}, +{AND_C020,{6U,5U,0U}}, +{AND_C020,{7U,5U,0U}}, +{AND_C028,{0U,5U,0U}}, +{AND_C028,{1U,5U,0U}}, +{AND_C028,{2U,5U,0U}}, +{AND_C028,{3U,5U,0U}}, +{AND_C028,{4U,5U,0U}}, +{AND_C028,{5U,5U,0U}}, +{AND_C028,{6U,5U,0U}}, +{AND_C028,{7U,5U,0U}}, +{AND_C030,{0U,5U,0U}}, +{AND_C030,{1U,5U,0U}}, +{AND_C030,{2U,5U,0U}}, +{AND_C030,{3U,5U,0U}}, +{AND_C030,{4U,5U,0U}}, +{AND_C030,{5U,5U,0U}}, +{AND_C030,{6U,5U,0U}}, +{AND_C030,{7U,5U,0U}}, +{AND_C038,{0U,5U,0U}}, +{AND_C039,{0U,5U,0U}}, +{AND_C03A,{0U,5U,0U}}, +{AND_C03B,{0U,5U,0U}}, +{AND_C03C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C040,{0U,5U,0U}}, +{AND_C040,{1U,5U,0U}}, +{AND_C040,{2U,5U,0U}}, +{AND_C040,{3U,5U,0U}}, +{AND_C040,{4U,5U,0U}}, +{AND_C040,{5U,5U,0U}}, +{AND_C040,{6U,5U,0U}}, +{AND_C040,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C050,{0U,5U,0U}}, +{AND_C050,{1U,5U,0U}}, +{AND_C050,{2U,5U,0U}}, +{AND_C050,{3U,5U,0U}}, +{AND_C050,{4U,5U,0U}}, +{AND_C050,{5U,5U,0U}}, +{AND_C050,{6U,5U,0U}}, +{AND_C050,{7U,5U,0U}}, +{AND_C058,{0U,5U,0U}}, +{AND_C058,{1U,5U,0U}}, +{AND_C058,{2U,5U,0U}}, +{AND_C058,{3U,5U,0U}}, +{AND_C058,{4U,5U,0U}}, +{AND_C058,{5U,5U,0U}}, +{AND_C058,{6U,5U,0U}}, +{AND_C058,{7U,5U,0U}}, +{AND_C060,{0U,5U,0U}}, +{AND_C060,{1U,5U,0U}}, +{AND_C060,{2U,5U,0U}}, +{AND_C060,{3U,5U,0U}}, +{AND_C060,{4U,5U,0U}}, +{AND_C060,{5U,5U,0U}}, +{AND_C060,{6U,5U,0U}}, +{AND_C060,{7U,5U,0U}}, +{AND_C068,{0U,5U,0U}}, +{AND_C068,{1U,5U,0U}}, +{AND_C068,{2U,5U,0U}}, +{AND_C068,{3U,5U,0U}}, +{AND_C068,{4U,5U,0U}}, +{AND_C068,{5U,5U,0U}}, +{AND_C068,{6U,5U,0U}}, +{AND_C068,{7U,5U,0U}}, +{AND_C070,{0U,5U,0U}}, +{AND_C070,{1U,5U,0U}}, +{AND_C070,{2U,5U,0U}}, +{AND_C070,{3U,5U,0U}}, +{AND_C070,{4U,5U,0U}}, +{AND_C070,{5U,5U,0U}}, +{AND_C070,{6U,5U,0U}}, +{AND_C070,{7U,5U,0U}}, +{AND_C078,{0U,5U,0U}}, +{AND_C079,{0U,5U,0U}}, +{AND_C07A,{0U,5U,0U}}, +{AND_C07B,{0U,5U,0U}}, +{AND_C07C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C080,{0U,5U,0U}}, +{AND_C080,{1U,5U,0U}}, +{AND_C080,{2U,5U,0U}}, +{AND_C080,{3U,5U,0U}}, +{AND_C080,{4U,5U,0U}}, +{AND_C080,{5U,5U,0U}}, +{AND_C080,{6U,5U,0U}}, +{AND_C080,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C090,{0U,5U,0U}}, +{AND_C090,{1U,5U,0U}}, +{AND_C090,{2U,5U,0U}}, +{AND_C090,{3U,5U,0U}}, +{AND_C090,{4U,5U,0U}}, +{AND_C090,{5U,5U,0U}}, +{AND_C090,{6U,5U,0U}}, +{AND_C090,{7U,5U,0U}}, +{AND_C098,{0U,5U,0U}}, +{AND_C098,{1U,5U,0U}}, +{AND_C098,{2U,5U,0U}}, +{AND_C098,{3U,5U,0U}}, +{AND_C098,{4U,5U,0U}}, +{AND_C098,{5U,5U,0U}}, +{AND_C098,{6U,5U,0U}}, +{AND_C098,{7U,5U,0U}}, +{AND_C0A0,{0U,5U,0U}}, +{AND_C0A0,{1U,5U,0U}}, +{AND_C0A0,{2U,5U,0U}}, +{AND_C0A0,{3U,5U,0U}}, +{AND_C0A0,{4U,5U,0U}}, +{AND_C0A0,{5U,5U,0U}}, +{AND_C0A0,{6U,5U,0U}}, +{AND_C0A0,{7U,5U,0U}}, +{AND_C0A8,{0U,5U,0U}}, +{AND_C0A8,{1U,5U,0U}}, +{AND_C0A8,{2U,5U,0U}}, +{AND_C0A8,{3U,5U,0U}}, +{AND_C0A8,{4U,5U,0U}}, +{AND_C0A8,{5U,5U,0U}}, +{AND_C0A8,{6U,5U,0U}}, +{AND_C0A8,{7U,5U,0U}}, +{AND_C0B0,{0U,5U,0U}}, +{AND_C0B0,{1U,5U,0U}}, +{AND_C0B0,{2U,5U,0U}}, +{AND_C0B0,{3U,5U,0U}}, +{AND_C0B0,{4U,5U,0U}}, +{AND_C0B0,{5U,5U,0U}}, +{AND_C0B0,{6U,5U,0U}}, +{AND_C0B0,{7U,5U,0U}}, +{AND_C0B8,{0U,5U,0U}}, +{AND_C0B9,{0U,5U,0U}}, +{AND_C0BA,{0U,5U,0U}}, +{AND_C0BB,{0U,5U,0U}}, +{AND_C0BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0C0,{0U,5U,0U}}, +{MULU_C0C0,{1U,5U,0U}}, +{MULU_C0C0,{2U,5U,0U}}, +{MULU_C0C0,{3U,5U,0U}}, +{MULU_C0C0,{4U,5U,0U}}, +{MULU_C0C0,{5U,5U,0U}}, +{MULU_C0C0,{6U,5U,0U}}, +{MULU_C0C0,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0D0,{0U,5U,0U}}, +{MULU_C0D0,{1U,5U,0U}}, +{MULU_C0D0,{2U,5U,0U}}, +{MULU_C0D0,{3U,5U,0U}}, +{MULU_C0D0,{4U,5U,0U}}, +{MULU_C0D0,{5U,5U,0U}}, +{MULU_C0D0,{6U,5U,0U}}, +{MULU_C0D0,{7U,5U,0U}}, +{MULU_C0D8,{0U,5U,0U}}, +{MULU_C0D8,{1U,5U,0U}}, +{MULU_C0D8,{2U,5U,0U}}, +{MULU_C0D8,{3U,5U,0U}}, +{MULU_C0D8,{4U,5U,0U}}, +{MULU_C0D8,{5U,5U,0U}}, +{MULU_C0D8,{6U,5U,0U}}, +{MULU_C0D8,{7U,5U,0U}}, +{MULU_C0E0,{0U,5U,0U}}, +{MULU_C0E0,{1U,5U,0U}}, +{MULU_C0E0,{2U,5U,0U}}, +{MULU_C0E0,{3U,5U,0U}}, +{MULU_C0E0,{4U,5U,0U}}, +{MULU_C0E0,{5U,5U,0U}}, +{MULU_C0E0,{6U,5U,0U}}, +{MULU_C0E0,{7U,5U,0U}}, +{MULU_C0E8,{0U,5U,0U}}, +{MULU_C0E8,{1U,5U,0U}}, +{MULU_C0E8,{2U,5U,0U}}, +{MULU_C0E8,{3U,5U,0U}}, +{MULU_C0E8,{4U,5U,0U}}, +{MULU_C0E8,{5U,5U,0U}}, +{MULU_C0E8,{6U,5U,0U}}, +{MULU_C0E8,{7U,5U,0U}}, +{MULU_C0F0,{0U,5U,0U}}, +{MULU_C0F0,{1U,5U,0U}}, +{MULU_C0F0,{2U,5U,0U}}, +{MULU_C0F0,{3U,5U,0U}}, +{MULU_C0F0,{4U,5U,0U}}, +{MULU_C0F0,{5U,5U,0U}}, +{MULU_C0F0,{6U,5U,0U}}, +{MULU_C0F0,{7U,5U,0U}}, +{MULU_C0F8,{0U,5U,0U}}, +{MULU_C0F9,{0U,5U,0U}}, +{MULU_C0FA,{0U,5U,0U}}, +{MULU_C0FB,{0U,5U,0U}}, +{MULU_C0FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ABCD_C100,{0U,5U,0U}}, +{ABCD_C100,{1U,5U,0U}}, +{ABCD_C100,{2U,5U,0U}}, +{ABCD_C100,{3U,5U,0U}}, +{ABCD_C100,{4U,5U,0U}}, +{ABCD_C100,{5U,5U,0U}}, +{ABCD_C100,{6U,5U,0U}}, +{ABCD_C100,{7U,5U,0U}}, +{ABCD_C108,{0U,5U,0U}}, +{ABCD_C108,{1U,5U,0U}}, +{ABCD_C108,{2U,5U,0U}}, +{ABCD_C108,{3U,5U,0U}}, +{ABCD_C108,{4U,5U,0U}}, +{ABCD_C108,{5U,5U,0U}}, +{ABCD_C108,{6U,5U,0U}}, +{ABCD_C108,{7U,5U,0U}}, +{AND_C110,{0U,5U,0U}}, +{AND_C110,{1U,5U,0U}}, +{AND_C110,{2U,5U,0U}}, +{AND_C110,{3U,5U,0U}}, +{AND_C110,{4U,5U,0U}}, +{AND_C110,{5U,5U,0U}}, +{AND_C110,{6U,5U,0U}}, +{AND_C110,{7U,5U,0U}}, +{AND_C118,{0U,5U,0U}}, +{AND_C118,{1U,5U,0U}}, +{AND_C118,{2U,5U,0U}}, +{AND_C118,{3U,5U,0U}}, +{AND_C118,{4U,5U,0U}}, +{AND_C118,{5U,5U,0U}}, +{AND_C118,{6U,5U,0U}}, +{AND_C118,{7U,5U,0U}}, +{AND_C120,{0U,5U,0U}}, +{AND_C120,{1U,5U,0U}}, +{AND_C120,{2U,5U,0U}}, +{AND_C120,{3U,5U,0U}}, +{AND_C120,{4U,5U,0U}}, +{AND_C120,{5U,5U,0U}}, +{AND_C120,{6U,5U,0U}}, +{AND_C120,{7U,5U,0U}}, +{AND_C128,{0U,5U,0U}}, +{AND_C128,{1U,5U,0U}}, +{AND_C128,{2U,5U,0U}}, +{AND_C128,{3U,5U,0U}}, +{AND_C128,{4U,5U,0U}}, +{AND_C128,{5U,5U,0U}}, +{AND_C128,{6U,5U,0U}}, +{AND_C128,{7U,5U,0U}}, +{AND_C130,{0U,5U,0U}}, +{AND_C130,{1U,5U,0U}}, +{AND_C130,{2U,5U,0U}}, +{AND_C130,{3U,5U,0U}}, +{AND_C130,{4U,5U,0U}}, +{AND_C130,{5U,5U,0U}}, +{AND_C130,{6U,5U,0U}}, +{AND_C130,{7U,5U,0U}}, +{AND_C138,{0U,5U,0U}}, +{AND_C139,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C140,{5U,0U,0U}}, +{EXG_C140,{5U,1U,0U}}, +{EXG_C140,{5U,2U,0U}}, +{EXG_C140,{5U,3U,0U}}, +{EXG_C140,{5U,4U,0U}}, +{EXG_C140,{5U,5U,0U}}, +{EXG_C140,{5U,6U,0U}}, +{EXG_C140,{5U,7U,0U}}, +{EXG_C148,{5U,0U,0U}}, +{EXG_C148,{5U,1U,0U}}, +{EXG_C148,{5U,2U,0U}}, +{EXG_C148,{5U,3U,0U}}, +{EXG_C148,{5U,4U,0U}}, +{EXG_C148,{5U,5U,0U}}, +{EXG_C148,{5U,6U,0U}}, +{EXG_C148,{5U,7U,0U}}, +{AND_C150,{0U,5U,0U}}, +{AND_C150,{1U,5U,0U}}, +{AND_C150,{2U,5U,0U}}, +{AND_C150,{3U,5U,0U}}, +{AND_C150,{4U,5U,0U}}, +{AND_C150,{5U,5U,0U}}, +{AND_C150,{6U,5U,0U}}, +{AND_C150,{7U,5U,0U}}, +{AND_C158,{0U,5U,0U}}, +{AND_C158,{1U,5U,0U}}, +{AND_C158,{2U,5U,0U}}, +{AND_C158,{3U,5U,0U}}, +{AND_C158,{4U,5U,0U}}, +{AND_C158,{5U,5U,0U}}, +{AND_C158,{6U,5U,0U}}, +{AND_C158,{7U,5U,0U}}, +{AND_C160,{0U,5U,0U}}, +{AND_C160,{1U,5U,0U}}, +{AND_C160,{2U,5U,0U}}, +{AND_C160,{3U,5U,0U}}, +{AND_C160,{4U,5U,0U}}, +{AND_C160,{5U,5U,0U}}, +{AND_C160,{6U,5U,0U}}, +{AND_C160,{7U,5U,0U}}, +{AND_C168,{0U,5U,0U}}, +{AND_C168,{1U,5U,0U}}, +{AND_C168,{2U,5U,0U}}, +{AND_C168,{3U,5U,0U}}, +{AND_C168,{4U,5U,0U}}, +{AND_C168,{5U,5U,0U}}, +{AND_C168,{6U,5U,0U}}, +{AND_C168,{7U,5U,0U}}, +{AND_C170,{0U,5U,0U}}, +{AND_C170,{1U,5U,0U}}, +{AND_C170,{2U,5U,0U}}, +{AND_C170,{3U,5U,0U}}, +{AND_C170,{4U,5U,0U}}, +{AND_C170,{5U,5U,0U}}, +{AND_C170,{6U,5U,0U}}, +{AND_C170,{7U,5U,0U}}, +{AND_C178,{0U,5U,0U}}, +{AND_C179,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C188,{5U,0U,0U}}, +{EXG_C188,{5U,1U,0U}}, +{EXG_C188,{5U,2U,0U}}, +{EXG_C188,{5U,3U,0U}}, +{EXG_C188,{5U,4U,0U}}, +{EXG_C188,{5U,5U,0U}}, +{EXG_C188,{5U,6U,0U}}, +{EXG_C188,{5U,7U,0U}}, +{AND_C190,{0U,5U,0U}}, +{AND_C190,{1U,5U,0U}}, +{AND_C190,{2U,5U,0U}}, +{AND_C190,{3U,5U,0U}}, +{AND_C190,{4U,5U,0U}}, +{AND_C190,{5U,5U,0U}}, +{AND_C190,{6U,5U,0U}}, +{AND_C190,{7U,5U,0U}}, +{AND_C198,{0U,5U,0U}}, +{AND_C198,{1U,5U,0U}}, +{AND_C198,{2U,5U,0U}}, +{AND_C198,{3U,5U,0U}}, +{AND_C198,{4U,5U,0U}}, +{AND_C198,{5U,5U,0U}}, +{AND_C198,{6U,5U,0U}}, +{AND_C198,{7U,5U,0U}}, +{AND_C1A0,{0U,5U,0U}}, +{AND_C1A0,{1U,5U,0U}}, +{AND_C1A0,{2U,5U,0U}}, +{AND_C1A0,{3U,5U,0U}}, +{AND_C1A0,{4U,5U,0U}}, +{AND_C1A0,{5U,5U,0U}}, +{AND_C1A0,{6U,5U,0U}}, +{AND_C1A0,{7U,5U,0U}}, +{AND_C1A8,{0U,5U,0U}}, +{AND_C1A8,{1U,5U,0U}}, +{AND_C1A8,{2U,5U,0U}}, +{AND_C1A8,{3U,5U,0U}}, +{AND_C1A8,{4U,5U,0U}}, +{AND_C1A8,{5U,5U,0U}}, +{AND_C1A8,{6U,5U,0U}}, +{AND_C1A8,{7U,5U,0U}}, +{AND_C1B0,{0U,5U,0U}}, +{AND_C1B0,{1U,5U,0U}}, +{AND_C1B0,{2U,5U,0U}}, +{AND_C1B0,{3U,5U,0U}}, +{AND_C1B0,{4U,5U,0U}}, +{AND_C1B0,{5U,5U,0U}}, +{AND_C1B0,{6U,5U,0U}}, +{AND_C1B0,{7U,5U,0U}}, +{AND_C1B8,{0U,5U,0U}}, +{AND_C1B9,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1C0,{0U,5U,0U}}, +{MULS_C1C0,{1U,5U,0U}}, +{MULS_C1C0,{2U,5U,0U}}, +{MULS_C1C0,{3U,5U,0U}}, +{MULS_C1C0,{4U,5U,0U}}, +{MULS_C1C0,{5U,5U,0U}}, +{MULS_C1C0,{6U,5U,0U}}, +{MULS_C1C0,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1D0,{0U,5U,0U}}, +{MULS_C1D0,{1U,5U,0U}}, +{MULS_C1D0,{2U,5U,0U}}, +{MULS_C1D0,{3U,5U,0U}}, +{MULS_C1D0,{4U,5U,0U}}, +{MULS_C1D0,{5U,5U,0U}}, +{MULS_C1D0,{6U,5U,0U}}, +{MULS_C1D0,{7U,5U,0U}}, +{MULS_C1D8,{0U,5U,0U}}, +{MULS_C1D8,{1U,5U,0U}}, +{MULS_C1D8,{2U,5U,0U}}, +{MULS_C1D8,{3U,5U,0U}}, +{MULS_C1D8,{4U,5U,0U}}, +{MULS_C1D8,{5U,5U,0U}}, +{MULS_C1D8,{6U,5U,0U}}, +{MULS_C1D8,{7U,5U,0U}}, +{MULS_C1E0,{0U,5U,0U}}, +{MULS_C1E0,{1U,5U,0U}}, +{MULS_C1E0,{2U,5U,0U}}, +{MULS_C1E0,{3U,5U,0U}}, +{MULS_C1E0,{4U,5U,0U}}, +{MULS_C1E0,{5U,5U,0U}}, +{MULS_C1E0,{6U,5U,0U}}, +{MULS_C1E0,{7U,5U,0U}}, +{MULS_C1E8,{0U,5U,0U}}, +{MULS_C1E8,{1U,5U,0U}}, +{MULS_C1E8,{2U,5U,0U}}, +{MULS_C1E8,{3U,5U,0U}}, +{MULS_C1E8,{4U,5U,0U}}, +{MULS_C1E8,{5U,5U,0U}}, +{MULS_C1E8,{6U,5U,0U}}, +{MULS_C1E8,{7U,5U,0U}}, +{MULS_C1F0,{0U,5U,0U}}, +{MULS_C1F0,{1U,5U,0U}}, +{MULS_C1F0,{2U,5U,0U}}, +{MULS_C1F0,{3U,5U,0U}}, +{MULS_C1F0,{4U,5U,0U}}, +{MULS_C1F0,{5U,5U,0U}}, +{MULS_C1F0,{6U,5U,0U}}, +{MULS_C1F0,{7U,5U,0U}}, +{MULS_C1F8,{0U,5U,0U}}, +{MULS_C1F9,{0U,5U,0U}}, +{MULS_C1FA,{0U,5U,0U}}, +{MULS_C1FB,{0U,5U,0U}}, +{MULS_C1FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C000,{0U,6U,0U}}, +{AND_C000,{1U,6U,0U}}, +{AND_C000,{2U,6U,0U}}, +{AND_C000,{3U,6U,0U}}, +{AND_C000,{4U,6U,0U}}, +{AND_C000,{5U,6U,0U}}, +{AND_C000,{6U,6U,0U}}, +{AND_C000,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C010,{0U,6U,0U}}, +{AND_C010,{1U,6U,0U}}, +{AND_C010,{2U,6U,0U}}, +{AND_C010,{3U,6U,0U}}, +{AND_C010,{4U,6U,0U}}, +{AND_C010,{5U,6U,0U}}, +{AND_C010,{6U,6U,0U}}, +{AND_C010,{7U,6U,0U}}, +{AND_C018,{0U,6U,0U}}, +{AND_C018,{1U,6U,0U}}, +{AND_C018,{2U,6U,0U}}, +{AND_C018,{3U,6U,0U}}, +{AND_C018,{4U,6U,0U}}, +{AND_C018,{5U,6U,0U}}, +{AND_C018,{6U,6U,0U}}, +{AND_C018,{7U,6U,0U}}, +{AND_C020,{0U,6U,0U}}, +{AND_C020,{1U,6U,0U}}, +{AND_C020,{2U,6U,0U}}, +{AND_C020,{3U,6U,0U}}, +{AND_C020,{4U,6U,0U}}, +{AND_C020,{5U,6U,0U}}, +{AND_C020,{6U,6U,0U}}, +{AND_C020,{7U,6U,0U}}, +{AND_C028,{0U,6U,0U}}, +{AND_C028,{1U,6U,0U}}, +{AND_C028,{2U,6U,0U}}, +{AND_C028,{3U,6U,0U}}, +{AND_C028,{4U,6U,0U}}, +{AND_C028,{5U,6U,0U}}, +{AND_C028,{6U,6U,0U}}, +{AND_C028,{7U,6U,0U}}, +{AND_C030,{0U,6U,0U}}, +{AND_C030,{1U,6U,0U}}, +{AND_C030,{2U,6U,0U}}, +{AND_C030,{3U,6U,0U}}, +{AND_C030,{4U,6U,0U}}, +{AND_C030,{5U,6U,0U}}, +{AND_C030,{6U,6U,0U}}, +{AND_C030,{7U,6U,0U}}, +{AND_C038,{0U,6U,0U}}, +{AND_C039,{0U,6U,0U}}, +{AND_C03A,{0U,6U,0U}}, +{AND_C03B,{0U,6U,0U}}, +{AND_C03C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C040,{0U,6U,0U}}, +{AND_C040,{1U,6U,0U}}, +{AND_C040,{2U,6U,0U}}, +{AND_C040,{3U,6U,0U}}, +{AND_C040,{4U,6U,0U}}, +{AND_C040,{5U,6U,0U}}, +{AND_C040,{6U,6U,0U}}, +{AND_C040,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C050,{0U,6U,0U}}, +{AND_C050,{1U,6U,0U}}, +{AND_C050,{2U,6U,0U}}, +{AND_C050,{3U,6U,0U}}, +{AND_C050,{4U,6U,0U}}, +{AND_C050,{5U,6U,0U}}, +{AND_C050,{6U,6U,0U}}, +{AND_C050,{7U,6U,0U}}, +{AND_C058,{0U,6U,0U}}, +{AND_C058,{1U,6U,0U}}, +{AND_C058,{2U,6U,0U}}, +{AND_C058,{3U,6U,0U}}, +{AND_C058,{4U,6U,0U}}, +{AND_C058,{5U,6U,0U}}, +{AND_C058,{6U,6U,0U}}, +{AND_C058,{7U,6U,0U}}, +{AND_C060,{0U,6U,0U}}, +{AND_C060,{1U,6U,0U}}, +{AND_C060,{2U,6U,0U}}, +{AND_C060,{3U,6U,0U}}, +{AND_C060,{4U,6U,0U}}, +{AND_C060,{5U,6U,0U}}, +{AND_C060,{6U,6U,0U}}, +{AND_C060,{7U,6U,0U}}, +{AND_C068,{0U,6U,0U}}, +{AND_C068,{1U,6U,0U}}, +{AND_C068,{2U,6U,0U}}, +{AND_C068,{3U,6U,0U}}, +{AND_C068,{4U,6U,0U}}, +{AND_C068,{5U,6U,0U}}, +{AND_C068,{6U,6U,0U}}, +{AND_C068,{7U,6U,0U}}, +{AND_C070,{0U,6U,0U}}, +{AND_C070,{1U,6U,0U}}, +{AND_C070,{2U,6U,0U}}, +{AND_C070,{3U,6U,0U}}, +{AND_C070,{4U,6U,0U}}, +{AND_C070,{5U,6U,0U}}, +{AND_C070,{6U,6U,0U}}, +{AND_C070,{7U,6U,0U}}, +{AND_C078,{0U,6U,0U}}, +{AND_C079,{0U,6U,0U}}, +{AND_C07A,{0U,6U,0U}}, +{AND_C07B,{0U,6U,0U}}, +{AND_C07C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C080,{0U,6U,0U}}, +{AND_C080,{1U,6U,0U}}, +{AND_C080,{2U,6U,0U}}, +{AND_C080,{3U,6U,0U}}, +{AND_C080,{4U,6U,0U}}, +{AND_C080,{5U,6U,0U}}, +{AND_C080,{6U,6U,0U}}, +{AND_C080,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C090,{0U,6U,0U}}, +{AND_C090,{1U,6U,0U}}, +{AND_C090,{2U,6U,0U}}, +{AND_C090,{3U,6U,0U}}, +{AND_C090,{4U,6U,0U}}, +{AND_C090,{5U,6U,0U}}, +{AND_C090,{6U,6U,0U}}, +{AND_C090,{7U,6U,0U}}, +{AND_C098,{0U,6U,0U}}, +{AND_C098,{1U,6U,0U}}, +{AND_C098,{2U,6U,0U}}, +{AND_C098,{3U,6U,0U}}, +{AND_C098,{4U,6U,0U}}, +{AND_C098,{5U,6U,0U}}, +{AND_C098,{6U,6U,0U}}, +{AND_C098,{7U,6U,0U}}, +{AND_C0A0,{0U,6U,0U}}, +{AND_C0A0,{1U,6U,0U}}, +{AND_C0A0,{2U,6U,0U}}, +{AND_C0A0,{3U,6U,0U}}, +{AND_C0A0,{4U,6U,0U}}, +{AND_C0A0,{5U,6U,0U}}, +{AND_C0A0,{6U,6U,0U}}, +{AND_C0A0,{7U,6U,0U}}, +{AND_C0A8,{0U,6U,0U}}, +{AND_C0A8,{1U,6U,0U}}, +{AND_C0A8,{2U,6U,0U}}, +{AND_C0A8,{3U,6U,0U}}, +{AND_C0A8,{4U,6U,0U}}, +{AND_C0A8,{5U,6U,0U}}, +{AND_C0A8,{6U,6U,0U}}, +{AND_C0A8,{7U,6U,0U}}, +{AND_C0B0,{0U,6U,0U}}, +{AND_C0B0,{1U,6U,0U}}, +{AND_C0B0,{2U,6U,0U}}, +{AND_C0B0,{3U,6U,0U}}, +{AND_C0B0,{4U,6U,0U}}, +{AND_C0B0,{5U,6U,0U}}, +{AND_C0B0,{6U,6U,0U}}, +{AND_C0B0,{7U,6U,0U}}, +{AND_C0B8,{0U,6U,0U}}, +{AND_C0B9,{0U,6U,0U}}, +{AND_C0BA,{0U,6U,0U}}, +{AND_C0BB,{0U,6U,0U}}, +{AND_C0BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0C0,{0U,6U,0U}}, +{MULU_C0C0,{1U,6U,0U}}, +{MULU_C0C0,{2U,6U,0U}}, +{MULU_C0C0,{3U,6U,0U}}, +{MULU_C0C0,{4U,6U,0U}}, +{MULU_C0C0,{5U,6U,0U}}, +{MULU_C0C0,{6U,6U,0U}}, +{MULU_C0C0,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0D0,{0U,6U,0U}}, +{MULU_C0D0,{1U,6U,0U}}, +{MULU_C0D0,{2U,6U,0U}}, +{MULU_C0D0,{3U,6U,0U}}, +{MULU_C0D0,{4U,6U,0U}}, +{MULU_C0D0,{5U,6U,0U}}, +{MULU_C0D0,{6U,6U,0U}}, +{MULU_C0D0,{7U,6U,0U}}, +{MULU_C0D8,{0U,6U,0U}}, +{MULU_C0D8,{1U,6U,0U}}, +{MULU_C0D8,{2U,6U,0U}}, +{MULU_C0D8,{3U,6U,0U}}, +{MULU_C0D8,{4U,6U,0U}}, +{MULU_C0D8,{5U,6U,0U}}, +{MULU_C0D8,{6U,6U,0U}}, +{MULU_C0D8,{7U,6U,0U}}, +{MULU_C0E0,{0U,6U,0U}}, +{MULU_C0E0,{1U,6U,0U}}, +{MULU_C0E0,{2U,6U,0U}}, +{MULU_C0E0,{3U,6U,0U}}, +{MULU_C0E0,{4U,6U,0U}}, +{MULU_C0E0,{5U,6U,0U}}, +{MULU_C0E0,{6U,6U,0U}}, +{MULU_C0E0,{7U,6U,0U}}, +{MULU_C0E8,{0U,6U,0U}}, +{MULU_C0E8,{1U,6U,0U}}, +{MULU_C0E8,{2U,6U,0U}}, +{MULU_C0E8,{3U,6U,0U}}, +{MULU_C0E8,{4U,6U,0U}}, +{MULU_C0E8,{5U,6U,0U}}, +{MULU_C0E8,{6U,6U,0U}}, +{MULU_C0E8,{7U,6U,0U}}, +{MULU_C0F0,{0U,6U,0U}}, +{MULU_C0F0,{1U,6U,0U}}, +{MULU_C0F0,{2U,6U,0U}}, +{MULU_C0F0,{3U,6U,0U}}, +{MULU_C0F0,{4U,6U,0U}}, +{MULU_C0F0,{5U,6U,0U}}, +{MULU_C0F0,{6U,6U,0U}}, +{MULU_C0F0,{7U,6U,0U}}, +{MULU_C0F8,{0U,6U,0U}}, +{MULU_C0F9,{0U,6U,0U}}, +{MULU_C0FA,{0U,6U,0U}}, +{MULU_C0FB,{0U,6U,0U}}, +{MULU_C0FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ABCD_C100,{0U,6U,0U}}, +{ABCD_C100,{1U,6U,0U}}, +{ABCD_C100,{2U,6U,0U}}, +{ABCD_C100,{3U,6U,0U}}, +{ABCD_C100,{4U,6U,0U}}, +{ABCD_C100,{5U,6U,0U}}, +{ABCD_C100,{6U,6U,0U}}, +{ABCD_C100,{7U,6U,0U}}, +{ABCD_C108,{0U,6U,0U}}, +{ABCD_C108,{1U,6U,0U}}, +{ABCD_C108,{2U,6U,0U}}, +{ABCD_C108,{3U,6U,0U}}, +{ABCD_C108,{4U,6U,0U}}, +{ABCD_C108,{5U,6U,0U}}, +{ABCD_C108,{6U,6U,0U}}, +{ABCD_C108,{7U,6U,0U}}, +{AND_C110,{0U,6U,0U}}, +{AND_C110,{1U,6U,0U}}, +{AND_C110,{2U,6U,0U}}, +{AND_C110,{3U,6U,0U}}, +{AND_C110,{4U,6U,0U}}, +{AND_C110,{5U,6U,0U}}, +{AND_C110,{6U,6U,0U}}, +{AND_C110,{7U,6U,0U}}, +{AND_C118,{0U,6U,0U}}, +{AND_C118,{1U,6U,0U}}, +{AND_C118,{2U,6U,0U}}, +{AND_C118,{3U,6U,0U}}, +{AND_C118,{4U,6U,0U}}, +{AND_C118,{5U,6U,0U}}, +{AND_C118,{6U,6U,0U}}, +{AND_C118,{7U,6U,0U}}, +{AND_C120,{0U,6U,0U}}, +{AND_C120,{1U,6U,0U}}, +{AND_C120,{2U,6U,0U}}, +{AND_C120,{3U,6U,0U}}, +{AND_C120,{4U,6U,0U}}, +{AND_C120,{5U,6U,0U}}, +{AND_C120,{6U,6U,0U}}, +{AND_C120,{7U,6U,0U}}, +{AND_C128,{0U,6U,0U}}, +{AND_C128,{1U,6U,0U}}, +{AND_C128,{2U,6U,0U}}, +{AND_C128,{3U,6U,0U}}, +{AND_C128,{4U,6U,0U}}, +{AND_C128,{5U,6U,0U}}, +{AND_C128,{6U,6U,0U}}, +{AND_C128,{7U,6U,0U}}, +{AND_C130,{0U,6U,0U}}, +{AND_C130,{1U,6U,0U}}, +{AND_C130,{2U,6U,0U}}, +{AND_C130,{3U,6U,0U}}, +{AND_C130,{4U,6U,0U}}, +{AND_C130,{5U,6U,0U}}, +{AND_C130,{6U,6U,0U}}, +{AND_C130,{7U,6U,0U}}, +{AND_C138,{0U,6U,0U}}, +{AND_C139,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C140,{6U,0U,0U}}, +{EXG_C140,{6U,1U,0U}}, +{EXG_C140,{6U,2U,0U}}, +{EXG_C140,{6U,3U,0U}}, +{EXG_C140,{6U,4U,0U}}, +{EXG_C140,{6U,5U,0U}}, +{EXG_C140,{6U,6U,0U}}, +{EXG_C140,{6U,7U,0U}}, +{EXG_C148,{6U,0U,0U}}, +{EXG_C148,{6U,1U,0U}}, +{EXG_C148,{6U,2U,0U}}, +{EXG_C148,{6U,3U,0U}}, +{EXG_C148,{6U,4U,0U}}, +{EXG_C148,{6U,5U,0U}}, +{EXG_C148,{6U,6U,0U}}, +{EXG_C148,{6U,7U,0U}}, +{AND_C150,{0U,6U,0U}}, +{AND_C150,{1U,6U,0U}}, +{AND_C150,{2U,6U,0U}}, +{AND_C150,{3U,6U,0U}}, +{AND_C150,{4U,6U,0U}}, +{AND_C150,{5U,6U,0U}}, +{AND_C150,{6U,6U,0U}}, +{AND_C150,{7U,6U,0U}}, +{AND_C158,{0U,6U,0U}}, +{AND_C158,{1U,6U,0U}}, +{AND_C158,{2U,6U,0U}}, +{AND_C158,{3U,6U,0U}}, +{AND_C158,{4U,6U,0U}}, +{AND_C158,{5U,6U,0U}}, +{AND_C158,{6U,6U,0U}}, +{AND_C158,{7U,6U,0U}}, +{AND_C160,{0U,6U,0U}}, +{AND_C160,{1U,6U,0U}}, +{AND_C160,{2U,6U,0U}}, +{AND_C160,{3U,6U,0U}}, +{AND_C160,{4U,6U,0U}}, +{AND_C160,{5U,6U,0U}}, +{AND_C160,{6U,6U,0U}}, +{AND_C160,{7U,6U,0U}}, +{AND_C168,{0U,6U,0U}}, +{AND_C168,{1U,6U,0U}}, +{AND_C168,{2U,6U,0U}}, +{AND_C168,{3U,6U,0U}}, +{AND_C168,{4U,6U,0U}}, +{AND_C168,{5U,6U,0U}}, +{AND_C168,{6U,6U,0U}}, +{AND_C168,{7U,6U,0U}}, +{AND_C170,{0U,6U,0U}}, +{AND_C170,{1U,6U,0U}}, +{AND_C170,{2U,6U,0U}}, +{AND_C170,{3U,6U,0U}}, +{AND_C170,{4U,6U,0U}}, +{AND_C170,{5U,6U,0U}}, +{AND_C170,{6U,6U,0U}}, +{AND_C170,{7U,6U,0U}}, +{AND_C178,{0U,6U,0U}}, +{AND_C179,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C188,{6U,0U,0U}}, +{EXG_C188,{6U,1U,0U}}, +{EXG_C188,{6U,2U,0U}}, +{EXG_C188,{6U,3U,0U}}, +{EXG_C188,{6U,4U,0U}}, +{EXG_C188,{6U,5U,0U}}, +{EXG_C188,{6U,6U,0U}}, +{EXG_C188,{6U,7U,0U}}, +{AND_C190,{0U,6U,0U}}, +{AND_C190,{1U,6U,0U}}, +{AND_C190,{2U,6U,0U}}, +{AND_C190,{3U,6U,0U}}, +{AND_C190,{4U,6U,0U}}, +{AND_C190,{5U,6U,0U}}, +{AND_C190,{6U,6U,0U}}, +{AND_C190,{7U,6U,0U}}, +{AND_C198,{0U,6U,0U}}, +{AND_C198,{1U,6U,0U}}, +{AND_C198,{2U,6U,0U}}, +{AND_C198,{3U,6U,0U}}, +{AND_C198,{4U,6U,0U}}, +{AND_C198,{5U,6U,0U}}, +{AND_C198,{6U,6U,0U}}, +{AND_C198,{7U,6U,0U}}, +{AND_C1A0,{0U,6U,0U}}, +{AND_C1A0,{1U,6U,0U}}, +{AND_C1A0,{2U,6U,0U}}, +{AND_C1A0,{3U,6U,0U}}, +{AND_C1A0,{4U,6U,0U}}, +{AND_C1A0,{5U,6U,0U}}, +{AND_C1A0,{6U,6U,0U}}, +{AND_C1A0,{7U,6U,0U}}, +{AND_C1A8,{0U,6U,0U}}, +{AND_C1A8,{1U,6U,0U}}, +{AND_C1A8,{2U,6U,0U}}, +{AND_C1A8,{3U,6U,0U}}, +{AND_C1A8,{4U,6U,0U}}, +{AND_C1A8,{5U,6U,0U}}, +{AND_C1A8,{6U,6U,0U}}, +{AND_C1A8,{7U,6U,0U}}, +{AND_C1B0,{0U,6U,0U}}, +{AND_C1B0,{1U,6U,0U}}, +{AND_C1B0,{2U,6U,0U}}, +{AND_C1B0,{3U,6U,0U}}, +{AND_C1B0,{4U,6U,0U}}, +{AND_C1B0,{5U,6U,0U}}, +{AND_C1B0,{6U,6U,0U}}, +{AND_C1B0,{7U,6U,0U}}, +{AND_C1B8,{0U,6U,0U}}, +{AND_C1B9,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1C0,{0U,6U,0U}}, +{MULS_C1C0,{1U,6U,0U}}, +{MULS_C1C0,{2U,6U,0U}}, +{MULS_C1C0,{3U,6U,0U}}, +{MULS_C1C0,{4U,6U,0U}}, +{MULS_C1C0,{5U,6U,0U}}, +{MULS_C1C0,{6U,6U,0U}}, +{MULS_C1C0,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1D0,{0U,6U,0U}}, +{MULS_C1D0,{1U,6U,0U}}, +{MULS_C1D0,{2U,6U,0U}}, +{MULS_C1D0,{3U,6U,0U}}, +{MULS_C1D0,{4U,6U,0U}}, +{MULS_C1D0,{5U,6U,0U}}, +{MULS_C1D0,{6U,6U,0U}}, +{MULS_C1D0,{7U,6U,0U}}, +{MULS_C1D8,{0U,6U,0U}}, +{MULS_C1D8,{1U,6U,0U}}, +{MULS_C1D8,{2U,6U,0U}}, +{MULS_C1D8,{3U,6U,0U}}, +{MULS_C1D8,{4U,6U,0U}}, +{MULS_C1D8,{5U,6U,0U}}, +{MULS_C1D8,{6U,6U,0U}}, +{MULS_C1D8,{7U,6U,0U}}, +{MULS_C1E0,{0U,6U,0U}}, +{MULS_C1E0,{1U,6U,0U}}, +{MULS_C1E0,{2U,6U,0U}}, +{MULS_C1E0,{3U,6U,0U}}, +{MULS_C1E0,{4U,6U,0U}}, +{MULS_C1E0,{5U,6U,0U}}, +{MULS_C1E0,{6U,6U,0U}}, +{MULS_C1E0,{7U,6U,0U}}, +{MULS_C1E8,{0U,6U,0U}}, +{MULS_C1E8,{1U,6U,0U}}, +{MULS_C1E8,{2U,6U,0U}}, +{MULS_C1E8,{3U,6U,0U}}, +{MULS_C1E8,{4U,6U,0U}}, +{MULS_C1E8,{5U,6U,0U}}, +{MULS_C1E8,{6U,6U,0U}}, +{MULS_C1E8,{7U,6U,0U}}, +{MULS_C1F0,{0U,6U,0U}}, +{MULS_C1F0,{1U,6U,0U}}, +{MULS_C1F0,{2U,6U,0U}}, +{MULS_C1F0,{3U,6U,0U}}, +{MULS_C1F0,{4U,6U,0U}}, +{MULS_C1F0,{5U,6U,0U}}, +{MULS_C1F0,{6U,6U,0U}}, +{MULS_C1F0,{7U,6U,0U}}, +{MULS_C1F8,{0U,6U,0U}}, +{MULS_C1F9,{0U,6U,0U}}, +{MULS_C1FA,{0U,6U,0U}}, +{MULS_C1FB,{0U,6U,0U}}, +{MULS_C1FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C000,{0U,7U,0U}}, +{AND_C000,{1U,7U,0U}}, +{AND_C000,{2U,7U,0U}}, +{AND_C000,{3U,7U,0U}}, +{AND_C000,{4U,7U,0U}}, +{AND_C000,{5U,7U,0U}}, +{AND_C000,{6U,7U,0U}}, +{AND_C000,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C010,{0U,7U,0U}}, +{AND_C010,{1U,7U,0U}}, +{AND_C010,{2U,7U,0U}}, +{AND_C010,{3U,7U,0U}}, +{AND_C010,{4U,7U,0U}}, +{AND_C010,{5U,7U,0U}}, +{AND_C010,{6U,7U,0U}}, +{AND_C010,{7U,7U,0U}}, +{AND_C018,{0U,7U,0U}}, +{AND_C018,{1U,7U,0U}}, +{AND_C018,{2U,7U,0U}}, +{AND_C018,{3U,7U,0U}}, +{AND_C018,{4U,7U,0U}}, +{AND_C018,{5U,7U,0U}}, +{AND_C018,{6U,7U,0U}}, +{AND_C018,{7U,7U,0U}}, +{AND_C020,{0U,7U,0U}}, +{AND_C020,{1U,7U,0U}}, +{AND_C020,{2U,7U,0U}}, +{AND_C020,{3U,7U,0U}}, +{AND_C020,{4U,7U,0U}}, +{AND_C020,{5U,7U,0U}}, +{AND_C020,{6U,7U,0U}}, +{AND_C020,{7U,7U,0U}}, +{AND_C028,{0U,7U,0U}}, +{AND_C028,{1U,7U,0U}}, +{AND_C028,{2U,7U,0U}}, +{AND_C028,{3U,7U,0U}}, +{AND_C028,{4U,7U,0U}}, +{AND_C028,{5U,7U,0U}}, +{AND_C028,{6U,7U,0U}}, +{AND_C028,{7U,7U,0U}}, +{AND_C030,{0U,7U,0U}}, +{AND_C030,{1U,7U,0U}}, +{AND_C030,{2U,7U,0U}}, +{AND_C030,{3U,7U,0U}}, +{AND_C030,{4U,7U,0U}}, +{AND_C030,{5U,7U,0U}}, +{AND_C030,{6U,7U,0U}}, +{AND_C030,{7U,7U,0U}}, +{AND_C038,{0U,7U,0U}}, +{AND_C039,{0U,7U,0U}}, +{AND_C03A,{0U,7U,0U}}, +{AND_C03B,{0U,7U,0U}}, +{AND_C03C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C040,{0U,7U,0U}}, +{AND_C040,{1U,7U,0U}}, +{AND_C040,{2U,7U,0U}}, +{AND_C040,{3U,7U,0U}}, +{AND_C040,{4U,7U,0U}}, +{AND_C040,{5U,7U,0U}}, +{AND_C040,{6U,7U,0U}}, +{AND_C040,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C050,{0U,7U,0U}}, +{AND_C050,{1U,7U,0U}}, +{AND_C050,{2U,7U,0U}}, +{AND_C050,{3U,7U,0U}}, +{AND_C050,{4U,7U,0U}}, +{AND_C050,{5U,7U,0U}}, +{AND_C050,{6U,7U,0U}}, +{AND_C050,{7U,7U,0U}}, +{AND_C058,{0U,7U,0U}}, +{AND_C058,{1U,7U,0U}}, +{AND_C058,{2U,7U,0U}}, +{AND_C058,{3U,7U,0U}}, +{AND_C058,{4U,7U,0U}}, +{AND_C058,{5U,7U,0U}}, +{AND_C058,{6U,7U,0U}}, +{AND_C058,{7U,7U,0U}}, +{AND_C060,{0U,7U,0U}}, +{AND_C060,{1U,7U,0U}}, +{AND_C060,{2U,7U,0U}}, +{AND_C060,{3U,7U,0U}}, +{AND_C060,{4U,7U,0U}}, +{AND_C060,{5U,7U,0U}}, +{AND_C060,{6U,7U,0U}}, +{AND_C060,{7U,7U,0U}}, +{AND_C068,{0U,7U,0U}}, +{AND_C068,{1U,7U,0U}}, +{AND_C068,{2U,7U,0U}}, +{AND_C068,{3U,7U,0U}}, +{AND_C068,{4U,7U,0U}}, +{AND_C068,{5U,7U,0U}}, +{AND_C068,{6U,7U,0U}}, +{AND_C068,{7U,7U,0U}}, +{AND_C070,{0U,7U,0U}}, +{AND_C070,{1U,7U,0U}}, +{AND_C070,{2U,7U,0U}}, +{AND_C070,{3U,7U,0U}}, +{AND_C070,{4U,7U,0U}}, +{AND_C070,{5U,7U,0U}}, +{AND_C070,{6U,7U,0U}}, +{AND_C070,{7U,7U,0U}}, +{AND_C078,{0U,7U,0U}}, +{AND_C079,{0U,7U,0U}}, +{AND_C07A,{0U,7U,0U}}, +{AND_C07B,{0U,7U,0U}}, +{AND_C07C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C080,{0U,7U,0U}}, +{AND_C080,{1U,7U,0U}}, +{AND_C080,{2U,7U,0U}}, +{AND_C080,{3U,7U,0U}}, +{AND_C080,{4U,7U,0U}}, +{AND_C080,{5U,7U,0U}}, +{AND_C080,{6U,7U,0U}}, +{AND_C080,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{AND_C090,{0U,7U,0U}}, +{AND_C090,{1U,7U,0U}}, +{AND_C090,{2U,7U,0U}}, +{AND_C090,{3U,7U,0U}}, +{AND_C090,{4U,7U,0U}}, +{AND_C090,{5U,7U,0U}}, +{AND_C090,{6U,7U,0U}}, +{AND_C090,{7U,7U,0U}}, +{AND_C098,{0U,7U,0U}}, +{AND_C098,{1U,7U,0U}}, +{AND_C098,{2U,7U,0U}}, +{AND_C098,{3U,7U,0U}}, +{AND_C098,{4U,7U,0U}}, +{AND_C098,{5U,7U,0U}}, +{AND_C098,{6U,7U,0U}}, +{AND_C098,{7U,7U,0U}}, +{AND_C0A0,{0U,7U,0U}}, +{AND_C0A0,{1U,7U,0U}}, +{AND_C0A0,{2U,7U,0U}}, +{AND_C0A0,{3U,7U,0U}}, +{AND_C0A0,{4U,7U,0U}}, +{AND_C0A0,{5U,7U,0U}}, +{AND_C0A0,{6U,7U,0U}}, +{AND_C0A0,{7U,7U,0U}}, +{AND_C0A8,{0U,7U,0U}}, +{AND_C0A8,{1U,7U,0U}}, +{AND_C0A8,{2U,7U,0U}}, +{AND_C0A8,{3U,7U,0U}}, +{AND_C0A8,{4U,7U,0U}}, +{AND_C0A8,{5U,7U,0U}}, +{AND_C0A8,{6U,7U,0U}}, +{AND_C0A8,{7U,7U,0U}}, +{AND_C0B0,{0U,7U,0U}}, +{AND_C0B0,{1U,7U,0U}}, +{AND_C0B0,{2U,7U,0U}}, +{AND_C0B0,{3U,7U,0U}}, +{AND_C0B0,{4U,7U,0U}}, +{AND_C0B0,{5U,7U,0U}}, +{AND_C0B0,{6U,7U,0U}}, +{AND_C0B0,{7U,7U,0U}}, +{AND_C0B8,{0U,7U,0U}}, +{AND_C0B9,{0U,7U,0U}}, +{AND_C0BA,{0U,7U,0U}}, +{AND_C0BB,{0U,7U,0U}}, +{AND_C0BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0C0,{0U,7U,0U}}, +{MULU_C0C0,{1U,7U,0U}}, +{MULU_C0C0,{2U,7U,0U}}, +{MULU_C0C0,{3U,7U,0U}}, +{MULU_C0C0,{4U,7U,0U}}, +{MULU_C0C0,{5U,7U,0U}}, +{MULU_C0C0,{6U,7U,0U}}, +{MULU_C0C0,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULU_C0D0,{0U,7U,0U}}, +{MULU_C0D0,{1U,7U,0U}}, +{MULU_C0D0,{2U,7U,0U}}, +{MULU_C0D0,{3U,7U,0U}}, +{MULU_C0D0,{4U,7U,0U}}, +{MULU_C0D0,{5U,7U,0U}}, +{MULU_C0D0,{6U,7U,0U}}, +{MULU_C0D0,{7U,7U,0U}}, +{MULU_C0D8,{0U,7U,0U}}, +{MULU_C0D8,{1U,7U,0U}}, +{MULU_C0D8,{2U,7U,0U}}, +{MULU_C0D8,{3U,7U,0U}}, +{MULU_C0D8,{4U,7U,0U}}, +{MULU_C0D8,{5U,7U,0U}}, +{MULU_C0D8,{6U,7U,0U}}, +{MULU_C0D8,{7U,7U,0U}}, +{MULU_C0E0,{0U,7U,0U}}, +{MULU_C0E0,{1U,7U,0U}}, +{MULU_C0E0,{2U,7U,0U}}, +{MULU_C0E0,{3U,7U,0U}}, +{MULU_C0E0,{4U,7U,0U}}, +{MULU_C0E0,{5U,7U,0U}}, +{MULU_C0E0,{6U,7U,0U}}, +{MULU_C0E0,{7U,7U,0U}}, +{MULU_C0E8,{0U,7U,0U}}, +{MULU_C0E8,{1U,7U,0U}}, +{MULU_C0E8,{2U,7U,0U}}, +{MULU_C0E8,{3U,7U,0U}}, +{MULU_C0E8,{4U,7U,0U}}, +{MULU_C0E8,{5U,7U,0U}}, +{MULU_C0E8,{6U,7U,0U}}, +{MULU_C0E8,{7U,7U,0U}}, +{MULU_C0F0,{0U,7U,0U}}, +{MULU_C0F0,{1U,7U,0U}}, +{MULU_C0F0,{2U,7U,0U}}, +{MULU_C0F0,{3U,7U,0U}}, +{MULU_C0F0,{4U,7U,0U}}, +{MULU_C0F0,{5U,7U,0U}}, +{MULU_C0F0,{6U,7U,0U}}, +{MULU_C0F0,{7U,7U,0U}}, +{MULU_C0F8,{0U,7U,0U}}, +{MULU_C0F9,{0U,7U,0U}}, +{MULU_C0FA,{0U,7U,0U}}, +{MULU_C0FB,{0U,7U,0U}}, +{MULU_C0FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ABCD_C100,{0U,7U,0U}}, +{ABCD_C100,{1U,7U,0U}}, +{ABCD_C100,{2U,7U,0U}}, +{ABCD_C100,{3U,7U,0U}}, +{ABCD_C100,{4U,7U,0U}}, +{ABCD_C100,{5U,7U,0U}}, +{ABCD_C100,{6U,7U,0U}}, +{ABCD_C100,{7U,7U,0U}}, +{ABCD_C108,{0U,7U,0U}}, +{ABCD_C108,{1U,7U,0U}}, +{ABCD_C108,{2U,7U,0U}}, +{ABCD_C108,{3U,7U,0U}}, +{ABCD_C108,{4U,7U,0U}}, +{ABCD_C108,{5U,7U,0U}}, +{ABCD_C108,{6U,7U,0U}}, +{ABCD_C108,{7U,7U,0U}}, +{AND_C110,{0U,7U,0U}}, +{AND_C110,{1U,7U,0U}}, +{AND_C110,{2U,7U,0U}}, +{AND_C110,{3U,7U,0U}}, +{AND_C110,{4U,7U,0U}}, +{AND_C110,{5U,7U,0U}}, +{AND_C110,{6U,7U,0U}}, +{AND_C110,{7U,7U,0U}}, +{AND_C118,{0U,7U,0U}}, +{AND_C118,{1U,7U,0U}}, +{AND_C118,{2U,7U,0U}}, +{AND_C118,{3U,7U,0U}}, +{AND_C118,{4U,7U,0U}}, +{AND_C118,{5U,7U,0U}}, +{AND_C118,{6U,7U,0U}}, +{AND_C118,{7U,7U,0U}}, +{AND_C120,{0U,7U,0U}}, +{AND_C120,{1U,7U,0U}}, +{AND_C120,{2U,7U,0U}}, +{AND_C120,{3U,7U,0U}}, +{AND_C120,{4U,7U,0U}}, +{AND_C120,{5U,7U,0U}}, +{AND_C120,{6U,7U,0U}}, +{AND_C120,{7U,7U,0U}}, +{AND_C128,{0U,7U,0U}}, +{AND_C128,{1U,7U,0U}}, +{AND_C128,{2U,7U,0U}}, +{AND_C128,{3U,7U,0U}}, +{AND_C128,{4U,7U,0U}}, +{AND_C128,{5U,7U,0U}}, +{AND_C128,{6U,7U,0U}}, +{AND_C128,{7U,7U,0U}}, +{AND_C130,{0U,7U,0U}}, +{AND_C130,{1U,7U,0U}}, +{AND_C130,{2U,7U,0U}}, +{AND_C130,{3U,7U,0U}}, +{AND_C130,{4U,7U,0U}}, +{AND_C130,{5U,7U,0U}}, +{AND_C130,{6U,7U,0U}}, +{AND_C130,{7U,7U,0U}}, +{AND_C138,{0U,7U,0U}}, +{AND_C139,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C140,{7U,0U,0U}}, +{EXG_C140,{7U,1U,0U}}, +{EXG_C140,{7U,2U,0U}}, +{EXG_C140,{7U,3U,0U}}, +{EXG_C140,{7U,4U,0U}}, +{EXG_C140,{7U,5U,0U}}, +{EXG_C140,{7U,6U,0U}}, +{EXG_C140,{7U,7U,0U}}, +{EXG_C148,{7U,0U,0U}}, +{EXG_C148,{7U,1U,0U}}, +{EXG_C148,{7U,2U,0U}}, +{EXG_C148,{7U,3U,0U}}, +{EXG_C148,{7U,4U,0U}}, +{EXG_C148,{7U,5U,0U}}, +{EXG_C148,{7U,6U,0U}}, +{EXG_C148,{7U,7U,0U}}, +{AND_C150,{0U,7U,0U}}, +{AND_C150,{1U,7U,0U}}, +{AND_C150,{2U,7U,0U}}, +{AND_C150,{3U,7U,0U}}, +{AND_C150,{4U,7U,0U}}, +{AND_C150,{5U,7U,0U}}, +{AND_C150,{6U,7U,0U}}, +{AND_C150,{7U,7U,0U}}, +{AND_C158,{0U,7U,0U}}, +{AND_C158,{1U,7U,0U}}, +{AND_C158,{2U,7U,0U}}, +{AND_C158,{3U,7U,0U}}, +{AND_C158,{4U,7U,0U}}, +{AND_C158,{5U,7U,0U}}, +{AND_C158,{6U,7U,0U}}, +{AND_C158,{7U,7U,0U}}, +{AND_C160,{0U,7U,0U}}, +{AND_C160,{1U,7U,0U}}, +{AND_C160,{2U,7U,0U}}, +{AND_C160,{3U,7U,0U}}, +{AND_C160,{4U,7U,0U}}, +{AND_C160,{5U,7U,0U}}, +{AND_C160,{6U,7U,0U}}, +{AND_C160,{7U,7U,0U}}, +{AND_C168,{0U,7U,0U}}, +{AND_C168,{1U,7U,0U}}, +{AND_C168,{2U,7U,0U}}, +{AND_C168,{3U,7U,0U}}, +{AND_C168,{4U,7U,0U}}, +{AND_C168,{5U,7U,0U}}, +{AND_C168,{6U,7U,0U}}, +{AND_C168,{7U,7U,0U}}, +{AND_C170,{0U,7U,0U}}, +{AND_C170,{1U,7U,0U}}, +{AND_C170,{2U,7U,0U}}, +{AND_C170,{3U,7U,0U}}, +{AND_C170,{4U,7U,0U}}, +{AND_C170,{5U,7U,0U}}, +{AND_C170,{6U,7U,0U}}, +{AND_C170,{7U,7U,0U}}, +{AND_C178,{0U,7U,0U}}, +{AND_C179,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{EXG_C188,{7U,0U,0U}}, +{EXG_C188,{7U,1U,0U}}, +{EXG_C188,{7U,2U,0U}}, +{EXG_C188,{7U,3U,0U}}, +{EXG_C188,{7U,4U,0U}}, +{EXG_C188,{7U,5U,0U}}, +{EXG_C188,{7U,6U,0U}}, +{EXG_C188,{7U,7U,0U}}, +{AND_C190,{0U,7U,0U}}, +{AND_C190,{1U,7U,0U}}, +{AND_C190,{2U,7U,0U}}, +{AND_C190,{3U,7U,0U}}, +{AND_C190,{4U,7U,0U}}, +{AND_C190,{5U,7U,0U}}, +{AND_C190,{6U,7U,0U}}, +{AND_C190,{7U,7U,0U}}, +{AND_C198,{0U,7U,0U}}, +{AND_C198,{1U,7U,0U}}, +{AND_C198,{2U,7U,0U}}, +{AND_C198,{3U,7U,0U}}, +{AND_C198,{4U,7U,0U}}, +{AND_C198,{5U,7U,0U}}, +{AND_C198,{6U,7U,0U}}, +{AND_C198,{7U,7U,0U}}, +{AND_C1A0,{0U,7U,0U}}, +{AND_C1A0,{1U,7U,0U}}, +{AND_C1A0,{2U,7U,0U}}, +{AND_C1A0,{3U,7U,0U}}, +{AND_C1A0,{4U,7U,0U}}, +{AND_C1A0,{5U,7U,0U}}, +{AND_C1A0,{6U,7U,0U}}, +{AND_C1A0,{7U,7U,0U}}, +{AND_C1A8,{0U,7U,0U}}, +{AND_C1A8,{1U,7U,0U}}, +{AND_C1A8,{2U,7U,0U}}, +{AND_C1A8,{3U,7U,0U}}, +{AND_C1A8,{4U,7U,0U}}, +{AND_C1A8,{5U,7U,0U}}, +{AND_C1A8,{6U,7U,0U}}, +{AND_C1A8,{7U,7U,0U}}, +{AND_C1B0,{0U,7U,0U}}, +{AND_C1B0,{1U,7U,0U}}, +{AND_C1B0,{2U,7U,0U}}, +{AND_C1B0,{3U,7U,0U}}, +{AND_C1B0,{4U,7U,0U}}, +{AND_C1B0,{5U,7U,0U}}, +{AND_C1B0,{6U,7U,0U}}, +{AND_C1B0,{7U,7U,0U}}, +{AND_C1B8,{0U,7U,0U}}, +{AND_C1B9,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1C0,{0U,7U,0U}}, +{MULS_C1C0,{1U,7U,0U}}, +{MULS_C1C0,{2U,7U,0U}}, +{MULS_C1C0,{3U,7U,0U}}, +{MULS_C1C0,{4U,7U,0U}}, +{MULS_C1C0,{5U,7U,0U}}, +{MULS_C1C0,{6U,7U,0U}}, +{MULS_C1C0,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{MULS_C1D0,{0U,7U,0U}}, +{MULS_C1D0,{1U,7U,0U}}, +{MULS_C1D0,{2U,7U,0U}}, +{MULS_C1D0,{3U,7U,0U}}, +{MULS_C1D0,{4U,7U,0U}}, +{MULS_C1D0,{5U,7U,0U}}, +{MULS_C1D0,{6U,7U,0U}}, +{MULS_C1D0,{7U,7U,0U}}, +{MULS_C1D8,{0U,7U,0U}}, +{MULS_C1D8,{1U,7U,0U}}, +{MULS_C1D8,{2U,7U,0U}}, +{MULS_C1D8,{3U,7U,0U}}, +{MULS_C1D8,{4U,7U,0U}}, +{MULS_C1D8,{5U,7U,0U}}, +{MULS_C1D8,{6U,7U,0U}}, +{MULS_C1D8,{7U,7U,0U}}, +{MULS_C1E0,{0U,7U,0U}}, +{MULS_C1E0,{1U,7U,0U}}, +{MULS_C1E0,{2U,7U,0U}}, +{MULS_C1E0,{3U,7U,0U}}, +{MULS_C1E0,{4U,7U,0U}}, +{MULS_C1E0,{5U,7U,0U}}, +{MULS_C1E0,{6U,7U,0U}}, +{MULS_C1E0,{7U,7U,0U}}, +{MULS_C1E8,{0U,7U,0U}}, +{MULS_C1E8,{1U,7U,0U}}, +{MULS_C1E8,{2U,7U,0U}}, +{MULS_C1E8,{3U,7U,0U}}, +{MULS_C1E8,{4U,7U,0U}}, +{MULS_C1E8,{5U,7U,0U}}, +{MULS_C1E8,{6U,7U,0U}}, +{MULS_C1E8,{7U,7U,0U}}, +{MULS_C1F0,{0U,7U,0U}}, +{MULS_C1F0,{1U,7U,0U}}, +{MULS_C1F0,{2U,7U,0U}}, +{MULS_C1F0,{3U,7U,0U}}, +{MULS_C1F0,{4U,7U,0U}}, +{MULS_C1F0,{5U,7U,0U}}, +{MULS_C1F0,{6U,7U,0U}}, +{MULS_C1F0,{7U,7U,0U}}, +{MULS_C1F8,{0U,7U,0U}}, +{MULS_C1F9,{0U,7U,0U}}, +{MULS_C1FA,{0U,7U,0U}}, +{MULS_C1FB,{0U,7U,0U}}, +{MULS_C1FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D000,{0U,0U,0U}}, +{ADD_D000,{1U,0U,0U}}, +{ADD_D000,{2U,0U,0U}}, +{ADD_D000,{3U,0U,0U}}, +{ADD_D000,{4U,0U,0U}}, +{ADD_D000,{5U,0U,0U}}, +{ADD_D000,{6U,0U,0U}}, +{ADD_D000,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D010,{0U,0U,0U}}, +{ADD_D010,{1U,0U,0U}}, +{ADD_D010,{2U,0U,0U}}, +{ADD_D010,{3U,0U,0U}}, +{ADD_D010,{4U,0U,0U}}, +{ADD_D010,{5U,0U,0U}}, +{ADD_D010,{6U,0U,0U}}, +{ADD_D010,{7U,0U,0U}}, +{ADD_D018,{0U,0U,0U}}, +{ADD_D018,{1U,0U,0U}}, +{ADD_D018,{2U,0U,0U}}, +{ADD_D018,{3U,0U,0U}}, +{ADD_D018,{4U,0U,0U}}, +{ADD_D018,{5U,0U,0U}}, +{ADD_D018,{6U,0U,0U}}, +{ADD_D018,{7U,0U,0U}}, +{ADD_D020,{0U,0U,0U}}, +{ADD_D020,{1U,0U,0U}}, +{ADD_D020,{2U,0U,0U}}, +{ADD_D020,{3U,0U,0U}}, +{ADD_D020,{4U,0U,0U}}, +{ADD_D020,{5U,0U,0U}}, +{ADD_D020,{6U,0U,0U}}, +{ADD_D020,{7U,0U,0U}}, +{ADD_D028,{0U,0U,0U}}, +{ADD_D028,{1U,0U,0U}}, +{ADD_D028,{2U,0U,0U}}, +{ADD_D028,{3U,0U,0U}}, +{ADD_D028,{4U,0U,0U}}, +{ADD_D028,{5U,0U,0U}}, +{ADD_D028,{6U,0U,0U}}, +{ADD_D028,{7U,0U,0U}}, +{ADD_D030,{0U,0U,0U}}, +{ADD_D030,{1U,0U,0U}}, +{ADD_D030,{2U,0U,0U}}, +{ADD_D030,{3U,0U,0U}}, +{ADD_D030,{4U,0U,0U}}, +{ADD_D030,{5U,0U,0U}}, +{ADD_D030,{6U,0U,0U}}, +{ADD_D030,{7U,0U,0U}}, +{ADD_D038,{0U,0U,0U}}, +{ADD_D039,{0U,0U,0U}}, +{ADD_D03A,{0U,0U,0U}}, +{ADD_D03B,{0U,0U,0U}}, +{ADD_D03C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D040,{0U,0U,0U}}, +{ADD_D040,{1U,0U,0U}}, +{ADD_D040,{2U,0U,0U}}, +{ADD_D040,{3U,0U,0U}}, +{ADD_D040,{4U,0U,0U}}, +{ADD_D040,{5U,0U,0U}}, +{ADD_D040,{6U,0U,0U}}, +{ADD_D040,{7U,0U,0U}}, +{ADD_D048,{0U,0U,0U}}, +{ADD_D048,{1U,0U,0U}}, +{ADD_D048,{2U,0U,0U}}, +{ADD_D048,{3U,0U,0U}}, +{ADD_D048,{4U,0U,0U}}, +{ADD_D048,{5U,0U,0U}}, +{ADD_D048,{6U,0U,0U}}, +{ADD_D048,{7U,0U,0U}}, +{ADD_D050,{0U,0U,0U}}, +{ADD_D050,{1U,0U,0U}}, +{ADD_D050,{2U,0U,0U}}, +{ADD_D050,{3U,0U,0U}}, +{ADD_D050,{4U,0U,0U}}, +{ADD_D050,{5U,0U,0U}}, +{ADD_D050,{6U,0U,0U}}, +{ADD_D050,{7U,0U,0U}}, +{ADD_D058,{0U,0U,0U}}, +{ADD_D058,{1U,0U,0U}}, +{ADD_D058,{2U,0U,0U}}, +{ADD_D058,{3U,0U,0U}}, +{ADD_D058,{4U,0U,0U}}, +{ADD_D058,{5U,0U,0U}}, +{ADD_D058,{6U,0U,0U}}, +{ADD_D058,{7U,0U,0U}}, +{ADD_D060,{0U,0U,0U}}, +{ADD_D060,{1U,0U,0U}}, +{ADD_D060,{2U,0U,0U}}, +{ADD_D060,{3U,0U,0U}}, +{ADD_D060,{4U,0U,0U}}, +{ADD_D060,{5U,0U,0U}}, +{ADD_D060,{6U,0U,0U}}, +{ADD_D060,{7U,0U,0U}}, +{ADD_D068,{0U,0U,0U}}, +{ADD_D068,{1U,0U,0U}}, +{ADD_D068,{2U,0U,0U}}, +{ADD_D068,{3U,0U,0U}}, +{ADD_D068,{4U,0U,0U}}, +{ADD_D068,{5U,0U,0U}}, +{ADD_D068,{6U,0U,0U}}, +{ADD_D068,{7U,0U,0U}}, +{ADD_D070,{0U,0U,0U}}, +{ADD_D070,{1U,0U,0U}}, +{ADD_D070,{2U,0U,0U}}, +{ADD_D070,{3U,0U,0U}}, +{ADD_D070,{4U,0U,0U}}, +{ADD_D070,{5U,0U,0U}}, +{ADD_D070,{6U,0U,0U}}, +{ADD_D070,{7U,0U,0U}}, +{ADD_D078,{0U,0U,0U}}, +{ADD_D079,{0U,0U,0U}}, +{ADD_D07A,{0U,0U,0U}}, +{ADD_D07B,{0U,0U,0U}}, +{ADD_D07C,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D080,{0U,0U,0U}}, +{ADD_D080,{1U,0U,0U}}, +{ADD_D080,{2U,0U,0U}}, +{ADD_D080,{3U,0U,0U}}, +{ADD_D080,{4U,0U,0U}}, +{ADD_D080,{5U,0U,0U}}, +{ADD_D080,{6U,0U,0U}}, +{ADD_D080,{7U,0U,0U}}, +{ADD_D088,{0U,0U,0U}}, +{ADD_D088,{1U,0U,0U}}, +{ADD_D088,{2U,0U,0U}}, +{ADD_D088,{3U,0U,0U}}, +{ADD_D088,{4U,0U,0U}}, +{ADD_D088,{5U,0U,0U}}, +{ADD_D088,{6U,0U,0U}}, +{ADD_D088,{7U,0U,0U}}, +{ADD_D090,{0U,0U,0U}}, +{ADD_D090,{1U,0U,0U}}, +{ADD_D090,{2U,0U,0U}}, +{ADD_D090,{3U,0U,0U}}, +{ADD_D090,{4U,0U,0U}}, +{ADD_D090,{5U,0U,0U}}, +{ADD_D090,{6U,0U,0U}}, +{ADD_D090,{7U,0U,0U}}, +{ADD_D098,{0U,0U,0U}}, +{ADD_D098,{1U,0U,0U}}, +{ADD_D098,{2U,0U,0U}}, +{ADD_D098,{3U,0U,0U}}, +{ADD_D098,{4U,0U,0U}}, +{ADD_D098,{5U,0U,0U}}, +{ADD_D098,{6U,0U,0U}}, +{ADD_D098,{7U,0U,0U}}, +{ADD_D0A0,{0U,0U,0U}}, +{ADD_D0A0,{1U,0U,0U}}, +{ADD_D0A0,{2U,0U,0U}}, +{ADD_D0A0,{3U,0U,0U}}, +{ADD_D0A0,{4U,0U,0U}}, +{ADD_D0A0,{5U,0U,0U}}, +{ADD_D0A0,{6U,0U,0U}}, +{ADD_D0A0,{7U,0U,0U}}, +{ADD_D0A8,{0U,0U,0U}}, +{ADD_D0A8,{1U,0U,0U}}, +{ADD_D0A8,{2U,0U,0U}}, +{ADD_D0A8,{3U,0U,0U}}, +{ADD_D0A8,{4U,0U,0U}}, +{ADD_D0A8,{5U,0U,0U}}, +{ADD_D0A8,{6U,0U,0U}}, +{ADD_D0A8,{7U,0U,0U}}, +{ADD_D0B0,{0U,0U,0U}}, +{ADD_D0B0,{1U,0U,0U}}, +{ADD_D0B0,{2U,0U,0U}}, +{ADD_D0B0,{3U,0U,0U}}, +{ADD_D0B0,{4U,0U,0U}}, +{ADD_D0B0,{5U,0U,0U}}, +{ADD_D0B0,{6U,0U,0U}}, +{ADD_D0B0,{7U,0U,0U}}, +{ADD_D0B8,{0U,0U,0U}}, +{ADD_D0B9,{0U,0U,0U}}, +{ADD_D0BA,{0U,0U,0U}}, +{ADD_D0BB,{0U,0U,0U}}, +{ADD_D0BC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D0C0,{0U,0U,0U}}, +{ADDA_D0C0,{1U,0U,0U}}, +{ADDA_D0C0,{2U,0U,0U}}, +{ADDA_D0C0,{3U,0U,0U}}, +{ADDA_D0C0,{4U,0U,0U}}, +{ADDA_D0C0,{5U,0U,0U}}, +{ADDA_D0C0,{6U,0U,0U}}, +{ADDA_D0C0,{7U,0U,0U}}, +{ADDA_D0C8,{0U,0U,0U}}, +{ADDA_D0C8,{1U,0U,0U}}, +{ADDA_D0C8,{2U,0U,0U}}, +{ADDA_D0C8,{3U,0U,0U}}, +{ADDA_D0C8,{4U,0U,0U}}, +{ADDA_D0C8,{5U,0U,0U}}, +{ADDA_D0C8,{6U,0U,0U}}, +{ADDA_D0C8,{7U,0U,0U}}, +{ADDA_D0D0,{0U,0U,0U}}, +{ADDA_D0D0,{1U,0U,0U}}, +{ADDA_D0D0,{2U,0U,0U}}, +{ADDA_D0D0,{3U,0U,0U}}, +{ADDA_D0D0,{4U,0U,0U}}, +{ADDA_D0D0,{5U,0U,0U}}, +{ADDA_D0D0,{6U,0U,0U}}, +{ADDA_D0D0,{7U,0U,0U}}, +{ADDA_D0D8,{0U,0U,0U}}, +{ADDA_D0D8,{1U,0U,0U}}, +{ADDA_D0D8,{2U,0U,0U}}, +{ADDA_D0D8,{3U,0U,0U}}, +{ADDA_D0D8,{4U,0U,0U}}, +{ADDA_D0D8,{5U,0U,0U}}, +{ADDA_D0D8,{6U,0U,0U}}, +{ADDA_D0D8,{7U,0U,0U}}, +{ADDA_D0E0,{0U,0U,0U}}, +{ADDA_D0E0,{1U,0U,0U}}, +{ADDA_D0E0,{2U,0U,0U}}, +{ADDA_D0E0,{3U,0U,0U}}, +{ADDA_D0E0,{4U,0U,0U}}, +{ADDA_D0E0,{5U,0U,0U}}, +{ADDA_D0E0,{6U,0U,0U}}, +{ADDA_D0E0,{7U,0U,0U}}, +{ADDA_D0E8,{0U,0U,0U}}, +{ADDA_D0E8,{1U,0U,0U}}, +{ADDA_D0E8,{2U,0U,0U}}, +{ADDA_D0E8,{3U,0U,0U}}, +{ADDA_D0E8,{4U,0U,0U}}, +{ADDA_D0E8,{5U,0U,0U}}, +{ADDA_D0E8,{6U,0U,0U}}, +{ADDA_D0E8,{7U,0U,0U}}, +{ADDA_D0F0,{0U,0U,0U}}, +{ADDA_D0F0,{1U,0U,0U}}, +{ADDA_D0F0,{2U,0U,0U}}, +{ADDA_D0F0,{3U,0U,0U}}, +{ADDA_D0F0,{4U,0U,0U}}, +{ADDA_D0F0,{5U,0U,0U}}, +{ADDA_D0F0,{6U,0U,0U}}, +{ADDA_D0F0,{7U,0U,0U}}, +{ADDA_D0F8,{0U,0U,0U}}, +{ADDA_D0F9,{0U,0U,0U}}, +{ADDA_D0FA,{0U,0U,0U}}, +{ADDA_D0FB,{0U,0U,0U}}, +{ADDA_D0FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D100,{0U,0U,0U}}, +{ADDX_D100,{1U,0U,0U}}, +{ADDX_D100,{2U,0U,0U}}, +{ADDX_D100,{3U,0U,0U}}, +{ADDX_D100,{4U,0U,0U}}, +{ADDX_D100,{5U,0U,0U}}, +{ADDX_D100,{6U,0U,0U}}, +{ADDX_D100,{7U,0U,0U}}, +{ADDX_D108,{0U,0U,0U}}, +{ADDX_D108,{1U,0U,0U}}, +{ADDX_D108,{2U,0U,0U}}, +{ADDX_D108,{3U,0U,0U}}, +{ADDX_D108,{4U,0U,0U}}, +{ADDX_D108,{5U,0U,0U}}, +{ADDX_D108,{6U,0U,0U}}, +{ADDX_D108,{7U,0U,0U}}, +{ADD_D110,{0U,0U,0U}}, +{ADD_D110,{1U,0U,0U}}, +{ADD_D110,{2U,0U,0U}}, +{ADD_D110,{3U,0U,0U}}, +{ADD_D110,{4U,0U,0U}}, +{ADD_D110,{5U,0U,0U}}, +{ADD_D110,{6U,0U,0U}}, +{ADD_D110,{7U,0U,0U}}, +{ADD_D118,{0U,0U,0U}}, +{ADD_D118,{1U,0U,0U}}, +{ADD_D118,{2U,0U,0U}}, +{ADD_D118,{3U,0U,0U}}, +{ADD_D118,{4U,0U,0U}}, +{ADD_D118,{5U,0U,0U}}, +{ADD_D118,{6U,0U,0U}}, +{ADD_D118,{7U,0U,0U}}, +{ADD_D120,{0U,0U,0U}}, +{ADD_D120,{1U,0U,0U}}, +{ADD_D120,{2U,0U,0U}}, +{ADD_D120,{3U,0U,0U}}, +{ADD_D120,{4U,0U,0U}}, +{ADD_D120,{5U,0U,0U}}, +{ADD_D120,{6U,0U,0U}}, +{ADD_D120,{7U,0U,0U}}, +{ADD_D128,{0U,0U,0U}}, +{ADD_D128,{1U,0U,0U}}, +{ADD_D128,{2U,0U,0U}}, +{ADD_D128,{3U,0U,0U}}, +{ADD_D128,{4U,0U,0U}}, +{ADD_D128,{5U,0U,0U}}, +{ADD_D128,{6U,0U,0U}}, +{ADD_D128,{7U,0U,0U}}, +{ADD_D130,{0U,0U,0U}}, +{ADD_D130,{1U,0U,0U}}, +{ADD_D130,{2U,0U,0U}}, +{ADD_D130,{3U,0U,0U}}, +{ADD_D130,{4U,0U,0U}}, +{ADD_D130,{5U,0U,0U}}, +{ADD_D130,{6U,0U,0U}}, +{ADD_D130,{7U,0U,0U}}, +{ADD_D138,{0U,0U,0U}}, +{ADD_D139,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D140,{0U,0U,0U}}, +{ADDX_D140,{1U,0U,0U}}, +{ADDX_D140,{2U,0U,0U}}, +{ADDX_D140,{3U,0U,0U}}, +{ADDX_D140,{4U,0U,0U}}, +{ADDX_D140,{5U,0U,0U}}, +{ADDX_D140,{6U,0U,0U}}, +{ADDX_D140,{7U,0U,0U}}, +{ADDX_D148,{0U,0U,0U}}, +{ADDX_D148,{1U,0U,0U}}, +{ADDX_D148,{2U,0U,0U}}, +{ADDX_D148,{3U,0U,0U}}, +{ADDX_D148,{4U,0U,0U}}, +{ADDX_D148,{5U,0U,0U}}, +{ADDX_D148,{6U,0U,0U}}, +{ADDX_D148,{7U,0U,0U}}, +{ADD_D150,{0U,0U,0U}}, +{ADD_D150,{1U,0U,0U}}, +{ADD_D150,{2U,0U,0U}}, +{ADD_D150,{3U,0U,0U}}, +{ADD_D150,{4U,0U,0U}}, +{ADD_D150,{5U,0U,0U}}, +{ADD_D150,{6U,0U,0U}}, +{ADD_D150,{7U,0U,0U}}, +{ADD_D158,{0U,0U,0U}}, +{ADD_D158,{1U,0U,0U}}, +{ADD_D158,{2U,0U,0U}}, +{ADD_D158,{3U,0U,0U}}, +{ADD_D158,{4U,0U,0U}}, +{ADD_D158,{5U,0U,0U}}, +{ADD_D158,{6U,0U,0U}}, +{ADD_D158,{7U,0U,0U}}, +{ADD_D160,{0U,0U,0U}}, +{ADD_D160,{1U,0U,0U}}, +{ADD_D160,{2U,0U,0U}}, +{ADD_D160,{3U,0U,0U}}, +{ADD_D160,{4U,0U,0U}}, +{ADD_D160,{5U,0U,0U}}, +{ADD_D160,{6U,0U,0U}}, +{ADD_D160,{7U,0U,0U}}, +{ADD_D168,{0U,0U,0U}}, +{ADD_D168,{1U,0U,0U}}, +{ADD_D168,{2U,0U,0U}}, +{ADD_D168,{3U,0U,0U}}, +{ADD_D168,{4U,0U,0U}}, +{ADD_D168,{5U,0U,0U}}, +{ADD_D168,{6U,0U,0U}}, +{ADD_D168,{7U,0U,0U}}, +{ADD_D170,{0U,0U,0U}}, +{ADD_D170,{1U,0U,0U}}, +{ADD_D170,{2U,0U,0U}}, +{ADD_D170,{3U,0U,0U}}, +{ADD_D170,{4U,0U,0U}}, +{ADD_D170,{5U,0U,0U}}, +{ADD_D170,{6U,0U,0U}}, +{ADD_D170,{7U,0U,0U}}, +{ADD_D178,{0U,0U,0U}}, +{ADD_D179,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D180,{0U,0U,0U}}, +{ADDX_D180,{1U,0U,0U}}, +{ADDX_D180,{2U,0U,0U}}, +{ADDX_D180,{3U,0U,0U}}, +{ADDX_D180,{4U,0U,0U}}, +{ADDX_D180,{5U,0U,0U}}, +{ADDX_D180,{6U,0U,0U}}, +{ADDX_D180,{7U,0U,0U}}, +{ADDX_D188,{0U,0U,0U}}, +{ADDX_D188,{1U,0U,0U}}, +{ADDX_D188,{2U,0U,0U}}, +{ADDX_D188,{3U,0U,0U}}, +{ADDX_D188,{4U,0U,0U}}, +{ADDX_D188,{5U,0U,0U}}, +{ADDX_D188,{6U,0U,0U}}, +{ADDX_D188,{7U,0U,0U}}, +{ADD_D190,{0U,0U,0U}}, +{ADD_D190,{1U,0U,0U}}, +{ADD_D190,{2U,0U,0U}}, +{ADD_D190,{3U,0U,0U}}, +{ADD_D190,{4U,0U,0U}}, +{ADD_D190,{5U,0U,0U}}, +{ADD_D190,{6U,0U,0U}}, +{ADD_D190,{7U,0U,0U}}, +{ADD_D198,{0U,0U,0U}}, +{ADD_D198,{1U,0U,0U}}, +{ADD_D198,{2U,0U,0U}}, +{ADD_D198,{3U,0U,0U}}, +{ADD_D198,{4U,0U,0U}}, +{ADD_D198,{5U,0U,0U}}, +{ADD_D198,{6U,0U,0U}}, +{ADD_D198,{7U,0U,0U}}, +{ADD_D1A0,{0U,0U,0U}}, +{ADD_D1A0,{1U,0U,0U}}, +{ADD_D1A0,{2U,0U,0U}}, +{ADD_D1A0,{3U,0U,0U}}, +{ADD_D1A0,{4U,0U,0U}}, +{ADD_D1A0,{5U,0U,0U}}, +{ADD_D1A0,{6U,0U,0U}}, +{ADD_D1A0,{7U,0U,0U}}, +{ADD_D1A8,{0U,0U,0U}}, +{ADD_D1A8,{1U,0U,0U}}, +{ADD_D1A8,{2U,0U,0U}}, +{ADD_D1A8,{3U,0U,0U}}, +{ADD_D1A8,{4U,0U,0U}}, +{ADD_D1A8,{5U,0U,0U}}, +{ADD_D1A8,{6U,0U,0U}}, +{ADD_D1A8,{7U,0U,0U}}, +{ADD_D1B0,{0U,0U,0U}}, +{ADD_D1B0,{1U,0U,0U}}, +{ADD_D1B0,{2U,0U,0U}}, +{ADD_D1B0,{3U,0U,0U}}, +{ADD_D1B0,{4U,0U,0U}}, +{ADD_D1B0,{5U,0U,0U}}, +{ADD_D1B0,{6U,0U,0U}}, +{ADD_D1B0,{7U,0U,0U}}, +{ADD_D1B8,{0U,0U,0U}}, +{ADD_D1B9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D1C0,{0U,0U,0U}}, +{ADDA_D1C0,{1U,0U,0U}}, +{ADDA_D1C0,{2U,0U,0U}}, +{ADDA_D1C0,{3U,0U,0U}}, +{ADDA_D1C0,{4U,0U,0U}}, +{ADDA_D1C0,{5U,0U,0U}}, +{ADDA_D1C0,{6U,0U,0U}}, +{ADDA_D1C0,{7U,0U,0U}}, +{ADDA_D1C8,{0U,0U,0U}}, +{ADDA_D1C8,{1U,0U,0U}}, +{ADDA_D1C8,{2U,0U,0U}}, +{ADDA_D1C8,{3U,0U,0U}}, +{ADDA_D1C8,{4U,0U,0U}}, +{ADDA_D1C8,{5U,0U,0U}}, +{ADDA_D1C8,{6U,0U,0U}}, +{ADDA_D1C8,{7U,0U,0U}}, +{ADDA_D1D0,{0U,0U,0U}}, +{ADDA_D1D0,{1U,0U,0U}}, +{ADDA_D1D0,{2U,0U,0U}}, +{ADDA_D1D0,{3U,0U,0U}}, +{ADDA_D1D0,{4U,0U,0U}}, +{ADDA_D1D0,{5U,0U,0U}}, +{ADDA_D1D0,{6U,0U,0U}}, +{ADDA_D1D0,{7U,0U,0U}}, +{ADDA_D1D8,{0U,0U,0U}}, +{ADDA_D1D8,{1U,0U,0U}}, +{ADDA_D1D8,{2U,0U,0U}}, +{ADDA_D1D8,{3U,0U,0U}}, +{ADDA_D1D8,{4U,0U,0U}}, +{ADDA_D1D8,{5U,0U,0U}}, +{ADDA_D1D8,{6U,0U,0U}}, +{ADDA_D1D8,{7U,0U,0U}}, +{ADDA_D1E0,{0U,0U,0U}}, +{ADDA_D1E0,{1U,0U,0U}}, +{ADDA_D1E0,{2U,0U,0U}}, +{ADDA_D1E0,{3U,0U,0U}}, +{ADDA_D1E0,{4U,0U,0U}}, +{ADDA_D1E0,{5U,0U,0U}}, +{ADDA_D1E0,{6U,0U,0U}}, +{ADDA_D1E0,{7U,0U,0U}}, +{ADDA_D1E8,{0U,0U,0U}}, +{ADDA_D1E8,{1U,0U,0U}}, +{ADDA_D1E8,{2U,0U,0U}}, +{ADDA_D1E8,{3U,0U,0U}}, +{ADDA_D1E8,{4U,0U,0U}}, +{ADDA_D1E8,{5U,0U,0U}}, +{ADDA_D1E8,{6U,0U,0U}}, +{ADDA_D1E8,{7U,0U,0U}}, +{ADDA_D1F0,{0U,0U,0U}}, +{ADDA_D1F0,{1U,0U,0U}}, +{ADDA_D1F0,{2U,0U,0U}}, +{ADDA_D1F0,{3U,0U,0U}}, +{ADDA_D1F0,{4U,0U,0U}}, +{ADDA_D1F0,{5U,0U,0U}}, +{ADDA_D1F0,{6U,0U,0U}}, +{ADDA_D1F0,{7U,0U,0U}}, +{ADDA_D1F8,{0U,0U,0U}}, +{ADDA_D1F9,{0U,0U,0U}}, +{ADDA_D1FA,{0U,0U,0U}}, +{ADDA_D1FB,{0U,0U,0U}}, +{ADDA_D1FC,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D000,{0U,1U,0U}}, +{ADD_D000,{1U,1U,0U}}, +{ADD_D000,{2U,1U,0U}}, +{ADD_D000,{3U,1U,0U}}, +{ADD_D000,{4U,1U,0U}}, +{ADD_D000,{5U,1U,0U}}, +{ADD_D000,{6U,1U,0U}}, +{ADD_D000,{7U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D010,{0U,1U,0U}}, +{ADD_D010,{1U,1U,0U}}, +{ADD_D010,{2U,1U,0U}}, +{ADD_D010,{3U,1U,0U}}, +{ADD_D010,{4U,1U,0U}}, +{ADD_D010,{5U,1U,0U}}, +{ADD_D010,{6U,1U,0U}}, +{ADD_D010,{7U,1U,0U}}, +{ADD_D018,{0U,1U,0U}}, +{ADD_D018,{1U,1U,0U}}, +{ADD_D018,{2U,1U,0U}}, +{ADD_D018,{3U,1U,0U}}, +{ADD_D018,{4U,1U,0U}}, +{ADD_D018,{5U,1U,0U}}, +{ADD_D018,{6U,1U,0U}}, +{ADD_D018,{7U,1U,0U}}, +{ADD_D020,{0U,1U,0U}}, +{ADD_D020,{1U,1U,0U}}, +{ADD_D020,{2U,1U,0U}}, +{ADD_D020,{3U,1U,0U}}, +{ADD_D020,{4U,1U,0U}}, +{ADD_D020,{5U,1U,0U}}, +{ADD_D020,{6U,1U,0U}}, +{ADD_D020,{7U,1U,0U}}, +{ADD_D028,{0U,1U,0U}}, +{ADD_D028,{1U,1U,0U}}, +{ADD_D028,{2U,1U,0U}}, +{ADD_D028,{3U,1U,0U}}, +{ADD_D028,{4U,1U,0U}}, +{ADD_D028,{5U,1U,0U}}, +{ADD_D028,{6U,1U,0U}}, +{ADD_D028,{7U,1U,0U}}, +{ADD_D030,{0U,1U,0U}}, +{ADD_D030,{1U,1U,0U}}, +{ADD_D030,{2U,1U,0U}}, +{ADD_D030,{3U,1U,0U}}, +{ADD_D030,{4U,1U,0U}}, +{ADD_D030,{5U,1U,0U}}, +{ADD_D030,{6U,1U,0U}}, +{ADD_D030,{7U,1U,0U}}, +{ADD_D038,{0U,1U,0U}}, +{ADD_D039,{0U,1U,0U}}, +{ADD_D03A,{0U,1U,0U}}, +{ADD_D03B,{0U,1U,0U}}, +{ADD_D03C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D040,{0U,1U,0U}}, +{ADD_D040,{1U,1U,0U}}, +{ADD_D040,{2U,1U,0U}}, +{ADD_D040,{3U,1U,0U}}, +{ADD_D040,{4U,1U,0U}}, +{ADD_D040,{5U,1U,0U}}, +{ADD_D040,{6U,1U,0U}}, +{ADD_D040,{7U,1U,0U}}, +{ADD_D048,{0U,1U,0U}}, +{ADD_D048,{1U,1U,0U}}, +{ADD_D048,{2U,1U,0U}}, +{ADD_D048,{3U,1U,0U}}, +{ADD_D048,{4U,1U,0U}}, +{ADD_D048,{5U,1U,0U}}, +{ADD_D048,{6U,1U,0U}}, +{ADD_D048,{7U,1U,0U}}, +{ADD_D050,{0U,1U,0U}}, +{ADD_D050,{1U,1U,0U}}, +{ADD_D050,{2U,1U,0U}}, +{ADD_D050,{3U,1U,0U}}, +{ADD_D050,{4U,1U,0U}}, +{ADD_D050,{5U,1U,0U}}, +{ADD_D050,{6U,1U,0U}}, +{ADD_D050,{7U,1U,0U}}, +{ADD_D058,{0U,1U,0U}}, +{ADD_D058,{1U,1U,0U}}, +{ADD_D058,{2U,1U,0U}}, +{ADD_D058,{3U,1U,0U}}, +{ADD_D058,{4U,1U,0U}}, +{ADD_D058,{5U,1U,0U}}, +{ADD_D058,{6U,1U,0U}}, +{ADD_D058,{7U,1U,0U}}, +{ADD_D060,{0U,1U,0U}}, +{ADD_D060,{1U,1U,0U}}, +{ADD_D060,{2U,1U,0U}}, +{ADD_D060,{3U,1U,0U}}, +{ADD_D060,{4U,1U,0U}}, +{ADD_D060,{5U,1U,0U}}, +{ADD_D060,{6U,1U,0U}}, +{ADD_D060,{7U,1U,0U}}, +{ADD_D068,{0U,1U,0U}}, +{ADD_D068,{1U,1U,0U}}, +{ADD_D068,{2U,1U,0U}}, +{ADD_D068,{3U,1U,0U}}, +{ADD_D068,{4U,1U,0U}}, +{ADD_D068,{5U,1U,0U}}, +{ADD_D068,{6U,1U,0U}}, +{ADD_D068,{7U,1U,0U}}, +{ADD_D070,{0U,1U,0U}}, +{ADD_D070,{1U,1U,0U}}, +{ADD_D070,{2U,1U,0U}}, +{ADD_D070,{3U,1U,0U}}, +{ADD_D070,{4U,1U,0U}}, +{ADD_D070,{5U,1U,0U}}, +{ADD_D070,{6U,1U,0U}}, +{ADD_D070,{7U,1U,0U}}, +{ADD_D078,{0U,1U,0U}}, +{ADD_D079,{0U,1U,0U}}, +{ADD_D07A,{0U,1U,0U}}, +{ADD_D07B,{0U,1U,0U}}, +{ADD_D07C,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D080,{0U,1U,0U}}, +{ADD_D080,{1U,1U,0U}}, +{ADD_D080,{2U,1U,0U}}, +{ADD_D080,{3U,1U,0U}}, +{ADD_D080,{4U,1U,0U}}, +{ADD_D080,{5U,1U,0U}}, +{ADD_D080,{6U,1U,0U}}, +{ADD_D080,{7U,1U,0U}}, +{ADD_D088,{0U,1U,0U}}, +{ADD_D088,{1U,1U,0U}}, +{ADD_D088,{2U,1U,0U}}, +{ADD_D088,{3U,1U,0U}}, +{ADD_D088,{4U,1U,0U}}, +{ADD_D088,{5U,1U,0U}}, +{ADD_D088,{6U,1U,0U}}, +{ADD_D088,{7U,1U,0U}}, +{ADD_D090,{0U,1U,0U}}, +{ADD_D090,{1U,1U,0U}}, +{ADD_D090,{2U,1U,0U}}, +{ADD_D090,{3U,1U,0U}}, +{ADD_D090,{4U,1U,0U}}, +{ADD_D090,{5U,1U,0U}}, +{ADD_D090,{6U,1U,0U}}, +{ADD_D090,{7U,1U,0U}}, +{ADD_D098,{0U,1U,0U}}, +{ADD_D098,{1U,1U,0U}}, +{ADD_D098,{2U,1U,0U}}, +{ADD_D098,{3U,1U,0U}}, +{ADD_D098,{4U,1U,0U}}, +{ADD_D098,{5U,1U,0U}}, +{ADD_D098,{6U,1U,0U}}, +{ADD_D098,{7U,1U,0U}}, +{ADD_D0A0,{0U,1U,0U}}, +{ADD_D0A0,{1U,1U,0U}}, +{ADD_D0A0,{2U,1U,0U}}, +{ADD_D0A0,{3U,1U,0U}}, +{ADD_D0A0,{4U,1U,0U}}, +{ADD_D0A0,{5U,1U,0U}}, +{ADD_D0A0,{6U,1U,0U}}, +{ADD_D0A0,{7U,1U,0U}}, +{ADD_D0A8,{0U,1U,0U}}, +{ADD_D0A8,{1U,1U,0U}}, +{ADD_D0A8,{2U,1U,0U}}, +{ADD_D0A8,{3U,1U,0U}}, +{ADD_D0A8,{4U,1U,0U}}, +{ADD_D0A8,{5U,1U,0U}}, +{ADD_D0A8,{6U,1U,0U}}, +{ADD_D0A8,{7U,1U,0U}}, +{ADD_D0B0,{0U,1U,0U}}, +{ADD_D0B0,{1U,1U,0U}}, +{ADD_D0B0,{2U,1U,0U}}, +{ADD_D0B0,{3U,1U,0U}}, +{ADD_D0B0,{4U,1U,0U}}, +{ADD_D0B0,{5U,1U,0U}}, +{ADD_D0B0,{6U,1U,0U}}, +{ADD_D0B0,{7U,1U,0U}}, +{ADD_D0B8,{0U,1U,0U}}, +{ADD_D0B9,{0U,1U,0U}}, +{ADD_D0BA,{0U,1U,0U}}, +{ADD_D0BB,{0U,1U,0U}}, +{ADD_D0BC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D0C0,{0U,1U,0U}}, +{ADDA_D0C0,{1U,1U,0U}}, +{ADDA_D0C0,{2U,1U,0U}}, +{ADDA_D0C0,{3U,1U,0U}}, +{ADDA_D0C0,{4U,1U,0U}}, +{ADDA_D0C0,{5U,1U,0U}}, +{ADDA_D0C0,{6U,1U,0U}}, +{ADDA_D0C0,{7U,1U,0U}}, +{ADDA_D0C8,{0U,1U,0U}}, +{ADDA_D0C8,{1U,1U,0U}}, +{ADDA_D0C8,{2U,1U,0U}}, +{ADDA_D0C8,{3U,1U,0U}}, +{ADDA_D0C8,{4U,1U,0U}}, +{ADDA_D0C8,{5U,1U,0U}}, +{ADDA_D0C8,{6U,1U,0U}}, +{ADDA_D0C8,{7U,1U,0U}}, +{ADDA_D0D0,{0U,1U,0U}}, +{ADDA_D0D0,{1U,1U,0U}}, +{ADDA_D0D0,{2U,1U,0U}}, +{ADDA_D0D0,{3U,1U,0U}}, +{ADDA_D0D0,{4U,1U,0U}}, +{ADDA_D0D0,{5U,1U,0U}}, +{ADDA_D0D0,{6U,1U,0U}}, +{ADDA_D0D0,{7U,1U,0U}}, +{ADDA_D0D8,{0U,1U,0U}}, +{ADDA_D0D8,{1U,1U,0U}}, +{ADDA_D0D8,{2U,1U,0U}}, +{ADDA_D0D8,{3U,1U,0U}}, +{ADDA_D0D8,{4U,1U,0U}}, +{ADDA_D0D8,{5U,1U,0U}}, +{ADDA_D0D8,{6U,1U,0U}}, +{ADDA_D0D8,{7U,1U,0U}}, +{ADDA_D0E0,{0U,1U,0U}}, +{ADDA_D0E0,{1U,1U,0U}}, +{ADDA_D0E0,{2U,1U,0U}}, +{ADDA_D0E0,{3U,1U,0U}}, +{ADDA_D0E0,{4U,1U,0U}}, +{ADDA_D0E0,{5U,1U,0U}}, +{ADDA_D0E0,{6U,1U,0U}}, +{ADDA_D0E0,{7U,1U,0U}}, +{ADDA_D0E8,{0U,1U,0U}}, +{ADDA_D0E8,{1U,1U,0U}}, +{ADDA_D0E8,{2U,1U,0U}}, +{ADDA_D0E8,{3U,1U,0U}}, +{ADDA_D0E8,{4U,1U,0U}}, +{ADDA_D0E8,{5U,1U,0U}}, +{ADDA_D0E8,{6U,1U,0U}}, +{ADDA_D0E8,{7U,1U,0U}}, +{ADDA_D0F0,{0U,1U,0U}}, +{ADDA_D0F0,{1U,1U,0U}}, +{ADDA_D0F0,{2U,1U,0U}}, +{ADDA_D0F0,{3U,1U,0U}}, +{ADDA_D0F0,{4U,1U,0U}}, +{ADDA_D0F0,{5U,1U,0U}}, +{ADDA_D0F0,{6U,1U,0U}}, +{ADDA_D0F0,{7U,1U,0U}}, +{ADDA_D0F8,{0U,1U,0U}}, +{ADDA_D0F9,{0U,1U,0U}}, +{ADDA_D0FA,{0U,1U,0U}}, +{ADDA_D0FB,{0U,1U,0U}}, +{ADDA_D0FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D100,{0U,1U,0U}}, +{ADDX_D100,{1U,1U,0U}}, +{ADDX_D100,{2U,1U,0U}}, +{ADDX_D100,{3U,1U,0U}}, +{ADDX_D100,{4U,1U,0U}}, +{ADDX_D100,{5U,1U,0U}}, +{ADDX_D100,{6U,1U,0U}}, +{ADDX_D100,{7U,1U,0U}}, +{ADDX_D108,{0U,1U,0U}}, +{ADDX_D108,{1U,1U,0U}}, +{ADDX_D108,{2U,1U,0U}}, +{ADDX_D108,{3U,1U,0U}}, +{ADDX_D108,{4U,1U,0U}}, +{ADDX_D108,{5U,1U,0U}}, +{ADDX_D108,{6U,1U,0U}}, +{ADDX_D108,{7U,1U,0U}}, +{ADD_D110,{0U,1U,0U}}, +{ADD_D110,{1U,1U,0U}}, +{ADD_D110,{2U,1U,0U}}, +{ADD_D110,{3U,1U,0U}}, +{ADD_D110,{4U,1U,0U}}, +{ADD_D110,{5U,1U,0U}}, +{ADD_D110,{6U,1U,0U}}, +{ADD_D110,{7U,1U,0U}}, +{ADD_D118,{0U,1U,0U}}, +{ADD_D118,{1U,1U,0U}}, +{ADD_D118,{2U,1U,0U}}, +{ADD_D118,{3U,1U,0U}}, +{ADD_D118,{4U,1U,0U}}, +{ADD_D118,{5U,1U,0U}}, +{ADD_D118,{6U,1U,0U}}, +{ADD_D118,{7U,1U,0U}}, +{ADD_D120,{0U,1U,0U}}, +{ADD_D120,{1U,1U,0U}}, +{ADD_D120,{2U,1U,0U}}, +{ADD_D120,{3U,1U,0U}}, +{ADD_D120,{4U,1U,0U}}, +{ADD_D120,{5U,1U,0U}}, +{ADD_D120,{6U,1U,0U}}, +{ADD_D120,{7U,1U,0U}}, +{ADD_D128,{0U,1U,0U}}, +{ADD_D128,{1U,1U,0U}}, +{ADD_D128,{2U,1U,0U}}, +{ADD_D128,{3U,1U,0U}}, +{ADD_D128,{4U,1U,0U}}, +{ADD_D128,{5U,1U,0U}}, +{ADD_D128,{6U,1U,0U}}, +{ADD_D128,{7U,1U,0U}}, +{ADD_D130,{0U,1U,0U}}, +{ADD_D130,{1U,1U,0U}}, +{ADD_D130,{2U,1U,0U}}, +{ADD_D130,{3U,1U,0U}}, +{ADD_D130,{4U,1U,0U}}, +{ADD_D130,{5U,1U,0U}}, +{ADD_D130,{6U,1U,0U}}, +{ADD_D130,{7U,1U,0U}}, +{ADD_D138,{0U,1U,0U}}, +{ADD_D139,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D140,{0U,1U,0U}}, +{ADDX_D140,{1U,1U,0U}}, +{ADDX_D140,{2U,1U,0U}}, +{ADDX_D140,{3U,1U,0U}}, +{ADDX_D140,{4U,1U,0U}}, +{ADDX_D140,{5U,1U,0U}}, +{ADDX_D140,{6U,1U,0U}}, +{ADDX_D140,{7U,1U,0U}}, +{ADDX_D148,{0U,1U,0U}}, +{ADDX_D148,{1U,1U,0U}}, +{ADDX_D148,{2U,1U,0U}}, +{ADDX_D148,{3U,1U,0U}}, +{ADDX_D148,{4U,1U,0U}}, +{ADDX_D148,{5U,1U,0U}}, +{ADDX_D148,{6U,1U,0U}}, +{ADDX_D148,{7U,1U,0U}}, +{ADD_D150,{0U,1U,0U}}, +{ADD_D150,{1U,1U,0U}}, +{ADD_D150,{2U,1U,0U}}, +{ADD_D150,{3U,1U,0U}}, +{ADD_D150,{4U,1U,0U}}, +{ADD_D150,{5U,1U,0U}}, +{ADD_D150,{6U,1U,0U}}, +{ADD_D150,{7U,1U,0U}}, +{ADD_D158,{0U,1U,0U}}, +{ADD_D158,{1U,1U,0U}}, +{ADD_D158,{2U,1U,0U}}, +{ADD_D158,{3U,1U,0U}}, +{ADD_D158,{4U,1U,0U}}, +{ADD_D158,{5U,1U,0U}}, +{ADD_D158,{6U,1U,0U}}, +{ADD_D158,{7U,1U,0U}}, +{ADD_D160,{0U,1U,0U}}, +{ADD_D160,{1U,1U,0U}}, +{ADD_D160,{2U,1U,0U}}, +{ADD_D160,{3U,1U,0U}}, +{ADD_D160,{4U,1U,0U}}, +{ADD_D160,{5U,1U,0U}}, +{ADD_D160,{6U,1U,0U}}, +{ADD_D160,{7U,1U,0U}}, +{ADD_D168,{0U,1U,0U}}, +{ADD_D168,{1U,1U,0U}}, +{ADD_D168,{2U,1U,0U}}, +{ADD_D168,{3U,1U,0U}}, +{ADD_D168,{4U,1U,0U}}, +{ADD_D168,{5U,1U,0U}}, +{ADD_D168,{6U,1U,0U}}, +{ADD_D168,{7U,1U,0U}}, +{ADD_D170,{0U,1U,0U}}, +{ADD_D170,{1U,1U,0U}}, +{ADD_D170,{2U,1U,0U}}, +{ADD_D170,{3U,1U,0U}}, +{ADD_D170,{4U,1U,0U}}, +{ADD_D170,{5U,1U,0U}}, +{ADD_D170,{6U,1U,0U}}, +{ADD_D170,{7U,1U,0U}}, +{ADD_D178,{0U,1U,0U}}, +{ADD_D179,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D180,{0U,1U,0U}}, +{ADDX_D180,{1U,1U,0U}}, +{ADDX_D180,{2U,1U,0U}}, +{ADDX_D180,{3U,1U,0U}}, +{ADDX_D180,{4U,1U,0U}}, +{ADDX_D180,{5U,1U,0U}}, +{ADDX_D180,{6U,1U,0U}}, +{ADDX_D180,{7U,1U,0U}}, +{ADDX_D188,{0U,1U,0U}}, +{ADDX_D188,{1U,1U,0U}}, +{ADDX_D188,{2U,1U,0U}}, +{ADDX_D188,{3U,1U,0U}}, +{ADDX_D188,{4U,1U,0U}}, +{ADDX_D188,{5U,1U,0U}}, +{ADDX_D188,{6U,1U,0U}}, +{ADDX_D188,{7U,1U,0U}}, +{ADD_D190,{0U,1U,0U}}, +{ADD_D190,{1U,1U,0U}}, +{ADD_D190,{2U,1U,0U}}, +{ADD_D190,{3U,1U,0U}}, +{ADD_D190,{4U,1U,0U}}, +{ADD_D190,{5U,1U,0U}}, +{ADD_D190,{6U,1U,0U}}, +{ADD_D190,{7U,1U,0U}}, +{ADD_D198,{0U,1U,0U}}, +{ADD_D198,{1U,1U,0U}}, +{ADD_D198,{2U,1U,0U}}, +{ADD_D198,{3U,1U,0U}}, +{ADD_D198,{4U,1U,0U}}, +{ADD_D198,{5U,1U,0U}}, +{ADD_D198,{6U,1U,0U}}, +{ADD_D198,{7U,1U,0U}}, +{ADD_D1A0,{0U,1U,0U}}, +{ADD_D1A0,{1U,1U,0U}}, +{ADD_D1A0,{2U,1U,0U}}, +{ADD_D1A0,{3U,1U,0U}}, +{ADD_D1A0,{4U,1U,0U}}, +{ADD_D1A0,{5U,1U,0U}}, +{ADD_D1A0,{6U,1U,0U}}, +{ADD_D1A0,{7U,1U,0U}}, +{ADD_D1A8,{0U,1U,0U}}, +{ADD_D1A8,{1U,1U,0U}}, +{ADD_D1A8,{2U,1U,0U}}, +{ADD_D1A8,{3U,1U,0U}}, +{ADD_D1A8,{4U,1U,0U}}, +{ADD_D1A8,{5U,1U,0U}}, +{ADD_D1A8,{6U,1U,0U}}, +{ADD_D1A8,{7U,1U,0U}}, +{ADD_D1B0,{0U,1U,0U}}, +{ADD_D1B0,{1U,1U,0U}}, +{ADD_D1B0,{2U,1U,0U}}, +{ADD_D1B0,{3U,1U,0U}}, +{ADD_D1B0,{4U,1U,0U}}, +{ADD_D1B0,{5U,1U,0U}}, +{ADD_D1B0,{6U,1U,0U}}, +{ADD_D1B0,{7U,1U,0U}}, +{ADD_D1B8,{0U,1U,0U}}, +{ADD_D1B9,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D1C0,{0U,1U,0U}}, +{ADDA_D1C0,{1U,1U,0U}}, +{ADDA_D1C0,{2U,1U,0U}}, +{ADDA_D1C0,{3U,1U,0U}}, +{ADDA_D1C0,{4U,1U,0U}}, +{ADDA_D1C0,{5U,1U,0U}}, +{ADDA_D1C0,{6U,1U,0U}}, +{ADDA_D1C0,{7U,1U,0U}}, +{ADDA_D1C8,{0U,1U,0U}}, +{ADDA_D1C8,{1U,1U,0U}}, +{ADDA_D1C8,{2U,1U,0U}}, +{ADDA_D1C8,{3U,1U,0U}}, +{ADDA_D1C8,{4U,1U,0U}}, +{ADDA_D1C8,{5U,1U,0U}}, +{ADDA_D1C8,{6U,1U,0U}}, +{ADDA_D1C8,{7U,1U,0U}}, +{ADDA_D1D0,{0U,1U,0U}}, +{ADDA_D1D0,{1U,1U,0U}}, +{ADDA_D1D0,{2U,1U,0U}}, +{ADDA_D1D0,{3U,1U,0U}}, +{ADDA_D1D0,{4U,1U,0U}}, +{ADDA_D1D0,{5U,1U,0U}}, +{ADDA_D1D0,{6U,1U,0U}}, +{ADDA_D1D0,{7U,1U,0U}}, +{ADDA_D1D8,{0U,1U,0U}}, +{ADDA_D1D8,{1U,1U,0U}}, +{ADDA_D1D8,{2U,1U,0U}}, +{ADDA_D1D8,{3U,1U,0U}}, +{ADDA_D1D8,{4U,1U,0U}}, +{ADDA_D1D8,{5U,1U,0U}}, +{ADDA_D1D8,{6U,1U,0U}}, +{ADDA_D1D8,{7U,1U,0U}}, +{ADDA_D1E0,{0U,1U,0U}}, +{ADDA_D1E0,{1U,1U,0U}}, +{ADDA_D1E0,{2U,1U,0U}}, +{ADDA_D1E0,{3U,1U,0U}}, +{ADDA_D1E0,{4U,1U,0U}}, +{ADDA_D1E0,{5U,1U,0U}}, +{ADDA_D1E0,{6U,1U,0U}}, +{ADDA_D1E0,{7U,1U,0U}}, +{ADDA_D1E8,{0U,1U,0U}}, +{ADDA_D1E8,{1U,1U,0U}}, +{ADDA_D1E8,{2U,1U,0U}}, +{ADDA_D1E8,{3U,1U,0U}}, +{ADDA_D1E8,{4U,1U,0U}}, +{ADDA_D1E8,{5U,1U,0U}}, +{ADDA_D1E8,{6U,1U,0U}}, +{ADDA_D1E8,{7U,1U,0U}}, +{ADDA_D1F0,{0U,1U,0U}}, +{ADDA_D1F0,{1U,1U,0U}}, +{ADDA_D1F0,{2U,1U,0U}}, +{ADDA_D1F0,{3U,1U,0U}}, +{ADDA_D1F0,{4U,1U,0U}}, +{ADDA_D1F0,{5U,1U,0U}}, +{ADDA_D1F0,{6U,1U,0U}}, +{ADDA_D1F0,{7U,1U,0U}}, +{ADDA_D1F8,{0U,1U,0U}}, +{ADDA_D1F9,{0U,1U,0U}}, +{ADDA_D1FA,{0U,1U,0U}}, +{ADDA_D1FB,{0U,1U,0U}}, +{ADDA_D1FC,{0U,1U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D000,{0U,2U,0U}}, +{ADD_D000,{1U,2U,0U}}, +{ADD_D000,{2U,2U,0U}}, +{ADD_D000,{3U,2U,0U}}, +{ADD_D000,{4U,2U,0U}}, +{ADD_D000,{5U,2U,0U}}, +{ADD_D000,{6U,2U,0U}}, +{ADD_D000,{7U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D010,{0U,2U,0U}}, +{ADD_D010,{1U,2U,0U}}, +{ADD_D010,{2U,2U,0U}}, +{ADD_D010,{3U,2U,0U}}, +{ADD_D010,{4U,2U,0U}}, +{ADD_D010,{5U,2U,0U}}, +{ADD_D010,{6U,2U,0U}}, +{ADD_D010,{7U,2U,0U}}, +{ADD_D018,{0U,2U,0U}}, +{ADD_D018,{1U,2U,0U}}, +{ADD_D018,{2U,2U,0U}}, +{ADD_D018,{3U,2U,0U}}, +{ADD_D018,{4U,2U,0U}}, +{ADD_D018,{5U,2U,0U}}, +{ADD_D018,{6U,2U,0U}}, +{ADD_D018,{7U,2U,0U}}, +{ADD_D020,{0U,2U,0U}}, +{ADD_D020,{1U,2U,0U}}, +{ADD_D020,{2U,2U,0U}}, +{ADD_D020,{3U,2U,0U}}, +{ADD_D020,{4U,2U,0U}}, +{ADD_D020,{5U,2U,0U}}, +{ADD_D020,{6U,2U,0U}}, +{ADD_D020,{7U,2U,0U}}, +{ADD_D028,{0U,2U,0U}}, +{ADD_D028,{1U,2U,0U}}, +{ADD_D028,{2U,2U,0U}}, +{ADD_D028,{3U,2U,0U}}, +{ADD_D028,{4U,2U,0U}}, +{ADD_D028,{5U,2U,0U}}, +{ADD_D028,{6U,2U,0U}}, +{ADD_D028,{7U,2U,0U}}, +{ADD_D030,{0U,2U,0U}}, +{ADD_D030,{1U,2U,0U}}, +{ADD_D030,{2U,2U,0U}}, +{ADD_D030,{3U,2U,0U}}, +{ADD_D030,{4U,2U,0U}}, +{ADD_D030,{5U,2U,0U}}, +{ADD_D030,{6U,2U,0U}}, +{ADD_D030,{7U,2U,0U}}, +{ADD_D038,{0U,2U,0U}}, +{ADD_D039,{0U,2U,0U}}, +{ADD_D03A,{0U,2U,0U}}, +{ADD_D03B,{0U,2U,0U}}, +{ADD_D03C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D040,{0U,2U,0U}}, +{ADD_D040,{1U,2U,0U}}, +{ADD_D040,{2U,2U,0U}}, +{ADD_D040,{3U,2U,0U}}, +{ADD_D040,{4U,2U,0U}}, +{ADD_D040,{5U,2U,0U}}, +{ADD_D040,{6U,2U,0U}}, +{ADD_D040,{7U,2U,0U}}, +{ADD_D048,{0U,2U,0U}}, +{ADD_D048,{1U,2U,0U}}, +{ADD_D048,{2U,2U,0U}}, +{ADD_D048,{3U,2U,0U}}, +{ADD_D048,{4U,2U,0U}}, +{ADD_D048,{5U,2U,0U}}, +{ADD_D048,{6U,2U,0U}}, +{ADD_D048,{7U,2U,0U}}, +{ADD_D050,{0U,2U,0U}}, +{ADD_D050,{1U,2U,0U}}, +{ADD_D050,{2U,2U,0U}}, +{ADD_D050,{3U,2U,0U}}, +{ADD_D050,{4U,2U,0U}}, +{ADD_D050,{5U,2U,0U}}, +{ADD_D050,{6U,2U,0U}}, +{ADD_D050,{7U,2U,0U}}, +{ADD_D058,{0U,2U,0U}}, +{ADD_D058,{1U,2U,0U}}, +{ADD_D058,{2U,2U,0U}}, +{ADD_D058,{3U,2U,0U}}, +{ADD_D058,{4U,2U,0U}}, +{ADD_D058,{5U,2U,0U}}, +{ADD_D058,{6U,2U,0U}}, +{ADD_D058,{7U,2U,0U}}, +{ADD_D060,{0U,2U,0U}}, +{ADD_D060,{1U,2U,0U}}, +{ADD_D060,{2U,2U,0U}}, +{ADD_D060,{3U,2U,0U}}, +{ADD_D060,{4U,2U,0U}}, +{ADD_D060,{5U,2U,0U}}, +{ADD_D060,{6U,2U,0U}}, +{ADD_D060,{7U,2U,0U}}, +{ADD_D068,{0U,2U,0U}}, +{ADD_D068,{1U,2U,0U}}, +{ADD_D068,{2U,2U,0U}}, +{ADD_D068,{3U,2U,0U}}, +{ADD_D068,{4U,2U,0U}}, +{ADD_D068,{5U,2U,0U}}, +{ADD_D068,{6U,2U,0U}}, +{ADD_D068,{7U,2U,0U}}, +{ADD_D070,{0U,2U,0U}}, +{ADD_D070,{1U,2U,0U}}, +{ADD_D070,{2U,2U,0U}}, +{ADD_D070,{3U,2U,0U}}, +{ADD_D070,{4U,2U,0U}}, +{ADD_D070,{5U,2U,0U}}, +{ADD_D070,{6U,2U,0U}}, +{ADD_D070,{7U,2U,0U}}, +{ADD_D078,{0U,2U,0U}}, +{ADD_D079,{0U,2U,0U}}, +{ADD_D07A,{0U,2U,0U}}, +{ADD_D07B,{0U,2U,0U}}, +{ADD_D07C,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D080,{0U,2U,0U}}, +{ADD_D080,{1U,2U,0U}}, +{ADD_D080,{2U,2U,0U}}, +{ADD_D080,{3U,2U,0U}}, +{ADD_D080,{4U,2U,0U}}, +{ADD_D080,{5U,2U,0U}}, +{ADD_D080,{6U,2U,0U}}, +{ADD_D080,{7U,2U,0U}}, +{ADD_D088,{0U,2U,0U}}, +{ADD_D088,{1U,2U,0U}}, +{ADD_D088,{2U,2U,0U}}, +{ADD_D088,{3U,2U,0U}}, +{ADD_D088,{4U,2U,0U}}, +{ADD_D088,{5U,2U,0U}}, +{ADD_D088,{6U,2U,0U}}, +{ADD_D088,{7U,2U,0U}}, +{ADD_D090,{0U,2U,0U}}, +{ADD_D090,{1U,2U,0U}}, +{ADD_D090,{2U,2U,0U}}, +{ADD_D090,{3U,2U,0U}}, +{ADD_D090,{4U,2U,0U}}, +{ADD_D090,{5U,2U,0U}}, +{ADD_D090,{6U,2U,0U}}, +{ADD_D090,{7U,2U,0U}}, +{ADD_D098,{0U,2U,0U}}, +{ADD_D098,{1U,2U,0U}}, +{ADD_D098,{2U,2U,0U}}, +{ADD_D098,{3U,2U,0U}}, +{ADD_D098,{4U,2U,0U}}, +{ADD_D098,{5U,2U,0U}}, +{ADD_D098,{6U,2U,0U}}, +{ADD_D098,{7U,2U,0U}}, +{ADD_D0A0,{0U,2U,0U}}, +{ADD_D0A0,{1U,2U,0U}}, +{ADD_D0A0,{2U,2U,0U}}, +{ADD_D0A0,{3U,2U,0U}}, +{ADD_D0A0,{4U,2U,0U}}, +{ADD_D0A0,{5U,2U,0U}}, +{ADD_D0A0,{6U,2U,0U}}, +{ADD_D0A0,{7U,2U,0U}}, +{ADD_D0A8,{0U,2U,0U}}, +{ADD_D0A8,{1U,2U,0U}}, +{ADD_D0A8,{2U,2U,0U}}, +{ADD_D0A8,{3U,2U,0U}}, +{ADD_D0A8,{4U,2U,0U}}, +{ADD_D0A8,{5U,2U,0U}}, +{ADD_D0A8,{6U,2U,0U}}, +{ADD_D0A8,{7U,2U,0U}}, +{ADD_D0B0,{0U,2U,0U}}, +{ADD_D0B0,{1U,2U,0U}}, +{ADD_D0B0,{2U,2U,0U}}, +{ADD_D0B0,{3U,2U,0U}}, +{ADD_D0B0,{4U,2U,0U}}, +{ADD_D0B0,{5U,2U,0U}}, +{ADD_D0B0,{6U,2U,0U}}, +{ADD_D0B0,{7U,2U,0U}}, +{ADD_D0B8,{0U,2U,0U}}, +{ADD_D0B9,{0U,2U,0U}}, +{ADD_D0BA,{0U,2U,0U}}, +{ADD_D0BB,{0U,2U,0U}}, +{ADD_D0BC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D0C0,{0U,2U,0U}}, +{ADDA_D0C0,{1U,2U,0U}}, +{ADDA_D0C0,{2U,2U,0U}}, +{ADDA_D0C0,{3U,2U,0U}}, +{ADDA_D0C0,{4U,2U,0U}}, +{ADDA_D0C0,{5U,2U,0U}}, +{ADDA_D0C0,{6U,2U,0U}}, +{ADDA_D0C0,{7U,2U,0U}}, +{ADDA_D0C8,{0U,2U,0U}}, +{ADDA_D0C8,{1U,2U,0U}}, +{ADDA_D0C8,{2U,2U,0U}}, +{ADDA_D0C8,{3U,2U,0U}}, +{ADDA_D0C8,{4U,2U,0U}}, +{ADDA_D0C8,{5U,2U,0U}}, +{ADDA_D0C8,{6U,2U,0U}}, +{ADDA_D0C8,{7U,2U,0U}}, +{ADDA_D0D0,{0U,2U,0U}}, +{ADDA_D0D0,{1U,2U,0U}}, +{ADDA_D0D0,{2U,2U,0U}}, +{ADDA_D0D0,{3U,2U,0U}}, +{ADDA_D0D0,{4U,2U,0U}}, +{ADDA_D0D0,{5U,2U,0U}}, +{ADDA_D0D0,{6U,2U,0U}}, +{ADDA_D0D0,{7U,2U,0U}}, +{ADDA_D0D8,{0U,2U,0U}}, +{ADDA_D0D8,{1U,2U,0U}}, +{ADDA_D0D8,{2U,2U,0U}}, +{ADDA_D0D8,{3U,2U,0U}}, +{ADDA_D0D8,{4U,2U,0U}}, +{ADDA_D0D8,{5U,2U,0U}}, +{ADDA_D0D8,{6U,2U,0U}}, +{ADDA_D0D8,{7U,2U,0U}}, +{ADDA_D0E0,{0U,2U,0U}}, +{ADDA_D0E0,{1U,2U,0U}}, +{ADDA_D0E0,{2U,2U,0U}}, +{ADDA_D0E0,{3U,2U,0U}}, +{ADDA_D0E0,{4U,2U,0U}}, +{ADDA_D0E0,{5U,2U,0U}}, +{ADDA_D0E0,{6U,2U,0U}}, +{ADDA_D0E0,{7U,2U,0U}}, +{ADDA_D0E8,{0U,2U,0U}}, +{ADDA_D0E8,{1U,2U,0U}}, +{ADDA_D0E8,{2U,2U,0U}}, +{ADDA_D0E8,{3U,2U,0U}}, +{ADDA_D0E8,{4U,2U,0U}}, +{ADDA_D0E8,{5U,2U,0U}}, +{ADDA_D0E8,{6U,2U,0U}}, +{ADDA_D0E8,{7U,2U,0U}}, +{ADDA_D0F0,{0U,2U,0U}}, +{ADDA_D0F0,{1U,2U,0U}}, +{ADDA_D0F0,{2U,2U,0U}}, +{ADDA_D0F0,{3U,2U,0U}}, +{ADDA_D0F0,{4U,2U,0U}}, +{ADDA_D0F0,{5U,2U,0U}}, +{ADDA_D0F0,{6U,2U,0U}}, +{ADDA_D0F0,{7U,2U,0U}}, +{ADDA_D0F8,{0U,2U,0U}}, +{ADDA_D0F9,{0U,2U,0U}}, +{ADDA_D0FA,{0U,2U,0U}}, +{ADDA_D0FB,{0U,2U,0U}}, +{ADDA_D0FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D100,{0U,2U,0U}}, +{ADDX_D100,{1U,2U,0U}}, +{ADDX_D100,{2U,2U,0U}}, +{ADDX_D100,{3U,2U,0U}}, +{ADDX_D100,{4U,2U,0U}}, +{ADDX_D100,{5U,2U,0U}}, +{ADDX_D100,{6U,2U,0U}}, +{ADDX_D100,{7U,2U,0U}}, +{ADDX_D108,{0U,2U,0U}}, +{ADDX_D108,{1U,2U,0U}}, +{ADDX_D108,{2U,2U,0U}}, +{ADDX_D108,{3U,2U,0U}}, +{ADDX_D108,{4U,2U,0U}}, +{ADDX_D108,{5U,2U,0U}}, +{ADDX_D108,{6U,2U,0U}}, +{ADDX_D108,{7U,2U,0U}}, +{ADD_D110,{0U,2U,0U}}, +{ADD_D110,{1U,2U,0U}}, +{ADD_D110,{2U,2U,0U}}, +{ADD_D110,{3U,2U,0U}}, +{ADD_D110,{4U,2U,0U}}, +{ADD_D110,{5U,2U,0U}}, +{ADD_D110,{6U,2U,0U}}, +{ADD_D110,{7U,2U,0U}}, +{ADD_D118,{0U,2U,0U}}, +{ADD_D118,{1U,2U,0U}}, +{ADD_D118,{2U,2U,0U}}, +{ADD_D118,{3U,2U,0U}}, +{ADD_D118,{4U,2U,0U}}, +{ADD_D118,{5U,2U,0U}}, +{ADD_D118,{6U,2U,0U}}, +{ADD_D118,{7U,2U,0U}}, +{ADD_D120,{0U,2U,0U}}, +{ADD_D120,{1U,2U,0U}}, +{ADD_D120,{2U,2U,0U}}, +{ADD_D120,{3U,2U,0U}}, +{ADD_D120,{4U,2U,0U}}, +{ADD_D120,{5U,2U,0U}}, +{ADD_D120,{6U,2U,0U}}, +{ADD_D120,{7U,2U,0U}}, +{ADD_D128,{0U,2U,0U}}, +{ADD_D128,{1U,2U,0U}}, +{ADD_D128,{2U,2U,0U}}, +{ADD_D128,{3U,2U,0U}}, +{ADD_D128,{4U,2U,0U}}, +{ADD_D128,{5U,2U,0U}}, +{ADD_D128,{6U,2U,0U}}, +{ADD_D128,{7U,2U,0U}}, +{ADD_D130,{0U,2U,0U}}, +{ADD_D130,{1U,2U,0U}}, +{ADD_D130,{2U,2U,0U}}, +{ADD_D130,{3U,2U,0U}}, +{ADD_D130,{4U,2U,0U}}, +{ADD_D130,{5U,2U,0U}}, +{ADD_D130,{6U,2U,0U}}, +{ADD_D130,{7U,2U,0U}}, +{ADD_D138,{0U,2U,0U}}, +{ADD_D139,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D140,{0U,2U,0U}}, +{ADDX_D140,{1U,2U,0U}}, +{ADDX_D140,{2U,2U,0U}}, +{ADDX_D140,{3U,2U,0U}}, +{ADDX_D140,{4U,2U,0U}}, +{ADDX_D140,{5U,2U,0U}}, +{ADDX_D140,{6U,2U,0U}}, +{ADDX_D140,{7U,2U,0U}}, +{ADDX_D148,{0U,2U,0U}}, +{ADDX_D148,{1U,2U,0U}}, +{ADDX_D148,{2U,2U,0U}}, +{ADDX_D148,{3U,2U,0U}}, +{ADDX_D148,{4U,2U,0U}}, +{ADDX_D148,{5U,2U,0U}}, +{ADDX_D148,{6U,2U,0U}}, +{ADDX_D148,{7U,2U,0U}}, +{ADD_D150,{0U,2U,0U}}, +{ADD_D150,{1U,2U,0U}}, +{ADD_D150,{2U,2U,0U}}, +{ADD_D150,{3U,2U,0U}}, +{ADD_D150,{4U,2U,0U}}, +{ADD_D150,{5U,2U,0U}}, +{ADD_D150,{6U,2U,0U}}, +{ADD_D150,{7U,2U,0U}}, +{ADD_D158,{0U,2U,0U}}, +{ADD_D158,{1U,2U,0U}}, +{ADD_D158,{2U,2U,0U}}, +{ADD_D158,{3U,2U,0U}}, +{ADD_D158,{4U,2U,0U}}, +{ADD_D158,{5U,2U,0U}}, +{ADD_D158,{6U,2U,0U}}, +{ADD_D158,{7U,2U,0U}}, +{ADD_D160,{0U,2U,0U}}, +{ADD_D160,{1U,2U,0U}}, +{ADD_D160,{2U,2U,0U}}, +{ADD_D160,{3U,2U,0U}}, +{ADD_D160,{4U,2U,0U}}, +{ADD_D160,{5U,2U,0U}}, +{ADD_D160,{6U,2U,0U}}, +{ADD_D160,{7U,2U,0U}}, +{ADD_D168,{0U,2U,0U}}, +{ADD_D168,{1U,2U,0U}}, +{ADD_D168,{2U,2U,0U}}, +{ADD_D168,{3U,2U,0U}}, +{ADD_D168,{4U,2U,0U}}, +{ADD_D168,{5U,2U,0U}}, +{ADD_D168,{6U,2U,0U}}, +{ADD_D168,{7U,2U,0U}}, +{ADD_D170,{0U,2U,0U}}, +{ADD_D170,{1U,2U,0U}}, +{ADD_D170,{2U,2U,0U}}, +{ADD_D170,{3U,2U,0U}}, +{ADD_D170,{4U,2U,0U}}, +{ADD_D170,{5U,2U,0U}}, +{ADD_D170,{6U,2U,0U}}, +{ADD_D170,{7U,2U,0U}}, +{ADD_D178,{0U,2U,0U}}, +{ADD_D179,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D180,{0U,2U,0U}}, +{ADDX_D180,{1U,2U,0U}}, +{ADDX_D180,{2U,2U,0U}}, +{ADDX_D180,{3U,2U,0U}}, +{ADDX_D180,{4U,2U,0U}}, +{ADDX_D180,{5U,2U,0U}}, +{ADDX_D180,{6U,2U,0U}}, +{ADDX_D180,{7U,2U,0U}}, +{ADDX_D188,{0U,2U,0U}}, +{ADDX_D188,{1U,2U,0U}}, +{ADDX_D188,{2U,2U,0U}}, +{ADDX_D188,{3U,2U,0U}}, +{ADDX_D188,{4U,2U,0U}}, +{ADDX_D188,{5U,2U,0U}}, +{ADDX_D188,{6U,2U,0U}}, +{ADDX_D188,{7U,2U,0U}}, +{ADD_D190,{0U,2U,0U}}, +{ADD_D190,{1U,2U,0U}}, +{ADD_D190,{2U,2U,0U}}, +{ADD_D190,{3U,2U,0U}}, +{ADD_D190,{4U,2U,0U}}, +{ADD_D190,{5U,2U,0U}}, +{ADD_D190,{6U,2U,0U}}, +{ADD_D190,{7U,2U,0U}}, +{ADD_D198,{0U,2U,0U}}, +{ADD_D198,{1U,2U,0U}}, +{ADD_D198,{2U,2U,0U}}, +{ADD_D198,{3U,2U,0U}}, +{ADD_D198,{4U,2U,0U}}, +{ADD_D198,{5U,2U,0U}}, +{ADD_D198,{6U,2U,0U}}, +{ADD_D198,{7U,2U,0U}}, +{ADD_D1A0,{0U,2U,0U}}, +{ADD_D1A0,{1U,2U,0U}}, +{ADD_D1A0,{2U,2U,0U}}, +{ADD_D1A0,{3U,2U,0U}}, +{ADD_D1A0,{4U,2U,0U}}, +{ADD_D1A0,{5U,2U,0U}}, +{ADD_D1A0,{6U,2U,0U}}, +{ADD_D1A0,{7U,2U,0U}}, +{ADD_D1A8,{0U,2U,0U}}, +{ADD_D1A8,{1U,2U,0U}}, +{ADD_D1A8,{2U,2U,0U}}, +{ADD_D1A8,{3U,2U,0U}}, +{ADD_D1A8,{4U,2U,0U}}, +{ADD_D1A8,{5U,2U,0U}}, +{ADD_D1A8,{6U,2U,0U}}, +{ADD_D1A8,{7U,2U,0U}}, +{ADD_D1B0,{0U,2U,0U}}, +{ADD_D1B0,{1U,2U,0U}}, +{ADD_D1B0,{2U,2U,0U}}, +{ADD_D1B0,{3U,2U,0U}}, +{ADD_D1B0,{4U,2U,0U}}, +{ADD_D1B0,{5U,2U,0U}}, +{ADD_D1B0,{6U,2U,0U}}, +{ADD_D1B0,{7U,2U,0U}}, +{ADD_D1B8,{0U,2U,0U}}, +{ADD_D1B9,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D1C0,{0U,2U,0U}}, +{ADDA_D1C0,{1U,2U,0U}}, +{ADDA_D1C0,{2U,2U,0U}}, +{ADDA_D1C0,{3U,2U,0U}}, +{ADDA_D1C0,{4U,2U,0U}}, +{ADDA_D1C0,{5U,2U,0U}}, +{ADDA_D1C0,{6U,2U,0U}}, +{ADDA_D1C0,{7U,2U,0U}}, +{ADDA_D1C8,{0U,2U,0U}}, +{ADDA_D1C8,{1U,2U,0U}}, +{ADDA_D1C8,{2U,2U,0U}}, +{ADDA_D1C8,{3U,2U,0U}}, +{ADDA_D1C8,{4U,2U,0U}}, +{ADDA_D1C8,{5U,2U,0U}}, +{ADDA_D1C8,{6U,2U,0U}}, +{ADDA_D1C8,{7U,2U,0U}}, +{ADDA_D1D0,{0U,2U,0U}}, +{ADDA_D1D0,{1U,2U,0U}}, +{ADDA_D1D0,{2U,2U,0U}}, +{ADDA_D1D0,{3U,2U,0U}}, +{ADDA_D1D0,{4U,2U,0U}}, +{ADDA_D1D0,{5U,2U,0U}}, +{ADDA_D1D0,{6U,2U,0U}}, +{ADDA_D1D0,{7U,2U,0U}}, +{ADDA_D1D8,{0U,2U,0U}}, +{ADDA_D1D8,{1U,2U,0U}}, +{ADDA_D1D8,{2U,2U,0U}}, +{ADDA_D1D8,{3U,2U,0U}}, +{ADDA_D1D8,{4U,2U,0U}}, +{ADDA_D1D8,{5U,2U,0U}}, +{ADDA_D1D8,{6U,2U,0U}}, +{ADDA_D1D8,{7U,2U,0U}}, +{ADDA_D1E0,{0U,2U,0U}}, +{ADDA_D1E0,{1U,2U,0U}}, +{ADDA_D1E0,{2U,2U,0U}}, +{ADDA_D1E0,{3U,2U,0U}}, +{ADDA_D1E0,{4U,2U,0U}}, +{ADDA_D1E0,{5U,2U,0U}}, +{ADDA_D1E0,{6U,2U,0U}}, +{ADDA_D1E0,{7U,2U,0U}}, +{ADDA_D1E8,{0U,2U,0U}}, +{ADDA_D1E8,{1U,2U,0U}}, +{ADDA_D1E8,{2U,2U,0U}}, +{ADDA_D1E8,{3U,2U,0U}}, +{ADDA_D1E8,{4U,2U,0U}}, +{ADDA_D1E8,{5U,2U,0U}}, +{ADDA_D1E8,{6U,2U,0U}}, +{ADDA_D1E8,{7U,2U,0U}}, +{ADDA_D1F0,{0U,2U,0U}}, +{ADDA_D1F0,{1U,2U,0U}}, +{ADDA_D1F0,{2U,2U,0U}}, +{ADDA_D1F0,{3U,2U,0U}}, +{ADDA_D1F0,{4U,2U,0U}}, +{ADDA_D1F0,{5U,2U,0U}}, +{ADDA_D1F0,{6U,2U,0U}}, +{ADDA_D1F0,{7U,2U,0U}}, +{ADDA_D1F8,{0U,2U,0U}}, +{ADDA_D1F9,{0U,2U,0U}}, +{ADDA_D1FA,{0U,2U,0U}}, +{ADDA_D1FB,{0U,2U,0U}}, +{ADDA_D1FC,{0U,2U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D000,{0U,3U,0U}}, +{ADD_D000,{1U,3U,0U}}, +{ADD_D000,{2U,3U,0U}}, +{ADD_D000,{3U,3U,0U}}, +{ADD_D000,{4U,3U,0U}}, +{ADD_D000,{5U,3U,0U}}, +{ADD_D000,{6U,3U,0U}}, +{ADD_D000,{7U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D010,{0U,3U,0U}}, +{ADD_D010,{1U,3U,0U}}, +{ADD_D010,{2U,3U,0U}}, +{ADD_D010,{3U,3U,0U}}, +{ADD_D010,{4U,3U,0U}}, +{ADD_D010,{5U,3U,0U}}, +{ADD_D010,{6U,3U,0U}}, +{ADD_D010,{7U,3U,0U}}, +{ADD_D018,{0U,3U,0U}}, +{ADD_D018,{1U,3U,0U}}, +{ADD_D018,{2U,3U,0U}}, +{ADD_D018,{3U,3U,0U}}, +{ADD_D018,{4U,3U,0U}}, +{ADD_D018,{5U,3U,0U}}, +{ADD_D018,{6U,3U,0U}}, +{ADD_D018,{7U,3U,0U}}, +{ADD_D020,{0U,3U,0U}}, +{ADD_D020,{1U,3U,0U}}, +{ADD_D020,{2U,3U,0U}}, +{ADD_D020,{3U,3U,0U}}, +{ADD_D020,{4U,3U,0U}}, +{ADD_D020,{5U,3U,0U}}, +{ADD_D020,{6U,3U,0U}}, +{ADD_D020,{7U,3U,0U}}, +{ADD_D028,{0U,3U,0U}}, +{ADD_D028,{1U,3U,0U}}, +{ADD_D028,{2U,3U,0U}}, +{ADD_D028,{3U,3U,0U}}, +{ADD_D028,{4U,3U,0U}}, +{ADD_D028,{5U,3U,0U}}, +{ADD_D028,{6U,3U,0U}}, +{ADD_D028,{7U,3U,0U}}, +{ADD_D030,{0U,3U,0U}}, +{ADD_D030,{1U,3U,0U}}, +{ADD_D030,{2U,3U,0U}}, +{ADD_D030,{3U,3U,0U}}, +{ADD_D030,{4U,3U,0U}}, +{ADD_D030,{5U,3U,0U}}, +{ADD_D030,{6U,3U,0U}}, +{ADD_D030,{7U,3U,0U}}, +{ADD_D038,{0U,3U,0U}}, +{ADD_D039,{0U,3U,0U}}, +{ADD_D03A,{0U,3U,0U}}, +{ADD_D03B,{0U,3U,0U}}, +{ADD_D03C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D040,{0U,3U,0U}}, +{ADD_D040,{1U,3U,0U}}, +{ADD_D040,{2U,3U,0U}}, +{ADD_D040,{3U,3U,0U}}, +{ADD_D040,{4U,3U,0U}}, +{ADD_D040,{5U,3U,0U}}, +{ADD_D040,{6U,3U,0U}}, +{ADD_D040,{7U,3U,0U}}, +{ADD_D048,{0U,3U,0U}}, +{ADD_D048,{1U,3U,0U}}, +{ADD_D048,{2U,3U,0U}}, +{ADD_D048,{3U,3U,0U}}, +{ADD_D048,{4U,3U,0U}}, +{ADD_D048,{5U,3U,0U}}, +{ADD_D048,{6U,3U,0U}}, +{ADD_D048,{7U,3U,0U}}, +{ADD_D050,{0U,3U,0U}}, +{ADD_D050,{1U,3U,0U}}, +{ADD_D050,{2U,3U,0U}}, +{ADD_D050,{3U,3U,0U}}, +{ADD_D050,{4U,3U,0U}}, +{ADD_D050,{5U,3U,0U}}, +{ADD_D050,{6U,3U,0U}}, +{ADD_D050,{7U,3U,0U}}, +{ADD_D058,{0U,3U,0U}}, +{ADD_D058,{1U,3U,0U}}, +{ADD_D058,{2U,3U,0U}}, +{ADD_D058,{3U,3U,0U}}, +{ADD_D058,{4U,3U,0U}}, +{ADD_D058,{5U,3U,0U}}, +{ADD_D058,{6U,3U,0U}}, +{ADD_D058,{7U,3U,0U}}, +{ADD_D060,{0U,3U,0U}}, +{ADD_D060,{1U,3U,0U}}, +{ADD_D060,{2U,3U,0U}}, +{ADD_D060,{3U,3U,0U}}, +{ADD_D060,{4U,3U,0U}}, +{ADD_D060,{5U,3U,0U}}, +{ADD_D060,{6U,3U,0U}}, +{ADD_D060,{7U,3U,0U}}, +{ADD_D068,{0U,3U,0U}}, +{ADD_D068,{1U,3U,0U}}, +{ADD_D068,{2U,3U,0U}}, +{ADD_D068,{3U,3U,0U}}, +{ADD_D068,{4U,3U,0U}}, +{ADD_D068,{5U,3U,0U}}, +{ADD_D068,{6U,3U,0U}}, +{ADD_D068,{7U,3U,0U}}, +{ADD_D070,{0U,3U,0U}}, +{ADD_D070,{1U,3U,0U}}, +{ADD_D070,{2U,3U,0U}}, +{ADD_D070,{3U,3U,0U}}, +{ADD_D070,{4U,3U,0U}}, +{ADD_D070,{5U,3U,0U}}, +{ADD_D070,{6U,3U,0U}}, +{ADD_D070,{7U,3U,0U}}, +{ADD_D078,{0U,3U,0U}}, +{ADD_D079,{0U,3U,0U}}, +{ADD_D07A,{0U,3U,0U}}, +{ADD_D07B,{0U,3U,0U}}, +{ADD_D07C,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D080,{0U,3U,0U}}, +{ADD_D080,{1U,3U,0U}}, +{ADD_D080,{2U,3U,0U}}, +{ADD_D080,{3U,3U,0U}}, +{ADD_D080,{4U,3U,0U}}, +{ADD_D080,{5U,3U,0U}}, +{ADD_D080,{6U,3U,0U}}, +{ADD_D080,{7U,3U,0U}}, +{ADD_D088,{0U,3U,0U}}, +{ADD_D088,{1U,3U,0U}}, +{ADD_D088,{2U,3U,0U}}, +{ADD_D088,{3U,3U,0U}}, +{ADD_D088,{4U,3U,0U}}, +{ADD_D088,{5U,3U,0U}}, +{ADD_D088,{6U,3U,0U}}, +{ADD_D088,{7U,3U,0U}}, +{ADD_D090,{0U,3U,0U}}, +{ADD_D090,{1U,3U,0U}}, +{ADD_D090,{2U,3U,0U}}, +{ADD_D090,{3U,3U,0U}}, +{ADD_D090,{4U,3U,0U}}, +{ADD_D090,{5U,3U,0U}}, +{ADD_D090,{6U,3U,0U}}, +{ADD_D090,{7U,3U,0U}}, +{ADD_D098,{0U,3U,0U}}, +{ADD_D098,{1U,3U,0U}}, +{ADD_D098,{2U,3U,0U}}, +{ADD_D098,{3U,3U,0U}}, +{ADD_D098,{4U,3U,0U}}, +{ADD_D098,{5U,3U,0U}}, +{ADD_D098,{6U,3U,0U}}, +{ADD_D098,{7U,3U,0U}}, +{ADD_D0A0,{0U,3U,0U}}, +{ADD_D0A0,{1U,3U,0U}}, +{ADD_D0A0,{2U,3U,0U}}, +{ADD_D0A0,{3U,3U,0U}}, +{ADD_D0A0,{4U,3U,0U}}, +{ADD_D0A0,{5U,3U,0U}}, +{ADD_D0A0,{6U,3U,0U}}, +{ADD_D0A0,{7U,3U,0U}}, +{ADD_D0A8,{0U,3U,0U}}, +{ADD_D0A8,{1U,3U,0U}}, +{ADD_D0A8,{2U,3U,0U}}, +{ADD_D0A8,{3U,3U,0U}}, +{ADD_D0A8,{4U,3U,0U}}, +{ADD_D0A8,{5U,3U,0U}}, +{ADD_D0A8,{6U,3U,0U}}, +{ADD_D0A8,{7U,3U,0U}}, +{ADD_D0B0,{0U,3U,0U}}, +{ADD_D0B0,{1U,3U,0U}}, +{ADD_D0B0,{2U,3U,0U}}, +{ADD_D0B0,{3U,3U,0U}}, +{ADD_D0B0,{4U,3U,0U}}, +{ADD_D0B0,{5U,3U,0U}}, +{ADD_D0B0,{6U,3U,0U}}, +{ADD_D0B0,{7U,3U,0U}}, +{ADD_D0B8,{0U,3U,0U}}, +{ADD_D0B9,{0U,3U,0U}}, +{ADD_D0BA,{0U,3U,0U}}, +{ADD_D0BB,{0U,3U,0U}}, +{ADD_D0BC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D0C0,{0U,3U,0U}}, +{ADDA_D0C0,{1U,3U,0U}}, +{ADDA_D0C0,{2U,3U,0U}}, +{ADDA_D0C0,{3U,3U,0U}}, +{ADDA_D0C0,{4U,3U,0U}}, +{ADDA_D0C0,{5U,3U,0U}}, +{ADDA_D0C0,{6U,3U,0U}}, +{ADDA_D0C0,{7U,3U,0U}}, +{ADDA_D0C8,{0U,3U,0U}}, +{ADDA_D0C8,{1U,3U,0U}}, +{ADDA_D0C8,{2U,3U,0U}}, +{ADDA_D0C8,{3U,3U,0U}}, +{ADDA_D0C8,{4U,3U,0U}}, +{ADDA_D0C8,{5U,3U,0U}}, +{ADDA_D0C8,{6U,3U,0U}}, +{ADDA_D0C8,{7U,3U,0U}}, +{ADDA_D0D0,{0U,3U,0U}}, +{ADDA_D0D0,{1U,3U,0U}}, +{ADDA_D0D0,{2U,3U,0U}}, +{ADDA_D0D0,{3U,3U,0U}}, +{ADDA_D0D0,{4U,3U,0U}}, +{ADDA_D0D0,{5U,3U,0U}}, +{ADDA_D0D0,{6U,3U,0U}}, +{ADDA_D0D0,{7U,3U,0U}}, +{ADDA_D0D8,{0U,3U,0U}}, +{ADDA_D0D8,{1U,3U,0U}}, +{ADDA_D0D8,{2U,3U,0U}}, +{ADDA_D0D8,{3U,3U,0U}}, +{ADDA_D0D8,{4U,3U,0U}}, +{ADDA_D0D8,{5U,3U,0U}}, +{ADDA_D0D8,{6U,3U,0U}}, +{ADDA_D0D8,{7U,3U,0U}}, +{ADDA_D0E0,{0U,3U,0U}}, +{ADDA_D0E0,{1U,3U,0U}}, +{ADDA_D0E0,{2U,3U,0U}}, +{ADDA_D0E0,{3U,3U,0U}}, +{ADDA_D0E0,{4U,3U,0U}}, +{ADDA_D0E0,{5U,3U,0U}}, +{ADDA_D0E0,{6U,3U,0U}}, +{ADDA_D0E0,{7U,3U,0U}}, +{ADDA_D0E8,{0U,3U,0U}}, +{ADDA_D0E8,{1U,3U,0U}}, +{ADDA_D0E8,{2U,3U,0U}}, +{ADDA_D0E8,{3U,3U,0U}}, +{ADDA_D0E8,{4U,3U,0U}}, +{ADDA_D0E8,{5U,3U,0U}}, +{ADDA_D0E8,{6U,3U,0U}}, +{ADDA_D0E8,{7U,3U,0U}}, +{ADDA_D0F0,{0U,3U,0U}}, +{ADDA_D0F0,{1U,3U,0U}}, +{ADDA_D0F0,{2U,3U,0U}}, +{ADDA_D0F0,{3U,3U,0U}}, +{ADDA_D0F0,{4U,3U,0U}}, +{ADDA_D0F0,{5U,3U,0U}}, +{ADDA_D0F0,{6U,3U,0U}}, +{ADDA_D0F0,{7U,3U,0U}}, +{ADDA_D0F8,{0U,3U,0U}}, +{ADDA_D0F9,{0U,3U,0U}}, +{ADDA_D0FA,{0U,3U,0U}}, +{ADDA_D0FB,{0U,3U,0U}}, +{ADDA_D0FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D100,{0U,3U,0U}}, +{ADDX_D100,{1U,3U,0U}}, +{ADDX_D100,{2U,3U,0U}}, +{ADDX_D100,{3U,3U,0U}}, +{ADDX_D100,{4U,3U,0U}}, +{ADDX_D100,{5U,3U,0U}}, +{ADDX_D100,{6U,3U,0U}}, +{ADDX_D100,{7U,3U,0U}}, +{ADDX_D108,{0U,3U,0U}}, +{ADDX_D108,{1U,3U,0U}}, +{ADDX_D108,{2U,3U,0U}}, +{ADDX_D108,{3U,3U,0U}}, +{ADDX_D108,{4U,3U,0U}}, +{ADDX_D108,{5U,3U,0U}}, +{ADDX_D108,{6U,3U,0U}}, +{ADDX_D108,{7U,3U,0U}}, +{ADD_D110,{0U,3U,0U}}, +{ADD_D110,{1U,3U,0U}}, +{ADD_D110,{2U,3U,0U}}, +{ADD_D110,{3U,3U,0U}}, +{ADD_D110,{4U,3U,0U}}, +{ADD_D110,{5U,3U,0U}}, +{ADD_D110,{6U,3U,0U}}, +{ADD_D110,{7U,3U,0U}}, +{ADD_D118,{0U,3U,0U}}, +{ADD_D118,{1U,3U,0U}}, +{ADD_D118,{2U,3U,0U}}, +{ADD_D118,{3U,3U,0U}}, +{ADD_D118,{4U,3U,0U}}, +{ADD_D118,{5U,3U,0U}}, +{ADD_D118,{6U,3U,0U}}, +{ADD_D118,{7U,3U,0U}}, +{ADD_D120,{0U,3U,0U}}, +{ADD_D120,{1U,3U,0U}}, +{ADD_D120,{2U,3U,0U}}, +{ADD_D120,{3U,3U,0U}}, +{ADD_D120,{4U,3U,0U}}, +{ADD_D120,{5U,3U,0U}}, +{ADD_D120,{6U,3U,0U}}, +{ADD_D120,{7U,3U,0U}}, +{ADD_D128,{0U,3U,0U}}, +{ADD_D128,{1U,3U,0U}}, +{ADD_D128,{2U,3U,0U}}, +{ADD_D128,{3U,3U,0U}}, +{ADD_D128,{4U,3U,0U}}, +{ADD_D128,{5U,3U,0U}}, +{ADD_D128,{6U,3U,0U}}, +{ADD_D128,{7U,3U,0U}}, +{ADD_D130,{0U,3U,0U}}, +{ADD_D130,{1U,3U,0U}}, +{ADD_D130,{2U,3U,0U}}, +{ADD_D130,{3U,3U,0U}}, +{ADD_D130,{4U,3U,0U}}, +{ADD_D130,{5U,3U,0U}}, +{ADD_D130,{6U,3U,0U}}, +{ADD_D130,{7U,3U,0U}}, +{ADD_D138,{0U,3U,0U}}, +{ADD_D139,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D140,{0U,3U,0U}}, +{ADDX_D140,{1U,3U,0U}}, +{ADDX_D140,{2U,3U,0U}}, +{ADDX_D140,{3U,3U,0U}}, +{ADDX_D140,{4U,3U,0U}}, +{ADDX_D140,{5U,3U,0U}}, +{ADDX_D140,{6U,3U,0U}}, +{ADDX_D140,{7U,3U,0U}}, +{ADDX_D148,{0U,3U,0U}}, +{ADDX_D148,{1U,3U,0U}}, +{ADDX_D148,{2U,3U,0U}}, +{ADDX_D148,{3U,3U,0U}}, +{ADDX_D148,{4U,3U,0U}}, +{ADDX_D148,{5U,3U,0U}}, +{ADDX_D148,{6U,3U,0U}}, +{ADDX_D148,{7U,3U,0U}}, +{ADD_D150,{0U,3U,0U}}, +{ADD_D150,{1U,3U,0U}}, +{ADD_D150,{2U,3U,0U}}, +{ADD_D150,{3U,3U,0U}}, +{ADD_D150,{4U,3U,0U}}, +{ADD_D150,{5U,3U,0U}}, +{ADD_D150,{6U,3U,0U}}, +{ADD_D150,{7U,3U,0U}}, +{ADD_D158,{0U,3U,0U}}, +{ADD_D158,{1U,3U,0U}}, +{ADD_D158,{2U,3U,0U}}, +{ADD_D158,{3U,3U,0U}}, +{ADD_D158,{4U,3U,0U}}, +{ADD_D158,{5U,3U,0U}}, +{ADD_D158,{6U,3U,0U}}, +{ADD_D158,{7U,3U,0U}}, +{ADD_D160,{0U,3U,0U}}, +{ADD_D160,{1U,3U,0U}}, +{ADD_D160,{2U,3U,0U}}, +{ADD_D160,{3U,3U,0U}}, +{ADD_D160,{4U,3U,0U}}, +{ADD_D160,{5U,3U,0U}}, +{ADD_D160,{6U,3U,0U}}, +{ADD_D160,{7U,3U,0U}}, +{ADD_D168,{0U,3U,0U}}, +{ADD_D168,{1U,3U,0U}}, +{ADD_D168,{2U,3U,0U}}, +{ADD_D168,{3U,3U,0U}}, +{ADD_D168,{4U,3U,0U}}, +{ADD_D168,{5U,3U,0U}}, +{ADD_D168,{6U,3U,0U}}, +{ADD_D168,{7U,3U,0U}}, +{ADD_D170,{0U,3U,0U}}, +{ADD_D170,{1U,3U,0U}}, +{ADD_D170,{2U,3U,0U}}, +{ADD_D170,{3U,3U,0U}}, +{ADD_D170,{4U,3U,0U}}, +{ADD_D170,{5U,3U,0U}}, +{ADD_D170,{6U,3U,0U}}, +{ADD_D170,{7U,3U,0U}}, +{ADD_D178,{0U,3U,0U}}, +{ADD_D179,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D180,{0U,3U,0U}}, +{ADDX_D180,{1U,3U,0U}}, +{ADDX_D180,{2U,3U,0U}}, +{ADDX_D180,{3U,3U,0U}}, +{ADDX_D180,{4U,3U,0U}}, +{ADDX_D180,{5U,3U,0U}}, +{ADDX_D180,{6U,3U,0U}}, +{ADDX_D180,{7U,3U,0U}}, +{ADDX_D188,{0U,3U,0U}}, +{ADDX_D188,{1U,3U,0U}}, +{ADDX_D188,{2U,3U,0U}}, +{ADDX_D188,{3U,3U,0U}}, +{ADDX_D188,{4U,3U,0U}}, +{ADDX_D188,{5U,3U,0U}}, +{ADDX_D188,{6U,3U,0U}}, +{ADDX_D188,{7U,3U,0U}}, +{ADD_D190,{0U,3U,0U}}, +{ADD_D190,{1U,3U,0U}}, +{ADD_D190,{2U,3U,0U}}, +{ADD_D190,{3U,3U,0U}}, +{ADD_D190,{4U,3U,0U}}, +{ADD_D190,{5U,3U,0U}}, +{ADD_D190,{6U,3U,0U}}, +{ADD_D190,{7U,3U,0U}}, +{ADD_D198,{0U,3U,0U}}, +{ADD_D198,{1U,3U,0U}}, +{ADD_D198,{2U,3U,0U}}, +{ADD_D198,{3U,3U,0U}}, +{ADD_D198,{4U,3U,0U}}, +{ADD_D198,{5U,3U,0U}}, +{ADD_D198,{6U,3U,0U}}, +{ADD_D198,{7U,3U,0U}}, +{ADD_D1A0,{0U,3U,0U}}, +{ADD_D1A0,{1U,3U,0U}}, +{ADD_D1A0,{2U,3U,0U}}, +{ADD_D1A0,{3U,3U,0U}}, +{ADD_D1A0,{4U,3U,0U}}, +{ADD_D1A0,{5U,3U,0U}}, +{ADD_D1A0,{6U,3U,0U}}, +{ADD_D1A0,{7U,3U,0U}}, +{ADD_D1A8,{0U,3U,0U}}, +{ADD_D1A8,{1U,3U,0U}}, +{ADD_D1A8,{2U,3U,0U}}, +{ADD_D1A8,{3U,3U,0U}}, +{ADD_D1A8,{4U,3U,0U}}, +{ADD_D1A8,{5U,3U,0U}}, +{ADD_D1A8,{6U,3U,0U}}, +{ADD_D1A8,{7U,3U,0U}}, +{ADD_D1B0,{0U,3U,0U}}, +{ADD_D1B0,{1U,3U,0U}}, +{ADD_D1B0,{2U,3U,0U}}, +{ADD_D1B0,{3U,3U,0U}}, +{ADD_D1B0,{4U,3U,0U}}, +{ADD_D1B0,{5U,3U,0U}}, +{ADD_D1B0,{6U,3U,0U}}, +{ADD_D1B0,{7U,3U,0U}}, +{ADD_D1B8,{0U,3U,0U}}, +{ADD_D1B9,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D1C0,{0U,3U,0U}}, +{ADDA_D1C0,{1U,3U,0U}}, +{ADDA_D1C0,{2U,3U,0U}}, +{ADDA_D1C0,{3U,3U,0U}}, +{ADDA_D1C0,{4U,3U,0U}}, +{ADDA_D1C0,{5U,3U,0U}}, +{ADDA_D1C0,{6U,3U,0U}}, +{ADDA_D1C0,{7U,3U,0U}}, +{ADDA_D1C8,{0U,3U,0U}}, +{ADDA_D1C8,{1U,3U,0U}}, +{ADDA_D1C8,{2U,3U,0U}}, +{ADDA_D1C8,{3U,3U,0U}}, +{ADDA_D1C8,{4U,3U,0U}}, +{ADDA_D1C8,{5U,3U,0U}}, +{ADDA_D1C8,{6U,3U,0U}}, +{ADDA_D1C8,{7U,3U,0U}}, +{ADDA_D1D0,{0U,3U,0U}}, +{ADDA_D1D0,{1U,3U,0U}}, +{ADDA_D1D0,{2U,3U,0U}}, +{ADDA_D1D0,{3U,3U,0U}}, +{ADDA_D1D0,{4U,3U,0U}}, +{ADDA_D1D0,{5U,3U,0U}}, +{ADDA_D1D0,{6U,3U,0U}}, +{ADDA_D1D0,{7U,3U,0U}}, +{ADDA_D1D8,{0U,3U,0U}}, +{ADDA_D1D8,{1U,3U,0U}}, +{ADDA_D1D8,{2U,3U,0U}}, +{ADDA_D1D8,{3U,3U,0U}}, +{ADDA_D1D8,{4U,3U,0U}}, +{ADDA_D1D8,{5U,3U,0U}}, +{ADDA_D1D8,{6U,3U,0U}}, +{ADDA_D1D8,{7U,3U,0U}}, +{ADDA_D1E0,{0U,3U,0U}}, +{ADDA_D1E0,{1U,3U,0U}}, +{ADDA_D1E0,{2U,3U,0U}}, +{ADDA_D1E0,{3U,3U,0U}}, +{ADDA_D1E0,{4U,3U,0U}}, +{ADDA_D1E0,{5U,3U,0U}}, +{ADDA_D1E0,{6U,3U,0U}}, +{ADDA_D1E0,{7U,3U,0U}}, +{ADDA_D1E8,{0U,3U,0U}}, +{ADDA_D1E8,{1U,3U,0U}}, +{ADDA_D1E8,{2U,3U,0U}}, +{ADDA_D1E8,{3U,3U,0U}}, +{ADDA_D1E8,{4U,3U,0U}}, +{ADDA_D1E8,{5U,3U,0U}}, +{ADDA_D1E8,{6U,3U,0U}}, +{ADDA_D1E8,{7U,3U,0U}}, +{ADDA_D1F0,{0U,3U,0U}}, +{ADDA_D1F0,{1U,3U,0U}}, +{ADDA_D1F0,{2U,3U,0U}}, +{ADDA_D1F0,{3U,3U,0U}}, +{ADDA_D1F0,{4U,3U,0U}}, +{ADDA_D1F0,{5U,3U,0U}}, +{ADDA_D1F0,{6U,3U,0U}}, +{ADDA_D1F0,{7U,3U,0U}}, +{ADDA_D1F8,{0U,3U,0U}}, +{ADDA_D1F9,{0U,3U,0U}}, +{ADDA_D1FA,{0U,3U,0U}}, +{ADDA_D1FB,{0U,3U,0U}}, +{ADDA_D1FC,{0U,3U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D000,{0U,4U,0U}}, +{ADD_D000,{1U,4U,0U}}, +{ADD_D000,{2U,4U,0U}}, +{ADD_D000,{3U,4U,0U}}, +{ADD_D000,{4U,4U,0U}}, +{ADD_D000,{5U,4U,0U}}, +{ADD_D000,{6U,4U,0U}}, +{ADD_D000,{7U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D010,{0U,4U,0U}}, +{ADD_D010,{1U,4U,0U}}, +{ADD_D010,{2U,4U,0U}}, +{ADD_D010,{3U,4U,0U}}, +{ADD_D010,{4U,4U,0U}}, +{ADD_D010,{5U,4U,0U}}, +{ADD_D010,{6U,4U,0U}}, +{ADD_D010,{7U,4U,0U}}, +{ADD_D018,{0U,4U,0U}}, +{ADD_D018,{1U,4U,0U}}, +{ADD_D018,{2U,4U,0U}}, +{ADD_D018,{3U,4U,0U}}, +{ADD_D018,{4U,4U,0U}}, +{ADD_D018,{5U,4U,0U}}, +{ADD_D018,{6U,4U,0U}}, +{ADD_D018,{7U,4U,0U}}, +{ADD_D020,{0U,4U,0U}}, +{ADD_D020,{1U,4U,0U}}, +{ADD_D020,{2U,4U,0U}}, +{ADD_D020,{3U,4U,0U}}, +{ADD_D020,{4U,4U,0U}}, +{ADD_D020,{5U,4U,0U}}, +{ADD_D020,{6U,4U,0U}}, +{ADD_D020,{7U,4U,0U}}, +{ADD_D028,{0U,4U,0U}}, +{ADD_D028,{1U,4U,0U}}, +{ADD_D028,{2U,4U,0U}}, +{ADD_D028,{3U,4U,0U}}, +{ADD_D028,{4U,4U,0U}}, +{ADD_D028,{5U,4U,0U}}, +{ADD_D028,{6U,4U,0U}}, +{ADD_D028,{7U,4U,0U}}, +{ADD_D030,{0U,4U,0U}}, +{ADD_D030,{1U,4U,0U}}, +{ADD_D030,{2U,4U,0U}}, +{ADD_D030,{3U,4U,0U}}, +{ADD_D030,{4U,4U,0U}}, +{ADD_D030,{5U,4U,0U}}, +{ADD_D030,{6U,4U,0U}}, +{ADD_D030,{7U,4U,0U}}, +{ADD_D038,{0U,4U,0U}}, +{ADD_D039,{0U,4U,0U}}, +{ADD_D03A,{0U,4U,0U}}, +{ADD_D03B,{0U,4U,0U}}, +{ADD_D03C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D040,{0U,4U,0U}}, +{ADD_D040,{1U,4U,0U}}, +{ADD_D040,{2U,4U,0U}}, +{ADD_D040,{3U,4U,0U}}, +{ADD_D040,{4U,4U,0U}}, +{ADD_D040,{5U,4U,0U}}, +{ADD_D040,{6U,4U,0U}}, +{ADD_D040,{7U,4U,0U}}, +{ADD_D048,{0U,4U,0U}}, +{ADD_D048,{1U,4U,0U}}, +{ADD_D048,{2U,4U,0U}}, +{ADD_D048,{3U,4U,0U}}, +{ADD_D048,{4U,4U,0U}}, +{ADD_D048,{5U,4U,0U}}, +{ADD_D048,{6U,4U,0U}}, +{ADD_D048,{7U,4U,0U}}, +{ADD_D050,{0U,4U,0U}}, +{ADD_D050,{1U,4U,0U}}, +{ADD_D050,{2U,4U,0U}}, +{ADD_D050,{3U,4U,0U}}, +{ADD_D050,{4U,4U,0U}}, +{ADD_D050,{5U,4U,0U}}, +{ADD_D050,{6U,4U,0U}}, +{ADD_D050,{7U,4U,0U}}, +{ADD_D058,{0U,4U,0U}}, +{ADD_D058,{1U,4U,0U}}, +{ADD_D058,{2U,4U,0U}}, +{ADD_D058,{3U,4U,0U}}, +{ADD_D058,{4U,4U,0U}}, +{ADD_D058,{5U,4U,0U}}, +{ADD_D058,{6U,4U,0U}}, +{ADD_D058,{7U,4U,0U}}, +{ADD_D060,{0U,4U,0U}}, +{ADD_D060,{1U,4U,0U}}, +{ADD_D060,{2U,4U,0U}}, +{ADD_D060,{3U,4U,0U}}, +{ADD_D060,{4U,4U,0U}}, +{ADD_D060,{5U,4U,0U}}, +{ADD_D060,{6U,4U,0U}}, +{ADD_D060,{7U,4U,0U}}, +{ADD_D068,{0U,4U,0U}}, +{ADD_D068,{1U,4U,0U}}, +{ADD_D068,{2U,4U,0U}}, +{ADD_D068,{3U,4U,0U}}, +{ADD_D068,{4U,4U,0U}}, +{ADD_D068,{5U,4U,0U}}, +{ADD_D068,{6U,4U,0U}}, +{ADD_D068,{7U,4U,0U}}, +{ADD_D070,{0U,4U,0U}}, +{ADD_D070,{1U,4U,0U}}, +{ADD_D070,{2U,4U,0U}}, +{ADD_D070,{3U,4U,0U}}, +{ADD_D070,{4U,4U,0U}}, +{ADD_D070,{5U,4U,0U}}, +{ADD_D070,{6U,4U,0U}}, +{ADD_D070,{7U,4U,0U}}, +{ADD_D078,{0U,4U,0U}}, +{ADD_D079,{0U,4U,0U}}, +{ADD_D07A,{0U,4U,0U}}, +{ADD_D07B,{0U,4U,0U}}, +{ADD_D07C,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D080,{0U,4U,0U}}, +{ADD_D080,{1U,4U,0U}}, +{ADD_D080,{2U,4U,0U}}, +{ADD_D080,{3U,4U,0U}}, +{ADD_D080,{4U,4U,0U}}, +{ADD_D080,{5U,4U,0U}}, +{ADD_D080,{6U,4U,0U}}, +{ADD_D080,{7U,4U,0U}}, +{ADD_D088,{0U,4U,0U}}, +{ADD_D088,{1U,4U,0U}}, +{ADD_D088,{2U,4U,0U}}, +{ADD_D088,{3U,4U,0U}}, +{ADD_D088,{4U,4U,0U}}, +{ADD_D088,{5U,4U,0U}}, +{ADD_D088,{6U,4U,0U}}, +{ADD_D088,{7U,4U,0U}}, +{ADD_D090,{0U,4U,0U}}, +{ADD_D090,{1U,4U,0U}}, +{ADD_D090,{2U,4U,0U}}, +{ADD_D090,{3U,4U,0U}}, +{ADD_D090,{4U,4U,0U}}, +{ADD_D090,{5U,4U,0U}}, +{ADD_D090,{6U,4U,0U}}, +{ADD_D090,{7U,4U,0U}}, +{ADD_D098,{0U,4U,0U}}, +{ADD_D098,{1U,4U,0U}}, +{ADD_D098,{2U,4U,0U}}, +{ADD_D098,{3U,4U,0U}}, +{ADD_D098,{4U,4U,0U}}, +{ADD_D098,{5U,4U,0U}}, +{ADD_D098,{6U,4U,0U}}, +{ADD_D098,{7U,4U,0U}}, +{ADD_D0A0,{0U,4U,0U}}, +{ADD_D0A0,{1U,4U,0U}}, +{ADD_D0A0,{2U,4U,0U}}, +{ADD_D0A0,{3U,4U,0U}}, +{ADD_D0A0,{4U,4U,0U}}, +{ADD_D0A0,{5U,4U,0U}}, +{ADD_D0A0,{6U,4U,0U}}, +{ADD_D0A0,{7U,4U,0U}}, +{ADD_D0A8,{0U,4U,0U}}, +{ADD_D0A8,{1U,4U,0U}}, +{ADD_D0A8,{2U,4U,0U}}, +{ADD_D0A8,{3U,4U,0U}}, +{ADD_D0A8,{4U,4U,0U}}, +{ADD_D0A8,{5U,4U,0U}}, +{ADD_D0A8,{6U,4U,0U}}, +{ADD_D0A8,{7U,4U,0U}}, +{ADD_D0B0,{0U,4U,0U}}, +{ADD_D0B0,{1U,4U,0U}}, +{ADD_D0B0,{2U,4U,0U}}, +{ADD_D0B0,{3U,4U,0U}}, +{ADD_D0B0,{4U,4U,0U}}, +{ADD_D0B0,{5U,4U,0U}}, +{ADD_D0B0,{6U,4U,0U}}, +{ADD_D0B0,{7U,4U,0U}}, +{ADD_D0B8,{0U,4U,0U}}, +{ADD_D0B9,{0U,4U,0U}}, +{ADD_D0BA,{0U,4U,0U}}, +{ADD_D0BB,{0U,4U,0U}}, +{ADD_D0BC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D0C0,{0U,4U,0U}}, +{ADDA_D0C0,{1U,4U,0U}}, +{ADDA_D0C0,{2U,4U,0U}}, +{ADDA_D0C0,{3U,4U,0U}}, +{ADDA_D0C0,{4U,4U,0U}}, +{ADDA_D0C0,{5U,4U,0U}}, +{ADDA_D0C0,{6U,4U,0U}}, +{ADDA_D0C0,{7U,4U,0U}}, +{ADDA_D0C8,{0U,4U,0U}}, +{ADDA_D0C8,{1U,4U,0U}}, +{ADDA_D0C8,{2U,4U,0U}}, +{ADDA_D0C8,{3U,4U,0U}}, +{ADDA_D0C8,{4U,4U,0U}}, +{ADDA_D0C8,{5U,4U,0U}}, +{ADDA_D0C8,{6U,4U,0U}}, +{ADDA_D0C8,{7U,4U,0U}}, +{ADDA_D0D0,{0U,4U,0U}}, +{ADDA_D0D0,{1U,4U,0U}}, +{ADDA_D0D0,{2U,4U,0U}}, +{ADDA_D0D0,{3U,4U,0U}}, +{ADDA_D0D0,{4U,4U,0U}}, +{ADDA_D0D0,{5U,4U,0U}}, +{ADDA_D0D0,{6U,4U,0U}}, +{ADDA_D0D0,{7U,4U,0U}}, +{ADDA_D0D8,{0U,4U,0U}}, +{ADDA_D0D8,{1U,4U,0U}}, +{ADDA_D0D8,{2U,4U,0U}}, +{ADDA_D0D8,{3U,4U,0U}}, +{ADDA_D0D8,{4U,4U,0U}}, +{ADDA_D0D8,{5U,4U,0U}}, +{ADDA_D0D8,{6U,4U,0U}}, +{ADDA_D0D8,{7U,4U,0U}}, +{ADDA_D0E0,{0U,4U,0U}}, +{ADDA_D0E0,{1U,4U,0U}}, +{ADDA_D0E0,{2U,4U,0U}}, +{ADDA_D0E0,{3U,4U,0U}}, +{ADDA_D0E0,{4U,4U,0U}}, +{ADDA_D0E0,{5U,4U,0U}}, +{ADDA_D0E0,{6U,4U,0U}}, +{ADDA_D0E0,{7U,4U,0U}}, +{ADDA_D0E8,{0U,4U,0U}}, +{ADDA_D0E8,{1U,4U,0U}}, +{ADDA_D0E8,{2U,4U,0U}}, +{ADDA_D0E8,{3U,4U,0U}}, +{ADDA_D0E8,{4U,4U,0U}}, +{ADDA_D0E8,{5U,4U,0U}}, +{ADDA_D0E8,{6U,4U,0U}}, +{ADDA_D0E8,{7U,4U,0U}}, +{ADDA_D0F0,{0U,4U,0U}}, +{ADDA_D0F0,{1U,4U,0U}}, +{ADDA_D0F0,{2U,4U,0U}}, +{ADDA_D0F0,{3U,4U,0U}}, +{ADDA_D0F0,{4U,4U,0U}}, +{ADDA_D0F0,{5U,4U,0U}}, +{ADDA_D0F0,{6U,4U,0U}}, +{ADDA_D0F0,{7U,4U,0U}}, +{ADDA_D0F8,{0U,4U,0U}}, +{ADDA_D0F9,{0U,4U,0U}}, +{ADDA_D0FA,{0U,4U,0U}}, +{ADDA_D0FB,{0U,4U,0U}}, +{ADDA_D0FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D100,{0U,4U,0U}}, +{ADDX_D100,{1U,4U,0U}}, +{ADDX_D100,{2U,4U,0U}}, +{ADDX_D100,{3U,4U,0U}}, +{ADDX_D100,{4U,4U,0U}}, +{ADDX_D100,{5U,4U,0U}}, +{ADDX_D100,{6U,4U,0U}}, +{ADDX_D100,{7U,4U,0U}}, +{ADDX_D108,{0U,4U,0U}}, +{ADDX_D108,{1U,4U,0U}}, +{ADDX_D108,{2U,4U,0U}}, +{ADDX_D108,{3U,4U,0U}}, +{ADDX_D108,{4U,4U,0U}}, +{ADDX_D108,{5U,4U,0U}}, +{ADDX_D108,{6U,4U,0U}}, +{ADDX_D108,{7U,4U,0U}}, +{ADD_D110,{0U,4U,0U}}, +{ADD_D110,{1U,4U,0U}}, +{ADD_D110,{2U,4U,0U}}, +{ADD_D110,{3U,4U,0U}}, +{ADD_D110,{4U,4U,0U}}, +{ADD_D110,{5U,4U,0U}}, +{ADD_D110,{6U,4U,0U}}, +{ADD_D110,{7U,4U,0U}}, +{ADD_D118,{0U,4U,0U}}, +{ADD_D118,{1U,4U,0U}}, +{ADD_D118,{2U,4U,0U}}, +{ADD_D118,{3U,4U,0U}}, +{ADD_D118,{4U,4U,0U}}, +{ADD_D118,{5U,4U,0U}}, +{ADD_D118,{6U,4U,0U}}, +{ADD_D118,{7U,4U,0U}}, +{ADD_D120,{0U,4U,0U}}, +{ADD_D120,{1U,4U,0U}}, +{ADD_D120,{2U,4U,0U}}, +{ADD_D120,{3U,4U,0U}}, +{ADD_D120,{4U,4U,0U}}, +{ADD_D120,{5U,4U,0U}}, +{ADD_D120,{6U,4U,0U}}, +{ADD_D120,{7U,4U,0U}}, +{ADD_D128,{0U,4U,0U}}, +{ADD_D128,{1U,4U,0U}}, +{ADD_D128,{2U,4U,0U}}, +{ADD_D128,{3U,4U,0U}}, +{ADD_D128,{4U,4U,0U}}, +{ADD_D128,{5U,4U,0U}}, +{ADD_D128,{6U,4U,0U}}, +{ADD_D128,{7U,4U,0U}}, +{ADD_D130,{0U,4U,0U}}, +{ADD_D130,{1U,4U,0U}}, +{ADD_D130,{2U,4U,0U}}, +{ADD_D130,{3U,4U,0U}}, +{ADD_D130,{4U,4U,0U}}, +{ADD_D130,{5U,4U,0U}}, +{ADD_D130,{6U,4U,0U}}, +{ADD_D130,{7U,4U,0U}}, +{ADD_D138,{0U,4U,0U}}, +{ADD_D139,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D140,{0U,4U,0U}}, +{ADDX_D140,{1U,4U,0U}}, +{ADDX_D140,{2U,4U,0U}}, +{ADDX_D140,{3U,4U,0U}}, +{ADDX_D140,{4U,4U,0U}}, +{ADDX_D140,{5U,4U,0U}}, +{ADDX_D140,{6U,4U,0U}}, +{ADDX_D140,{7U,4U,0U}}, +{ADDX_D148,{0U,4U,0U}}, +{ADDX_D148,{1U,4U,0U}}, +{ADDX_D148,{2U,4U,0U}}, +{ADDX_D148,{3U,4U,0U}}, +{ADDX_D148,{4U,4U,0U}}, +{ADDX_D148,{5U,4U,0U}}, +{ADDX_D148,{6U,4U,0U}}, +{ADDX_D148,{7U,4U,0U}}, +{ADD_D150,{0U,4U,0U}}, +{ADD_D150,{1U,4U,0U}}, +{ADD_D150,{2U,4U,0U}}, +{ADD_D150,{3U,4U,0U}}, +{ADD_D150,{4U,4U,0U}}, +{ADD_D150,{5U,4U,0U}}, +{ADD_D150,{6U,4U,0U}}, +{ADD_D150,{7U,4U,0U}}, +{ADD_D158,{0U,4U,0U}}, +{ADD_D158,{1U,4U,0U}}, +{ADD_D158,{2U,4U,0U}}, +{ADD_D158,{3U,4U,0U}}, +{ADD_D158,{4U,4U,0U}}, +{ADD_D158,{5U,4U,0U}}, +{ADD_D158,{6U,4U,0U}}, +{ADD_D158,{7U,4U,0U}}, +{ADD_D160,{0U,4U,0U}}, +{ADD_D160,{1U,4U,0U}}, +{ADD_D160,{2U,4U,0U}}, +{ADD_D160,{3U,4U,0U}}, +{ADD_D160,{4U,4U,0U}}, +{ADD_D160,{5U,4U,0U}}, +{ADD_D160,{6U,4U,0U}}, +{ADD_D160,{7U,4U,0U}}, +{ADD_D168,{0U,4U,0U}}, +{ADD_D168,{1U,4U,0U}}, +{ADD_D168,{2U,4U,0U}}, +{ADD_D168,{3U,4U,0U}}, +{ADD_D168,{4U,4U,0U}}, +{ADD_D168,{5U,4U,0U}}, +{ADD_D168,{6U,4U,0U}}, +{ADD_D168,{7U,4U,0U}}, +{ADD_D170,{0U,4U,0U}}, +{ADD_D170,{1U,4U,0U}}, +{ADD_D170,{2U,4U,0U}}, +{ADD_D170,{3U,4U,0U}}, +{ADD_D170,{4U,4U,0U}}, +{ADD_D170,{5U,4U,0U}}, +{ADD_D170,{6U,4U,0U}}, +{ADD_D170,{7U,4U,0U}}, +{ADD_D178,{0U,4U,0U}}, +{ADD_D179,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D180,{0U,4U,0U}}, +{ADDX_D180,{1U,4U,0U}}, +{ADDX_D180,{2U,4U,0U}}, +{ADDX_D180,{3U,4U,0U}}, +{ADDX_D180,{4U,4U,0U}}, +{ADDX_D180,{5U,4U,0U}}, +{ADDX_D180,{6U,4U,0U}}, +{ADDX_D180,{7U,4U,0U}}, +{ADDX_D188,{0U,4U,0U}}, +{ADDX_D188,{1U,4U,0U}}, +{ADDX_D188,{2U,4U,0U}}, +{ADDX_D188,{3U,4U,0U}}, +{ADDX_D188,{4U,4U,0U}}, +{ADDX_D188,{5U,4U,0U}}, +{ADDX_D188,{6U,4U,0U}}, +{ADDX_D188,{7U,4U,0U}}, +{ADD_D190,{0U,4U,0U}}, +{ADD_D190,{1U,4U,0U}}, +{ADD_D190,{2U,4U,0U}}, +{ADD_D190,{3U,4U,0U}}, +{ADD_D190,{4U,4U,0U}}, +{ADD_D190,{5U,4U,0U}}, +{ADD_D190,{6U,4U,0U}}, +{ADD_D190,{7U,4U,0U}}, +{ADD_D198,{0U,4U,0U}}, +{ADD_D198,{1U,4U,0U}}, +{ADD_D198,{2U,4U,0U}}, +{ADD_D198,{3U,4U,0U}}, +{ADD_D198,{4U,4U,0U}}, +{ADD_D198,{5U,4U,0U}}, +{ADD_D198,{6U,4U,0U}}, +{ADD_D198,{7U,4U,0U}}, +{ADD_D1A0,{0U,4U,0U}}, +{ADD_D1A0,{1U,4U,0U}}, +{ADD_D1A0,{2U,4U,0U}}, +{ADD_D1A0,{3U,4U,0U}}, +{ADD_D1A0,{4U,4U,0U}}, +{ADD_D1A0,{5U,4U,0U}}, +{ADD_D1A0,{6U,4U,0U}}, +{ADD_D1A0,{7U,4U,0U}}, +{ADD_D1A8,{0U,4U,0U}}, +{ADD_D1A8,{1U,4U,0U}}, +{ADD_D1A8,{2U,4U,0U}}, +{ADD_D1A8,{3U,4U,0U}}, +{ADD_D1A8,{4U,4U,0U}}, +{ADD_D1A8,{5U,4U,0U}}, +{ADD_D1A8,{6U,4U,0U}}, +{ADD_D1A8,{7U,4U,0U}}, +{ADD_D1B0,{0U,4U,0U}}, +{ADD_D1B0,{1U,4U,0U}}, +{ADD_D1B0,{2U,4U,0U}}, +{ADD_D1B0,{3U,4U,0U}}, +{ADD_D1B0,{4U,4U,0U}}, +{ADD_D1B0,{5U,4U,0U}}, +{ADD_D1B0,{6U,4U,0U}}, +{ADD_D1B0,{7U,4U,0U}}, +{ADD_D1B8,{0U,4U,0U}}, +{ADD_D1B9,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D1C0,{0U,4U,0U}}, +{ADDA_D1C0,{1U,4U,0U}}, +{ADDA_D1C0,{2U,4U,0U}}, +{ADDA_D1C0,{3U,4U,0U}}, +{ADDA_D1C0,{4U,4U,0U}}, +{ADDA_D1C0,{5U,4U,0U}}, +{ADDA_D1C0,{6U,4U,0U}}, +{ADDA_D1C0,{7U,4U,0U}}, +{ADDA_D1C8,{0U,4U,0U}}, +{ADDA_D1C8,{1U,4U,0U}}, +{ADDA_D1C8,{2U,4U,0U}}, +{ADDA_D1C8,{3U,4U,0U}}, +{ADDA_D1C8,{4U,4U,0U}}, +{ADDA_D1C8,{5U,4U,0U}}, +{ADDA_D1C8,{6U,4U,0U}}, +{ADDA_D1C8,{7U,4U,0U}}, +{ADDA_D1D0,{0U,4U,0U}}, +{ADDA_D1D0,{1U,4U,0U}}, +{ADDA_D1D0,{2U,4U,0U}}, +{ADDA_D1D0,{3U,4U,0U}}, +{ADDA_D1D0,{4U,4U,0U}}, +{ADDA_D1D0,{5U,4U,0U}}, +{ADDA_D1D0,{6U,4U,0U}}, +{ADDA_D1D0,{7U,4U,0U}}, +{ADDA_D1D8,{0U,4U,0U}}, +{ADDA_D1D8,{1U,4U,0U}}, +{ADDA_D1D8,{2U,4U,0U}}, +{ADDA_D1D8,{3U,4U,0U}}, +{ADDA_D1D8,{4U,4U,0U}}, +{ADDA_D1D8,{5U,4U,0U}}, +{ADDA_D1D8,{6U,4U,0U}}, +{ADDA_D1D8,{7U,4U,0U}}, +{ADDA_D1E0,{0U,4U,0U}}, +{ADDA_D1E0,{1U,4U,0U}}, +{ADDA_D1E0,{2U,4U,0U}}, +{ADDA_D1E0,{3U,4U,0U}}, +{ADDA_D1E0,{4U,4U,0U}}, +{ADDA_D1E0,{5U,4U,0U}}, +{ADDA_D1E0,{6U,4U,0U}}, +{ADDA_D1E0,{7U,4U,0U}}, +{ADDA_D1E8,{0U,4U,0U}}, +{ADDA_D1E8,{1U,4U,0U}}, +{ADDA_D1E8,{2U,4U,0U}}, +{ADDA_D1E8,{3U,4U,0U}}, +{ADDA_D1E8,{4U,4U,0U}}, +{ADDA_D1E8,{5U,4U,0U}}, +{ADDA_D1E8,{6U,4U,0U}}, +{ADDA_D1E8,{7U,4U,0U}}, +{ADDA_D1F0,{0U,4U,0U}}, +{ADDA_D1F0,{1U,4U,0U}}, +{ADDA_D1F0,{2U,4U,0U}}, +{ADDA_D1F0,{3U,4U,0U}}, +{ADDA_D1F0,{4U,4U,0U}}, +{ADDA_D1F0,{5U,4U,0U}}, +{ADDA_D1F0,{6U,4U,0U}}, +{ADDA_D1F0,{7U,4U,0U}}, +{ADDA_D1F8,{0U,4U,0U}}, +{ADDA_D1F9,{0U,4U,0U}}, +{ADDA_D1FA,{0U,4U,0U}}, +{ADDA_D1FB,{0U,4U,0U}}, +{ADDA_D1FC,{0U,4U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D000,{0U,5U,0U}}, +{ADD_D000,{1U,5U,0U}}, +{ADD_D000,{2U,5U,0U}}, +{ADD_D000,{3U,5U,0U}}, +{ADD_D000,{4U,5U,0U}}, +{ADD_D000,{5U,5U,0U}}, +{ADD_D000,{6U,5U,0U}}, +{ADD_D000,{7U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D010,{0U,5U,0U}}, +{ADD_D010,{1U,5U,0U}}, +{ADD_D010,{2U,5U,0U}}, +{ADD_D010,{3U,5U,0U}}, +{ADD_D010,{4U,5U,0U}}, +{ADD_D010,{5U,5U,0U}}, +{ADD_D010,{6U,5U,0U}}, +{ADD_D010,{7U,5U,0U}}, +{ADD_D018,{0U,5U,0U}}, +{ADD_D018,{1U,5U,0U}}, +{ADD_D018,{2U,5U,0U}}, +{ADD_D018,{3U,5U,0U}}, +{ADD_D018,{4U,5U,0U}}, +{ADD_D018,{5U,5U,0U}}, +{ADD_D018,{6U,5U,0U}}, +{ADD_D018,{7U,5U,0U}}, +{ADD_D020,{0U,5U,0U}}, +{ADD_D020,{1U,5U,0U}}, +{ADD_D020,{2U,5U,0U}}, +{ADD_D020,{3U,5U,0U}}, +{ADD_D020,{4U,5U,0U}}, +{ADD_D020,{5U,5U,0U}}, +{ADD_D020,{6U,5U,0U}}, +{ADD_D020,{7U,5U,0U}}, +{ADD_D028,{0U,5U,0U}}, +{ADD_D028,{1U,5U,0U}}, +{ADD_D028,{2U,5U,0U}}, +{ADD_D028,{3U,5U,0U}}, +{ADD_D028,{4U,5U,0U}}, +{ADD_D028,{5U,5U,0U}}, +{ADD_D028,{6U,5U,0U}}, +{ADD_D028,{7U,5U,0U}}, +{ADD_D030,{0U,5U,0U}}, +{ADD_D030,{1U,5U,0U}}, +{ADD_D030,{2U,5U,0U}}, +{ADD_D030,{3U,5U,0U}}, +{ADD_D030,{4U,5U,0U}}, +{ADD_D030,{5U,5U,0U}}, +{ADD_D030,{6U,5U,0U}}, +{ADD_D030,{7U,5U,0U}}, +{ADD_D038,{0U,5U,0U}}, +{ADD_D039,{0U,5U,0U}}, +{ADD_D03A,{0U,5U,0U}}, +{ADD_D03B,{0U,5U,0U}}, +{ADD_D03C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D040,{0U,5U,0U}}, +{ADD_D040,{1U,5U,0U}}, +{ADD_D040,{2U,5U,0U}}, +{ADD_D040,{3U,5U,0U}}, +{ADD_D040,{4U,5U,0U}}, +{ADD_D040,{5U,5U,0U}}, +{ADD_D040,{6U,5U,0U}}, +{ADD_D040,{7U,5U,0U}}, +{ADD_D048,{0U,5U,0U}}, +{ADD_D048,{1U,5U,0U}}, +{ADD_D048,{2U,5U,0U}}, +{ADD_D048,{3U,5U,0U}}, +{ADD_D048,{4U,5U,0U}}, +{ADD_D048,{5U,5U,0U}}, +{ADD_D048,{6U,5U,0U}}, +{ADD_D048,{7U,5U,0U}}, +{ADD_D050,{0U,5U,0U}}, +{ADD_D050,{1U,5U,0U}}, +{ADD_D050,{2U,5U,0U}}, +{ADD_D050,{3U,5U,0U}}, +{ADD_D050,{4U,5U,0U}}, +{ADD_D050,{5U,5U,0U}}, +{ADD_D050,{6U,5U,0U}}, +{ADD_D050,{7U,5U,0U}}, +{ADD_D058,{0U,5U,0U}}, +{ADD_D058,{1U,5U,0U}}, +{ADD_D058,{2U,5U,0U}}, +{ADD_D058,{3U,5U,0U}}, +{ADD_D058,{4U,5U,0U}}, +{ADD_D058,{5U,5U,0U}}, +{ADD_D058,{6U,5U,0U}}, +{ADD_D058,{7U,5U,0U}}, +{ADD_D060,{0U,5U,0U}}, +{ADD_D060,{1U,5U,0U}}, +{ADD_D060,{2U,5U,0U}}, +{ADD_D060,{3U,5U,0U}}, +{ADD_D060,{4U,5U,0U}}, +{ADD_D060,{5U,5U,0U}}, +{ADD_D060,{6U,5U,0U}}, +{ADD_D060,{7U,5U,0U}}, +{ADD_D068,{0U,5U,0U}}, +{ADD_D068,{1U,5U,0U}}, +{ADD_D068,{2U,5U,0U}}, +{ADD_D068,{3U,5U,0U}}, +{ADD_D068,{4U,5U,0U}}, +{ADD_D068,{5U,5U,0U}}, +{ADD_D068,{6U,5U,0U}}, +{ADD_D068,{7U,5U,0U}}, +{ADD_D070,{0U,5U,0U}}, +{ADD_D070,{1U,5U,0U}}, +{ADD_D070,{2U,5U,0U}}, +{ADD_D070,{3U,5U,0U}}, +{ADD_D070,{4U,5U,0U}}, +{ADD_D070,{5U,5U,0U}}, +{ADD_D070,{6U,5U,0U}}, +{ADD_D070,{7U,5U,0U}}, +{ADD_D078,{0U,5U,0U}}, +{ADD_D079,{0U,5U,0U}}, +{ADD_D07A,{0U,5U,0U}}, +{ADD_D07B,{0U,5U,0U}}, +{ADD_D07C,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D080,{0U,5U,0U}}, +{ADD_D080,{1U,5U,0U}}, +{ADD_D080,{2U,5U,0U}}, +{ADD_D080,{3U,5U,0U}}, +{ADD_D080,{4U,5U,0U}}, +{ADD_D080,{5U,5U,0U}}, +{ADD_D080,{6U,5U,0U}}, +{ADD_D080,{7U,5U,0U}}, +{ADD_D088,{0U,5U,0U}}, +{ADD_D088,{1U,5U,0U}}, +{ADD_D088,{2U,5U,0U}}, +{ADD_D088,{3U,5U,0U}}, +{ADD_D088,{4U,5U,0U}}, +{ADD_D088,{5U,5U,0U}}, +{ADD_D088,{6U,5U,0U}}, +{ADD_D088,{7U,5U,0U}}, +{ADD_D090,{0U,5U,0U}}, +{ADD_D090,{1U,5U,0U}}, +{ADD_D090,{2U,5U,0U}}, +{ADD_D090,{3U,5U,0U}}, +{ADD_D090,{4U,5U,0U}}, +{ADD_D090,{5U,5U,0U}}, +{ADD_D090,{6U,5U,0U}}, +{ADD_D090,{7U,5U,0U}}, +{ADD_D098,{0U,5U,0U}}, +{ADD_D098,{1U,5U,0U}}, +{ADD_D098,{2U,5U,0U}}, +{ADD_D098,{3U,5U,0U}}, +{ADD_D098,{4U,5U,0U}}, +{ADD_D098,{5U,5U,0U}}, +{ADD_D098,{6U,5U,0U}}, +{ADD_D098,{7U,5U,0U}}, +{ADD_D0A0,{0U,5U,0U}}, +{ADD_D0A0,{1U,5U,0U}}, +{ADD_D0A0,{2U,5U,0U}}, +{ADD_D0A0,{3U,5U,0U}}, +{ADD_D0A0,{4U,5U,0U}}, +{ADD_D0A0,{5U,5U,0U}}, +{ADD_D0A0,{6U,5U,0U}}, +{ADD_D0A0,{7U,5U,0U}}, +{ADD_D0A8,{0U,5U,0U}}, +{ADD_D0A8,{1U,5U,0U}}, +{ADD_D0A8,{2U,5U,0U}}, +{ADD_D0A8,{3U,5U,0U}}, +{ADD_D0A8,{4U,5U,0U}}, +{ADD_D0A8,{5U,5U,0U}}, +{ADD_D0A8,{6U,5U,0U}}, +{ADD_D0A8,{7U,5U,0U}}, +{ADD_D0B0,{0U,5U,0U}}, +{ADD_D0B0,{1U,5U,0U}}, +{ADD_D0B0,{2U,5U,0U}}, +{ADD_D0B0,{3U,5U,0U}}, +{ADD_D0B0,{4U,5U,0U}}, +{ADD_D0B0,{5U,5U,0U}}, +{ADD_D0B0,{6U,5U,0U}}, +{ADD_D0B0,{7U,5U,0U}}, +{ADD_D0B8,{0U,5U,0U}}, +{ADD_D0B9,{0U,5U,0U}}, +{ADD_D0BA,{0U,5U,0U}}, +{ADD_D0BB,{0U,5U,0U}}, +{ADD_D0BC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D0C0,{0U,5U,0U}}, +{ADDA_D0C0,{1U,5U,0U}}, +{ADDA_D0C0,{2U,5U,0U}}, +{ADDA_D0C0,{3U,5U,0U}}, +{ADDA_D0C0,{4U,5U,0U}}, +{ADDA_D0C0,{5U,5U,0U}}, +{ADDA_D0C0,{6U,5U,0U}}, +{ADDA_D0C0,{7U,5U,0U}}, +{ADDA_D0C8,{0U,5U,0U}}, +{ADDA_D0C8,{1U,5U,0U}}, +{ADDA_D0C8,{2U,5U,0U}}, +{ADDA_D0C8,{3U,5U,0U}}, +{ADDA_D0C8,{4U,5U,0U}}, +{ADDA_D0C8,{5U,5U,0U}}, +{ADDA_D0C8,{6U,5U,0U}}, +{ADDA_D0C8,{7U,5U,0U}}, +{ADDA_D0D0,{0U,5U,0U}}, +{ADDA_D0D0,{1U,5U,0U}}, +{ADDA_D0D0,{2U,5U,0U}}, +{ADDA_D0D0,{3U,5U,0U}}, +{ADDA_D0D0,{4U,5U,0U}}, +{ADDA_D0D0,{5U,5U,0U}}, +{ADDA_D0D0,{6U,5U,0U}}, +{ADDA_D0D0,{7U,5U,0U}}, +{ADDA_D0D8,{0U,5U,0U}}, +{ADDA_D0D8,{1U,5U,0U}}, +{ADDA_D0D8,{2U,5U,0U}}, +{ADDA_D0D8,{3U,5U,0U}}, +{ADDA_D0D8,{4U,5U,0U}}, +{ADDA_D0D8,{5U,5U,0U}}, +{ADDA_D0D8,{6U,5U,0U}}, +{ADDA_D0D8,{7U,5U,0U}}, +{ADDA_D0E0,{0U,5U,0U}}, +{ADDA_D0E0,{1U,5U,0U}}, +{ADDA_D0E0,{2U,5U,0U}}, +{ADDA_D0E0,{3U,5U,0U}}, +{ADDA_D0E0,{4U,5U,0U}}, +{ADDA_D0E0,{5U,5U,0U}}, +{ADDA_D0E0,{6U,5U,0U}}, +{ADDA_D0E0,{7U,5U,0U}}, +{ADDA_D0E8,{0U,5U,0U}}, +{ADDA_D0E8,{1U,5U,0U}}, +{ADDA_D0E8,{2U,5U,0U}}, +{ADDA_D0E8,{3U,5U,0U}}, +{ADDA_D0E8,{4U,5U,0U}}, +{ADDA_D0E8,{5U,5U,0U}}, +{ADDA_D0E8,{6U,5U,0U}}, +{ADDA_D0E8,{7U,5U,0U}}, +{ADDA_D0F0,{0U,5U,0U}}, +{ADDA_D0F0,{1U,5U,0U}}, +{ADDA_D0F0,{2U,5U,0U}}, +{ADDA_D0F0,{3U,5U,0U}}, +{ADDA_D0F0,{4U,5U,0U}}, +{ADDA_D0F0,{5U,5U,0U}}, +{ADDA_D0F0,{6U,5U,0U}}, +{ADDA_D0F0,{7U,5U,0U}}, +{ADDA_D0F8,{0U,5U,0U}}, +{ADDA_D0F9,{0U,5U,0U}}, +{ADDA_D0FA,{0U,5U,0U}}, +{ADDA_D0FB,{0U,5U,0U}}, +{ADDA_D0FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D100,{0U,5U,0U}}, +{ADDX_D100,{1U,5U,0U}}, +{ADDX_D100,{2U,5U,0U}}, +{ADDX_D100,{3U,5U,0U}}, +{ADDX_D100,{4U,5U,0U}}, +{ADDX_D100,{5U,5U,0U}}, +{ADDX_D100,{6U,5U,0U}}, +{ADDX_D100,{7U,5U,0U}}, +{ADDX_D108,{0U,5U,0U}}, +{ADDX_D108,{1U,5U,0U}}, +{ADDX_D108,{2U,5U,0U}}, +{ADDX_D108,{3U,5U,0U}}, +{ADDX_D108,{4U,5U,0U}}, +{ADDX_D108,{5U,5U,0U}}, +{ADDX_D108,{6U,5U,0U}}, +{ADDX_D108,{7U,5U,0U}}, +{ADD_D110,{0U,5U,0U}}, +{ADD_D110,{1U,5U,0U}}, +{ADD_D110,{2U,5U,0U}}, +{ADD_D110,{3U,5U,0U}}, +{ADD_D110,{4U,5U,0U}}, +{ADD_D110,{5U,5U,0U}}, +{ADD_D110,{6U,5U,0U}}, +{ADD_D110,{7U,5U,0U}}, +{ADD_D118,{0U,5U,0U}}, +{ADD_D118,{1U,5U,0U}}, +{ADD_D118,{2U,5U,0U}}, +{ADD_D118,{3U,5U,0U}}, +{ADD_D118,{4U,5U,0U}}, +{ADD_D118,{5U,5U,0U}}, +{ADD_D118,{6U,5U,0U}}, +{ADD_D118,{7U,5U,0U}}, +{ADD_D120,{0U,5U,0U}}, +{ADD_D120,{1U,5U,0U}}, +{ADD_D120,{2U,5U,0U}}, +{ADD_D120,{3U,5U,0U}}, +{ADD_D120,{4U,5U,0U}}, +{ADD_D120,{5U,5U,0U}}, +{ADD_D120,{6U,5U,0U}}, +{ADD_D120,{7U,5U,0U}}, +{ADD_D128,{0U,5U,0U}}, +{ADD_D128,{1U,5U,0U}}, +{ADD_D128,{2U,5U,0U}}, +{ADD_D128,{3U,5U,0U}}, +{ADD_D128,{4U,5U,0U}}, +{ADD_D128,{5U,5U,0U}}, +{ADD_D128,{6U,5U,0U}}, +{ADD_D128,{7U,5U,0U}}, +{ADD_D130,{0U,5U,0U}}, +{ADD_D130,{1U,5U,0U}}, +{ADD_D130,{2U,5U,0U}}, +{ADD_D130,{3U,5U,0U}}, +{ADD_D130,{4U,5U,0U}}, +{ADD_D130,{5U,5U,0U}}, +{ADD_D130,{6U,5U,0U}}, +{ADD_D130,{7U,5U,0U}}, +{ADD_D138,{0U,5U,0U}}, +{ADD_D139,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D140,{0U,5U,0U}}, +{ADDX_D140,{1U,5U,0U}}, +{ADDX_D140,{2U,5U,0U}}, +{ADDX_D140,{3U,5U,0U}}, +{ADDX_D140,{4U,5U,0U}}, +{ADDX_D140,{5U,5U,0U}}, +{ADDX_D140,{6U,5U,0U}}, +{ADDX_D140,{7U,5U,0U}}, +{ADDX_D148,{0U,5U,0U}}, +{ADDX_D148,{1U,5U,0U}}, +{ADDX_D148,{2U,5U,0U}}, +{ADDX_D148,{3U,5U,0U}}, +{ADDX_D148,{4U,5U,0U}}, +{ADDX_D148,{5U,5U,0U}}, +{ADDX_D148,{6U,5U,0U}}, +{ADDX_D148,{7U,5U,0U}}, +{ADD_D150,{0U,5U,0U}}, +{ADD_D150,{1U,5U,0U}}, +{ADD_D150,{2U,5U,0U}}, +{ADD_D150,{3U,5U,0U}}, +{ADD_D150,{4U,5U,0U}}, +{ADD_D150,{5U,5U,0U}}, +{ADD_D150,{6U,5U,0U}}, +{ADD_D150,{7U,5U,0U}}, +{ADD_D158,{0U,5U,0U}}, +{ADD_D158,{1U,5U,0U}}, +{ADD_D158,{2U,5U,0U}}, +{ADD_D158,{3U,5U,0U}}, +{ADD_D158,{4U,5U,0U}}, +{ADD_D158,{5U,5U,0U}}, +{ADD_D158,{6U,5U,0U}}, +{ADD_D158,{7U,5U,0U}}, +{ADD_D160,{0U,5U,0U}}, +{ADD_D160,{1U,5U,0U}}, +{ADD_D160,{2U,5U,0U}}, +{ADD_D160,{3U,5U,0U}}, +{ADD_D160,{4U,5U,0U}}, +{ADD_D160,{5U,5U,0U}}, +{ADD_D160,{6U,5U,0U}}, +{ADD_D160,{7U,5U,0U}}, +{ADD_D168,{0U,5U,0U}}, +{ADD_D168,{1U,5U,0U}}, +{ADD_D168,{2U,5U,0U}}, +{ADD_D168,{3U,5U,0U}}, +{ADD_D168,{4U,5U,0U}}, +{ADD_D168,{5U,5U,0U}}, +{ADD_D168,{6U,5U,0U}}, +{ADD_D168,{7U,5U,0U}}, +{ADD_D170,{0U,5U,0U}}, +{ADD_D170,{1U,5U,0U}}, +{ADD_D170,{2U,5U,0U}}, +{ADD_D170,{3U,5U,0U}}, +{ADD_D170,{4U,5U,0U}}, +{ADD_D170,{5U,5U,0U}}, +{ADD_D170,{6U,5U,0U}}, +{ADD_D170,{7U,5U,0U}}, +{ADD_D178,{0U,5U,0U}}, +{ADD_D179,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D180,{0U,5U,0U}}, +{ADDX_D180,{1U,5U,0U}}, +{ADDX_D180,{2U,5U,0U}}, +{ADDX_D180,{3U,5U,0U}}, +{ADDX_D180,{4U,5U,0U}}, +{ADDX_D180,{5U,5U,0U}}, +{ADDX_D180,{6U,5U,0U}}, +{ADDX_D180,{7U,5U,0U}}, +{ADDX_D188,{0U,5U,0U}}, +{ADDX_D188,{1U,5U,0U}}, +{ADDX_D188,{2U,5U,0U}}, +{ADDX_D188,{3U,5U,0U}}, +{ADDX_D188,{4U,5U,0U}}, +{ADDX_D188,{5U,5U,0U}}, +{ADDX_D188,{6U,5U,0U}}, +{ADDX_D188,{7U,5U,0U}}, +{ADD_D190,{0U,5U,0U}}, +{ADD_D190,{1U,5U,0U}}, +{ADD_D190,{2U,5U,0U}}, +{ADD_D190,{3U,5U,0U}}, +{ADD_D190,{4U,5U,0U}}, +{ADD_D190,{5U,5U,0U}}, +{ADD_D190,{6U,5U,0U}}, +{ADD_D190,{7U,5U,0U}}, +{ADD_D198,{0U,5U,0U}}, +{ADD_D198,{1U,5U,0U}}, +{ADD_D198,{2U,5U,0U}}, +{ADD_D198,{3U,5U,0U}}, +{ADD_D198,{4U,5U,0U}}, +{ADD_D198,{5U,5U,0U}}, +{ADD_D198,{6U,5U,0U}}, +{ADD_D198,{7U,5U,0U}}, +{ADD_D1A0,{0U,5U,0U}}, +{ADD_D1A0,{1U,5U,0U}}, +{ADD_D1A0,{2U,5U,0U}}, +{ADD_D1A0,{3U,5U,0U}}, +{ADD_D1A0,{4U,5U,0U}}, +{ADD_D1A0,{5U,5U,0U}}, +{ADD_D1A0,{6U,5U,0U}}, +{ADD_D1A0,{7U,5U,0U}}, +{ADD_D1A8,{0U,5U,0U}}, +{ADD_D1A8,{1U,5U,0U}}, +{ADD_D1A8,{2U,5U,0U}}, +{ADD_D1A8,{3U,5U,0U}}, +{ADD_D1A8,{4U,5U,0U}}, +{ADD_D1A8,{5U,5U,0U}}, +{ADD_D1A8,{6U,5U,0U}}, +{ADD_D1A8,{7U,5U,0U}}, +{ADD_D1B0,{0U,5U,0U}}, +{ADD_D1B0,{1U,5U,0U}}, +{ADD_D1B0,{2U,5U,0U}}, +{ADD_D1B0,{3U,5U,0U}}, +{ADD_D1B0,{4U,5U,0U}}, +{ADD_D1B0,{5U,5U,0U}}, +{ADD_D1B0,{6U,5U,0U}}, +{ADD_D1B0,{7U,5U,0U}}, +{ADD_D1B8,{0U,5U,0U}}, +{ADD_D1B9,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D1C0,{0U,5U,0U}}, +{ADDA_D1C0,{1U,5U,0U}}, +{ADDA_D1C0,{2U,5U,0U}}, +{ADDA_D1C0,{3U,5U,0U}}, +{ADDA_D1C0,{4U,5U,0U}}, +{ADDA_D1C0,{5U,5U,0U}}, +{ADDA_D1C0,{6U,5U,0U}}, +{ADDA_D1C0,{7U,5U,0U}}, +{ADDA_D1C8,{0U,5U,0U}}, +{ADDA_D1C8,{1U,5U,0U}}, +{ADDA_D1C8,{2U,5U,0U}}, +{ADDA_D1C8,{3U,5U,0U}}, +{ADDA_D1C8,{4U,5U,0U}}, +{ADDA_D1C8,{5U,5U,0U}}, +{ADDA_D1C8,{6U,5U,0U}}, +{ADDA_D1C8,{7U,5U,0U}}, +{ADDA_D1D0,{0U,5U,0U}}, +{ADDA_D1D0,{1U,5U,0U}}, +{ADDA_D1D0,{2U,5U,0U}}, +{ADDA_D1D0,{3U,5U,0U}}, +{ADDA_D1D0,{4U,5U,0U}}, +{ADDA_D1D0,{5U,5U,0U}}, +{ADDA_D1D0,{6U,5U,0U}}, +{ADDA_D1D0,{7U,5U,0U}}, +{ADDA_D1D8,{0U,5U,0U}}, +{ADDA_D1D8,{1U,5U,0U}}, +{ADDA_D1D8,{2U,5U,0U}}, +{ADDA_D1D8,{3U,5U,0U}}, +{ADDA_D1D8,{4U,5U,0U}}, +{ADDA_D1D8,{5U,5U,0U}}, +{ADDA_D1D8,{6U,5U,0U}}, +{ADDA_D1D8,{7U,5U,0U}}, +{ADDA_D1E0,{0U,5U,0U}}, +{ADDA_D1E0,{1U,5U,0U}}, +{ADDA_D1E0,{2U,5U,0U}}, +{ADDA_D1E0,{3U,5U,0U}}, +{ADDA_D1E0,{4U,5U,0U}}, +{ADDA_D1E0,{5U,5U,0U}}, +{ADDA_D1E0,{6U,5U,0U}}, +{ADDA_D1E0,{7U,5U,0U}}, +{ADDA_D1E8,{0U,5U,0U}}, +{ADDA_D1E8,{1U,5U,0U}}, +{ADDA_D1E8,{2U,5U,0U}}, +{ADDA_D1E8,{3U,5U,0U}}, +{ADDA_D1E8,{4U,5U,0U}}, +{ADDA_D1E8,{5U,5U,0U}}, +{ADDA_D1E8,{6U,5U,0U}}, +{ADDA_D1E8,{7U,5U,0U}}, +{ADDA_D1F0,{0U,5U,0U}}, +{ADDA_D1F0,{1U,5U,0U}}, +{ADDA_D1F0,{2U,5U,0U}}, +{ADDA_D1F0,{3U,5U,0U}}, +{ADDA_D1F0,{4U,5U,0U}}, +{ADDA_D1F0,{5U,5U,0U}}, +{ADDA_D1F0,{6U,5U,0U}}, +{ADDA_D1F0,{7U,5U,0U}}, +{ADDA_D1F8,{0U,5U,0U}}, +{ADDA_D1F9,{0U,5U,0U}}, +{ADDA_D1FA,{0U,5U,0U}}, +{ADDA_D1FB,{0U,5U,0U}}, +{ADDA_D1FC,{0U,5U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D000,{0U,6U,0U}}, +{ADD_D000,{1U,6U,0U}}, +{ADD_D000,{2U,6U,0U}}, +{ADD_D000,{3U,6U,0U}}, +{ADD_D000,{4U,6U,0U}}, +{ADD_D000,{5U,6U,0U}}, +{ADD_D000,{6U,6U,0U}}, +{ADD_D000,{7U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D010,{0U,6U,0U}}, +{ADD_D010,{1U,6U,0U}}, +{ADD_D010,{2U,6U,0U}}, +{ADD_D010,{3U,6U,0U}}, +{ADD_D010,{4U,6U,0U}}, +{ADD_D010,{5U,6U,0U}}, +{ADD_D010,{6U,6U,0U}}, +{ADD_D010,{7U,6U,0U}}, +{ADD_D018,{0U,6U,0U}}, +{ADD_D018,{1U,6U,0U}}, +{ADD_D018,{2U,6U,0U}}, +{ADD_D018,{3U,6U,0U}}, +{ADD_D018,{4U,6U,0U}}, +{ADD_D018,{5U,6U,0U}}, +{ADD_D018,{6U,6U,0U}}, +{ADD_D018,{7U,6U,0U}}, +{ADD_D020,{0U,6U,0U}}, +{ADD_D020,{1U,6U,0U}}, +{ADD_D020,{2U,6U,0U}}, +{ADD_D020,{3U,6U,0U}}, +{ADD_D020,{4U,6U,0U}}, +{ADD_D020,{5U,6U,0U}}, +{ADD_D020,{6U,6U,0U}}, +{ADD_D020,{7U,6U,0U}}, +{ADD_D028,{0U,6U,0U}}, +{ADD_D028,{1U,6U,0U}}, +{ADD_D028,{2U,6U,0U}}, +{ADD_D028,{3U,6U,0U}}, +{ADD_D028,{4U,6U,0U}}, +{ADD_D028,{5U,6U,0U}}, +{ADD_D028,{6U,6U,0U}}, +{ADD_D028,{7U,6U,0U}}, +{ADD_D030,{0U,6U,0U}}, +{ADD_D030,{1U,6U,0U}}, +{ADD_D030,{2U,6U,0U}}, +{ADD_D030,{3U,6U,0U}}, +{ADD_D030,{4U,6U,0U}}, +{ADD_D030,{5U,6U,0U}}, +{ADD_D030,{6U,6U,0U}}, +{ADD_D030,{7U,6U,0U}}, +{ADD_D038,{0U,6U,0U}}, +{ADD_D039,{0U,6U,0U}}, +{ADD_D03A,{0U,6U,0U}}, +{ADD_D03B,{0U,6U,0U}}, +{ADD_D03C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D040,{0U,6U,0U}}, +{ADD_D040,{1U,6U,0U}}, +{ADD_D040,{2U,6U,0U}}, +{ADD_D040,{3U,6U,0U}}, +{ADD_D040,{4U,6U,0U}}, +{ADD_D040,{5U,6U,0U}}, +{ADD_D040,{6U,6U,0U}}, +{ADD_D040,{7U,6U,0U}}, +{ADD_D048,{0U,6U,0U}}, +{ADD_D048,{1U,6U,0U}}, +{ADD_D048,{2U,6U,0U}}, +{ADD_D048,{3U,6U,0U}}, +{ADD_D048,{4U,6U,0U}}, +{ADD_D048,{5U,6U,0U}}, +{ADD_D048,{6U,6U,0U}}, +{ADD_D048,{7U,6U,0U}}, +{ADD_D050,{0U,6U,0U}}, +{ADD_D050,{1U,6U,0U}}, +{ADD_D050,{2U,6U,0U}}, +{ADD_D050,{3U,6U,0U}}, +{ADD_D050,{4U,6U,0U}}, +{ADD_D050,{5U,6U,0U}}, +{ADD_D050,{6U,6U,0U}}, +{ADD_D050,{7U,6U,0U}}, +{ADD_D058,{0U,6U,0U}}, +{ADD_D058,{1U,6U,0U}}, +{ADD_D058,{2U,6U,0U}}, +{ADD_D058,{3U,6U,0U}}, +{ADD_D058,{4U,6U,0U}}, +{ADD_D058,{5U,6U,0U}}, +{ADD_D058,{6U,6U,0U}}, +{ADD_D058,{7U,6U,0U}}, +{ADD_D060,{0U,6U,0U}}, +{ADD_D060,{1U,6U,0U}}, +{ADD_D060,{2U,6U,0U}}, +{ADD_D060,{3U,6U,0U}}, +{ADD_D060,{4U,6U,0U}}, +{ADD_D060,{5U,6U,0U}}, +{ADD_D060,{6U,6U,0U}}, +{ADD_D060,{7U,6U,0U}}, +{ADD_D068,{0U,6U,0U}}, +{ADD_D068,{1U,6U,0U}}, +{ADD_D068,{2U,6U,0U}}, +{ADD_D068,{3U,6U,0U}}, +{ADD_D068,{4U,6U,0U}}, +{ADD_D068,{5U,6U,0U}}, +{ADD_D068,{6U,6U,0U}}, +{ADD_D068,{7U,6U,0U}}, +{ADD_D070,{0U,6U,0U}}, +{ADD_D070,{1U,6U,0U}}, +{ADD_D070,{2U,6U,0U}}, +{ADD_D070,{3U,6U,0U}}, +{ADD_D070,{4U,6U,0U}}, +{ADD_D070,{5U,6U,0U}}, +{ADD_D070,{6U,6U,0U}}, +{ADD_D070,{7U,6U,0U}}, +{ADD_D078,{0U,6U,0U}}, +{ADD_D079,{0U,6U,0U}}, +{ADD_D07A,{0U,6U,0U}}, +{ADD_D07B,{0U,6U,0U}}, +{ADD_D07C,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D080,{0U,6U,0U}}, +{ADD_D080,{1U,6U,0U}}, +{ADD_D080,{2U,6U,0U}}, +{ADD_D080,{3U,6U,0U}}, +{ADD_D080,{4U,6U,0U}}, +{ADD_D080,{5U,6U,0U}}, +{ADD_D080,{6U,6U,0U}}, +{ADD_D080,{7U,6U,0U}}, +{ADD_D088,{0U,6U,0U}}, +{ADD_D088,{1U,6U,0U}}, +{ADD_D088,{2U,6U,0U}}, +{ADD_D088,{3U,6U,0U}}, +{ADD_D088,{4U,6U,0U}}, +{ADD_D088,{5U,6U,0U}}, +{ADD_D088,{6U,6U,0U}}, +{ADD_D088,{7U,6U,0U}}, +{ADD_D090,{0U,6U,0U}}, +{ADD_D090,{1U,6U,0U}}, +{ADD_D090,{2U,6U,0U}}, +{ADD_D090,{3U,6U,0U}}, +{ADD_D090,{4U,6U,0U}}, +{ADD_D090,{5U,6U,0U}}, +{ADD_D090,{6U,6U,0U}}, +{ADD_D090,{7U,6U,0U}}, +{ADD_D098,{0U,6U,0U}}, +{ADD_D098,{1U,6U,0U}}, +{ADD_D098,{2U,6U,0U}}, +{ADD_D098,{3U,6U,0U}}, +{ADD_D098,{4U,6U,0U}}, +{ADD_D098,{5U,6U,0U}}, +{ADD_D098,{6U,6U,0U}}, +{ADD_D098,{7U,6U,0U}}, +{ADD_D0A0,{0U,6U,0U}}, +{ADD_D0A0,{1U,6U,0U}}, +{ADD_D0A0,{2U,6U,0U}}, +{ADD_D0A0,{3U,6U,0U}}, +{ADD_D0A0,{4U,6U,0U}}, +{ADD_D0A0,{5U,6U,0U}}, +{ADD_D0A0,{6U,6U,0U}}, +{ADD_D0A0,{7U,6U,0U}}, +{ADD_D0A8,{0U,6U,0U}}, +{ADD_D0A8,{1U,6U,0U}}, +{ADD_D0A8,{2U,6U,0U}}, +{ADD_D0A8,{3U,6U,0U}}, +{ADD_D0A8,{4U,6U,0U}}, +{ADD_D0A8,{5U,6U,0U}}, +{ADD_D0A8,{6U,6U,0U}}, +{ADD_D0A8,{7U,6U,0U}}, +{ADD_D0B0,{0U,6U,0U}}, +{ADD_D0B0,{1U,6U,0U}}, +{ADD_D0B0,{2U,6U,0U}}, +{ADD_D0B0,{3U,6U,0U}}, +{ADD_D0B0,{4U,6U,0U}}, +{ADD_D0B0,{5U,6U,0U}}, +{ADD_D0B0,{6U,6U,0U}}, +{ADD_D0B0,{7U,6U,0U}}, +{ADD_D0B8,{0U,6U,0U}}, +{ADD_D0B9,{0U,6U,0U}}, +{ADD_D0BA,{0U,6U,0U}}, +{ADD_D0BB,{0U,6U,0U}}, +{ADD_D0BC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D0C0,{0U,6U,0U}}, +{ADDA_D0C0,{1U,6U,0U}}, +{ADDA_D0C0,{2U,6U,0U}}, +{ADDA_D0C0,{3U,6U,0U}}, +{ADDA_D0C0,{4U,6U,0U}}, +{ADDA_D0C0,{5U,6U,0U}}, +{ADDA_D0C0,{6U,6U,0U}}, +{ADDA_D0C0,{7U,6U,0U}}, +{ADDA_D0C8,{0U,6U,0U}}, +{ADDA_D0C8,{1U,6U,0U}}, +{ADDA_D0C8,{2U,6U,0U}}, +{ADDA_D0C8,{3U,6U,0U}}, +{ADDA_D0C8,{4U,6U,0U}}, +{ADDA_D0C8,{5U,6U,0U}}, +{ADDA_D0C8,{6U,6U,0U}}, +{ADDA_D0C8,{7U,6U,0U}}, +{ADDA_D0D0,{0U,6U,0U}}, +{ADDA_D0D0,{1U,6U,0U}}, +{ADDA_D0D0,{2U,6U,0U}}, +{ADDA_D0D0,{3U,6U,0U}}, +{ADDA_D0D0,{4U,6U,0U}}, +{ADDA_D0D0,{5U,6U,0U}}, +{ADDA_D0D0,{6U,6U,0U}}, +{ADDA_D0D0,{7U,6U,0U}}, +{ADDA_D0D8,{0U,6U,0U}}, +{ADDA_D0D8,{1U,6U,0U}}, +{ADDA_D0D8,{2U,6U,0U}}, +{ADDA_D0D8,{3U,6U,0U}}, +{ADDA_D0D8,{4U,6U,0U}}, +{ADDA_D0D8,{5U,6U,0U}}, +{ADDA_D0D8,{6U,6U,0U}}, +{ADDA_D0D8,{7U,6U,0U}}, +{ADDA_D0E0,{0U,6U,0U}}, +{ADDA_D0E0,{1U,6U,0U}}, +{ADDA_D0E0,{2U,6U,0U}}, +{ADDA_D0E0,{3U,6U,0U}}, +{ADDA_D0E0,{4U,6U,0U}}, +{ADDA_D0E0,{5U,6U,0U}}, +{ADDA_D0E0,{6U,6U,0U}}, +{ADDA_D0E0,{7U,6U,0U}}, +{ADDA_D0E8,{0U,6U,0U}}, +{ADDA_D0E8,{1U,6U,0U}}, +{ADDA_D0E8,{2U,6U,0U}}, +{ADDA_D0E8,{3U,6U,0U}}, +{ADDA_D0E8,{4U,6U,0U}}, +{ADDA_D0E8,{5U,6U,0U}}, +{ADDA_D0E8,{6U,6U,0U}}, +{ADDA_D0E8,{7U,6U,0U}}, +{ADDA_D0F0,{0U,6U,0U}}, +{ADDA_D0F0,{1U,6U,0U}}, +{ADDA_D0F0,{2U,6U,0U}}, +{ADDA_D0F0,{3U,6U,0U}}, +{ADDA_D0F0,{4U,6U,0U}}, +{ADDA_D0F0,{5U,6U,0U}}, +{ADDA_D0F0,{6U,6U,0U}}, +{ADDA_D0F0,{7U,6U,0U}}, +{ADDA_D0F8,{0U,6U,0U}}, +{ADDA_D0F9,{0U,6U,0U}}, +{ADDA_D0FA,{0U,6U,0U}}, +{ADDA_D0FB,{0U,6U,0U}}, +{ADDA_D0FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D100,{0U,6U,0U}}, +{ADDX_D100,{1U,6U,0U}}, +{ADDX_D100,{2U,6U,0U}}, +{ADDX_D100,{3U,6U,0U}}, +{ADDX_D100,{4U,6U,0U}}, +{ADDX_D100,{5U,6U,0U}}, +{ADDX_D100,{6U,6U,0U}}, +{ADDX_D100,{7U,6U,0U}}, +{ADDX_D108,{0U,6U,0U}}, +{ADDX_D108,{1U,6U,0U}}, +{ADDX_D108,{2U,6U,0U}}, +{ADDX_D108,{3U,6U,0U}}, +{ADDX_D108,{4U,6U,0U}}, +{ADDX_D108,{5U,6U,0U}}, +{ADDX_D108,{6U,6U,0U}}, +{ADDX_D108,{7U,6U,0U}}, +{ADD_D110,{0U,6U,0U}}, +{ADD_D110,{1U,6U,0U}}, +{ADD_D110,{2U,6U,0U}}, +{ADD_D110,{3U,6U,0U}}, +{ADD_D110,{4U,6U,0U}}, +{ADD_D110,{5U,6U,0U}}, +{ADD_D110,{6U,6U,0U}}, +{ADD_D110,{7U,6U,0U}}, +{ADD_D118,{0U,6U,0U}}, +{ADD_D118,{1U,6U,0U}}, +{ADD_D118,{2U,6U,0U}}, +{ADD_D118,{3U,6U,0U}}, +{ADD_D118,{4U,6U,0U}}, +{ADD_D118,{5U,6U,0U}}, +{ADD_D118,{6U,6U,0U}}, +{ADD_D118,{7U,6U,0U}}, +{ADD_D120,{0U,6U,0U}}, +{ADD_D120,{1U,6U,0U}}, +{ADD_D120,{2U,6U,0U}}, +{ADD_D120,{3U,6U,0U}}, +{ADD_D120,{4U,6U,0U}}, +{ADD_D120,{5U,6U,0U}}, +{ADD_D120,{6U,6U,0U}}, +{ADD_D120,{7U,6U,0U}}, +{ADD_D128,{0U,6U,0U}}, +{ADD_D128,{1U,6U,0U}}, +{ADD_D128,{2U,6U,0U}}, +{ADD_D128,{3U,6U,0U}}, +{ADD_D128,{4U,6U,0U}}, +{ADD_D128,{5U,6U,0U}}, +{ADD_D128,{6U,6U,0U}}, +{ADD_D128,{7U,6U,0U}}, +{ADD_D130,{0U,6U,0U}}, +{ADD_D130,{1U,6U,0U}}, +{ADD_D130,{2U,6U,0U}}, +{ADD_D130,{3U,6U,0U}}, +{ADD_D130,{4U,6U,0U}}, +{ADD_D130,{5U,6U,0U}}, +{ADD_D130,{6U,6U,0U}}, +{ADD_D130,{7U,6U,0U}}, +{ADD_D138,{0U,6U,0U}}, +{ADD_D139,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D140,{0U,6U,0U}}, +{ADDX_D140,{1U,6U,0U}}, +{ADDX_D140,{2U,6U,0U}}, +{ADDX_D140,{3U,6U,0U}}, +{ADDX_D140,{4U,6U,0U}}, +{ADDX_D140,{5U,6U,0U}}, +{ADDX_D140,{6U,6U,0U}}, +{ADDX_D140,{7U,6U,0U}}, +{ADDX_D148,{0U,6U,0U}}, +{ADDX_D148,{1U,6U,0U}}, +{ADDX_D148,{2U,6U,0U}}, +{ADDX_D148,{3U,6U,0U}}, +{ADDX_D148,{4U,6U,0U}}, +{ADDX_D148,{5U,6U,0U}}, +{ADDX_D148,{6U,6U,0U}}, +{ADDX_D148,{7U,6U,0U}}, +{ADD_D150,{0U,6U,0U}}, +{ADD_D150,{1U,6U,0U}}, +{ADD_D150,{2U,6U,0U}}, +{ADD_D150,{3U,6U,0U}}, +{ADD_D150,{4U,6U,0U}}, +{ADD_D150,{5U,6U,0U}}, +{ADD_D150,{6U,6U,0U}}, +{ADD_D150,{7U,6U,0U}}, +{ADD_D158,{0U,6U,0U}}, +{ADD_D158,{1U,6U,0U}}, +{ADD_D158,{2U,6U,0U}}, +{ADD_D158,{3U,6U,0U}}, +{ADD_D158,{4U,6U,0U}}, +{ADD_D158,{5U,6U,0U}}, +{ADD_D158,{6U,6U,0U}}, +{ADD_D158,{7U,6U,0U}}, +{ADD_D160,{0U,6U,0U}}, +{ADD_D160,{1U,6U,0U}}, +{ADD_D160,{2U,6U,0U}}, +{ADD_D160,{3U,6U,0U}}, +{ADD_D160,{4U,6U,0U}}, +{ADD_D160,{5U,6U,0U}}, +{ADD_D160,{6U,6U,0U}}, +{ADD_D160,{7U,6U,0U}}, +{ADD_D168,{0U,6U,0U}}, +{ADD_D168,{1U,6U,0U}}, +{ADD_D168,{2U,6U,0U}}, +{ADD_D168,{3U,6U,0U}}, +{ADD_D168,{4U,6U,0U}}, +{ADD_D168,{5U,6U,0U}}, +{ADD_D168,{6U,6U,0U}}, +{ADD_D168,{7U,6U,0U}}, +{ADD_D170,{0U,6U,0U}}, +{ADD_D170,{1U,6U,0U}}, +{ADD_D170,{2U,6U,0U}}, +{ADD_D170,{3U,6U,0U}}, +{ADD_D170,{4U,6U,0U}}, +{ADD_D170,{5U,6U,0U}}, +{ADD_D170,{6U,6U,0U}}, +{ADD_D170,{7U,6U,0U}}, +{ADD_D178,{0U,6U,0U}}, +{ADD_D179,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D180,{0U,6U,0U}}, +{ADDX_D180,{1U,6U,0U}}, +{ADDX_D180,{2U,6U,0U}}, +{ADDX_D180,{3U,6U,0U}}, +{ADDX_D180,{4U,6U,0U}}, +{ADDX_D180,{5U,6U,0U}}, +{ADDX_D180,{6U,6U,0U}}, +{ADDX_D180,{7U,6U,0U}}, +{ADDX_D188,{0U,6U,0U}}, +{ADDX_D188,{1U,6U,0U}}, +{ADDX_D188,{2U,6U,0U}}, +{ADDX_D188,{3U,6U,0U}}, +{ADDX_D188,{4U,6U,0U}}, +{ADDX_D188,{5U,6U,0U}}, +{ADDX_D188,{6U,6U,0U}}, +{ADDX_D188,{7U,6U,0U}}, +{ADD_D190,{0U,6U,0U}}, +{ADD_D190,{1U,6U,0U}}, +{ADD_D190,{2U,6U,0U}}, +{ADD_D190,{3U,6U,0U}}, +{ADD_D190,{4U,6U,0U}}, +{ADD_D190,{5U,6U,0U}}, +{ADD_D190,{6U,6U,0U}}, +{ADD_D190,{7U,6U,0U}}, +{ADD_D198,{0U,6U,0U}}, +{ADD_D198,{1U,6U,0U}}, +{ADD_D198,{2U,6U,0U}}, +{ADD_D198,{3U,6U,0U}}, +{ADD_D198,{4U,6U,0U}}, +{ADD_D198,{5U,6U,0U}}, +{ADD_D198,{6U,6U,0U}}, +{ADD_D198,{7U,6U,0U}}, +{ADD_D1A0,{0U,6U,0U}}, +{ADD_D1A0,{1U,6U,0U}}, +{ADD_D1A0,{2U,6U,0U}}, +{ADD_D1A0,{3U,6U,0U}}, +{ADD_D1A0,{4U,6U,0U}}, +{ADD_D1A0,{5U,6U,0U}}, +{ADD_D1A0,{6U,6U,0U}}, +{ADD_D1A0,{7U,6U,0U}}, +{ADD_D1A8,{0U,6U,0U}}, +{ADD_D1A8,{1U,6U,0U}}, +{ADD_D1A8,{2U,6U,0U}}, +{ADD_D1A8,{3U,6U,0U}}, +{ADD_D1A8,{4U,6U,0U}}, +{ADD_D1A8,{5U,6U,0U}}, +{ADD_D1A8,{6U,6U,0U}}, +{ADD_D1A8,{7U,6U,0U}}, +{ADD_D1B0,{0U,6U,0U}}, +{ADD_D1B0,{1U,6U,0U}}, +{ADD_D1B0,{2U,6U,0U}}, +{ADD_D1B0,{3U,6U,0U}}, +{ADD_D1B0,{4U,6U,0U}}, +{ADD_D1B0,{5U,6U,0U}}, +{ADD_D1B0,{6U,6U,0U}}, +{ADD_D1B0,{7U,6U,0U}}, +{ADD_D1B8,{0U,6U,0U}}, +{ADD_D1B9,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D1C0,{0U,6U,0U}}, +{ADDA_D1C0,{1U,6U,0U}}, +{ADDA_D1C0,{2U,6U,0U}}, +{ADDA_D1C0,{3U,6U,0U}}, +{ADDA_D1C0,{4U,6U,0U}}, +{ADDA_D1C0,{5U,6U,0U}}, +{ADDA_D1C0,{6U,6U,0U}}, +{ADDA_D1C0,{7U,6U,0U}}, +{ADDA_D1C8,{0U,6U,0U}}, +{ADDA_D1C8,{1U,6U,0U}}, +{ADDA_D1C8,{2U,6U,0U}}, +{ADDA_D1C8,{3U,6U,0U}}, +{ADDA_D1C8,{4U,6U,0U}}, +{ADDA_D1C8,{5U,6U,0U}}, +{ADDA_D1C8,{6U,6U,0U}}, +{ADDA_D1C8,{7U,6U,0U}}, +{ADDA_D1D0,{0U,6U,0U}}, +{ADDA_D1D0,{1U,6U,0U}}, +{ADDA_D1D0,{2U,6U,0U}}, +{ADDA_D1D0,{3U,6U,0U}}, +{ADDA_D1D0,{4U,6U,0U}}, +{ADDA_D1D0,{5U,6U,0U}}, +{ADDA_D1D0,{6U,6U,0U}}, +{ADDA_D1D0,{7U,6U,0U}}, +{ADDA_D1D8,{0U,6U,0U}}, +{ADDA_D1D8,{1U,6U,0U}}, +{ADDA_D1D8,{2U,6U,0U}}, +{ADDA_D1D8,{3U,6U,0U}}, +{ADDA_D1D8,{4U,6U,0U}}, +{ADDA_D1D8,{5U,6U,0U}}, +{ADDA_D1D8,{6U,6U,0U}}, +{ADDA_D1D8,{7U,6U,0U}}, +{ADDA_D1E0,{0U,6U,0U}}, +{ADDA_D1E0,{1U,6U,0U}}, +{ADDA_D1E0,{2U,6U,0U}}, +{ADDA_D1E0,{3U,6U,0U}}, +{ADDA_D1E0,{4U,6U,0U}}, +{ADDA_D1E0,{5U,6U,0U}}, +{ADDA_D1E0,{6U,6U,0U}}, +{ADDA_D1E0,{7U,6U,0U}}, +{ADDA_D1E8,{0U,6U,0U}}, +{ADDA_D1E8,{1U,6U,0U}}, +{ADDA_D1E8,{2U,6U,0U}}, +{ADDA_D1E8,{3U,6U,0U}}, +{ADDA_D1E8,{4U,6U,0U}}, +{ADDA_D1E8,{5U,6U,0U}}, +{ADDA_D1E8,{6U,6U,0U}}, +{ADDA_D1E8,{7U,6U,0U}}, +{ADDA_D1F0,{0U,6U,0U}}, +{ADDA_D1F0,{1U,6U,0U}}, +{ADDA_D1F0,{2U,6U,0U}}, +{ADDA_D1F0,{3U,6U,0U}}, +{ADDA_D1F0,{4U,6U,0U}}, +{ADDA_D1F0,{5U,6U,0U}}, +{ADDA_D1F0,{6U,6U,0U}}, +{ADDA_D1F0,{7U,6U,0U}}, +{ADDA_D1F8,{0U,6U,0U}}, +{ADDA_D1F9,{0U,6U,0U}}, +{ADDA_D1FA,{0U,6U,0U}}, +{ADDA_D1FB,{0U,6U,0U}}, +{ADDA_D1FC,{0U,6U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D000,{0U,7U,0U}}, +{ADD_D000,{1U,7U,0U}}, +{ADD_D000,{2U,7U,0U}}, +{ADD_D000,{3U,7U,0U}}, +{ADD_D000,{4U,7U,0U}}, +{ADD_D000,{5U,7U,0U}}, +{ADD_D000,{6U,7U,0U}}, +{ADD_D000,{7U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D010,{0U,7U,0U}}, +{ADD_D010,{1U,7U,0U}}, +{ADD_D010,{2U,7U,0U}}, +{ADD_D010,{3U,7U,0U}}, +{ADD_D010,{4U,7U,0U}}, +{ADD_D010,{5U,7U,0U}}, +{ADD_D010,{6U,7U,0U}}, +{ADD_D010,{7U,7U,0U}}, +{ADD_D018,{0U,7U,0U}}, +{ADD_D018,{1U,7U,0U}}, +{ADD_D018,{2U,7U,0U}}, +{ADD_D018,{3U,7U,0U}}, +{ADD_D018,{4U,7U,0U}}, +{ADD_D018,{5U,7U,0U}}, +{ADD_D018,{6U,7U,0U}}, +{ADD_D018,{7U,7U,0U}}, +{ADD_D020,{0U,7U,0U}}, +{ADD_D020,{1U,7U,0U}}, +{ADD_D020,{2U,7U,0U}}, +{ADD_D020,{3U,7U,0U}}, +{ADD_D020,{4U,7U,0U}}, +{ADD_D020,{5U,7U,0U}}, +{ADD_D020,{6U,7U,0U}}, +{ADD_D020,{7U,7U,0U}}, +{ADD_D028,{0U,7U,0U}}, +{ADD_D028,{1U,7U,0U}}, +{ADD_D028,{2U,7U,0U}}, +{ADD_D028,{3U,7U,0U}}, +{ADD_D028,{4U,7U,0U}}, +{ADD_D028,{5U,7U,0U}}, +{ADD_D028,{6U,7U,0U}}, +{ADD_D028,{7U,7U,0U}}, +{ADD_D030,{0U,7U,0U}}, +{ADD_D030,{1U,7U,0U}}, +{ADD_D030,{2U,7U,0U}}, +{ADD_D030,{3U,7U,0U}}, +{ADD_D030,{4U,7U,0U}}, +{ADD_D030,{5U,7U,0U}}, +{ADD_D030,{6U,7U,0U}}, +{ADD_D030,{7U,7U,0U}}, +{ADD_D038,{0U,7U,0U}}, +{ADD_D039,{0U,7U,0U}}, +{ADD_D03A,{0U,7U,0U}}, +{ADD_D03B,{0U,7U,0U}}, +{ADD_D03C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D040,{0U,7U,0U}}, +{ADD_D040,{1U,7U,0U}}, +{ADD_D040,{2U,7U,0U}}, +{ADD_D040,{3U,7U,0U}}, +{ADD_D040,{4U,7U,0U}}, +{ADD_D040,{5U,7U,0U}}, +{ADD_D040,{6U,7U,0U}}, +{ADD_D040,{7U,7U,0U}}, +{ADD_D048,{0U,7U,0U}}, +{ADD_D048,{1U,7U,0U}}, +{ADD_D048,{2U,7U,0U}}, +{ADD_D048,{3U,7U,0U}}, +{ADD_D048,{4U,7U,0U}}, +{ADD_D048,{5U,7U,0U}}, +{ADD_D048,{6U,7U,0U}}, +{ADD_D048,{7U,7U,0U}}, +{ADD_D050,{0U,7U,0U}}, +{ADD_D050,{1U,7U,0U}}, +{ADD_D050,{2U,7U,0U}}, +{ADD_D050,{3U,7U,0U}}, +{ADD_D050,{4U,7U,0U}}, +{ADD_D050,{5U,7U,0U}}, +{ADD_D050,{6U,7U,0U}}, +{ADD_D050,{7U,7U,0U}}, +{ADD_D058,{0U,7U,0U}}, +{ADD_D058,{1U,7U,0U}}, +{ADD_D058,{2U,7U,0U}}, +{ADD_D058,{3U,7U,0U}}, +{ADD_D058,{4U,7U,0U}}, +{ADD_D058,{5U,7U,0U}}, +{ADD_D058,{6U,7U,0U}}, +{ADD_D058,{7U,7U,0U}}, +{ADD_D060,{0U,7U,0U}}, +{ADD_D060,{1U,7U,0U}}, +{ADD_D060,{2U,7U,0U}}, +{ADD_D060,{3U,7U,0U}}, +{ADD_D060,{4U,7U,0U}}, +{ADD_D060,{5U,7U,0U}}, +{ADD_D060,{6U,7U,0U}}, +{ADD_D060,{7U,7U,0U}}, +{ADD_D068,{0U,7U,0U}}, +{ADD_D068,{1U,7U,0U}}, +{ADD_D068,{2U,7U,0U}}, +{ADD_D068,{3U,7U,0U}}, +{ADD_D068,{4U,7U,0U}}, +{ADD_D068,{5U,7U,0U}}, +{ADD_D068,{6U,7U,0U}}, +{ADD_D068,{7U,7U,0U}}, +{ADD_D070,{0U,7U,0U}}, +{ADD_D070,{1U,7U,0U}}, +{ADD_D070,{2U,7U,0U}}, +{ADD_D070,{3U,7U,0U}}, +{ADD_D070,{4U,7U,0U}}, +{ADD_D070,{5U,7U,0U}}, +{ADD_D070,{6U,7U,0U}}, +{ADD_D070,{7U,7U,0U}}, +{ADD_D078,{0U,7U,0U}}, +{ADD_D079,{0U,7U,0U}}, +{ADD_D07A,{0U,7U,0U}}, +{ADD_D07B,{0U,7U,0U}}, +{ADD_D07C,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADD_D080,{0U,7U,0U}}, +{ADD_D080,{1U,7U,0U}}, +{ADD_D080,{2U,7U,0U}}, +{ADD_D080,{3U,7U,0U}}, +{ADD_D080,{4U,7U,0U}}, +{ADD_D080,{5U,7U,0U}}, +{ADD_D080,{6U,7U,0U}}, +{ADD_D080,{7U,7U,0U}}, +{ADD_D088,{0U,7U,0U}}, +{ADD_D088,{1U,7U,0U}}, +{ADD_D088,{2U,7U,0U}}, +{ADD_D088,{3U,7U,0U}}, +{ADD_D088,{4U,7U,0U}}, +{ADD_D088,{5U,7U,0U}}, +{ADD_D088,{6U,7U,0U}}, +{ADD_D088,{7U,7U,0U}}, +{ADD_D090,{0U,7U,0U}}, +{ADD_D090,{1U,7U,0U}}, +{ADD_D090,{2U,7U,0U}}, +{ADD_D090,{3U,7U,0U}}, +{ADD_D090,{4U,7U,0U}}, +{ADD_D090,{5U,7U,0U}}, +{ADD_D090,{6U,7U,0U}}, +{ADD_D090,{7U,7U,0U}}, +{ADD_D098,{0U,7U,0U}}, +{ADD_D098,{1U,7U,0U}}, +{ADD_D098,{2U,7U,0U}}, +{ADD_D098,{3U,7U,0U}}, +{ADD_D098,{4U,7U,0U}}, +{ADD_D098,{5U,7U,0U}}, +{ADD_D098,{6U,7U,0U}}, +{ADD_D098,{7U,7U,0U}}, +{ADD_D0A0,{0U,7U,0U}}, +{ADD_D0A0,{1U,7U,0U}}, +{ADD_D0A0,{2U,7U,0U}}, +{ADD_D0A0,{3U,7U,0U}}, +{ADD_D0A0,{4U,7U,0U}}, +{ADD_D0A0,{5U,7U,0U}}, +{ADD_D0A0,{6U,7U,0U}}, +{ADD_D0A0,{7U,7U,0U}}, +{ADD_D0A8,{0U,7U,0U}}, +{ADD_D0A8,{1U,7U,0U}}, +{ADD_D0A8,{2U,7U,0U}}, +{ADD_D0A8,{3U,7U,0U}}, +{ADD_D0A8,{4U,7U,0U}}, +{ADD_D0A8,{5U,7U,0U}}, +{ADD_D0A8,{6U,7U,0U}}, +{ADD_D0A8,{7U,7U,0U}}, +{ADD_D0B0,{0U,7U,0U}}, +{ADD_D0B0,{1U,7U,0U}}, +{ADD_D0B0,{2U,7U,0U}}, +{ADD_D0B0,{3U,7U,0U}}, +{ADD_D0B0,{4U,7U,0U}}, +{ADD_D0B0,{5U,7U,0U}}, +{ADD_D0B0,{6U,7U,0U}}, +{ADD_D0B0,{7U,7U,0U}}, +{ADD_D0B8,{0U,7U,0U}}, +{ADD_D0B9,{0U,7U,0U}}, +{ADD_D0BA,{0U,7U,0U}}, +{ADD_D0BB,{0U,7U,0U}}, +{ADD_D0BC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D0C0,{0U,7U,0U}}, +{ADDA_D0C0,{1U,7U,0U}}, +{ADDA_D0C0,{2U,7U,0U}}, +{ADDA_D0C0,{3U,7U,0U}}, +{ADDA_D0C0,{4U,7U,0U}}, +{ADDA_D0C0,{5U,7U,0U}}, +{ADDA_D0C0,{6U,7U,0U}}, +{ADDA_D0C0,{7U,7U,0U}}, +{ADDA_D0C8,{0U,7U,0U}}, +{ADDA_D0C8,{1U,7U,0U}}, +{ADDA_D0C8,{2U,7U,0U}}, +{ADDA_D0C8,{3U,7U,0U}}, +{ADDA_D0C8,{4U,7U,0U}}, +{ADDA_D0C8,{5U,7U,0U}}, +{ADDA_D0C8,{6U,7U,0U}}, +{ADDA_D0C8,{7U,7U,0U}}, +{ADDA_D0D0,{0U,7U,0U}}, +{ADDA_D0D0,{1U,7U,0U}}, +{ADDA_D0D0,{2U,7U,0U}}, +{ADDA_D0D0,{3U,7U,0U}}, +{ADDA_D0D0,{4U,7U,0U}}, +{ADDA_D0D0,{5U,7U,0U}}, +{ADDA_D0D0,{6U,7U,0U}}, +{ADDA_D0D0,{7U,7U,0U}}, +{ADDA_D0D8,{0U,7U,0U}}, +{ADDA_D0D8,{1U,7U,0U}}, +{ADDA_D0D8,{2U,7U,0U}}, +{ADDA_D0D8,{3U,7U,0U}}, +{ADDA_D0D8,{4U,7U,0U}}, +{ADDA_D0D8,{5U,7U,0U}}, +{ADDA_D0D8,{6U,7U,0U}}, +{ADDA_D0D8,{7U,7U,0U}}, +{ADDA_D0E0,{0U,7U,0U}}, +{ADDA_D0E0,{1U,7U,0U}}, +{ADDA_D0E0,{2U,7U,0U}}, +{ADDA_D0E0,{3U,7U,0U}}, +{ADDA_D0E0,{4U,7U,0U}}, +{ADDA_D0E0,{5U,7U,0U}}, +{ADDA_D0E0,{6U,7U,0U}}, +{ADDA_D0E0,{7U,7U,0U}}, +{ADDA_D0E8,{0U,7U,0U}}, +{ADDA_D0E8,{1U,7U,0U}}, +{ADDA_D0E8,{2U,7U,0U}}, +{ADDA_D0E8,{3U,7U,0U}}, +{ADDA_D0E8,{4U,7U,0U}}, +{ADDA_D0E8,{5U,7U,0U}}, +{ADDA_D0E8,{6U,7U,0U}}, +{ADDA_D0E8,{7U,7U,0U}}, +{ADDA_D0F0,{0U,7U,0U}}, +{ADDA_D0F0,{1U,7U,0U}}, +{ADDA_D0F0,{2U,7U,0U}}, +{ADDA_D0F0,{3U,7U,0U}}, +{ADDA_D0F0,{4U,7U,0U}}, +{ADDA_D0F0,{5U,7U,0U}}, +{ADDA_D0F0,{6U,7U,0U}}, +{ADDA_D0F0,{7U,7U,0U}}, +{ADDA_D0F8,{0U,7U,0U}}, +{ADDA_D0F9,{0U,7U,0U}}, +{ADDA_D0FA,{0U,7U,0U}}, +{ADDA_D0FB,{0U,7U,0U}}, +{ADDA_D0FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D100,{0U,7U,0U}}, +{ADDX_D100,{1U,7U,0U}}, +{ADDX_D100,{2U,7U,0U}}, +{ADDX_D100,{3U,7U,0U}}, +{ADDX_D100,{4U,7U,0U}}, +{ADDX_D100,{5U,7U,0U}}, +{ADDX_D100,{6U,7U,0U}}, +{ADDX_D100,{7U,7U,0U}}, +{ADDX_D108,{0U,7U,0U}}, +{ADDX_D108,{1U,7U,0U}}, +{ADDX_D108,{2U,7U,0U}}, +{ADDX_D108,{3U,7U,0U}}, +{ADDX_D108,{4U,7U,0U}}, +{ADDX_D108,{5U,7U,0U}}, +{ADDX_D108,{6U,7U,0U}}, +{ADDX_D108,{7U,7U,0U}}, +{ADD_D110,{0U,7U,0U}}, +{ADD_D110,{1U,7U,0U}}, +{ADD_D110,{2U,7U,0U}}, +{ADD_D110,{3U,7U,0U}}, +{ADD_D110,{4U,7U,0U}}, +{ADD_D110,{5U,7U,0U}}, +{ADD_D110,{6U,7U,0U}}, +{ADD_D110,{7U,7U,0U}}, +{ADD_D118,{0U,7U,0U}}, +{ADD_D118,{1U,7U,0U}}, +{ADD_D118,{2U,7U,0U}}, +{ADD_D118,{3U,7U,0U}}, +{ADD_D118,{4U,7U,0U}}, +{ADD_D118,{5U,7U,0U}}, +{ADD_D118,{6U,7U,0U}}, +{ADD_D118,{7U,7U,0U}}, +{ADD_D120,{0U,7U,0U}}, +{ADD_D120,{1U,7U,0U}}, +{ADD_D120,{2U,7U,0U}}, +{ADD_D120,{3U,7U,0U}}, +{ADD_D120,{4U,7U,0U}}, +{ADD_D120,{5U,7U,0U}}, +{ADD_D120,{6U,7U,0U}}, +{ADD_D120,{7U,7U,0U}}, +{ADD_D128,{0U,7U,0U}}, +{ADD_D128,{1U,7U,0U}}, +{ADD_D128,{2U,7U,0U}}, +{ADD_D128,{3U,7U,0U}}, +{ADD_D128,{4U,7U,0U}}, +{ADD_D128,{5U,7U,0U}}, +{ADD_D128,{6U,7U,0U}}, +{ADD_D128,{7U,7U,0U}}, +{ADD_D130,{0U,7U,0U}}, +{ADD_D130,{1U,7U,0U}}, +{ADD_D130,{2U,7U,0U}}, +{ADD_D130,{3U,7U,0U}}, +{ADD_D130,{4U,7U,0U}}, +{ADD_D130,{5U,7U,0U}}, +{ADD_D130,{6U,7U,0U}}, +{ADD_D130,{7U,7U,0U}}, +{ADD_D138,{0U,7U,0U}}, +{ADD_D139,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D140,{0U,7U,0U}}, +{ADDX_D140,{1U,7U,0U}}, +{ADDX_D140,{2U,7U,0U}}, +{ADDX_D140,{3U,7U,0U}}, +{ADDX_D140,{4U,7U,0U}}, +{ADDX_D140,{5U,7U,0U}}, +{ADDX_D140,{6U,7U,0U}}, +{ADDX_D140,{7U,7U,0U}}, +{ADDX_D148,{0U,7U,0U}}, +{ADDX_D148,{1U,7U,0U}}, +{ADDX_D148,{2U,7U,0U}}, +{ADDX_D148,{3U,7U,0U}}, +{ADDX_D148,{4U,7U,0U}}, +{ADDX_D148,{5U,7U,0U}}, +{ADDX_D148,{6U,7U,0U}}, +{ADDX_D148,{7U,7U,0U}}, +{ADD_D150,{0U,7U,0U}}, +{ADD_D150,{1U,7U,0U}}, +{ADD_D150,{2U,7U,0U}}, +{ADD_D150,{3U,7U,0U}}, +{ADD_D150,{4U,7U,0U}}, +{ADD_D150,{5U,7U,0U}}, +{ADD_D150,{6U,7U,0U}}, +{ADD_D150,{7U,7U,0U}}, +{ADD_D158,{0U,7U,0U}}, +{ADD_D158,{1U,7U,0U}}, +{ADD_D158,{2U,7U,0U}}, +{ADD_D158,{3U,7U,0U}}, +{ADD_D158,{4U,7U,0U}}, +{ADD_D158,{5U,7U,0U}}, +{ADD_D158,{6U,7U,0U}}, +{ADD_D158,{7U,7U,0U}}, +{ADD_D160,{0U,7U,0U}}, +{ADD_D160,{1U,7U,0U}}, +{ADD_D160,{2U,7U,0U}}, +{ADD_D160,{3U,7U,0U}}, +{ADD_D160,{4U,7U,0U}}, +{ADD_D160,{5U,7U,0U}}, +{ADD_D160,{6U,7U,0U}}, +{ADD_D160,{7U,7U,0U}}, +{ADD_D168,{0U,7U,0U}}, +{ADD_D168,{1U,7U,0U}}, +{ADD_D168,{2U,7U,0U}}, +{ADD_D168,{3U,7U,0U}}, +{ADD_D168,{4U,7U,0U}}, +{ADD_D168,{5U,7U,0U}}, +{ADD_D168,{6U,7U,0U}}, +{ADD_D168,{7U,7U,0U}}, +{ADD_D170,{0U,7U,0U}}, +{ADD_D170,{1U,7U,0U}}, +{ADD_D170,{2U,7U,0U}}, +{ADD_D170,{3U,7U,0U}}, +{ADD_D170,{4U,7U,0U}}, +{ADD_D170,{5U,7U,0U}}, +{ADD_D170,{6U,7U,0U}}, +{ADD_D170,{7U,7U,0U}}, +{ADD_D178,{0U,7U,0U}}, +{ADD_D179,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDX_D180,{0U,7U,0U}}, +{ADDX_D180,{1U,7U,0U}}, +{ADDX_D180,{2U,7U,0U}}, +{ADDX_D180,{3U,7U,0U}}, +{ADDX_D180,{4U,7U,0U}}, +{ADDX_D180,{5U,7U,0U}}, +{ADDX_D180,{6U,7U,0U}}, +{ADDX_D180,{7U,7U,0U}}, +{ADDX_D188,{0U,7U,0U}}, +{ADDX_D188,{1U,7U,0U}}, +{ADDX_D188,{2U,7U,0U}}, +{ADDX_D188,{3U,7U,0U}}, +{ADDX_D188,{4U,7U,0U}}, +{ADDX_D188,{5U,7U,0U}}, +{ADDX_D188,{6U,7U,0U}}, +{ADDX_D188,{7U,7U,0U}}, +{ADD_D190,{0U,7U,0U}}, +{ADD_D190,{1U,7U,0U}}, +{ADD_D190,{2U,7U,0U}}, +{ADD_D190,{3U,7U,0U}}, +{ADD_D190,{4U,7U,0U}}, +{ADD_D190,{5U,7U,0U}}, +{ADD_D190,{6U,7U,0U}}, +{ADD_D190,{7U,7U,0U}}, +{ADD_D198,{0U,7U,0U}}, +{ADD_D198,{1U,7U,0U}}, +{ADD_D198,{2U,7U,0U}}, +{ADD_D198,{3U,7U,0U}}, +{ADD_D198,{4U,7U,0U}}, +{ADD_D198,{5U,7U,0U}}, +{ADD_D198,{6U,7U,0U}}, +{ADD_D198,{7U,7U,0U}}, +{ADD_D1A0,{0U,7U,0U}}, +{ADD_D1A0,{1U,7U,0U}}, +{ADD_D1A0,{2U,7U,0U}}, +{ADD_D1A0,{3U,7U,0U}}, +{ADD_D1A0,{4U,7U,0U}}, +{ADD_D1A0,{5U,7U,0U}}, +{ADD_D1A0,{6U,7U,0U}}, +{ADD_D1A0,{7U,7U,0U}}, +{ADD_D1A8,{0U,7U,0U}}, +{ADD_D1A8,{1U,7U,0U}}, +{ADD_D1A8,{2U,7U,0U}}, +{ADD_D1A8,{3U,7U,0U}}, +{ADD_D1A8,{4U,7U,0U}}, +{ADD_D1A8,{5U,7U,0U}}, +{ADD_D1A8,{6U,7U,0U}}, +{ADD_D1A8,{7U,7U,0U}}, +{ADD_D1B0,{0U,7U,0U}}, +{ADD_D1B0,{1U,7U,0U}}, +{ADD_D1B0,{2U,7U,0U}}, +{ADD_D1B0,{3U,7U,0U}}, +{ADD_D1B0,{4U,7U,0U}}, +{ADD_D1B0,{5U,7U,0U}}, +{ADD_D1B0,{6U,7U,0U}}, +{ADD_D1B0,{7U,7U,0U}}, +{ADD_D1B8,{0U,7U,0U}}, +{ADD_D1B9,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ADDA_D1C0,{0U,7U,0U}}, +{ADDA_D1C0,{1U,7U,0U}}, +{ADDA_D1C0,{2U,7U,0U}}, +{ADDA_D1C0,{3U,7U,0U}}, +{ADDA_D1C0,{4U,7U,0U}}, +{ADDA_D1C0,{5U,7U,0U}}, +{ADDA_D1C0,{6U,7U,0U}}, +{ADDA_D1C0,{7U,7U,0U}}, +{ADDA_D1C8,{0U,7U,0U}}, +{ADDA_D1C8,{1U,7U,0U}}, +{ADDA_D1C8,{2U,7U,0U}}, +{ADDA_D1C8,{3U,7U,0U}}, +{ADDA_D1C8,{4U,7U,0U}}, +{ADDA_D1C8,{5U,7U,0U}}, +{ADDA_D1C8,{6U,7U,0U}}, +{ADDA_D1C8,{7U,7U,0U}}, +{ADDA_D1D0,{0U,7U,0U}}, +{ADDA_D1D0,{1U,7U,0U}}, +{ADDA_D1D0,{2U,7U,0U}}, +{ADDA_D1D0,{3U,7U,0U}}, +{ADDA_D1D0,{4U,7U,0U}}, +{ADDA_D1D0,{5U,7U,0U}}, +{ADDA_D1D0,{6U,7U,0U}}, +{ADDA_D1D0,{7U,7U,0U}}, +{ADDA_D1D8,{0U,7U,0U}}, +{ADDA_D1D8,{1U,7U,0U}}, +{ADDA_D1D8,{2U,7U,0U}}, +{ADDA_D1D8,{3U,7U,0U}}, +{ADDA_D1D8,{4U,7U,0U}}, +{ADDA_D1D8,{5U,7U,0U}}, +{ADDA_D1D8,{6U,7U,0U}}, +{ADDA_D1D8,{7U,7U,0U}}, +{ADDA_D1E0,{0U,7U,0U}}, +{ADDA_D1E0,{1U,7U,0U}}, +{ADDA_D1E0,{2U,7U,0U}}, +{ADDA_D1E0,{3U,7U,0U}}, +{ADDA_D1E0,{4U,7U,0U}}, +{ADDA_D1E0,{5U,7U,0U}}, +{ADDA_D1E0,{6U,7U,0U}}, +{ADDA_D1E0,{7U,7U,0U}}, +{ADDA_D1E8,{0U,7U,0U}}, +{ADDA_D1E8,{1U,7U,0U}}, +{ADDA_D1E8,{2U,7U,0U}}, +{ADDA_D1E8,{3U,7U,0U}}, +{ADDA_D1E8,{4U,7U,0U}}, +{ADDA_D1E8,{5U,7U,0U}}, +{ADDA_D1E8,{6U,7U,0U}}, +{ADDA_D1E8,{7U,7U,0U}}, +{ADDA_D1F0,{0U,7U,0U}}, +{ADDA_D1F0,{1U,7U,0U}}, +{ADDA_D1F0,{2U,7U,0U}}, +{ADDA_D1F0,{3U,7U,0U}}, +{ADDA_D1F0,{4U,7U,0U}}, +{ADDA_D1F0,{5U,7U,0U}}, +{ADDA_D1F0,{6U,7U,0U}}, +{ADDA_D1F0,{7U,7U,0U}}, +{ADDA_D1F8,{0U,7U,0U}}, +{ADDA_D1F9,{0U,7U,0U}}, +{ADDA_D1FA,{0U,7U,0U}}, +{ADDA_D1FB,{0U,7U,0U}}, +{ADDA_D1FC,{0U,7U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASR_E000,{0U,8U,6U}}, +{ASR_E000,{1U,8U,6U}}, +{ASR_E000,{2U,8U,6U}}, +{ASR_E000,{3U,8U,6U}}, +{ASR_E000,{4U,8U,6U}}, +{ASR_E000,{5U,8U,6U}}, +{ASR_E000,{6U,8U,6U}}, +{ASR_E000,{7U,8U,6U}}, +{LSR_E008,{0U,8U,6U}}, +{LSR_E008,{1U,8U,6U}}, +{LSR_E008,{2U,8U,6U}}, +{LSR_E008,{3U,8U,6U}}, +{LSR_E008,{4U,8U,6U}}, +{LSR_E008,{5U,8U,6U}}, +{LSR_E008,{6U,8U,6U}}, +{LSR_E008,{7U,8U,6U}}, +{ROXR_E010,{0U,8U,6U}}, +{ROXR_E010,{1U,8U,6U}}, +{ROXR_E010,{2U,8U,6U}}, +{ROXR_E010,{3U,8U,6U}}, +{ROXR_E010,{4U,8U,6U}}, +{ROXR_E010,{5U,8U,6U}}, +{ROXR_E010,{6U,8U,6U}}, +{ROXR_E010,{7U,8U,6U}}, +{ROR_E018,{0U,8U,6U}}, +{ROR_E018,{1U,8U,6U}}, +{ROR_E018,{2U,8U,6U}}, +{ROR_E018,{3U,8U,6U}}, +{ROR_E018,{4U,8U,6U}}, +{ROR_E018,{5U,8U,6U}}, +{ROR_E018,{6U,8U,6U}}, +{ROR_E018,{7U,8U,6U}}, +{ASR_E020,{0U,0U,6U}}, +{ASR_E020,{1U,0U,6U}}, +{ASR_E020,{2U,0U,6U}}, +{ASR_E020,{3U,0U,6U}}, +{ASR_E020,{4U,0U,6U}}, +{ASR_E020,{5U,0U,6U}}, +{ASR_E020,{6U,0U,6U}}, +{ASR_E020,{7U,0U,6U}}, +{LSR_E028,{0U,0U,6U}}, +{LSR_E028,{1U,0U,6U}}, +{LSR_E028,{2U,0U,6U}}, +{LSR_E028,{3U,0U,6U}}, +{LSR_E028,{4U,0U,6U}}, +{LSR_E028,{5U,0U,6U}}, +{LSR_E028,{6U,0U,6U}}, +{LSR_E028,{7U,0U,6U}}, +{ROXR_E030,{0U,0U,6U}}, +{ROXR_E030,{1U,0U,6U}}, +{ROXR_E030,{2U,0U,6U}}, +{ROXR_E030,{3U,0U,6U}}, +{ROXR_E030,{4U,0U,6U}}, +{ROXR_E030,{5U,0U,6U}}, +{ROXR_E030,{6U,0U,6U}}, +{ROXR_E030,{7U,0U,6U}}, +{ROR_E038,{0U,0U,6U}}, +{ROR_E038,{1U,0U,6U}}, +{ROR_E038,{2U,0U,6U}}, +{ROR_E038,{3U,0U,6U}}, +{ROR_E038,{4U,0U,6U}}, +{ROR_E038,{5U,0U,6U}}, +{ROR_E038,{6U,0U,6U}}, +{ROR_E038,{7U,0U,6U}}, +{ASR_E040,{0U,8U,6U}}, +{ASR_E040,{1U,8U,6U}}, +{ASR_E040,{2U,8U,6U}}, +{ASR_E040,{3U,8U,6U}}, +{ASR_E040,{4U,8U,6U}}, +{ASR_E040,{5U,8U,6U}}, +{ASR_E040,{6U,8U,6U}}, +{ASR_E040,{7U,8U,6U}}, +{LSR_E048,{0U,8U,6U}}, +{LSR_E048,{1U,8U,6U}}, +{LSR_E048,{2U,8U,6U}}, +{LSR_E048,{3U,8U,6U}}, +{LSR_E048,{4U,8U,6U}}, +{LSR_E048,{5U,8U,6U}}, +{LSR_E048,{6U,8U,6U}}, +{LSR_E048,{7U,8U,6U}}, +{ROXR_E050,{0U,8U,6U}}, +{ROXR_E050,{1U,8U,6U}}, +{ROXR_E050,{2U,8U,6U}}, +{ROXR_E050,{3U,8U,6U}}, +{ROXR_E050,{4U,8U,6U}}, +{ROXR_E050,{5U,8U,6U}}, +{ROXR_E050,{6U,8U,6U}}, +{ROXR_E050,{7U,8U,6U}}, +{ROR_E058,{0U,8U,6U}}, +{ROR_E058,{1U,8U,6U}}, +{ROR_E058,{2U,8U,6U}}, +{ROR_E058,{3U,8U,6U}}, +{ROR_E058,{4U,8U,6U}}, +{ROR_E058,{5U,8U,6U}}, +{ROR_E058,{6U,8U,6U}}, +{ROR_E058,{7U,8U,6U}}, +{ASR_E060,{0U,0U,6U}}, +{ASR_E060,{1U,0U,6U}}, +{ASR_E060,{2U,0U,6U}}, +{ASR_E060,{3U,0U,6U}}, +{ASR_E060,{4U,0U,6U}}, +{ASR_E060,{5U,0U,6U}}, +{ASR_E060,{6U,0U,6U}}, +{ASR_E060,{7U,0U,6U}}, +{LSR_E068,{0U,0U,6U}}, +{LSR_E068,{1U,0U,6U}}, +{LSR_E068,{2U,0U,6U}}, +{LSR_E068,{3U,0U,6U}}, +{LSR_E068,{4U,0U,6U}}, +{LSR_E068,{5U,0U,6U}}, +{LSR_E068,{6U,0U,6U}}, +{LSR_E068,{7U,0U,6U}}, +{ROXR_E070,{0U,0U,6U}}, +{ROXR_E070,{1U,0U,6U}}, +{ROXR_E070,{2U,0U,6U}}, +{ROXR_E070,{3U,0U,6U}}, +{ROXR_E070,{4U,0U,6U}}, +{ROXR_E070,{5U,0U,6U}}, +{ROXR_E070,{6U,0U,6U}}, +{ROXR_E070,{7U,0U,6U}}, +{ROR_E078,{0U,0U,6U}}, +{ROR_E078,{1U,0U,6U}}, +{ROR_E078,{2U,0U,6U}}, +{ROR_E078,{3U,0U,6U}}, +{ROR_E078,{4U,0U,6U}}, +{ROR_E078,{5U,0U,6U}}, +{ROR_E078,{6U,0U,6U}}, +{ROR_E078,{7U,0U,6U}}, +{ASR_E080,{0U,8U,8U}}, +{ASR_E080,{1U,8U,8U}}, +{ASR_E080,{2U,8U,8U}}, +{ASR_E080,{3U,8U,8U}}, +{ASR_E080,{4U,8U,8U}}, +{ASR_E080,{5U,8U,8U}}, +{ASR_E080,{6U,8U,8U}}, +{ASR_E080,{7U,8U,8U}}, +{LSR_E088,{0U,8U,8U}}, +{LSR_E088,{1U,8U,8U}}, +{LSR_E088,{2U,8U,8U}}, +{LSR_E088,{3U,8U,8U}}, +{LSR_E088,{4U,8U,8U}}, +{LSR_E088,{5U,8U,8U}}, +{LSR_E088,{6U,8U,8U}}, +{LSR_E088,{7U,8U,8U}}, +{ROXR_E090,{0U,8U,8U}}, +{ROXR_E090,{1U,8U,8U}}, +{ROXR_E090,{2U,8U,8U}}, +{ROXR_E090,{3U,8U,8U}}, +{ROXR_E090,{4U,8U,8U}}, +{ROXR_E090,{5U,8U,8U}}, +{ROXR_E090,{6U,8U,8U}}, +{ROXR_E090,{7U,8U,8U}}, +{ROR_E098,{0U,8U,8U}}, +{ROR_E098,{1U,8U,8U}}, +{ROR_E098,{2U,8U,8U}}, +{ROR_E098,{3U,8U,8U}}, +{ROR_E098,{4U,8U,8U}}, +{ROR_E098,{5U,8U,8U}}, +{ROR_E098,{6U,8U,8U}}, +{ROR_E098,{7U,8U,8U}}, +{ASR_E0A0,{0U,0U,8U}}, +{ASR_E0A0,{1U,0U,8U}}, +{ASR_E0A0,{2U,0U,8U}}, +{ASR_E0A0,{3U,0U,8U}}, +{ASR_E0A0,{4U,0U,8U}}, +{ASR_E0A0,{5U,0U,8U}}, +{ASR_E0A0,{6U,0U,8U}}, +{ASR_E0A0,{7U,0U,8U}}, +{LSR_E0A8,{0U,0U,8U}}, +{LSR_E0A8,{1U,0U,8U}}, +{LSR_E0A8,{2U,0U,8U}}, +{LSR_E0A8,{3U,0U,8U}}, +{LSR_E0A8,{4U,0U,8U}}, +{LSR_E0A8,{5U,0U,8U}}, +{LSR_E0A8,{6U,0U,8U}}, +{LSR_E0A8,{7U,0U,8U}}, +{ROXR_E0B0,{0U,0U,8U}}, +{ROXR_E0B0,{1U,0U,8U}}, +{ROXR_E0B0,{2U,0U,8U}}, +{ROXR_E0B0,{3U,0U,8U}}, +{ROXR_E0B0,{4U,0U,8U}}, +{ROXR_E0B0,{5U,0U,8U}}, +{ROXR_E0B0,{6U,0U,8U}}, +{ROXR_E0B0,{7U,0U,8U}}, +{ROR_E0B8,{0U,0U,8U}}, +{ROR_E0B8,{1U,0U,8U}}, +{ROR_E0B8,{2U,0U,8U}}, +{ROR_E0B8,{3U,0U,8U}}, +{ROR_E0B8,{4U,0U,8U}}, +{ROR_E0B8,{5U,0U,8U}}, +{ROR_E0B8,{6U,0U,8U}}, +{ROR_E0B8,{7U,0U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASR_E0D0,{0U,0U,10U}}, +{ASR_E0D0,{1U,0U,10U}}, +{ASR_E0D0,{2U,0U,10U}}, +{ASR_E0D0,{3U,0U,10U}}, +{ASR_E0D0,{4U,0U,10U}}, +{ASR_E0D0,{5U,0U,10U}}, +{ASR_E0D0,{6U,0U,10U}}, +{ASR_E0D0,{7U,0U,10U}}, +{ASR_E0D8,{0U,0U,10U}}, +{ASR_E0D8,{1U,0U,10U}}, +{ASR_E0D8,{2U,0U,10U}}, +{ASR_E0D8,{3U,0U,10U}}, +{ASR_E0D8,{4U,0U,10U}}, +{ASR_E0D8,{5U,0U,10U}}, +{ASR_E0D8,{6U,0U,10U}}, +{ASR_E0D8,{7U,0U,10U}}, +{ASR_E0E0,{0U,0U,12U}}, +{ASR_E0E0,{1U,0U,12U}}, +{ASR_E0E0,{2U,0U,12U}}, +{ASR_E0E0,{3U,0U,12U}}, +{ASR_E0E0,{4U,0U,12U}}, +{ASR_E0E0,{5U,0U,12U}}, +{ASR_E0E0,{6U,0U,12U}}, +{ASR_E0E0,{7U,0U,12U}}, +{ASR_E0E8,{0U,0U,14U}}, +{ASR_E0E8,{1U,0U,14U}}, +{ASR_E0E8,{2U,0U,14U}}, +{ASR_E0E8,{3U,0U,14U}}, +{ASR_E0E8,{4U,0U,14U}}, +{ASR_E0E8,{5U,0U,14U}}, +{ASR_E0E8,{6U,0U,14U}}, +{ASR_E0E8,{7U,0U,14U}}, +{ASR_E0F0,{0U,0U,16U}}, +{ASR_E0F0,{1U,0U,16U}}, +{ASR_E0F0,{2U,0U,16U}}, +{ASR_E0F0,{3U,0U,16U}}, +{ASR_E0F0,{4U,0U,16U}}, +{ASR_E0F0,{5U,0U,16U}}, +{ASR_E0F0,{6U,0U,16U}}, +{ASR_E0F0,{7U,0U,16U}}, +{ASR_E0F8,{0U,0U,14U}}, +{ASR_E0F9,{0U,0U,18U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASL_E100,{0U,8U,6U}}, +{ASL_E100,{1U,8U,6U}}, +{ASL_E100,{2U,8U,6U}}, +{ASL_E100,{3U,8U,6U}}, +{ASL_E100,{4U,8U,6U}}, +{ASL_E100,{5U,8U,6U}}, +{ASL_E100,{6U,8U,6U}}, +{ASL_E100,{7U,8U,6U}}, +{LSL_E108,{0U,8U,6U}}, +{LSL_E108,{1U,8U,6U}}, +{LSL_E108,{2U,8U,6U}}, +{LSL_E108,{3U,8U,6U}}, +{LSL_E108,{4U,8U,6U}}, +{LSL_E108,{5U,8U,6U}}, +{LSL_E108,{6U,8U,6U}}, +{LSL_E108,{7U,8U,6U}}, +{ROXL_E110,{0U,8U,6U}}, +{ROXL_E110,{1U,8U,6U}}, +{ROXL_E110,{2U,8U,6U}}, +{ROXL_E110,{3U,8U,6U}}, +{ROXL_E110,{4U,8U,6U}}, +{ROXL_E110,{5U,8U,6U}}, +{ROXL_E110,{6U,8U,6U}}, +{ROXL_E110,{7U,8U,6U}}, +{ROL_E118,{0U,8U,6U}}, +{ROL_E118,{1U,8U,6U}}, +{ROL_E118,{2U,8U,6U}}, +{ROL_E118,{3U,8U,6U}}, +{ROL_E118,{4U,8U,6U}}, +{ROL_E118,{5U,8U,6U}}, +{ROL_E118,{6U,8U,6U}}, +{ROL_E118,{7U,8U,6U}}, +{ASL_E120,{0U,0U,6U}}, +{ASL_E120,{1U,0U,6U}}, +{ASL_E120,{2U,0U,6U}}, +{ASL_E120,{3U,0U,6U}}, +{ASL_E120,{4U,0U,6U}}, +{ASL_E120,{5U,0U,6U}}, +{ASL_E120,{6U,0U,6U}}, +{ASL_E120,{7U,0U,6U}}, +{LSL_E128,{0U,0U,6U}}, +{LSL_E128,{1U,0U,6U}}, +{LSL_E128,{2U,0U,6U}}, +{LSL_E128,{3U,0U,6U}}, +{LSL_E128,{4U,0U,6U}}, +{LSL_E128,{5U,0U,6U}}, +{LSL_E128,{6U,0U,6U}}, +{LSL_E128,{7U,0U,6U}}, +{ROXL_E130,{0U,0U,6U}}, +{ROXL_E130,{1U,0U,6U}}, +{ROXL_E130,{2U,0U,6U}}, +{ROXL_E130,{3U,0U,6U}}, +{ROXL_E130,{4U,0U,6U}}, +{ROXL_E130,{5U,0U,6U}}, +{ROXL_E130,{6U,0U,6U}}, +{ROXL_E130,{7U,0U,6U}}, +{ROL_E138,{0U,0U,6U}}, +{ROL_E138,{1U,0U,6U}}, +{ROL_E138,{2U,0U,6U}}, +{ROL_E138,{3U,0U,6U}}, +{ROL_E138,{4U,0U,6U}}, +{ROL_E138,{5U,0U,6U}}, +{ROL_E138,{6U,0U,6U}}, +{ROL_E138,{7U,0U,6U}}, +{ASL_E140,{0U,8U,6U}}, +{ASL_E140,{1U,8U,6U}}, +{ASL_E140,{2U,8U,6U}}, +{ASL_E140,{3U,8U,6U}}, +{ASL_E140,{4U,8U,6U}}, +{ASL_E140,{5U,8U,6U}}, +{ASL_E140,{6U,8U,6U}}, +{ASL_E140,{7U,8U,6U}}, +{LSL_E148,{0U,8U,6U}}, +{LSL_E148,{1U,8U,6U}}, +{LSL_E148,{2U,8U,6U}}, +{LSL_E148,{3U,8U,6U}}, +{LSL_E148,{4U,8U,6U}}, +{LSL_E148,{5U,8U,6U}}, +{LSL_E148,{6U,8U,6U}}, +{LSL_E148,{7U,8U,6U}}, +{ROXL_E150,{0U,8U,6U}}, +{ROXL_E150,{1U,8U,6U}}, +{ROXL_E150,{2U,8U,6U}}, +{ROXL_E150,{3U,8U,6U}}, +{ROXL_E150,{4U,8U,6U}}, +{ROXL_E150,{5U,8U,6U}}, +{ROXL_E150,{6U,8U,6U}}, +{ROXL_E150,{7U,8U,6U}}, +{ROL_E158,{0U,8U,6U}}, +{ROL_E158,{1U,8U,6U}}, +{ROL_E158,{2U,8U,6U}}, +{ROL_E158,{3U,8U,6U}}, +{ROL_E158,{4U,8U,6U}}, +{ROL_E158,{5U,8U,6U}}, +{ROL_E158,{6U,8U,6U}}, +{ROL_E158,{7U,8U,6U}}, +{ASL_E160,{0U,0U,6U}}, +{ASL_E160,{1U,0U,6U}}, +{ASL_E160,{2U,0U,6U}}, +{ASL_E160,{3U,0U,6U}}, +{ASL_E160,{4U,0U,6U}}, +{ASL_E160,{5U,0U,6U}}, +{ASL_E160,{6U,0U,6U}}, +{ASL_E160,{7U,0U,6U}}, +{LSL_E168,{0U,0U,6U}}, +{LSL_E168,{1U,0U,6U}}, +{LSL_E168,{2U,0U,6U}}, +{LSL_E168,{3U,0U,6U}}, +{LSL_E168,{4U,0U,6U}}, +{LSL_E168,{5U,0U,6U}}, +{LSL_E168,{6U,0U,6U}}, +{LSL_E168,{7U,0U,6U}}, +{ROXL_E170,{0U,0U,6U}}, +{ROXL_E170,{1U,0U,6U}}, +{ROXL_E170,{2U,0U,6U}}, +{ROXL_E170,{3U,0U,6U}}, +{ROXL_E170,{4U,0U,6U}}, +{ROXL_E170,{5U,0U,6U}}, +{ROXL_E170,{6U,0U,6U}}, +{ROXL_E170,{7U,0U,6U}}, +{ROL_E178,{0U,0U,6U}}, +{ROL_E178,{1U,0U,6U}}, +{ROL_E178,{2U,0U,6U}}, +{ROL_E178,{3U,0U,6U}}, +{ROL_E178,{4U,0U,6U}}, +{ROL_E178,{5U,0U,6U}}, +{ROL_E178,{6U,0U,6U}}, +{ROL_E178,{7U,0U,6U}}, +{ASL_E180,{0U,8U,8U}}, +{ASL_E180,{1U,8U,8U}}, +{ASL_E180,{2U,8U,8U}}, +{ASL_E180,{3U,8U,8U}}, +{ASL_E180,{4U,8U,8U}}, +{ASL_E180,{5U,8U,8U}}, +{ASL_E180,{6U,8U,8U}}, +{ASL_E180,{7U,8U,8U}}, +{LSL_E188,{0U,8U,8U}}, +{LSL_E188,{1U,8U,8U}}, +{LSL_E188,{2U,8U,8U}}, +{LSL_E188,{3U,8U,8U}}, +{LSL_E188,{4U,8U,8U}}, +{LSL_E188,{5U,8U,8U}}, +{LSL_E188,{6U,8U,8U}}, +{LSL_E188,{7U,8U,8U}}, +{ROXL_E190,{0U,8U,8U}}, +{ROXL_E190,{1U,8U,8U}}, +{ROXL_E190,{2U,8U,8U}}, +{ROXL_E190,{3U,8U,8U}}, +{ROXL_E190,{4U,8U,8U}}, +{ROXL_E190,{5U,8U,8U}}, +{ROXL_E190,{6U,8U,8U}}, +{ROXL_E190,{7U,8U,8U}}, +{ROL_E198,{0U,8U,8U}}, +{ROL_E198,{1U,8U,8U}}, +{ROL_E198,{2U,8U,8U}}, +{ROL_E198,{3U,8U,8U}}, +{ROL_E198,{4U,8U,8U}}, +{ROL_E198,{5U,8U,8U}}, +{ROL_E198,{6U,8U,8U}}, +{ROL_E198,{7U,8U,8U}}, +{ASL_E1A0,{0U,0U,8U}}, +{ASL_E1A0,{1U,0U,8U}}, +{ASL_E1A0,{2U,0U,8U}}, +{ASL_E1A0,{3U,0U,8U}}, +{ASL_E1A0,{4U,0U,8U}}, +{ASL_E1A0,{5U,0U,8U}}, +{ASL_E1A0,{6U,0U,8U}}, +{ASL_E1A0,{7U,0U,8U}}, +{LSL_E1A8,{0U,0U,8U}}, +{LSL_E1A8,{1U,0U,8U}}, +{LSL_E1A8,{2U,0U,8U}}, +{LSL_E1A8,{3U,0U,8U}}, +{LSL_E1A8,{4U,0U,8U}}, +{LSL_E1A8,{5U,0U,8U}}, +{LSL_E1A8,{6U,0U,8U}}, +{LSL_E1A8,{7U,0U,8U}}, +{ROXL_E1B0,{0U,0U,8U}}, +{ROXL_E1B0,{1U,0U,8U}}, +{ROXL_E1B0,{2U,0U,8U}}, +{ROXL_E1B0,{3U,0U,8U}}, +{ROXL_E1B0,{4U,0U,8U}}, +{ROXL_E1B0,{5U,0U,8U}}, +{ROXL_E1B0,{6U,0U,8U}}, +{ROXL_E1B0,{7U,0U,8U}}, +{ROL_E1B8,{0U,0U,8U}}, +{ROL_E1B8,{1U,0U,8U}}, +{ROL_E1B8,{2U,0U,8U}}, +{ROL_E1B8,{3U,0U,8U}}, +{ROL_E1B8,{4U,0U,8U}}, +{ROL_E1B8,{5U,0U,8U}}, +{ROL_E1B8,{6U,0U,8U}}, +{ROL_E1B8,{7U,0U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASL_E1D0,{0U,0U,10U}}, +{ASL_E1D0,{1U,0U,10U}}, +{ASL_E1D0,{2U,0U,10U}}, +{ASL_E1D0,{3U,0U,10U}}, +{ASL_E1D0,{4U,0U,10U}}, +{ASL_E1D0,{5U,0U,10U}}, +{ASL_E1D0,{6U,0U,10U}}, +{ASL_E1D0,{7U,0U,10U}}, +{ASL_E1D8,{0U,0U,10U}}, +{ASL_E1D8,{1U,0U,10U}}, +{ASL_E1D8,{2U,0U,10U}}, +{ASL_E1D8,{3U,0U,10U}}, +{ASL_E1D8,{4U,0U,10U}}, +{ASL_E1D8,{5U,0U,10U}}, +{ASL_E1D8,{6U,0U,10U}}, +{ASL_E1D8,{7U,0U,10U}}, +{ASL_E1E0,{0U,0U,12U}}, +{ASL_E1E0,{1U,0U,12U}}, +{ASL_E1E0,{2U,0U,12U}}, +{ASL_E1E0,{3U,0U,12U}}, +{ASL_E1E0,{4U,0U,12U}}, +{ASL_E1E0,{5U,0U,12U}}, +{ASL_E1E0,{6U,0U,12U}}, +{ASL_E1E0,{7U,0U,12U}}, +{ASL_E1E8,{0U,0U,14U}}, +{ASL_E1E8,{1U,0U,14U}}, +{ASL_E1E8,{2U,0U,14U}}, +{ASL_E1E8,{3U,0U,14U}}, +{ASL_E1E8,{4U,0U,14U}}, +{ASL_E1E8,{5U,0U,14U}}, +{ASL_E1E8,{6U,0U,14U}}, +{ASL_E1E8,{7U,0U,14U}}, +{ASL_E1F0,{0U,0U,16U}}, +{ASL_E1F0,{1U,0U,16U}}, +{ASL_E1F0,{2U,0U,16U}}, +{ASL_E1F0,{3U,0U,16U}}, +{ASL_E1F0,{4U,0U,16U}}, +{ASL_E1F0,{5U,0U,16U}}, +{ASL_E1F0,{6U,0U,16U}}, +{ASL_E1F0,{7U,0U,16U}}, +{ASL_E1F8,{0U,0U,14U}}, +{ASL_E1F9,{0U,0U,18U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASR_E000,{0U,1U,6U}}, +{ASR_E000,{1U,1U,6U}}, +{ASR_E000,{2U,1U,6U}}, +{ASR_E000,{3U,1U,6U}}, +{ASR_E000,{4U,1U,6U}}, +{ASR_E000,{5U,1U,6U}}, +{ASR_E000,{6U,1U,6U}}, +{ASR_E000,{7U,1U,6U}}, +{LSR_E008,{0U,1U,6U}}, +{LSR_E008,{1U,1U,6U}}, +{LSR_E008,{2U,1U,6U}}, +{LSR_E008,{3U,1U,6U}}, +{LSR_E008,{4U,1U,6U}}, +{LSR_E008,{5U,1U,6U}}, +{LSR_E008,{6U,1U,6U}}, +{LSR_E008,{7U,1U,6U}}, +{ROXR_E010,{0U,1U,6U}}, +{ROXR_E010,{1U,1U,6U}}, +{ROXR_E010,{2U,1U,6U}}, +{ROXR_E010,{3U,1U,6U}}, +{ROXR_E010,{4U,1U,6U}}, +{ROXR_E010,{5U,1U,6U}}, +{ROXR_E010,{6U,1U,6U}}, +{ROXR_E010,{7U,1U,6U}}, +{ROR_E018,{0U,1U,6U}}, +{ROR_E018,{1U,1U,6U}}, +{ROR_E018,{2U,1U,6U}}, +{ROR_E018,{3U,1U,6U}}, +{ROR_E018,{4U,1U,6U}}, +{ROR_E018,{5U,1U,6U}}, +{ROR_E018,{6U,1U,6U}}, +{ROR_E018,{7U,1U,6U}}, +{ASR_E020,{0U,1U,6U}}, +{ASR_E020,{1U,1U,6U}}, +{ASR_E020,{2U,1U,6U}}, +{ASR_E020,{3U,1U,6U}}, +{ASR_E020,{4U,1U,6U}}, +{ASR_E020,{5U,1U,6U}}, +{ASR_E020,{6U,1U,6U}}, +{ASR_E020,{7U,1U,6U}}, +{LSR_E028,{0U,1U,6U}}, +{LSR_E028,{1U,1U,6U}}, +{LSR_E028,{2U,1U,6U}}, +{LSR_E028,{3U,1U,6U}}, +{LSR_E028,{4U,1U,6U}}, +{LSR_E028,{5U,1U,6U}}, +{LSR_E028,{6U,1U,6U}}, +{LSR_E028,{7U,1U,6U}}, +{ROXR_E030,{0U,1U,6U}}, +{ROXR_E030,{1U,1U,6U}}, +{ROXR_E030,{2U,1U,6U}}, +{ROXR_E030,{3U,1U,6U}}, +{ROXR_E030,{4U,1U,6U}}, +{ROXR_E030,{5U,1U,6U}}, +{ROXR_E030,{6U,1U,6U}}, +{ROXR_E030,{7U,1U,6U}}, +{ROR_E038,{0U,1U,6U}}, +{ROR_E038,{1U,1U,6U}}, +{ROR_E038,{2U,1U,6U}}, +{ROR_E038,{3U,1U,6U}}, +{ROR_E038,{4U,1U,6U}}, +{ROR_E038,{5U,1U,6U}}, +{ROR_E038,{6U,1U,6U}}, +{ROR_E038,{7U,1U,6U}}, +{ASR_E040,{0U,1U,6U}}, +{ASR_E040,{1U,1U,6U}}, +{ASR_E040,{2U,1U,6U}}, +{ASR_E040,{3U,1U,6U}}, +{ASR_E040,{4U,1U,6U}}, +{ASR_E040,{5U,1U,6U}}, +{ASR_E040,{6U,1U,6U}}, +{ASR_E040,{7U,1U,6U}}, +{LSR_E048,{0U,1U,6U}}, +{LSR_E048,{1U,1U,6U}}, +{LSR_E048,{2U,1U,6U}}, +{LSR_E048,{3U,1U,6U}}, +{LSR_E048,{4U,1U,6U}}, +{LSR_E048,{5U,1U,6U}}, +{LSR_E048,{6U,1U,6U}}, +{LSR_E048,{7U,1U,6U}}, +{ROXR_E050,{0U,1U,6U}}, +{ROXR_E050,{1U,1U,6U}}, +{ROXR_E050,{2U,1U,6U}}, +{ROXR_E050,{3U,1U,6U}}, +{ROXR_E050,{4U,1U,6U}}, +{ROXR_E050,{5U,1U,6U}}, +{ROXR_E050,{6U,1U,6U}}, +{ROXR_E050,{7U,1U,6U}}, +{ROR_E058,{0U,1U,6U}}, +{ROR_E058,{1U,1U,6U}}, +{ROR_E058,{2U,1U,6U}}, +{ROR_E058,{3U,1U,6U}}, +{ROR_E058,{4U,1U,6U}}, +{ROR_E058,{5U,1U,6U}}, +{ROR_E058,{6U,1U,6U}}, +{ROR_E058,{7U,1U,6U}}, +{ASR_E060,{0U,1U,6U}}, +{ASR_E060,{1U,1U,6U}}, +{ASR_E060,{2U,1U,6U}}, +{ASR_E060,{3U,1U,6U}}, +{ASR_E060,{4U,1U,6U}}, +{ASR_E060,{5U,1U,6U}}, +{ASR_E060,{6U,1U,6U}}, +{ASR_E060,{7U,1U,6U}}, +{LSR_E068,{0U,1U,6U}}, +{LSR_E068,{1U,1U,6U}}, +{LSR_E068,{2U,1U,6U}}, +{LSR_E068,{3U,1U,6U}}, +{LSR_E068,{4U,1U,6U}}, +{LSR_E068,{5U,1U,6U}}, +{LSR_E068,{6U,1U,6U}}, +{LSR_E068,{7U,1U,6U}}, +{ROXR_E070,{0U,1U,6U}}, +{ROXR_E070,{1U,1U,6U}}, +{ROXR_E070,{2U,1U,6U}}, +{ROXR_E070,{3U,1U,6U}}, +{ROXR_E070,{4U,1U,6U}}, +{ROXR_E070,{5U,1U,6U}}, +{ROXR_E070,{6U,1U,6U}}, +{ROXR_E070,{7U,1U,6U}}, +{ROR_E078,{0U,1U,6U}}, +{ROR_E078,{1U,1U,6U}}, +{ROR_E078,{2U,1U,6U}}, +{ROR_E078,{3U,1U,6U}}, +{ROR_E078,{4U,1U,6U}}, +{ROR_E078,{5U,1U,6U}}, +{ROR_E078,{6U,1U,6U}}, +{ROR_E078,{7U,1U,6U}}, +{ASR_E080,{0U,1U,8U}}, +{ASR_E080,{1U,1U,8U}}, +{ASR_E080,{2U,1U,8U}}, +{ASR_E080,{3U,1U,8U}}, +{ASR_E080,{4U,1U,8U}}, +{ASR_E080,{5U,1U,8U}}, +{ASR_E080,{6U,1U,8U}}, +{ASR_E080,{7U,1U,8U}}, +{LSR_E088,{0U,1U,8U}}, +{LSR_E088,{1U,1U,8U}}, +{LSR_E088,{2U,1U,8U}}, +{LSR_E088,{3U,1U,8U}}, +{LSR_E088,{4U,1U,8U}}, +{LSR_E088,{5U,1U,8U}}, +{LSR_E088,{6U,1U,8U}}, +{LSR_E088,{7U,1U,8U}}, +{ROXR_E090,{0U,1U,8U}}, +{ROXR_E090,{1U,1U,8U}}, +{ROXR_E090,{2U,1U,8U}}, +{ROXR_E090,{3U,1U,8U}}, +{ROXR_E090,{4U,1U,8U}}, +{ROXR_E090,{5U,1U,8U}}, +{ROXR_E090,{6U,1U,8U}}, +{ROXR_E090,{7U,1U,8U}}, +{ROR_E098,{0U,1U,8U}}, +{ROR_E098,{1U,1U,8U}}, +{ROR_E098,{2U,1U,8U}}, +{ROR_E098,{3U,1U,8U}}, +{ROR_E098,{4U,1U,8U}}, +{ROR_E098,{5U,1U,8U}}, +{ROR_E098,{6U,1U,8U}}, +{ROR_E098,{7U,1U,8U}}, +{ASR_E0A0,{0U,1U,8U}}, +{ASR_E0A0,{1U,1U,8U}}, +{ASR_E0A0,{2U,1U,8U}}, +{ASR_E0A0,{3U,1U,8U}}, +{ASR_E0A0,{4U,1U,8U}}, +{ASR_E0A0,{5U,1U,8U}}, +{ASR_E0A0,{6U,1U,8U}}, +{ASR_E0A0,{7U,1U,8U}}, +{LSR_E0A8,{0U,1U,8U}}, +{LSR_E0A8,{1U,1U,8U}}, +{LSR_E0A8,{2U,1U,8U}}, +{LSR_E0A8,{3U,1U,8U}}, +{LSR_E0A8,{4U,1U,8U}}, +{LSR_E0A8,{5U,1U,8U}}, +{LSR_E0A8,{6U,1U,8U}}, +{LSR_E0A8,{7U,1U,8U}}, +{ROXR_E0B0,{0U,1U,8U}}, +{ROXR_E0B0,{1U,1U,8U}}, +{ROXR_E0B0,{2U,1U,8U}}, +{ROXR_E0B0,{3U,1U,8U}}, +{ROXR_E0B0,{4U,1U,8U}}, +{ROXR_E0B0,{5U,1U,8U}}, +{ROXR_E0B0,{6U,1U,8U}}, +{ROXR_E0B0,{7U,1U,8U}}, +{ROR_E0B8,{0U,1U,8U}}, +{ROR_E0B8,{1U,1U,8U}}, +{ROR_E0B8,{2U,1U,8U}}, +{ROR_E0B8,{3U,1U,8U}}, +{ROR_E0B8,{4U,1U,8U}}, +{ROR_E0B8,{5U,1U,8U}}, +{ROR_E0B8,{6U,1U,8U}}, +{ROR_E0B8,{7U,1U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LSR_E2D0,{0U,0U,10U}}, +{LSR_E2D0,{1U,0U,10U}}, +{LSR_E2D0,{2U,0U,10U}}, +{LSR_E2D0,{3U,0U,10U}}, +{LSR_E2D0,{4U,0U,10U}}, +{LSR_E2D0,{5U,0U,10U}}, +{LSR_E2D0,{6U,0U,10U}}, +{LSR_E2D0,{7U,0U,10U}}, +{LSR_E2D8,{0U,0U,10U}}, +{LSR_E2D8,{1U,0U,10U}}, +{LSR_E2D8,{2U,0U,10U}}, +{LSR_E2D8,{3U,0U,10U}}, +{LSR_E2D8,{4U,0U,10U}}, +{LSR_E2D8,{5U,0U,10U}}, +{LSR_E2D8,{6U,0U,10U}}, +{LSR_E2D8,{7U,0U,10U}}, +{LSR_E2E0,{0U,0U,12U}}, +{LSR_E2E0,{1U,0U,12U}}, +{LSR_E2E0,{2U,0U,12U}}, +{LSR_E2E0,{3U,0U,12U}}, +{LSR_E2E0,{4U,0U,12U}}, +{LSR_E2E0,{5U,0U,12U}}, +{LSR_E2E0,{6U,0U,12U}}, +{LSR_E2E0,{7U,0U,12U}}, +{LSR_E2E8,{0U,0U,14U}}, +{LSR_E2E8,{1U,0U,14U}}, +{LSR_E2E8,{2U,0U,14U}}, +{LSR_E2E8,{3U,0U,14U}}, +{LSR_E2E8,{4U,0U,14U}}, +{LSR_E2E8,{5U,0U,14U}}, +{LSR_E2E8,{6U,0U,14U}}, +{LSR_E2E8,{7U,0U,14U}}, +{LSR_E2F0,{0U,0U,16U}}, +{LSR_E2F0,{1U,0U,16U}}, +{LSR_E2F0,{2U,0U,16U}}, +{LSR_E2F0,{3U,0U,16U}}, +{LSR_E2F0,{4U,0U,16U}}, +{LSR_E2F0,{5U,0U,16U}}, +{LSR_E2F0,{6U,0U,16U}}, +{LSR_E2F0,{7U,0U,16U}}, +{LSR_E2F8,{0U,0U,14U}}, +{LSR_E2F9,{0U,0U,18U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASL_E100,{0U,1U,6U}}, +{ASL_E100,{1U,1U,6U}}, +{ASL_E100,{2U,1U,6U}}, +{ASL_E100,{3U,1U,6U}}, +{ASL_E100,{4U,1U,6U}}, +{ASL_E100,{5U,1U,6U}}, +{ASL_E100,{6U,1U,6U}}, +{ASL_E100,{7U,1U,6U}}, +{LSL_E108,{0U,1U,6U}}, +{LSL_E108,{1U,1U,6U}}, +{LSL_E108,{2U,1U,6U}}, +{LSL_E108,{3U,1U,6U}}, +{LSL_E108,{4U,1U,6U}}, +{LSL_E108,{5U,1U,6U}}, +{LSL_E108,{6U,1U,6U}}, +{LSL_E108,{7U,1U,6U}}, +{ROXL_E110,{0U,1U,6U}}, +{ROXL_E110,{1U,1U,6U}}, +{ROXL_E110,{2U,1U,6U}}, +{ROXL_E110,{3U,1U,6U}}, +{ROXL_E110,{4U,1U,6U}}, +{ROXL_E110,{5U,1U,6U}}, +{ROXL_E110,{6U,1U,6U}}, +{ROXL_E110,{7U,1U,6U}}, +{ROL_E118,{0U,1U,6U}}, +{ROL_E118,{1U,1U,6U}}, +{ROL_E118,{2U,1U,6U}}, +{ROL_E118,{3U,1U,6U}}, +{ROL_E118,{4U,1U,6U}}, +{ROL_E118,{5U,1U,6U}}, +{ROL_E118,{6U,1U,6U}}, +{ROL_E118,{7U,1U,6U}}, +{ASL_E120,{0U,1U,6U}}, +{ASL_E120,{1U,1U,6U}}, +{ASL_E120,{2U,1U,6U}}, +{ASL_E120,{3U,1U,6U}}, +{ASL_E120,{4U,1U,6U}}, +{ASL_E120,{5U,1U,6U}}, +{ASL_E120,{6U,1U,6U}}, +{ASL_E120,{7U,1U,6U}}, +{LSL_E128,{0U,1U,6U}}, +{LSL_E128,{1U,1U,6U}}, +{LSL_E128,{2U,1U,6U}}, +{LSL_E128,{3U,1U,6U}}, +{LSL_E128,{4U,1U,6U}}, +{LSL_E128,{5U,1U,6U}}, +{LSL_E128,{6U,1U,6U}}, +{LSL_E128,{7U,1U,6U}}, +{ROXL_E130,{0U,1U,6U}}, +{ROXL_E130,{1U,1U,6U}}, +{ROXL_E130,{2U,1U,6U}}, +{ROXL_E130,{3U,1U,6U}}, +{ROXL_E130,{4U,1U,6U}}, +{ROXL_E130,{5U,1U,6U}}, +{ROXL_E130,{6U,1U,6U}}, +{ROXL_E130,{7U,1U,6U}}, +{ROL_E138,{0U,1U,6U}}, +{ROL_E138,{1U,1U,6U}}, +{ROL_E138,{2U,1U,6U}}, +{ROL_E138,{3U,1U,6U}}, +{ROL_E138,{4U,1U,6U}}, +{ROL_E138,{5U,1U,6U}}, +{ROL_E138,{6U,1U,6U}}, +{ROL_E138,{7U,1U,6U}}, +{ASL_E140,{0U,1U,6U}}, +{ASL_E140,{1U,1U,6U}}, +{ASL_E140,{2U,1U,6U}}, +{ASL_E140,{3U,1U,6U}}, +{ASL_E140,{4U,1U,6U}}, +{ASL_E140,{5U,1U,6U}}, +{ASL_E140,{6U,1U,6U}}, +{ASL_E140,{7U,1U,6U}}, +{LSL_E148,{0U,1U,6U}}, +{LSL_E148,{1U,1U,6U}}, +{LSL_E148,{2U,1U,6U}}, +{LSL_E148,{3U,1U,6U}}, +{LSL_E148,{4U,1U,6U}}, +{LSL_E148,{5U,1U,6U}}, +{LSL_E148,{6U,1U,6U}}, +{LSL_E148,{7U,1U,6U}}, +{ROXL_E150,{0U,1U,6U}}, +{ROXL_E150,{1U,1U,6U}}, +{ROXL_E150,{2U,1U,6U}}, +{ROXL_E150,{3U,1U,6U}}, +{ROXL_E150,{4U,1U,6U}}, +{ROXL_E150,{5U,1U,6U}}, +{ROXL_E150,{6U,1U,6U}}, +{ROXL_E150,{7U,1U,6U}}, +{ROL_E158,{0U,1U,6U}}, +{ROL_E158,{1U,1U,6U}}, +{ROL_E158,{2U,1U,6U}}, +{ROL_E158,{3U,1U,6U}}, +{ROL_E158,{4U,1U,6U}}, +{ROL_E158,{5U,1U,6U}}, +{ROL_E158,{6U,1U,6U}}, +{ROL_E158,{7U,1U,6U}}, +{ASL_E160,{0U,1U,6U}}, +{ASL_E160,{1U,1U,6U}}, +{ASL_E160,{2U,1U,6U}}, +{ASL_E160,{3U,1U,6U}}, +{ASL_E160,{4U,1U,6U}}, +{ASL_E160,{5U,1U,6U}}, +{ASL_E160,{6U,1U,6U}}, +{ASL_E160,{7U,1U,6U}}, +{LSL_E168,{0U,1U,6U}}, +{LSL_E168,{1U,1U,6U}}, +{LSL_E168,{2U,1U,6U}}, +{LSL_E168,{3U,1U,6U}}, +{LSL_E168,{4U,1U,6U}}, +{LSL_E168,{5U,1U,6U}}, +{LSL_E168,{6U,1U,6U}}, +{LSL_E168,{7U,1U,6U}}, +{ROXL_E170,{0U,1U,6U}}, +{ROXL_E170,{1U,1U,6U}}, +{ROXL_E170,{2U,1U,6U}}, +{ROXL_E170,{3U,1U,6U}}, +{ROXL_E170,{4U,1U,6U}}, +{ROXL_E170,{5U,1U,6U}}, +{ROXL_E170,{6U,1U,6U}}, +{ROXL_E170,{7U,1U,6U}}, +{ROL_E178,{0U,1U,6U}}, +{ROL_E178,{1U,1U,6U}}, +{ROL_E178,{2U,1U,6U}}, +{ROL_E178,{3U,1U,6U}}, +{ROL_E178,{4U,1U,6U}}, +{ROL_E178,{5U,1U,6U}}, +{ROL_E178,{6U,1U,6U}}, +{ROL_E178,{7U,1U,6U}}, +{ASL_E180,{0U,1U,8U}}, +{ASL_E180,{1U,1U,8U}}, +{ASL_E180,{2U,1U,8U}}, +{ASL_E180,{3U,1U,8U}}, +{ASL_E180,{4U,1U,8U}}, +{ASL_E180,{5U,1U,8U}}, +{ASL_E180,{6U,1U,8U}}, +{ASL_E180,{7U,1U,8U}}, +{LSL_E188,{0U,1U,8U}}, +{LSL_E188,{1U,1U,8U}}, +{LSL_E188,{2U,1U,8U}}, +{LSL_E188,{3U,1U,8U}}, +{LSL_E188,{4U,1U,8U}}, +{LSL_E188,{5U,1U,8U}}, +{LSL_E188,{6U,1U,8U}}, +{LSL_E188,{7U,1U,8U}}, +{ROXL_E190,{0U,1U,8U}}, +{ROXL_E190,{1U,1U,8U}}, +{ROXL_E190,{2U,1U,8U}}, +{ROXL_E190,{3U,1U,8U}}, +{ROXL_E190,{4U,1U,8U}}, +{ROXL_E190,{5U,1U,8U}}, +{ROXL_E190,{6U,1U,8U}}, +{ROXL_E190,{7U,1U,8U}}, +{ROL_E198,{0U,1U,8U}}, +{ROL_E198,{1U,1U,8U}}, +{ROL_E198,{2U,1U,8U}}, +{ROL_E198,{3U,1U,8U}}, +{ROL_E198,{4U,1U,8U}}, +{ROL_E198,{5U,1U,8U}}, +{ROL_E198,{6U,1U,8U}}, +{ROL_E198,{7U,1U,8U}}, +{ASL_E1A0,{0U,1U,8U}}, +{ASL_E1A0,{1U,1U,8U}}, +{ASL_E1A0,{2U,1U,8U}}, +{ASL_E1A0,{3U,1U,8U}}, +{ASL_E1A0,{4U,1U,8U}}, +{ASL_E1A0,{5U,1U,8U}}, +{ASL_E1A0,{6U,1U,8U}}, +{ASL_E1A0,{7U,1U,8U}}, +{LSL_E1A8,{0U,1U,8U}}, +{LSL_E1A8,{1U,1U,8U}}, +{LSL_E1A8,{2U,1U,8U}}, +{LSL_E1A8,{3U,1U,8U}}, +{LSL_E1A8,{4U,1U,8U}}, +{LSL_E1A8,{5U,1U,8U}}, +{LSL_E1A8,{6U,1U,8U}}, +{LSL_E1A8,{7U,1U,8U}}, +{ROXL_E1B0,{0U,1U,8U}}, +{ROXL_E1B0,{1U,1U,8U}}, +{ROXL_E1B0,{2U,1U,8U}}, +{ROXL_E1B0,{3U,1U,8U}}, +{ROXL_E1B0,{4U,1U,8U}}, +{ROXL_E1B0,{5U,1U,8U}}, +{ROXL_E1B0,{6U,1U,8U}}, +{ROXL_E1B0,{7U,1U,8U}}, +{ROL_E1B8,{0U,1U,8U}}, +{ROL_E1B8,{1U,1U,8U}}, +{ROL_E1B8,{2U,1U,8U}}, +{ROL_E1B8,{3U,1U,8U}}, +{ROL_E1B8,{4U,1U,8U}}, +{ROL_E1B8,{5U,1U,8U}}, +{ROL_E1B8,{6U,1U,8U}}, +{ROL_E1B8,{7U,1U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{LSL_E3D0,{0U,0U,10U}}, +{LSL_E3D0,{1U,0U,10U}}, +{LSL_E3D0,{2U,0U,10U}}, +{LSL_E3D0,{3U,0U,10U}}, +{LSL_E3D0,{4U,0U,10U}}, +{LSL_E3D0,{5U,0U,10U}}, +{LSL_E3D0,{6U,0U,10U}}, +{LSL_E3D0,{7U,0U,10U}}, +{LSL_E3D8,{0U,0U,10U}}, +{LSL_E3D8,{1U,0U,10U}}, +{LSL_E3D8,{2U,0U,10U}}, +{LSL_E3D8,{3U,0U,10U}}, +{LSL_E3D8,{4U,0U,10U}}, +{LSL_E3D8,{5U,0U,10U}}, +{LSL_E3D8,{6U,0U,10U}}, +{LSL_E3D8,{7U,0U,10U}}, +{LSL_E3E0,{0U,0U,12U}}, +{LSL_E3E0,{1U,0U,12U}}, +{LSL_E3E0,{2U,0U,12U}}, +{LSL_E3E0,{3U,0U,12U}}, +{LSL_E3E0,{4U,0U,12U}}, +{LSL_E3E0,{5U,0U,12U}}, +{LSL_E3E0,{6U,0U,12U}}, +{LSL_E3E0,{7U,0U,12U}}, +{LSL_E3E8,{0U,0U,14U}}, +{LSL_E3E8,{1U,0U,14U}}, +{LSL_E3E8,{2U,0U,14U}}, +{LSL_E3E8,{3U,0U,14U}}, +{LSL_E3E8,{4U,0U,14U}}, +{LSL_E3E8,{5U,0U,14U}}, +{LSL_E3E8,{6U,0U,14U}}, +{LSL_E3E8,{7U,0U,14U}}, +{LSL_E3F0,{0U,0U,16U}}, +{LSL_E3F0,{1U,0U,16U}}, +{LSL_E3F0,{2U,0U,16U}}, +{LSL_E3F0,{3U,0U,16U}}, +{LSL_E3F0,{4U,0U,16U}}, +{LSL_E3F0,{5U,0U,16U}}, +{LSL_E3F0,{6U,0U,16U}}, +{LSL_E3F0,{7U,0U,16U}}, +{LSL_E3F8,{0U,0U,14U}}, +{LSL_E3F9,{0U,0U,18U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASR_E000,{0U,2U,6U}}, +{ASR_E000,{1U,2U,6U}}, +{ASR_E000,{2U,2U,6U}}, +{ASR_E000,{3U,2U,6U}}, +{ASR_E000,{4U,2U,6U}}, +{ASR_E000,{5U,2U,6U}}, +{ASR_E000,{6U,2U,6U}}, +{ASR_E000,{7U,2U,6U}}, +{LSR_E008,{0U,2U,6U}}, +{LSR_E008,{1U,2U,6U}}, +{LSR_E008,{2U,2U,6U}}, +{LSR_E008,{3U,2U,6U}}, +{LSR_E008,{4U,2U,6U}}, +{LSR_E008,{5U,2U,6U}}, +{LSR_E008,{6U,2U,6U}}, +{LSR_E008,{7U,2U,6U}}, +{ROXR_E010,{0U,2U,6U}}, +{ROXR_E010,{1U,2U,6U}}, +{ROXR_E010,{2U,2U,6U}}, +{ROXR_E010,{3U,2U,6U}}, +{ROXR_E010,{4U,2U,6U}}, +{ROXR_E010,{5U,2U,6U}}, +{ROXR_E010,{6U,2U,6U}}, +{ROXR_E010,{7U,2U,6U}}, +{ROR_E018,{0U,2U,6U}}, +{ROR_E018,{1U,2U,6U}}, +{ROR_E018,{2U,2U,6U}}, +{ROR_E018,{3U,2U,6U}}, +{ROR_E018,{4U,2U,6U}}, +{ROR_E018,{5U,2U,6U}}, +{ROR_E018,{6U,2U,6U}}, +{ROR_E018,{7U,2U,6U}}, +{ASR_E020,{0U,2U,6U}}, +{ASR_E020,{1U,2U,6U}}, +{ASR_E020,{2U,2U,6U}}, +{ASR_E020,{3U,2U,6U}}, +{ASR_E020,{4U,2U,6U}}, +{ASR_E020,{5U,2U,6U}}, +{ASR_E020,{6U,2U,6U}}, +{ASR_E020,{7U,2U,6U}}, +{LSR_E028,{0U,2U,6U}}, +{LSR_E028,{1U,2U,6U}}, +{LSR_E028,{2U,2U,6U}}, +{LSR_E028,{3U,2U,6U}}, +{LSR_E028,{4U,2U,6U}}, +{LSR_E028,{5U,2U,6U}}, +{LSR_E028,{6U,2U,6U}}, +{LSR_E028,{7U,2U,6U}}, +{ROXR_E030,{0U,2U,6U}}, +{ROXR_E030,{1U,2U,6U}}, +{ROXR_E030,{2U,2U,6U}}, +{ROXR_E030,{3U,2U,6U}}, +{ROXR_E030,{4U,2U,6U}}, +{ROXR_E030,{5U,2U,6U}}, +{ROXR_E030,{6U,2U,6U}}, +{ROXR_E030,{7U,2U,6U}}, +{ROR_E038,{0U,2U,6U}}, +{ROR_E038,{1U,2U,6U}}, +{ROR_E038,{2U,2U,6U}}, +{ROR_E038,{3U,2U,6U}}, +{ROR_E038,{4U,2U,6U}}, +{ROR_E038,{5U,2U,6U}}, +{ROR_E038,{6U,2U,6U}}, +{ROR_E038,{7U,2U,6U}}, +{ASR_E040,{0U,2U,6U}}, +{ASR_E040,{1U,2U,6U}}, +{ASR_E040,{2U,2U,6U}}, +{ASR_E040,{3U,2U,6U}}, +{ASR_E040,{4U,2U,6U}}, +{ASR_E040,{5U,2U,6U}}, +{ASR_E040,{6U,2U,6U}}, +{ASR_E040,{7U,2U,6U}}, +{LSR_E048,{0U,2U,6U}}, +{LSR_E048,{1U,2U,6U}}, +{LSR_E048,{2U,2U,6U}}, +{LSR_E048,{3U,2U,6U}}, +{LSR_E048,{4U,2U,6U}}, +{LSR_E048,{5U,2U,6U}}, +{LSR_E048,{6U,2U,6U}}, +{LSR_E048,{7U,2U,6U}}, +{ROXR_E050,{0U,2U,6U}}, +{ROXR_E050,{1U,2U,6U}}, +{ROXR_E050,{2U,2U,6U}}, +{ROXR_E050,{3U,2U,6U}}, +{ROXR_E050,{4U,2U,6U}}, +{ROXR_E050,{5U,2U,6U}}, +{ROXR_E050,{6U,2U,6U}}, +{ROXR_E050,{7U,2U,6U}}, +{ROR_E058,{0U,2U,6U}}, +{ROR_E058,{1U,2U,6U}}, +{ROR_E058,{2U,2U,6U}}, +{ROR_E058,{3U,2U,6U}}, +{ROR_E058,{4U,2U,6U}}, +{ROR_E058,{5U,2U,6U}}, +{ROR_E058,{6U,2U,6U}}, +{ROR_E058,{7U,2U,6U}}, +{ASR_E060,{0U,2U,6U}}, +{ASR_E060,{1U,2U,6U}}, +{ASR_E060,{2U,2U,6U}}, +{ASR_E060,{3U,2U,6U}}, +{ASR_E060,{4U,2U,6U}}, +{ASR_E060,{5U,2U,6U}}, +{ASR_E060,{6U,2U,6U}}, +{ASR_E060,{7U,2U,6U}}, +{LSR_E068,{0U,2U,6U}}, +{LSR_E068,{1U,2U,6U}}, +{LSR_E068,{2U,2U,6U}}, +{LSR_E068,{3U,2U,6U}}, +{LSR_E068,{4U,2U,6U}}, +{LSR_E068,{5U,2U,6U}}, +{LSR_E068,{6U,2U,6U}}, +{LSR_E068,{7U,2U,6U}}, +{ROXR_E070,{0U,2U,6U}}, +{ROXR_E070,{1U,2U,6U}}, +{ROXR_E070,{2U,2U,6U}}, +{ROXR_E070,{3U,2U,6U}}, +{ROXR_E070,{4U,2U,6U}}, +{ROXR_E070,{5U,2U,6U}}, +{ROXR_E070,{6U,2U,6U}}, +{ROXR_E070,{7U,2U,6U}}, +{ROR_E078,{0U,2U,6U}}, +{ROR_E078,{1U,2U,6U}}, +{ROR_E078,{2U,2U,6U}}, +{ROR_E078,{3U,2U,6U}}, +{ROR_E078,{4U,2U,6U}}, +{ROR_E078,{5U,2U,6U}}, +{ROR_E078,{6U,2U,6U}}, +{ROR_E078,{7U,2U,6U}}, +{ASR_E080,{0U,2U,8U}}, +{ASR_E080,{1U,2U,8U}}, +{ASR_E080,{2U,2U,8U}}, +{ASR_E080,{3U,2U,8U}}, +{ASR_E080,{4U,2U,8U}}, +{ASR_E080,{5U,2U,8U}}, +{ASR_E080,{6U,2U,8U}}, +{ASR_E080,{7U,2U,8U}}, +{LSR_E088,{0U,2U,8U}}, +{LSR_E088,{1U,2U,8U}}, +{LSR_E088,{2U,2U,8U}}, +{LSR_E088,{3U,2U,8U}}, +{LSR_E088,{4U,2U,8U}}, +{LSR_E088,{5U,2U,8U}}, +{LSR_E088,{6U,2U,8U}}, +{LSR_E088,{7U,2U,8U}}, +{ROXR_E090,{0U,2U,8U}}, +{ROXR_E090,{1U,2U,8U}}, +{ROXR_E090,{2U,2U,8U}}, +{ROXR_E090,{3U,2U,8U}}, +{ROXR_E090,{4U,2U,8U}}, +{ROXR_E090,{5U,2U,8U}}, +{ROXR_E090,{6U,2U,8U}}, +{ROXR_E090,{7U,2U,8U}}, +{ROR_E098,{0U,2U,8U}}, +{ROR_E098,{1U,2U,8U}}, +{ROR_E098,{2U,2U,8U}}, +{ROR_E098,{3U,2U,8U}}, +{ROR_E098,{4U,2U,8U}}, +{ROR_E098,{5U,2U,8U}}, +{ROR_E098,{6U,2U,8U}}, +{ROR_E098,{7U,2U,8U}}, +{ASR_E0A0,{0U,2U,8U}}, +{ASR_E0A0,{1U,2U,8U}}, +{ASR_E0A0,{2U,2U,8U}}, +{ASR_E0A0,{3U,2U,8U}}, +{ASR_E0A0,{4U,2U,8U}}, +{ASR_E0A0,{5U,2U,8U}}, +{ASR_E0A0,{6U,2U,8U}}, +{ASR_E0A0,{7U,2U,8U}}, +{LSR_E0A8,{0U,2U,8U}}, +{LSR_E0A8,{1U,2U,8U}}, +{LSR_E0A8,{2U,2U,8U}}, +{LSR_E0A8,{3U,2U,8U}}, +{LSR_E0A8,{4U,2U,8U}}, +{LSR_E0A8,{5U,2U,8U}}, +{LSR_E0A8,{6U,2U,8U}}, +{LSR_E0A8,{7U,2U,8U}}, +{ROXR_E0B0,{0U,2U,8U}}, +{ROXR_E0B0,{1U,2U,8U}}, +{ROXR_E0B0,{2U,2U,8U}}, +{ROXR_E0B0,{3U,2U,8U}}, +{ROXR_E0B0,{4U,2U,8U}}, +{ROXR_E0B0,{5U,2U,8U}}, +{ROXR_E0B0,{6U,2U,8U}}, +{ROXR_E0B0,{7U,2U,8U}}, +{ROR_E0B8,{0U,2U,8U}}, +{ROR_E0B8,{1U,2U,8U}}, +{ROR_E0B8,{2U,2U,8U}}, +{ROR_E0B8,{3U,2U,8U}}, +{ROR_E0B8,{4U,2U,8U}}, +{ROR_E0B8,{5U,2U,8U}}, +{ROR_E0B8,{6U,2U,8U}}, +{ROR_E0B8,{7U,2U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ROXR_E4D0,{0U,0U,10U}}, +{ROXR_E4D0,{1U,0U,10U}}, +{ROXR_E4D0,{2U,0U,10U}}, +{ROXR_E4D0,{3U,0U,10U}}, +{ROXR_E4D0,{4U,0U,10U}}, +{ROXR_E4D0,{5U,0U,10U}}, +{ROXR_E4D0,{6U,0U,10U}}, +{ROXR_E4D0,{7U,0U,10U}}, +{ROXR_E4D8,{0U,0U,10U}}, +{ROXR_E4D8,{1U,0U,10U}}, +{ROXR_E4D8,{2U,0U,10U}}, +{ROXR_E4D8,{3U,0U,10U}}, +{ROXR_E4D8,{4U,0U,10U}}, +{ROXR_E4D8,{5U,0U,10U}}, +{ROXR_E4D8,{6U,0U,10U}}, +{ROXR_E4D8,{7U,0U,10U}}, +{ROXR_E4E0,{0U,0U,12U}}, +{ROXR_E4E0,{1U,0U,12U}}, +{ROXR_E4E0,{2U,0U,12U}}, +{ROXR_E4E0,{3U,0U,12U}}, +{ROXR_E4E0,{4U,0U,12U}}, +{ROXR_E4E0,{5U,0U,12U}}, +{ROXR_E4E0,{6U,0U,12U}}, +{ROXR_E4E0,{7U,0U,12U}}, +{ROXR_E4E8,{0U,0U,14U}}, +{ROXR_E4E8,{1U,0U,14U}}, +{ROXR_E4E8,{2U,0U,14U}}, +{ROXR_E4E8,{3U,0U,14U}}, +{ROXR_E4E8,{4U,0U,14U}}, +{ROXR_E4E8,{5U,0U,14U}}, +{ROXR_E4E8,{6U,0U,14U}}, +{ROXR_E4E8,{7U,0U,14U}}, +{ROXR_E4F0,{0U,0U,16U}}, +{ROXR_E4F0,{1U,0U,16U}}, +{ROXR_E4F0,{2U,0U,16U}}, +{ROXR_E4F0,{3U,0U,16U}}, +{ROXR_E4F0,{4U,0U,16U}}, +{ROXR_E4F0,{5U,0U,16U}}, +{ROXR_E4F0,{6U,0U,16U}}, +{ROXR_E4F0,{7U,0U,16U}}, +{ROXR_E4F8,{0U,0U,14U}}, +{ROXR_E4F9,{0U,0U,18U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASL_E100,{0U,2U,6U}}, +{ASL_E100,{1U,2U,6U}}, +{ASL_E100,{2U,2U,6U}}, +{ASL_E100,{3U,2U,6U}}, +{ASL_E100,{4U,2U,6U}}, +{ASL_E100,{5U,2U,6U}}, +{ASL_E100,{6U,2U,6U}}, +{ASL_E100,{7U,2U,6U}}, +{LSL_E108,{0U,2U,6U}}, +{LSL_E108,{1U,2U,6U}}, +{LSL_E108,{2U,2U,6U}}, +{LSL_E108,{3U,2U,6U}}, +{LSL_E108,{4U,2U,6U}}, +{LSL_E108,{5U,2U,6U}}, +{LSL_E108,{6U,2U,6U}}, +{LSL_E108,{7U,2U,6U}}, +{ROXL_E110,{0U,2U,6U}}, +{ROXL_E110,{1U,2U,6U}}, +{ROXL_E110,{2U,2U,6U}}, +{ROXL_E110,{3U,2U,6U}}, +{ROXL_E110,{4U,2U,6U}}, +{ROXL_E110,{5U,2U,6U}}, +{ROXL_E110,{6U,2U,6U}}, +{ROXL_E110,{7U,2U,6U}}, +{ROL_E118,{0U,2U,6U}}, +{ROL_E118,{1U,2U,6U}}, +{ROL_E118,{2U,2U,6U}}, +{ROL_E118,{3U,2U,6U}}, +{ROL_E118,{4U,2U,6U}}, +{ROL_E118,{5U,2U,6U}}, +{ROL_E118,{6U,2U,6U}}, +{ROL_E118,{7U,2U,6U}}, +{ASL_E120,{0U,2U,6U}}, +{ASL_E120,{1U,2U,6U}}, +{ASL_E120,{2U,2U,6U}}, +{ASL_E120,{3U,2U,6U}}, +{ASL_E120,{4U,2U,6U}}, +{ASL_E120,{5U,2U,6U}}, +{ASL_E120,{6U,2U,6U}}, +{ASL_E120,{7U,2U,6U}}, +{LSL_E128,{0U,2U,6U}}, +{LSL_E128,{1U,2U,6U}}, +{LSL_E128,{2U,2U,6U}}, +{LSL_E128,{3U,2U,6U}}, +{LSL_E128,{4U,2U,6U}}, +{LSL_E128,{5U,2U,6U}}, +{LSL_E128,{6U,2U,6U}}, +{LSL_E128,{7U,2U,6U}}, +{ROXL_E130,{0U,2U,6U}}, +{ROXL_E130,{1U,2U,6U}}, +{ROXL_E130,{2U,2U,6U}}, +{ROXL_E130,{3U,2U,6U}}, +{ROXL_E130,{4U,2U,6U}}, +{ROXL_E130,{5U,2U,6U}}, +{ROXL_E130,{6U,2U,6U}}, +{ROXL_E130,{7U,2U,6U}}, +{ROL_E138,{0U,2U,6U}}, +{ROL_E138,{1U,2U,6U}}, +{ROL_E138,{2U,2U,6U}}, +{ROL_E138,{3U,2U,6U}}, +{ROL_E138,{4U,2U,6U}}, +{ROL_E138,{5U,2U,6U}}, +{ROL_E138,{6U,2U,6U}}, +{ROL_E138,{7U,2U,6U}}, +{ASL_E140,{0U,2U,6U}}, +{ASL_E140,{1U,2U,6U}}, +{ASL_E140,{2U,2U,6U}}, +{ASL_E140,{3U,2U,6U}}, +{ASL_E140,{4U,2U,6U}}, +{ASL_E140,{5U,2U,6U}}, +{ASL_E140,{6U,2U,6U}}, +{ASL_E140,{7U,2U,6U}}, +{LSL_E148,{0U,2U,6U}}, +{LSL_E148,{1U,2U,6U}}, +{LSL_E148,{2U,2U,6U}}, +{LSL_E148,{3U,2U,6U}}, +{LSL_E148,{4U,2U,6U}}, +{LSL_E148,{5U,2U,6U}}, +{LSL_E148,{6U,2U,6U}}, +{LSL_E148,{7U,2U,6U}}, +{ROXL_E150,{0U,2U,6U}}, +{ROXL_E150,{1U,2U,6U}}, +{ROXL_E150,{2U,2U,6U}}, +{ROXL_E150,{3U,2U,6U}}, +{ROXL_E150,{4U,2U,6U}}, +{ROXL_E150,{5U,2U,6U}}, +{ROXL_E150,{6U,2U,6U}}, +{ROXL_E150,{7U,2U,6U}}, +{ROL_E158,{0U,2U,6U}}, +{ROL_E158,{1U,2U,6U}}, +{ROL_E158,{2U,2U,6U}}, +{ROL_E158,{3U,2U,6U}}, +{ROL_E158,{4U,2U,6U}}, +{ROL_E158,{5U,2U,6U}}, +{ROL_E158,{6U,2U,6U}}, +{ROL_E158,{7U,2U,6U}}, +{ASL_E160,{0U,2U,6U}}, +{ASL_E160,{1U,2U,6U}}, +{ASL_E160,{2U,2U,6U}}, +{ASL_E160,{3U,2U,6U}}, +{ASL_E160,{4U,2U,6U}}, +{ASL_E160,{5U,2U,6U}}, +{ASL_E160,{6U,2U,6U}}, +{ASL_E160,{7U,2U,6U}}, +{LSL_E168,{0U,2U,6U}}, +{LSL_E168,{1U,2U,6U}}, +{LSL_E168,{2U,2U,6U}}, +{LSL_E168,{3U,2U,6U}}, +{LSL_E168,{4U,2U,6U}}, +{LSL_E168,{5U,2U,6U}}, +{LSL_E168,{6U,2U,6U}}, +{LSL_E168,{7U,2U,6U}}, +{ROXL_E170,{0U,2U,6U}}, +{ROXL_E170,{1U,2U,6U}}, +{ROXL_E170,{2U,2U,6U}}, +{ROXL_E170,{3U,2U,6U}}, +{ROXL_E170,{4U,2U,6U}}, +{ROXL_E170,{5U,2U,6U}}, +{ROXL_E170,{6U,2U,6U}}, +{ROXL_E170,{7U,2U,6U}}, +{ROL_E178,{0U,2U,6U}}, +{ROL_E178,{1U,2U,6U}}, +{ROL_E178,{2U,2U,6U}}, +{ROL_E178,{3U,2U,6U}}, +{ROL_E178,{4U,2U,6U}}, +{ROL_E178,{5U,2U,6U}}, +{ROL_E178,{6U,2U,6U}}, +{ROL_E178,{7U,2U,6U}}, +{ASL_E180,{0U,2U,8U}}, +{ASL_E180,{1U,2U,8U}}, +{ASL_E180,{2U,2U,8U}}, +{ASL_E180,{3U,2U,8U}}, +{ASL_E180,{4U,2U,8U}}, +{ASL_E180,{5U,2U,8U}}, +{ASL_E180,{6U,2U,8U}}, +{ASL_E180,{7U,2U,8U}}, +{LSL_E188,{0U,2U,8U}}, +{LSL_E188,{1U,2U,8U}}, +{LSL_E188,{2U,2U,8U}}, +{LSL_E188,{3U,2U,8U}}, +{LSL_E188,{4U,2U,8U}}, +{LSL_E188,{5U,2U,8U}}, +{LSL_E188,{6U,2U,8U}}, +{LSL_E188,{7U,2U,8U}}, +{ROXL_E190,{0U,2U,8U}}, +{ROXL_E190,{1U,2U,8U}}, +{ROXL_E190,{2U,2U,8U}}, +{ROXL_E190,{3U,2U,8U}}, +{ROXL_E190,{4U,2U,8U}}, +{ROXL_E190,{5U,2U,8U}}, +{ROXL_E190,{6U,2U,8U}}, +{ROXL_E190,{7U,2U,8U}}, +{ROL_E198,{0U,2U,8U}}, +{ROL_E198,{1U,2U,8U}}, +{ROL_E198,{2U,2U,8U}}, +{ROL_E198,{3U,2U,8U}}, +{ROL_E198,{4U,2U,8U}}, +{ROL_E198,{5U,2U,8U}}, +{ROL_E198,{6U,2U,8U}}, +{ROL_E198,{7U,2U,8U}}, +{ASL_E1A0,{0U,2U,8U}}, +{ASL_E1A0,{1U,2U,8U}}, +{ASL_E1A0,{2U,2U,8U}}, +{ASL_E1A0,{3U,2U,8U}}, +{ASL_E1A0,{4U,2U,8U}}, +{ASL_E1A0,{5U,2U,8U}}, +{ASL_E1A0,{6U,2U,8U}}, +{ASL_E1A0,{7U,2U,8U}}, +{LSL_E1A8,{0U,2U,8U}}, +{LSL_E1A8,{1U,2U,8U}}, +{LSL_E1A8,{2U,2U,8U}}, +{LSL_E1A8,{3U,2U,8U}}, +{LSL_E1A8,{4U,2U,8U}}, +{LSL_E1A8,{5U,2U,8U}}, +{LSL_E1A8,{6U,2U,8U}}, +{LSL_E1A8,{7U,2U,8U}}, +{ROXL_E1B0,{0U,2U,8U}}, +{ROXL_E1B0,{1U,2U,8U}}, +{ROXL_E1B0,{2U,2U,8U}}, +{ROXL_E1B0,{3U,2U,8U}}, +{ROXL_E1B0,{4U,2U,8U}}, +{ROXL_E1B0,{5U,2U,8U}}, +{ROXL_E1B0,{6U,2U,8U}}, +{ROXL_E1B0,{7U,2U,8U}}, +{ROL_E1B8,{0U,2U,8U}}, +{ROL_E1B8,{1U,2U,8U}}, +{ROL_E1B8,{2U,2U,8U}}, +{ROL_E1B8,{3U,2U,8U}}, +{ROL_E1B8,{4U,2U,8U}}, +{ROL_E1B8,{5U,2U,8U}}, +{ROL_E1B8,{6U,2U,8U}}, +{ROL_E1B8,{7U,2U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ROXL_E5D0,{0U,0U,10U}}, +{ROXL_E5D0,{1U,0U,10U}}, +{ROXL_E5D0,{2U,0U,10U}}, +{ROXL_E5D0,{3U,0U,10U}}, +{ROXL_E5D0,{4U,0U,10U}}, +{ROXL_E5D0,{5U,0U,10U}}, +{ROXL_E5D0,{6U,0U,10U}}, +{ROXL_E5D0,{7U,0U,10U}}, +{ROXL_E5D8,{0U,0U,10U}}, +{ROXL_E5D8,{1U,0U,10U}}, +{ROXL_E5D8,{2U,0U,10U}}, +{ROXL_E5D8,{3U,0U,10U}}, +{ROXL_E5D8,{4U,0U,10U}}, +{ROXL_E5D8,{5U,0U,10U}}, +{ROXL_E5D8,{6U,0U,10U}}, +{ROXL_E5D8,{7U,0U,10U}}, +{ROXL_E5E0,{0U,0U,12U}}, +{ROXL_E5E0,{1U,0U,12U}}, +{ROXL_E5E0,{2U,0U,12U}}, +{ROXL_E5E0,{3U,0U,12U}}, +{ROXL_E5E0,{4U,0U,12U}}, +{ROXL_E5E0,{5U,0U,12U}}, +{ROXL_E5E0,{6U,0U,12U}}, +{ROXL_E5E0,{7U,0U,12U}}, +{ROXL_E5E8,{0U,0U,14U}}, +{ROXL_E5E8,{1U,0U,14U}}, +{ROXL_E5E8,{2U,0U,14U}}, +{ROXL_E5E8,{3U,0U,14U}}, +{ROXL_E5E8,{4U,0U,14U}}, +{ROXL_E5E8,{5U,0U,14U}}, +{ROXL_E5E8,{6U,0U,14U}}, +{ROXL_E5E8,{7U,0U,14U}}, +{ROXL_E5F0,{0U,0U,16U}}, +{ROXL_E5F0,{1U,0U,16U}}, +{ROXL_E5F0,{2U,0U,16U}}, +{ROXL_E5F0,{3U,0U,16U}}, +{ROXL_E5F0,{4U,0U,16U}}, +{ROXL_E5F0,{5U,0U,16U}}, +{ROXL_E5F0,{6U,0U,16U}}, +{ROXL_E5F0,{7U,0U,16U}}, +{ROXL_E5F8,{0U,0U,14U}}, +{ROXL_E5F9,{0U,0U,18U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASR_E000,{0U,3U,6U}}, +{ASR_E000,{1U,3U,6U}}, +{ASR_E000,{2U,3U,6U}}, +{ASR_E000,{3U,3U,6U}}, +{ASR_E000,{4U,3U,6U}}, +{ASR_E000,{5U,3U,6U}}, +{ASR_E000,{6U,3U,6U}}, +{ASR_E000,{7U,3U,6U}}, +{LSR_E008,{0U,3U,6U}}, +{LSR_E008,{1U,3U,6U}}, +{LSR_E008,{2U,3U,6U}}, +{LSR_E008,{3U,3U,6U}}, +{LSR_E008,{4U,3U,6U}}, +{LSR_E008,{5U,3U,6U}}, +{LSR_E008,{6U,3U,6U}}, +{LSR_E008,{7U,3U,6U}}, +{ROXR_E010,{0U,3U,6U}}, +{ROXR_E010,{1U,3U,6U}}, +{ROXR_E010,{2U,3U,6U}}, +{ROXR_E010,{3U,3U,6U}}, +{ROXR_E010,{4U,3U,6U}}, +{ROXR_E010,{5U,3U,6U}}, +{ROXR_E010,{6U,3U,6U}}, +{ROXR_E010,{7U,3U,6U}}, +{ROR_E018,{0U,3U,6U}}, +{ROR_E018,{1U,3U,6U}}, +{ROR_E018,{2U,3U,6U}}, +{ROR_E018,{3U,3U,6U}}, +{ROR_E018,{4U,3U,6U}}, +{ROR_E018,{5U,3U,6U}}, +{ROR_E018,{6U,3U,6U}}, +{ROR_E018,{7U,3U,6U}}, +{ASR_E020,{0U,3U,6U}}, +{ASR_E020,{1U,3U,6U}}, +{ASR_E020,{2U,3U,6U}}, +{ASR_E020,{3U,3U,6U}}, +{ASR_E020,{4U,3U,6U}}, +{ASR_E020,{5U,3U,6U}}, +{ASR_E020,{6U,3U,6U}}, +{ASR_E020,{7U,3U,6U}}, +{LSR_E028,{0U,3U,6U}}, +{LSR_E028,{1U,3U,6U}}, +{LSR_E028,{2U,3U,6U}}, +{LSR_E028,{3U,3U,6U}}, +{LSR_E028,{4U,3U,6U}}, +{LSR_E028,{5U,3U,6U}}, +{LSR_E028,{6U,3U,6U}}, +{LSR_E028,{7U,3U,6U}}, +{ROXR_E030,{0U,3U,6U}}, +{ROXR_E030,{1U,3U,6U}}, +{ROXR_E030,{2U,3U,6U}}, +{ROXR_E030,{3U,3U,6U}}, +{ROXR_E030,{4U,3U,6U}}, +{ROXR_E030,{5U,3U,6U}}, +{ROXR_E030,{6U,3U,6U}}, +{ROXR_E030,{7U,3U,6U}}, +{ROR_E038,{0U,3U,6U}}, +{ROR_E038,{1U,3U,6U}}, +{ROR_E038,{2U,3U,6U}}, +{ROR_E038,{3U,3U,6U}}, +{ROR_E038,{4U,3U,6U}}, +{ROR_E038,{5U,3U,6U}}, +{ROR_E038,{6U,3U,6U}}, +{ROR_E038,{7U,3U,6U}}, +{ASR_E040,{0U,3U,6U}}, +{ASR_E040,{1U,3U,6U}}, +{ASR_E040,{2U,3U,6U}}, +{ASR_E040,{3U,3U,6U}}, +{ASR_E040,{4U,3U,6U}}, +{ASR_E040,{5U,3U,6U}}, +{ASR_E040,{6U,3U,6U}}, +{ASR_E040,{7U,3U,6U}}, +{LSR_E048,{0U,3U,6U}}, +{LSR_E048,{1U,3U,6U}}, +{LSR_E048,{2U,3U,6U}}, +{LSR_E048,{3U,3U,6U}}, +{LSR_E048,{4U,3U,6U}}, +{LSR_E048,{5U,3U,6U}}, +{LSR_E048,{6U,3U,6U}}, +{LSR_E048,{7U,3U,6U}}, +{ROXR_E050,{0U,3U,6U}}, +{ROXR_E050,{1U,3U,6U}}, +{ROXR_E050,{2U,3U,6U}}, +{ROXR_E050,{3U,3U,6U}}, +{ROXR_E050,{4U,3U,6U}}, +{ROXR_E050,{5U,3U,6U}}, +{ROXR_E050,{6U,3U,6U}}, +{ROXR_E050,{7U,3U,6U}}, +{ROR_E058,{0U,3U,6U}}, +{ROR_E058,{1U,3U,6U}}, +{ROR_E058,{2U,3U,6U}}, +{ROR_E058,{3U,3U,6U}}, +{ROR_E058,{4U,3U,6U}}, +{ROR_E058,{5U,3U,6U}}, +{ROR_E058,{6U,3U,6U}}, +{ROR_E058,{7U,3U,6U}}, +{ASR_E060,{0U,3U,6U}}, +{ASR_E060,{1U,3U,6U}}, +{ASR_E060,{2U,3U,6U}}, +{ASR_E060,{3U,3U,6U}}, +{ASR_E060,{4U,3U,6U}}, +{ASR_E060,{5U,3U,6U}}, +{ASR_E060,{6U,3U,6U}}, +{ASR_E060,{7U,3U,6U}}, +{LSR_E068,{0U,3U,6U}}, +{LSR_E068,{1U,3U,6U}}, +{LSR_E068,{2U,3U,6U}}, +{LSR_E068,{3U,3U,6U}}, +{LSR_E068,{4U,3U,6U}}, +{LSR_E068,{5U,3U,6U}}, +{LSR_E068,{6U,3U,6U}}, +{LSR_E068,{7U,3U,6U}}, +{ROXR_E070,{0U,3U,6U}}, +{ROXR_E070,{1U,3U,6U}}, +{ROXR_E070,{2U,3U,6U}}, +{ROXR_E070,{3U,3U,6U}}, +{ROXR_E070,{4U,3U,6U}}, +{ROXR_E070,{5U,3U,6U}}, +{ROXR_E070,{6U,3U,6U}}, +{ROXR_E070,{7U,3U,6U}}, +{ROR_E078,{0U,3U,6U}}, +{ROR_E078,{1U,3U,6U}}, +{ROR_E078,{2U,3U,6U}}, +{ROR_E078,{3U,3U,6U}}, +{ROR_E078,{4U,3U,6U}}, +{ROR_E078,{5U,3U,6U}}, +{ROR_E078,{6U,3U,6U}}, +{ROR_E078,{7U,3U,6U}}, +{ASR_E080,{0U,3U,8U}}, +{ASR_E080,{1U,3U,8U}}, +{ASR_E080,{2U,3U,8U}}, +{ASR_E080,{3U,3U,8U}}, +{ASR_E080,{4U,3U,8U}}, +{ASR_E080,{5U,3U,8U}}, +{ASR_E080,{6U,3U,8U}}, +{ASR_E080,{7U,3U,8U}}, +{LSR_E088,{0U,3U,8U}}, +{LSR_E088,{1U,3U,8U}}, +{LSR_E088,{2U,3U,8U}}, +{LSR_E088,{3U,3U,8U}}, +{LSR_E088,{4U,3U,8U}}, +{LSR_E088,{5U,3U,8U}}, +{LSR_E088,{6U,3U,8U}}, +{LSR_E088,{7U,3U,8U}}, +{ROXR_E090,{0U,3U,8U}}, +{ROXR_E090,{1U,3U,8U}}, +{ROXR_E090,{2U,3U,8U}}, +{ROXR_E090,{3U,3U,8U}}, +{ROXR_E090,{4U,3U,8U}}, +{ROXR_E090,{5U,3U,8U}}, +{ROXR_E090,{6U,3U,8U}}, +{ROXR_E090,{7U,3U,8U}}, +{ROR_E098,{0U,3U,8U}}, +{ROR_E098,{1U,3U,8U}}, +{ROR_E098,{2U,3U,8U}}, +{ROR_E098,{3U,3U,8U}}, +{ROR_E098,{4U,3U,8U}}, +{ROR_E098,{5U,3U,8U}}, +{ROR_E098,{6U,3U,8U}}, +{ROR_E098,{7U,3U,8U}}, +{ASR_E0A0,{0U,3U,8U}}, +{ASR_E0A0,{1U,3U,8U}}, +{ASR_E0A0,{2U,3U,8U}}, +{ASR_E0A0,{3U,3U,8U}}, +{ASR_E0A0,{4U,3U,8U}}, +{ASR_E0A0,{5U,3U,8U}}, +{ASR_E0A0,{6U,3U,8U}}, +{ASR_E0A0,{7U,3U,8U}}, +{LSR_E0A8,{0U,3U,8U}}, +{LSR_E0A8,{1U,3U,8U}}, +{LSR_E0A8,{2U,3U,8U}}, +{LSR_E0A8,{3U,3U,8U}}, +{LSR_E0A8,{4U,3U,8U}}, +{LSR_E0A8,{5U,3U,8U}}, +{LSR_E0A8,{6U,3U,8U}}, +{LSR_E0A8,{7U,3U,8U}}, +{ROXR_E0B0,{0U,3U,8U}}, +{ROXR_E0B0,{1U,3U,8U}}, +{ROXR_E0B0,{2U,3U,8U}}, +{ROXR_E0B0,{3U,3U,8U}}, +{ROXR_E0B0,{4U,3U,8U}}, +{ROXR_E0B0,{5U,3U,8U}}, +{ROXR_E0B0,{6U,3U,8U}}, +{ROXR_E0B0,{7U,3U,8U}}, +{ROR_E0B8,{0U,3U,8U}}, +{ROR_E0B8,{1U,3U,8U}}, +{ROR_E0B8,{2U,3U,8U}}, +{ROR_E0B8,{3U,3U,8U}}, +{ROR_E0B8,{4U,3U,8U}}, +{ROR_E0B8,{5U,3U,8U}}, +{ROR_E0B8,{6U,3U,8U}}, +{ROR_E0B8,{7U,3U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ROR_E6D0,{0U,0U,10U}}, +{ROR_E6D0,{1U,0U,10U}}, +{ROR_E6D0,{2U,0U,10U}}, +{ROR_E6D0,{3U,0U,10U}}, +{ROR_E6D0,{4U,0U,10U}}, +{ROR_E6D0,{5U,0U,10U}}, +{ROR_E6D0,{6U,0U,10U}}, +{ROR_E6D0,{7U,0U,10U}}, +{ROR_E6D8,{0U,0U,10U}}, +{ROR_E6D8,{1U,0U,10U}}, +{ROR_E6D8,{2U,0U,10U}}, +{ROR_E6D8,{3U,0U,10U}}, +{ROR_E6D8,{4U,0U,10U}}, +{ROR_E6D8,{5U,0U,10U}}, +{ROR_E6D8,{6U,0U,10U}}, +{ROR_E6D8,{7U,0U,10U}}, +{ROR_E6E0,{0U,0U,12U}}, +{ROR_E6E0,{1U,0U,12U}}, +{ROR_E6E0,{2U,0U,12U}}, +{ROR_E6E0,{3U,0U,12U}}, +{ROR_E6E0,{4U,0U,12U}}, +{ROR_E6E0,{5U,0U,12U}}, +{ROR_E6E0,{6U,0U,12U}}, +{ROR_E6E0,{7U,0U,12U}}, +{ROR_E6E8,{0U,0U,14U}}, +{ROR_E6E8,{1U,0U,14U}}, +{ROR_E6E8,{2U,0U,14U}}, +{ROR_E6E8,{3U,0U,14U}}, +{ROR_E6E8,{4U,0U,14U}}, +{ROR_E6E8,{5U,0U,14U}}, +{ROR_E6E8,{6U,0U,14U}}, +{ROR_E6E8,{7U,0U,14U}}, +{ROR_E6F0,{0U,0U,16U}}, +{ROR_E6F0,{1U,0U,16U}}, +{ROR_E6F0,{2U,0U,16U}}, +{ROR_E6F0,{3U,0U,16U}}, +{ROR_E6F0,{4U,0U,16U}}, +{ROR_E6F0,{5U,0U,16U}}, +{ROR_E6F0,{6U,0U,16U}}, +{ROR_E6F0,{7U,0U,16U}}, +{ROR_E6F8,{0U,0U,14U}}, +{ROR_E6F9,{0U,0U,18U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASL_E100,{0U,3U,6U}}, +{ASL_E100,{1U,3U,6U}}, +{ASL_E100,{2U,3U,6U}}, +{ASL_E100,{3U,3U,6U}}, +{ASL_E100,{4U,3U,6U}}, +{ASL_E100,{5U,3U,6U}}, +{ASL_E100,{6U,3U,6U}}, +{ASL_E100,{7U,3U,6U}}, +{LSL_E108,{0U,3U,6U}}, +{LSL_E108,{1U,3U,6U}}, +{LSL_E108,{2U,3U,6U}}, +{LSL_E108,{3U,3U,6U}}, +{LSL_E108,{4U,3U,6U}}, +{LSL_E108,{5U,3U,6U}}, +{LSL_E108,{6U,3U,6U}}, +{LSL_E108,{7U,3U,6U}}, +{ROXL_E110,{0U,3U,6U}}, +{ROXL_E110,{1U,3U,6U}}, +{ROXL_E110,{2U,3U,6U}}, +{ROXL_E110,{3U,3U,6U}}, +{ROXL_E110,{4U,3U,6U}}, +{ROXL_E110,{5U,3U,6U}}, +{ROXL_E110,{6U,3U,6U}}, +{ROXL_E110,{7U,3U,6U}}, +{ROL_E118,{0U,3U,6U}}, +{ROL_E118,{1U,3U,6U}}, +{ROL_E118,{2U,3U,6U}}, +{ROL_E118,{3U,3U,6U}}, +{ROL_E118,{4U,3U,6U}}, +{ROL_E118,{5U,3U,6U}}, +{ROL_E118,{6U,3U,6U}}, +{ROL_E118,{7U,3U,6U}}, +{ASL_E120,{0U,3U,6U}}, +{ASL_E120,{1U,3U,6U}}, +{ASL_E120,{2U,3U,6U}}, +{ASL_E120,{3U,3U,6U}}, +{ASL_E120,{4U,3U,6U}}, +{ASL_E120,{5U,3U,6U}}, +{ASL_E120,{6U,3U,6U}}, +{ASL_E120,{7U,3U,6U}}, +{LSL_E128,{0U,3U,6U}}, +{LSL_E128,{1U,3U,6U}}, +{LSL_E128,{2U,3U,6U}}, +{LSL_E128,{3U,3U,6U}}, +{LSL_E128,{4U,3U,6U}}, +{LSL_E128,{5U,3U,6U}}, +{LSL_E128,{6U,3U,6U}}, +{LSL_E128,{7U,3U,6U}}, +{ROXL_E130,{0U,3U,6U}}, +{ROXL_E130,{1U,3U,6U}}, +{ROXL_E130,{2U,3U,6U}}, +{ROXL_E130,{3U,3U,6U}}, +{ROXL_E130,{4U,3U,6U}}, +{ROXL_E130,{5U,3U,6U}}, +{ROXL_E130,{6U,3U,6U}}, +{ROXL_E130,{7U,3U,6U}}, +{ROL_E138,{0U,3U,6U}}, +{ROL_E138,{1U,3U,6U}}, +{ROL_E138,{2U,3U,6U}}, +{ROL_E138,{3U,3U,6U}}, +{ROL_E138,{4U,3U,6U}}, +{ROL_E138,{5U,3U,6U}}, +{ROL_E138,{6U,3U,6U}}, +{ROL_E138,{7U,3U,6U}}, +{ASL_E140,{0U,3U,6U}}, +{ASL_E140,{1U,3U,6U}}, +{ASL_E140,{2U,3U,6U}}, +{ASL_E140,{3U,3U,6U}}, +{ASL_E140,{4U,3U,6U}}, +{ASL_E140,{5U,3U,6U}}, +{ASL_E140,{6U,3U,6U}}, +{ASL_E140,{7U,3U,6U}}, +{LSL_E148,{0U,3U,6U}}, +{LSL_E148,{1U,3U,6U}}, +{LSL_E148,{2U,3U,6U}}, +{LSL_E148,{3U,3U,6U}}, +{LSL_E148,{4U,3U,6U}}, +{LSL_E148,{5U,3U,6U}}, +{LSL_E148,{6U,3U,6U}}, +{LSL_E148,{7U,3U,6U}}, +{ROXL_E150,{0U,3U,6U}}, +{ROXL_E150,{1U,3U,6U}}, +{ROXL_E150,{2U,3U,6U}}, +{ROXL_E150,{3U,3U,6U}}, +{ROXL_E150,{4U,3U,6U}}, +{ROXL_E150,{5U,3U,6U}}, +{ROXL_E150,{6U,3U,6U}}, +{ROXL_E150,{7U,3U,6U}}, +{ROL_E158,{0U,3U,6U}}, +{ROL_E158,{1U,3U,6U}}, +{ROL_E158,{2U,3U,6U}}, +{ROL_E158,{3U,3U,6U}}, +{ROL_E158,{4U,3U,6U}}, +{ROL_E158,{5U,3U,6U}}, +{ROL_E158,{6U,3U,6U}}, +{ROL_E158,{7U,3U,6U}}, +{ASL_E160,{0U,3U,6U}}, +{ASL_E160,{1U,3U,6U}}, +{ASL_E160,{2U,3U,6U}}, +{ASL_E160,{3U,3U,6U}}, +{ASL_E160,{4U,3U,6U}}, +{ASL_E160,{5U,3U,6U}}, +{ASL_E160,{6U,3U,6U}}, +{ASL_E160,{7U,3U,6U}}, +{LSL_E168,{0U,3U,6U}}, +{LSL_E168,{1U,3U,6U}}, +{LSL_E168,{2U,3U,6U}}, +{LSL_E168,{3U,3U,6U}}, +{LSL_E168,{4U,3U,6U}}, +{LSL_E168,{5U,3U,6U}}, +{LSL_E168,{6U,3U,6U}}, +{LSL_E168,{7U,3U,6U}}, +{ROXL_E170,{0U,3U,6U}}, +{ROXL_E170,{1U,3U,6U}}, +{ROXL_E170,{2U,3U,6U}}, +{ROXL_E170,{3U,3U,6U}}, +{ROXL_E170,{4U,3U,6U}}, +{ROXL_E170,{5U,3U,6U}}, +{ROXL_E170,{6U,3U,6U}}, +{ROXL_E170,{7U,3U,6U}}, +{ROL_E178,{0U,3U,6U}}, +{ROL_E178,{1U,3U,6U}}, +{ROL_E178,{2U,3U,6U}}, +{ROL_E178,{3U,3U,6U}}, +{ROL_E178,{4U,3U,6U}}, +{ROL_E178,{5U,3U,6U}}, +{ROL_E178,{6U,3U,6U}}, +{ROL_E178,{7U,3U,6U}}, +{ASL_E180,{0U,3U,8U}}, +{ASL_E180,{1U,3U,8U}}, +{ASL_E180,{2U,3U,8U}}, +{ASL_E180,{3U,3U,8U}}, +{ASL_E180,{4U,3U,8U}}, +{ASL_E180,{5U,3U,8U}}, +{ASL_E180,{6U,3U,8U}}, +{ASL_E180,{7U,3U,8U}}, +{LSL_E188,{0U,3U,8U}}, +{LSL_E188,{1U,3U,8U}}, +{LSL_E188,{2U,3U,8U}}, +{LSL_E188,{3U,3U,8U}}, +{LSL_E188,{4U,3U,8U}}, +{LSL_E188,{5U,3U,8U}}, +{LSL_E188,{6U,3U,8U}}, +{LSL_E188,{7U,3U,8U}}, +{ROXL_E190,{0U,3U,8U}}, +{ROXL_E190,{1U,3U,8U}}, +{ROXL_E190,{2U,3U,8U}}, +{ROXL_E190,{3U,3U,8U}}, +{ROXL_E190,{4U,3U,8U}}, +{ROXL_E190,{5U,3U,8U}}, +{ROXL_E190,{6U,3U,8U}}, +{ROXL_E190,{7U,3U,8U}}, +{ROL_E198,{0U,3U,8U}}, +{ROL_E198,{1U,3U,8U}}, +{ROL_E198,{2U,3U,8U}}, +{ROL_E198,{3U,3U,8U}}, +{ROL_E198,{4U,3U,8U}}, +{ROL_E198,{5U,3U,8U}}, +{ROL_E198,{6U,3U,8U}}, +{ROL_E198,{7U,3U,8U}}, +{ASL_E1A0,{0U,3U,8U}}, +{ASL_E1A0,{1U,3U,8U}}, +{ASL_E1A0,{2U,3U,8U}}, +{ASL_E1A0,{3U,3U,8U}}, +{ASL_E1A0,{4U,3U,8U}}, +{ASL_E1A0,{5U,3U,8U}}, +{ASL_E1A0,{6U,3U,8U}}, +{ASL_E1A0,{7U,3U,8U}}, +{LSL_E1A8,{0U,3U,8U}}, +{LSL_E1A8,{1U,3U,8U}}, +{LSL_E1A8,{2U,3U,8U}}, +{LSL_E1A8,{3U,3U,8U}}, +{LSL_E1A8,{4U,3U,8U}}, +{LSL_E1A8,{5U,3U,8U}}, +{LSL_E1A8,{6U,3U,8U}}, +{LSL_E1A8,{7U,3U,8U}}, +{ROXL_E1B0,{0U,3U,8U}}, +{ROXL_E1B0,{1U,3U,8U}}, +{ROXL_E1B0,{2U,3U,8U}}, +{ROXL_E1B0,{3U,3U,8U}}, +{ROXL_E1B0,{4U,3U,8U}}, +{ROXL_E1B0,{5U,3U,8U}}, +{ROXL_E1B0,{6U,3U,8U}}, +{ROXL_E1B0,{7U,3U,8U}}, +{ROL_E1B8,{0U,3U,8U}}, +{ROL_E1B8,{1U,3U,8U}}, +{ROL_E1B8,{2U,3U,8U}}, +{ROL_E1B8,{3U,3U,8U}}, +{ROL_E1B8,{4U,3U,8U}}, +{ROL_E1B8,{5U,3U,8U}}, +{ROL_E1B8,{6U,3U,8U}}, +{ROL_E1B8,{7U,3U,8U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ROL_E7D0,{0U,0U,10U}}, +{ROL_E7D0,{1U,0U,10U}}, +{ROL_E7D0,{2U,0U,10U}}, +{ROL_E7D0,{3U,0U,10U}}, +{ROL_E7D0,{4U,0U,10U}}, +{ROL_E7D0,{5U,0U,10U}}, +{ROL_E7D0,{6U,0U,10U}}, +{ROL_E7D0,{7U,0U,10U}}, +{ROL_E7D8,{0U,0U,10U}}, +{ROL_E7D8,{1U,0U,10U}}, +{ROL_E7D8,{2U,0U,10U}}, +{ROL_E7D8,{3U,0U,10U}}, +{ROL_E7D8,{4U,0U,10U}}, +{ROL_E7D8,{5U,0U,10U}}, +{ROL_E7D8,{6U,0U,10U}}, +{ROL_E7D8,{7U,0U,10U}}, +{ROL_E7E0,{0U,0U,12U}}, +{ROL_E7E0,{1U,0U,12U}}, +{ROL_E7E0,{2U,0U,12U}}, +{ROL_E7E0,{3U,0U,12U}}, +{ROL_E7E0,{4U,0U,12U}}, +{ROL_E7E0,{5U,0U,12U}}, +{ROL_E7E0,{6U,0U,12U}}, +{ROL_E7E0,{7U,0U,12U}}, +{ROL_E7E8,{0U,0U,14U}}, +{ROL_E7E8,{1U,0U,14U}}, +{ROL_E7E8,{2U,0U,14U}}, +{ROL_E7E8,{3U,0U,14U}}, +{ROL_E7E8,{4U,0U,14U}}, +{ROL_E7E8,{5U,0U,14U}}, +{ROL_E7E8,{6U,0U,14U}}, +{ROL_E7E8,{7U,0U,14U}}, +{ROL_E7F0,{0U,0U,16U}}, +{ROL_E7F0,{1U,0U,16U}}, +{ROL_E7F0,{2U,0U,16U}}, +{ROL_E7F0,{3U,0U,16U}}, +{ROL_E7F0,{4U,0U,16U}}, +{ROL_E7F0,{5U,0U,16U}}, +{ROL_E7F0,{6U,0U,16U}}, +{ROL_E7F0,{7U,0U,16U}}, +{ROL_E7F8,{0U,0U,14U}}, +{ROL_E7F9,{0U,0U,18U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASR_E000,{0U,4U,6U}}, +{ASR_E000,{1U,4U,6U}}, +{ASR_E000,{2U,4U,6U}}, +{ASR_E000,{3U,4U,6U}}, +{ASR_E000,{4U,4U,6U}}, +{ASR_E000,{5U,4U,6U}}, +{ASR_E000,{6U,4U,6U}}, +{ASR_E000,{7U,4U,6U}}, +{LSR_E008,{0U,4U,6U}}, +{LSR_E008,{1U,4U,6U}}, +{LSR_E008,{2U,4U,6U}}, +{LSR_E008,{3U,4U,6U}}, +{LSR_E008,{4U,4U,6U}}, +{LSR_E008,{5U,4U,6U}}, +{LSR_E008,{6U,4U,6U}}, +{LSR_E008,{7U,4U,6U}}, +{ROXR_E010,{0U,4U,6U}}, +{ROXR_E010,{1U,4U,6U}}, +{ROXR_E010,{2U,4U,6U}}, +{ROXR_E010,{3U,4U,6U}}, +{ROXR_E010,{4U,4U,6U}}, +{ROXR_E010,{5U,4U,6U}}, +{ROXR_E010,{6U,4U,6U}}, +{ROXR_E010,{7U,4U,6U}}, +{ROR_E018,{0U,4U,6U}}, +{ROR_E018,{1U,4U,6U}}, +{ROR_E018,{2U,4U,6U}}, +{ROR_E018,{3U,4U,6U}}, +{ROR_E018,{4U,4U,6U}}, +{ROR_E018,{5U,4U,6U}}, +{ROR_E018,{6U,4U,6U}}, +{ROR_E018,{7U,4U,6U}}, +{ASR_E020,{0U,4U,6U}}, +{ASR_E020,{1U,4U,6U}}, +{ASR_E020,{2U,4U,6U}}, +{ASR_E020,{3U,4U,6U}}, +{ASR_E020,{4U,4U,6U}}, +{ASR_E020,{5U,4U,6U}}, +{ASR_E020,{6U,4U,6U}}, +{ASR_E020,{7U,4U,6U}}, +{LSR_E028,{0U,4U,6U}}, +{LSR_E028,{1U,4U,6U}}, +{LSR_E028,{2U,4U,6U}}, +{LSR_E028,{3U,4U,6U}}, +{LSR_E028,{4U,4U,6U}}, +{LSR_E028,{5U,4U,6U}}, +{LSR_E028,{6U,4U,6U}}, +{LSR_E028,{7U,4U,6U}}, +{ROXR_E030,{0U,4U,6U}}, +{ROXR_E030,{1U,4U,6U}}, +{ROXR_E030,{2U,4U,6U}}, +{ROXR_E030,{3U,4U,6U}}, +{ROXR_E030,{4U,4U,6U}}, +{ROXR_E030,{5U,4U,6U}}, +{ROXR_E030,{6U,4U,6U}}, +{ROXR_E030,{7U,4U,6U}}, +{ROR_E038,{0U,4U,6U}}, +{ROR_E038,{1U,4U,6U}}, +{ROR_E038,{2U,4U,6U}}, +{ROR_E038,{3U,4U,6U}}, +{ROR_E038,{4U,4U,6U}}, +{ROR_E038,{5U,4U,6U}}, +{ROR_E038,{6U,4U,6U}}, +{ROR_E038,{7U,4U,6U}}, +{ASR_E040,{0U,4U,6U}}, +{ASR_E040,{1U,4U,6U}}, +{ASR_E040,{2U,4U,6U}}, +{ASR_E040,{3U,4U,6U}}, +{ASR_E040,{4U,4U,6U}}, +{ASR_E040,{5U,4U,6U}}, +{ASR_E040,{6U,4U,6U}}, +{ASR_E040,{7U,4U,6U}}, +{LSR_E048,{0U,4U,6U}}, +{LSR_E048,{1U,4U,6U}}, +{LSR_E048,{2U,4U,6U}}, +{LSR_E048,{3U,4U,6U}}, +{LSR_E048,{4U,4U,6U}}, +{LSR_E048,{5U,4U,6U}}, +{LSR_E048,{6U,4U,6U}}, +{LSR_E048,{7U,4U,6U}}, +{ROXR_E050,{0U,4U,6U}}, +{ROXR_E050,{1U,4U,6U}}, +{ROXR_E050,{2U,4U,6U}}, +{ROXR_E050,{3U,4U,6U}}, +{ROXR_E050,{4U,4U,6U}}, +{ROXR_E050,{5U,4U,6U}}, +{ROXR_E050,{6U,4U,6U}}, +{ROXR_E050,{7U,4U,6U}}, +{ROR_E058,{0U,4U,6U}}, +{ROR_E058,{1U,4U,6U}}, +{ROR_E058,{2U,4U,6U}}, +{ROR_E058,{3U,4U,6U}}, +{ROR_E058,{4U,4U,6U}}, +{ROR_E058,{5U,4U,6U}}, +{ROR_E058,{6U,4U,6U}}, +{ROR_E058,{7U,4U,6U}}, +{ASR_E060,{0U,4U,6U}}, +{ASR_E060,{1U,4U,6U}}, +{ASR_E060,{2U,4U,6U}}, +{ASR_E060,{3U,4U,6U}}, +{ASR_E060,{4U,4U,6U}}, +{ASR_E060,{5U,4U,6U}}, +{ASR_E060,{6U,4U,6U}}, +{ASR_E060,{7U,4U,6U}}, +{LSR_E068,{0U,4U,6U}}, +{LSR_E068,{1U,4U,6U}}, +{LSR_E068,{2U,4U,6U}}, +{LSR_E068,{3U,4U,6U}}, +{LSR_E068,{4U,4U,6U}}, +{LSR_E068,{5U,4U,6U}}, +{LSR_E068,{6U,4U,6U}}, +{LSR_E068,{7U,4U,6U}}, +{ROXR_E070,{0U,4U,6U}}, +{ROXR_E070,{1U,4U,6U}}, +{ROXR_E070,{2U,4U,6U}}, +{ROXR_E070,{3U,4U,6U}}, +{ROXR_E070,{4U,4U,6U}}, +{ROXR_E070,{5U,4U,6U}}, +{ROXR_E070,{6U,4U,6U}}, +{ROXR_E070,{7U,4U,6U}}, +{ROR_E078,{0U,4U,6U}}, +{ROR_E078,{1U,4U,6U}}, +{ROR_E078,{2U,4U,6U}}, +{ROR_E078,{3U,4U,6U}}, +{ROR_E078,{4U,4U,6U}}, +{ROR_E078,{5U,4U,6U}}, +{ROR_E078,{6U,4U,6U}}, +{ROR_E078,{7U,4U,6U}}, +{ASR_E080,{0U,4U,8U}}, +{ASR_E080,{1U,4U,8U}}, +{ASR_E080,{2U,4U,8U}}, +{ASR_E080,{3U,4U,8U}}, +{ASR_E080,{4U,4U,8U}}, +{ASR_E080,{5U,4U,8U}}, +{ASR_E080,{6U,4U,8U}}, +{ASR_E080,{7U,4U,8U}}, +{LSR_E088,{0U,4U,8U}}, +{LSR_E088,{1U,4U,8U}}, +{LSR_E088,{2U,4U,8U}}, +{LSR_E088,{3U,4U,8U}}, +{LSR_E088,{4U,4U,8U}}, +{LSR_E088,{5U,4U,8U}}, +{LSR_E088,{6U,4U,8U}}, +{LSR_E088,{7U,4U,8U}}, +{ROXR_E090,{0U,4U,8U}}, +{ROXR_E090,{1U,4U,8U}}, +{ROXR_E090,{2U,4U,8U}}, +{ROXR_E090,{3U,4U,8U}}, +{ROXR_E090,{4U,4U,8U}}, +{ROXR_E090,{5U,4U,8U}}, +{ROXR_E090,{6U,4U,8U}}, +{ROXR_E090,{7U,4U,8U}}, +{ROR_E098,{0U,4U,8U}}, +{ROR_E098,{1U,4U,8U}}, +{ROR_E098,{2U,4U,8U}}, +{ROR_E098,{3U,4U,8U}}, +{ROR_E098,{4U,4U,8U}}, +{ROR_E098,{5U,4U,8U}}, +{ROR_E098,{6U,4U,8U}}, +{ROR_E098,{7U,4U,8U}}, +{ASR_E0A0,{0U,4U,8U}}, +{ASR_E0A0,{1U,4U,8U}}, +{ASR_E0A0,{2U,4U,8U}}, +{ASR_E0A0,{3U,4U,8U}}, +{ASR_E0A0,{4U,4U,8U}}, +{ASR_E0A0,{5U,4U,8U}}, +{ASR_E0A0,{6U,4U,8U}}, +{ASR_E0A0,{7U,4U,8U}}, +{LSR_E0A8,{0U,4U,8U}}, +{LSR_E0A8,{1U,4U,8U}}, +{LSR_E0A8,{2U,4U,8U}}, +{LSR_E0A8,{3U,4U,8U}}, +{LSR_E0A8,{4U,4U,8U}}, +{LSR_E0A8,{5U,4U,8U}}, +{LSR_E0A8,{6U,4U,8U}}, +{LSR_E0A8,{7U,4U,8U}}, +{ROXR_E0B0,{0U,4U,8U}}, +{ROXR_E0B0,{1U,4U,8U}}, +{ROXR_E0B0,{2U,4U,8U}}, +{ROXR_E0B0,{3U,4U,8U}}, +{ROXR_E0B0,{4U,4U,8U}}, +{ROXR_E0B0,{5U,4U,8U}}, +{ROXR_E0B0,{6U,4U,8U}}, +{ROXR_E0B0,{7U,4U,8U}}, +{ROR_E0B8,{0U,4U,8U}}, +{ROR_E0B8,{1U,4U,8U}}, +{ROR_E0B8,{2U,4U,8U}}, +{ROR_E0B8,{3U,4U,8U}}, +{ROR_E0B8,{4U,4U,8U}}, +{ROR_E0B8,{5U,4U,8U}}, +{ROR_E0B8,{6U,4U,8U}}, +{ROR_E0B8,{7U,4U,8U}}, +{BFTST_E8C0,{0U,0U,0U}}, +{BFTST_E8C0,{1U,0U,0U}}, +{BFTST_E8C0,{2U,0U,0U}}, +{BFTST_E8C0,{3U,0U,0U}}, +{BFTST_E8C0,{4U,0U,0U}}, +{BFTST_E8C0,{5U,0U,0U}}, +{BFTST_E8C0,{6U,0U,0U}}, +{BFTST_E8C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFTST_E8D0,{0U,0U,0U}}, +{BFTST_E8D0,{1U,0U,0U}}, +{BFTST_E8D0,{2U,0U,0U}}, +{BFTST_E8D0,{3U,0U,0U}}, +{BFTST_E8D0,{4U,0U,0U}}, +{BFTST_E8D0,{5U,0U,0U}}, +{BFTST_E8D0,{6U,0U,0U}}, +{BFTST_E8D0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFTST_E8E8,{0U,0U,0U}}, +{BFTST_E8E8,{1U,0U,0U}}, +{BFTST_E8E8,{2U,0U,0U}}, +{BFTST_E8E8,{3U,0U,0U}}, +{BFTST_E8E8,{4U,0U,0U}}, +{BFTST_E8E8,{5U,0U,0U}}, +{BFTST_E8E8,{6U,0U,0U}}, +{BFTST_E8E8,{7U,0U,0U}}, +{BFTST_E8F0,{0U,0U,0U}}, +{BFTST_E8F0,{1U,0U,0U}}, +{BFTST_E8F0,{2U,0U,0U}}, +{BFTST_E8F0,{3U,0U,0U}}, +{BFTST_E8F0,{4U,0U,0U}}, +{BFTST_E8F0,{5U,0U,0U}}, +{BFTST_E8F0,{6U,0U,0U}}, +{BFTST_E8F0,{7U,0U,0U}}, +{BFTST_E8F8,{0U,0U,0U}}, +{BFTST_E8F9,{0U,0U,0U}}, +{BFTST_E8FA,{0U,0U,0U}}, +{BFTST_E8FB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASL_E100,{0U,4U,6U}}, +{ASL_E100,{1U,4U,6U}}, +{ASL_E100,{2U,4U,6U}}, +{ASL_E100,{3U,4U,6U}}, +{ASL_E100,{4U,4U,6U}}, +{ASL_E100,{5U,4U,6U}}, +{ASL_E100,{6U,4U,6U}}, +{ASL_E100,{7U,4U,6U}}, +{LSL_E108,{0U,4U,6U}}, +{LSL_E108,{1U,4U,6U}}, +{LSL_E108,{2U,4U,6U}}, +{LSL_E108,{3U,4U,6U}}, +{LSL_E108,{4U,4U,6U}}, +{LSL_E108,{5U,4U,6U}}, +{LSL_E108,{6U,4U,6U}}, +{LSL_E108,{7U,4U,6U}}, +{ROXL_E110,{0U,4U,6U}}, +{ROXL_E110,{1U,4U,6U}}, +{ROXL_E110,{2U,4U,6U}}, +{ROXL_E110,{3U,4U,6U}}, +{ROXL_E110,{4U,4U,6U}}, +{ROXL_E110,{5U,4U,6U}}, +{ROXL_E110,{6U,4U,6U}}, +{ROXL_E110,{7U,4U,6U}}, +{ROL_E118,{0U,4U,6U}}, +{ROL_E118,{1U,4U,6U}}, +{ROL_E118,{2U,4U,6U}}, +{ROL_E118,{3U,4U,6U}}, +{ROL_E118,{4U,4U,6U}}, +{ROL_E118,{5U,4U,6U}}, +{ROL_E118,{6U,4U,6U}}, +{ROL_E118,{7U,4U,6U}}, +{ASL_E120,{0U,4U,6U}}, +{ASL_E120,{1U,4U,6U}}, +{ASL_E120,{2U,4U,6U}}, +{ASL_E120,{3U,4U,6U}}, +{ASL_E120,{4U,4U,6U}}, +{ASL_E120,{5U,4U,6U}}, +{ASL_E120,{6U,4U,6U}}, +{ASL_E120,{7U,4U,6U}}, +{LSL_E128,{0U,4U,6U}}, +{LSL_E128,{1U,4U,6U}}, +{LSL_E128,{2U,4U,6U}}, +{LSL_E128,{3U,4U,6U}}, +{LSL_E128,{4U,4U,6U}}, +{LSL_E128,{5U,4U,6U}}, +{LSL_E128,{6U,4U,6U}}, +{LSL_E128,{7U,4U,6U}}, +{ROXL_E130,{0U,4U,6U}}, +{ROXL_E130,{1U,4U,6U}}, +{ROXL_E130,{2U,4U,6U}}, +{ROXL_E130,{3U,4U,6U}}, +{ROXL_E130,{4U,4U,6U}}, +{ROXL_E130,{5U,4U,6U}}, +{ROXL_E130,{6U,4U,6U}}, +{ROXL_E130,{7U,4U,6U}}, +{ROL_E138,{0U,4U,6U}}, +{ROL_E138,{1U,4U,6U}}, +{ROL_E138,{2U,4U,6U}}, +{ROL_E138,{3U,4U,6U}}, +{ROL_E138,{4U,4U,6U}}, +{ROL_E138,{5U,4U,6U}}, +{ROL_E138,{6U,4U,6U}}, +{ROL_E138,{7U,4U,6U}}, +{ASL_E140,{0U,4U,6U}}, +{ASL_E140,{1U,4U,6U}}, +{ASL_E140,{2U,4U,6U}}, +{ASL_E140,{3U,4U,6U}}, +{ASL_E140,{4U,4U,6U}}, +{ASL_E140,{5U,4U,6U}}, +{ASL_E140,{6U,4U,6U}}, +{ASL_E140,{7U,4U,6U}}, +{LSL_E148,{0U,4U,6U}}, +{LSL_E148,{1U,4U,6U}}, +{LSL_E148,{2U,4U,6U}}, +{LSL_E148,{3U,4U,6U}}, +{LSL_E148,{4U,4U,6U}}, +{LSL_E148,{5U,4U,6U}}, +{LSL_E148,{6U,4U,6U}}, +{LSL_E148,{7U,4U,6U}}, +{ROXL_E150,{0U,4U,6U}}, +{ROXL_E150,{1U,4U,6U}}, +{ROXL_E150,{2U,4U,6U}}, +{ROXL_E150,{3U,4U,6U}}, +{ROXL_E150,{4U,4U,6U}}, +{ROXL_E150,{5U,4U,6U}}, +{ROXL_E150,{6U,4U,6U}}, +{ROXL_E150,{7U,4U,6U}}, +{ROL_E158,{0U,4U,6U}}, +{ROL_E158,{1U,4U,6U}}, +{ROL_E158,{2U,4U,6U}}, +{ROL_E158,{3U,4U,6U}}, +{ROL_E158,{4U,4U,6U}}, +{ROL_E158,{5U,4U,6U}}, +{ROL_E158,{6U,4U,6U}}, +{ROL_E158,{7U,4U,6U}}, +{ASL_E160,{0U,4U,6U}}, +{ASL_E160,{1U,4U,6U}}, +{ASL_E160,{2U,4U,6U}}, +{ASL_E160,{3U,4U,6U}}, +{ASL_E160,{4U,4U,6U}}, +{ASL_E160,{5U,4U,6U}}, +{ASL_E160,{6U,4U,6U}}, +{ASL_E160,{7U,4U,6U}}, +{LSL_E168,{0U,4U,6U}}, +{LSL_E168,{1U,4U,6U}}, +{LSL_E168,{2U,4U,6U}}, +{LSL_E168,{3U,4U,6U}}, +{LSL_E168,{4U,4U,6U}}, +{LSL_E168,{5U,4U,6U}}, +{LSL_E168,{6U,4U,6U}}, +{LSL_E168,{7U,4U,6U}}, +{ROXL_E170,{0U,4U,6U}}, +{ROXL_E170,{1U,4U,6U}}, +{ROXL_E170,{2U,4U,6U}}, +{ROXL_E170,{3U,4U,6U}}, +{ROXL_E170,{4U,4U,6U}}, +{ROXL_E170,{5U,4U,6U}}, +{ROXL_E170,{6U,4U,6U}}, +{ROXL_E170,{7U,4U,6U}}, +{ROL_E178,{0U,4U,6U}}, +{ROL_E178,{1U,4U,6U}}, +{ROL_E178,{2U,4U,6U}}, +{ROL_E178,{3U,4U,6U}}, +{ROL_E178,{4U,4U,6U}}, +{ROL_E178,{5U,4U,6U}}, +{ROL_E178,{6U,4U,6U}}, +{ROL_E178,{7U,4U,6U}}, +{ASL_E180,{0U,4U,8U}}, +{ASL_E180,{1U,4U,8U}}, +{ASL_E180,{2U,4U,8U}}, +{ASL_E180,{3U,4U,8U}}, +{ASL_E180,{4U,4U,8U}}, +{ASL_E180,{5U,4U,8U}}, +{ASL_E180,{6U,4U,8U}}, +{ASL_E180,{7U,4U,8U}}, +{LSL_E188,{0U,4U,8U}}, +{LSL_E188,{1U,4U,8U}}, +{LSL_E188,{2U,4U,8U}}, +{LSL_E188,{3U,4U,8U}}, +{LSL_E188,{4U,4U,8U}}, +{LSL_E188,{5U,4U,8U}}, +{LSL_E188,{6U,4U,8U}}, +{LSL_E188,{7U,4U,8U}}, +{ROXL_E190,{0U,4U,8U}}, +{ROXL_E190,{1U,4U,8U}}, +{ROXL_E190,{2U,4U,8U}}, +{ROXL_E190,{3U,4U,8U}}, +{ROXL_E190,{4U,4U,8U}}, +{ROXL_E190,{5U,4U,8U}}, +{ROXL_E190,{6U,4U,8U}}, +{ROXL_E190,{7U,4U,8U}}, +{ROL_E198,{0U,4U,8U}}, +{ROL_E198,{1U,4U,8U}}, +{ROL_E198,{2U,4U,8U}}, +{ROL_E198,{3U,4U,8U}}, +{ROL_E198,{4U,4U,8U}}, +{ROL_E198,{5U,4U,8U}}, +{ROL_E198,{6U,4U,8U}}, +{ROL_E198,{7U,4U,8U}}, +{ASL_E1A0,{0U,4U,8U}}, +{ASL_E1A0,{1U,4U,8U}}, +{ASL_E1A0,{2U,4U,8U}}, +{ASL_E1A0,{3U,4U,8U}}, +{ASL_E1A0,{4U,4U,8U}}, +{ASL_E1A0,{5U,4U,8U}}, +{ASL_E1A0,{6U,4U,8U}}, +{ASL_E1A0,{7U,4U,8U}}, +{LSL_E1A8,{0U,4U,8U}}, +{LSL_E1A8,{1U,4U,8U}}, +{LSL_E1A8,{2U,4U,8U}}, +{LSL_E1A8,{3U,4U,8U}}, +{LSL_E1A8,{4U,4U,8U}}, +{LSL_E1A8,{5U,4U,8U}}, +{LSL_E1A8,{6U,4U,8U}}, +{LSL_E1A8,{7U,4U,8U}}, +{ROXL_E1B0,{0U,4U,8U}}, +{ROXL_E1B0,{1U,4U,8U}}, +{ROXL_E1B0,{2U,4U,8U}}, +{ROXL_E1B0,{3U,4U,8U}}, +{ROXL_E1B0,{4U,4U,8U}}, +{ROXL_E1B0,{5U,4U,8U}}, +{ROXL_E1B0,{6U,4U,8U}}, +{ROXL_E1B0,{7U,4U,8U}}, +{ROL_E1B8,{0U,4U,8U}}, +{ROL_E1B8,{1U,4U,8U}}, +{ROL_E1B8,{2U,4U,8U}}, +{ROL_E1B8,{3U,4U,8U}}, +{ROL_E1B8,{4U,4U,8U}}, +{ROL_E1B8,{5U,4U,8U}}, +{ROL_E1B8,{6U,4U,8U}}, +{ROL_E1B8,{7U,4U,8U}}, +{BFEXTU_E9C0,{0U,0U,0U}}, +{BFEXTU_E9C0,{1U,0U,0U}}, +{BFEXTU_E9C0,{2U,0U,0U}}, +{BFEXTU_E9C0,{3U,0U,0U}}, +{BFEXTU_E9C0,{4U,0U,0U}}, +{BFEXTU_E9C0,{5U,0U,0U}}, +{BFEXTU_E9C0,{6U,0U,0U}}, +{BFEXTU_E9C0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFEXTU_E9D0,{0U,0U,0U}}, +{BFEXTU_E9D0,{1U,0U,0U}}, +{BFEXTU_E9D0,{2U,0U,0U}}, +{BFEXTU_E9D0,{3U,0U,0U}}, +{BFEXTU_E9D0,{4U,0U,0U}}, +{BFEXTU_E9D0,{5U,0U,0U}}, +{BFEXTU_E9D0,{6U,0U,0U}}, +{BFEXTU_E9D0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFEXTU_E9E8,{0U,0U,0U}}, +{BFEXTU_E9E8,{1U,0U,0U}}, +{BFEXTU_E9E8,{2U,0U,0U}}, +{BFEXTU_E9E8,{3U,0U,0U}}, +{BFEXTU_E9E8,{4U,0U,0U}}, +{BFEXTU_E9E8,{5U,0U,0U}}, +{BFEXTU_E9E8,{6U,0U,0U}}, +{BFEXTU_E9E8,{7U,0U,0U}}, +{BFEXTU_E9F0,{0U,0U,0U}}, +{BFEXTU_E9F0,{1U,0U,0U}}, +{BFEXTU_E9F0,{2U,0U,0U}}, +{BFEXTU_E9F0,{3U,0U,0U}}, +{BFEXTU_E9F0,{4U,0U,0U}}, +{BFEXTU_E9F0,{5U,0U,0U}}, +{BFEXTU_E9F0,{6U,0U,0U}}, +{BFEXTU_E9F0,{7U,0U,0U}}, +{BFEXTU_E9F8,{0U,0U,0U}}, +{BFEXTU_E9F9,{0U,0U,0U}}, +{BFEXTU_E9FA,{0U,0U,0U}}, +{BFEXTU_E9FB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASR_E000,{0U,5U,6U}}, +{ASR_E000,{1U,5U,6U}}, +{ASR_E000,{2U,5U,6U}}, +{ASR_E000,{3U,5U,6U}}, +{ASR_E000,{4U,5U,6U}}, +{ASR_E000,{5U,5U,6U}}, +{ASR_E000,{6U,5U,6U}}, +{ASR_E000,{7U,5U,6U}}, +{LSR_E008,{0U,5U,6U}}, +{LSR_E008,{1U,5U,6U}}, +{LSR_E008,{2U,5U,6U}}, +{LSR_E008,{3U,5U,6U}}, +{LSR_E008,{4U,5U,6U}}, +{LSR_E008,{5U,5U,6U}}, +{LSR_E008,{6U,5U,6U}}, +{LSR_E008,{7U,5U,6U}}, +{ROXR_E010,{0U,5U,6U}}, +{ROXR_E010,{1U,5U,6U}}, +{ROXR_E010,{2U,5U,6U}}, +{ROXR_E010,{3U,5U,6U}}, +{ROXR_E010,{4U,5U,6U}}, +{ROXR_E010,{5U,5U,6U}}, +{ROXR_E010,{6U,5U,6U}}, +{ROXR_E010,{7U,5U,6U}}, +{ROR_E018,{0U,5U,6U}}, +{ROR_E018,{1U,5U,6U}}, +{ROR_E018,{2U,5U,6U}}, +{ROR_E018,{3U,5U,6U}}, +{ROR_E018,{4U,5U,6U}}, +{ROR_E018,{5U,5U,6U}}, +{ROR_E018,{6U,5U,6U}}, +{ROR_E018,{7U,5U,6U}}, +{ASR_E020,{0U,5U,6U}}, +{ASR_E020,{1U,5U,6U}}, +{ASR_E020,{2U,5U,6U}}, +{ASR_E020,{3U,5U,6U}}, +{ASR_E020,{4U,5U,6U}}, +{ASR_E020,{5U,5U,6U}}, +{ASR_E020,{6U,5U,6U}}, +{ASR_E020,{7U,5U,6U}}, +{LSR_E028,{0U,5U,6U}}, +{LSR_E028,{1U,5U,6U}}, +{LSR_E028,{2U,5U,6U}}, +{LSR_E028,{3U,5U,6U}}, +{LSR_E028,{4U,5U,6U}}, +{LSR_E028,{5U,5U,6U}}, +{LSR_E028,{6U,5U,6U}}, +{LSR_E028,{7U,5U,6U}}, +{ROXR_E030,{0U,5U,6U}}, +{ROXR_E030,{1U,5U,6U}}, +{ROXR_E030,{2U,5U,6U}}, +{ROXR_E030,{3U,5U,6U}}, +{ROXR_E030,{4U,5U,6U}}, +{ROXR_E030,{5U,5U,6U}}, +{ROXR_E030,{6U,5U,6U}}, +{ROXR_E030,{7U,5U,6U}}, +{ROR_E038,{0U,5U,6U}}, +{ROR_E038,{1U,5U,6U}}, +{ROR_E038,{2U,5U,6U}}, +{ROR_E038,{3U,5U,6U}}, +{ROR_E038,{4U,5U,6U}}, +{ROR_E038,{5U,5U,6U}}, +{ROR_E038,{6U,5U,6U}}, +{ROR_E038,{7U,5U,6U}}, +{ASR_E040,{0U,5U,6U}}, +{ASR_E040,{1U,5U,6U}}, +{ASR_E040,{2U,5U,6U}}, +{ASR_E040,{3U,5U,6U}}, +{ASR_E040,{4U,5U,6U}}, +{ASR_E040,{5U,5U,6U}}, +{ASR_E040,{6U,5U,6U}}, +{ASR_E040,{7U,5U,6U}}, +{LSR_E048,{0U,5U,6U}}, +{LSR_E048,{1U,5U,6U}}, +{LSR_E048,{2U,5U,6U}}, +{LSR_E048,{3U,5U,6U}}, +{LSR_E048,{4U,5U,6U}}, +{LSR_E048,{5U,5U,6U}}, +{LSR_E048,{6U,5U,6U}}, +{LSR_E048,{7U,5U,6U}}, +{ROXR_E050,{0U,5U,6U}}, +{ROXR_E050,{1U,5U,6U}}, +{ROXR_E050,{2U,5U,6U}}, +{ROXR_E050,{3U,5U,6U}}, +{ROXR_E050,{4U,5U,6U}}, +{ROXR_E050,{5U,5U,6U}}, +{ROXR_E050,{6U,5U,6U}}, +{ROXR_E050,{7U,5U,6U}}, +{ROR_E058,{0U,5U,6U}}, +{ROR_E058,{1U,5U,6U}}, +{ROR_E058,{2U,5U,6U}}, +{ROR_E058,{3U,5U,6U}}, +{ROR_E058,{4U,5U,6U}}, +{ROR_E058,{5U,5U,6U}}, +{ROR_E058,{6U,5U,6U}}, +{ROR_E058,{7U,5U,6U}}, +{ASR_E060,{0U,5U,6U}}, +{ASR_E060,{1U,5U,6U}}, +{ASR_E060,{2U,5U,6U}}, +{ASR_E060,{3U,5U,6U}}, +{ASR_E060,{4U,5U,6U}}, +{ASR_E060,{5U,5U,6U}}, +{ASR_E060,{6U,5U,6U}}, +{ASR_E060,{7U,5U,6U}}, +{LSR_E068,{0U,5U,6U}}, +{LSR_E068,{1U,5U,6U}}, +{LSR_E068,{2U,5U,6U}}, +{LSR_E068,{3U,5U,6U}}, +{LSR_E068,{4U,5U,6U}}, +{LSR_E068,{5U,5U,6U}}, +{LSR_E068,{6U,5U,6U}}, +{LSR_E068,{7U,5U,6U}}, +{ROXR_E070,{0U,5U,6U}}, +{ROXR_E070,{1U,5U,6U}}, +{ROXR_E070,{2U,5U,6U}}, +{ROXR_E070,{3U,5U,6U}}, +{ROXR_E070,{4U,5U,6U}}, +{ROXR_E070,{5U,5U,6U}}, +{ROXR_E070,{6U,5U,6U}}, +{ROXR_E070,{7U,5U,6U}}, +{ROR_E078,{0U,5U,6U}}, +{ROR_E078,{1U,5U,6U}}, +{ROR_E078,{2U,5U,6U}}, +{ROR_E078,{3U,5U,6U}}, +{ROR_E078,{4U,5U,6U}}, +{ROR_E078,{5U,5U,6U}}, +{ROR_E078,{6U,5U,6U}}, +{ROR_E078,{7U,5U,6U}}, +{ASR_E080,{0U,5U,8U}}, +{ASR_E080,{1U,5U,8U}}, +{ASR_E080,{2U,5U,8U}}, +{ASR_E080,{3U,5U,8U}}, +{ASR_E080,{4U,5U,8U}}, +{ASR_E080,{5U,5U,8U}}, +{ASR_E080,{6U,5U,8U}}, +{ASR_E080,{7U,5U,8U}}, +{LSR_E088,{0U,5U,8U}}, +{LSR_E088,{1U,5U,8U}}, +{LSR_E088,{2U,5U,8U}}, +{LSR_E088,{3U,5U,8U}}, +{LSR_E088,{4U,5U,8U}}, +{LSR_E088,{5U,5U,8U}}, +{LSR_E088,{6U,5U,8U}}, +{LSR_E088,{7U,5U,8U}}, +{ROXR_E090,{0U,5U,8U}}, +{ROXR_E090,{1U,5U,8U}}, +{ROXR_E090,{2U,5U,8U}}, +{ROXR_E090,{3U,5U,8U}}, +{ROXR_E090,{4U,5U,8U}}, +{ROXR_E090,{5U,5U,8U}}, +{ROXR_E090,{6U,5U,8U}}, +{ROXR_E090,{7U,5U,8U}}, +{ROR_E098,{0U,5U,8U}}, +{ROR_E098,{1U,5U,8U}}, +{ROR_E098,{2U,5U,8U}}, +{ROR_E098,{3U,5U,8U}}, +{ROR_E098,{4U,5U,8U}}, +{ROR_E098,{5U,5U,8U}}, +{ROR_E098,{6U,5U,8U}}, +{ROR_E098,{7U,5U,8U}}, +{ASR_E0A0,{0U,5U,8U}}, +{ASR_E0A0,{1U,5U,8U}}, +{ASR_E0A0,{2U,5U,8U}}, +{ASR_E0A0,{3U,5U,8U}}, +{ASR_E0A0,{4U,5U,8U}}, +{ASR_E0A0,{5U,5U,8U}}, +{ASR_E0A0,{6U,5U,8U}}, +{ASR_E0A0,{7U,5U,8U}}, +{LSR_E0A8,{0U,5U,8U}}, +{LSR_E0A8,{1U,5U,8U}}, +{LSR_E0A8,{2U,5U,8U}}, +{LSR_E0A8,{3U,5U,8U}}, +{LSR_E0A8,{4U,5U,8U}}, +{LSR_E0A8,{5U,5U,8U}}, +{LSR_E0A8,{6U,5U,8U}}, +{LSR_E0A8,{7U,5U,8U}}, +{ROXR_E0B0,{0U,5U,8U}}, +{ROXR_E0B0,{1U,5U,8U}}, +{ROXR_E0B0,{2U,5U,8U}}, +{ROXR_E0B0,{3U,5U,8U}}, +{ROXR_E0B0,{4U,5U,8U}}, +{ROXR_E0B0,{5U,5U,8U}}, +{ROXR_E0B0,{6U,5U,8U}}, +{ROXR_E0B0,{7U,5U,8U}}, +{ROR_E0B8,{0U,5U,8U}}, +{ROR_E0B8,{1U,5U,8U}}, +{ROR_E0B8,{2U,5U,8U}}, +{ROR_E0B8,{3U,5U,8U}}, +{ROR_E0B8,{4U,5U,8U}}, +{ROR_E0B8,{5U,5U,8U}}, +{ROR_E0B8,{6U,5U,8U}}, +{ROR_E0B8,{7U,5U,8U}}, +{BFCHG_EAC0,{0U,0U,0U}}, +{BFCHG_EAC0,{1U,0U,0U}}, +{BFCHG_EAC0,{2U,0U,0U}}, +{BFCHG_EAC0,{3U,0U,0U}}, +{BFCHG_EAC0,{4U,0U,0U}}, +{BFCHG_EAC0,{5U,0U,0U}}, +{BFCHG_EAC0,{6U,0U,0U}}, +{BFCHG_EAC0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFCHG_EAD0,{0U,0U,0U}}, +{BFCHG_EAD0,{1U,0U,0U}}, +{BFCHG_EAD0,{2U,0U,0U}}, +{BFCHG_EAD0,{3U,0U,0U}}, +{BFCHG_EAD0,{4U,0U,0U}}, +{BFCHG_EAD0,{5U,0U,0U}}, +{BFCHG_EAD0,{6U,0U,0U}}, +{BFCHG_EAD0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFCHG_EAE8,{0U,0U,0U}}, +{BFCHG_EAE8,{1U,0U,0U}}, +{BFCHG_EAE8,{2U,0U,0U}}, +{BFCHG_EAE8,{3U,0U,0U}}, +{BFCHG_EAE8,{4U,0U,0U}}, +{BFCHG_EAE8,{5U,0U,0U}}, +{BFCHG_EAE8,{6U,0U,0U}}, +{BFCHG_EAE8,{7U,0U,0U}}, +{BFCHG_EAF0,{0U,0U,0U}}, +{BFCHG_EAF0,{1U,0U,0U}}, +{BFCHG_EAF0,{2U,0U,0U}}, +{BFCHG_EAF0,{3U,0U,0U}}, +{BFCHG_EAF0,{4U,0U,0U}}, +{BFCHG_EAF0,{5U,0U,0U}}, +{BFCHG_EAF0,{6U,0U,0U}}, +{BFCHG_EAF0,{7U,0U,0U}}, +{BFCHG_EAF8,{0U,0U,0U}}, +{BFCHG_EAF9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASL_E100,{0U,5U,6U}}, +{ASL_E100,{1U,5U,6U}}, +{ASL_E100,{2U,5U,6U}}, +{ASL_E100,{3U,5U,6U}}, +{ASL_E100,{4U,5U,6U}}, +{ASL_E100,{5U,5U,6U}}, +{ASL_E100,{6U,5U,6U}}, +{ASL_E100,{7U,5U,6U}}, +{LSL_E108,{0U,5U,6U}}, +{LSL_E108,{1U,5U,6U}}, +{LSL_E108,{2U,5U,6U}}, +{LSL_E108,{3U,5U,6U}}, +{LSL_E108,{4U,5U,6U}}, +{LSL_E108,{5U,5U,6U}}, +{LSL_E108,{6U,5U,6U}}, +{LSL_E108,{7U,5U,6U}}, +{ROXL_E110,{0U,5U,6U}}, +{ROXL_E110,{1U,5U,6U}}, +{ROXL_E110,{2U,5U,6U}}, +{ROXL_E110,{3U,5U,6U}}, +{ROXL_E110,{4U,5U,6U}}, +{ROXL_E110,{5U,5U,6U}}, +{ROXL_E110,{6U,5U,6U}}, +{ROXL_E110,{7U,5U,6U}}, +{ROL_E118,{0U,5U,6U}}, +{ROL_E118,{1U,5U,6U}}, +{ROL_E118,{2U,5U,6U}}, +{ROL_E118,{3U,5U,6U}}, +{ROL_E118,{4U,5U,6U}}, +{ROL_E118,{5U,5U,6U}}, +{ROL_E118,{6U,5U,6U}}, +{ROL_E118,{7U,5U,6U}}, +{ASL_E120,{0U,5U,6U}}, +{ASL_E120,{1U,5U,6U}}, +{ASL_E120,{2U,5U,6U}}, +{ASL_E120,{3U,5U,6U}}, +{ASL_E120,{4U,5U,6U}}, +{ASL_E120,{5U,5U,6U}}, +{ASL_E120,{6U,5U,6U}}, +{ASL_E120,{7U,5U,6U}}, +{LSL_E128,{0U,5U,6U}}, +{LSL_E128,{1U,5U,6U}}, +{LSL_E128,{2U,5U,6U}}, +{LSL_E128,{3U,5U,6U}}, +{LSL_E128,{4U,5U,6U}}, +{LSL_E128,{5U,5U,6U}}, +{LSL_E128,{6U,5U,6U}}, +{LSL_E128,{7U,5U,6U}}, +{ROXL_E130,{0U,5U,6U}}, +{ROXL_E130,{1U,5U,6U}}, +{ROXL_E130,{2U,5U,6U}}, +{ROXL_E130,{3U,5U,6U}}, +{ROXL_E130,{4U,5U,6U}}, +{ROXL_E130,{5U,5U,6U}}, +{ROXL_E130,{6U,5U,6U}}, +{ROXL_E130,{7U,5U,6U}}, +{ROL_E138,{0U,5U,6U}}, +{ROL_E138,{1U,5U,6U}}, +{ROL_E138,{2U,5U,6U}}, +{ROL_E138,{3U,5U,6U}}, +{ROL_E138,{4U,5U,6U}}, +{ROL_E138,{5U,5U,6U}}, +{ROL_E138,{6U,5U,6U}}, +{ROL_E138,{7U,5U,6U}}, +{ASL_E140,{0U,5U,6U}}, +{ASL_E140,{1U,5U,6U}}, +{ASL_E140,{2U,5U,6U}}, +{ASL_E140,{3U,5U,6U}}, +{ASL_E140,{4U,5U,6U}}, +{ASL_E140,{5U,5U,6U}}, +{ASL_E140,{6U,5U,6U}}, +{ASL_E140,{7U,5U,6U}}, +{LSL_E148,{0U,5U,6U}}, +{LSL_E148,{1U,5U,6U}}, +{LSL_E148,{2U,5U,6U}}, +{LSL_E148,{3U,5U,6U}}, +{LSL_E148,{4U,5U,6U}}, +{LSL_E148,{5U,5U,6U}}, +{LSL_E148,{6U,5U,6U}}, +{LSL_E148,{7U,5U,6U}}, +{ROXL_E150,{0U,5U,6U}}, +{ROXL_E150,{1U,5U,6U}}, +{ROXL_E150,{2U,5U,6U}}, +{ROXL_E150,{3U,5U,6U}}, +{ROXL_E150,{4U,5U,6U}}, +{ROXL_E150,{5U,5U,6U}}, +{ROXL_E150,{6U,5U,6U}}, +{ROXL_E150,{7U,5U,6U}}, +{ROL_E158,{0U,5U,6U}}, +{ROL_E158,{1U,5U,6U}}, +{ROL_E158,{2U,5U,6U}}, +{ROL_E158,{3U,5U,6U}}, +{ROL_E158,{4U,5U,6U}}, +{ROL_E158,{5U,5U,6U}}, +{ROL_E158,{6U,5U,6U}}, +{ROL_E158,{7U,5U,6U}}, +{ASL_E160,{0U,5U,6U}}, +{ASL_E160,{1U,5U,6U}}, +{ASL_E160,{2U,5U,6U}}, +{ASL_E160,{3U,5U,6U}}, +{ASL_E160,{4U,5U,6U}}, +{ASL_E160,{5U,5U,6U}}, +{ASL_E160,{6U,5U,6U}}, +{ASL_E160,{7U,5U,6U}}, +{LSL_E168,{0U,5U,6U}}, +{LSL_E168,{1U,5U,6U}}, +{LSL_E168,{2U,5U,6U}}, +{LSL_E168,{3U,5U,6U}}, +{LSL_E168,{4U,5U,6U}}, +{LSL_E168,{5U,5U,6U}}, +{LSL_E168,{6U,5U,6U}}, +{LSL_E168,{7U,5U,6U}}, +{ROXL_E170,{0U,5U,6U}}, +{ROXL_E170,{1U,5U,6U}}, +{ROXL_E170,{2U,5U,6U}}, +{ROXL_E170,{3U,5U,6U}}, +{ROXL_E170,{4U,5U,6U}}, +{ROXL_E170,{5U,5U,6U}}, +{ROXL_E170,{6U,5U,6U}}, +{ROXL_E170,{7U,5U,6U}}, +{ROL_E178,{0U,5U,6U}}, +{ROL_E178,{1U,5U,6U}}, +{ROL_E178,{2U,5U,6U}}, +{ROL_E178,{3U,5U,6U}}, +{ROL_E178,{4U,5U,6U}}, +{ROL_E178,{5U,5U,6U}}, +{ROL_E178,{6U,5U,6U}}, +{ROL_E178,{7U,5U,6U}}, +{ASL_E180,{0U,5U,8U}}, +{ASL_E180,{1U,5U,8U}}, +{ASL_E180,{2U,5U,8U}}, +{ASL_E180,{3U,5U,8U}}, +{ASL_E180,{4U,5U,8U}}, +{ASL_E180,{5U,5U,8U}}, +{ASL_E180,{6U,5U,8U}}, +{ASL_E180,{7U,5U,8U}}, +{LSL_E188,{0U,5U,8U}}, +{LSL_E188,{1U,5U,8U}}, +{LSL_E188,{2U,5U,8U}}, +{LSL_E188,{3U,5U,8U}}, +{LSL_E188,{4U,5U,8U}}, +{LSL_E188,{5U,5U,8U}}, +{LSL_E188,{6U,5U,8U}}, +{LSL_E188,{7U,5U,8U}}, +{ROXL_E190,{0U,5U,8U}}, +{ROXL_E190,{1U,5U,8U}}, +{ROXL_E190,{2U,5U,8U}}, +{ROXL_E190,{3U,5U,8U}}, +{ROXL_E190,{4U,5U,8U}}, +{ROXL_E190,{5U,5U,8U}}, +{ROXL_E190,{6U,5U,8U}}, +{ROXL_E190,{7U,5U,8U}}, +{ROL_E198,{0U,5U,8U}}, +{ROL_E198,{1U,5U,8U}}, +{ROL_E198,{2U,5U,8U}}, +{ROL_E198,{3U,5U,8U}}, +{ROL_E198,{4U,5U,8U}}, +{ROL_E198,{5U,5U,8U}}, +{ROL_E198,{6U,5U,8U}}, +{ROL_E198,{7U,5U,8U}}, +{ASL_E1A0,{0U,5U,8U}}, +{ASL_E1A0,{1U,5U,8U}}, +{ASL_E1A0,{2U,5U,8U}}, +{ASL_E1A0,{3U,5U,8U}}, +{ASL_E1A0,{4U,5U,8U}}, +{ASL_E1A0,{5U,5U,8U}}, +{ASL_E1A0,{6U,5U,8U}}, +{ASL_E1A0,{7U,5U,8U}}, +{LSL_E1A8,{0U,5U,8U}}, +{LSL_E1A8,{1U,5U,8U}}, +{LSL_E1A8,{2U,5U,8U}}, +{LSL_E1A8,{3U,5U,8U}}, +{LSL_E1A8,{4U,5U,8U}}, +{LSL_E1A8,{5U,5U,8U}}, +{LSL_E1A8,{6U,5U,8U}}, +{LSL_E1A8,{7U,5U,8U}}, +{ROXL_E1B0,{0U,5U,8U}}, +{ROXL_E1B0,{1U,5U,8U}}, +{ROXL_E1B0,{2U,5U,8U}}, +{ROXL_E1B0,{3U,5U,8U}}, +{ROXL_E1B0,{4U,5U,8U}}, +{ROXL_E1B0,{5U,5U,8U}}, +{ROXL_E1B0,{6U,5U,8U}}, +{ROXL_E1B0,{7U,5U,8U}}, +{ROL_E1B8,{0U,5U,8U}}, +{ROL_E1B8,{1U,5U,8U}}, +{ROL_E1B8,{2U,5U,8U}}, +{ROL_E1B8,{3U,5U,8U}}, +{ROL_E1B8,{4U,5U,8U}}, +{ROL_E1B8,{5U,5U,8U}}, +{ROL_E1B8,{6U,5U,8U}}, +{ROL_E1B8,{7U,5U,8U}}, +{BFEXTS_EBC0,{0U,0U,0U}}, +{BFEXTS_EBC0,{1U,0U,0U}}, +{BFEXTS_EBC0,{2U,0U,0U}}, +{BFEXTS_EBC0,{3U,0U,0U}}, +{BFEXTS_EBC0,{4U,0U,0U}}, +{BFEXTS_EBC0,{5U,0U,0U}}, +{BFEXTS_EBC0,{6U,0U,0U}}, +{BFEXTS_EBC0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFEXTS_EBD0,{0U,0U,0U}}, +{BFEXTS_EBD0,{1U,0U,0U}}, +{BFEXTS_EBD0,{2U,0U,0U}}, +{BFEXTS_EBD0,{3U,0U,0U}}, +{BFEXTS_EBD0,{4U,0U,0U}}, +{BFEXTS_EBD0,{5U,0U,0U}}, +{BFEXTS_EBD0,{6U,0U,0U}}, +{BFEXTS_EBD0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFEXTS_EBE8,{0U,0U,0U}}, +{BFEXTS_EBE8,{1U,0U,0U}}, +{BFEXTS_EBE8,{2U,0U,0U}}, +{BFEXTS_EBE8,{3U,0U,0U}}, +{BFEXTS_EBE8,{4U,0U,0U}}, +{BFEXTS_EBE8,{5U,0U,0U}}, +{BFEXTS_EBE8,{6U,0U,0U}}, +{BFEXTS_EBE8,{7U,0U,0U}}, +{BFEXTS_EBF0,{0U,0U,0U}}, +{BFEXTS_EBF0,{1U,0U,0U}}, +{BFEXTS_EBF0,{2U,0U,0U}}, +{BFEXTS_EBF0,{3U,0U,0U}}, +{BFEXTS_EBF0,{4U,0U,0U}}, +{BFEXTS_EBF0,{5U,0U,0U}}, +{BFEXTS_EBF0,{6U,0U,0U}}, +{BFEXTS_EBF0,{7U,0U,0U}}, +{BFEXTS_EBF8,{0U,0U,0U}}, +{BFEXTS_EBF9,{0U,0U,0U}}, +{BFEXTS_EBFA,{0U,0U,0U}}, +{BFEXTS_EBFB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASR_E000,{0U,6U,6U}}, +{ASR_E000,{1U,6U,6U}}, +{ASR_E000,{2U,6U,6U}}, +{ASR_E000,{3U,6U,6U}}, +{ASR_E000,{4U,6U,6U}}, +{ASR_E000,{5U,6U,6U}}, +{ASR_E000,{6U,6U,6U}}, +{ASR_E000,{7U,6U,6U}}, +{LSR_E008,{0U,6U,6U}}, +{LSR_E008,{1U,6U,6U}}, +{LSR_E008,{2U,6U,6U}}, +{LSR_E008,{3U,6U,6U}}, +{LSR_E008,{4U,6U,6U}}, +{LSR_E008,{5U,6U,6U}}, +{LSR_E008,{6U,6U,6U}}, +{LSR_E008,{7U,6U,6U}}, +{ROXR_E010,{0U,6U,6U}}, +{ROXR_E010,{1U,6U,6U}}, +{ROXR_E010,{2U,6U,6U}}, +{ROXR_E010,{3U,6U,6U}}, +{ROXR_E010,{4U,6U,6U}}, +{ROXR_E010,{5U,6U,6U}}, +{ROXR_E010,{6U,6U,6U}}, +{ROXR_E010,{7U,6U,6U}}, +{ROR_E018,{0U,6U,6U}}, +{ROR_E018,{1U,6U,6U}}, +{ROR_E018,{2U,6U,6U}}, +{ROR_E018,{3U,6U,6U}}, +{ROR_E018,{4U,6U,6U}}, +{ROR_E018,{5U,6U,6U}}, +{ROR_E018,{6U,6U,6U}}, +{ROR_E018,{7U,6U,6U}}, +{ASR_E020,{0U,6U,6U}}, +{ASR_E020,{1U,6U,6U}}, +{ASR_E020,{2U,6U,6U}}, +{ASR_E020,{3U,6U,6U}}, +{ASR_E020,{4U,6U,6U}}, +{ASR_E020,{5U,6U,6U}}, +{ASR_E020,{6U,6U,6U}}, +{ASR_E020,{7U,6U,6U}}, +{LSR_E028,{0U,6U,6U}}, +{LSR_E028,{1U,6U,6U}}, +{LSR_E028,{2U,6U,6U}}, +{LSR_E028,{3U,6U,6U}}, +{LSR_E028,{4U,6U,6U}}, +{LSR_E028,{5U,6U,6U}}, +{LSR_E028,{6U,6U,6U}}, +{LSR_E028,{7U,6U,6U}}, +{ROXR_E030,{0U,6U,6U}}, +{ROXR_E030,{1U,6U,6U}}, +{ROXR_E030,{2U,6U,6U}}, +{ROXR_E030,{3U,6U,6U}}, +{ROXR_E030,{4U,6U,6U}}, +{ROXR_E030,{5U,6U,6U}}, +{ROXR_E030,{6U,6U,6U}}, +{ROXR_E030,{7U,6U,6U}}, +{ROR_E038,{0U,6U,6U}}, +{ROR_E038,{1U,6U,6U}}, +{ROR_E038,{2U,6U,6U}}, +{ROR_E038,{3U,6U,6U}}, +{ROR_E038,{4U,6U,6U}}, +{ROR_E038,{5U,6U,6U}}, +{ROR_E038,{6U,6U,6U}}, +{ROR_E038,{7U,6U,6U}}, +{ASR_E040,{0U,6U,6U}}, +{ASR_E040,{1U,6U,6U}}, +{ASR_E040,{2U,6U,6U}}, +{ASR_E040,{3U,6U,6U}}, +{ASR_E040,{4U,6U,6U}}, +{ASR_E040,{5U,6U,6U}}, +{ASR_E040,{6U,6U,6U}}, +{ASR_E040,{7U,6U,6U}}, +{LSR_E048,{0U,6U,6U}}, +{LSR_E048,{1U,6U,6U}}, +{LSR_E048,{2U,6U,6U}}, +{LSR_E048,{3U,6U,6U}}, +{LSR_E048,{4U,6U,6U}}, +{LSR_E048,{5U,6U,6U}}, +{LSR_E048,{6U,6U,6U}}, +{LSR_E048,{7U,6U,6U}}, +{ROXR_E050,{0U,6U,6U}}, +{ROXR_E050,{1U,6U,6U}}, +{ROXR_E050,{2U,6U,6U}}, +{ROXR_E050,{3U,6U,6U}}, +{ROXR_E050,{4U,6U,6U}}, +{ROXR_E050,{5U,6U,6U}}, +{ROXR_E050,{6U,6U,6U}}, +{ROXR_E050,{7U,6U,6U}}, +{ROR_E058,{0U,6U,6U}}, +{ROR_E058,{1U,6U,6U}}, +{ROR_E058,{2U,6U,6U}}, +{ROR_E058,{3U,6U,6U}}, +{ROR_E058,{4U,6U,6U}}, +{ROR_E058,{5U,6U,6U}}, +{ROR_E058,{6U,6U,6U}}, +{ROR_E058,{7U,6U,6U}}, +{ASR_E060,{0U,6U,6U}}, +{ASR_E060,{1U,6U,6U}}, +{ASR_E060,{2U,6U,6U}}, +{ASR_E060,{3U,6U,6U}}, +{ASR_E060,{4U,6U,6U}}, +{ASR_E060,{5U,6U,6U}}, +{ASR_E060,{6U,6U,6U}}, +{ASR_E060,{7U,6U,6U}}, +{LSR_E068,{0U,6U,6U}}, +{LSR_E068,{1U,6U,6U}}, +{LSR_E068,{2U,6U,6U}}, +{LSR_E068,{3U,6U,6U}}, +{LSR_E068,{4U,6U,6U}}, +{LSR_E068,{5U,6U,6U}}, +{LSR_E068,{6U,6U,6U}}, +{LSR_E068,{7U,6U,6U}}, +{ROXR_E070,{0U,6U,6U}}, +{ROXR_E070,{1U,6U,6U}}, +{ROXR_E070,{2U,6U,6U}}, +{ROXR_E070,{3U,6U,6U}}, +{ROXR_E070,{4U,6U,6U}}, +{ROXR_E070,{5U,6U,6U}}, +{ROXR_E070,{6U,6U,6U}}, +{ROXR_E070,{7U,6U,6U}}, +{ROR_E078,{0U,6U,6U}}, +{ROR_E078,{1U,6U,6U}}, +{ROR_E078,{2U,6U,6U}}, +{ROR_E078,{3U,6U,6U}}, +{ROR_E078,{4U,6U,6U}}, +{ROR_E078,{5U,6U,6U}}, +{ROR_E078,{6U,6U,6U}}, +{ROR_E078,{7U,6U,6U}}, +{ASR_E080,{0U,6U,8U}}, +{ASR_E080,{1U,6U,8U}}, +{ASR_E080,{2U,6U,8U}}, +{ASR_E080,{3U,6U,8U}}, +{ASR_E080,{4U,6U,8U}}, +{ASR_E080,{5U,6U,8U}}, +{ASR_E080,{6U,6U,8U}}, +{ASR_E080,{7U,6U,8U}}, +{LSR_E088,{0U,6U,8U}}, +{LSR_E088,{1U,6U,8U}}, +{LSR_E088,{2U,6U,8U}}, +{LSR_E088,{3U,6U,8U}}, +{LSR_E088,{4U,6U,8U}}, +{LSR_E088,{5U,6U,8U}}, +{LSR_E088,{6U,6U,8U}}, +{LSR_E088,{7U,6U,8U}}, +{ROXR_E090,{0U,6U,8U}}, +{ROXR_E090,{1U,6U,8U}}, +{ROXR_E090,{2U,6U,8U}}, +{ROXR_E090,{3U,6U,8U}}, +{ROXR_E090,{4U,6U,8U}}, +{ROXR_E090,{5U,6U,8U}}, +{ROXR_E090,{6U,6U,8U}}, +{ROXR_E090,{7U,6U,8U}}, +{ROR_E098,{0U,6U,8U}}, +{ROR_E098,{1U,6U,8U}}, +{ROR_E098,{2U,6U,8U}}, +{ROR_E098,{3U,6U,8U}}, +{ROR_E098,{4U,6U,8U}}, +{ROR_E098,{5U,6U,8U}}, +{ROR_E098,{6U,6U,8U}}, +{ROR_E098,{7U,6U,8U}}, +{ASR_E0A0,{0U,6U,8U}}, +{ASR_E0A0,{1U,6U,8U}}, +{ASR_E0A0,{2U,6U,8U}}, +{ASR_E0A0,{3U,6U,8U}}, +{ASR_E0A0,{4U,6U,8U}}, +{ASR_E0A0,{5U,6U,8U}}, +{ASR_E0A0,{6U,6U,8U}}, +{ASR_E0A0,{7U,6U,8U}}, +{LSR_E0A8,{0U,6U,8U}}, +{LSR_E0A8,{1U,6U,8U}}, +{LSR_E0A8,{2U,6U,8U}}, +{LSR_E0A8,{3U,6U,8U}}, +{LSR_E0A8,{4U,6U,8U}}, +{LSR_E0A8,{5U,6U,8U}}, +{LSR_E0A8,{6U,6U,8U}}, +{LSR_E0A8,{7U,6U,8U}}, +{ROXR_E0B0,{0U,6U,8U}}, +{ROXR_E0B0,{1U,6U,8U}}, +{ROXR_E0B0,{2U,6U,8U}}, +{ROXR_E0B0,{3U,6U,8U}}, +{ROXR_E0B0,{4U,6U,8U}}, +{ROXR_E0B0,{5U,6U,8U}}, +{ROXR_E0B0,{6U,6U,8U}}, +{ROXR_E0B0,{7U,6U,8U}}, +{ROR_E0B8,{0U,6U,8U}}, +{ROR_E0B8,{1U,6U,8U}}, +{ROR_E0B8,{2U,6U,8U}}, +{ROR_E0B8,{3U,6U,8U}}, +{ROR_E0B8,{4U,6U,8U}}, +{ROR_E0B8,{5U,6U,8U}}, +{ROR_E0B8,{6U,6U,8U}}, +{ROR_E0B8,{7U,6U,8U}}, +{BFCLR_ECC0,{0U,0U,0U}}, +{BFCLR_ECC0,{1U,0U,0U}}, +{BFCLR_ECC0,{2U,0U,0U}}, +{BFCLR_ECC0,{3U,0U,0U}}, +{BFCLR_ECC0,{4U,0U,0U}}, +{BFCLR_ECC0,{5U,0U,0U}}, +{BFCLR_ECC0,{6U,0U,0U}}, +{BFCLR_ECC0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFCLR_ECD0,{0U,0U,0U}}, +{BFCLR_ECD0,{1U,0U,0U}}, +{BFCLR_ECD0,{2U,0U,0U}}, +{BFCLR_ECD0,{3U,0U,0U}}, +{BFCLR_ECD0,{4U,0U,0U}}, +{BFCLR_ECD0,{5U,0U,0U}}, +{BFCLR_ECD0,{6U,0U,0U}}, +{BFCLR_ECD0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFCLR_ECE8,{0U,0U,0U}}, +{BFCLR_ECE8,{1U,0U,0U}}, +{BFCLR_ECE8,{2U,0U,0U}}, +{BFCLR_ECE8,{3U,0U,0U}}, +{BFCLR_ECE8,{4U,0U,0U}}, +{BFCLR_ECE8,{5U,0U,0U}}, +{BFCLR_ECE8,{6U,0U,0U}}, +{BFCLR_ECE8,{7U,0U,0U}}, +{BFCLR_ECF0,{0U,0U,0U}}, +{BFCLR_ECF0,{1U,0U,0U}}, +{BFCLR_ECF0,{2U,0U,0U}}, +{BFCLR_ECF0,{3U,0U,0U}}, +{BFCLR_ECF0,{4U,0U,0U}}, +{BFCLR_ECF0,{5U,0U,0U}}, +{BFCLR_ECF0,{6U,0U,0U}}, +{BFCLR_ECF0,{7U,0U,0U}}, +{BFCLR_ECF8,{0U,0U,0U}}, +{BFCLR_ECF9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASL_E100,{0U,6U,6U}}, +{ASL_E100,{1U,6U,6U}}, +{ASL_E100,{2U,6U,6U}}, +{ASL_E100,{3U,6U,6U}}, +{ASL_E100,{4U,6U,6U}}, +{ASL_E100,{5U,6U,6U}}, +{ASL_E100,{6U,6U,6U}}, +{ASL_E100,{7U,6U,6U}}, +{LSL_E108,{0U,6U,6U}}, +{LSL_E108,{1U,6U,6U}}, +{LSL_E108,{2U,6U,6U}}, +{LSL_E108,{3U,6U,6U}}, +{LSL_E108,{4U,6U,6U}}, +{LSL_E108,{5U,6U,6U}}, +{LSL_E108,{6U,6U,6U}}, +{LSL_E108,{7U,6U,6U}}, +{ROXL_E110,{0U,6U,6U}}, +{ROXL_E110,{1U,6U,6U}}, +{ROXL_E110,{2U,6U,6U}}, +{ROXL_E110,{3U,6U,6U}}, +{ROXL_E110,{4U,6U,6U}}, +{ROXL_E110,{5U,6U,6U}}, +{ROXL_E110,{6U,6U,6U}}, +{ROXL_E110,{7U,6U,6U}}, +{ROL_E118,{0U,6U,6U}}, +{ROL_E118,{1U,6U,6U}}, +{ROL_E118,{2U,6U,6U}}, +{ROL_E118,{3U,6U,6U}}, +{ROL_E118,{4U,6U,6U}}, +{ROL_E118,{5U,6U,6U}}, +{ROL_E118,{6U,6U,6U}}, +{ROL_E118,{7U,6U,6U}}, +{ASL_E120,{0U,6U,6U}}, +{ASL_E120,{1U,6U,6U}}, +{ASL_E120,{2U,6U,6U}}, +{ASL_E120,{3U,6U,6U}}, +{ASL_E120,{4U,6U,6U}}, +{ASL_E120,{5U,6U,6U}}, +{ASL_E120,{6U,6U,6U}}, +{ASL_E120,{7U,6U,6U}}, +{LSL_E128,{0U,6U,6U}}, +{LSL_E128,{1U,6U,6U}}, +{LSL_E128,{2U,6U,6U}}, +{LSL_E128,{3U,6U,6U}}, +{LSL_E128,{4U,6U,6U}}, +{LSL_E128,{5U,6U,6U}}, +{LSL_E128,{6U,6U,6U}}, +{LSL_E128,{7U,6U,6U}}, +{ROXL_E130,{0U,6U,6U}}, +{ROXL_E130,{1U,6U,6U}}, +{ROXL_E130,{2U,6U,6U}}, +{ROXL_E130,{3U,6U,6U}}, +{ROXL_E130,{4U,6U,6U}}, +{ROXL_E130,{5U,6U,6U}}, +{ROXL_E130,{6U,6U,6U}}, +{ROXL_E130,{7U,6U,6U}}, +{ROL_E138,{0U,6U,6U}}, +{ROL_E138,{1U,6U,6U}}, +{ROL_E138,{2U,6U,6U}}, +{ROL_E138,{3U,6U,6U}}, +{ROL_E138,{4U,6U,6U}}, +{ROL_E138,{5U,6U,6U}}, +{ROL_E138,{6U,6U,6U}}, +{ROL_E138,{7U,6U,6U}}, +{ASL_E140,{0U,6U,6U}}, +{ASL_E140,{1U,6U,6U}}, +{ASL_E140,{2U,6U,6U}}, +{ASL_E140,{3U,6U,6U}}, +{ASL_E140,{4U,6U,6U}}, +{ASL_E140,{5U,6U,6U}}, +{ASL_E140,{6U,6U,6U}}, +{ASL_E140,{7U,6U,6U}}, +{LSL_E148,{0U,6U,6U}}, +{LSL_E148,{1U,6U,6U}}, +{LSL_E148,{2U,6U,6U}}, +{LSL_E148,{3U,6U,6U}}, +{LSL_E148,{4U,6U,6U}}, +{LSL_E148,{5U,6U,6U}}, +{LSL_E148,{6U,6U,6U}}, +{LSL_E148,{7U,6U,6U}}, +{ROXL_E150,{0U,6U,6U}}, +{ROXL_E150,{1U,6U,6U}}, +{ROXL_E150,{2U,6U,6U}}, +{ROXL_E150,{3U,6U,6U}}, +{ROXL_E150,{4U,6U,6U}}, +{ROXL_E150,{5U,6U,6U}}, +{ROXL_E150,{6U,6U,6U}}, +{ROXL_E150,{7U,6U,6U}}, +{ROL_E158,{0U,6U,6U}}, +{ROL_E158,{1U,6U,6U}}, +{ROL_E158,{2U,6U,6U}}, +{ROL_E158,{3U,6U,6U}}, +{ROL_E158,{4U,6U,6U}}, +{ROL_E158,{5U,6U,6U}}, +{ROL_E158,{6U,6U,6U}}, +{ROL_E158,{7U,6U,6U}}, +{ASL_E160,{0U,6U,6U}}, +{ASL_E160,{1U,6U,6U}}, +{ASL_E160,{2U,6U,6U}}, +{ASL_E160,{3U,6U,6U}}, +{ASL_E160,{4U,6U,6U}}, +{ASL_E160,{5U,6U,6U}}, +{ASL_E160,{6U,6U,6U}}, +{ASL_E160,{7U,6U,6U}}, +{LSL_E168,{0U,6U,6U}}, +{LSL_E168,{1U,6U,6U}}, +{LSL_E168,{2U,6U,6U}}, +{LSL_E168,{3U,6U,6U}}, +{LSL_E168,{4U,6U,6U}}, +{LSL_E168,{5U,6U,6U}}, +{LSL_E168,{6U,6U,6U}}, +{LSL_E168,{7U,6U,6U}}, +{ROXL_E170,{0U,6U,6U}}, +{ROXL_E170,{1U,6U,6U}}, +{ROXL_E170,{2U,6U,6U}}, +{ROXL_E170,{3U,6U,6U}}, +{ROXL_E170,{4U,6U,6U}}, +{ROXL_E170,{5U,6U,6U}}, +{ROXL_E170,{6U,6U,6U}}, +{ROXL_E170,{7U,6U,6U}}, +{ROL_E178,{0U,6U,6U}}, +{ROL_E178,{1U,6U,6U}}, +{ROL_E178,{2U,6U,6U}}, +{ROL_E178,{3U,6U,6U}}, +{ROL_E178,{4U,6U,6U}}, +{ROL_E178,{5U,6U,6U}}, +{ROL_E178,{6U,6U,6U}}, +{ROL_E178,{7U,6U,6U}}, +{ASL_E180,{0U,6U,8U}}, +{ASL_E180,{1U,6U,8U}}, +{ASL_E180,{2U,6U,8U}}, +{ASL_E180,{3U,6U,8U}}, +{ASL_E180,{4U,6U,8U}}, +{ASL_E180,{5U,6U,8U}}, +{ASL_E180,{6U,6U,8U}}, +{ASL_E180,{7U,6U,8U}}, +{LSL_E188,{0U,6U,8U}}, +{LSL_E188,{1U,6U,8U}}, +{LSL_E188,{2U,6U,8U}}, +{LSL_E188,{3U,6U,8U}}, +{LSL_E188,{4U,6U,8U}}, +{LSL_E188,{5U,6U,8U}}, +{LSL_E188,{6U,6U,8U}}, +{LSL_E188,{7U,6U,8U}}, +{ROXL_E190,{0U,6U,8U}}, +{ROXL_E190,{1U,6U,8U}}, +{ROXL_E190,{2U,6U,8U}}, +{ROXL_E190,{3U,6U,8U}}, +{ROXL_E190,{4U,6U,8U}}, +{ROXL_E190,{5U,6U,8U}}, +{ROXL_E190,{6U,6U,8U}}, +{ROXL_E190,{7U,6U,8U}}, +{ROL_E198,{0U,6U,8U}}, +{ROL_E198,{1U,6U,8U}}, +{ROL_E198,{2U,6U,8U}}, +{ROL_E198,{3U,6U,8U}}, +{ROL_E198,{4U,6U,8U}}, +{ROL_E198,{5U,6U,8U}}, +{ROL_E198,{6U,6U,8U}}, +{ROL_E198,{7U,6U,8U}}, +{ASL_E1A0,{0U,6U,8U}}, +{ASL_E1A0,{1U,6U,8U}}, +{ASL_E1A0,{2U,6U,8U}}, +{ASL_E1A0,{3U,6U,8U}}, +{ASL_E1A0,{4U,6U,8U}}, +{ASL_E1A0,{5U,6U,8U}}, +{ASL_E1A0,{6U,6U,8U}}, +{ASL_E1A0,{7U,6U,8U}}, +{LSL_E1A8,{0U,6U,8U}}, +{LSL_E1A8,{1U,6U,8U}}, +{LSL_E1A8,{2U,6U,8U}}, +{LSL_E1A8,{3U,6U,8U}}, +{LSL_E1A8,{4U,6U,8U}}, +{LSL_E1A8,{5U,6U,8U}}, +{LSL_E1A8,{6U,6U,8U}}, +{LSL_E1A8,{7U,6U,8U}}, +{ROXL_E1B0,{0U,6U,8U}}, +{ROXL_E1B0,{1U,6U,8U}}, +{ROXL_E1B0,{2U,6U,8U}}, +{ROXL_E1B0,{3U,6U,8U}}, +{ROXL_E1B0,{4U,6U,8U}}, +{ROXL_E1B0,{5U,6U,8U}}, +{ROXL_E1B0,{6U,6U,8U}}, +{ROXL_E1B0,{7U,6U,8U}}, +{ROL_E1B8,{0U,6U,8U}}, +{ROL_E1B8,{1U,6U,8U}}, +{ROL_E1B8,{2U,6U,8U}}, +{ROL_E1B8,{3U,6U,8U}}, +{ROL_E1B8,{4U,6U,8U}}, +{ROL_E1B8,{5U,6U,8U}}, +{ROL_E1B8,{6U,6U,8U}}, +{ROL_E1B8,{7U,6U,8U}}, +{BFFFO_EDC0,{0U,0U,0U}}, +{BFFFO_EDC0,{1U,0U,0U}}, +{BFFFO_EDC0,{2U,0U,0U}}, +{BFFFO_EDC0,{3U,0U,0U}}, +{BFFFO_EDC0,{4U,0U,0U}}, +{BFFFO_EDC0,{5U,0U,0U}}, +{BFFFO_EDC0,{6U,0U,0U}}, +{BFFFO_EDC0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFFFO_EDD0,{0U,0U,0U}}, +{BFFFO_EDD0,{1U,0U,0U}}, +{BFFFO_EDD0,{2U,0U,0U}}, +{BFFFO_EDD0,{3U,0U,0U}}, +{BFFFO_EDD0,{4U,0U,0U}}, +{BFFFO_EDD0,{5U,0U,0U}}, +{BFFFO_EDD0,{6U,0U,0U}}, +{BFFFO_EDD0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFFFO_EDE8,{0U,0U,0U}}, +{BFFFO_EDE8,{1U,0U,0U}}, +{BFFFO_EDE8,{2U,0U,0U}}, +{BFFFO_EDE8,{3U,0U,0U}}, +{BFFFO_EDE8,{4U,0U,0U}}, +{BFFFO_EDE8,{5U,0U,0U}}, +{BFFFO_EDE8,{6U,0U,0U}}, +{BFFFO_EDE8,{7U,0U,0U}}, +{BFFFO_EDF0,{0U,0U,0U}}, +{BFFFO_EDF0,{1U,0U,0U}}, +{BFFFO_EDF0,{2U,0U,0U}}, +{BFFFO_EDF0,{3U,0U,0U}}, +{BFFFO_EDF0,{4U,0U,0U}}, +{BFFFO_EDF0,{5U,0U,0U}}, +{BFFFO_EDF0,{6U,0U,0U}}, +{BFFFO_EDF0,{7U,0U,0U}}, +{BFFFO_EDF8,{0U,0U,0U}}, +{BFFFO_EDF9,{0U,0U,0U}}, +{BFFFO_EDFA,{0U,0U,0U}}, +{BFFFO_EDFB,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASR_E000,{0U,7U,6U}}, +{ASR_E000,{1U,7U,6U}}, +{ASR_E000,{2U,7U,6U}}, +{ASR_E000,{3U,7U,6U}}, +{ASR_E000,{4U,7U,6U}}, +{ASR_E000,{5U,7U,6U}}, +{ASR_E000,{6U,7U,6U}}, +{ASR_E000,{7U,7U,6U}}, +{LSR_E008,{0U,7U,6U}}, +{LSR_E008,{1U,7U,6U}}, +{LSR_E008,{2U,7U,6U}}, +{LSR_E008,{3U,7U,6U}}, +{LSR_E008,{4U,7U,6U}}, +{LSR_E008,{5U,7U,6U}}, +{LSR_E008,{6U,7U,6U}}, +{LSR_E008,{7U,7U,6U}}, +{ROXR_E010,{0U,7U,6U}}, +{ROXR_E010,{1U,7U,6U}}, +{ROXR_E010,{2U,7U,6U}}, +{ROXR_E010,{3U,7U,6U}}, +{ROXR_E010,{4U,7U,6U}}, +{ROXR_E010,{5U,7U,6U}}, +{ROXR_E010,{6U,7U,6U}}, +{ROXR_E010,{7U,7U,6U}}, +{ROR_E018,{0U,7U,6U}}, +{ROR_E018,{1U,7U,6U}}, +{ROR_E018,{2U,7U,6U}}, +{ROR_E018,{3U,7U,6U}}, +{ROR_E018,{4U,7U,6U}}, +{ROR_E018,{5U,7U,6U}}, +{ROR_E018,{6U,7U,6U}}, +{ROR_E018,{7U,7U,6U}}, +{ASR_E020,{0U,7U,6U}}, +{ASR_E020,{1U,7U,6U}}, +{ASR_E020,{2U,7U,6U}}, +{ASR_E020,{3U,7U,6U}}, +{ASR_E020,{4U,7U,6U}}, +{ASR_E020,{5U,7U,6U}}, +{ASR_E020,{6U,7U,6U}}, +{ASR_E020,{7U,7U,6U}}, +{LSR_E028,{0U,7U,6U}}, +{LSR_E028,{1U,7U,6U}}, +{LSR_E028,{2U,7U,6U}}, +{LSR_E028,{3U,7U,6U}}, +{LSR_E028,{4U,7U,6U}}, +{LSR_E028,{5U,7U,6U}}, +{LSR_E028,{6U,7U,6U}}, +{LSR_E028,{7U,7U,6U}}, +{ROXR_E030,{0U,7U,6U}}, +{ROXR_E030,{1U,7U,6U}}, +{ROXR_E030,{2U,7U,6U}}, +{ROXR_E030,{3U,7U,6U}}, +{ROXR_E030,{4U,7U,6U}}, +{ROXR_E030,{5U,7U,6U}}, +{ROXR_E030,{6U,7U,6U}}, +{ROXR_E030,{7U,7U,6U}}, +{ROR_E038,{0U,7U,6U}}, +{ROR_E038,{1U,7U,6U}}, +{ROR_E038,{2U,7U,6U}}, +{ROR_E038,{3U,7U,6U}}, +{ROR_E038,{4U,7U,6U}}, +{ROR_E038,{5U,7U,6U}}, +{ROR_E038,{6U,7U,6U}}, +{ROR_E038,{7U,7U,6U}}, +{ASR_E040,{0U,7U,6U}}, +{ASR_E040,{1U,7U,6U}}, +{ASR_E040,{2U,7U,6U}}, +{ASR_E040,{3U,7U,6U}}, +{ASR_E040,{4U,7U,6U}}, +{ASR_E040,{5U,7U,6U}}, +{ASR_E040,{6U,7U,6U}}, +{ASR_E040,{7U,7U,6U}}, +{LSR_E048,{0U,7U,6U}}, +{LSR_E048,{1U,7U,6U}}, +{LSR_E048,{2U,7U,6U}}, +{LSR_E048,{3U,7U,6U}}, +{LSR_E048,{4U,7U,6U}}, +{LSR_E048,{5U,7U,6U}}, +{LSR_E048,{6U,7U,6U}}, +{LSR_E048,{7U,7U,6U}}, +{ROXR_E050,{0U,7U,6U}}, +{ROXR_E050,{1U,7U,6U}}, +{ROXR_E050,{2U,7U,6U}}, +{ROXR_E050,{3U,7U,6U}}, +{ROXR_E050,{4U,7U,6U}}, +{ROXR_E050,{5U,7U,6U}}, +{ROXR_E050,{6U,7U,6U}}, +{ROXR_E050,{7U,7U,6U}}, +{ROR_E058,{0U,7U,6U}}, +{ROR_E058,{1U,7U,6U}}, +{ROR_E058,{2U,7U,6U}}, +{ROR_E058,{3U,7U,6U}}, +{ROR_E058,{4U,7U,6U}}, +{ROR_E058,{5U,7U,6U}}, +{ROR_E058,{6U,7U,6U}}, +{ROR_E058,{7U,7U,6U}}, +{ASR_E060,{0U,7U,6U}}, +{ASR_E060,{1U,7U,6U}}, +{ASR_E060,{2U,7U,6U}}, +{ASR_E060,{3U,7U,6U}}, +{ASR_E060,{4U,7U,6U}}, +{ASR_E060,{5U,7U,6U}}, +{ASR_E060,{6U,7U,6U}}, +{ASR_E060,{7U,7U,6U}}, +{LSR_E068,{0U,7U,6U}}, +{LSR_E068,{1U,7U,6U}}, +{LSR_E068,{2U,7U,6U}}, +{LSR_E068,{3U,7U,6U}}, +{LSR_E068,{4U,7U,6U}}, +{LSR_E068,{5U,7U,6U}}, +{LSR_E068,{6U,7U,6U}}, +{LSR_E068,{7U,7U,6U}}, +{ROXR_E070,{0U,7U,6U}}, +{ROXR_E070,{1U,7U,6U}}, +{ROXR_E070,{2U,7U,6U}}, +{ROXR_E070,{3U,7U,6U}}, +{ROXR_E070,{4U,7U,6U}}, +{ROXR_E070,{5U,7U,6U}}, +{ROXR_E070,{6U,7U,6U}}, +{ROXR_E070,{7U,7U,6U}}, +{ROR_E078,{0U,7U,6U}}, +{ROR_E078,{1U,7U,6U}}, +{ROR_E078,{2U,7U,6U}}, +{ROR_E078,{3U,7U,6U}}, +{ROR_E078,{4U,7U,6U}}, +{ROR_E078,{5U,7U,6U}}, +{ROR_E078,{6U,7U,6U}}, +{ROR_E078,{7U,7U,6U}}, +{ASR_E080,{0U,7U,8U}}, +{ASR_E080,{1U,7U,8U}}, +{ASR_E080,{2U,7U,8U}}, +{ASR_E080,{3U,7U,8U}}, +{ASR_E080,{4U,7U,8U}}, +{ASR_E080,{5U,7U,8U}}, +{ASR_E080,{6U,7U,8U}}, +{ASR_E080,{7U,7U,8U}}, +{LSR_E088,{0U,7U,8U}}, +{LSR_E088,{1U,7U,8U}}, +{LSR_E088,{2U,7U,8U}}, +{LSR_E088,{3U,7U,8U}}, +{LSR_E088,{4U,7U,8U}}, +{LSR_E088,{5U,7U,8U}}, +{LSR_E088,{6U,7U,8U}}, +{LSR_E088,{7U,7U,8U}}, +{ROXR_E090,{0U,7U,8U}}, +{ROXR_E090,{1U,7U,8U}}, +{ROXR_E090,{2U,7U,8U}}, +{ROXR_E090,{3U,7U,8U}}, +{ROXR_E090,{4U,7U,8U}}, +{ROXR_E090,{5U,7U,8U}}, +{ROXR_E090,{6U,7U,8U}}, +{ROXR_E090,{7U,7U,8U}}, +{ROR_E098,{0U,7U,8U}}, +{ROR_E098,{1U,7U,8U}}, +{ROR_E098,{2U,7U,8U}}, +{ROR_E098,{3U,7U,8U}}, +{ROR_E098,{4U,7U,8U}}, +{ROR_E098,{5U,7U,8U}}, +{ROR_E098,{6U,7U,8U}}, +{ROR_E098,{7U,7U,8U}}, +{ASR_E0A0,{0U,7U,8U}}, +{ASR_E0A0,{1U,7U,8U}}, +{ASR_E0A0,{2U,7U,8U}}, +{ASR_E0A0,{3U,7U,8U}}, +{ASR_E0A0,{4U,7U,8U}}, +{ASR_E0A0,{5U,7U,8U}}, +{ASR_E0A0,{6U,7U,8U}}, +{ASR_E0A0,{7U,7U,8U}}, +{LSR_E0A8,{0U,7U,8U}}, +{LSR_E0A8,{1U,7U,8U}}, +{LSR_E0A8,{2U,7U,8U}}, +{LSR_E0A8,{3U,7U,8U}}, +{LSR_E0A8,{4U,7U,8U}}, +{LSR_E0A8,{5U,7U,8U}}, +{LSR_E0A8,{6U,7U,8U}}, +{LSR_E0A8,{7U,7U,8U}}, +{ROXR_E0B0,{0U,7U,8U}}, +{ROXR_E0B0,{1U,7U,8U}}, +{ROXR_E0B0,{2U,7U,8U}}, +{ROXR_E0B0,{3U,7U,8U}}, +{ROXR_E0B0,{4U,7U,8U}}, +{ROXR_E0B0,{5U,7U,8U}}, +{ROXR_E0B0,{6U,7U,8U}}, +{ROXR_E0B0,{7U,7U,8U}}, +{ROR_E0B8,{0U,7U,8U}}, +{ROR_E0B8,{1U,7U,8U}}, +{ROR_E0B8,{2U,7U,8U}}, +{ROR_E0B8,{3U,7U,8U}}, +{ROR_E0B8,{4U,7U,8U}}, +{ROR_E0B8,{5U,7U,8U}}, +{ROR_E0B8,{6U,7U,8U}}, +{ROR_E0B8,{7U,7U,8U}}, +{BFSET_EEC0,{0U,0U,0U}}, +{BFSET_EEC0,{1U,0U,0U}}, +{BFSET_EEC0,{2U,0U,0U}}, +{BFSET_EEC0,{3U,0U,0U}}, +{BFSET_EEC0,{4U,0U,0U}}, +{BFSET_EEC0,{5U,0U,0U}}, +{BFSET_EEC0,{6U,0U,0U}}, +{BFSET_EEC0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFSET_EED0,{0U,0U,0U}}, +{BFSET_EED0,{1U,0U,0U}}, +{BFSET_EED0,{2U,0U,0U}}, +{BFSET_EED0,{3U,0U,0U}}, +{BFSET_EED0,{4U,0U,0U}}, +{BFSET_EED0,{5U,0U,0U}}, +{BFSET_EED0,{6U,0U,0U}}, +{BFSET_EED0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFSET_EEE8,{0U,0U,0U}}, +{BFSET_EEE8,{1U,0U,0U}}, +{BFSET_EEE8,{2U,0U,0U}}, +{BFSET_EEE8,{3U,0U,0U}}, +{BFSET_EEE8,{4U,0U,0U}}, +{BFSET_EEE8,{5U,0U,0U}}, +{BFSET_EEE8,{6U,0U,0U}}, +{BFSET_EEE8,{7U,0U,0U}}, +{BFSET_EEF0,{0U,0U,0U}}, +{BFSET_EEF0,{1U,0U,0U}}, +{BFSET_EEF0,{2U,0U,0U}}, +{BFSET_EEF0,{3U,0U,0U}}, +{BFSET_EEF0,{4U,0U,0U}}, +{BFSET_EEF0,{5U,0U,0U}}, +{BFSET_EEF0,{6U,0U,0U}}, +{BFSET_EEF0,{7U,0U,0U}}, +{BFSET_EEF8,{0U,0U,0U}}, +{BFSET_EEF9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{ASL_E100,{0U,7U,6U}}, +{ASL_E100,{1U,7U,6U}}, +{ASL_E100,{2U,7U,6U}}, +{ASL_E100,{3U,7U,6U}}, +{ASL_E100,{4U,7U,6U}}, +{ASL_E100,{5U,7U,6U}}, +{ASL_E100,{6U,7U,6U}}, +{ASL_E100,{7U,7U,6U}}, +{LSL_E108,{0U,7U,6U}}, +{LSL_E108,{1U,7U,6U}}, +{LSL_E108,{2U,7U,6U}}, +{LSL_E108,{3U,7U,6U}}, +{LSL_E108,{4U,7U,6U}}, +{LSL_E108,{5U,7U,6U}}, +{LSL_E108,{6U,7U,6U}}, +{LSL_E108,{7U,7U,6U}}, +{ROXL_E110,{0U,7U,6U}}, +{ROXL_E110,{1U,7U,6U}}, +{ROXL_E110,{2U,7U,6U}}, +{ROXL_E110,{3U,7U,6U}}, +{ROXL_E110,{4U,7U,6U}}, +{ROXL_E110,{5U,7U,6U}}, +{ROXL_E110,{6U,7U,6U}}, +{ROXL_E110,{7U,7U,6U}}, +{ROL_E118,{0U,7U,6U}}, +{ROL_E118,{1U,7U,6U}}, +{ROL_E118,{2U,7U,6U}}, +{ROL_E118,{3U,7U,6U}}, +{ROL_E118,{4U,7U,6U}}, +{ROL_E118,{5U,7U,6U}}, +{ROL_E118,{6U,7U,6U}}, +{ROL_E118,{7U,7U,6U}}, +{ASL_E120,{0U,7U,6U}}, +{ASL_E120,{1U,7U,6U}}, +{ASL_E120,{2U,7U,6U}}, +{ASL_E120,{3U,7U,6U}}, +{ASL_E120,{4U,7U,6U}}, +{ASL_E120,{5U,7U,6U}}, +{ASL_E120,{6U,7U,6U}}, +{ASL_E120,{7U,7U,6U}}, +{LSL_E128,{0U,7U,6U}}, +{LSL_E128,{1U,7U,6U}}, +{LSL_E128,{2U,7U,6U}}, +{LSL_E128,{3U,7U,6U}}, +{LSL_E128,{4U,7U,6U}}, +{LSL_E128,{5U,7U,6U}}, +{LSL_E128,{6U,7U,6U}}, +{LSL_E128,{7U,7U,6U}}, +{ROXL_E130,{0U,7U,6U}}, +{ROXL_E130,{1U,7U,6U}}, +{ROXL_E130,{2U,7U,6U}}, +{ROXL_E130,{3U,7U,6U}}, +{ROXL_E130,{4U,7U,6U}}, +{ROXL_E130,{5U,7U,6U}}, +{ROXL_E130,{6U,7U,6U}}, +{ROXL_E130,{7U,7U,6U}}, +{ROL_E138,{0U,7U,6U}}, +{ROL_E138,{1U,7U,6U}}, +{ROL_E138,{2U,7U,6U}}, +{ROL_E138,{3U,7U,6U}}, +{ROL_E138,{4U,7U,6U}}, +{ROL_E138,{5U,7U,6U}}, +{ROL_E138,{6U,7U,6U}}, +{ROL_E138,{7U,7U,6U}}, +{ASL_E140,{0U,7U,6U}}, +{ASL_E140,{1U,7U,6U}}, +{ASL_E140,{2U,7U,6U}}, +{ASL_E140,{3U,7U,6U}}, +{ASL_E140,{4U,7U,6U}}, +{ASL_E140,{5U,7U,6U}}, +{ASL_E140,{6U,7U,6U}}, +{ASL_E140,{7U,7U,6U}}, +{LSL_E148,{0U,7U,6U}}, +{LSL_E148,{1U,7U,6U}}, +{LSL_E148,{2U,7U,6U}}, +{LSL_E148,{3U,7U,6U}}, +{LSL_E148,{4U,7U,6U}}, +{LSL_E148,{5U,7U,6U}}, +{LSL_E148,{6U,7U,6U}}, +{LSL_E148,{7U,7U,6U}}, +{ROXL_E150,{0U,7U,6U}}, +{ROXL_E150,{1U,7U,6U}}, +{ROXL_E150,{2U,7U,6U}}, +{ROXL_E150,{3U,7U,6U}}, +{ROXL_E150,{4U,7U,6U}}, +{ROXL_E150,{5U,7U,6U}}, +{ROXL_E150,{6U,7U,6U}}, +{ROXL_E150,{7U,7U,6U}}, +{ROL_E158,{0U,7U,6U}}, +{ROL_E158,{1U,7U,6U}}, +{ROL_E158,{2U,7U,6U}}, +{ROL_E158,{3U,7U,6U}}, +{ROL_E158,{4U,7U,6U}}, +{ROL_E158,{5U,7U,6U}}, +{ROL_E158,{6U,7U,6U}}, +{ROL_E158,{7U,7U,6U}}, +{ASL_E160,{0U,7U,6U}}, +{ASL_E160,{1U,7U,6U}}, +{ASL_E160,{2U,7U,6U}}, +{ASL_E160,{3U,7U,6U}}, +{ASL_E160,{4U,7U,6U}}, +{ASL_E160,{5U,7U,6U}}, +{ASL_E160,{6U,7U,6U}}, +{ASL_E160,{7U,7U,6U}}, +{LSL_E168,{0U,7U,6U}}, +{LSL_E168,{1U,7U,6U}}, +{LSL_E168,{2U,7U,6U}}, +{LSL_E168,{3U,7U,6U}}, +{LSL_E168,{4U,7U,6U}}, +{LSL_E168,{5U,7U,6U}}, +{LSL_E168,{6U,7U,6U}}, +{LSL_E168,{7U,7U,6U}}, +{ROXL_E170,{0U,7U,6U}}, +{ROXL_E170,{1U,7U,6U}}, +{ROXL_E170,{2U,7U,6U}}, +{ROXL_E170,{3U,7U,6U}}, +{ROXL_E170,{4U,7U,6U}}, +{ROXL_E170,{5U,7U,6U}}, +{ROXL_E170,{6U,7U,6U}}, +{ROXL_E170,{7U,7U,6U}}, +{ROL_E178,{0U,7U,6U}}, +{ROL_E178,{1U,7U,6U}}, +{ROL_E178,{2U,7U,6U}}, +{ROL_E178,{3U,7U,6U}}, +{ROL_E178,{4U,7U,6U}}, +{ROL_E178,{5U,7U,6U}}, +{ROL_E178,{6U,7U,6U}}, +{ROL_E178,{7U,7U,6U}}, +{ASL_E180,{0U,7U,8U}}, +{ASL_E180,{1U,7U,8U}}, +{ASL_E180,{2U,7U,8U}}, +{ASL_E180,{3U,7U,8U}}, +{ASL_E180,{4U,7U,8U}}, +{ASL_E180,{5U,7U,8U}}, +{ASL_E180,{6U,7U,8U}}, +{ASL_E180,{7U,7U,8U}}, +{LSL_E188,{0U,7U,8U}}, +{LSL_E188,{1U,7U,8U}}, +{LSL_E188,{2U,7U,8U}}, +{LSL_E188,{3U,7U,8U}}, +{LSL_E188,{4U,7U,8U}}, +{LSL_E188,{5U,7U,8U}}, +{LSL_E188,{6U,7U,8U}}, +{LSL_E188,{7U,7U,8U}}, +{ROXL_E190,{0U,7U,8U}}, +{ROXL_E190,{1U,7U,8U}}, +{ROXL_E190,{2U,7U,8U}}, +{ROXL_E190,{3U,7U,8U}}, +{ROXL_E190,{4U,7U,8U}}, +{ROXL_E190,{5U,7U,8U}}, +{ROXL_E190,{6U,7U,8U}}, +{ROXL_E190,{7U,7U,8U}}, +{ROL_E198,{0U,7U,8U}}, +{ROL_E198,{1U,7U,8U}}, +{ROL_E198,{2U,7U,8U}}, +{ROL_E198,{3U,7U,8U}}, +{ROL_E198,{4U,7U,8U}}, +{ROL_E198,{5U,7U,8U}}, +{ROL_E198,{6U,7U,8U}}, +{ROL_E198,{7U,7U,8U}}, +{ASL_E1A0,{0U,7U,8U}}, +{ASL_E1A0,{1U,7U,8U}}, +{ASL_E1A0,{2U,7U,8U}}, +{ASL_E1A0,{3U,7U,8U}}, +{ASL_E1A0,{4U,7U,8U}}, +{ASL_E1A0,{5U,7U,8U}}, +{ASL_E1A0,{6U,7U,8U}}, +{ASL_E1A0,{7U,7U,8U}}, +{LSL_E1A8,{0U,7U,8U}}, +{LSL_E1A8,{1U,7U,8U}}, +{LSL_E1A8,{2U,7U,8U}}, +{LSL_E1A8,{3U,7U,8U}}, +{LSL_E1A8,{4U,7U,8U}}, +{LSL_E1A8,{5U,7U,8U}}, +{LSL_E1A8,{6U,7U,8U}}, +{LSL_E1A8,{7U,7U,8U}}, +{ROXL_E1B0,{0U,7U,8U}}, +{ROXL_E1B0,{1U,7U,8U}}, +{ROXL_E1B0,{2U,7U,8U}}, +{ROXL_E1B0,{3U,7U,8U}}, +{ROXL_E1B0,{4U,7U,8U}}, +{ROXL_E1B0,{5U,7U,8U}}, +{ROXL_E1B0,{6U,7U,8U}}, +{ROXL_E1B0,{7U,7U,8U}}, +{ROL_E1B8,{0U,7U,8U}}, +{ROL_E1B8,{1U,7U,8U}}, +{ROL_E1B8,{2U,7U,8U}}, +{ROL_E1B8,{3U,7U,8U}}, +{ROL_E1B8,{4U,7U,8U}}, +{ROL_E1B8,{5U,7U,8U}}, +{ROL_E1B8,{6U,7U,8U}}, +{ROL_E1B8,{7U,7U,8U}}, +{BFINS_EFC0,{0U,0U,0U}}, +{BFINS_EFC0,{1U,0U,0U}}, +{BFINS_EFC0,{2U,0U,0U}}, +{BFINS_EFC0,{3U,0U,0U}}, +{BFINS_EFC0,{4U,0U,0U}}, +{BFINS_EFC0,{5U,0U,0U}}, +{BFINS_EFC0,{6U,0U,0U}}, +{BFINS_EFC0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFINS_EFD0,{0U,0U,0U}}, +{BFINS_EFD0,{1U,0U,0U}}, +{BFINS_EFD0,{2U,0U,0U}}, +{BFINS_EFD0,{3U,0U,0U}}, +{BFINS_EFD0,{4U,0U,0U}}, +{BFINS_EFD0,{5U,0U,0U}}, +{BFINS_EFD0,{6U,0U,0U}}, +{BFINS_EFD0,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{BFINS_EFE8,{0U,0U,0U}}, +{BFINS_EFE8,{1U,0U,0U}}, +{BFINS_EFE8,{2U,0U,0U}}, +{BFINS_EFE8,{3U,0U,0U}}, +{BFINS_EFE8,{4U,0U,0U}}, +{BFINS_EFE8,{5U,0U,0U}}, +{BFINS_EFE8,{6U,0U,0U}}, +{BFINS_EFE8,{7U,0U,0U}}, +{BFINS_EFF0,{0U,0U,0U}}, +{BFINS_EFF0,{1U,0U,0U}}, +{BFINS_EFF0,{2U,0U,0U}}, +{BFINS_EFF0,{3U,0U,0U}}, +{BFINS_EFF0,{4U,0U,0U}}, +{BFINS_EFF0,{5U,0U,0U}}, +{BFINS_EFF0,{6U,0U,0U}}, +{BFINS_EFF0,{7U,0U,0U}}, +{BFINS_EFF8,{0U,0U,0U}}, +{BFINS_EFF9,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PFLUSH030_F010,{0U,0U,0U}}, +{PFLUSH030_F010,{1U,0U,0U}}, +{PFLUSH030_F010,{2U,0U,0U}}, +{PFLUSH030_F010,{3U,0U,0U}}, +{PFLUSH030_F010,{4U,0U,0U}}, +{PFLUSH030_F010,{5U,0U,0U}}, +{PFLUSH030_F010,{6U,0U,0U}}, +{PFLUSH030_F010,{7U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{PFLUSH030_F028,{0U,0U,0U}}, +{PFLUSH030_F028,{1U,0U,0U}}, +{PFLUSH030_F028,{2U,0U,0U}}, +{PFLUSH030_F028,{3U,0U,0U}}, +{PFLUSH030_F028,{4U,0U,0U}}, +{PFLUSH030_F028,{5U,0U,0U}}, +{PFLUSH030_F028,{6U,0U,0U}}, +{PFLUSH030_F028,{7U,0U,0U}}, +{PFLUSH030_F030,{0U,0U,0U}}, +{PFLUSH030_F030,{1U,0U,0U}}, +{PFLUSH030_F030,{2U,0U,0U}}, +{PFLUSH030_F030,{3U,0U,0U}}, +{PFLUSH030_F030,{4U,0U,0U}}, +{PFLUSH030_F030,{5U,0U,0U}}, +{PFLUSH030_F030,{6U,0U,0U}}, +{PFLUSH030_F030,{7U,0U,0U}}, +{PFLUSH030_F038,{0U,0U,0U}}, +{PFLUSH030_F039,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, +{cpuIllegalInstruction,{0U,0U,0U}}, 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ADD_D000(ULO*opc_data); +static void ADD_D010(ULO*opc_data); +static void ADD_D018(ULO*opc_data); +static void ADD_D020(ULO*opc_data); +static void ADD_D028(ULO*opc_data); +static void ADD_D030(ULO*opc_data); +static void ADD_D038(ULO*opc_data); +static void ADD_D039(ULO*opc_data); +static void ADD_D03A(ULO*opc_data); +static void ADD_D03B(ULO*opc_data); +static void ADD_D03C(ULO*opc_data); +static void ADD_D040(ULO*opc_data); +static void ADD_D048(ULO*opc_data); +static void ADD_D050(ULO*opc_data); +static void ADD_D058(ULO*opc_data); +static void ADD_D060(ULO*opc_data); +static void ADD_D068(ULO*opc_data); +static void ADD_D070(ULO*opc_data); +static void ADD_D078(ULO*opc_data); +static void ADD_D079(ULO*opc_data); +static void ADD_D07A(ULO*opc_data); +static void ADD_D07B(ULO*opc_data); +static void ADD_D07C(ULO*opc_data); +static void ADD_D080(ULO*opc_data); +static void ADD_D088(ULO*opc_data); +static void ADD_D090(ULO*opc_data); +static void ADD_D098(ULO*opc_data); +static void ADD_D0A0(ULO*opc_data); +static void ADD_D0A8(ULO*opc_data); +static void ADD_D0B0(ULO*opc_data); +static void ADD_D0B8(ULO*opc_data); +static void ADD_D0B9(ULO*opc_data); +static void ADD_D0BA(ULO*opc_data); +static void ADD_D0BB(ULO*opc_data); +static void ADD_D0BC(ULO*opc_data); +static void ADD_D110(ULO*opc_data); +static void ADD_D118(ULO*opc_data); +static void ADD_D120(ULO*opc_data); +static void ADD_D128(ULO*opc_data); +static void ADD_D130(ULO*opc_data); +static void ADD_D138(ULO*opc_data); +static void ADD_D139(ULO*opc_data); +static void ADD_D150(ULO*opc_data); +static void ADD_D158(ULO*opc_data); +static void ADD_D160(ULO*opc_data); +static void ADD_D168(ULO*opc_data); +static void ADD_D170(ULO*opc_data); +static void ADD_D178(ULO*opc_data); +static void ADD_D179(ULO*opc_data); +static void ADD_D190(ULO*opc_data); +static void ADD_D198(ULO*opc_data); +static void ADD_D1A0(ULO*opc_data); +static void ADD_D1A8(ULO*opc_data); +static void ADD_D1B0(ULO*opc_data); +static void ADD_D1B8(ULO*opc_data); +static void ADD_D1B9(ULO*opc_data); +static void ADDA_D0C0(ULO*opc_data); +static void ADDA_D0C8(ULO*opc_data); +static void ADDA_D0D0(ULO*opc_data); +static void ADDA_D0D8(ULO*opc_data); +static void ADDA_D0E0(ULO*opc_data); +static void ADDA_D0E8(ULO*opc_data); +static void ADDA_D0F0(ULO*opc_data); +static void ADDA_D0F8(ULO*opc_data); +static void ADDA_D0F9(ULO*opc_data); +static void ADDA_D0FA(ULO*opc_data); +static void ADDA_D0FB(ULO*opc_data); +static void ADDA_D0FC(ULO*opc_data); +static void ADDA_D1C0(ULO*opc_data); +static void ADDA_D1C8(ULO*opc_data); +static void ADDA_D1D0(ULO*opc_data); +static void ADDA_D1D8(ULO*opc_data); +static void ADDA_D1E0(ULO*opc_data); +static void ADDA_D1E8(ULO*opc_data); +static void ADDA_D1F0(ULO*opc_data); +static void ADDA_D1F8(ULO*opc_data); +static void ADDA_D1F9(ULO*opc_data); +static void ADDA_D1FA(ULO*opc_data); +static void ADDA_D1FB(ULO*opc_data); +static void ADDA_D1FC(ULO*opc_data); +static void ADDI_0600(ULO*opc_data); +static void ADDI_0610(ULO*opc_data); +static void ADDI_0618(ULO*opc_data); +static void ADDI_0620(ULO*opc_data); +static void ADDI_0628(ULO*opc_data); +static void ADDI_0630(ULO*opc_data); +static void ADDI_0638(ULO*opc_data); +static void ADDI_0639(ULO*opc_data); +static void ADDI_0640(ULO*opc_data); +static void ADDI_0650(ULO*opc_data); +static void ADDI_0658(ULO*opc_data); +static void ADDI_0660(ULO*opc_data); +static void ADDI_0668(ULO*opc_data); +static void ADDI_0670(ULO*opc_data); +static void ADDI_0678(ULO*opc_data); +static void ADDI_0679(ULO*opc_data); +static void ADDI_0680(ULO*opc_data); +static void ADDI_0690(ULO*opc_data); +static void ADDI_0698(ULO*opc_data); +static void ADDI_06A0(ULO*opc_data); +static void ADDI_06A8(ULO*opc_data); +static void ADDI_06B0(ULO*opc_data); +static void ADDI_06B8(ULO*opc_data); +static void ADDI_06B9(ULO*opc_data); +static void ADDQ_5000(ULO*opc_data); +static void ADDQ_5010(ULO*opc_data); +static void ADDQ_5018(ULO*opc_data); +static void ADDQ_5020(ULO*opc_data); +static void ADDQ_5028(ULO*opc_data); +static void ADDQ_5030(ULO*opc_data); +static void ADDQ_5038(ULO*opc_data); +static void ADDQ_5039(ULO*opc_data); +static void ADDQ_5040(ULO*opc_data); +static void ADDQ_5050(ULO*opc_data); +static void ADDQ_5058(ULO*opc_data); +static void ADDQ_5060(ULO*opc_data); +static void ADDQ_5068(ULO*opc_data); +static void ADDQ_5070(ULO*opc_data); +static void ADDQ_5078(ULO*opc_data); +static void ADDQ_5079(ULO*opc_data); +static void ADDQ_5080(ULO*opc_data); +static void ADDQ_5090(ULO*opc_data); +static void ADDQ_5098(ULO*opc_data); +static void ADDQ_50A0(ULO*opc_data); +static void ADDQ_50A8(ULO*opc_data); +static void ADDQ_50B0(ULO*opc_data); +static void ADDQ_50B8(ULO*opc_data); +static void ADDQ_50B9(ULO*opc_data); +static void ADDQ_5048(ULO*opc_data); +static void ADDQ_5088(ULO*opc_data); +static void AND_C000(ULO*opc_data); +static void AND_C010(ULO*opc_data); +static void AND_C018(ULO*opc_data); +static void AND_C020(ULO*opc_data); +static void AND_C028(ULO*opc_data); +static void AND_C030(ULO*opc_data); +static void AND_C038(ULO*opc_data); +static void AND_C039(ULO*opc_data); +static void AND_C03A(ULO*opc_data); +static void AND_C03B(ULO*opc_data); +static void AND_C03C(ULO*opc_data); +static void AND_C040(ULO*opc_data); +static void AND_C050(ULO*opc_data); +static void AND_C058(ULO*opc_data); +static void AND_C060(ULO*opc_data); +static void AND_C068(ULO*opc_data); +static void AND_C070(ULO*opc_data); +static void AND_C078(ULO*opc_data); +static void AND_C079(ULO*opc_data); +static void AND_C07A(ULO*opc_data); +static void AND_C07B(ULO*opc_data); +static void AND_C07C(ULO*opc_data); +static void AND_C080(ULO*opc_data); +static void AND_C090(ULO*opc_data); +static void AND_C098(ULO*opc_data); +static void AND_C0A0(ULO*opc_data); +static void AND_C0A8(ULO*opc_data); +static void AND_C0B0(ULO*opc_data); +static void AND_C0B8(ULO*opc_data); +static void AND_C0B9(ULO*opc_data); +static void AND_C0BA(ULO*opc_data); +static void AND_C0BB(ULO*opc_data); +static void AND_C0BC(ULO*opc_data); +static void AND_C110(ULO*opc_data); +static void AND_C118(ULO*opc_data); +static void AND_C120(ULO*opc_data); +static void AND_C128(ULO*opc_data); +static void AND_C130(ULO*opc_data); +static void AND_C138(ULO*opc_data); +static void AND_C139(ULO*opc_data); +static void AND_C150(ULO*opc_data); +static void AND_C158(ULO*opc_data); +static void AND_C160(ULO*opc_data); +static void AND_C168(ULO*opc_data); +static void AND_C170(ULO*opc_data); +static void AND_C178(ULO*opc_data); +static void AND_C179(ULO*opc_data); +static void AND_C190(ULO*opc_data); +static void AND_C198(ULO*opc_data); +static void AND_C1A0(ULO*opc_data); +static void AND_C1A8(ULO*opc_data); +static void AND_C1B0(ULO*opc_data); +static void AND_C1B8(ULO*opc_data); +static void AND_C1B9(ULO*opc_data); +static void ANDI_0200(ULO*opc_data); +static void ANDI_0210(ULO*opc_data); +static void ANDI_0218(ULO*opc_data); +static void ANDI_0220(ULO*opc_data); +static void ANDI_0228(ULO*opc_data); +static void ANDI_0230(ULO*opc_data); +static void ANDI_0238(ULO*opc_data); +static void ANDI_0239(ULO*opc_data); +static void ANDI_0240(ULO*opc_data); +static void ANDI_0250(ULO*opc_data); +static void ANDI_0258(ULO*opc_data); +static void ANDI_0260(ULO*opc_data); +static void ANDI_0268(ULO*opc_data); +static void ANDI_0270(ULO*opc_data); +static void ANDI_0278(ULO*opc_data); +static void ANDI_0279(ULO*opc_data); +static void ANDI_0280(ULO*opc_data); +static void ANDI_0290(ULO*opc_data); +static void ANDI_0298(ULO*opc_data); +static void ANDI_02A0(ULO*opc_data); +static void ANDI_02A8(ULO*opc_data); +static void ANDI_02B0(ULO*opc_data); +static void ANDI_02B8(ULO*opc_data); +static void ANDI_02B9(ULO*opc_data); +static void ANDI_023C(ULO*opc_data); +static void ANDI_027C(ULO*opc_data); +static void EOR_B100(ULO*opc_data); +static void EOR_B110(ULO*opc_data); +static void EOR_B118(ULO*opc_data); +static void EOR_B120(ULO*opc_data); +static void EOR_B128(ULO*opc_data); +static void EOR_B130(ULO*opc_data); +static void EOR_B138(ULO*opc_data); +static void EOR_B139(ULO*opc_data); +static void EOR_B140(ULO*opc_data); +static void EOR_B150(ULO*opc_data); +static void EOR_B158(ULO*opc_data); +static void EOR_B160(ULO*opc_data); +static void EOR_B168(ULO*opc_data); +static void EOR_B170(ULO*opc_data); +static void EOR_B178(ULO*opc_data); +static void EOR_B179(ULO*opc_data); +static void EOR_B180(ULO*opc_data); +static void EOR_B190(ULO*opc_data); +static void EOR_B198(ULO*opc_data); +static void EOR_B1A0(ULO*opc_data); +static void EOR_B1A8(ULO*opc_data); +static void EOR_B1B0(ULO*opc_data); +static void EOR_B1B8(ULO*opc_data); +static void EOR_B1B9(ULO*opc_data); +static void EORI_0A00(ULO*opc_data); +static void EORI_0A10(ULO*opc_data); +static void EORI_0A18(ULO*opc_data); +static void EORI_0A20(ULO*opc_data); +static void EORI_0A28(ULO*opc_data); +static void EORI_0A30(ULO*opc_data); +static void EORI_0A38(ULO*opc_data); +static void EORI_0A39(ULO*opc_data); +static void EORI_0A40(ULO*opc_data); +static void EORI_0A50(ULO*opc_data); +static void EORI_0A58(ULO*opc_data); +static void EORI_0A60(ULO*opc_data); +static void EORI_0A68(ULO*opc_data); +static void EORI_0A70(ULO*opc_data); +static void EORI_0A78(ULO*opc_data); +static void EORI_0A79(ULO*opc_data); +static void EORI_0A80(ULO*opc_data); +static void EORI_0A90(ULO*opc_data); +static void EORI_0A98(ULO*opc_data); +static void EORI_0AA0(ULO*opc_data); +static void EORI_0AA8(ULO*opc_data); +static void EORI_0AB0(ULO*opc_data); +static void EORI_0AB8(ULO*opc_data); +static void EORI_0AB9(ULO*opc_data); +static void EORI_0A3C(ULO*opc_data); +static void EORI_0A7C(ULO*opc_data); +static void OR_8000(ULO*opc_data); +static void OR_8010(ULO*opc_data); +static void OR_8018(ULO*opc_data); +static void OR_8020(ULO*opc_data); +static void OR_8028(ULO*opc_data); +static void OR_8030(ULO*opc_data); +static void OR_8038(ULO*opc_data); +static void OR_8039(ULO*opc_data); +static void OR_803A(ULO*opc_data); +static void OR_803B(ULO*opc_data); +static void OR_803C(ULO*opc_data); +static void OR_8040(ULO*opc_data); +static void OR_8050(ULO*opc_data); +static void OR_8058(ULO*opc_data); +static void OR_8060(ULO*opc_data); +static void OR_8068(ULO*opc_data); +static void OR_8070(ULO*opc_data); +static void OR_8078(ULO*opc_data); +static void OR_8079(ULO*opc_data); +static void OR_807A(ULO*opc_data); +static void OR_807B(ULO*opc_data); +static void OR_807C(ULO*opc_data); +static void OR_8080(ULO*opc_data); +static void OR_8090(ULO*opc_data); +static void OR_8098(ULO*opc_data); +static void OR_80A0(ULO*opc_data); +static void OR_80A8(ULO*opc_data); +static void OR_80B0(ULO*opc_data); +static void OR_80B8(ULO*opc_data); +static void OR_80B9(ULO*opc_data); +static void OR_80BA(ULO*opc_data); +static void OR_80BB(ULO*opc_data); +static void OR_80BC(ULO*opc_data); +static void OR_8110(ULO*opc_data); +static void OR_8118(ULO*opc_data); +static void OR_8120(ULO*opc_data); +static void OR_8128(ULO*opc_data); +static void OR_8130(ULO*opc_data); +static void OR_8138(ULO*opc_data); +static void OR_8139(ULO*opc_data); +static void OR_8150(ULO*opc_data); +static void OR_8158(ULO*opc_data); +static void OR_8160(ULO*opc_data); +static void OR_8168(ULO*opc_data); +static void OR_8170(ULO*opc_data); +static void OR_8178(ULO*opc_data); +static void OR_8179(ULO*opc_data); +static void OR_8190(ULO*opc_data); +static void OR_8198(ULO*opc_data); +static void OR_81A0(ULO*opc_data); +static void OR_81A8(ULO*opc_data); +static void OR_81B0(ULO*opc_data); +static void OR_81B8(ULO*opc_data); +static void OR_81B9(ULO*opc_data); +static void ORI_0000(ULO*opc_data); +static void ORI_0010(ULO*opc_data); +static void ORI_0018(ULO*opc_data); +static void ORI_0020(ULO*opc_data); +static void ORI_0028(ULO*opc_data); +static void ORI_0030(ULO*opc_data); +static void ORI_0038(ULO*opc_data); +static void ORI_0039(ULO*opc_data); +static void ORI_0040(ULO*opc_data); +static void ORI_0050(ULO*opc_data); +static void ORI_0058(ULO*opc_data); +static void ORI_0060(ULO*opc_data); +static void ORI_0068(ULO*opc_data); +static void ORI_0070(ULO*opc_data); +static void ORI_0078(ULO*opc_data); +static void ORI_0079(ULO*opc_data); +static void ORI_0080(ULO*opc_data); +static void ORI_0090(ULO*opc_data); +static void ORI_0098(ULO*opc_data); +static void ORI_00A0(ULO*opc_data); +static void ORI_00A8(ULO*opc_data); +static void ORI_00B0(ULO*opc_data); +static void ORI_00B8(ULO*opc_data); +static void ORI_00B9(ULO*opc_data); +static void ORI_003C(ULO*opc_data); +static void ORI_007C(ULO*opc_data); +static void SUB_9000(ULO*opc_data); +static void SUB_9010(ULO*opc_data); +static void SUB_9018(ULO*opc_data); +static void SUB_9020(ULO*opc_data); +static void SUB_9028(ULO*opc_data); +static void SUB_9030(ULO*opc_data); +static void SUB_9038(ULO*opc_data); +static void SUB_9039(ULO*opc_data); +static void SUB_903A(ULO*opc_data); +static void SUB_903B(ULO*opc_data); +static void SUB_903C(ULO*opc_data); +static void SUB_9040(ULO*opc_data); +static void SUB_9048(ULO*opc_data); +static void SUB_9050(ULO*opc_data); +static void SUB_9058(ULO*opc_data); +static void SUB_9060(ULO*opc_data); +static void SUB_9068(ULO*opc_data); +static void SUB_9070(ULO*opc_data); +static void SUB_9078(ULO*opc_data); +static void SUB_9079(ULO*opc_data); +static void SUB_907A(ULO*opc_data); +static void SUB_907B(ULO*opc_data); +static void SUB_907C(ULO*opc_data); +static void SUB_9080(ULO*opc_data); +static void SUB_9088(ULO*opc_data); +static void SUB_9090(ULO*opc_data); +static void SUB_9098(ULO*opc_data); +static void SUB_90A0(ULO*opc_data); +static void SUB_90A8(ULO*opc_data); +static void SUB_90B0(ULO*opc_data); +static void SUB_90B8(ULO*opc_data); +static void SUB_90B9(ULO*opc_data); +static void SUB_90BA(ULO*opc_data); +static void SUB_90BB(ULO*opc_data); +static void SUB_90BC(ULO*opc_data); +static void SUB_9110(ULO*opc_data); +static void SUB_9118(ULO*opc_data); +static void SUB_9120(ULO*opc_data); +static void SUB_9128(ULO*opc_data); +static void SUB_9130(ULO*opc_data); +static void SUB_9138(ULO*opc_data); +static void SUB_9139(ULO*opc_data); +static void SUB_9150(ULO*opc_data); +static void SUB_9158(ULO*opc_data); +static void SUB_9160(ULO*opc_data); +static void SUB_9168(ULO*opc_data); +static void SUB_9170(ULO*opc_data); +static void SUB_9178(ULO*opc_data); +static void SUB_9179(ULO*opc_data); +static void SUB_9190(ULO*opc_data); +static void SUB_9198(ULO*opc_data); +static void SUB_91A0(ULO*opc_data); +static void SUB_91A8(ULO*opc_data); +static void SUB_91B0(ULO*opc_data); +static void SUB_91B8(ULO*opc_data); +static void SUB_91B9(ULO*opc_data); +static void SUBA_90C0(ULO*opc_data); +static void SUBA_90C8(ULO*opc_data); +static void SUBA_90D0(ULO*opc_data); +static void SUBA_90D8(ULO*opc_data); +static void SUBA_90E0(ULO*opc_data); +static void SUBA_90E8(ULO*opc_data); +static void SUBA_90F0(ULO*opc_data); +static void SUBA_90F8(ULO*opc_data); +static void SUBA_90F9(ULO*opc_data); +static void SUBA_90FA(ULO*opc_data); +static void SUBA_90FB(ULO*opc_data); +static void SUBA_90FC(ULO*opc_data); +static void SUBA_91C0(ULO*opc_data); +static void SUBA_91C8(ULO*opc_data); +static void SUBA_91D0(ULO*opc_data); +static void SUBA_91D8(ULO*opc_data); +static void SUBA_91E0(ULO*opc_data); +static void SUBA_91E8(ULO*opc_data); +static void SUBA_91F0(ULO*opc_data); +static void SUBA_91F8(ULO*opc_data); +static void SUBA_91F9(ULO*opc_data); +static void SUBA_91FA(ULO*opc_data); +static void SUBA_91FB(ULO*opc_data); +static void SUBA_91FC(ULO*opc_data); +static void SUBI_0400(ULO*opc_data); +static void SUBI_0410(ULO*opc_data); +static void SUBI_0418(ULO*opc_data); +static void SUBI_0420(ULO*opc_data); +static void SUBI_0428(ULO*opc_data); +static void SUBI_0430(ULO*opc_data); +static void SUBI_0438(ULO*opc_data); +static void SUBI_0439(ULO*opc_data); +static void SUBI_0440(ULO*opc_data); +static void SUBI_0450(ULO*opc_data); +static void SUBI_0458(ULO*opc_data); +static void SUBI_0460(ULO*opc_data); +static void SUBI_0468(ULO*opc_data); +static void SUBI_0470(ULO*opc_data); +static void SUBI_0478(ULO*opc_data); +static void SUBI_0479(ULO*opc_data); +static void SUBI_0480(ULO*opc_data); +static void SUBI_0490(ULO*opc_data); +static void SUBI_0498(ULO*opc_data); +static void SUBI_04A0(ULO*opc_data); +static void SUBI_04A8(ULO*opc_data); +static void SUBI_04B0(ULO*opc_data); +static void SUBI_04B8(ULO*opc_data); +static void SUBI_04B9(ULO*opc_data); +static void SUBQ_5100(ULO*opc_data); +static void SUBQ_5110(ULO*opc_data); +static void SUBQ_5118(ULO*opc_data); +static void SUBQ_5120(ULO*opc_data); +static void SUBQ_5128(ULO*opc_data); +static void SUBQ_5130(ULO*opc_data); +static void SUBQ_5138(ULO*opc_data); +static void SUBQ_5139(ULO*opc_data); +static void SUBQ_5140(ULO*opc_data); +static void SUBQ_5150(ULO*opc_data); +static void SUBQ_5158(ULO*opc_data); +static void SUBQ_5160(ULO*opc_data); +static void SUBQ_5168(ULO*opc_data); +static void SUBQ_5170(ULO*opc_data); +static void SUBQ_5178(ULO*opc_data); +static void SUBQ_5179(ULO*opc_data); +static void SUBQ_5180(ULO*opc_data); +static void SUBQ_5190(ULO*opc_data); +static void SUBQ_5198(ULO*opc_data); +static void SUBQ_51A0(ULO*opc_data); +static void SUBQ_51A8(ULO*opc_data); +static void SUBQ_51B0(ULO*opc_data); +static void SUBQ_51B8(ULO*opc_data); +static void SUBQ_51B9(ULO*opc_data); +static void SUBQ_5148(ULO*opc_data); +static void SUBQ_5188(ULO*opc_data); +static void CHK_4180(ULO*opc_data); +static void CHK_4190(ULO*opc_data); +static void CHK_4198(ULO*opc_data); +static void CHK_41A0(ULO*opc_data); +static void CHK_41A8(ULO*opc_data); +static void CHK_41B0(ULO*opc_data); +static void CHK_41B8(ULO*opc_data); +static void CHK_41B9(ULO*opc_data); +static void CHK_41BA(ULO*opc_data); +static void CHK_41BB(ULO*opc_data); +static void CHK_41BC(ULO*opc_data); +static void CHK_4100(ULO*opc_data); +static void CHK_4110(ULO*opc_data); +static void CHK_4118(ULO*opc_data); +static void CHK_4120(ULO*opc_data); +static void CHK_4128(ULO*opc_data); +static void CHK_4130(ULO*opc_data); +static void CHK_4138(ULO*opc_data); +static void CHK_4139(ULO*opc_data); +static void CHK_413A(ULO*opc_data); +static void CHK_413B(ULO*opc_data); +static void CHK_413C(ULO*opc_data); +static void CMP_B000(ULO*opc_data); +static void CMP_B010(ULO*opc_data); +static void CMP_B018(ULO*opc_data); +static void CMP_B020(ULO*opc_data); +static void CMP_B028(ULO*opc_data); +static void CMP_B030(ULO*opc_data); +static void CMP_B038(ULO*opc_data); +static void CMP_B039(ULO*opc_data); +static void CMP_B03A(ULO*opc_data); +static void CMP_B03B(ULO*opc_data); +static void CMP_B03C(ULO*opc_data); +static void CMP_B040(ULO*opc_data); +static void CMP_B048(ULO*opc_data); +static void CMP_B050(ULO*opc_data); +static void CMP_B058(ULO*opc_data); +static void CMP_B060(ULO*opc_data); +static void CMP_B068(ULO*opc_data); +static void CMP_B070(ULO*opc_data); +static void CMP_B078(ULO*opc_data); +static void CMP_B079(ULO*opc_data); +static void CMP_B07A(ULO*opc_data); +static void CMP_B07B(ULO*opc_data); +static void CMP_B07C(ULO*opc_data); +static void CMP_B080(ULO*opc_data); +static void CMP_B088(ULO*opc_data); +static void CMP_B090(ULO*opc_data); +static void CMP_B098(ULO*opc_data); +static void CMP_B0A0(ULO*opc_data); +static void CMP_B0A8(ULO*opc_data); +static void CMP_B0B0(ULO*opc_data); +static void CMP_B0B8(ULO*opc_data); +static void CMP_B0B9(ULO*opc_data); +static void CMP_B0BA(ULO*opc_data); +static void CMP_B0BB(ULO*opc_data); +static void CMP_B0BC(ULO*opc_data); +static void CMPA_B0C0(ULO*opc_data); +static void CMPA_B0C8(ULO*opc_data); +static void CMPA_B0D0(ULO*opc_data); +static void CMPA_B0D8(ULO*opc_data); +static void CMPA_B0E0(ULO*opc_data); +static void CMPA_B0E8(ULO*opc_data); +static void CMPA_B0F0(ULO*opc_data); +static void CMPA_B0F8(ULO*opc_data); +static void CMPA_B0F9(ULO*opc_data); +static void CMPA_B0FA(ULO*opc_data); +static void CMPA_B0FB(ULO*opc_data); +static void CMPA_B0FC(ULO*opc_data); +static void CMPA_B1C0(ULO*opc_data); +static void CMPA_B1C8(ULO*opc_data); +static void CMPA_B1D0(ULO*opc_data); +static void CMPA_B1D8(ULO*opc_data); +static void CMPA_B1E0(ULO*opc_data); +static void CMPA_B1E8(ULO*opc_data); +static void CMPA_B1F0(ULO*opc_data); +static void CMPA_B1F8(ULO*opc_data); +static void CMPA_B1F9(ULO*opc_data); +static void CMPA_B1FA(ULO*opc_data); +static void CMPA_B1FB(ULO*opc_data); +static void CMPA_B1FC(ULO*opc_data); +static void CMPI_0C00(ULO*opc_data); +static void CMPI_0C10(ULO*opc_data); +static void CMPI_0C18(ULO*opc_data); +static void CMPI_0C20(ULO*opc_data); +static void CMPI_0C28(ULO*opc_data); +static void CMPI_0C30(ULO*opc_data); +static void CMPI_0C38(ULO*opc_data); +static void CMPI_0C39(ULO*opc_data); +static void CMPI_0C40(ULO*opc_data); +static void CMPI_0C50(ULO*opc_data); +static void CMPI_0C58(ULO*opc_data); +static void CMPI_0C60(ULO*opc_data); +static void CMPI_0C68(ULO*opc_data); +static void CMPI_0C70(ULO*opc_data); +static void CMPI_0C78(ULO*opc_data); +static void CMPI_0C79(ULO*opc_data); +static void CMPI_0C80(ULO*opc_data); +static void CMPI_0C90(ULO*opc_data); +static void CMPI_0C98(ULO*opc_data); +static void CMPI_0CA0(ULO*opc_data); +static void CMPI_0CA8(ULO*opc_data); +static void CMPI_0CB0(ULO*opc_data); +static void CMPI_0CB8(ULO*opc_data); +static void CMPI_0CB9(ULO*opc_data); +static void CMPI_0C3A(ULO*opc_data); +static void CMPI_0C3B(ULO*opc_data); +static void CMPI_0C7A(ULO*opc_data); +static void CMPI_0C7B(ULO*opc_data); +static void CMPI_0CBA(ULO*opc_data); +static void CMPI_0CBB(ULO*opc_data); +static void BCHG_0150(ULO*opc_data); +static void BCHG_0158(ULO*opc_data); +static void BCHG_0160(ULO*opc_data); +static void BCHG_0168(ULO*opc_data); +static void BCHG_0170(ULO*opc_data); +static void BCHG_0178(ULO*opc_data); +static void BCHG_0179(ULO*opc_data); +static void BCHG_0140(ULO*opc_data); +static void BCHG_0850(ULO*opc_data); +static void BCHG_0858(ULO*opc_data); +static void BCHG_0860(ULO*opc_data); +static void BCHG_0868(ULO*opc_data); +static void BCHG_0870(ULO*opc_data); +static void BCHG_0878(ULO*opc_data); +static void BCHG_0879(ULO*opc_data); +static void BCHG_0840(ULO*opc_data); +static void BCLR_0190(ULO*opc_data); +static void BCLR_0198(ULO*opc_data); +static void BCLR_01A0(ULO*opc_data); +static void BCLR_01A8(ULO*opc_data); +static void BCLR_01B0(ULO*opc_data); +static void BCLR_01B8(ULO*opc_data); +static void BCLR_01B9(ULO*opc_data); +static void BCLR_0180(ULO*opc_data); +static void BCLR_0890(ULO*opc_data); +static void BCLR_0898(ULO*opc_data); +static void BCLR_08A0(ULO*opc_data); +static void BCLR_08A8(ULO*opc_data); +static void BCLR_08B0(ULO*opc_data); +static void BCLR_08B8(ULO*opc_data); +static void BCLR_08B9(ULO*opc_data); +static void BCLR_0880(ULO*opc_data); +static void BSET_01D0(ULO*opc_data); +static void BSET_01D8(ULO*opc_data); +static void BSET_01E0(ULO*opc_data); +static void BSET_01E8(ULO*opc_data); +static void BSET_01F0(ULO*opc_data); +static void BSET_01F8(ULO*opc_data); +static void BSET_01F9(ULO*opc_data); +static void BSET_01C0(ULO*opc_data); +static void BSET_08D0(ULO*opc_data); +static void BSET_08D8(ULO*opc_data); +static void BSET_08E0(ULO*opc_data); +static void BSET_08E8(ULO*opc_data); +static void BSET_08F0(ULO*opc_data); +static void BSET_08F8(ULO*opc_data); +static void BSET_08F9(ULO*opc_data); +static void BSET_08C0(ULO*opc_data); +static void BTST_0110(ULO*opc_data); +static void BTST_0118(ULO*opc_data); +static void BTST_0120(ULO*opc_data); +static void BTST_0128(ULO*opc_data); +static void BTST_0130(ULO*opc_data); +static void BTST_0138(ULO*opc_data); +static void BTST_0139(ULO*opc_data); +static void BTST_013A(ULO*opc_data); +static void BTST_013B(ULO*opc_data); +static void BTST_013C(ULO*opc_data); +static void BTST_0100(ULO*opc_data); +static void BTST_0810(ULO*opc_data); +static void BTST_0818(ULO*opc_data); +static void BTST_0820(ULO*opc_data); +static void BTST_0828(ULO*opc_data); +static void BTST_0830(ULO*opc_data); +static void BTST_0838(ULO*opc_data); +static void BTST_0839(ULO*opc_data); +static void BTST_083A(ULO*opc_data); +static void BTST_083B(ULO*opc_data); +static void BTST_0800(ULO*opc_data); +static void LEA_41D0(ULO*opc_data); +static void LEA_41E8(ULO*opc_data); +static void LEA_41F0(ULO*opc_data); +static void LEA_41F8(ULO*opc_data); +static void LEA_41F9(ULO*opc_data); +static void LEA_41FA(ULO*opc_data); +static void LEA_41FB(ULO*opc_data); +static void MULS_C1C0(ULO*opc_data); +static void MULS_C1D0(ULO*opc_data); +static void MULS_C1D8(ULO*opc_data); +static void MULS_C1E0(ULO*opc_data); +static void MULS_C1E8(ULO*opc_data); +static void MULS_C1F0(ULO*opc_data); +static void MULS_C1F8(ULO*opc_data); +static void MULS_C1F9(ULO*opc_data); +static void MULS_C1FA(ULO*opc_data); +static void MULS_C1FB(ULO*opc_data); +static void MULS_C1FC(ULO*opc_data); +static void MULU_C0C0(ULO*opc_data); +static void MULU_C0D0(ULO*opc_data); +static void MULU_C0D8(ULO*opc_data); +static void MULU_C0E0(ULO*opc_data); +static void MULU_C0E8(ULO*opc_data); +static void MULU_C0F0(ULO*opc_data); +static void MULU_C0F8(ULO*opc_data); +static void MULU_C0F9(ULO*opc_data); +static void MULU_C0FA(ULO*opc_data); +static void MULU_C0FB(ULO*opc_data); +static void MULU_C0FC(ULO*opc_data); +static void DIVS_81C0(ULO*opc_data); +static void DIVS_81D0(ULO*opc_data); +static void DIVS_81D8(ULO*opc_data); +static void DIVS_81E0(ULO*opc_data); +static void DIVS_81E8(ULO*opc_data); +static void DIVS_81F0(ULO*opc_data); +static void DIVS_81F8(ULO*opc_data); +static void DIVS_81F9(ULO*opc_data); +static void DIVS_81FA(ULO*opc_data); +static void DIVS_81FB(ULO*opc_data); +static void DIVS_81FC(ULO*opc_data); +static void DIVL_4C40(ULO*opc_data); +static void DIVL_4C50(ULO*opc_data); +static void DIVL_4C58(ULO*opc_data); +static void DIVL_4C60(ULO*opc_data); +static void DIVL_4C68(ULO*opc_data); +static void DIVL_4C70(ULO*opc_data); +static void DIVL_4C78(ULO*opc_data); +static void DIVL_4C79(ULO*opc_data); +static void DIVL_4C7A(ULO*opc_data); +static void DIVL_4C7B(ULO*opc_data); +static void DIVL_4C7C(ULO*opc_data); +static void DIVU_80C0(ULO*opc_data); +static void DIVU_80D0(ULO*opc_data); +static void DIVU_80D8(ULO*opc_data); +static void DIVU_80E0(ULO*opc_data); +static void DIVU_80E8(ULO*opc_data); +static void DIVU_80F0(ULO*opc_data); +static void DIVU_80F8(ULO*opc_data); +static void DIVU_80F9(ULO*opc_data); +static void DIVU_80FA(ULO*opc_data); +static void DIVU_80FB(ULO*opc_data); +static void DIVU_80FC(ULO*opc_data); +static void MOVEM_48A0(ULO*opc_data); +static void MOVEM_48E0(ULO*opc_data); +static void MOVEM_4C98(ULO*opc_data); +static void MOVEM_4CD8(ULO*opc_data); +static void MOVEM_4890(ULO*opc_data); +static void MOVEM_48A8(ULO*opc_data); +static void MOVEM_48B0(ULO*opc_data); +static void MOVEM_48B8(ULO*opc_data); +static void MOVEM_48B9(ULO*opc_data); +static void MOVEM_48D0(ULO*opc_data); +static void MOVEM_48E8(ULO*opc_data); +static void MOVEM_48F0(ULO*opc_data); +static void MOVEM_48F8(ULO*opc_data); +static void MOVEM_48F9(ULO*opc_data); +static void MOVEM_4C90(ULO*opc_data); +static void MOVEM_4CA8(ULO*opc_data); +static void MOVEM_4CB0(ULO*opc_data); +static void MOVEM_4CB8(ULO*opc_data); +static void MOVEM_4CB9(ULO*opc_data); +static void MOVEM_4CBA(ULO*opc_data); +static void MOVEM_4CBB(ULO*opc_data); +static void MOVEM_4CD0(ULO*opc_data); +static void MOVEM_4CE8(ULO*opc_data); +static void MOVEM_4CF0(ULO*opc_data); +static void MOVEM_4CF8(ULO*opc_data); +static void MOVEM_4CF9(ULO*opc_data); +static void MOVEM_4CFA(ULO*opc_data); +static void MOVEM_4CFB(ULO*opc_data); +static void CLR_4200(ULO*opc_data); +static void CLR_4210(ULO*opc_data); +static void CLR_4218(ULO*opc_data); +static void CLR_4220(ULO*opc_data); +static void CLR_4228(ULO*opc_data); +static void CLR_4230(ULO*opc_data); +static void CLR_4238(ULO*opc_data); +static void CLR_4239(ULO*opc_data); +static void CLR_4240(ULO*opc_data); +static void CLR_4250(ULO*opc_data); +static void CLR_4258(ULO*opc_data); +static void CLR_4260(ULO*opc_data); +static void CLR_4268(ULO*opc_data); +static void CLR_4270(ULO*opc_data); +static void CLR_4278(ULO*opc_data); +static void CLR_4279(ULO*opc_data); +static void CLR_4280(ULO*opc_data); +static void CLR_4290(ULO*opc_data); +static void CLR_4298(ULO*opc_data); +static void CLR_42A0(ULO*opc_data); +static void CLR_42A8(ULO*opc_data); +static void CLR_42B0(ULO*opc_data); +static void CLR_42B8(ULO*opc_data); +static void CLR_42B9(ULO*opc_data); +static void BFCHG_EAD0(ULO*opc_data); +static void BFCHG_EAE8(ULO*opc_data); +static void BFCHG_EAF0(ULO*opc_data); +static void BFCHG_EAF8(ULO*opc_data); +static void BFCHG_EAF9(ULO*opc_data); +static void BFCLR_ECD0(ULO*opc_data); +static void BFCLR_ECE8(ULO*opc_data); +static void BFCLR_ECF0(ULO*opc_data); +static void BFCLR_ECF8(ULO*opc_data); +static void BFCLR_ECF9(ULO*opc_data); +static void BFEXTS_EBD0(ULO*opc_data); +static void BFEXTS_EBE8(ULO*opc_data); +static void BFEXTS_EBF0(ULO*opc_data); +static void BFEXTS_EBF8(ULO*opc_data); +static void BFEXTS_EBF9(ULO*opc_data); +static void BFEXTS_EBFA(ULO*opc_data); +static void BFEXTS_EBFB(ULO*opc_data); +static void BFEXTU_E9D0(ULO*opc_data); +static void BFEXTU_E9E8(ULO*opc_data); +static void BFEXTU_E9F0(ULO*opc_data); +static void BFEXTU_E9F8(ULO*opc_data); +static void BFEXTU_E9F9(ULO*opc_data); +static void BFEXTU_E9FA(ULO*opc_data); +static void BFEXTU_E9FB(ULO*opc_data); +static void BFFFO_EDD0(ULO*opc_data); +static void BFFFO_EDE8(ULO*opc_data); +static void BFFFO_EDF0(ULO*opc_data); +static void BFFFO_EDF8(ULO*opc_data); +static void BFFFO_EDF9(ULO*opc_data); +static void BFFFO_EDFA(ULO*opc_data); +static void BFFFO_EDFB(ULO*opc_data); +static void BFINS_EFD0(ULO*opc_data); +static void BFINS_EFE8(ULO*opc_data); +static void BFINS_EFF0(ULO*opc_data); +static void BFINS_EFF8(ULO*opc_data); +static void BFINS_EFF9(ULO*opc_data); +static void BFSET_EED0(ULO*opc_data); +static void BFSET_EEE8(ULO*opc_data); +static void BFSET_EEF0(ULO*opc_data); +static void BFSET_EEF8(ULO*opc_data); +static void BFSET_EEF9(ULO*opc_data); +static void BFTST_E8D0(ULO*opc_data); +static void BFTST_E8E8(ULO*opc_data); +static void BFTST_E8F0(ULO*opc_data); +static void BFTST_E8F8(ULO*opc_data); +static void BFTST_E8F9(ULO*opc_data); +static void BFTST_E8FA(ULO*opc_data); +static void BFTST_E8FB(ULO*opc_data); +static void BFCHG_EAC0(ULO*opc_data); +static void BFCLR_ECC0(ULO*opc_data); +static void BFEXTS_EBC0(ULO*opc_data); +static void BFEXTU_E9C0(ULO*opc_data); +static void BFFFO_EDC0(ULO*opc_data); +static void BFINS_EFC0(ULO*opc_data); +static void BFSET_EEC0(ULO*opc_data); +static void BFTST_E8C0(ULO*opc_data); +static void MULL_4C00(ULO*opc_data); +static void MULL_4C10(ULO*opc_data); +static void MULL_4C18(ULO*opc_data); +static void MULL_4C20(ULO*opc_data); +static void MULL_4C28(ULO*opc_data); +static void MULL_4C30(ULO*opc_data); +static void MULL_4C38(ULO*opc_data); +static void MULL_4C39(ULO*opc_data); +static void MULL_4C3A(ULO*opc_data); +static void MULL_4C3B(ULO*opc_data); +static void MULL_4C3C(ULO*opc_data); +static void MOVES_0E10(ULO*opc_data); +static void MOVES_0E18(ULO*opc_data); +static void MOVES_0E20(ULO*opc_data); +static void MOVES_0E28(ULO*opc_data); +static void MOVES_0E30(ULO*opc_data); +static void MOVES_0E38(ULO*opc_data); +static void MOVES_0E39(ULO*opc_data); +static void MOVES_0E50(ULO*opc_data); +static void MOVES_0E58(ULO*opc_data); +static void MOVES_0E60(ULO*opc_data); +static void MOVES_0E68(ULO*opc_data); +static void MOVES_0E70(ULO*opc_data); +static void MOVES_0E78(ULO*opc_data); +static void MOVES_0E79(ULO*opc_data); +static void MOVES_0E90(ULO*opc_data); +static void MOVES_0E98(ULO*opc_data); +static void MOVES_0EA0(ULO*opc_data); +static void MOVES_0EA8(ULO*opc_data); +static void MOVES_0EB0(ULO*opc_data); +static void MOVES_0EB8(ULO*opc_data); +static void MOVES_0EB9(ULO*opc_data); +static void NBCD_4800(ULO*opc_data); +static void NBCD_4810(ULO*opc_data); +static void NBCD_4818(ULO*opc_data); +static void NBCD_4820(ULO*opc_data); +static void NBCD_4828(ULO*opc_data); +static void NBCD_4830(ULO*opc_data); +static void NBCD_4838(ULO*opc_data); +static void NBCD_4839(ULO*opc_data); +static void NEG_4400(ULO*opc_data); +static void NEG_4410(ULO*opc_data); +static void NEG_4418(ULO*opc_data); +static void NEG_4420(ULO*opc_data); +static void NEG_4428(ULO*opc_data); +static void NEG_4430(ULO*opc_data); +static void NEG_4438(ULO*opc_data); +static void NEG_4439(ULO*opc_data); +static void NEG_4440(ULO*opc_data); +static void NEG_4450(ULO*opc_data); +static void NEG_4458(ULO*opc_data); +static void NEG_4460(ULO*opc_data); +static void NEG_4468(ULO*opc_data); +static void NEG_4470(ULO*opc_data); +static void NEG_4478(ULO*opc_data); +static void NEG_4479(ULO*opc_data); +static void NEG_4480(ULO*opc_data); +static void NEG_4490(ULO*opc_data); +static void NEG_4498(ULO*opc_data); +static void NEG_44A0(ULO*opc_data); +static void NEG_44A8(ULO*opc_data); +static void NEG_44B0(ULO*opc_data); +static void NEG_44B8(ULO*opc_data); +static void NEG_44B9(ULO*opc_data); +static void NEGX_4000(ULO*opc_data); +static void NEGX_4010(ULO*opc_data); +static void NEGX_4018(ULO*opc_data); +static void NEGX_4020(ULO*opc_data); +static void NEGX_4028(ULO*opc_data); +static void NEGX_4030(ULO*opc_data); +static void NEGX_4038(ULO*opc_data); +static void NEGX_4039(ULO*opc_data); +static void NEGX_4040(ULO*opc_data); +static void NEGX_4050(ULO*opc_data); +static void NEGX_4058(ULO*opc_data); +static void NEGX_4060(ULO*opc_data); +static void NEGX_4068(ULO*opc_data); +static void NEGX_4070(ULO*opc_data); +static void NEGX_4078(ULO*opc_data); +static void NEGX_4079(ULO*opc_data); +static void NEGX_4080(ULO*opc_data); +static void NEGX_4090(ULO*opc_data); +static void NEGX_4098(ULO*opc_data); +static void NEGX_40A0(ULO*opc_data); +static void NEGX_40A8(ULO*opc_data); +static void NEGX_40B0(ULO*opc_data); +static void NEGX_40B8(ULO*opc_data); +static void NEGX_40B9(ULO*opc_data); +static void NOT_4600(ULO*opc_data); +static void NOT_4610(ULO*opc_data); +static void NOT_4618(ULO*opc_data); +static void NOT_4620(ULO*opc_data); +static void NOT_4628(ULO*opc_data); +static void NOT_4630(ULO*opc_data); +static void NOT_4638(ULO*opc_data); +static void NOT_4639(ULO*opc_data); +static void NOT_4640(ULO*opc_data); +static void NOT_4650(ULO*opc_data); +static void NOT_4658(ULO*opc_data); +static void NOT_4660(ULO*opc_data); +static void NOT_4668(ULO*opc_data); +static void NOT_4670(ULO*opc_data); +static void NOT_4678(ULO*opc_data); +static void NOT_4679(ULO*opc_data); +static void NOT_4680(ULO*opc_data); +static void NOT_4690(ULO*opc_data); +static void NOT_4698(ULO*opc_data); +static void NOT_46A0(ULO*opc_data); +static void NOT_46A8(ULO*opc_data); +static void NOT_46B0(ULO*opc_data); +static void NOT_46B8(ULO*opc_data); +static void NOT_46B9(ULO*opc_data); +static void TAS_4AC0(ULO*opc_data); +static void TAS_4AD0(ULO*opc_data); +static void TAS_4AD8(ULO*opc_data); +static void TAS_4AE0(ULO*opc_data); +static void TAS_4AE8(ULO*opc_data); +static void TAS_4AF0(ULO*opc_data); +static void TAS_4AF8(ULO*opc_data); +static void TAS_4AF9(ULO*opc_data); +static void TST_4A00(ULO*opc_data); +static void TST_4A10(ULO*opc_data); +static void TST_4A18(ULO*opc_data); +static void TST_4A20(ULO*opc_data); +static void TST_4A28(ULO*opc_data); +static void TST_4A30(ULO*opc_data); +static void TST_4A38(ULO*opc_data); +static void TST_4A39(ULO*opc_data); +static void TST_4A40(ULO*opc_data); +static void TST_4A50(ULO*opc_data); +static void TST_4A58(ULO*opc_data); +static void TST_4A60(ULO*opc_data); +static void TST_4A68(ULO*opc_data); +static void TST_4A70(ULO*opc_data); +static void TST_4A78(ULO*opc_data); +static void TST_4A79(ULO*opc_data); +static void TST_4A80(ULO*opc_data); +static void TST_4A90(ULO*opc_data); +static void TST_4A98(ULO*opc_data); +static void TST_4AA0(ULO*opc_data); +static void TST_4AA8(ULO*opc_data); +static void TST_4AB0(ULO*opc_data); +static void TST_4AB8(ULO*opc_data); +static void TST_4AB9(ULO*opc_data); +static void TST_4A3A(ULO*opc_data); +static void TST_4A3B(ULO*opc_data); +static void TST_4A3C(ULO*opc_data); +static void TST_4A48(ULO*opc_data); +static void TST_4A7A(ULO*opc_data); +static void TST_4A7B(ULO*opc_data); +static void TST_4A7C(ULO*opc_data); +static void TST_4A88(ULO*opc_data); +static void TST_4ABA(ULO*opc_data); +static void TST_4ABB(ULO*opc_data); +static void TST_4ABC(ULO*opc_data); +static void PEA_4850(ULO*opc_data); +static void PEA_4868(ULO*opc_data); +static void PEA_4870(ULO*opc_data); +static void PEA_4878(ULO*opc_data); +static void PEA_4879(ULO*opc_data); +static void PEA_487A(ULO*opc_data); +static void PEA_487B(ULO*opc_data); +static void JMP_4ED0(ULO*opc_data); +static void JMP_4EE8(ULO*opc_data); +static void JMP_4EF0(ULO*opc_data); +static void JMP_4EF8(ULO*opc_data); +static void JMP_4EF9(ULO*opc_data); +static void JMP_4EFA(ULO*opc_data); +static void JMP_4EFB(ULO*opc_data); +static void JSR_4E90(ULO*opc_data); +static void JSR_4EA8(ULO*opc_data); +static void JSR_4EB0(ULO*opc_data); +static void JSR_4EB8(ULO*opc_data); +static void JSR_4EB9(ULO*opc_data); +static void JSR_4EBA(ULO*opc_data); +static void JSR_4EBB(ULO*opc_data); +static void MOVETOSR_46C0(ULO*opc_data); +static void MOVETOSR_46D0(ULO*opc_data); +static void MOVETOSR_46D8(ULO*opc_data); +static void MOVETOSR_46E0(ULO*opc_data); +static void MOVETOSR_46E8(ULO*opc_data); +static void MOVETOSR_46F0(ULO*opc_data); +static void MOVETOSR_46F8(ULO*opc_data); +static void MOVETOSR_46F9(ULO*opc_data); +static void MOVETOSR_46FA(ULO*opc_data); +static void MOVETOSR_46FB(ULO*opc_data); +static void MOVETOSR_46FC(ULO*opc_data); +static void MOVETOCCR_44C0(ULO*opc_data); +static void MOVETOCCR_44D0(ULO*opc_data); +static void MOVETOCCR_44D8(ULO*opc_data); +static void MOVETOCCR_44E0(ULO*opc_data); +static void MOVETOCCR_44E8(ULO*opc_data); +static void MOVETOCCR_44F0(ULO*opc_data); +static void MOVETOCCR_44F8(ULO*opc_data); +static void MOVETOCCR_44F9(ULO*opc_data); +static void MOVETOCCR_44FA(ULO*opc_data); +static void MOVETOCCR_44FB(ULO*opc_data); +static void MOVETOCCR_44FC(ULO*opc_data); +static void SCC_50C0(ULO*opc_data); +static void SCC_50D0(ULO*opc_data); +static void SCC_50D8(ULO*opc_data); +static void SCC_50E0(ULO*opc_data); +static void SCC_50E8(ULO*opc_data); +static void SCC_50F0(ULO*opc_data); +static void SCC_50F8(ULO*opc_data); +static void SCC_50F9(ULO*opc_data); +static void MOVEFROMCCR_42C0(ULO*opc_data); +static void MOVEFROMCCR_42D0(ULO*opc_data); +static void MOVEFROMCCR_42D8(ULO*opc_data); +static void MOVEFROMCCR_42E0(ULO*opc_data); +static void MOVEFROMCCR_42E8(ULO*opc_data); +static void MOVEFROMCCR_42F0(ULO*opc_data); +static void MOVEFROMCCR_42F8(ULO*opc_data); +static void MOVEFROMCCR_42F9(ULO*opc_data); +static void MOVEFROMSR_40C0(ULO*opc_data); +static void MOVEFROMSR_40D0(ULO*opc_data); +static void MOVEFROMSR_40D8(ULO*opc_data); +static void MOVEFROMSR_40E0(ULO*opc_data); +static void MOVEFROMSR_40E8(ULO*opc_data); +static void MOVEFROMSR_40F0(ULO*opc_data); +static void MOVEFROMSR_40F8(ULO*opc_data); +static void MOVEFROMSR_40F9(ULO*opc_data); +static void CAS_0AD0(ULO*opc_data); +static void CAS_0AD8(ULO*opc_data); +static void CAS_0AE0(ULO*opc_data); +static void CAS_0AE8(ULO*opc_data); +static void CAS_0AF0(ULO*opc_data); +static void CAS_0AF8(ULO*opc_data); +static void CAS_0AF9(ULO*opc_data); +static void CAS_0CD0(ULO*opc_data); +static void CAS_0CD8(ULO*opc_data); +static void CAS_0CE0(ULO*opc_data); +static void CAS_0CE8(ULO*opc_data); +static void CAS_0CF0(ULO*opc_data); +static void CAS_0CF8(ULO*opc_data); +static void CAS_0CF9(ULO*opc_data); +static void CAS_0ED0(ULO*opc_data); +static void CAS_0ED8(ULO*opc_data); +static void CAS_0EE0(ULO*opc_data); +static void CAS_0EE8(ULO*opc_data); +static void CAS_0EF0(ULO*opc_data); +static void CAS_0EF8(ULO*opc_data); +static void CAS_0EF9(ULO*opc_data); +static void CHKCMP2_00D0(ULO*opc_data); +static void CHKCMP2_00E8(ULO*opc_data); +static void CHKCMP2_00F0(ULO*opc_data); +static void CHKCMP2_00F8(ULO*opc_data); +static void CHKCMP2_00F9(ULO*opc_data); +static void CHKCMP2_00FA(ULO*opc_data); +static void CHKCMP2_00FB(ULO*opc_data); +static void CHKCMP2_02D0(ULO*opc_data); +static void CHKCMP2_02E8(ULO*opc_data); +static void CHKCMP2_02F0(ULO*opc_data); +static void CHKCMP2_02F8(ULO*opc_data); +static void CHKCMP2_02F9(ULO*opc_data); +static void CHKCMP2_02FA(ULO*opc_data); +static void CHKCMP2_02FB(ULO*opc_data); +static void CHKCMP2_04D0(ULO*opc_data); +static void CHKCMP2_04E8(ULO*opc_data); +static void CHKCMP2_04F0(ULO*opc_data); +static void CHKCMP2_04F8(ULO*opc_data); +static void CHKCMP2_04F9(ULO*opc_data); +static void CHKCMP2_04FA(ULO*opc_data); +static void CHKCMP2_04FB(ULO*opc_data); +static void CALLM_06D0(ULO*opc_data); +static void CALLM_06E8(ULO*opc_data); +static void CALLM_06F0(ULO*opc_data); +static void CALLM_06F8(ULO*opc_data); +static void CALLM_06F9(ULO*opc_data); +static void CALLM_06FA(ULO*opc_data); +static void CALLM_06FB(ULO*opc_data); +static void PFLUSH030_F010(ULO*opc_data); +static void PFLUSH030_F028(ULO*opc_data); +static void PFLUSH030_F030(ULO*opc_data); +static void PFLUSH030_F038(ULO*opc_data); +static void PFLUSH030_F039(ULO*opc_data); +static void MOVEQ_7000(ULO*opc_data); +static void MOVE_1000(ULO*opc_data); +static void MOVE_1008(ULO*opc_data); +static void MOVE_1010(ULO*opc_data); +static void MOVE_1018(ULO*opc_data); +static void MOVE_1020(ULO*opc_data); +static void MOVE_1028(ULO*opc_data); +static void MOVE_1030(ULO*opc_data); +static void MOVE_1038(ULO*opc_data); +static void MOVE_1039(ULO*opc_data); +static void MOVE_103A(ULO*opc_data); +static void MOVE_103B(ULO*opc_data); +static void MOVE_103C(ULO*opc_data); +static void MOVE_1080(ULO*opc_data); +static void MOVE_1088(ULO*opc_data); +static void MOVE_1090(ULO*opc_data); +static void MOVE_1098(ULO*opc_data); +static void MOVE_10A0(ULO*opc_data); +static void MOVE_10A8(ULO*opc_data); +static void MOVE_10B0(ULO*opc_data); +static void MOVE_10B8(ULO*opc_data); +static void MOVE_10B9(ULO*opc_data); +static void MOVE_10BA(ULO*opc_data); +static void MOVE_10BB(ULO*opc_data); +static void MOVE_10BC(ULO*opc_data); +static void MOVE_10C0(ULO*opc_data); +static void MOVE_10C8(ULO*opc_data); +static void MOVE_10D0(ULO*opc_data); +static void MOVE_10D8(ULO*opc_data); +static void MOVE_10E0(ULO*opc_data); +static void MOVE_10E8(ULO*opc_data); +static void MOVE_10F0(ULO*opc_data); +static void MOVE_10F8(ULO*opc_data); +static void MOVE_10F9(ULO*opc_data); +static void MOVE_10FA(ULO*opc_data); +static void MOVE_10FB(ULO*opc_data); +static void MOVE_10FC(ULO*opc_data); +static void MOVE_1100(ULO*opc_data); +static void MOVE_1108(ULO*opc_data); +static void MOVE_1110(ULO*opc_data); +static void MOVE_1118(ULO*opc_data); +static void MOVE_1120(ULO*opc_data); +static void MOVE_1128(ULO*opc_data); +static void MOVE_1130(ULO*opc_data); +static void MOVE_1138(ULO*opc_data); +static void MOVE_1139(ULO*opc_data); +static void MOVE_113A(ULO*opc_data); +static void MOVE_113B(ULO*opc_data); +static void MOVE_113C(ULO*opc_data); +static void MOVE_1140(ULO*opc_data); +static void MOVE_1148(ULO*opc_data); +static void MOVE_1150(ULO*opc_data); +static void MOVE_1158(ULO*opc_data); +static void MOVE_1160(ULO*opc_data); +static void MOVE_1168(ULO*opc_data); +static void MOVE_1170(ULO*opc_data); +static void MOVE_1178(ULO*opc_data); +static void MOVE_1179(ULO*opc_data); +static void MOVE_117A(ULO*opc_data); +static void MOVE_117B(ULO*opc_data); +static void MOVE_117C(ULO*opc_data); +static void MOVE_1180(ULO*opc_data); +static void MOVE_1188(ULO*opc_data); +static void MOVE_1190(ULO*opc_data); +static void MOVE_1198(ULO*opc_data); +static void MOVE_11A0(ULO*opc_data); +static void MOVE_11A8(ULO*opc_data); +static void MOVE_11B0(ULO*opc_data); +static void MOVE_11B8(ULO*opc_data); +static void MOVE_11B9(ULO*opc_data); +static void MOVE_11BA(ULO*opc_data); +static void MOVE_11BB(ULO*opc_data); +static void MOVE_11BC(ULO*opc_data); +static void MOVE_11C0(ULO*opc_data); +static void MOVE_11C8(ULO*opc_data); +static void MOVE_11D0(ULO*opc_data); +static void MOVE_11D8(ULO*opc_data); +static void MOVE_11E0(ULO*opc_data); +static void MOVE_11E8(ULO*opc_data); +static void MOVE_11F0(ULO*opc_data); +static void MOVE_11F8(ULO*opc_data); +static void MOVE_11F9(ULO*opc_data); +static void MOVE_11FA(ULO*opc_data); +static void MOVE_11FB(ULO*opc_data); +static void MOVE_11FC(ULO*opc_data); +static void MOVE_13C0(ULO*opc_data); +static void MOVE_13C8(ULO*opc_data); +static void MOVE_13D0(ULO*opc_data); +static void MOVE_13D8(ULO*opc_data); +static void MOVE_13E0(ULO*opc_data); +static void MOVE_13E8(ULO*opc_data); +static void MOVE_13F0(ULO*opc_data); +static void MOVE_13F8(ULO*opc_data); +static void MOVE_13F9(ULO*opc_data); +static void MOVE_13FA(ULO*opc_data); +static void MOVE_13FB(ULO*opc_data); +static void MOVE_13FC(ULO*opc_data); +static void MOVE_3000(ULO*opc_data); +static void MOVE_3008(ULO*opc_data); +static void MOVE_3010(ULO*opc_data); +static void MOVE_3018(ULO*opc_data); +static void MOVE_3020(ULO*opc_data); +static void MOVE_3028(ULO*opc_data); +static void MOVE_3030(ULO*opc_data); +static void MOVE_3038(ULO*opc_data); +static void MOVE_3039(ULO*opc_data); +static void MOVE_303A(ULO*opc_data); +static void MOVE_303B(ULO*opc_data); +static void MOVE_303C(ULO*opc_data); +static void MOVE_3080(ULO*opc_data); +static void MOVE_3088(ULO*opc_data); +static void MOVE_3090(ULO*opc_data); +static void MOVE_3098(ULO*opc_data); +static void MOVE_30A0(ULO*opc_data); +static void MOVE_30A8(ULO*opc_data); +static void MOVE_30B0(ULO*opc_data); +static void MOVE_30B8(ULO*opc_data); +static void MOVE_30B9(ULO*opc_data); +static void MOVE_30BA(ULO*opc_data); +static void MOVE_30BB(ULO*opc_data); +static void MOVE_30BC(ULO*opc_data); +static void MOVE_30C0(ULO*opc_data); +static void MOVE_30C8(ULO*opc_data); +static void MOVE_30D0(ULO*opc_data); +static void MOVE_30D8(ULO*opc_data); +static void MOVE_30E0(ULO*opc_data); +static void MOVE_30E8(ULO*opc_data); +static void MOVE_30F0(ULO*opc_data); +static void MOVE_30F8(ULO*opc_data); +static void MOVE_30F9(ULO*opc_data); +static void MOVE_30FA(ULO*opc_data); +static void MOVE_30FB(ULO*opc_data); +static void MOVE_30FC(ULO*opc_data); +static void MOVE_3100(ULO*opc_data); +static void MOVE_3108(ULO*opc_data); +static void MOVE_3110(ULO*opc_data); +static void MOVE_3118(ULO*opc_data); +static void MOVE_3120(ULO*opc_data); +static void MOVE_3128(ULO*opc_data); +static void MOVE_3130(ULO*opc_data); +static void MOVE_3138(ULO*opc_data); +static void MOVE_3139(ULO*opc_data); +static void MOVE_313A(ULO*opc_data); +static void MOVE_313B(ULO*opc_data); +static void MOVE_313C(ULO*opc_data); +static void MOVE_3140(ULO*opc_data); +static void MOVE_3148(ULO*opc_data); +static void MOVE_3150(ULO*opc_data); +static void MOVE_3158(ULO*opc_data); +static void MOVE_3160(ULO*opc_data); +static void MOVE_3168(ULO*opc_data); +static void MOVE_3170(ULO*opc_data); +static void MOVE_3178(ULO*opc_data); +static void MOVE_3179(ULO*opc_data); +static void MOVE_317A(ULO*opc_data); +static void MOVE_317B(ULO*opc_data); +static void MOVE_317C(ULO*opc_data); +static void MOVE_3180(ULO*opc_data); +static void MOVE_3188(ULO*opc_data); +static void MOVE_3190(ULO*opc_data); +static void MOVE_3198(ULO*opc_data); +static void MOVE_31A0(ULO*opc_data); +static void MOVE_31A8(ULO*opc_data); +static void MOVE_31B0(ULO*opc_data); +static void MOVE_31B8(ULO*opc_data); +static void MOVE_31B9(ULO*opc_data); +static void MOVE_31BA(ULO*opc_data); +static void MOVE_31BB(ULO*opc_data); +static void MOVE_31BC(ULO*opc_data); +static void MOVE_31C0(ULO*opc_data); +static void MOVE_31C8(ULO*opc_data); +static void MOVE_31D0(ULO*opc_data); +static void MOVE_31D8(ULO*opc_data); +static void MOVE_31E0(ULO*opc_data); +static void MOVE_31E8(ULO*opc_data); +static void MOVE_31F0(ULO*opc_data); +static void MOVE_31F8(ULO*opc_data); +static void MOVE_31F9(ULO*opc_data); +static void MOVE_31FA(ULO*opc_data); +static void MOVE_31FB(ULO*opc_data); +static void MOVE_31FC(ULO*opc_data); +static void MOVE_33C0(ULO*opc_data); +static void MOVE_33C8(ULO*opc_data); +static void MOVE_33D0(ULO*opc_data); +static void MOVE_33D8(ULO*opc_data); +static void MOVE_33E0(ULO*opc_data); +static void MOVE_33E8(ULO*opc_data); +static void MOVE_33F0(ULO*opc_data); +static void MOVE_33F8(ULO*opc_data); +static void MOVE_33F9(ULO*opc_data); +static void MOVE_33FA(ULO*opc_data); +static void MOVE_33FB(ULO*opc_data); +static void MOVE_33FC(ULO*opc_data); +static void MOVE_2000(ULO*opc_data); +static void MOVE_2008(ULO*opc_data); +static void MOVE_2010(ULO*opc_data); +static void MOVE_2018(ULO*opc_data); +static void MOVE_2020(ULO*opc_data); +static void MOVE_2028(ULO*opc_data); +static void MOVE_2030(ULO*opc_data); +static void MOVE_2038(ULO*opc_data); +static void MOVE_2039(ULO*opc_data); +static void MOVE_203A(ULO*opc_data); +static void MOVE_203B(ULO*opc_data); +static void MOVE_203C(ULO*opc_data); +static void MOVE_2080(ULO*opc_data); +static void MOVE_2088(ULO*opc_data); +static void MOVE_2090(ULO*opc_data); +static void MOVE_2098(ULO*opc_data); +static void MOVE_20A0(ULO*opc_data); +static void MOVE_20A8(ULO*opc_data); +static void MOVE_20B0(ULO*opc_data); +static void MOVE_20B8(ULO*opc_data); +static void MOVE_20B9(ULO*opc_data); +static void MOVE_20BA(ULO*opc_data); +static void MOVE_20BB(ULO*opc_data); +static void MOVE_20BC(ULO*opc_data); +static void MOVE_20C0(ULO*opc_data); +static void MOVE_20C8(ULO*opc_data); +static void MOVE_20D0(ULO*opc_data); +static void MOVE_20D8(ULO*opc_data); +static void MOVE_20E0(ULO*opc_data); +static void MOVE_20E8(ULO*opc_data); +static void MOVE_20F0(ULO*opc_data); +static void MOVE_20F8(ULO*opc_data); +static void MOVE_20F9(ULO*opc_data); +static void MOVE_20FA(ULO*opc_data); +static void MOVE_20FB(ULO*opc_data); +static void MOVE_20FC(ULO*opc_data); +static void MOVE_2100(ULO*opc_data); +static void MOVE_2108(ULO*opc_data); +static void MOVE_2110(ULO*opc_data); +static void MOVE_2118(ULO*opc_data); +static void MOVE_2120(ULO*opc_data); +static void MOVE_2128(ULO*opc_data); +static void MOVE_2130(ULO*opc_data); +static void MOVE_2138(ULO*opc_data); +static void MOVE_2139(ULO*opc_data); +static void MOVE_213A(ULO*opc_data); +static void MOVE_213B(ULO*opc_data); +static void MOVE_213C(ULO*opc_data); +static void MOVE_2140(ULO*opc_data); +static void MOVE_2148(ULO*opc_data); +static void MOVE_2150(ULO*opc_data); +static void MOVE_2158(ULO*opc_data); +static void MOVE_2160(ULO*opc_data); +static void MOVE_2168(ULO*opc_data); +static void MOVE_2170(ULO*opc_data); +static void MOVE_2178(ULO*opc_data); +static void MOVE_2179(ULO*opc_data); +static void MOVE_217A(ULO*opc_data); +static void MOVE_217B(ULO*opc_data); +static void MOVE_217C(ULO*opc_data); +static void MOVE_2180(ULO*opc_data); +static void MOVE_2188(ULO*opc_data); +static void MOVE_2190(ULO*opc_data); +static void MOVE_2198(ULO*opc_data); +static void MOVE_21A0(ULO*opc_data); +static void MOVE_21A8(ULO*opc_data); +static void MOVE_21B0(ULO*opc_data); +static void MOVE_21B8(ULO*opc_data); +static void MOVE_21B9(ULO*opc_data); +static void MOVE_21BA(ULO*opc_data); +static void MOVE_21BB(ULO*opc_data); +static void MOVE_21BC(ULO*opc_data); +static void MOVE_21C0(ULO*opc_data); +static void MOVE_21C8(ULO*opc_data); +static void MOVE_21D0(ULO*opc_data); +static void MOVE_21D8(ULO*opc_data); +static void MOVE_21E0(ULO*opc_data); +static void MOVE_21E8(ULO*opc_data); +static void MOVE_21F0(ULO*opc_data); +static void MOVE_21F8(ULO*opc_data); +static void MOVE_21F9(ULO*opc_data); +static void MOVE_21FA(ULO*opc_data); +static void MOVE_21FB(ULO*opc_data); +static void MOVE_21FC(ULO*opc_data); +static void MOVE_23C0(ULO*opc_data); +static void MOVE_23C8(ULO*opc_data); +static void MOVE_23D0(ULO*opc_data); +static void MOVE_23D8(ULO*opc_data); +static void MOVE_23E0(ULO*opc_data); +static void MOVE_23E8(ULO*opc_data); +static void MOVE_23F0(ULO*opc_data); +static void MOVE_23F8(ULO*opc_data); +static void MOVE_23F9(ULO*opc_data); +static void MOVE_23FA(ULO*opc_data); +static void MOVE_23FB(ULO*opc_data); +static void MOVE_23FC(ULO*opc_data); +static void MOVEA_3040(ULO*opc_data); +static void MOVEA_3048(ULO*opc_data); +static void MOVEA_3050(ULO*opc_data); +static void MOVEA_3058(ULO*opc_data); +static void MOVEA_3060(ULO*opc_data); +static void MOVEA_3068(ULO*opc_data); +static void MOVEA_3070(ULO*opc_data); +static void MOVEA_3078(ULO*opc_data); +static void MOVEA_3079(ULO*opc_data); +static void MOVEA_307A(ULO*opc_data); +static void MOVEA_307B(ULO*opc_data); +static void MOVEA_307C(ULO*opc_data); +static void MOVEA_2040(ULO*opc_data); +static void MOVEA_2048(ULO*opc_data); +static void MOVEA_2050(ULO*opc_data); +static void MOVEA_2058(ULO*opc_data); +static void MOVEA_2060(ULO*opc_data); +static void MOVEA_2068(ULO*opc_data); +static void MOVEA_2070(ULO*opc_data); +static void MOVEA_2078(ULO*opc_data); +static void MOVEA_2079(ULO*opc_data); +static void MOVEA_207A(ULO*opc_data); +static void MOVEA_207B(ULO*opc_data); +static void MOVEA_207C(ULO*opc_data); +static void BCCB_6200(ULO*opc_data); +static void BCCB_6300(ULO*opc_data); +static void BCCB_6400(ULO*opc_data); +static void BCCB_6500(ULO*opc_data); +static void BCCB_6600(ULO*opc_data); +static void BCCB_6700(ULO*opc_data); +static void BCCB_6800(ULO*opc_data); +static void BCCB_6900(ULO*opc_data); +static void BCCB_6A00(ULO*opc_data); +static void BCCB_6B00(ULO*opc_data); +static void BCCB_6C00(ULO*opc_data); +static void BCCB_6D00(ULO*opc_data); +static void BCCB_6E00(ULO*opc_data); +static void BCCB_6F00(ULO*opc_data); +static void BCCW_6200(ULO*opc_data); +static void BCCW_6300(ULO*opc_data); +static void BCCW_6400(ULO*opc_data); +static void BCCW_6500(ULO*opc_data); +static void BCCW_6600(ULO*opc_data); +static void BCCW_6700(ULO*opc_data); +static void BCCW_6800(ULO*opc_data); +static void BCCW_6900(ULO*opc_data); +static void BCCW_6A00(ULO*opc_data); +static void BCCW_6B00(ULO*opc_data); +static void BCCW_6C00(ULO*opc_data); +static void BCCW_6D00(ULO*opc_data); +static void BCCW_6E00(ULO*opc_data); +static void BCCW_6F00(ULO*opc_data); +static void BCCL_62FF(ULO*opc_data); +static void BCCL_63FF(ULO*opc_data); +static void BCCL_64FF(ULO*opc_data); +static void BCCL_65FF(ULO*opc_data); +static void BCCL_66FF(ULO*opc_data); +static void BCCL_67FF(ULO*opc_data); +static void BCCL_68FF(ULO*opc_data); +static void BCCL_69FF(ULO*opc_data); +static void BCCL_6AFF(ULO*opc_data); +static void BCCL_6BFF(ULO*opc_data); +static void BCCL_6CFF(ULO*opc_data); +static void BCCL_6DFF(ULO*opc_data); +static void BCCL_6EFF(ULO*opc_data); +static void BCCL_6FFF(ULO*opc_data); +static void BKPT_4848(ULO*opc_data); +static void EXG_C140(ULO*opc_data); +static void EXG_C148(ULO*opc_data); +static void EXG_C188(ULO*opc_data); +static void EXT_4880(ULO*opc_data); +static void EXT_48C0(ULO*opc_data); +static void EXT_49C0(ULO*opc_data); +static void SWAP_4840(ULO*opc_data); +static void LINK_4E50(ULO*opc_data); +static void LINK_4808(ULO*opc_data); +static void UNLK_4E58(ULO*opc_data); +static void BRAB_6000(ULO*opc_data); +static void BRAW_6000(ULO*opc_data); +static void BRAL_60FF(ULO*opc_data); +static void BSRB_6100(ULO*opc_data); +static void BSRW_6100(ULO*opc_data); +static void BSRL_61FF(ULO*opc_data); +static void DBCC_50C8(ULO*opc_data); +static void DBCC_51C8(ULO*opc_data); +static void DBCC_52C8(ULO*opc_data); +static void DBCC_53C8(ULO*opc_data); +static void DBCC_54C8(ULO*opc_data); +static void DBCC_55C8(ULO*opc_data); +static void DBCC_56C8(ULO*opc_data); +static void DBCC_57C8(ULO*opc_data); +static void DBCC_58C8(ULO*opc_data); +static void DBCC_59C8(ULO*opc_data); +static void DBCC_5AC8(ULO*opc_data); +static void DBCC_5BC8(ULO*opc_data); +static void DBCC_5CC8(ULO*opc_data); +static void DBCC_5DC8(ULO*opc_data); +static void DBCC_5EC8(ULO*opc_data); +static void DBCC_5FC8(ULO*opc_data); +static void TRAPCC_50FC(ULO*opc_data); +static void TRAPCC_51FC(ULO*opc_data); +static void TRAPCC_52FC(ULO*opc_data); +static void TRAPCC_53FC(ULO*opc_data); +static void TRAPCC_54FC(ULO*opc_data); +static void TRAPCC_55FC(ULO*opc_data); +static void TRAPCC_56FC(ULO*opc_data); +static void TRAPCC_57FC(ULO*opc_data); +static void TRAPCC_58FC(ULO*opc_data); +static void TRAPCC_59FC(ULO*opc_data); +static void TRAPCC_5AFC(ULO*opc_data); +static void TRAPCC_5BFC(ULO*opc_data); +static void TRAPCC_5CFC(ULO*opc_data); +static void TRAPCC_5DFC(ULO*opc_data); +static void TRAPCC_5EFC(ULO*opc_data); +static void TRAPCC_5FFC(ULO*opc_data); +static void TRAPCC_50FA(ULO*opc_data); +static void TRAPCC_51FA(ULO*opc_data); +static void TRAPCC_52FA(ULO*opc_data); +static void TRAPCC_53FA(ULO*opc_data); +static void TRAPCC_54FA(ULO*opc_data); +static void TRAPCC_55FA(ULO*opc_data); +static void TRAPCC_56FA(ULO*opc_data); +static void TRAPCC_57FA(ULO*opc_data); +static void TRAPCC_58FA(ULO*opc_data); +static void TRAPCC_59FA(ULO*opc_data); +static void TRAPCC_5AFA(ULO*opc_data); +static void TRAPCC_5BFA(ULO*opc_data); +static void TRAPCC_5CFA(ULO*opc_data); +static void TRAPCC_5DFA(ULO*opc_data); +static void TRAPCC_5EFA(ULO*opc_data); +static void TRAPCC_5FFA(ULO*opc_data); +static void TRAPCC_50FB(ULO*opc_data); +static void TRAPCC_51FB(ULO*opc_data); +static void TRAPCC_52FB(ULO*opc_data); +static void TRAPCC_53FB(ULO*opc_data); +static void TRAPCC_54FB(ULO*opc_data); +static void TRAPCC_55FB(ULO*opc_data); +static void TRAPCC_56FB(ULO*opc_data); +static void TRAPCC_57FB(ULO*opc_data); +static void TRAPCC_58FB(ULO*opc_data); +static void TRAPCC_59FB(ULO*opc_data); +static void TRAPCC_5AFB(ULO*opc_data); +static void TRAPCC_5BFB(ULO*opc_data); +static void TRAPCC_5CFB(ULO*opc_data); +static void TRAPCC_5DFB(ULO*opc_data); +static void TRAPCC_5EFB(ULO*opc_data); +static void TRAPCC_5FFB(ULO*opc_data); +static void RTD_4E74(ULO*opc_data); +static void RTE_4E73(ULO*opc_data); +static void RTS_4E75(ULO*opc_data); +static void RTR_4E77(ULO*opc_data); +static void NOP_4E71(ULO*opc_data); +static void MOVEC_4E7A(ULO*opc_data); +static void MOVEC_4E7B(ULO*opc_data); +static void CAS2_0CFC(ULO*opc_data); +static void CAS2_0EFC(ULO*opc_data); +static void TRAP_4E40(ULO*opc_data); +static void TRAPV_4E76(ULO*opc_data); +static void STOP_4E72(ULO*opc_data); +static void RESET_4E70(ULO*opc_data); +static void MOVEUSP_4E60(ULO*opc_data); +static void MOVEUSP_4E68(ULO*opc_data); +static void CMPM_B108(ULO*opc_data); +static void CMPM_B148(ULO*opc_data); +static void CMPM_B188(ULO*opc_data); +static void RTM_06C0(ULO*opc_data); +static void PFLUSH040_F500(ULO*opc_data); +static void PTEST040_F548(ULO*opc_data); +static void ADDX_D100(ULO*opc_data); +static void ADDX_D140(ULO*opc_data); +static void ADDX_D180(ULO*opc_data); +static void ADDX_D108(ULO*opc_data); +static void ADDX_D148(ULO*opc_data); +static void ADDX_D188(ULO*opc_data); +static void SUBX_9100(ULO*opc_data); +static void SUBX_9140(ULO*opc_data); +static void SUBX_9180(ULO*opc_data); +static void SUBX_9108(ULO*opc_data); +static void SUBX_9148(ULO*opc_data); +static void SUBX_9188(ULO*opc_data); +static void ABCD_C100(ULO*opc_data); +static void ABCD_C108(ULO*opc_data); +static void SBCD_8100(ULO*opc_data); +static void SBCD_8108(ULO*opc_data); +static void LSL_E108(ULO*opc_data); +static void LSL_E148(ULO*opc_data); +static void LSL_E188(ULO*opc_data); +static void LSL_E128(ULO*opc_data); +static void LSL_E168(ULO*opc_data); +static void LSL_E1A8(ULO*opc_data); +static void LSL_E3D0(ULO*opc_data); +static void LSL_E3D8(ULO*opc_data); +static void LSL_E3E0(ULO*opc_data); +static void LSL_E3E8(ULO*opc_data); +static void LSL_E3F0(ULO*opc_data); +static void LSL_E3F8(ULO*opc_data); +static void LSL_E3F9(ULO*opc_data); +static void LSR_E008(ULO*opc_data); +static void LSR_E048(ULO*opc_data); +static void LSR_E088(ULO*opc_data); +static void LSR_E028(ULO*opc_data); +static void LSR_E068(ULO*opc_data); +static void LSR_E0A8(ULO*opc_data); +static void LSR_E2D0(ULO*opc_data); +static void LSR_E2D8(ULO*opc_data); +static void LSR_E2E0(ULO*opc_data); +static void LSR_E2E8(ULO*opc_data); +static void LSR_E2F0(ULO*opc_data); +static void LSR_E2F8(ULO*opc_data); +static void LSR_E2F9(ULO*opc_data); +static void ASL_E100(ULO*opc_data); +static void ASL_E140(ULO*opc_data); +static void ASL_E180(ULO*opc_data); +static void ASL_E120(ULO*opc_data); +static void ASL_E160(ULO*opc_data); +static void ASL_E1A0(ULO*opc_data); +static void ASL_E1D0(ULO*opc_data); +static void ASL_E1D8(ULO*opc_data); +static void ASL_E1E0(ULO*opc_data); +static void ASL_E1E8(ULO*opc_data); +static void ASL_E1F0(ULO*opc_data); +static void ASL_E1F8(ULO*opc_data); +static void ASL_E1F9(ULO*opc_data); +static void ASR_E000(ULO*opc_data); +static void ASR_E040(ULO*opc_data); +static void ASR_E080(ULO*opc_data); +static void ASR_E020(ULO*opc_data); +static void ASR_E060(ULO*opc_data); +static void ASR_E0A0(ULO*opc_data); +static void ASR_E0D0(ULO*opc_data); +static void ASR_E0D8(ULO*opc_data); +static void ASR_E0E0(ULO*opc_data); +static void ASR_E0E8(ULO*opc_data); +static void ASR_E0F0(ULO*opc_data); +static void ASR_E0F8(ULO*opc_data); +static void ASR_E0F9(ULO*opc_data); +static void ROL_E118(ULO*opc_data); +static void ROL_E158(ULO*opc_data); +static void ROL_E198(ULO*opc_data); +static void ROL_E138(ULO*opc_data); +static void ROL_E178(ULO*opc_data); +static void ROL_E1B8(ULO*opc_data); +static void ROL_E7D0(ULO*opc_data); +static void ROL_E7D8(ULO*opc_data); +static void ROL_E7E0(ULO*opc_data); +static void ROL_E7E8(ULO*opc_data); +static void ROL_E7F0(ULO*opc_data); +static void ROL_E7F8(ULO*opc_data); +static void ROL_E7F9(ULO*opc_data); +static void ROR_E018(ULO*opc_data); +static void ROR_E058(ULO*opc_data); +static void ROR_E098(ULO*opc_data); +static void ROR_E038(ULO*opc_data); +static void ROR_E078(ULO*opc_data); +static void ROR_E0B8(ULO*opc_data); +static void ROR_E6D0(ULO*opc_data); +static void ROR_E6D8(ULO*opc_data); +static void ROR_E6E0(ULO*opc_data); +static void ROR_E6E8(ULO*opc_data); +static void ROR_E6F0(ULO*opc_data); +static void ROR_E6F8(ULO*opc_data); +static void ROR_E6F9(ULO*opc_data); +static void ROXL_E110(ULO*opc_data); +static void ROXL_E150(ULO*opc_data); +static void ROXL_E190(ULO*opc_data); +static void ROXL_E130(ULO*opc_data); +static void ROXL_E170(ULO*opc_data); +static void ROXL_E1B0(ULO*opc_data); +static void ROXL_E5D0(ULO*opc_data); +static void ROXL_E5D8(ULO*opc_data); +static void ROXL_E5E0(ULO*opc_data); +static void ROXL_E5E8(ULO*opc_data); +static void ROXL_E5F0(ULO*opc_data); +static void ROXL_E5F8(ULO*opc_data); +static void ROXL_E5F9(ULO*opc_data); +static void ROXR_E010(ULO*opc_data); +static void ROXR_E050(ULO*opc_data); +static void ROXR_E090(ULO*opc_data); +static void ROXR_E030(ULO*opc_data); +static void ROXR_E070(ULO*opc_data); +static void ROXR_E0B0(ULO*opc_data); +static void ROXR_E4D0(ULO*opc_data); +static void ROXR_E4D8(ULO*opc_data); +static void ROXR_E4E0(ULO*opc_data); +static void ROXR_E4E8(ULO*opc_data); +static void ROXR_E4F0(ULO*opc_data); +static void ROXR_E4F8(ULO*opc_data); +static void ROXR_E4F9(ULO*opc_data); +static void MOVEP_0188(ULO*opc_data); +static void MOVEP_01C8(ULO*opc_data); +static void MOVEP_0108(ULO*opc_data); +static void MOVEP_0148(ULO*opc_data); +static void PACK_8140(ULO*opc_data); +static void PACK_8148(ULO*opc_data); +static void UNPK_8180(ULO*opc_data); +static void UNPK_8188(ULO*opc_data); +#endif diff --git a/cpu/CpuModule_Disassembler.c b/cpu/CpuModule_Disassembler.c new file mode 100644 index 0000000..f9ddf8d --- /dev/null +++ b/cpu/CpuModule_Disassembler.c @@ -0,0 +1,1764 @@ +/* @(#) $Id: CpuModule_Disassembler.c,v 1.2 2009/07/26 22:56:07 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* CPU disassembly */ +/* */ +/* Author: Petter Schau */ +/* */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ +#include "defs.h" +#include "fmem.h" +#include "CpuModule.h" +#include "CpuModule_DisassemblerFunc.h" + +typedef ULO (*cpuDisFunc)(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands); + +static ULO cpuDisGetSourceMode(UWO opcode) +{ + return (ULO) (opcode >> 3) & 7; +} + +static ULO cpuDisGetDestinationMode(UWO opcode) +{ + return (ULO) (opcode >> 6) & 7; +} + +static ULO cpuDisGetSourceRegister(UWO opcode) +{ + return (ULO) (opcode & 7); +} + +static ULO cpuDisGetDestinationRegister(UWO opcode) +{ + return (ULO) (opcode >> 9) & 7; +} + +static ULO cpuDisGetEaNo(ULO eamode, ULO eareg) +{ + return (eamode < 7) ? eamode : (eamode + eareg); +} + +static ULO cpuDisGetBit(UWO opcode, ULO bit) +{ + return (ULO) ((opcode >> bit) & 1); +} + +static LON cpuDisGetLowByteSignExtend(UWO opc) +{ + return (LON)(BYT)opc; +} + +static ULO cpuDisGetSize(UWO opcode) +{ + ULO result = 0; + switch ((opcode >> 6) & 3) + { + case 0: result = 8; break; + case 1: result = 16; break; + case 2: result = 32; break; + case 3: result = 64; break; + } + return result; +} + +static ULO cpuDisGetSize2(UWO opcode) +{ + ULO result = 0; + switch ((opcode >> 8) & 1) + { + case 0: result = 16; break; + case 1: result = 32; break; + } + return result; +} +static ULO cpuDisGetSize3(UWO opc) +{ + if ((opc & 0x3000) == 0x1000) return 8; + else if ((opc & 0x3000) == 0x3000) return 16; + return 32; +} + +static ULO cpuDisGetSize4(UWO opc) +{ + if ((opc & 0x600) == 0x200) return 8; + else if ((opc & 0x600) == 0x400) return 16; + return 32; +} + +static STR cpuDisSizeChar(ULO size) +{ + return (STR) ((size == 8) ? 'B' : ((size == 16) ? 'W' : 'L')); +} + +static STR *cpu_dis_btab[16] = {"RA", "SR", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", +"PL", "MI", "GE", "LT", "GT", "LE"}; + +static ULO cpuDisGetBranchType(UWO opc) +{ + return (opc >> 8) & 0xf; +} + +/*=========================================================================== +Disassembly of the address-modes +Parameters: +ULO reg - The register used in the address-mode +ULO pcp - The address of the next byte not used. +STR *st - The string to write the dissassembly to. +ULO *pos - The position in the string where the hex-words used are written +Returnvalue: +PC after possible extension words +===========================================================================*/ + +static STR* cpuDisEoS(STR *s) +{ + return s + strlen(s); +} + +static void cpuDisCommaAppend(STR *s) +{ + strcat(s, ","); +} + +static void cpuDisWordAppend(ULO data, STR *sdata) +{ + sprintf(cpuDisEoS(sdata), " %.4X", data); +} + +static void cpuDisLongAppend(ULO data, STR *sdata) +{ + sprintf(cpuDisEoS(sdata), " %.8X", data); +} + +static ULO cpuDis05(ULO regno, ULO pcp, STR *sdata, STR *soperands) +{ + ULO disp = memoryReadWord(pcp); + + cpuDisWordAppend(disp, sdata); + sprintf(cpuDisEoS(soperands), "$%.4X(A%1d)", disp, regno); + return pcp + 2; +} + +static ULO cpuDis06Brief(ULO regno, ULO pcp, ULO ext, BOOLE is_pc_indirect, STR *sdata, STR *soperands) +{ + STR *scale[4] = {"", "*2", "*4", "*8"}; + STR indexregtype = (STR) ((ext & 0x8000) ? 'A' : 'D'); + STR indexsize = (STR) ((ext & 0x0800) ? 'L' : 'W'); + ULO indexregno = (ext >> 12) & 7; + ULO offset = ext & 0xff; + ULO scalefactor = (ext >> 9) & 3; + + cpuDisWordAppend(ext, sdata); + if (cpuGetModelMajor() < 2) + { + if (!is_pc_indirect) + { + sprintf(cpuDisEoS(soperands), "$%.2X(A%1d,%c%1d.%c)", offset, regno, indexregtype, indexregno, indexsize); + } + else + { + sprintf(cpuDisEoS(soperands), "$%.2X(PC,%c%1d.%c)", offset, indexregtype, indexregno, indexsize); + } + } + else + { + if (!is_pc_indirect) + { + sprintf(cpuDisEoS(soperands), "$%.2X(A%1d,%c%1d.%c%s)", offset, regno, indexregtype, indexregno, indexsize, scale[scalefactor]); + } + else + { + sprintf(cpuDisEoS(soperands), "$%.2X(PC,%c%1d.%c%s)", offset, indexregtype, indexregno, indexsize, scale[scalefactor]); + } + } + return pcp; +} + +static ULO cpuDis06Od(ULO pcp, BOOLE wordsize, STR *sdata, STR *soperands) +{ + ULO od; + + if (wordsize) + { + od = memoryReadWord(pcp); + pcp += 2; + cpuDisWordAppend(od, sdata); + sprintf(cpuDisEoS(soperands), "$%.4X", od); + } + else + { + od = memoryReadLong(pcp); + pcp += 4; + cpuDisLongAppend(od, sdata); + sprintf(cpuDisEoS(soperands), "$%.8X", od); + } + return pcp; +} + +static ULO cpuDis06Extended(ULO regno, ULO pcp, ULO ext, BOOLE is_pc_indirect, STR *sdata, STR *soperands) +{ + STR *scale[4] = {"", "*2", "*4", "*8"}; + STR indexregtype = (STR) ((ext & 0x8000) ? 'A' : 'D'); + STR indexsize = (STR)((ext & 0x0800) ? 'L' : 'W'); + ULO indexregno = (ext >> 12) & 7; + ULO scalefactor = (ext >> 9) & 3; + ULO iis = ext & 0x0007; + ULO bdsize = (ext >> 4) & 3; + ULO bd; + BOOLE is = !!(ext & 0x0040); + BOOLE bs = !!(ext & 0x0080); + STR baseregstr[32]; + STR indexstr[32]; + STR basedispstr[32]; + STR outerdispstr[32]; + + baseregstr[0] = '\0'; + indexstr[0] = '\0'; + basedispstr[0] = '\0'; + outerdispstr[0] = '\0'; + + /* Print extension word */ + + cpuDisWordAppend(ext, sdata); + + /* Base register */ + + if (bs) + { /* Base register suppress */ + baseregstr[0] = '\0'; + } + else + { /* Base register included */ + if (is_pc_indirect) + { + strcpy(baseregstr, "PC"); + } + else + { + sprintf(baseregstr, "A%d", regno); + } + } + + /* Index register */ + + if (is) + { /* Index suppress */ + indexstr[0] = '\0'; + } + else + { /* Index included */ + sprintf(indexstr, "%c%d.%c%s", indexregtype, indexregno, indexsize, scale[scalefactor]); + } + + /* Base displacement */ + + if (bdsize < 2) + { + basedispstr[0] = '\0'; + } + else if (bdsize == 2) + { + bd = memoryReadWord(pcp); + pcp += 2; + cpuDisWordAppend(bd, sdata); + sprintf(basedispstr, "$%.4X", bd); + } + else if (bdsize == 3) + { + bd = memoryReadLong(pcp); + pcp += 4; + cpuDisLongAppend(bd, sdata); + sprintf(basedispstr, "$%.8X", bd); + } + + switch (iis) + { /* Evaluate and add index operand */ + case 0: /* No memory indirect action */ + sprintf(cpuDisEoS(soperands), "(%s,%s,%s)", basedispstr, baseregstr, indexstr); + break; + case 1: /* Preindexed with null outer displacement */ + sprintf(cpuDisEoS(soperands), "([%s,%s,%s])", basedispstr, baseregstr, indexstr); + break; + case 2: /* Preindexed with word outer displacement */ + pcp = cpuDis06Od(pcp, TRUE, sdata, outerdispstr); + sprintf(cpuDisEoS(soperands), "([%s,%s,%s],%s)", basedispstr, baseregstr, indexstr, outerdispstr); + break; + case 3: /* Preindexed with long outer displacement */ + pcp = cpuDis06Od(pcp, TRUE, sdata, outerdispstr); + sprintf(cpuDisEoS(soperands), "([%s,%s,%s],%s)", basedispstr, baseregstr, indexstr, outerdispstr); + break; + case 4: /* Reserved ie. Illegal */ + sprintf(cpuDisEoS(soperands), "RESERVED/ILLEGAL"); + break; + case 5: /* Postindexed with null outer displacement */ + if (is) + { + sprintf(cpuDisEoS(soperands), "RESERVED/ILLEGAL"); + } + else + { + sprintf(cpuDisEoS(soperands), "([%s,%s],%s)", basedispstr, baseregstr, indexstr); + } + break; + case 6: /* Postindexed with word outer displacement */ + if (is) + { + sprintf(cpuDisEoS(soperands), "RESERVED/ILLEGAL"); + } + else + { + pcp = cpuDis06Od(pcp, TRUE, sdata, outerdispstr); + sprintf(cpuDisEoS(soperands), "([%s,%s],%s,%s)", basedispstr, baseregstr, indexstr, outerdispstr); + } + break; + case 7: /* Postindexed with long outer displacement */ + if (is) + { + sprintf(cpuDisEoS(soperands), "RESERVED/ILLEGAL"); + } + else + { + pcp = cpuDis06Od(pcp, TRUE, sdata, outerdispstr); + sprintf(cpuDisEoS(soperands), "([%s,%s],%s,%s)", basedispstr, baseregstr, indexstr, outerdispstr); + } + break; + } + return pcp; +} + + +static ULO cpuDis06(ULO regno, ULO pcp, STR *sdata, STR *soperands) +{ + ULO ext = memoryReadWord(pcp); + + if (cpuGetModelMajor() < 2 || !(ext & 0x0100)) + return cpuDis06Brief(regno, pcp + 2, ext, FALSE, sdata, soperands); + else + return cpuDis06Extended(regno, pcp + 2, ext, FALSE, sdata, soperands); +} + +static ULO cpuDis70(ULO pcp, STR *sdata, STR *soperands) +{ + ULO absadr = memoryReadWord(pcp); + + cpuDisWordAppend(absadr, sdata); + sprintf(cpuDisEoS(soperands), "$%.4X", absadr); + return pcp + 2; +} + +static ULO cpuDis71(ULO pcp, STR *sdata, STR *soperands) +{ + ULO absadr = memoryReadLong(pcp); + + cpuDisLongAppend(absadr, sdata); + sprintf(cpuDisEoS(soperands), "$%.8X", absadr); + return pcp + 4; +} + +static ULO cpuDis72(ULO pcp, STR *sdata, STR *soperands) +{ + ULO disp = memoryReadWord(pcp); + + cpuDisWordAppend(disp, sdata); + sprintf(cpuDisEoS(soperands), "$%.4X(PC)", disp); + return pcp + 2; +} + +static ULO cpuDis73(ULO pcp, STR *sdata, STR *soperands) +{ + ULO ext = memoryReadWord(pcp); + + if (cpuGetModelMajor() < 2 || !(ext & 0x0100)) + return cpuDis06Brief(0, pcp + 2, ext, TRUE, sdata, soperands); + else + return cpuDis06Extended(0, pcp + 2, ext, TRUE, sdata, soperands); +} + +static ULO cpuDis74(ULO size, ULO pcp, STR *sdata, STR *soperands) +{ + ULO imm; + + if (size == 8) + { + imm = memoryReadWord(pcp); + cpuDisWordAppend(imm, sdata); + sprintf(cpuDisEoS(soperands), "#$%.2X", imm & 0x00ff); + return pcp + 2; + } + else if (size == 16) + { + imm = memoryReadWord(pcp); + cpuDisWordAppend(imm, sdata); + sprintf(cpuDisEoS(soperands), "#$%.4X", imm); + return pcp + 2; + } + else + { + imm = memoryReadLong(pcp); + cpuDisLongAppend(imm, sdata); + sprintf(cpuDisEoS(soperands), "#$%.8X", imm); + return pcp + 4; + } +} + +static void cpuDisRegCat(BOOLE is_datareg, ULO regno, STR *soperands) +{ + size_t i = strlen(soperands); + + soperands[i++] = (STR) ((is_datareg) ? 'D' : 'A'); + soperands[i++] = (STR) (regno + 0x30); + soperands[i] = '\0'; +} + +static void cpuDisIndRegCat(ULO mode, ULO regno, STR *soperands) +{ + size_t i = strlen(soperands); + + if (mode == 4) soperands[i++] = '-'; + soperands[i++] = '('; + soperands[i++] = 'A'; + soperands[i++] = (STR) (regno + 0x30); + soperands[i++] = ')'; + if (mode == 3) soperands[i++] = '+'; + soperands[i] = '\0'; +} + +static ULO cpuDisAdrMode(ULO eamode, ULO earegno, ULO pcp, ULO size, STR *sdata, STR *soperands) +{ + switch (eamode) + { + case 0: + case 1: cpuDisRegCat(eamode == 0, earegno, soperands); break; + case 2: + case 3: + case 4: cpuDisIndRegCat(eamode, earegno, soperands); break; + case 5: return cpuDis05(earegno, pcp, sdata, soperands); + case 6: return cpuDis06(earegno, pcp, sdata, soperands); + case 7: return cpuDis70(pcp, sdata, soperands); + case 8: return cpuDis71(pcp, sdata, soperands); + case 9: return cpuDis72(pcp, sdata, soperands); + case 10: return cpuDis73(pcp, sdata, soperands); + case 11: return cpuDis74(size, pcp, sdata, soperands); + default: return pcp; + } + return pcp; +} + +/*=============================*/ +/* Common disassembly routines */ +/*=============================*/ + +/* Common disassembly for BCHG, BCLR, BSET, BTST */ + +static ULO cpu_dis_btX_trans[4] = {3, 0, 1, 2}; +static STR *cpu_dis_bnr[4] = {"CHG","CLR","SET","TST"}; + +static ULO cpuDisBtX(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + BOOLE is_reg = cpuDisGetBit(opc, 8); + ULO eareg = cpuDisGetSourceRegister(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + ULO bitreg = cpuDisGetDestinationRegister(opc); + STR sizech = (eamode == 0) ? 'L' : 'B'; + + sprintf(sinstruction, "B%s.%c", cpu_dis_bnr[cpu_dis_btX_trans[(opc >> 6) & 3]], sizech); + if (!is_reg) + { + ULO imm = memoryReadWord(prc + 2); + cpuDisWordAppend(imm, sdata); + sprintf(soperands, "#$%.4X,", imm & ((eamode == 0) ? 0x1f : 7)); + prc += 2; + } + else + { + sprintf(soperands, "D%1X,", bitreg); + } + return cpuDisAdrMode(eamode, eareg, prc + 2, 8, sdata, soperands); +} + +/* Common disassembly for ADD, SUB, CMP, AND, EOR, OR */ + +static STR *cpu_dis_anr[6] = {"ADD","SUB","CMP","AND","EOR","OR"}; + +static ULO cpuDisArith1(ULO prc, UWO opc, ULO nr, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO dreg = cpuDisGetDestinationRegister(opc); + ULO o = cpuDisGetBit(opc, 8); + ULO size = cpuDisGetSize(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + + sprintf(sinstruction, "%s.%c", cpu_dis_anr[nr], cpuDisSizeChar(size)); + prc = cpuDisAdrMode((o) ? 0 : eamode, (o) ? dreg : eareg, prc + 2, size, sdata, soperands); + cpuDisCommaAppend(soperands); + prc = cpuDisAdrMode((o) ? eamode : 0, (o) ? eareg : dreg, prc, size, sdata, soperands); + return prc; +} + +/* Common disassembly for ADDA, SUBA, CMPA */ + +static ULO cpuDisArith2(ULO prc, UWO opc, ULO nr, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO dreg = cpuDisGetDestinationRegister(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + ULO size = cpuDisGetSize2(opc); + + sprintf(sinstruction, "%sA.%c", cpu_dis_anr[nr], cpuDisSizeChar(size)); + prc = cpuDisAdrMode(eamode, eareg, prc + 2, size, sdata, soperands); + cpuDisCommaAppend(soperands); + cpuDisAdrMode(1, dreg, prc, size, sdata, soperands); + return prc; +} + +/* Common disassembly for ADDI, SUBI, CMPI, ANDI, EORI, ORI */ + +static ULO cpuDisArith3(ULO prc, UWO opc, ULO nr, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + ULO size = cpuDisGetSize(opc); + + sprintf(sinstruction, "%sI.%c", cpu_dis_anr[nr], cpuDisSizeChar(size)); + prc = cpuDisAdrMode(11, 4, prc + 2, size, sdata, soperands); + cpuDisCommaAppend(soperands); + if ((nr > 2) && (eamode == 11)) + { + strcat(soperands, (size == 8) ? "CCR" : "SR"); + } + else + { + prc = cpuDisAdrMode(eamode, eareg, prc, size, sdata, soperands); + } + return prc; +} + +/* Common disassembly for ADDQ, SUBQ */ + +static ULO cpuDisArith4(ULO prc, UWO opc, ULO nr, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + ULO size = cpuDisGetSize(opc); + ULO imm = cpuDisGetDestinationRegister(opc); + if (imm == 0) + { + imm = 8; + } + sprintf(sinstruction, "%sQ.%c", cpu_dis_anr[nr], cpuDisSizeChar(size)); + sprintf(soperands, "#$%.1d,", imm); + return cpuDisAdrMode(eamode, eareg, prc + 2, size, sdata, soperands); +} + +/* Common disassembly for ADDX, SUBX, ABCD, SBCD, CMPM */ + +static STR *cpu_dis_a5nr[5] = {"ADDX","SUBX","ABCD","SBCD","CMPM"}; + +static ULO cpuDisArith5(ULO prc, UWO opc, ULO nr, STR *sinstruction, STR *soperands) +{ + ULO bit3 = cpuDisGetBit(opc, 3); + STR *minus = ((nr == 4) || !bit3) ? "" : "-"; + STR *plus = ((nr == 4) && !bit3) ? "+" : ""; + + sprintf(sinstruction, "%s.%c", cpu_dis_a5nr[nr], cpuDisSizeChar(cpuDisGetSize(opc))); + sprintf(soperands, + ((!bit3) ? + "%sD%d%s,%sD%d%s": + "%s(A%d)%s,%s(A%d)%s"), + minus, + cpuDisGetSourceRegister(opc), + plus, + minus, + cpuDisGetDestinationRegister(opc), + plus); + return prc + 2; +} + +/* Common disassembly for ASX, LSX, ROX, ROXX */ + +static STR *cpu_dis_shnr[4] = {"AS", "LS", "RO", "ROX"}; + +static ULO cpuDisShift(ULO prc, UWO opc, ULO nr, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + ULO size = cpuDisGetSize(opc); + STR rl = (STR) ((cpuDisGetBit(opc, 8)) ? 'L' : 'R'); + + if (size == 64) + { + sprintf(sinstruction, "%s%c.W", cpu_dis_shnr[nr], rl); + sprintf(soperands, "#$1,"); + prc = cpuDisAdrMode(eamode, eareg, prc + 2, 16, sdata, soperands); + } + else + { + STR sc = cpuDisSizeChar(size); + ULO dreg = cpuDisGetDestinationRegister(opc); + if (!cpuDisGetBit(opc, 5)) + { + if (dreg == 0) + { + dreg = 8; + } + sprintf(sinstruction, "%s%c.%c", cpu_dis_shnr[nr], rl, sc); + sprintf(soperands, "#$%1X,D%1d", dreg, eareg); + } + else + { + sprintf(sinstruction, "%s%c.%c", cpu_dis_shnr[nr], rl, sc); + sprintf(soperands, "D%1d,D%1d", dreg, eareg); + } + prc += 2; + } + return prc; +} + +/* Common disassembly for CLR, NEG, NOT, TST, JMP, JSR, PEA, NBCD, NEGX */ + +static STR *cpu_dis_unanr[10] = {"CLR","NEG","NOT","TST","JMP","JSR","PEA","TAS","NCBD","NEGX"}; + +static ULO cpuDisUnary(ULO prc, UWO opc, ULO nr, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + ULO size = cpuDisGetSize(opc); + if (nr < 4 || nr > 7) + { + sprintf(sinstruction, "%s.%c", cpu_dis_unanr[nr], cpuDisSizeChar(size)); + } + else + { + sprintf(sinstruction, "%s", cpu_dis_unanr[nr]); + } + return cpuDisAdrMode(eamode, eareg, prc + 2, size, sdata, soperands); +} + +/* Common disassembly for NOP, RESET, RTE, RTR, RTS, TRAPV */ + +static STR *cpu_dis_singnr[6] = {"NOP","RESET","RTE","RTR","RTS","TRAPV"}; + +static ULO cpuDisSingle(ULO prc, ULO nr, STR *sinstruction) +{ + sprintf(sinstruction, "%s", cpu_dis_singnr[nr]); + return prc + 2; +} + +/* Common disassembly for CHK, DIVS, DIVU, LEA, MULS, MULU */ + +static STR *cpu_dis_var1nr[6] = {"CHK","DIVS","DIVU","LEA","MULS","MULU"}; + +static ULO cpuDisVarious1(ULO prc, UWO opc, ULO nr, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + ULO dreg = cpuDisGetDestinationRegister(opc); + + sprintf(sinstruction, "%s.%c", cpu_dis_var1nr[nr], (nr == 3) ? 'L' : 'W'); + prc = cpuDisAdrMode(eamode, eareg, prc + 2, 16, sdata, soperands); + cpuDisCommaAppend(soperands); + return cpuDisAdrMode((nr != 3) ? 0 : 1, dreg, prc, 16, sdata, soperands); +} + +/* Common disassembly for SWAP, UNLK */ + +static STR *cpu_dis_var2nr[2] = {"SWAP","UNLK"}; + +static ULO cpuDisVarious2(ULO prc, UWO opc, ULO nr, STR *sinstruction, STR *soperands) +{ + STR regtype = (STR) ((nr == 0) ? 'D' : 'A'); + sprintf(sinstruction, "%s", cpu_dis_var2nr[nr]); + sprintf(soperands, "%c%1X", regtype, cpuDisGetSourceRegister(opc)); + return prc + 2; +} + +static ULO cpuDisIllegal(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + sprintf(sinstruction, "ILLEGAL"); + return prc + 2; +} + +static ULO cpuDisAbcd(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith5(prc, opc, 2, sinstruction, soperands); +} + +static ULO cpuDisAdd(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith1(prc, opc, 0, sdata, sinstruction, soperands); +} + +static ULO cpuDisAdda(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith2(prc, opc, 0, sdata, sinstruction, soperands); +} + +static ULO cpuDisAddi(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith3(prc, opc, 0, sdata, sinstruction, soperands); +} + +static ULO cpuDisAddq(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith4(prc, opc, 0, sdata, sinstruction, soperands); +} + +static ULO cpuDisAddx(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith5(prc, opc, 0, sinstruction, soperands); +} + +static ULO cpuDisAnd(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith1(prc, opc, 3, sdata, sinstruction, soperands); +} + +static ULO cpuDisAndi(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith3(prc, opc, 3, sdata, sinstruction, soperands); +} + +static ULO cpuDisAsx(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisShift(prc, opc, 0, sdata, sinstruction, soperands); +} + +static ULO cpuDisBcc(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO disp2; + ULO adr; + LON disp = cpuDisGetLowByteSignExtend(opc); + + sprintf(sinstruction, "B%s.%c", cpu_dis_btab[cpuDisGetBranchType(opc)], (disp == -1) ? 'L' : ((disp == 0) ? 'W' : 'B')); + if (disp == 0) + { + prc += 2; + disp2 = memoryReadWord(prc); + cpuDisWordAppend(disp2, sdata); + adr = (disp2 > 32767) ? (prc + disp2 - 65536) : (prc + disp2); + } + else if (disp == -1 && cpuGetModelMajor() >= 2) + { + prc += 2; + disp2 = memoryReadLong(prc); + cpuDisLongAppend(disp2, sdata); + adr = prc + disp2; + } + else + { + adr = prc + 2 + disp; + } + sprintf(cpuDisEoS(soperands), "$%8.8X", adr); + return prc + 2; +} + +static ULO cpuDisBt(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisBtX(prc, opc, sdata, sinstruction, soperands); +} + +static ULO cpuDisChk(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisVarious1(prc, opc, 0, sdata, sinstruction, soperands); +} + +static ULO cpuDisClr(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisUnary(prc, opc, 0, sdata, sinstruction, soperands); +} + +static ULO cpuDisCmp(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith1(prc, opc, 2, sdata, sinstruction, soperands); +} + +static ULO cpuDisCmpa(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith2(prc, opc, 2, sdata, sinstruction, soperands); +} + +static ULO cpuDisCmpi(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith3(prc, opc, 2, sdata, sinstruction, soperands); +} + +static ULO cpuDisCmpm(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith5(prc, opc, 4, sinstruction, soperands); +} + +static ULO cpuDisDBcc(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO offset; + ULO adr; + ULO bratype = cpuDisGetBranchType(opc); + + prc += 2; + offset = memoryReadWord(prc); + adr = (offset > 32767) ? (prc + offset - 65536) : (prc + offset); + cpuDisWordAppend(offset, sdata); + sprintf(sinstruction, "DB%s", (bratype == 0) ? "T" : ((bratype == 1) ? "F" : cpu_dis_btab[bratype])); + sprintf(soperands, "D%1d,$%6.6X", cpuDisGetSourceRegister(opc), adr); + return prc + 2; +} + +static ULO cpuDisDivs(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisVarious1(prc, opc, 1, sdata, sinstruction, soperands); +} + +static ULO cpuDisDivu(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisVarious1(prc, opc, 2, sdata, sinstruction, soperands); +} + +static ULO cpuDisEor(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith1(prc, opc, 4, sdata, sinstruction, soperands); +} + +static ULO cpuDisEori(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisArith3(prc, opc, 4, sdata, sinstruction, soperands); +} + +static ULO cpuDisExg(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO o = (opc & 0x00f8) >> 3; + + sprintf(sinstruction, "EXG.L"); + sprintf(soperands, (o == 8) ? "D%d,D%d" : ((o == 9) ? "A%d,A%d" : "A%d,D%d"), cpuDisGetSourceRegister(opc), cpuDisGetDestinationRegister(opc)); + return prc + 2; +} + +static ULO cpuDisExt(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + sprintf(sinstruction, "EXT.%c", (cpuDisGetBit(opc, 6) == 0) ? 'W' : 'L'); + sprintf(soperands, "D%d", cpuDisGetSourceRegister(opc)); + return prc + 2; +} + +static ULO cpuDisJmp(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisUnary(prc, opc, 4, sdata, sinstruction, soperands); +} + +static ULO cpuDisJsr(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisUnary(prc, opc, 5, sdata, sinstruction, soperands); +} + +static ULO cpuDisLea(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisVarious1(prc, opc, 3, sdata, sinstruction, soperands); +} + +static ULO cpuDisLink(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO imm = memoryReadWord(prc + 2); + + cpuDisWordAppend(imm, sdata); + sprintf(sinstruction, "LINK"); + sprintf(soperands, "A%1d,#$%.4X", cpuDisGetSourceRegister(opc), imm); + return prc + 4; +} + +static ULO cpuDisLsx(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + return cpuDisShift(prc, opc, 1, sdata, sinstruction, soperands); +} + +static ULO cpuDisMove(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO srcreg = cpuDisGetSourceRegister(opc); + ULO srcmode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), srcreg); + ULO dstreg = cpuDisGetDestinationRegister(opc); + ULO dstmode = cpuDisGetEaNo(cpuDisGetDestinationMode(opc), dstreg); + ULO size = cpuDisGetSize3(opc); + + sprintf(sinstruction, "MOVE.%c", cpuDisSizeChar(size)); + prc = cpuDisAdrMode(srcmode, srcreg, prc + 2, size, sdata, soperands); + cpuDisCommaAppend(soperands); + return cpuDisAdrMode(dstmode, dstreg, prc, size, sdata, soperands); +} + +static ULO cpuDisMoveToCcr(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + + sprintf(sinstruction, "MOVE.B"); + prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 2, 8, sdata, soperands); + strcat(soperands, ",CCR"); + return prc; +} + +static ULO cpuDisMoveToSr(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + + sprintf(sinstruction, "MOVE.W"); + prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 2, 16, sdata, soperands); + strcat(soperands, ",SR"); + return prc; +} + +static ULO cpuDisMoveFromSr(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + + sprintf(sinstruction, "MOVE.W"); + sprintf(soperands, "SR,"); + prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 2, 16, sdata, soperands); + return prc; +} + +static ULO cpuDisMoveUsp(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + sprintf(sinstruction, "MOVE.L"); + sprintf(soperands, (cpuDisGetBit(opc, 3)) ? "USP,A%1d" : "A%1d,USP", cpuDisGetSourceRegister(opc)); + return prc + 2; +} + +static ULO cpuDisMovea(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO dreg = cpuDisGetDestinationRegister(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + ULO size = cpuDisGetSize3(opc); + + sprintf(sinstruction, "MOVEA.%c", cpuDisSizeChar(size)); + prc = cpuDisAdrMode(eamode, eareg, prc + 2, size, sdata, soperands); + cpuDisCommaAppend(soperands); + return cpuDisAdrMode(1, dreg, prc, size, sdata, soperands); +} + +static void cpuDisMovemRegmaskStrCat(ULO regmask, STR *s, BOOLE predec) +{ + ULO i, j; + STR tmp[2][16]; + STR *tmpp; + + for (j = 0; j < 2; j++) + { + tmpp = tmp[j]; + for (i = (8*j); i < (8 + (8*j)); i++) + { + if (regmask & (1<> 8) & 7; + ULO offset = (ext & 0x7c0) >> 6; + ULO width = ext & 0x1f; + STR stmp[16]; + + cpuDisWordAppend(ext, sdata); + sprintf(sinstruction, "BF%s", cpu_dis_bftxt[n]); + if (n == 7) + { + sprintf(stmp, "D%d,", (ext >> 12) & 7); + strcat(soperands, stmp); + } + prc = cpuDisAdrMode(eamode, eareg, prc + 4, 16, sdata, soperands); + if (ext & 0x800) + { + sprintf(stmp, "{D%d:", offset & 7); + } + else + { + sprintf(stmp, "{%d:", offset); + } + strcat(soperands, stmp); + if (ext & 0x20) + { + sprintf(stmp, "D%d}", width & 7); + } + else + { + sprintf(stmp, "%d}", width); + } + strcat(soperands, stmp); + if ((n == 1) || (n == 3) || (n == 7)) + { + sprintf(stmp, ",D%d", (ext >> 12) & 7); + strcat(soperands, stmp); + } + return prc; +} + +static ULO cpuDisCas(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO ext = memoryReadWord(prc + 2); + ULO size = cpuDisGetSize4(opc); + + cpuDisWordAppend(ext, sdata); + if ((opc & 0x3f) == 0x3c) + { /* CAS2 */ + ULO ext2 = memoryReadWord(prc + 4); + cpuDisWordAppend(ext2, sdata); + sprintf(sinstruction, "CAS2.%c", cpuDisSizeChar(size)); + + sprintf(soperands, + "D%d:D%d,D%d:D%d,(%s%d):(%s%d)", + ext & 7, + ext2 & 7, + (ext >> 6) & 7, + (ext2 >> 6) & 7, + (ext & 0x8000) ? "A" : "D", + (ext >> 12) & 7, + (ext2 & 0x8000) ? "A" : "D", + (ext2 >> 12) & 7); + prc += 6; + } + else + { + sprintf(sinstruction, "CAS.%c", cpuDisSizeChar(size)); + sprintf(soperands, "D%d,D%d,", ext & 7, (ext >> 6) & 7); + prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, size, sdata, soperands); + } + return prc; +} + +static ULO cpuDisChkl(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + + sprintf(sinstruction, "CHK.L"); + prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 2, 32, sdata, soperands); + cpuDisCommaAppend(soperands); + return cpuDisAdrMode(0, cpuDisGetDestinationRegister(opc), prc + 2, 32, sdata, soperands); +} + +static ULO cpuDisChk2(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO ext = memoryReadWord(prc + 2); + ULO size = cpuDisGetSize4(opc); + STR stmp[16]; + + cpuDisWordAppend(ext, sdata); + sprintf(sinstruction, "%s.%c", (ext & 0x800) ? "CHK2" : "CMP2", cpuDisSizeChar(size)); + prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, size, sdata, soperands); + sprintf(stmp, ",%s%d", (ext & 0x8000) ? "A" : "D", (ext>>12) & 7); + strcat(soperands, stmp); + return prc; +} + +static ULO cpuDisDivl(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO ext = memoryReadWord(prc + 2); + ULO dq; + ULO dr; + STR stmp[16]; + + cpuDisWordAppend(ext, sdata); + dq = (ext >> 12) & 7; + dr = ext & 7; + sprintf(sinstruction, "DIV%c%s.L ", (ext & 0x800) ? 'S' : 'U', (ext & 0x400) ? "L" : ""); + prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, 32, sdata, soperands); + if (ext & 0x400) + { + sprintf(stmp, ",D%d:D%d", dr, dq); + } + else + { + sprintf(stmp, ",D%d", dq); + } + strcat(soperands, stmp); + return prc; +} + +static ULO cpuDisExtb(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + sprintf(sinstruction, "EXTB.L"); + sprintf(soperands, "D%d", cpuDisGetSourceRegister(opc)); + return prc + 2; +} + +static ULO cpuDisLinkl(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO disp = memoryReadLong(prc + 2); + cpuDisLongAppend(disp, sdata); + sprintf(sinstruction, "LINK.L"); + sprintf(soperands, "A%d, #$%.8X", cpuDisGetSourceRegister(opc), disp); + return prc + 6; +} + +static ULO cpuDisMoveFromCcr(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + sprintf(sinstruction, "MOVE.W"); + sprintf(soperands, "CCR,"); + return cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 2, 16, sdata, soperands); +} + +static ULO cpuDisMovec(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO creg; + ULO extw = memoryReadWord(prc + 2); + STR stmp[16]; + + cpuDisWordAppend(extw, sdata); + sprintf(sinstruction, "MOVEC.L"); + if (opc & 1) + { /* To control register */ + sprintf(stmp, "%s%d,", (extw & 0x8000) ? "A" : "D", (extw>>12) & 7); + strcat(soperands, stmp); + } + creg = extw & 0xfff; + if (cpuGetModelMajor() == 1 && ((creg != 0) && (creg != 1) && (creg != 0x800) && + (creg != 0x801))) creg = 0xfff; + switch (creg) + { + case 0x000: /* SFC, Source function code X12346*/ + strcat(soperands, "SFC"); + break; + case 0x001: /* DFC, Destination function code X12346 */ + strcat(soperands, "DFC"); + break; + case 0x800: /* USP, User stack pointer X12346 */ + strcat(soperands, "USP"); + break; + case 0x801: /* VBR, Vector base register X12346 */ + strcat(soperands, "VBR"); + break; + case 0x002: /* CACR, Cache control register XX2346 */ + strcat(soperands, "CACR"); + break; + case 0x802: /* CAAR, Cache adress register XX2346 */ + strcat(soperands, "CAAR"); + break; + case 0x803: /* MSP, Master stack pointer XX234X */ + strcat(soperands, "MSP"); + break; + case 0x804: /* ISP, Interrupt stack pointer XX234X */ + strcat(soperands, "ISP"); + break; + default: + strcat(soperands, "ILLEGAL"); + break; + } + if (!(opc & 1)) + { /* From control register */ + sprintf(stmp, ",%s%d", (extw & 0x8000) ? "A":"D", (extw >> 12) & 7); + strcat(soperands, stmp); + } + return prc + 4; +} + +static ULO cpuDisMoves(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO ext = memoryReadWord(prc + 2); + ULO size = cpuDisGetSize(opc); + STR stmp[16]; + + cpuDisWordAppend(ext, sdata); + sprintf(sinstruction, "MOVES.%c", cpuDisSizeChar(size)); + if (ext & 0x800) + { + sprintf(stmp, "%s%d,", (ext & 0x8000) ? "A" : "D", (ext >> 12) & 7); + strcat(soperands, stmp); + } + prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, size, sdata, soperands); + if (!(ext & 0x800)) + { + sprintf(stmp, ",%s%d", (ext & 0x8000) ? "A" : "D", (ext >> 12) & 7); + strcat(soperands, stmp); + } + return prc; +} + +static ULO cpuDisMull(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO ext = memoryReadWord(prc + 2); + ULO dl; + ULO dh; + STR stmp[16]; + + dl = (ext>>12) & 7; + dh = ext & 7; + cpuDisWordAppend(ext, sdata); + sprintf(sinstruction, "MUL%c.L", (ext & 0x800) ? 'S' : 'U'); + prc = cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, 32, sdata, soperands); + if (ext & 0x400) + { + sprintf(stmp, ",D%d:D%d", dh, dl); + } + else + { + sprintf(stmp, ",D%d", dl); + } + strcat(soperands, stmp); + return prc; +} + +static ULO cpuDisPack(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO sreg = cpuDisGetSourceRegister(opc); + ULO dreg = cpuDisGetDestinationRegister(opc); + ULO mode = (opc & 8)>>1; + ULO adjw = memoryReadWord(prc + 2); + STR tmp[16]; + + cpuDisWordAppend(adjw, sdata); + sprintf(sinstruction, "PACK"); + prc = cpuDisAdrMode(mode, sreg, prc + 4, 16, sdata, soperands); + cpuDisCommaAppend(soperands); + prc = cpuDisAdrMode(mode, dreg, prc, 16, sdata, soperands); + sprintf(tmp, ",#$%.4X", adjw); + strcat(soperands, tmp); + return prc; +} + +/* Disassemble for 030 */ + +static void cpuDisPflush030PrintFc(STR *soperands, ULO fcode) +{ + STR stmp[16]; + if (fcode == 0) strcat(soperands, "SFC,"); + else if (fcode == 1) strcat(soperands, "DFC,"); + else if ((fcode & 0x18) == 8) + { + sprintf(stmp, "D%d,", fcode & 7); + strcat(soperands, stmp); + } + else if ((fcode & 0x18) == 0x10) + { + sprintf(stmp, "#%d,", fcode & 7); + strcat(soperands, stmp); + } +} + +static ULO cpuDisPflush030(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO eamode = cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg); + ULO ext = memoryReadWord(prc + 2); + ULO mode = (ext >> 10) & 7; + ULO fcode = ext & 0x1f; + ULO mask = ext & 0x1f; + ULO op = (ext >> 13) & 7; + STR stmp[16]; + + cpuDisWordAppend(ext, sdata); + if (op == 0x1) + { + if (mode != 0) + { /* PFLUSH */ + sprintf(sinstruction, "PFLUSH%s", (mode == 1) ? "A" : ""); + prc += 4; + if (mode != 1) + { + cpuDisPflush030PrintFc(soperands, fcode); + sprintf(stmp, "%.3X", mask); + strcat(soperands, stmp); + if (mode == 6) + { + cpuDisCommaAppend(soperands); + prc = cpuDisAdrMode(eamode, eareg, prc, 16, sdata, soperands); + } + } + } + else + { /* PLOAD */ + sprintf(sinstruction, "PLOAD%c", (ext & 0x200) ? 'R':'W'); + prc += 4; + cpuDisPflush030PrintFc(soperands, fcode); + cpuDisCommaAppend(soperands); + prc = cpuDisAdrMode(eamode, eareg, prc, 16, sdata, soperands); + } + } + else if (op == 4) + { /* PTEST */ + sprintf(sinstruction, "PTEST"); + prc += 4; + prc = cpuDisAdrMode(eamode, eareg, prc, 16, sdata, soperands); + } + else if (op == 0 || op == 2 || op == 3) + { /* PMOVE */ + sprintf(sinstruction, "PMOVE"); + prc += 4; + prc = cpuDisAdrMode(eamode, eareg, prc, 16, sdata, soperands); + } + return prc; +} + +/* PFLUSH disassemble for 68040 */ + +static ULO cpuDisPflush040(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO reg = cpuDisGetSourceRegister(opc); + ULO opmode = (opc & 0x18)>>3; + + switch (opmode) + { + case 0: + sprintf(sinstruction, "PFLUSHN"); + sprintf(soperands, "(A%d)", reg); + break; + case 1: + sprintf(sinstruction, "PFLUSH"); + sprintf(soperands, "(A%d)", reg); + break; + case 2: + sprintf(sinstruction, "PFLUSHAN"); + break; + case 3: + sprintf(sinstruction, "PFLUSHA"); + break; + } + return prc + 2; +} + +/* PTEST disassemble on 68040 */ + +static ULO cpuDisPtest040(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO reg = cpuDisGetSourceRegister(opc); + ULO rw = cpuDisGetBit(opc, 5); + + sprintf(sinstruction, "PTEST%c", (rw) ? 'R' : 'W'); + sprintf(soperands, "(A%d)", reg); + return prc + 2; +} + +static ULO cpuDisRtd(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO extw = memoryReadWord(prc + 2); + cpuDisWordAppend(extw, sdata); + sprintf(sinstruction, "RTD"); + sprintf(soperands, "#%.4X", extw); + return prc + 4; +} + +static ULO cpuDisTrapcc(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO bratype = cpuDisGetBranchType(opc); + ULO ext = 0; + ULO op = (opc & 7) - 2; + + sprintf(sinstruction, "TRAP%s", (bratype == 0) ? "T" : ((bratype == 1) ? "F" : cpu_dis_btab[bratype])); + if (op == 0) + { + ext = memoryReadWord(prc + 2); + prc += 2; + cpuDisWordAppend(ext, sdata); + strcat(sinstruction, ".W"); + sprintf(soperands, "#%.4X", ext); + } + else if (op == 1) + { + ext = memoryReadLong(prc + 2); + prc += 4; + cpuDisLongAppend(ext, sdata); + strcat(sinstruction, ".L"); + sprintf(soperands, "#%.8X", ext); + } + return prc + 2; +} + +static ULO cpuDisUnpk(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO sreg = cpuDisGetSourceRegister(opc); + ULO dreg = cpuDisGetDestinationRegister(opc); + ULO mode = (opc & 8)>>1; + ULO adjw = memoryReadWord(prc + 2); + STR tmp[16]; + + cpuDisWordAppend(adjw, sdata); + sprintf(sinstruction, "UNPK"); + prc = cpuDisAdrMode(mode, sreg, prc + 4, 16, sdata, soperands); + cpuDisCommaAppend(soperands); + prc = cpuDisAdrMode(mode, dreg, prc, 16, sdata, soperands); + sprintf(tmp, ",#$%.4X", adjw); + strcat(soperands, tmp); + return prc; +} + +static ULO cpuDisCallm(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + ULO eareg = cpuDisGetSourceRegister(opc); + ULO ext = memoryReadWord(prc + 2); + cpuDisWordAppend(ext, sdata); + sprintf(soperands, "#%d,", ext & 0xff); + return cpuDisAdrMode(cpuDisGetEaNo(cpuDisGetSourceMode(opc), eareg), eareg, prc + 4, 16, sdata, soperands); +} + +static ULO cpuDisRtm(ULO prc, UWO opc, STR *sdata, STR *sinstruction, STR *soperands) +{ + sprintf(sinstruction, "RTM"); + sprintf(soperands, "%c%d", (opc & 8) ? 'A':'D', cpuDisGetSourceRegister(opc)); + return prc + 2; +} + +static cpuDisFunc cpu_dis_index[100] = +{ + cpuDisIllegal, // 0 + cpuDisAbcd, + cpuDisAdd, + cpuDisAdda, + cpuDisAddi, + cpuDisAddq, // 5 + cpuDisAddx, + cpuDisAnd, + cpuDisAndi, + cpuDisAsx, + cpuDisBcc, // 10 + cpuDisBt, + cpuDisBkpt, + cpuDisBf, + cpuDisCallm, + cpuDisCas, // 15 + cpuDisChk, + cpuDisChk2, + cpuDisChkl, + cpuDisClr, + cpuDisCmp, // 20 + cpuDisCmpa, + cpuDisCmpi, + cpuDisCmpm, + cpuDisDBcc, + cpuDisDivl, // 25 + cpuDisDivs, + cpuDisDivu, + cpuDisEor, + cpuDisEori, + cpuDisExg, // 30 + cpuDisExt, + cpuDisExtb, + cpuDisJmp, + cpuDisJsr, + cpuDisLea, // 35 + cpuDisLink, + cpuDisLinkl, + cpuDisLsx, + cpuDisMove, + cpuDisMovea, // 40 + cpuDisMovec, + cpuDisMoveFromCcr, + cpuDisMoveFromSr, + cpuDisMovem, + cpuDisMovep, // 45 + cpuDisMoveq, + cpuDisMoves, + cpuDisMoveToCcr, + cpuDisMoveToSr, + cpuDisMoveUsp, // 50 + cpuDisMull, + cpuDisMuls, + cpuDisMulu, + cpuDisNbcd, + cpuDisNeg, // 55 + cpuDisNegx, + cpuDisNop, + cpuDisNot, + cpuDisOr, + cpuDisOri, // 60 + cpuDisPack, + cpuDisPea, + cpuDisPflush030, + cpuDisPflush040, + cpuDisPtest040, // 65 + cpuDisReset, + cpuDisRox, + cpuDisRoxx, + cpuDisRtd, + cpuDisRte, // 70 + cpuDisRtm, + cpuDisRtr, + cpuDisRts, + cpuDisSbcd, + cpuDisScc, // 75 + cpuDisStop, + cpuDisSub, + cpuDisSuba, + cpuDisSubi, + cpuDisSubq, // 80 + cpuDisSubx, + cpuDisSwap, + cpuDisTas, + cpuDisTrap, + cpuDisTrapcc, // 85 + cpuDisTrapv, + cpuDisTst, + cpuDisUnlk, + cpuDisUnpk // 89 +}; + +ULO cpuDisOpcode(ULO disasm_pc, STR *saddress, STR *sdata, STR *sinstruction, STR *soperands) +{ + UWO opcode = (UWO) memoryReadWord(disasm_pc); + sprintf(saddress, "$%.8X", disasm_pc); + sprintf(sdata, "%.4X", opcode); + return cpu_dis_index[cpu_dis_func_tab[opcode]](disasm_pc, opcode, sdata, sinstruction, soperands); +} diff --git a/cpu/CpuModule_Disassembler.h b/cpu/CpuModule_Disassembler.h new file mode 100644 index 0000000..5dc77f3 --- /dev/null +++ b/cpu/CpuModule_Disassembler.h @@ -0,0 +1,97 @@ +#ifndef CPUMODULE_DISASSEMBLER_H +#define CPUMODULE_DISASSEMBLER_H + +extern ULO cpuDisOpcode(ULO disasm_pc, STR *saddress, STR *sdata, STR *sinstruction, STR *soperands); + +extern ULO cpuDisIllegal(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisAbcd(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisAdd(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisAdda(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisAddi(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisAddq(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisAddx(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisAnd(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisAndi(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisAsx(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisBcc(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisBt(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisChk(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisClr(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisCmp(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisCmpa(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisCmpi(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisCmpm(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisDBcc(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisDivs(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisDivu(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisEor(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisEori(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisExg(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisExt(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisJmp(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisJsr(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisLea(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisLink(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisLsx(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMove(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMoveToCcr(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMoveToSr(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMoveFromSr(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMoveUsp(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMovea(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMovem(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMovep(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMoveq(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMuls(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMulu(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisNbcd(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisNeg(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisNegx(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisNop(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisNot(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisOr(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisOri(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisPea(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisReset(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisRox(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisRoxx(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisRte(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisRtr(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisRts(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisSbcd(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisScc(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisStop(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisSub(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisSuba(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisSubi(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisSubq(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisSubx(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisSwap(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisTas(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisTrap(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisTrapv(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisTst(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisUnlk(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisBkpt(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisBf(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisCas(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisChkl(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisChk2(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisDivl(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisExtb(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisLinkl(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMoveFromCcr(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMovec(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMoves(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisMull(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisPack(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisPflush030(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisPflush040(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisPtest040(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisRtd(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisTrapcc(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisUnpk(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisCallm(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); +extern ULO cpuDisRtm(ULO prc, ULO opc, STR *sdata, STR *sinstruction, STR *soperands); + +#endif diff --git a/cpu/CpuModule_DisassemblerFunc.h b/cpu/CpuModule_DisassemblerFunc.h new file mode 100644 index 0000000..02ce766 --- /dev/null +++ b/cpu/CpuModule_DisassemblerFunc.h @@ -0,0 +1,4103 @@ +#ifndef CPUMODULE_DISASSEMBLERFUNC_H +#define CPUMODULE_DISASSEMBLERFUNC_H + +static UBY cpu_dis_func_tab[65536] = +{ +60,60,60,60,60,60,60,60,0,0,0,0,0,0,0,0, +60,60,60,60,60,60,60,60,60,60,60,60,60,60,60,60, +60,60,60,60,60,60,60,60,60,60,60,60,60,60,60,60, +60,60,60,60,60,60,60,60,60,60,0,0,60,0,0,0, +60,60,60,60,60,60,60,60,0,0,0,0,0,0,0,0, +60,60,60,60,60,60,60,60,60,60,60,60,60,60,60,60, +60,60,60,60,60,60,60,60,60,60,60,60,60,60,60,60, +60,60,60,60,60,60,60,60,60,60,0,0,60,0,0,0, +60,60,60,60,60,60,60,60,0,0,0,0,0,0,0,0, +60,60,60,60,60,60,60,60,60,60,60,60,60,60,60,60, +60,60,60,60,60,60,60,60,60,60,60,60,60,60,60,60, +60,60,60,60,60,60,60,60,60,60,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +17,17,17,17,17,17,17,17,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,17,17,17,17,17,17,17,17, +17,17,17,17,17,17,17,17,17,17,17,17,0,0,0,0, +11,11,11,11,11,11,11,11,45,45,45,45,45,45,45,45, +11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, +11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, +11,11,11,11,11,11,11,11,11,11,11,11,11,0,0,0, +11,11,11,11,11,11,11,11,45,45,45,45,45,45,45,45, +11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, +11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, +11,11,11,11,11,11,11,11,11,11,0,0,0,0,0,0, +11,11,11,11,11,11,11,11,45,45,45,45,45,45,45,45, +11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, +11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, +11,11,11,11,11,11,11,11,11,11,0,0,0,0,0,0, +11,11,11,11,11,11,11,11,45,45,45,45,45,45,45,45, +11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, 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+/* CPU 68k effective address calculation functions */ +/* */ +/* Author: Petter Schau */ +/* */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ + +#include "defs.h" +#include "fellow.h" +#include "fmem.h" + +#include "CpuModule.h" +#include "CpuModule_Internal.h" + +/* Calculates EA for (Ax). */ +ULO cpuEA02(ULO regno) +{ + return cpuGetAReg(regno); +} + +/* Calculates EA for (Ax)+ */ +ULO cpuEA03(ULO regno, ULO size) +{ + ULO tmp = cpuGetAReg(regno); + if (regno == 7 && size == 1) size++; + cpuSetAReg(regno, tmp + size); + return tmp; +} + +/* Calculates EA for -(Ax) */ +ULO cpuEA04(ULO regno, ULO size) +{ + if (regno == 7 && size == 1) size++; + cpuSetAReg(regno, cpuGetAReg(regno) - size); + return cpuGetAReg(regno); +} + +/* Calculates EA for disp16(Ax) */ +ULO cpuEA05(ULO regno) +{ + return cpuGetAReg(regno) + cpuGetNextWordSignExt(); +} + +/* Calculates EA for disp8(Ax,Ri.size) with 68020 extended modes. */ +static ULO cpuEA06Ext(UWO ext, ULO base_reg_value, ULO index_value) +{ + ULO base_displacement; + ULO outer_displacement; + BOOLE index_register_suppressed = (ext & 0x0040); + BOOLE base_register_suppressed = (ext & 0x0080); + ULO base_displacement_size = (ext >> 4) & 3; + ULO memory_indirect_action = (ext & 7); + + if (memory_indirect_action == 4 + || (memory_indirect_action > 4 && index_register_suppressed)) + { + cpuThrowIllegalInstructionException(TRUE); /* Illegal instruction */ + // Never returns + } + + if (index_register_suppressed) + { + index_value = 0; + } + + if (base_register_suppressed) + { + base_reg_value = 0; + } + + switch (base_displacement_size) + { + case 0: /* Reserved */ + cpuThrowIllegalInstructionException(TRUE); /* Illegal instruction */ + break; + case 1: /* Null base displacement */ + base_displacement = 0; + break; + case 2: /* Word base displacement */ + base_displacement = cpuGetNextWordSignExt(); + break; + case 3: /* Long base displacement */ + base_displacement = cpuGetNextLong(); + break; + } + + switch (memory_indirect_action) + { + case 0: /* No memory indirect action */ + return base_reg_value + base_displacement + index_value; + case 1: /* Indirect preindexed with null outer displacement */ + return memoryReadLong(base_reg_value + base_displacement + index_value); + case 2: /* Indirect preindexed with word outer displacement */ + outer_displacement = cpuGetNextWordSignExt(); + return memoryReadLong(base_reg_value + base_displacement + index_value) + outer_displacement; + case 3: /* Indirect preindexed with long outer displacement */ + outer_displacement = cpuGetNextLong(); + return memoryReadLong(base_reg_value + base_displacement + index_value) + outer_displacement; + case 5: /* Indirect postindexed with null outer displacement, reserved for index register suppressed */ + return memoryReadLong(base_reg_value + base_displacement) + index_value; + case 6: /* Indirect postindexed with word outer displacement, reserved for index register suppressed */ + outer_displacement = cpuGetNextWordSignExt(); + return memoryReadLong(base_reg_value + base_displacement) + index_value + outer_displacement; + case 7: /* Indirect postindexed with long outer displacement, reserved for index register suppressed */ + outer_displacement = cpuGetNextLong(); + return memoryReadLong(base_reg_value + base_displacement) + index_value + outer_displacement; + } + return 0; /* Should never come here. */ +} + +/* Calculates EA for disp8(Ax,Ri.size), calls cpuEA06Ext() for 68020 extended modes. */ +ULO cpuEA06(ULO regno) +{ + ULO reg_value = cpuGetAReg(regno); + UWO ext = cpuGetNextWord(); + ULO index_value = cpuGetReg(ext >> 15, (ext >> 12) & 7); + if (!(ext & 0x0800)) + { + index_value = cpuSignExtWordToLong((UWO)index_value); + } + if (cpuGetModelMajor() >= 2) + { + index_value = index_value << ((ext >> 9) & 3); /* Scaling index value */ + if (ext & 0x0100) /* Full extension word */ + { + return cpuEA06Ext(ext, reg_value, index_value); + } + } + return reg_value + index_value + cpuSignExtByteToLong((UBY)ext); +} + +/* Calculates EA for xxxx.W */ +ULO cpuEA70(void) +{ + return cpuGetNextWordSignExt(); +} + +/* Calculates EA for xxxxxxxx.L */ +ULO cpuEA71(void) +{ + return cpuGetNextLong(); +} + +/// +/// Calculates EA for disp16(PC) +/// +/// Address +ULO cpuEA72(void) +{ + ULO pc_tmp = cpuGetPC(); + return pc_tmp + cpuGetNextWordSignExt(); +} + +/// +/// Calculates EA for disp8(PC,Ri.size). Calls cpuEA06Ext() to calculate extended 68020 modes. +/// +/// Address +ULO cpuEA73(void) +{ + ULO reg_value = cpuGetPC(); + UWO ext = cpuGetNextWord(); + ULO index_value = cpuGetReg(ext >> 15, (ext >> 12) & 0x7); + if (!(ext & 0x0800)) + { + index_value = cpuSignExtWordToLong((UWO)index_value); + } + if (cpuGetModelMajor() >= 2) + { + index_value = index_value << ((ext >> 9) & 0x3); // Scaling index value + if (ext & 0x0100) // Full extension word + { + return cpuEA06Ext(ext, reg_value, index_value); + } + } + return reg_value + index_value + cpuSignExtByteToLong((UBY)ext); +} diff --git a/cpu/CpuModule_Exceptions.c b/cpu/CpuModule_Exceptions.c new file mode 100644 index 0000000..b2d803d --- /dev/null +++ b/cpu/CpuModule_Exceptions.c @@ -0,0 +1,266 @@ +/* @(#) $Id: CpuModule_Exceptions.c,v 1.5 2012/08/12 16:51:02 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* CPU 68k exception handling functions */ +/* */ +/* Author: Petter Schau */ +/* */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ + +#include "defs.h" +#include "fellow.h" +#include "fmem.h" + +#include "CpuModule.h" +#include "CpuModule_Internal.h" + +/* Function for exiting from mid-instruction exceptions */ +static cpuMidInstructionExceptionFunc cpu_mid_instruction_exception_func; + +static void cpuCallMidInstructionExceptionFunc(void) +{ + cpu_mid_instruction_exception_func(); +} + +void cpuSetMidInstructionExceptionFunc(cpuMidInstructionExceptionFunc func) +{ + cpu_mid_instruction_exception_func = func; +} + +/* Function for notifying the emulator about a reset */ +static cpuResetExceptionFunc cpu_reset_exception_func; + +void cpuCallResetExceptionFunc(void) +{ + cpu_reset_exception_func(); +} + +void cpuSetResetExceptionFunc(cpuResetExceptionFunc func) +{ + cpu_reset_exception_func = func; +} + +static STR *cpuGetExceptionName(ULO vector_offset) +{ + char *name; + + if (vector_offset == 0x8) + name = "Exception: 2 - Access fault"; + else if (vector_offset == 0xc) + name = "Exception: 3 - Address error"; + else if (vector_offset == 0x10) + name = "Exception: 4 - Illegal Instruction"; + else if (vector_offset == 0x14) + name = "Exception: 5 - Integer division by zero"; + else if (vector_offset == 0x18) + name = "Exception: 6 - CHK, CHK2"; + else if (vector_offset == 0x1c) + name = "Exception: 7 - FTRAPcc, TRAPcc, TRAPV"; + else if (vector_offset == 0x20) + name = "Exception: 8 - Privilege Violation"; + else if (vector_offset == 0x24) + name = "Exception: 9 - Trace"; + else if (vector_offset == 0x28) + name = "Exception: 10 - A-Line"; + else if (vector_offset == 0x2c) + name = "Exception: 11 - F-Line"; + else if (vector_offset == 0x38) + name = "Exception: 14 - Format error"; + else if (vector_offset >= 0x80 && vector_offset <= 0xbc) + name = "Exception: TRAP"; + else + name = "Exception: Unknown"; + + return name; +} + +/*=============================================== + Sets up an exception + ===============================================*/ + +void cpuThrowException(ULO vector_offset, ULO pc, BOOLE executejmp) +{ + ULO vector_address; + +#ifdef CPU_INSTRUCTION_LOGGING + cpuCallExceptionLoggingFunc(cpuGetExceptionName(vector_offset), cpuGetOriginalPC(), cpuGetCurrentOpcode()); +#endif + + cpuActivateSSP(); + cpuStackFrameGenerate((UWO) vector_offset, pc); + + // read a memory position + vector_address = memoryReadLong(cpuGetVbr() + vector_offset); + if (cpuGetModelMajor() < 2 && vector_address & 0x1 && vector_offset == 0xc) + { + // Avoid endless loop that will crash the emulator. + // The (odd) address error exception vector contained an odd address. + cpuCallResetExceptionFunc(); + cpuHardReset(); + cpuSetInstructionTime(132); + } + else + { + // set supervisor modus + cpuSetSR(cpuGetSR() | 0x2000); + cpuSetSR(cpuGetSR() & 0x3fff); + + // restart cpu, if needed + cpuSetStop(FALSE); + + cpuInitializeFromNewPC(vector_address); + cpuSetInstructionTime(40); + } + + // If the exception happened mid-instruction... + if (executejmp) + { + cpuCallMidInstructionExceptionFunc(); // Supposed to be doing setjmp/longjmp back to machine emulator code + } +} + +void cpuThrowPrivilegeViolationException(void) +{ + // The saved pc points to the instruction causing the violation + // (And the kickstart excpects pc in the stack frame to be the opcode PC.) + cpuThrowException(0x20, cpuGetOriginalPC(), FALSE); +} + +void cpuThrowIllegalInstructionException(BOOLE executejmp) +{ + // The saved pc points to the illegal instruction + cpuThrowException(0x10, cpuGetOriginalPC(), executejmp); +} + +void cpuThrowALineException(void) +{ + // The saved pc points to the a-line instruction + cpuThrowException(0x28, cpuGetOriginalPC(), FALSE); +} + +void cpuThrowFLineException(void) +{ + // The saved pc points to the f-line instruction + cpuThrowException(0x2c, cpuGetOriginalPC(), FALSE); +} + +void cpuThrowTrapVException(void) +{ + // The saved pc points to the next instruction, which is now in pc + cpuThrowException(0x1c, cpuGetPC(), FALSE); +} + +void cpuThrowDivisionByZeroException(BOOLE executejmp) +{ + // The saved pc points to the next instruction, which is now in pc + cpuThrowException(0x14, cpuGetPC(), executejmp); +} + +void cpuThrowTrapException(ULO vector_no) +{ + // The saved pc points to the next instruction, which is now in pc + cpuThrowException(0x80 + vector_no*4, cpuGetPC(), FALSE); +} + +void cpuThrowChkException(void) +{ + // The saved pc points to the next instruction, which is now in pc + cpuThrowException(0x18, cpuGetPC(), FALSE); +} + +void cpuThrowTraceException(void) +{ + // The saved pc points to the next instruction, which is now in pc + cpuThrowException(0x24, cpuGetPC(), FALSE); +} + +void cpuThrowAddressErrorException(void) +{ + cpuThrowException(0xc, cpuGetPC(), TRUE); +} + +/*=================*/ +/* Reset exception */ +/*=================*/ + +static void cpuThrowResetException000(void) +{ + cpuSetSR(cpuGetSR() & 0x271f); /* T = 0 */ + cpuSetSR(cpuGetSR() | 0x2700); /* S = 1, ilvl = 7 */ + cpuSetVbr(0); + cpuSetSspDirect(cpuGetInitialSP()); /* ssp = fake vector 0 */ + cpuInitializeFromNewPC(cpuGetInitialPC()); /* pc = fake vector 1 */ +} + +static void cpuThrowResetException010(void) +{ + cpuSetSR(cpuGetSR() & 0x271f); /* T = 0 */ + cpuSetSR(cpuGetSR() | 0x2700); /* S = 1, ilvl = 7 */ + cpuSetVbr(0); + cpuSetSspDirect(cpuGetInitialSP()); /* ssp = fake vector 0 */ + cpuInitializeFromNewPC(cpuGetInitialPC()); /* pc = fake vector 1 */ +} + +static void cpuThrowResetException020(void) +{ + cpuSetSR(cpuGetSR() & 0x271f); /* T1T0 = 0, M = 0 */ + cpuSetSR(cpuGetSR() | 0x2700); /* S = 1, ilvl = 7 */ + cpuSetVbr(0); + cpuSetCacr(0); /* E = 0, F = 0 */ + cpuSetCaar(0); + /* Invalidate cache, we don't have one */ + cpuSetSspDirect(cpuGetInitialSP()); /* ssp = fake vector 0 */ + cpuInitializeFromNewPC(cpuGetInitialPC()); /* pc = fake vector 1 */ +} + +static void cpuThrowResetException030(void) +{ + cpuSetSR(cpuGetSR() & 0x271f); /* T1T0 = 0, M = 0 */ + cpuSetSR(cpuGetSR() | 0x2700); /* S = 1, ilvl = 7 */ + cpuSetVbr(0); + cpuSetCacr(0); /* E = 0, F = 0 */ + cpuSetCaar(0); + /* Invalidate cache, we don't have one */ + cpuSetSspDirect(cpuGetInitialSP()); /* ssp = fake vector 0 */ + cpuInitializeFromNewPC(cpuGetInitialPC()); /* pc = fake vector 1 */ +} + +/*============================*/ +/* Performs a Reset exception */ +/*============================*/ + +void cpuThrowResetException(void) +{ + cpuSetStop(FALSE); + switch (cpuGetModelMajor()) + { + case 0: + cpuThrowResetException000(); + break; + case 1: + cpuThrowResetException010(); + break; + case 2: + cpuThrowResetException020(); + break; + case 3: + cpuThrowResetException030(); + break; + } +} diff --git a/cpu/CpuModule_Flags.c b/cpu/CpuModule_Flags.c new file mode 100644 index 0000000..f1859e2 --- /dev/null +++ b/cpu/CpuModule_Flags.c @@ -0,0 +1,578 @@ +/* @(#) $Id: CpuModule_Flags.c,v 1.3 2011/07/18 17:22:55 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* 68000 flag and condition code handling */ +/* */ +/* Author: Petter Schau */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ +#include "defs.h" +#include "fellow.h" +#include "CpuModule.h" +#include "CpuModule_Internal.h" + + +/// Sets the Z flag for bit operations +void cpuSetZFlagBitOpsB(UBY res) +{ + ULO flags = cpu_sr & 0xfffb; + if (res == 0) flags |= 4; + cpu_sr = flags; +} + +/// Sets the Z flag for bit operations +void cpuSetZFlagBitOpsL(ULO res) +{ + ULO flags = cpu_sr & 0xfffb; + if (res == 0) flags |= 4; + cpu_sr = flags; +} + +// rm,dm,sm +ULO cpu_xnvc_flag_add_table[2][2][2] = { 0,0x11,0x11,0x13,0xa,8,8,0x19}; + +/// +/// Calculate XNVC flags of an add operation. +/// +/// The MSB of the result. +/// The MSB of the destination source. +/// The MSB of the source. +static ULO cpuMakeFlagXNVCAdd(BOOLE rm, BOOLE dm, BOOLE sm) +{ + return cpu_xnvc_flag_add_table[rm][dm][sm]; +} + +// rm,dm,sm +ULO cpu_nvc_flag_add_table[2][2][2] = { 0,1,1,3,0xa,8,8,9}; + +/// +/// Calculate NVC flags of an add operation for instructions not setting X. +/// +/// The MSB of the result. +/// The MSB of the destination source. +/// The MSB of the source. +static ULO cpuMakeFlagNVCAdd(BOOLE rm, BOOLE dm, BOOLE sm) +{ + return cpu_nvc_flag_add_table[rm][dm][sm]; +} + +// rm,dm,sm +ULO cpu_xnvc_flag_sub_table[2][2][2] = { 0,0x11,2,0,0x19,0x1b,8,0x19}; + +/// +/// Calculate XNVC flags of a sub operation. +/// +/// The MSB of the result. +/// The MSB of the destination source. +/// The MSB of the source. +static ULO cpuMakeFlagXNVCSub(BOOLE rm, BOOLE dm, BOOLE sm) +{ + return cpu_xnvc_flag_sub_table[rm][dm][sm]; +} + +// rm,dm,sm +ULO cpu_nvc_flag_sub_table[2][2][2] = { 0,1,2,0,9,0xb,8,9}; + +/// +/// Calculate NVC flags of a sub operation for instructions not setting X. +/// +/// The MSB of the result. +/// The MSB of the destination source. +/// The MSB of the source. +static ULO cpuMakeFlagNVCSub(BOOLE rm, BOOLE dm, BOOLE sm) +{ + return cpu_nvc_flag_sub_table[rm][dm][sm]; +} + +/// +/// Set the X and C flags to the value f. +/// +/// The new state of the flags. +void cpuSetFlagXC(BOOLE f) +{ + cpu_sr = (cpu_sr & 0xffee) | ((f) ? 0x11 : 0); +} + +/// +/// Set the C flag to the value f. +/// +/// The new state of the flag. +void cpuSetFlagC(BOOLE f) +{ + cpu_sr = (cpu_sr & 0xfffe) | ((f) ? 1 : 0); +} + +/// +/// Set the V flag. +/// +/// The new state of the flag. +void cpuSetFlagV(BOOLE f) +{ + cpu_sr = (cpu_sr & 0xfffd) | ((f) ? 2 : 0); +} + +/// +/// Clear the V flag. +/// +static void cpuClearFlagV(void) +{ + cpu_sr = cpu_sr & 0xfffd; +} + +/// +/// Get the V flag. +/// +BOOLE cpuGetFlagV(void) +{ + return cpu_sr & 0x2; +} + +/// +/// Set the N flag. +/// +/// The new state of the flag. +void cpuSetFlagN(BOOLE f) +{ + cpu_sr = (cpu_sr & 0xfff7) | ((f) ? 8 : 0); +} + +/// +/// Set the Z flag. +/// +/// The new state of the flag. +void cpuSetFlagZ(BOOLE f) +{ + cpu_sr = (cpu_sr & 0xfffb) | ((f) ? 4 : 0); +} + +/// +/// Clear the Z flag. +/// +static void cpuClearFlagZ(void) +{ + cpu_sr = cpu_sr & 0xfffb; +} + +/// +/// Get the Z flag. +/// +static BOOLE cpuGetFlagZ(void) +{ + return cpu_sr & 0x4; +} + +/// +/// Get the X flag. +/// +BOOLE cpuGetFlagX(void) +{ + return cpu_sr & 0x10; +} + +/// +/// Set the flags. +/// +void cpuSetFlags0100(void) +{ + cpu_sr = (cpu_sr & 0xfff0) | 4; +} + +/// +/// Clear V and C. +/// +static void cpuClearFlagsVC(void) +{ + cpu_sr = cpu_sr & 0xfffc; +} + +UWO cpuGetZFlagB(UBY res) {return (UWO)((res) ? 0 : 4);} +UWO cpuGetZFlagW(UWO res) {return (UWO)((res) ? 0 : 4);} +UWO cpuGetZFlagL(ULO res) {return (UWO)((res) ? 0 : 4);} + +UWO cpuGetNFlagB(UBY res) {return (UWO)((res & 0x80) >> 4);} +UWO cpuGetNFlagW(UWO res) {return (UWO)((res & 0x8000) >> 12);} +UWO cpuGetNFlagL(ULO res) {return (UWO)((res & 0x80000000) >> 28);} + +/// +/// Set the flags NZVC. +/// +/// The Z flag. +/// The N flag. +/// The V flag. +/// The C flag. +void cpuSetFlagsNZVC(BOOLE z, BOOLE n, BOOLE v, BOOLE c) +{ + ULO flags = cpu_sr & 0xfff0; + if (n) flags |= 8; + else if (z) flags |= 4; + if (v) flags |= 2; + if (c) flags |= 1; + cpu_sr = flags; +} + +/// +/// Set the flags VC. +/// +/// The V flag. +/// The C flag. +void cpuSetFlagsVC(BOOLE v, BOOLE c) +{ + ULO flags = cpu_sr & 0xfffc; + if (v) flags |= 2; + if (c) flags |= 1; + cpu_sr = flags; +} + +/// +/// Set the flags (all) of an add operation. +/// +/// The Z flag. +/// The MSB of the result. +/// The MSB of the destination source. +/// The MSB of the source. +void cpuSetFlagsAdd(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm) +{ + ULO flags = cpu_sr & 0xffe0; + if (z) flags |= 4; + flags |= cpuMakeFlagXNVCAdd(rm, dm, sm); + cpu_sr = flags; +} + +/// +/// Set the flags (all) of a sub operation. +/// +/// The Z flag. +/// The MSB of the result. +/// The MSB of the destination source. +/// The MSB of the source. +void cpuSetFlagsSub(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm) +{ + ULO flags = cpu_sr & 0xffe0; + if (z) flags |= 4; + flags |= cpuMakeFlagXNVCSub(rm, dm, sm); + cpu_sr = flags; +} + +/// +/// Set the flags (all) of an addx operation. +/// +/// The Z flag. +/// The MSB of the result. +/// The MSB of the destination source. +/// The MSB of the source. +void cpuSetFlagsAddX(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm) +{ + ULO flags = cpu_sr & ((z) ? 0xffe4 : 0xffe0); // Clear z if result is non-zero + flags |= cpuMakeFlagXNVCAdd(rm, dm, sm); + cpu_sr = flags; +} + +/// +/// Set the flags (all) of a subx operation. +/// +/// The Z flag. +/// The MSB of the result. +/// The MSB of the destination source. +/// The MSB of the source. +void cpuSetFlagsSubX(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm) +{ + ULO flags = cpu_sr & ((z) ? 0xffe4 : 0xffe0); // Clear z if result is non-zero + flags |= cpuMakeFlagXNVCSub(rm, dm, sm); + cpu_sr = flags; +} + +/// +/// Set the flags (all) of a neg operation. +/// +/// The Z flag. +/// The MSB of the result. +/// The MSB of the destination source. +void cpuSetFlagsNeg(BOOLE z, BOOLE rm, BOOLE dm) +{ + ULO flags = cpu_sr & 0xffe0; + if (z) flags |= 4; + else + { + flags |= 0x11; // set XC if result is non-zero + if (rm) + { + flags |= 8; + if (dm) flags |= 2; // V + } + } + cpu_sr = flags; +} + +/// +/// Set the flags (all) of a negx operation. +/// +/// The Z flag. +/// The MSB of the result. +/// The MSB of the destination source. +void cpuSetFlagsNegx(BOOLE z, BOOLE rm, BOOLE dm) +{ + ULO flags = cpu_sr & ((z) ? 0xffe4 : 0xffe0); // Clear z if result is non-zero + if (dm || rm) + { + flags |= 0x11; // XC + if (rm) + { + flags |= 8; + if (dm) flags |= 2; // V + } + } + cpu_sr = flags; +} + +/// +/// Set the flags (all) of a cmp operation. (Same as sub, but no X.) +/// +/// The Z flag. +/// The MSB of the result. +/// The MSB of the destination source. +/// The MSB of the source. +void cpuSetFlagsCmp(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm) +{ + ULO flags = cpu_sr & 0xfff0; + if (z) flags |= 4; + flags |= cpuMakeFlagNVCSub(rm, dm, sm); + cpu_sr = flags; +} + +/// +/// Set the flags of a 0 shift count operation. +/// +/// The Z flag. +/// The MSB of the result. +void cpuSetFlagsShiftZero(BOOLE z, BOOLE rm) +{ + ULO flags = cpu_sr & 0xfff0; // Always clearing the VC flag + if (rm) flags |= 8; + else if (z) flags |= 4; + cpu_sr = flags; +} + +/// +/// Set the flags of a shift operation. +/// +/// The Z flag. +/// The MSB of the result. +/// The carry of the result. +/// The overflow of the result. +void cpuSetFlagsShift(BOOLE z, BOOLE rm, BOOLE c, BOOLE v) +{ + ULO flags = cpu_sr & 0xffe0; + if (rm) flags |= 8; + else if (z) flags |= 4; + if (v) flags |= 2; + if (c) flags |= 0x11; + cpu_sr = flags; +} + +/// +/// Set the flags of a rotate operation. +/// +/// The Z flag. +/// The MSB of the result. +/// The carry of the result. +void cpuSetFlagsRotate(BOOLE z, BOOLE rm, BOOLE c) +{ + ULO flags = cpu_sr & 0xfff0; // Always clearing the V flag + + if (rm) flags |= 8; + else if (z) flags |= 4; + if (c) flags |= 1; + + cpu_sr = flags; +} + +/// +/// Set the flags of a rotate with x operation. +/// +/// The Z flag. +/// The MSB of the result. +/// The extend bit and carry of the result. +void cpuSetFlagsRotateX(UWO z, UWO rm, UWO x) +{ + cpu_sr = (cpu_sr & 0xffe0) | z | rm | x; +} + +/// +/// Set the flags (ZN00). +/// +void cpuSetFlagsNZ00NewB(UBY res) +{ + ULO flag = cpu_sr & 0xfff0; + if (res & 0x80) flag |= 0x8; + else if (res == 0) flag |= 0x4; + cpu_sr = flag; +} + +/// +/// Set the flags (ZN00). +/// +void cpuSetFlagsNZ00NewW(UWO res) +{ + ULO flag = cpu_sr & 0xfff0; + if (res & 0x8000) flag |= 0x8; + else if (res == 0) flag |= 0x4; + cpu_sr = flag; +} + +/// +/// Set the flags (ZN00). +/// +void cpuSetFlagsNZ00NewL(ULO res) +{ + ULO flag = cpu_sr & 0xfff0; + if (res & 0x80000000) flag |= 0x8; + else if (res == 0) flag |= 0x4; + cpu_sr = flag; +} + +/// +/// Set the flags (ZN00). +/// +void cpuSetFlagsNZ00New64(LLO res) +{ + ULO flag = cpu_sr & 0xfff0; + if (res < 0) flag |= 0x8; + else if (res == 0) flag |= 0x4; + cpu_sr = flag; +} + +/// +/// Set the 4 flags absolute. +/// +/// flags +void cpuSetFlagsAbs(UWO f) +{ + cpu_sr = (cpu_sr & 0xfff0) | f; +} + +/// +/// Calculates the values for the condition codes. +/// +/// TRUE or FALSE +BOOLE cpuCalculateConditionCode0(void) +{ + return TRUE; +} + +BOOLE cpuCalculateConditionCode1(void) +{ + return FALSE; +} + +BOOLE cpuCalculateConditionCode2(void) +{ + return !(cpu_sr & 5); // HI - !C && !Z +} + +BOOLE cpuCalculateConditionCode3(void) +{ + return cpu_sr & 5; // LS - C || Z +} + +BOOLE cpuCalculateConditionCode4(void) +{ + return (~cpu_sr) & 1; // CC - !C +} + +BOOLE cpuCalculateConditionCode5(void) +{ + return cpu_sr & 1; // CS - C +} + +BOOLE cpuCalculateConditionCode6(void) +{ + return (~cpu_sr) & 4; // NE - !Z +} + +BOOLE cpuCalculateConditionCode7(void) +{ + return cpu_sr & 4; // EQ - Z +} + +BOOLE cpuCalculateConditionCode8(void) +{ + return (~cpu_sr) & 2; // VC - !V +} + +BOOLE cpuCalculateConditionCode9(void) +{ + return cpu_sr & 2; // VS - V +} + +BOOLE cpuCalculateConditionCode10(void) +{ + return (~cpu_sr) & 8; // PL - !N +} + +BOOLE cpuCalculateConditionCode11(void) +{ + return cpu_sr & 8; // MI - N +} + +BOOLE cpuCalculateConditionCode12(void) +{ + ULO tmp = cpu_sr & 0xa; + return (tmp == 0xa) || (tmp == 0); // GE - (N && V) || (!N && !V) +} + +BOOLE cpuCalculateConditionCode13(void) +{ + ULO tmp = cpu_sr & 0xa; + return (tmp == 0x8) || (tmp == 0x2); // LT - (N && !V) || (!N && V) +} + +BOOLE cpuCalculateConditionCode14(void) +{ + ULO tmp = cpu_sr & 0xa; + return (!(cpu_sr & 0x4)) && ((tmp == 0xa) || (tmp == 0)); // GT - (N && V && !Z) || (!N && !V && !Z) +} + +BOOLE cpuCalculateConditionCode15(void) +{ + ULO tmp = cpu_sr & 0xa; + return (cpu_sr & 0x4) || (tmp == 0x8) || (tmp == 2);// LE - Z || (N && !V) || (!N && V) +} + +BOOLE cpuCalculateConditionCode(ULO cc) +{ + switch (cc & 0xf) + { + case 0: return cpuCalculateConditionCode0(); + case 1: return cpuCalculateConditionCode1(); + case 2: return cpuCalculateConditionCode2(); + case 3: return cpuCalculateConditionCode3(); + case 4: return cpuCalculateConditionCode4(); + case 5: return cpuCalculateConditionCode5(); + case 6: return cpuCalculateConditionCode6(); + case 7: return cpuCalculateConditionCode7(); + case 8: return cpuCalculateConditionCode8(); + case 9: return cpuCalculateConditionCode9(); + case 10: return cpuCalculateConditionCode10(); + case 11: return cpuCalculateConditionCode11(); + case 12: return cpuCalculateConditionCode12(); + case 13: return cpuCalculateConditionCode13(); + case 14: return cpuCalculateConditionCode14(); + case 15: return cpuCalculateConditionCode15(); + } + return FALSE; +} diff --git a/cpu/CpuModule_Instructions.c b/cpu/CpuModule_Instructions.c new file mode 100644 index 0000000..e276c32 --- /dev/null +++ b/cpu/CpuModule_Instructions.c @@ -0,0 +1,3735 @@ +/* @(#) $Id: CpuModule_Instructions.c,v 1.12 2013/01/08 18:55:48 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* CPU 68k functions */ +/* */ +/* Author: Petter Schau */ +/* */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ + +#include "defs.h" +#include "fellow.h" +#include "fmem.h" +#include "CpuModule.h" +#include "CpuModule_Internal.h" + +#ifdef UAE_FILESYS +#include "uae2fell.h" +#include "autoconf.h" +#endif + +/*============================================================================*/ +/* profiling help functions */ +/*============================================================================*/ + +#ifndef X64 +static __inline void cpuTscBefore(LLO* a) +{ + LLO local_a = *a; + __asm + { + push eax + push edx + push ecx + mov ecx,10h + rdtsc + pop ecx + mov dword ptr [local_a], eax + mov dword ptr [local_a + 4], edx + pop edx + pop eax + } + *a = local_a; +} + +static __inline void cpuTscAfter(LLO* a, LLO* b, ULO* c) +{ + LLO local_a = *a; + LLO local_b = *b; + ULO local_c = *c; + + __asm + { + push eax + push edx + push ecx + mov ecx, 10h + rdtsc + pop ecx + sub eax, dword ptr [local_a] + sbb edx, dword ptr [local_a + 4] + add dword ptr [local_b], eax + adc dword ptr [local_b + 4], edx + inc dword ptr [local_c] + pop edx + pop eax + } + *a = local_a; + *b = local_b; + *c = local_c; +} +#endif + +/* Maintains the integrity of the super/user state */ + +void cpuUpdateSr(ULO new_sr) { + BOOLE supermode_was_set = cpuGetFlagSupervisor(); + BOOLE master_was_set = (cpuGetModelMajor() >= 2) && cpuGetFlagMaster(); + + BOOLE supermode_is_set = !!(new_sr & 0x2000); + BOOLE master_is_set = (cpuGetModelMajor() >= 2) && !!(new_sr & 0x1000); + + ULO runlevel_old = (cpuGetSR() >> 8) & 7; + ULO runlevel_new = (new_sr >> 8) & 7; + + if (!supermode_was_set) + cpuSetUspDirect(cpuGetAReg(7)); + else if (master_was_set) + cpuSetMspDirect(cpuGetAReg(7)); + else + cpuSetSspDirect(cpuGetAReg(7)); + + if (!supermode_is_set) + cpuSetAReg(7, cpuGetUspDirect()); + else if (master_is_set) + cpuSetAReg(7, cpuGetMspDirect()); + else + cpuSetAReg(7, cpuGetSspDirect()); + + cpuSetSR(new_sr); + + if (runlevel_old != runlevel_new) { + cpuCallCheckPendingInterruptsFunc(); + } +} + +static void cpuIllegal(void) { + UWO opcode = memoryReadWord(cpuGetPC() - 2); + if ((opcode & 0xf000) == 0xf000) { + cpuThrowFLineException(); + } else if ((opcode & 0xa000) == 0xa000) { +#ifdef UAE_FILESYS + if ((cpuGetPC() & 0xff0000) == 0xf00000) + { + call_calltrap(opcode & 0xfff); + cpuInitializeFromNewPC(cpuGetPC()); + cpuSetInstructionTime(512); + } + else +#endif + { + cpuThrowALineException(); + } + } + else + { + cpuThrowIllegalInstructionException(FALSE); + } +} + +/// +/// Illegal instruction handler. +/// +static void cpuIllegalInstruction(ULO *opcode_data) +{ + cpuIllegal(); +} + +/// +/// BKPT +/// +static void cpuBkpt(ULO vector) +{ + cpuIllegal(); +} + +/// +/// Adds bytes src1 to src2. Sets all flags. +/// +/// The result +static UBY cpuAddB(UBY src2, UBY src1) +{ + UBY res = src2 + src1; + cpuSetFlagsAdd(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(src2), cpuMsbB(src1)); + return res; +} + +/// +/// Adds words src1 to src2. Sets all flags. +/// +/// The result +static UWO cpuAddW(UWO src2, UWO src1) +{ + UWO res = src2 + src1; + cpuSetFlagsAdd(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(src2), cpuMsbW(src1)); + return res; +} + +/// +/// Adds dwords src1 to src2. Sets all flags. +/// +/// The result +static ULO cpuAddL(ULO src2, ULO src1) +{ + ULO res = src2 + src1; + cpuSetFlagsAdd(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(src2), cpuMsbL(src1)); + return res; +} + +/// +/// Adds src1 to src2 (For address registers). No flags. +/// +/// The result +static ULO cpuAddaW(ULO src2, ULO src1) +{ + return src2 + src1; +} + +/// +/// Adds src1 to src2 (For address registers). No flags. +/// +/// The result +static ULO cpuAddaL(ULO src2, ULO src1) +{ + return src2 + src1; +} + +/// +/// Subtracts src1 from src2. Sets all flags. +/// +/// The result +static UBY cpuSubB(UBY src2, UBY src1) +{ + UBY res = src2 - src1; + cpuSetFlagsSub(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(src2), cpuMsbB(src1)); + return res; +} + +/// +/// Subtracts src1 from src2. Sets all flags. +/// +/// The result +static UWO cpuSubW(UWO src2, UWO src1) +{ + UWO res = src2 - src1; + cpuSetFlagsSub(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(src2), cpuMsbW(src1)); + return res; +} + +/// +/// Subtracts src1 from src2. Sets all flags. +/// +/// The result +static ULO cpuSubL(ULO src2, ULO src1) +{ + ULO res = src2 - src1; + cpuSetFlagsSub(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(src2), cpuMsbL(src1)); + return res; +} + +/// +/// Subtracts src1 from src2 (For address registers). No flags. +/// +/// The result +static ULO cpuSubaW(ULO src2, ULO src1) +{ + return src2 - src1; +} + +/// +/// Subtracts src1 from src2 (For address registers). No flags. +/// +/// The result +static ULO cpuSubaL(ULO src2, ULO src1) +{ + return src2 - src1; +} + +/// +/// Subtracts src1 from src2. Sets all flags. +/// +static void cpuCmpB(UBY src2, UBY src1) +{ + UBY res = src2 - src1; + cpuSetFlagsCmp(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(src2), cpuMsbB(src1)); +} + +/// +/// Subtracts src1 from src2. Sets all flags. +/// +static void cpuCmpW(UWO src2, UWO src1) +{ + UWO res = src2 - src1; + cpuSetFlagsCmp(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(src2), cpuMsbW(src1)); +} + +/// +/// Subtracts src1 from src2. Sets all flags. +/// +static void cpuCmpL(ULO src2, ULO src1) +{ + ULO res = src2 - src1; + cpuSetFlagsCmp(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(src2), cpuMsbL(src1)); +} + +/// +/// Ands src1 to src2. Sets NZ00 flags. +/// +/// The result +static UBY cpuAndB(UBY src2, UBY src1) +{ + UBY res = src2 & src1; + cpuSetFlagsNZ00NewB(res); + return res; +} + +/// +/// Ands src1 to src2. Sets NZ00 flags. +/// +/// The result +static UWO cpuAndW(UWO src2, UWO src1) +{ + UWO res = src2 & src1; + cpuSetFlagsNZ00NewW(res); + return res; +} + +/// +/// Ands src1 to src2. Sets NZ00 flags. +/// +/// The result +static ULO cpuAndL(ULO src2, ULO src1) +{ + ULO res = src2 & src1; + cpuSetFlagsNZ00NewL(res); + return res; +} + +/// +/// Eors src1 to src2. Sets NZ00 flags. +/// +/// The result +static UBY cpuEorB(UBY src2, UBY src1) +{ + UBY res = src2 ^ src1; + cpuSetFlagsNZ00NewB(res); + return res; +} + +/// +/// Eors src1 to src2. Sets NZ00 flags. +/// +/// The result +static UWO cpuEorW(UWO src2, UWO src1) +{ + UWO res = src2 ^ src1; + cpuSetFlagsNZ00NewW(res); + return res; +} + +/// +/// Eors src1 to src2. Sets NZ00 flags. +/// +/// The result +static ULO cpuEorL(ULO src2, ULO src1) +{ + ULO res = src2 ^ src1; + cpuSetFlagsNZ00NewL(res); + return res; +} + +/// +/// Ors src1 to src2. Sets NZ00 flags. +/// +/// The result +static UBY cpuOrB(UBY src2, UBY src1) +{ + UBY res = src2 | src1; + cpuSetFlagsNZ00NewB(res); + return res; +} + +/// +/// Ors src1 to src2. Sets NZ00 flags. +/// +/// The result +static UWO cpuOrW(UWO src2, UWO src1) +{ + UWO res = src2 | src1; + cpuSetFlagsNZ00NewW(res); + return res; +} + +/// +/// Ors src1 to src2. Sets NZ00 flags. +/// +/// The result +static ULO cpuOrL(ULO src2, ULO src1) +{ + ULO res = src2 | src1; + cpuSetFlagsNZ00NewL(res); + return res; +} + +/// +/// Changes bit in src. Sets Z flag. +/// +/// The result +static UBY cpuBchgB(UBY src, UBY bit) +{ + UBY bit_mask = 1 << (bit & 7); + cpuSetZFlagBitOpsB(src & bit_mask); + return src ^ bit_mask; +} + +/// +/// Changes bit in src. Sets Z flag. +/// +/// The result +static ULO cpuBchgL(ULO src, ULO bit) +{ + ULO bit_mask = 1 << (bit & 31); + cpuSetZFlagBitOpsL(src & bit_mask); + return src ^ bit_mask; +} + +/// +/// Clears bit in src. Sets Z flag. +/// +/// The result +static UBY cpuBclrB(UBY src, UBY bit) +{ + UBY bit_mask = 1 << (bit & 7); + cpuSetZFlagBitOpsB(src & bit_mask); + return src & ~bit_mask; +} + +/// +/// Clears bit in src. Sets Z flag. +/// +/// The result +static ULO cpuBclrL(ULO src, ULO bit) +{ + ULO bit_mask = 1 << (bit & 31); + cpuSetZFlagBitOpsL(src & bit_mask); + return src & ~bit_mask; +} + +/// +/// Sets bit in src. Sets Z flag. +/// +/// The result +static UBY cpuBsetB(UBY src, UBY bit) +{ + UBY bit_mask = 1 << (bit & 7); + cpuSetZFlagBitOpsB(src & bit_mask); + return src | bit_mask; +} + +/// +/// Sets bit in src. Sets Z flag. +/// +/// The result +static ULO cpuBsetL(ULO src, ULO bit) +{ + ULO bit_mask = 1 << (bit & 31); + cpuSetZFlagBitOpsL(src & bit_mask); + return src | bit_mask; +} + +/// +/// Tests bit in src. Sets Z flag. +/// +static void cpuBtstB(UBY src, UBY bit) +{ + UBY bit_mask = 1 << (bit & 7); + cpuSetZFlagBitOpsB(src & bit_mask); +} + +/// +/// Tests bit in src. Sets Z flag. +/// +static void cpuBtstL(ULO src, ULO bit) +{ + ULO bit_mask = 1 << (bit & 31); + cpuSetZFlagBitOpsL(src & bit_mask); +} + +/// +/// Set flags for clr operation. X0100. +/// +static void cpuClr() +{ + cpuSetFlags0100(); +} + +/// +/// Neg src1. Sets sub flags. +/// +/// The result +static UBY cpuNegB(UBY src1) +{ + UBY res = (UBY)-(BYT)src1; + cpuSetFlagsNeg(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(src1)); + return res; +} + +/// +/// Neg src1. Sets sub flags. +/// +/// The result +static UWO cpuNegW(UWO src1) +{ + UWO res = (UWO)-(WOR)src1; + cpuSetFlagsNeg(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(src1)); + return res; +} + +/// +/// Neg src1. Sets sub flags. +/// +/// The result +static ULO cpuNegL(ULO src1) +{ + ULO res = (ULO)-(LON)src1; + cpuSetFlagsNeg(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(src1)); + return res; +} + +/// +/// Negx src1. +/// +/// The result +static UBY cpuNegxB(UBY src1) +{ + BYT x = (cpuGetFlagX()) ? 1 : 0; + UBY res = (UBY)-(BYT)src1 - x; + cpuSetFlagsNegx(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(src1)); + return res; +} + +/// +/// Negx src1. +/// +/// The result +static UWO cpuNegxW(UWO src1) +{ + WOR x = (cpuGetFlagX()) ? 1 : 0; + UWO res = (UWO)-(WOR)src1 - x; + cpuSetFlagsNegx(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(src1)); + return res; +} + +/// +/// Negx src1. +/// +/// The result +static ULO cpuNegxL(ULO src1) +{ + LON x = (cpuGetFlagX()) ? 1 : 0; + ULO res = (ULO)-(LON)src1 - x; + cpuSetFlagsNegx(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(src1)); + return res; +} + +/// +/// Not src1. +/// +/// The result +static UBY cpuNotB(UBY src1) +{ + UBY res = ~src1; + cpuSetFlagsNZ00NewB(res); + return res; +} + +/// +/// Not src1. +/// +/// The result +static UWO cpuNotW(UWO src1) +{ + UWO res = ~src1; + cpuSetFlagsNZ00NewW(res); + return res; +} + +/// +/// Not src. +/// +/// The result +static ULO cpuNotL(ULO src) +{ + ULO res = ~src; + cpuSetFlagsNZ00NewL(res); + return res; +} + +/// +/// Tas src. +/// +/// The result +static UBY cpuTas(UBY src) +{ + cpuSetFlagsNZ00NewB(src); + return src | 0x80; +} + +/// +/// Tst res. +/// +static void cpuTestB(UBY res) +{ + cpuSetFlagsNZ00NewB(res); +} + +/// +/// Tst res. +/// +static void cpuTestW(UWO res) +{ + cpuSetFlagsNZ00NewW(res); +} + +/// +/// Tst res. +/// +static void cpuTestL(ULO res) +{ + cpuSetFlagsNZ00NewL(res); +} + +/// +/// PEA ea. +/// +static void cpuPeaL(ULO ea) +{ + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(ea, cpuGetAReg(7)); +} + +/// +/// JMP ea. +/// +static void cpuJmp(ULO ea) +{ + cpuInitializeFromNewPC(ea); +} + +/// +/// JSR ea. +/// +static void cpuJsr(ULO ea) +{ + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(cpuGetPC(), cpuGetAReg(7)); + cpuInitializeFromNewPC(ea); +} + +/// +/// Move res +/// +/// The result +static void cpuMoveB(UBY res) +{ + cpuSetFlagsNZ00NewB(res); +} + +/// +/// Move res +/// +/// The result +static void cpuMoveW(UWO res) +{ + cpuSetFlagsNZ00NewW(res); +} + +/// +/// Move res +/// +/// The result +static void cpuMoveL(ULO res) +{ + cpuSetFlagsNZ00NewL(res); +} + +/// +/// Bra byte offset. +/// +static void cpuBraB(ULO offset) +{ + cpuInitializeFromNewPC(cpuGetPC() + offset); + cpuSetInstructionTime(10); +} + +/// +/// Bra word offset. +/// +static void cpuBraW() +{ + ULO tmp_pc = cpuGetPC(); + cpuInitializeFromNewPC(tmp_pc + cpuGetNextWordSignExt()); + cpuSetInstructionTime(10); +} + +/// +/// Bra long offset. +/// +static void cpuBraL() +{ + if (cpuGetModelMajor() < 2) cpuBraB(0xffffffff); + else + { + ULO tmp_pc = cpuGetPC(); + cpuInitializeFromNewPC(tmp_pc + cpuGetNextLong()); + cpuSetInstructionTime(4); + } +} + +/// +/// Bsr byte offset. +/// +static void cpuBsrB(ULO offset) +{ + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(cpuGetPC(), cpuGetAReg(7)); + cpuInitializeFromNewPC(cpuGetPC() + offset); + cpuSetInstructionTime(18); +} + +/// +/// Bsr word offset. +/// +static void cpuBsrW() +{ + ULO tmp_pc = cpuGetPC(); + ULO offset = cpuGetNextWordSignExt(); + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(cpuGetPC(), cpuGetAReg(7)); + cpuInitializeFromNewPC(tmp_pc + offset); + cpuSetInstructionTime(18); +} + +/// +/// Bsr long offset. (020+) +/// +static void cpuBsrL() +{ + if (cpuGetModelMajor() < 2) cpuBsrB(0xffffffff); + else + { + ULO tmp_pc = cpuGetPC(); + ULO offset = cpuGetNextLong(); + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(cpuGetPC(), cpuGetAReg(7)); + cpuInitializeFromNewPC(tmp_pc + offset); + cpuSetInstructionTime(4); + } +} + +/// +/// Bcc byte offset. +/// +static void cpuBccB(BOOLE cc, ULO offset) +{ + if (cc) + { + cpuInitializeFromNewPC(cpuGetPC() + offset); + cpuSetInstructionTime(10); + } + else + { + cpuSetInstructionTime(8); + } +} + +/// +/// Bcc word offset. +/// +static void cpuBccW(BOOLE cc) +{ + if (cc) + { + ULO tmp_pc = cpuGetPC(); + cpuInitializeFromNewPC(tmp_pc + cpuGetNextWordSignExt()); + cpuSetInstructionTime(10); + } + else + { + cpuSkipNextWord(); + cpuSetInstructionTime(12); + } +} + +/// +/// Bcc long offset. (020+) +/// +static void cpuBccL(BOOLE cc) +{ + if (cpuGetModelMajor() < 2) cpuBccB(cc, 0xffffffff); + else + { + if (cc) + { + ULO tmp_pc = cpuGetPC(); + cpuInitializeFromNewPC(tmp_pc + cpuGetNextLong()); + } + else + { + cpuSkipNextLong(); + } + cpuSetInstructionTime(4); + } +} + +/// +/// DBcc word offset. +/// +static void cpuDbcc(BOOLE cc, ULO reg) +{ + if (!cc) + { + WOR val = (WOR)cpuGetDRegWord(reg); + val--; + cpuSetDRegWord(reg, val); + if (val != -1) + { + ULO tmp_pc = cpuGetPC(); + cpuInitializeFromNewPC(tmp_pc + cpuGetNextWordSignExt()); + cpuSetInstructionTime(10); + } + else + { + cpuSkipNextWord(); + cpuSetInstructionTime(14); + } + } + else + { + cpuSkipNextWord(); + cpuSetInstructionTime(12); + } +} + +/// +/// And #imm, ccr +/// +static void cpuAndCcrB() +{ + UWO imm = cpuGetNextWord(); + cpuSetSR(cpuGetSR() & (0xffe0 | (imm & 0x1f))); +} + +/// +/// And #imm, sr +/// +static void cpuAndSrW() +{ + if (cpuGetFlagSupervisor()) + { + UWO imm = cpuGetNextWord(); + cpuUpdateSr(cpuGetSR() & imm); + } + else + { + cpuThrowPrivilegeViolationException(); + } +} + +/// +/// Or #imm, ccr +/// +static void cpuOrCcrB() +{ + UWO imm = cpuGetNextWord(); + cpuSetSR(cpuGetSR() | (imm & 0x1f)); +} + +/// +/// Or #imm, sr +/// +static void cpuOrSrW() +{ + if (cpuGetFlagSupervisor()) + { + UWO imm = cpuGetNextWord(); + cpuUpdateSr(cpuGetSR() | imm); + } + else + { + cpuThrowPrivilegeViolationException(); + } +} + +/// +/// Eor #imm, ccr +/// +static void cpuEorCcrB() +{ + UWO imm = cpuGetNextWord(); + cpuSetSR(cpuGetSR() ^ (imm & 0x1f)); +} + +/// +/// Eor #imm, sr +/// +static void cpuEorSrW() +{ + if (cpuGetFlagSupervisor()) + { + UWO imm = cpuGetNextWord(); + cpuUpdateSr(cpuGetSR() ^ imm); + } + else + { + cpuThrowPrivilegeViolationException(); + } +} + +/// +/// Move ea, ccr +/// +static void cpuMoveToCcr(UWO src) +{ + cpuSetSR((cpuGetSR() & 0xff00) | (src & 0x1f)); +} + +/// +/// Move , sr +/// +static void cpuMoveToSr(UWO src) +{ + if (cpuGetFlagSupervisor()) + { + cpuUpdateSr(src); + } + else + { + cpuThrowPrivilegeViolationException(); + } +} + +/// +/// Move ccr, ea +/// +static UWO cpuMoveFromCcr() +{ + return cpuGetSR() & 0x1f; +} + +/// +/// Move , sr +/// +static UWO cpuMoveFromSr() +{ + if (cpuGetModelMajor() == 0 || (cpuGetModelMajor() > 0 && cpuGetFlagSupervisor())) + { + return (UWO) cpuGetSR(); + } + else + { + cpuThrowPrivilegeViolationException(); + } + return 0; +} + +/// +/// Scc byte. +/// +static UBY cpuScc(ULO cc) +{ + return (cpuCalculateConditionCode(cc)) ? 0xff : 0; +} + +/// +/// Rts +/// +static void cpuRts() +{ + cpuInitializeFromNewPC(memoryReadLong(cpuGetAReg(7))); + cpuSetAReg(7, cpuGetAReg(7) + 4); + cpuSetInstructionTime(16); +} + +/// +/// Rtr +/// +static void cpuRtr() +{ + cpuSetSR((cpuGetSR() & 0xffe0) | (memoryReadWord(cpuGetAReg(7)) & 0x1f)); + cpuSetAReg(7, cpuGetAReg(7) + 2); + cpuInitializeFromNewPC(memoryReadLong(cpuGetAReg(7))); + cpuSetAReg(7, cpuGetAReg(7) + 4); + cpuSetInstructionTime(20); +} + +/// +/// Nop +/// +static void cpuNop() +{ + cpuSetInstructionTime(4); +} + +/// +/// Trapv +/// +static void cpuTrapv() +{ + if (cpuGetFlagV()) + { + cpuThrowTrapVException(); + return; + } + cpuSetInstructionTime(4); +} + +/// +/// Muls/u.l +/// +static void cpuMulL(ULO src1, UWO extension) +{ + ULO dl = (extension >> 12) & 7; + if (extension & 0x0800) // muls.l + { + LLO result = ((LLO)(LON) src1) * ((LLO)(LON)cpuGetDReg(dl)); + if (extension & 0x0400) // 32bx32b=64b + { + ULO dh = extension & 7; + cpuSetDReg(dh, (ULO)(result >> 32)); + cpuSetDReg(dl, (ULO)result); + cpuSetFlagsNZ00New64(result); + } + else // 32bx32b=32b + { + BOOLE o; + if (result >= 0) + o = (result & 0xffffffff00000000) != 0; + else + o = (result & 0xffffffff00000000) != 0xffffffff00000000; + cpuSetDReg(dl, (ULO)result); + cpuSetFlagsNZVC(result == 0, result < 0, o, FALSE); + } + } + else // mulu.l + { + ULL result = ((ULL) src1) * ((ULL) cpuGetDReg(dl)); + if (extension & 0x0400) // 32bx32b=64b + { + ULO dh = extension & 7; + cpuSetDReg(dh, (ULO)(result >> 32)); + cpuSetDReg(dl, (ULO)result); + cpuSetFlagsNZ00New64(result); + } + else // 32bx32b=32b + { + cpuSetDReg(dl, (ULO)result); + cpuSetFlagsNZVC(result == 0, !!(result & 0x8000000000000000), (result >> 32) != 0, FALSE); + } + } + cpuSetInstructionTime(4); +} + +UBY cpuMuluTime[256]; +UBY cpuMulsTime[512]; + +void cpuCreateMuluTimeTable(void) +{ + ULO i, j, k; + + for (i = 0; i < 256; i++) + { + j = 0; + for (k = 0; k < 8; k++) + if (((i>>k) & 1) == 1) + j++; + cpuMuluTime[i] = (UBY) j*2; + } +} + +void cpuCreateMulsTimeTable(void) +{ + ULO i, j, k; + + for (i = 0; i < 512; i++) + { + j = 0; + for (k = 0; k < 9; k++) + if ((((i>>k) & 3) == 1) || (((i>>k) & 3) == 2)) + j++; + cpuMulsTime[i] = (UBY) j*2; + } +} + +void cpuCreateMulTimeTables(void) +{ + cpuCreateMuluTimeTable(); + cpuCreateMulsTimeTable(); +} + +/// +/// Muls.w +/// +static ULO cpuMulsW(UWO src2, UWO src1, ULO eatime) +{ + ULO res = (ULO)(((LON)(WOR)src2)*((LON)(WOR)src1)); + cpuSetFlagsNZ00NewL(res); + cpuSetInstructionTime(38 + eatime + cpuMulsTime[(src1 << 1) & 0x1ff] + cpuMulsTime[src1 >> 7]); + return res; +} + +/// +/// Mulu.w +/// +static ULO cpuMuluW(UWO src2, UWO src1, ULO eatime) +{ + ULO res = ((ULO)src2)*((ULO)src1); + cpuSetFlagsNZ00NewL(res); + cpuSetInstructionTime(38 + eatime + cpuMuluTime[src1 & 0xff] + cpuMuluTime[src1 >> 8]); + return res; +} + +/// +/// Divsw, src1 / src2 +/// +static ULO cpuDivsW(ULO dst, UWO src1) +{ + ULO result; + if (src1 == 0) + { + // Alcatraz odyssey assumes that PC in this exception points after the instruction. + cpuThrowDivisionByZeroException(TRUE); + result = dst; + } + else + { + LON x = (LON) dst; + LON y = (LON)(WOR) src1; + LON res = x / y; + LON rem = x % y; + if (res > 32767 || res < -32768) + { + result = dst; + cpuSetFlagsVC(TRUE, FALSE); + } + else + { + result = (rem << 16) | (res & 0xffff); + cpuSetFlagsNZVC(cpuIsZeroW((UWO) res), cpuMsbW((UWO) res), FALSE, FALSE); + } + } + return result; +} + +/// +/// Divuw, src1 / src2 +/// +static ULO cpuDivuW(ULO dst, UWO src1) +{ + ULO result; + if (src1 == 0) + { + // Alcatraz odyssey assumes that PC in this exception points after the instruction. + cpuThrowDivisionByZeroException(TRUE); + result = dst; + } + else + { + ULO x = dst; + ULO y = (ULO) src1; + ULO res = x / y; + ULO rem = x % y; + if (res > 65535) + { + result = dst; + cpuSetFlagsVC(TRUE, FALSE); + } + else + { + result = (rem << 16) | (res & 0xffff); + cpuSetFlagsNZVC(cpuIsZeroW((UWO) res), cpuMsbW((UWO) res), FALSE, FALSE); + } + } + return result; +} + +static void cpuDivL(ULO divisor, ULO ext) +{ + if (divisor != 0) + { + ULO dq_reg = (ext>>12) & 7; /* Get operand registers, size and sign */ + ULO dr_reg = ext & 7; + BOOLE size64 = (ext>>10) & 1; + BOOLE sign = (ext>>11) & 1; + BOOLE resultsigned = FALSE, restsigned = FALSE; + ULL result, rest; + ULL x, y; + LLO x_signed, y_signed; + + if (sign) + { + if (size64) x_signed = ((LLO) (LON) cpuGetDReg(dq_reg)) | (((LLO) cpuGetDReg(dr_reg))<<32); + else x_signed = (LLO) (LON) cpuGetDReg(dq_reg); + y_signed = (LLO) (LON) divisor; + + if (y_signed < 0) + { + y = (ULL) -y_signed; + resultsigned = !resultsigned; + } + else y = y_signed; + if (x_signed < 0) + { + x = (ULL) -x_signed; + resultsigned = !resultsigned; + restsigned = TRUE; + } + else x = (ULL) x_signed; + } + else + { + if (size64) x = ((ULL) cpuGetDReg(dq_reg)) | (((ULL) cpuGetDReg(dr_reg))<<32); + else x = (ULL) cpuGetDReg(dq_reg); + y = (ULL) divisor; + } + + result = x / y; + rest = x % y; + + if (sign) + { + if ((resultsigned && result > 0x80000000) || (!resultsigned && result > 0x7fffffff)) + { + /* Overflow */ + cpuSetFlagsVC(TRUE, FALSE); + } + else + { + LLO result_signed = (resultsigned) ? (-(LLO)result) : ((LLO)result); + LLO rest_signed = (restsigned) ? (-(LLO)rest) : ((LLO)rest); + cpuSetDReg(dr_reg, (ULO) rest_signed); + cpuSetDReg(dq_reg, (ULO) result_signed); + cpuSetFlagsNZ00NewL((ULO) result_signed); + } + } + else + { + if (result > 0xffffffff) + { + /* Overflow */ + cpuSetFlagsVC(TRUE, FALSE); + } + else + { + cpuSetDReg(dr_reg, (ULO) rest); + cpuSetDReg(dq_reg, (ULO) result); + cpuSetFlagsNZ00NewL((ULO) result); + } + } + } + else + { + cpuThrowDivisionByZeroException(FALSE); + } +} + +/// +/// Lslb +/// +static UBY cpuLslB(UBY dst, ULO sh, ULO cycles) +{ + UBY res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroB(dst), cpuMsbB(dst)); + res = dst; + } + else if (sh >= 8) + { + res = 0; + cpuSetFlagsShift(TRUE, FALSE, (sh == 8) ? (dst & 1) : FALSE, FALSE); + } + else + { + res = dst << sh; + cpuSetFlagsShift(cpuIsZeroB(res), cpuMsbB(res), dst & (0x80>>(sh-1)), FALSE); + } + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Lslw +/// +static UWO cpuLslW(UWO dst, ULO sh, ULO cycles) +{ + UWO res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroW(dst), cpuMsbW(dst)); + res = dst; + } + else if (sh >= 16) + { + res = 0; + cpuSetFlagsShift(TRUE, FALSE, (sh == 16) ? (dst & 1) : FALSE, FALSE); + } + else + { + res = dst << sh; + cpuSetFlagsShift(cpuIsZeroW(res), cpuMsbW(res), dst & (0x8000>>(sh-1)), FALSE); + } + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Lsll +/// +static ULO cpuLslL(ULO dst, ULO sh, ULO cycles) +{ + ULO res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroL(dst), cpuMsbL(dst)); + res = dst; + } + else if (sh >= 32) + { + res = 0; + cpuSetFlagsShift(TRUE, FALSE, (sh == 32) ? (dst & 1) : FALSE, FALSE); + } + else + { + res = dst << sh; + cpuSetFlagsShift(cpuIsZeroL(res), cpuMsbL(res), dst & (0x80000000>>(sh-1)), FALSE); + } + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Lsrb +/// +static UBY cpuLsrB(UBY dst, ULO sh, ULO cycles) +{ + UBY res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroB(dst), cpuMsbB(dst)); + res = dst; + } + else if (sh >= 8) + { + res = 0; + cpuSetFlagsShift(TRUE, FALSE, (sh == 8) ? cpuMsbB(dst) : FALSE, FALSE); + } + else + { + res = dst >> sh; + cpuSetFlagsShift(cpuIsZeroB(res), FALSE, dst & (1<<(sh-1)), FALSE); + } + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Lsrw +/// +static UWO cpuLsrW(UWO dst, ULO sh, ULO cycles) +{ + UWO res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroW(dst), cpuMsbW(dst)); + res = dst; + } + else if (sh >= 16) + { + res = 0; + cpuSetFlagsShift(TRUE, FALSE, (sh == 16) ? cpuMsbW(dst) : FALSE, FALSE); + } + else + { + res = dst >> sh; + cpuSetFlagsShift(cpuIsZeroW(res), FALSE, dst & (1<<(sh-1)), FALSE); + } + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Lsrl +/// +static ULO cpuLsrL(ULO dst, ULO sh, ULO cycles) +{ + ULO res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroL(dst), cpuMsbL(dst)); + res = dst; + } + else if (sh >= 32) + { + res = 0; + cpuSetFlagsShift(TRUE, FALSE, (sh == 32) ? cpuMsbL(dst) : FALSE, FALSE); + } + else + { + res = dst >> sh; + cpuSetFlagsShift(cpuIsZeroL(res), FALSE, dst & (1<<(sh-1)), FALSE); + } + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Aslb +/// +static UBY cpuAslB(UBY dst, ULO sh, ULO cycles) +{ + BYT res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroB(dst), cpuMsbB(dst)); + res = (BYT) dst; + } + else if (sh >= 8) + { + res = 0; + cpuSetFlagsShift(TRUE, FALSE, (sh == 8) ? (dst & 1) : FALSE, dst != 0); + } + else + { + UBY mask = 0xff << (7-sh); + UBY out = dst & mask; + BOOLE n; + res = ((BYT)dst) << sh; + n = cpuMsbB(res); + cpuSetFlagsShift(cpuIsZeroB(res), n, dst & (0x80>>(sh-1)), (cpuMsbB(dst)) ? (out != mask) : (out != 0)); + } + cpuSetInstructionTime(cycles + sh*2); + return (UBY) res; +} + +/// +/// Aslw +/// +static UWO cpuAslW(UWO dst, ULO sh, ULO cycles) +{ + WOR res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroW(dst), cpuMsbW(dst)); + res = (WOR) dst; + } + else if (sh >= 16) + { + res = 0; + cpuSetFlagsShift(TRUE, FALSE, (sh == 16) ? (dst & 1) : FALSE, dst != 0); + } + else + { + UWO mask = 0xffff << (15-sh); + UWO out = dst & mask; + BOOLE n; + res = ((WOR)dst) << sh; + n = cpuMsbW(res); + cpuSetFlagsShift(cpuIsZeroW(res), n, dst & (0x8000>>(sh-1)), (cpuMsbW(dst)) ? (out != mask) : (out != 0)); + } + cpuSetInstructionTime(cycles + sh*2); + return (UWO) res; +} + +/// +/// Asll +/// +static ULO cpuAslL(ULO dst, ULO sh, ULO cycles) +{ + LON res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroL(dst), cpuMsbL(dst)); + res = (LON) dst; + } + else if (sh >= 32) + { + res = 0; + cpuSetFlagsShift(TRUE, FALSE, (sh == 32) ? (dst & 1) : FALSE, dst != 0); + } + else + { + ULO mask = 0xffffffff << (31-sh); + ULO out = dst & mask; + BOOLE n; + res = ((LON)dst) << sh; + n = cpuMsbL(res); + cpuSetFlagsShift(cpuIsZeroL(res), n, dst & (0x80000000>>(sh-1)), (cpuMsbL(dst)) ? (out != mask) : (out != 0)); + } + cpuSetInstructionTime(cycles + sh*2); + return (ULO) res; +} + +/// +/// Asrb +/// +static UBY cpuAsrB(UBY dst, ULO sh, ULO cycles) +{ + BYT res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroB(dst), cpuMsbB(dst)); + res = (BYT) dst; + } + else if (sh >= 8) + { + res = (cpuMsbB(dst)) ? 0xff : 0; + cpuSetFlagsShift(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(res), FALSE); + } + else + { + res = ((BYT)dst) >> sh; + cpuSetFlagsShift(cpuIsZeroB(res), cpuMsbB(res), dst & (1<<(sh-1)), FALSE); + } + cpuSetInstructionTime(cycles + sh*2); + return (UBY) res; +} + +/// +/// Asrw +/// +static UWO cpuAsrW(UWO dst, ULO sh, ULO cycles) +{ + WOR res; + sh &= 0x3f; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroW(dst), cpuMsbW(dst)); + res = (WOR) dst; + } + else if (sh >= 16) + { + res = (cpuMsbW(dst)) ? 0xffff : 0; + cpuSetFlagsShift(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(res), FALSE); + } + else + { + res = ((WOR)dst) >> sh; + cpuSetFlagsShift(cpuIsZeroW(res), cpuMsbW(res), dst & (1<<(sh-1)), FALSE); + } + cpuSetInstructionTime(cycles + sh*2); + return (UWO) res; +} + +/// +/// Asrl +/// +static ULO cpuAsrL(ULO dst, ULO sh, ULO cycles) +{ + LON res; + sh &= 0x3f; + + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroL(dst), cpuMsbL(dst)); + res = (LON) dst; + } + else if (sh >= 32) + { + res = (cpuMsbL(dst)) ? 0xffffffff : 0; + cpuSetFlagsShift(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(res), FALSE); + } + else + { + res = ((LON)dst) >> sh; + cpuSetFlagsShift(cpuIsZeroL(res), cpuMsbL(res), dst & (1<<(sh-1)), FALSE); + } + cpuSetInstructionTime(cycles + sh*2); + return (ULO) res; +} + +/// +/// Rolb +/// +static UBY cpuRolB(UBY dst, ULO sh, ULO cycles) +{ + UBY res; + sh &= 0x3f; + cycles += sh*2; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroB(dst), cpuMsbB(dst)); + res = dst; + } + else + { + sh &= 7; + res = (dst << sh) | (dst >> (8-sh)); + cpuSetFlagsRotate(cpuIsZeroB(res), cpuMsbB(res), res & 1); + } + cpuSetInstructionTime(cycles); + return res; +} + +/// +/// Rolw +/// +static UWO cpuRolW(UWO dst, ULO sh, ULO cycles) +{ + UWO res; + sh &= 0x3f; + cycles += sh*2; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroW(dst), cpuMsbW(dst)); + res = dst; + } + else + { + sh &= 15; + res = (dst << sh) | (dst >> (16-sh)); + cpuSetFlagsRotate(cpuIsZeroW(res), cpuMsbW(res), res & 1); + } + cpuSetInstructionTime(cycles); + return res; +} + +/// +/// Roll +/// +static ULO cpuRolL(ULO dst, ULO sh, ULO cycles) +{ + ULO res; + sh &= 0x3f; + cycles += sh*2; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroL(dst), cpuMsbL(dst)); + res = dst; + } + else + { + sh &= 31; + res = (dst << sh) | (dst >> (32-sh)); + cpuSetFlagsRotate(cpuIsZeroL(res), cpuMsbL(res), res & 1); + } + cpuSetInstructionTime(cycles); + return res; +} + +/// +/// Rorb +/// +static UBY cpuRorB(UBY dst, ULO sh, ULO cycles) +{ + UBY res; + sh &= 0x3f; + cycles += sh*2; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroB(dst), cpuMsbB(dst)); + res = dst; + } + else + { + sh &= 7; + res = (dst >> sh) | (dst << (8-sh)); + cpuSetFlagsRotate(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(res)); + } + cpuSetInstructionTime(cycles); + return res; +} + +/// +/// Rorw +/// +static UWO cpuRorW(UWO dst, ULO sh, ULO cycles) +{ + UWO res; + sh &= 0x3f; + cycles += sh*2; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroW(dst), cpuMsbW(dst)); + res = dst; + } + else + { + sh &= 15; + res = (dst >> sh) | (dst << (16-sh)); + cpuSetFlagsRotate(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(res)); + } + cpuSetInstructionTime(cycles); + return res; +} + +/// +/// Rorl +/// +static ULO cpuRorL(ULO dst, ULO sh, ULO cycles) +{ + ULO res; + sh &= 0x3f; + cycles += sh*2; + if (sh == 0) + { + cpuSetFlagsShiftZero(cpuIsZeroL(dst), cpuMsbL(dst)); + res = dst; + } + else + { + sh &= 31; + res = (dst >> sh) | (dst << (32-sh)); + cpuSetFlagsRotate(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(res)); + } + cpuSetInstructionTime(cycles); + return res; +} + +/// +/// Roxlb +/// +static UBY cpuRoxlB(UBY dst, ULO sh, ULO cycles) +{ + BOOLE x = cpuGetFlagX(); + BOOLE x_temp; + UBY res = dst; + ULO i; + sh &= 0x3f; + for (i = 0; i < sh; ++i) + { + x_temp = cpuMsbB(res); + res = (res << 1) | ((x) ? 1:0); + x = x_temp; + } + cpuSetFlagsRotateX(cpuGetZFlagB(res), cpuGetNFlagB(res), (x) ? 0x11 : 0); + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Roxlw +/// +static UWO cpuRoxlW(UWO dst, ULO sh, ULO cycles) +{ + BOOLE x = cpuGetFlagX(); + BOOLE x_temp; + UWO res = dst; + ULO i; + sh &= 0x3f; + for (i = 0; i < sh; ++i) + { + x_temp = cpuMsbW(res); + res = (res << 1) | ((x) ? 1:0); + x = x_temp; + } + cpuSetFlagsRotateX(cpuGetZFlagW(res), cpuGetNFlagW(res), (x) ? 0x11 : 0); + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Roxll +/// +static ULO cpuRoxlL(ULO dst, ULO sh, ULO cycles) +{ + BOOLE x = cpuGetFlagX(); + BOOLE x_temp; + ULO res = dst; + ULO i; + sh &= 0x3f; + for (i = 0; i < sh; ++i) + { + x_temp = cpuMsbL(res); + res = (res << 1) | ((x) ? 1:0); + x = x_temp; + } + cpuSetFlagsRotateX(cpuGetZFlagL(res), cpuGetNFlagL(res), (x) ? 0x11 : 0); + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Roxrb +/// +static UBY cpuRoxrB(UBY dst, ULO sh, ULO cycles) +{ + BOOLE x = cpuGetFlagX(); + BOOLE x_temp; + UBY res = dst; + ULO i; + sh &= 0x3f; + for (i = 0; i < sh; ++i) + { + x_temp = res & 1; + res = (res >> 1) | ((x) ? 0x80:0); + x = x_temp; + } + cpuSetFlagsRotateX(cpuGetZFlagB(res), cpuGetNFlagB(res), (x) ? 0x11 : 0); + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Roxrw +/// +static UWO cpuRoxrW(UWO dst, ULO sh, ULO cycles) +{ + BOOLE x = cpuGetFlagX(); + BOOLE x_temp; + UWO res = dst; + ULO i; + sh &= 0x3f; + for (i = 0; i < sh; ++i) + { + x_temp = res & 1; + res = (res >> 1) | ((x) ? 0x8000:0); + x = x_temp; + } + cpuSetFlagsRotateX(cpuGetZFlagW(res), cpuGetNFlagW(res), (x) ? 0x11 : 0); + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Roxrl +/// +static ULO cpuRoxrL(ULO dst, ULO sh, ULO cycles) +{ + BOOLE x = cpuGetFlagX(); + BOOLE x_temp; + ULO res = dst; + ULO i; + sh &= 0x3f; + for (i = 0; i < sh; ++i) + { + x_temp = res & 1; + res = (res >> 1) | ((x) ? 0x80000000:0); + x = x_temp; + } + cpuSetFlagsRotateX(cpuGetZFlagL(res), cpuGetNFlagL(res), (x) ? 0x11 : 0); + cpuSetInstructionTime(cycles + sh*2); + return res; +} + +/// +/// Stop +/// +static void cpuStop(UWO flags) +{ + if (cpuGetFlagSupervisor()) + { + cpuSetStop(TRUE); + cpuUpdateSr(flags); + cpuSetInstructionTime(4); + } + else + { + cpuThrowPrivilegeViolationException(); + } +} + +/// +/// Reset +/// +static void cpuReset() +{ + cpuCallResetExceptionFunc(); + cpuSetInstructionTime(132); +} + +/// +/// Rtd +/// +static void cpuRtd() +{ + ULO displacement = cpuGetNextWordSignExt(); + cpuSetAReg(7, cpuGetAReg(7) + 4 + displacement); + cpuSetInstructionTime(4); +} + +static ULO cpuRteStackInc[16] = {0, 0, 4, 4, 8, 0, 0, 52, 50, 10, 24, 84, 16, 18, 0, 0}; + +/// +/// Rte +/// +static void cpuRte() +{ + if (cpuGetFlagSupervisor()) + { + BOOLE redo = TRUE; + UWO newsr; + do + { + newsr = memoryReadWord(cpuGetAReg(7)); + cpuSetAReg(7, cpuGetAReg(7) + 2); + + cpuInitializeFromNewPC(memoryReadLong(cpuGetAReg(7))); + cpuSetAReg(7, cpuGetAReg(7) + 4); + + if (cpuGetModelMajor() > 0) + { + ULO frame_type = (memoryReadWord(cpuGetAReg(7)) >> 12) & 0xf; + cpuSetAReg(7, cpuGetAReg(7) + 2); + cpuSetAReg(7, cpuGetAReg(7) + cpuRteStackInc[frame_type]); + redo = (frame_type == 1 && cpuGetModelMajor() >= 2 && cpuGetModelMajor() < 6); + } + else redo = FALSE; + + cpuUpdateSr(newsr); // Because we can go from isp to msp here. + + } while (redo); + } + else + { + cpuThrowPrivilegeViolationException(); + } + cpuSetInstructionTime(20); +} + +/// +/// Swap +/// +static void cpuSwap(ULO reg) +{ + ULO res = cpuJoinWordToLong((UWO)cpuGetDReg(reg), (UWO) (cpuGetDReg(reg) >> 16)); + cpuSetDReg(reg, res); + cpuSetFlagsNZ00NewL(res); + cpuSetInstructionTime(4); +} + +/// +/// Unlk +/// +static void cpuUnlk(ULO reg) +{ + cpuSetAReg(7, cpuGetAReg(reg)); + cpuSetAReg(reg, memoryReadLong(cpuGetAReg(7))); + cpuSetAReg(7, cpuGetAReg(7) + 4); + cpuSetInstructionTime(12); +} + +/// +/// Link +/// +static void cpuLinkW(ULO reg) +{ + ULO disp = cpuGetNextWordSignExt(); + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(cpuGetAReg(reg), cpuGetAReg(7)); + cpuSetAReg(reg, cpuGetAReg(7)); + cpuSetAReg(7, cpuGetAReg(7) + disp); + cpuSetInstructionTime(16); +} + +/// +/// Link. +/// 68020, 68030 and 68040 only. +/// +static void cpuLinkL(ULO reg) +{ + ULO disp = cpuGetNextLong(); + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(cpuGetAReg(reg), cpuGetAReg(7)); + cpuSetAReg(reg, cpuGetAReg(7)); + cpuSetAReg(7, cpuGetAReg(7) + disp); + cpuSetInstructionTime(4); +} + +/// +/// Ext.w (byte to word) +/// +static void cpuExtW(ULO reg) +{ + UWO res = cpuGetDRegByteSignExtWord(reg); + cpuSetDRegWord(reg, res); + cpuSetFlagsNZ00NewW(res); + cpuSetInstructionTime(4); +} + +/// +/// Ext.l (word to long) +/// +static void cpuExtL(ULO reg) +{ + ULO res = cpuGetDRegWordSignExtLong(reg); + cpuSetDReg(reg, res); + cpuSetFlagsNZ00NewL(res); + cpuSetInstructionTime(4); +} + +/// +/// ExtB.l (byte to long) (020+) +/// +static void cpuExtBL(ULO reg) +{ + ULO res = cpuGetDRegByteSignExtLong(reg); + cpuSetDReg(reg, res); + cpuSetFlagsNZ00NewL(res); + cpuSetInstructionTime(4); +} + +/// +/// Exg Rx,Ry +/// +static void cpuExgAll(ULO reg1_type, ULO reg1, ULO reg2_type, ULO reg2) +{ + ULO tmp = cpuGetReg(reg1_type, reg1); + cpuSetReg(reg1_type, reg1, cpuGetReg(reg2_type, reg2)); + cpuSetReg(reg2_type, reg2, tmp); + cpuSetInstructionTime(6); +} + +/// +/// Exg Dx,Dy +/// +static void cpuExgDD(ULO reg1, ULO reg2) +{ + cpuExgAll(0, reg1, 0, reg2); +} + +/// +/// Exg Ax,Ay +/// +static void cpuExgAA(ULO reg1, ULO reg2) +{ + cpuExgAll(1, reg1, 1, reg2); +} + +/// +/// Exg Dx,Ay +/// +static void cpuExgDA(ULO reg1, ULO reg2) +{ + cpuExgAll(0, reg1, 1, reg2); +} + +/// +/// Movem.w regs, -(Ax) +/// Order: d0-d7,a0-a7 a7 first +/// +static void cpuMovemwPre(UWO regs, ULO reg) +{ + ULO cycles = 8; + ULO dstea = cpuGetAReg(reg); + ULO index = 1; + LON i, j; + BOOLE ea_reg_seen = FALSE; + ULO ea_reg_ea = 0; + + i = 1; + for (j = 7; j >= 0; j--) + { + if (regs & index) + { + dstea -= 2; + if (cpuGetModelMajor() >= 2 && j == reg) + { + ea_reg_seen = TRUE; + ea_reg_ea = dstea; + } + else + { + memoryWriteWord(cpuGetRegWord(i, j), dstea); + } + cycles += 4; + } + index = index << 1; + } + + i = 0; + for (j = 7; j >= 0; j--) + { + if (regs & index) + { + dstea -= 2; + memoryWriteWord(cpuGetRegWord(i, j), dstea); + cycles += 4; + } + index = index << 1; + } + if (ea_reg_seen) + { + memoryWriteWord((UWO)dstea, ea_reg_ea); + } + cpuSetAReg(reg, dstea); + cpuSetInstructionTime(cycles); +} + +/// +/// Movem.l regs, -(Ax) +/// Order: d0-d7,a0-a7 a7 first +/// +static void cpuMovemlPre(UWO regs, ULO reg) +{ + ULO cycles = 8; + ULO dstea = cpuGetAReg(reg); + ULO index = 1; + LON i, j; + BOOLE ea_reg_seen = FALSE; + ULO ea_reg_ea = 0; + + i = 1; + for (j = 7; j >= 0; j--) + { + if (regs & index) + { + dstea -= 4; + if (cpuGetModelMajor() >= 2 && j == reg) + { + ea_reg_seen = TRUE; + ea_reg_ea = dstea; + } + else + { + memoryWriteLong(cpuGetReg(i, j), dstea); + } + cycles += 8; + } + index = index << 1; + } + + i = 0; + for (j = 7; j >= 0; j--) + { + if (regs & index) + { + dstea -= 4; + memoryWriteLong(cpuGetReg(i, j), dstea); + cycles += 8; + } + index = index << 1; + } + + if (ea_reg_seen) + { + memoryWriteLong(dstea, ea_reg_ea); + } + cpuSetAReg(reg, dstea); + cpuSetInstructionTime(cycles); +} + +/// +/// Movem.w (Ax)+, regs +/// Order: a7-a0,d7-d0 d0 first +/// +static void cpuMovemwPost(UWO regs, ULO reg) +{ + ULO cycles = 12; + ULO dstea = cpuGetAReg(reg); + ULO index = 1; + ULO i, j; + + for (i = 0; i < 2; ++i) + { + for (j = 0; j < 8; ++j) + { + if (regs & index) + { + // Each word, for both data and address registers, is sign-extended before stored. + cpuSetReg(i, j, (ULO)(LON)(WOR) memoryReadWord(dstea)); + dstea += 2; + cycles += 4; + } + index = index << 1; + } + } + cpuSetAReg(reg, dstea); + cpuSetInstructionTime(cycles); +} + +/// +/// Movem.l (Ax)+, regs +/// Order: a7-a0,d7-d0 d0 first +/// +static void cpuMovemlPost(UWO regs, ULO reg) +{ + ULO cycles = 12; + ULO dstea = cpuGetAReg(reg); + ULO index = 1; + ULO i, j; + + for (i = 0; i < 2; ++i) + { + for (j = 0; j < 8; ++j) + { + if (regs & index) + { + cpuSetReg(i, j, memoryReadLong(dstea)); + dstea += 4; + cycles += 8; + } + index = index << 1; + } + } + cpuSetAReg(reg, dstea); + cpuSetInstructionTime(cycles); +} + +/// +/// Movem.w , regs +/// Order: a7-a0,d7-d0 d0 first +/// +static void cpuMovemwEa2R(UWO regs, ULO ea, ULO eacycles) +{ + ULO cycles = eacycles; + ULO dstea = ea; + ULO index = 1; + ULO i, j; + + for (i = 0; i < 2; ++i) + { + for (j = 0; j < 8; ++j) + { + if (regs & index) + { + // Each word, for both data and address registers, is sign-extended before stored. + cpuSetReg(i, j, (ULO)(LON)(WOR) memoryReadWord(dstea)); + dstea += 2; + cycles += 4; + } + index = index << 1; + } + } + cpuSetInstructionTime(cycles); +} + +/// +/// Movem.l , regs +/// Order: a7-a0,d7-d0 d0 first +/// +static void cpuMovemlEa2R(UWO regs, ULO ea, ULO eacycles) +{ + ULO cycles = eacycles; + ULO dstea = ea; + ULO index = 1; + ULO i, j; + + for (i = 0; i < 2; ++i) + { + for (j = 0; j < 8; ++j) + { + if (regs & index) + { + cpuSetReg(i, j, memoryReadLong(dstea)); + dstea += 4; + cycles += 8; + } + index = index << 1; + } + } + cpuSetInstructionTime(cycles); +} + +/// +/// Movem.w regs, +/// Order: a7-a0,d7-d0 d0 first +/// +static void cpuMovemwR2Ea(UWO regs, ULO ea, ULO eacycles) +{ + ULO cycles = eacycles; + ULO dstea = ea; + ULO index = 1; + ULO i, j; + + for (i = 0; i < 2; ++i) + { + for (j = 0; j < 8; ++j) + { + if (regs & index) + { + memoryWriteWord(cpuGetRegWord(i, j), dstea); + dstea += 2; + cycles += 4; + } + index = index << 1; + } + } + cpuSetInstructionTime(cycles); +} + +/// +/// Movem.l regs, +/// Order: a7-a0,d7-d0 d0 first +/// +static void cpuMovemlR2Ea(UWO regs, ULO ea, ULO eacycles) +{ + ULO cycles = eacycles; + ULO dstea = ea; + ULO index = 1; + ULO i, j; + + for (i = 0; i < 2; ++i) + { + for (j = 0; j < 8; ++j) + { + if (regs & index) + { + memoryWriteLong(cpuGetReg(i, j), dstea); + dstea += 4; + cycles += 8; + } + index = index << 1; + } + } + cpuSetInstructionTime(cycles); +} + +/// +/// Trap #vectorno +/// +static void cpuTrap(ULO vectorno) +{ + // PC written to the exception frame must be pc + 2, the address of the next instruction. + cpuThrowTrapException(vectorno); +} + +/// +/// move.l Ax,Usp +/// +static void cpuMoveToUsp(ULO reg) +{ + if (cpuGetFlagSupervisor()) + { + // In supervisor mode, usp does not affect a7 + cpuSetUspDirect(cpuGetAReg(reg)); + cpuSetInstructionTime(4); + } + else + { + cpuThrowPrivilegeViolationException(); + } +} + +/// +/// move.l Usp,Ax +/// +static void cpuMoveFromUsp(ULO reg) +{ + if (cpuGetFlagSupervisor()) + { + // In supervisor mode, usp is up to date + cpuSetAReg(reg, cpuGetUspDirect()); + cpuSetInstructionTime(4); + } + else + { + cpuThrowPrivilegeViolationException(); + } +} + +/// +/// cmp.b (Ay)+,(Ax)+ +/// +static void cpuCmpMB(ULO regx, ULO regy) +{ + UBY src = memoryReadByte(cpuEA03(regy, 1)); + UBY dst = memoryReadByte(cpuEA03(regx, 1)); + UBY res = dst - src; + cpuSetFlagsCmp(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(dst), cpuMsbB(src)); + cpuSetInstructionTime(12); +} + +/// +/// cmp.w (Ay)+,(Ax)+ +/// +static void cpuCmpMW(ULO regx, ULO regy) +{ + UWO src = memoryReadWord(cpuEA03(regy, 2)); + UWO dst = memoryReadWord(cpuEA03(regx, 2)); + UWO res = dst - src; + cpuSetFlagsCmp(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(dst), cpuMsbW(src)); + cpuSetInstructionTime(12); +} + +/// +/// cmp.l (Ay)+,(Ax)+ +/// +static void cpuCmpML(ULO regx, ULO regy) +{ + ULO src = memoryReadLong(cpuEA03(regy, 4)); + ULO dst = memoryReadLong(cpuEA03(regx, 4)); + ULO res = dst - src; + cpuSetFlagsCmp(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(dst), cpuMsbL(src)); + cpuSetInstructionTime(20); +} + +/// +/// chk.w Dx, ea +/// Undocumented features: +/// Z is set from the register operand, +/// V and C is always cleared. +/// +static void cpuChkW(UWO value, UWO ub) +{ + cpuSetFlagZ(value == 0); + cpuSetFlagsVC(FALSE, FALSE); + if (((WOR)value) < 0) + { + cpuSetFlagN(TRUE); + cpuThrowChkException(); + } + else if (((WOR)value) > ((WOR)ub)) + { + cpuSetFlagN(FALSE); + cpuThrowChkException(); + } +} + +/// +/// chk.l Dx, ea +/// 68020+ +/// Undocumented features: +/// Z is set from the register operand, +/// V and C is always cleared. +/// +static void cpuChkL(ULO value, ULO ub) +{ + cpuSetFlagZ(value == 0); + cpuSetFlagsVC(FALSE, FALSE); + if (((LON)value) < 0) + { + cpuSetFlagN(TRUE); + cpuThrowChkException(); + } + else if (((LON)value) > ((LON)ub)) + { + cpuSetFlagN(FALSE); + cpuThrowChkException(); + } +} + +/// +/// addx.b dx,dy +/// +static UBY cpuAddXB(UBY dst, UBY src) +{ + UBY res = dst + src + ((cpuGetFlagX()) ? 1:0); + cpuSetFlagsAddX(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(dst), cpuMsbB(src)); + return res; +} + +/// +/// addx.w dx,dy +/// +static UWO cpuAddXW(UWO dst, UWO src) +{ + UWO res = dst + src + ((cpuGetFlagX()) ? 1:0); + cpuSetFlagsAddX(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(dst), cpuMsbW(src)); + return res; +} + +/// +/// addx.l dx,dy +/// +static ULO cpuAddXL(ULO dst, ULO src) +{ + ULO res = dst + src + ((cpuGetFlagX()) ? 1:0); + cpuSetFlagsAddX(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(dst), cpuMsbL(src)); + return res; +} + +/// +/// subx.b dx,dy +/// +static UBY cpuSubXB(UBY dst, UBY src) +{ + UBY res = dst - src - ((cpuGetFlagX()) ? 1:0); + cpuSetFlagsSubX(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(dst), cpuMsbB(src)); + return res; +} + +/// +/// subx.w dx,dy +/// +static UWO cpuSubXW(UWO dst, UWO src) +{ + UWO res = dst - src - ((cpuGetFlagX()) ? 1:0); + cpuSetFlagsSubX(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(dst), cpuMsbW(src)); + return res; +} + +/// +/// subx.l dx,dy +/// +static ULO cpuSubXL(ULO dst, ULO src) +{ + ULO res = dst - src - ((cpuGetFlagX()) ? 1:0); + cpuSetFlagsSubX(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(dst), cpuMsbL(src)); + return res; +} + +/// +/// abcd.b src,dst +/// Implemented using the information from: +/// 68000 Undocumented Behavior Notes +/// Fourth Edition +/// by Bart Trzynadlowski, May 12, 2003 +/// +static UBY cpuAbcdB(UBY dst, UBY src) +{ + UBY xflag = (cpuGetFlagX()) ? 1:0; + UWO res = dst + src + xflag; + UWO res_unadjusted = res; + UBY res_bcd; + UBY low_nibble = (dst & 0xf) + (src & 0xf) + xflag; + + if (low_nibble > 9) + { + res += 6; + } + + if (res > 0x99) + { + res += 0x60; + cpuSetFlagXC(TRUE); + } + else + { + cpuSetFlagXC(FALSE); + } + + res_bcd = (UBY) res; + + if (res_bcd != 0) + { + cpuSetFlagZ(FALSE); + } + if (res_bcd & 0x80) + { + cpuSetFlagN(TRUE); + } + cpuSetFlagV(((res_unadjusted & 0x80) == 0) && (res_bcd & 0x80)); + return res_bcd; +} + +/// +/// sbcd.b src,dst +/// nbcd.b src (set dst=0) +/// Implemented using the information from: +/// 68000 Undocumented Behavior Notes +/// Fourth Edition +/// by Bart Trzynadlowski, May 12, 2003 +/// +static UBY cpuSbcdB(UBY dst, UBY src) +{ + UBY xflag = (cpuGetFlagX()) ? 1:0; + UWO res = dst - src - xflag; + UWO res_unadjusted = res; + UBY res_bcd; + + if (((src & 0xf) + xflag) > (dst & 0xf)) + { + res -= 6; + } + if (res & 0x80) + { + res -= 0x60; + cpuSetFlagXC(TRUE); + } + else + { + cpuSetFlagXC(FALSE); + } + res_bcd = (UBY) res; + + if (res_bcd != 0) + { + cpuSetFlagZ(FALSE); + } + if (res_bcd & 0x80) + { + cpuSetFlagN(TRUE); + } + cpuSetFlagV(((res_unadjusted & 0x80) == 0x80) && !(res_bcd & 0x80)); + return res_bcd; +} + +/// +/// nbcd.b dst +/// +static UBY cpuNbcdB(UBY dst) +{ + return cpuSbcdB(0, dst); +} + +// Bit field functions +static void cpuGetBfRegBytes(UBY *bytes, ULO regno) +{ + bytes[0] = (UBY)(cpuGetDReg(regno) >> 24); + bytes[1] = (UBY)(cpuGetDReg(regno) >> 16); + bytes[2] = (UBY)(cpuGetDReg(regno) >> 8); + bytes[3] = (UBY)cpuGetDReg(regno); +} + +static void cpuGetBfEaBytes(UBY *bytes, ULO address, ULO count) +{ + ULO i; + for (i = 0; i < count; ++i) + { + bytes[i] = memoryReadByte(address + i); + } +} + +static void cpuSetBfRegBytes(UBY *bytes, ULO regno) +{ + cpuSetDReg(regno, cpuJoinByteToLong(bytes[0], bytes[1], bytes[2], bytes[3])); +} + +static void cpuSetBfEaBytes(UBY *bytes, ULO address, ULO count) +{ + ULO i; + for (i = 0; i < count; ++i) + { + memoryWriteByte(bytes[i], address + i); + } +} + +static LON cpuGetBfOffset(UWO ext, BOOLE offsetIsDr) +{ + LON offset = (ext >> 6) & 0x1f; + if (offsetIsDr) + { + offset = (LON) cpuGetDReg(offset & 7); + } + return offset; +} + +static ULO cpuGetBfWidth(UWO ext, BOOLE widthIsDr) +{ + ULO width = (ext & 0x1f); + if (widthIsDr) + { + width = (cpuGetDReg(width & 7) & 0x1f); + } + if (width == 0) + { + width = 32; + } + return width; +} + +static ULO cpuGetBfField(UBY *bytes, ULO end_offset, ULO byte_count, ULO field_mask) +{ + ULO i; + ULO field = ((ULO)bytes[byte_count - 1]) >> end_offset; + + for (i = 1; i < byte_count; i++) + { + field |= ((ULO)bytes[byte_count - i - 1]) << (8*i - end_offset); + } + return field & field_mask; +} + +static void cpuSetBfField(UBY *bytes, ULO end_offset, ULO byte_count, ULO field, ULO field_mask) +{ + ULO i; + + bytes[byte_count - 1] = (UBY)((field << end_offset) | (bytes[byte_count - 1] & (UBY)~(field_mask << end_offset))); + for (i = 1; i < byte_count - 1; ++i) + { + bytes[byte_count - i - 1] = (UBY)(field >> (end_offset + 8*i)); + } + if (i < byte_count) + { + bytes[0] = (bytes[0] & (UBY)~(field_mask >> (end_offset + 8*i)) | (UBY)(field >> (end_offset + 8*i))); + } +} + +struct cpuBfData +{ + UWO ext; + BOOLE offsetIsDr; + BOOLE widthIsDr; + LON offset; + ULO width; + ULO base_address; + ULO bit_offset; + ULO end_offset; + ULO byte_count; + ULO field; + ULO field_mask; + ULO dn; + UBY b[5]; +}; + +void cpuBfExtWord(struct cpuBfData *bf_data, ULO val, BOOLE has_dn, BOOLE has_ea, UWO ext) +{ + bf_data->ext = ext; + bf_data->offsetIsDr = (bf_data->ext & 0x0800); + bf_data->widthIsDr = (bf_data->ext & 0x20); + bf_data->offset = cpuGetBfOffset(bf_data->ext, bf_data->offsetIsDr); + bf_data->width = cpuGetBfWidth(bf_data->ext, bf_data->widthIsDr); + bf_data->bit_offset = bf_data->offset & 7; + bf_data->byte_count = ((bf_data->bit_offset + bf_data->width + 7) >> 3); + bf_data->end_offset = (bf_data->byte_count*8 - (bf_data->offset + bf_data->width)) & 7; + bf_data->field = 0; + bf_data->field_mask = 0xffffffff >> (32 - bf_data->width); + if (has_dn) + { + bf_data->dn = (bf_data->ext & 0x7000) >> 12; + } + if (has_ea) + { + bf_data->base_address = val + (bf_data->offset >> 3); + cpuGetBfEaBytes(&bf_data->b[0], bf_data->base_address, bf_data->byte_count); + } + else + { + cpuGetBfRegBytes(&bf_data->b[0], val); + } +} + +/// +/// bfchg common logic +/// +static void cpuBfChgCommon(ULO val, BOOLE has_ea, UWO ext) +{ + struct cpuBfData bf_data; + cpuBfExtWord(&bf_data, val, FALSE, has_ea, ext); + bf_data.field = cpuGetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field_mask); + cpuSetFlagsNZVC(bf_data.field == 0, bf_data.field & (1 << (bf_data.width - 1)), FALSE, FALSE); + cpuSetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, (~bf_data.field) & bf_data.field_mask, bf_data.field_mask); + if (has_ea) + { + cpuSetBfEaBytes(&bf_data.b[0], bf_data.base_address, bf_data.byte_count); + } + else + { + cpuSetBfRegBytes(&bf_data.b[0], val); + } +} + +/// +/// bfchg dx {offset:width} +/// +static void cpuBfChgReg(ULO regno, UWO ext) +{ + cpuBfChgCommon(regno, FALSE, ext); +} + +/// +/// bfchg ea {offset:width} +/// +static void cpuBfChgEa(ULO ea, UWO ext) +{ + cpuBfChgCommon(ea, TRUE, ext); +} + +/// +/// bfclr common logic +/// +static void cpuBfClrCommon(ULO val, BOOLE has_ea, UWO ext) +{ + struct cpuBfData bf_data; + cpuBfExtWord(&bf_data, val, FALSE, has_ea, ext); + bf_data.field = cpuGetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field_mask); + cpuSetFlagsNZVC(bf_data.field == 0, bf_data.field & (1 << (bf_data.width - 1)), FALSE, FALSE); + cpuSetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, 0, bf_data.field_mask); + if (has_ea) + { + cpuSetBfEaBytes(&bf_data.b[0], bf_data.base_address, bf_data.byte_count); + } + else + { + cpuSetBfRegBytes(&bf_data.b[0], val); + } +} + +/// +/// bfclr dx {offset:width} +/// +static void cpuBfClrReg(ULO regno, UWO ext) +{ + cpuBfClrCommon(regno, FALSE, ext); +} + +/// +/// bfclr ea {offset:width} +/// +static void cpuBfClrEa(ULO ea, UWO ext) +{ + cpuBfClrCommon(ea, TRUE, ext); +} + +/// +/// bfexts common logic +/// +static void cpuBfExtsCommon(ULO val, BOOLE has_ea, UWO ext) +{ + struct cpuBfData bf_data; + BOOLE n_flag; + cpuBfExtWord(&bf_data, val, TRUE, has_ea, ext); + bf_data.field = cpuGetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field_mask); + n_flag = bf_data.field & (1 << (bf_data.width - 1)); + cpuSetFlagsNZVC(bf_data.field == 0, n_flag, FALSE, FALSE); + if (n_flag) + { + bf_data.field = ~bf_data.field_mask | bf_data.field; + } + cpuSetDReg(bf_data.dn, bf_data.field); +} + +/// +/// bfexts dx {offset:width}, Dn +/// +static void cpuBfExtsReg(ULO regno, UWO ext) +{ + cpuBfExtsCommon(regno, FALSE, ext); +} + +/// +/// bfexts ea {offset:width}, Dn +/// +static void cpuBfExtsEa(ULO ea, UWO ext) +{ + cpuBfExtsCommon(ea, TRUE, ext); +} + +/// +/// bfextu ea {offset:width}, Dn +/// +static void cpuBfExtuCommon(ULO val, BOOLE has_ea, UWO ext) +{ + struct cpuBfData bf_data; + cpuBfExtWord(&bf_data, val, TRUE, has_ea, ext); + bf_data.field = cpuGetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field_mask); + cpuSetFlagsNZVC(bf_data.field == 0, bf_data.field & (1 << (bf_data.width - 1)), FALSE, FALSE); + cpuSetDReg(bf_data.dn, bf_data.field); +} + +/// +/// bfextu dx {offset:width}, Dn +/// +static void cpuBfExtuReg(ULO regno, UWO ext) +{ + cpuBfExtuCommon(regno, FALSE, ext); +} + +/// +/// bfextu ea {offset:width}, Dn +/// +static void cpuBfExtuEa(ULO ea, UWO ext) +{ + cpuBfExtuCommon(ea, TRUE, ext); +} + +/// +/// bfffo common logic +/// +static void cpuBfFfoCommon(ULO val, BOOLE has_ea, UWO ext) +{ + struct cpuBfData bf_data; + ULO i; + cpuBfExtWord(&bf_data, val, TRUE, has_ea, ext); + bf_data.field = cpuGetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field_mask); + cpuSetFlagsNZVC(bf_data.field == 0, bf_data.field & (1 << (bf_data.width - 1)), FALSE, FALSE); + for (i = 0; i < bf_data.width; ++i) + { + if (bf_data.field & (0x1 << (bf_data.width - i - 1))) + break; + } + cpuSetDReg(bf_data.dn, bf_data.offset + i); +} + +/// +/// bfffo dx {offset:width}, Dn +/// +static void cpuBfFfoReg(ULO regno, UWO ext) +{ + cpuBfFfoCommon(regno, FALSE, ext); +} + +/// +/// bfffo ea {offset:width}, Dn +/// +static void cpuBfFfoEa(ULO ea, UWO ext) +{ + cpuBfFfoCommon(ea, TRUE, ext); +} + +/// +/// bfins common logic +/// +static void cpuBfInsCommon(ULO val, BOOLE has_ea, UWO ext) +{ + struct cpuBfData bf_data; + cpuBfExtWord(&bf_data, val, TRUE, has_ea, ext); + bf_data.field = cpuGetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field_mask); + cpuSetFlagsNZVC(bf_data.field == 0, bf_data.field & (1 << (bf_data.width - 1)), FALSE, FALSE); + bf_data.field = cpuGetDReg(bf_data.dn) & bf_data.field_mask; + cpuSetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field, bf_data.field_mask); + if (has_ea) + { + cpuSetBfEaBytes(&bf_data.b[0], bf_data.base_address, bf_data.byte_count); + } + else + { + cpuSetBfRegBytes(&bf_data.b[0], val); + } +} + +/// +/// bfins Dn, ea {offset:width} +/// +static void cpuBfInsReg(ULO regno, UWO ext) +{ + cpuBfInsCommon(regno, FALSE, ext); +} + +/// +/// bfins Dn, ea {offset:width} +/// +static void cpuBfInsEa(ULO ea, UWO ext) +{ + cpuBfInsCommon(ea, TRUE, ext); +} + +/// +/// bfset common logic +/// +static void cpuBfSetCommon(ULO val, BOOLE has_ea, UWO ext) +{ + struct cpuBfData bf_data; + cpuBfExtWord(&bf_data, val, FALSE, has_ea, ext); + bf_data.field = cpuGetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field_mask); + cpuSetFlagsNZVC(bf_data.field == 0, bf_data.field & (1 << (bf_data.width - 1)), FALSE, FALSE); + bf_data.field = bf_data.field_mask; + cpuSetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field, bf_data.field_mask); + if (has_ea) + { + cpuSetBfEaBytes(&bf_data.b[0], bf_data.base_address, bf_data.byte_count); + } + else + { + cpuSetBfRegBytes(&bf_data.b[0], val); + } +} + +/// +/// bfset dx {offset:width} +/// +static void cpuBfSetReg(ULO regno, UWO ext) +{ + cpuBfSetCommon(regno, FALSE, ext); +} + +/// +/// bfset ea {offset:width} +/// +static void cpuBfSetEa(ULO ea, UWO ext) +{ + cpuBfSetCommon(ea, TRUE, ext); +} + +/// +/// bftst common logic +/// +static void cpuBfTstCommon(ULO val, BOOLE has_ea, UWO ext) +{ + struct cpuBfData bf_data; + cpuBfExtWord(&bf_data, val, FALSE, has_ea, ext); + bf_data.field = cpuGetBfField(&bf_data.b[0], bf_data.end_offset, bf_data.byte_count, bf_data.field_mask); + cpuSetFlagsNZVC(bf_data.field == 0, bf_data.field & (1 << (bf_data.width - 1)), FALSE, FALSE); +} + +/// +/// bftst dx {offset:width} +/// +static void cpuBfTstReg(ULO regno, UWO ext) +{ + cpuBfTstCommon(regno, FALSE, ext); +} + +/// +/// bftst ea {offset:width} +/// +static void cpuBfTstEa(ULO ea, UWO ext) +{ + cpuBfTstCommon(ea, TRUE, ext); +} + +/// +/// movep.w (d16, Ay), Dx +/// +static void cpuMovepWReg(ULO areg, ULO dreg) +{ + ULO ea = cpuGetAReg(areg) + cpuGetNextWordSignExt(); + memoryWriteByte((UBY) (cpuGetDReg(dreg) >> 8), ea); + memoryWriteByte(cpuGetDRegByte(dreg), ea + 2); + cpuSetInstructionTime(16); +} + +/// +/// movep.l (d16, Ay), Dx +/// +static void cpuMovepLReg(ULO areg, ULO dreg) +{ + ULO ea = cpuGetAReg(areg) + cpuGetNextWordSignExt(); + memoryWriteByte((UBY)(cpuGetDReg(dreg) >> 24), ea); + memoryWriteByte((UBY)(cpuGetDReg(dreg) >> 16), ea + 2); + memoryWriteByte((UBY)(cpuGetDReg(dreg) >> 8), ea + 4); + memoryWriteByte(cpuGetDRegByte(dreg), ea + 6); + cpuSetInstructionTime(24); +} + +/// +/// movep.w Dx, (d16, Ay) +/// +static void cpuMovepWEa(ULO areg, ULO dreg) +{ + ULO ea = cpuGetAReg(areg) + cpuGetNextWordSignExt(); + cpuSetDRegWord(dreg, cpuJoinByteToWord(memoryReadByte(ea), memoryReadByte(ea + 2))); + cpuSetInstructionTime(16); +} + +/// +/// movep.l Dx, (d16, Ay) +/// +static void cpuMovepLEa(ULO areg, ULO dreg) +{ + ULO ea = cpuGetAReg(areg) + cpuGetNextWordSignExt(); + cpuSetDReg(dreg, cpuJoinByteToLong(memoryReadByte(ea), memoryReadByte(ea + 2), memoryReadByte(ea + 4), memoryReadByte(ea + 6))); + cpuSetInstructionTime(24); +} + +/// +/// pack Dx, Dy, #adjustment +/// +static void cpuPackReg(ULO yreg, ULO xreg) +{ + UWO adjustment = cpuGetNextWord(); + UWO src = cpuGetDRegWord(xreg) + adjustment; + cpuSetDRegByte(yreg, (UBY) (((src >> 4) & 0xf0) | (src & 0xf))); + cpuSetInstructionTime(4); +} + +/// +/// pack -(Ax), -(Ay), #adjustment +/// +static void cpuPackEa(ULO yreg, ULO xreg) +{ + UWO adjustment = cpuGetNextWord(); + UBY b1 = memoryReadByte(cpuEA04(xreg, 1)); + UBY b2 = memoryReadByte(cpuEA04(xreg, 1)); + UWO result = ((((UWO)b1) << 8) | (UWO) b2) + adjustment; + memoryWriteByte((UBY) (((result >> 4) & 0xf0) | (result & 0xf)), cpuEA04(yreg, 1)); + cpuSetInstructionTime(4); +} + +/// +/// unpk Dx, Dy, #adjustment +/// +static void cpuUnpkReg(ULO yreg, ULO xreg) +{ + UWO adjustment = cpuGetNextWord(); + UBY b1 = cpuGetDRegByte(xreg); + UWO result = ((((UWO)(b1 & 0xf0)) << 4) | ((UWO)(b1 & 0xf))) + adjustment; + cpuSetDRegWord(yreg, result); + cpuSetInstructionTime(4); +} + +/// +/// unpk -(Ax), -(Ay), #adjustment +/// +static void cpuUnpkEa(ULO yreg, ULO xreg) +{ + UWO adjustment = cpuGetNextWord(); + UBY b1 = memoryReadByte(cpuEA04(xreg, 1)); + UWO result = ((((UWO)(b1 & 0xf0)) << 4) | ((UWO)(b1 & 0xf))) + adjustment; + memoryWriteByte((UBY) (result >> 8), cpuEA04(yreg, 1)); + memoryWriteByte((UBY) result, cpuEA04(yreg, 1)); + cpuSetInstructionTime(4); +} + +/// +/// movec +/// +static void cpuMoveCFrom() +{ + if (cpuGetFlagSupervisor()) + { + UWO extension = (UWO) cpuGetNextWord(); + ULO da = (extension >> 15) & 1; + ULO regno = (extension >> 12) & 7; + ULO ctrl_regno = extension & 0xfff; + if (cpuGetModelMajor() == 1) + { + switch (ctrl_regno) + { + case 0x000: cpuSetReg(da, regno, cpuGetSfc()); break; + case 0x001: cpuSetReg(da, regno, cpuGetDfc()); break; + case 0x800: cpuSetReg(da, regno, cpuGetUspDirect()); break; // In supervisor mode, usp is up to date. + case 0x801: cpuSetReg(da, regno, cpuGetVbr()); break; + default: cpuThrowIllegalInstructionException(FALSE); return; // Illegal instruction + } + } + else if (cpuGetModelMajor() == 2) + { + switch (ctrl_regno) + { + case 0x000: cpuSetReg(da, regno, cpuGetSfc()); break; + case 0x001: cpuSetReg(da, regno, cpuGetDfc()); break; + case 0x002: cpuSetReg(da, regno, cpuGetCacr() & 3); break; + case 0x800: cpuSetReg(da, regno, cpuGetUspDirect()); break; // In supervisor mode, usp is up to date. + case 0x801: cpuSetReg(da, regno, cpuGetVbr()); break; + case 0x802: cpuSetReg(da, regno, cpuGetCaar() & 0xfc); break; + case 0x803: cpuSetReg(da, regno, cpuGetMspAutoMap()); break; + case 0x804: cpuSetReg(da, regno, cpuGetIspAutoMap()); break; + default: cpuThrowIllegalInstructionException(FALSE); return; // Illegal instruction + } + } + else if (cpuGetModelMajor() == 3) + { + switch (ctrl_regno) + { + case 0x000: cpuSetReg(da, regno, cpuGetSfc()); break; + case 0x001: cpuSetReg(da, regno, cpuGetDfc()); break; + case 0x002: cpuSetReg(da, regno, cpuGetCacr()); break; + case 0x800: cpuSetReg(da, regno, cpuGetUspDirect()); break; // In supervisor mode, usp is up to date. + case 0x801: cpuSetReg(da, regno, cpuGetVbr()); break; + case 0x802: cpuSetReg(da, regno, cpuGetCaar() & 0xfc); break; + case 0x803: cpuSetReg(da, regno, cpuGetMspAutoMap()); break; + case 0x804: cpuSetReg(da, regno, cpuGetIspAutoMap()); break; + default: cpuThrowIllegalInstructionException(FALSE); return; // Illegal instruction + } + } + } + else + { + cpuThrowPrivilegeViolationException(); + return; + } + cpuSetInstructionTime(4); +} + +/// +/// movec +/// +static void cpuMoveCTo() +{ + if (cpuGetFlagSupervisor()) + { + UWO extension = (UWO) cpuGetNextWord(); + ULO da = (extension >> 15) & 1; + ULO regno = (extension >> 12) & 7; + ULO ctrl_regno = extension & 0xfff; + if (cpuGetModelMajor() == 1) + { + switch (ctrl_regno) + { + case 0x000: cpuSetSfc(cpuGetReg(da, regno) & 7); break; + case 0x001: cpuSetDfc(cpuGetReg(da, regno) & 7); break; + case 0x800: cpuSetUspDirect(cpuGetReg(da, regno)); break; + case 0x801: cpuSetVbr(cpuGetReg(da, regno)); break; + default: cpuThrowIllegalInstructionException(FALSE); return; // Illegal instruction + } + } + else if (cpuGetModelMajor() == 2) + { + switch (ctrl_regno) + { + case 0x000: cpuSetSfc(cpuGetReg(da, regno) & 7); break; + case 0x001: cpuSetDfc(cpuGetReg(da, regno) & 7); break; + case 0x002: cpuSetCacr(cpuGetReg(da, regno) & 0x3); break; + case 0x800: cpuSetUspDirect(cpuGetReg(da, regno)); break; + case 0x801: cpuSetVbr(cpuGetReg(da, regno)); break; + case 0x802: cpuSetCaar(cpuGetReg(da, regno) & 0x00fc); break; + case 0x803: cpuSetMspAutoMap(cpuGetReg(da, regno)); break; + case 0x804: cpuSetIspAutoMap(cpuGetReg(da, regno)); break; + default: cpuThrowIllegalInstructionException(FALSE); return; // Illegal instruction + } + } + else if (cpuGetModelMajor() == 3) + { + switch (ctrl_regno) + { + case 0x000: cpuSetSfc(cpuGetReg(da, regno) & 7); break; + case 0x001: cpuSetDfc(cpuGetReg(da, regno) & 7); break; + case 0x002: cpuSetCacr(cpuGetReg(da, regno) & 0x3313); break; + case 0x800: cpuSetUspDirect(cpuGetReg(da, regno)); break; + case 0x801: cpuSetVbr(cpuGetReg(da, regno)); break; + case 0x802: cpuSetCaar(cpuGetReg(da, regno) & 0x00fc); break; + case 0x803: cpuSetMspAutoMap(cpuGetReg(da, regno)); break; + case 0x804: cpuSetIspAutoMap(cpuGetReg(da, regno)); break; + default: cpuThrowIllegalInstructionException(FALSE); return; // Illegal instruction + } + } + } + else + { + cpuThrowPrivilegeViolationException(); + return; + } + cpuSetInstructionTime(4); +} + +/// +/// moves.b Rn, ea / moves.b ea, Rn +/// +static void cpuMoveSB(ULO ea, UWO extension) +{ + if (cpuGetFlagSupervisor()) + { + ULO da = (extension >> 15) & 1; + ULO regno = (extension >> 12) & 7; + if (extension & 0x0800) // From Rn to ea (in dfc) + { + memoryWriteByte((UBY)cpuGetReg(da, regno), ea); + } + else // From ea to Rn (in sfc) + { + UBY data = memoryReadByte(ea); + if (da == 0) + { + cpuSetDRegByte(regno, data); + } + else + { + cpuSetAReg(regno, (ULO)(LON)(BYT) data); + } + } + } + else + { + cpuThrowPrivilegeViolationException(); + return; + } + cpuSetInstructionTime(4); +} + +/// +/// moves.w Rn, ea / moves.w ea, Rn +/// +static void cpuMoveSW(ULO ea, UWO extension) +{ + if (cpuGetFlagSupervisor()) + { + ULO da = (extension >> 15) & 1; + ULO regno = (extension >> 12) & 7; + if (extension & 0x0800) // From Rn to ea (in dfc) + { + memoryWriteWord((UWO)cpuGetReg(da, regno), ea); + } + else // From ea to Rn (in sfc) + { + UWO data = memoryReadWord(ea); + if (da == 0) + { + cpuSetDRegWord(regno, data); + } + else + { + cpuSetAReg(regno, (ULO)(LON)(WOR) data); + } + } + } + else + { + cpuThrowPrivilegeViolationException(); + return; + } + cpuSetInstructionTime(4); +} + +/// +/// moves.l Rn, ea / moves.l ea, Rn +/// +static void cpuMoveSL(ULO ea, UWO extension) +{ + if (cpuGetFlagSupervisor()) + { + ULO da = (extension >> 15) & 1; + ULO regno = (extension >> 12) & 7; + if (extension & 0x0800) // From Rn to ea (in dfc) + { + memoryWriteLong(cpuGetReg(da, regno), ea); + } + else // From ea to Rn (in sfc) + { + cpuSetDReg(regno, memoryReadLong(ea)); + } + } + else + { + cpuThrowPrivilegeViolationException(); + return; + } + cpuSetInstructionTime(4); +} + +/// +/// Trapcc +/// +static void cpuTrapcc(ULO cc) +{ + if (cc) + { + cpuThrowTrapVException(); // TrapV and Trapcc share the exception vector + return; + } + cpuSetInstructionTime(4); +} + +/// +/// Trapcc.w # +/// +static void cpuTrapccW(ULO cc) +{ + cpuGetNextWord(); + if (cc) + { + cpuThrowTrapVException(); // TrapV and Trapcc share the exception vector + return; + } + cpuSetInstructionTime(4); +} + +/// +/// trapcc.l # +/// +static void cpuTrapccL(ULO cc) +{ + cpuGetNextLong(); + if (cc) + { + cpuThrowTrapVException(); // TrapV and Trapcc share the exception vector + return; + } + cpuSetInstructionTime(4); +} + +/// +/// cas.b Dc,Du, ea +/// +static void cpuCasB(ULO ea, UWO extension) +{ + UBY dst = memoryReadByte(ea); + ULO cmp_regno = extension & 7; + UBY res = dst - cpuGetDRegByte(cmp_regno); + + cpuSetFlagsCmp(cpuIsZeroB(res), cpuMsbB(res), cpuMsbB(dst), cpuMsbB(cpuGetDRegByte(cmp_regno))); + + if (cpuIsZeroB(res)) + { + memoryWriteByte(cpuGetDRegByte((extension >> 6) & 7), ea); + } + else + { + cpuSetDRegByte(cmp_regno, dst); + } + cpuSetInstructionTime(4); +} + +/// +/// cas.w Dc,Du, ea +/// +static void cpuCasW(ULO ea, UWO extension) +{ + UWO dst = memoryReadWord(ea); + ULO cmp_regno = extension & 7; + UWO res = dst - cpuGetDRegWord(cmp_regno); + + cpuSetFlagsCmp(cpuIsZeroW(res), cpuMsbW(res), cpuMsbW(dst), cpuMsbW(cpuGetDRegWord(cmp_regno))); + + if (cpuIsZeroW(res)) + { + memoryWriteWord(cpuGetDRegWord((extension >> 6) & 7), ea); + } + else + { + cpuSetDRegWord(cmp_regno, dst); + } + cpuSetInstructionTime(4); +} + +/// +/// cas.l Dc,Du, ea +/// +static void cpuCasL(ULO ea, UWO extension) +{ + ULO dst = memoryReadLong(ea); + ULO cmp_regno = extension & 7; + ULO res = dst - cpuGetDReg(cmp_regno); + + cpuSetFlagsCmp(cpuIsZeroL(res), cpuMsbL(res), cpuMsbL(dst), cpuMsbL(cpuGetDReg(cmp_regno))); + + if (cpuIsZeroL(res)) + { + memoryWriteLong(cpuGetDReg((extension >> 6) & 7), ea); + } + else + { + cpuSetDReg(cmp_regno, dst); + } + cpuSetInstructionTime(4); +} + +/// +/// cas2.w Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) +/// +static void cpuCas2W() +{ + UWO extension1 = cpuGetNextWord(); + UWO extension2 = cpuGetNextWord(); + ULO ea1 = cpuGetReg(extension1 >> 15, (extension1 >> 12) & 7); + ULO ea2 = cpuGetReg(extension2 >> 15, (extension2 >> 12) & 7); + UWO dst1 = memoryReadWord(ea1); + UWO dst2 = memoryReadWord(ea2); + ULO cmp1_regno = extension1 & 7; + ULO cmp2_regno = extension2 & 7; + UWO res1 = dst1 - cpuGetDRegWord(cmp1_regno); + UWO res2 = dst2 - cpuGetDRegWord(cmp2_regno); + + if (cpuIsZeroW(res1)) + { + cpuSetFlagsCmp(cpuIsZeroW(res2), cpuMsbW(res2), cpuMsbW(dst2), cpuMsbW(cpuGetDRegWord(cmp2_regno))); + } + else + { + cpuSetFlagsCmp(cpuIsZeroW(res1), cpuMsbW(res1), cpuMsbW(dst1), cpuMsbW(cpuGetDRegWord(cmp1_regno))); + } + + if (cpuIsZeroW(res1) && cpuIsZeroW(res2)) + { + memoryWriteWord(cpuGetDRegWord((extension1 >> 6) & 7), ea1); + memoryWriteWord(cpuGetDRegWord((extension2 >> 6) & 7), ea2); + } + else + { + cpuSetDRegWord(cmp1_regno, dst1); + cpuSetDRegWord(cmp2_regno, dst2); + } + cpuSetInstructionTime(4); +} + +/// +/// cas2.l Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) +/// +static void cpuCas2L() +{ + UWO extension1 = cpuGetNextWord(); + UWO extension2 = cpuGetNextWord(); + ULO ea1 = cpuGetReg(extension1 >> 15, (extension1 >> 12) & 7); + ULO ea2 = cpuGetReg(extension2 >> 15, (extension2 >> 12) & 7); + ULO dst1 = memoryReadLong(ea1); + ULO dst2 = memoryReadLong(ea2); + ULO cmp1_regno = extension1 & 7; + ULO cmp2_regno = extension2 & 7; + ULO res1 = dst1 - cpuGetDReg(cmp1_regno); + ULO res2 = dst2 - cpuGetDReg(cmp2_regno); + + if (cpuIsZeroL(res1)) + { + cpuSetFlagsCmp(cpuIsZeroL(res2), cpuMsbL(res2), cpuMsbL(dst2), cpuMsbL(cpuGetDReg(cmp2_regno))); + } + else + { + cpuSetFlagsCmp(cpuIsZeroL(res1), cpuMsbL(res1), cpuMsbL(dst1), cpuMsbL(cpuGetDReg(cmp1_regno))); + } + + if (cpuIsZeroL(res1) && cpuIsZeroL(res2)) + { + memoryWriteLong(cpuGetDReg((extension1 >> 6) & 7), ea1); + memoryWriteLong(cpuGetDReg((extension2 >> 6) & 7), ea2); + } + else + { + cpuSetDReg(cmp1_regno, dst1); + cpuSetDReg(cmp2_regno, dst2); + } + cpuSetInstructionTime(4); +} + +/// +/// Common code for chk2 ea, Rn / cmp2 ea, Rn +/// +static void cpuChkCmp(ULO lb, ULO ub, ULO val, BOOLE is_chk2) +{ + BOOLE z = (val == lb || val == ub); + BOOLE c = ((lb <= ub) && (val < lb || val > ub)) || ((lb > ub) && (val < lb) && (val > ub)); + cpuSetFlagZ(z); + cpuSetFlagC(c); + cpuSetInstructionTime(4); + if (is_chk2 && c) + { + cpuThrowChkException(); + } +} + +/// +/// chk2.b ea, Rn / cmp2.b ea, Rn +/// +static void cpuChkCmp2B(ULO ea, UWO extension) +{ + ULO da = (ULO) (extension >> 15); + ULO rn = (ULO) (extension >> 12) & 7; + BOOLE is_chk2 = (extension & 0x0800); + if (da == 1) + { + cpuChkCmp((ULO)(LON)(BYT)memoryReadByte(ea), (ULO)(LON)(BYT)memoryReadByte(ea + 1), cpuGetAReg(rn), is_chk2); + } + else + { + cpuChkCmp((ULO)memoryReadByte(ea), (ULO)memoryReadByte(ea + 1), (ULO)(UBY)cpuGetDReg(rn), is_chk2); + } +} + +/// +/// chk2.w ea, Rn / cmp2.w ea, Rn +/// +static void cpuChkCmp2W(ULO ea, UWO extension) +{ + ULO da = (ULO) (extension >> 15); + ULO rn = (ULO) (extension >> 12) & 7; + BOOLE is_chk2 = (extension & 0x0800); + if (da == 1) + { + cpuChkCmp((ULO)(LON)(WOR)memoryReadWord(ea), (ULO)(LON)(WOR)memoryReadWord(ea + 1), cpuGetAReg(rn), is_chk2); + } + else + { + cpuChkCmp((ULO)memoryReadWord(ea), (ULO)memoryReadWord(ea + 2), (ULO)(UWO)cpuGetDReg(rn), is_chk2); + } +} + +/// +/// chk2.l ea, Rn / cmp2.l ea, Rn +/// +static void cpuChkCmp2L(ULO ea, UWO extension) +{ + ULO da = (ULO) (extension >> 15); + ULO rn = (ULO) (extension >> 12) & 7; + BOOLE is_chk2 = (extension & 0x0800); + cpuChkCmp(memoryReadLong(ea), memoryReadLong(ea + 4), cpuGetReg(da, rn), is_chk2); +} + +/// +/// callm +/// Since this is a coprocessor instruction, this is NOP. +/// This will likely fail, but anything we do here will be wrong anyhow. +/// +static void cpuCallm(ULO ea, UWO extension) +{ + cpuSetInstructionTime(4); +} + +/// +/// rtm +/// Since this is a coprocessor instruction, this is NOP. +/// This will likely fail, but anything we do here will be wrong anyhow. +/// +static void cpuRtm(ULO da, ULO regno) +{ + cpuSetInstructionTime(4); +} + +/// +/// 68030 version only. +/// +/// Extension word: 001xxx00xxxxxxxx +/// pflusha +/// pflush fc, mask +/// pflush fc, mask, ea +/// +/// Extension word: 001000x0000xxxxx +/// ploadr fc, ea +/// ploadw fc, ea +/// +/// Extension word: 010xxxxx00000000 (SRp, CRP, TC) +/// Extension word: 011000x000000000 (MMU status register) +/// Extension word: 000xxxxx00000000 (TT) +/// pmove mrn, ea +/// pmove ea, mrn +/// pmovefd ea, mrn +/// +/// Extension word: 100xxxxxxxxxxxxx +/// ptestr fc, ea, #level +/// ptestr fc, ea, #level, An +/// ptestw fc, ea, #level +/// ptestw fc, ea, #level, An +/// +/// Since this is a coprocessor instruction, this is NOP. +/// +static void cpuPflush030(ULO ea, UWO extension) +{ + if (cpuGetFlagSupervisor()) + { + if ((extension & 0xfde0) == 0x2000) + { + // ploadr, ploadw + } + else if ((extension & 0xe300) == 0x2000) + { + // pflusha, pflush + ULO mode = (extension >> 10) & 7; + ULO mask = (extension >> 5) & 7; + ULO fc = extension & 0x1f; + } + } + else + { + cpuThrowPrivilegeViolationException(); + return; + } + cpuSetInstructionTime(4); +} + +/// +/// pflusha +/// pflush fc, mask +/// pflush fc, mask, ea +/// +/// 68040 version only. +/// +/// Since this is a coprocessor instruction, this is NOP. +/// +static void cpuPflush040(ULO opmode, ULO regno) +{ + if (cpuGetFlagSupervisor()) + { + if (cpuGetModelMajor() != 2) // This is NOP on 68EC040 + { + switch (opmode) + { + case 0: //PFLUSHN (An) + break; + case 1: //PFLUSH (An) + break; + case 2: //PFLUSHAN + break; + case 3: //PFLUSHA + break; + } + } + } + else + { + cpuThrowPrivilegeViolationException(); + return; + } + cpuSetInstructionTime(4); +} + +/// +/// ptestr (An) +/// ptestw (An) +/// +/// 68040 version only. +/// +/// Since this is a coprocessor instruction, this is NOP. +/// +static void cpuPtest040(ULO rw, ULO regno) +{ + if (cpuGetFlagSupervisor()) + { + if (cpuGetModelMajor() != 2) // This is NOP on 68EC040 + { + if (rw == 0) + { + // ptestr + } + else + { + // ptestw + } + } + } + else + { + cpuThrowPrivilegeViolationException(); + return; + } + cpuSetInstructionTime(4); +} + +#include "CpuModule_Decl.h" +#include "CpuModule_Data.h" +#include "CpuModule_Profile.h" +#include "CpuModule_Code.h" + +cpuOpcodeData cpu_opcode_data_current[65536]; + +void cpuMakeOpcodeTableForModel(void) +{ + ULO opcode; + for (opcode = 0; opcode < 65536; opcode++) + { + if (cpu_opcode_model_mask[opcode] & cpuGetModelMask()) + { + cpu_opcode_data_current[opcode] = cpu_opcode_data[opcode]; + } + else + { + cpu_opcode_data_current[opcode].instruction_func = cpuIllegalInstruction; + cpu_opcode_data_current[opcode].data[0] = 0; + cpu_opcode_data_current[opcode].data[1] = 0; + cpu_opcode_data_current[opcode].data[2] = 0; + } + } +} + +ULO cpuExecuteInstruction(void) +{ + if (cpuGetRaiseInterrupt()) + { + cpuSetUpInterrupt(); + cpuCheckPendingInterrupts(); + return 44; + } + else + { + ULO oldSr = cpuGetSR(); + UWO opcode; + +#ifdef CPU_INSTRUCTION_LOGGING + cpuCallInstructionLoggingFunc(); +#endif + + cpuSetOriginalPC(cpuGetPC()); // Store pc and opcode for exception logging + opcode = cpuGetNextWord(); + +#ifdef CPU_INSTRUCTION_LOGGING + cpuSetCurrentOpcode(opcode); +#endif + + cpuSetInstructionTime(0); + + cpu_opcode_data_current[opcode].instruction_func( + cpu_opcode_data_current[opcode].data); + if (oldSr & 0xc000) + { + // This instruction was traced + ULO cycles = cpuGetInstructionTime(); + cpuThrowTraceException(); + cpuSetInstructionTime(cpuGetInstructionTime() + cycles); + } + return cpuGetInstructionTime(); + } +} diff --git a/cpu/CpuModule_Internal.h b/cpu/CpuModule_Internal.h new file mode 100644 index 0000000..3fab76f --- /dev/null +++ b/cpu/CpuModule_Internal.h @@ -0,0 +1,200 @@ +#ifndef CpuModule_Internal_H +#define CpuModule_Internal_H + +// This header file defines the internal interfaces of the CPU module. +extern void cpuMakeOpcodeTableForModel(void); +extern void cpuCreateMulTimeTables(void); + +// StackFrameGen +extern void cpuStackFrameGenerate(UWO vector_no, ULO pc); +extern void cpuStackFrameInit(void); + +// Registers +extern ULO cpu_sr; // Not static because the flags calculation uses it extensively +extern BOOLE cpuGetFlagSupervisor(void); +extern BOOLE cpuGetFlagMaster(void); +extern void cpuSetUspDirect(ULO usp); +extern ULO cpuGetUspDirect(void); +extern ULO cpuGetUspAutoMap(void); +extern void cpuSetSspDirect(ULO ssp); +extern ULO cpuGetSspDirect(void); +extern ULO cpuGetSspAutoMap(void); +extern void cpuSetMspDirect(ULO msp); +extern ULO cpuGetMspDirect(void); +extern ULO cpuGetMspAutoMap(void); +extern void cpuSetMspAutoMap(ULO new_msp); +extern ULO cpuGetIspAutoMap(void); +extern void cpuSetIspAutoMap(ULO new_isp); +extern void cpuSetDReg(ULO i, ULO value); +extern ULO cpuGetDReg(ULO i); +extern void cpuSetAReg(ULO i, ULO value); +extern ULO cpuGetAReg(ULO i); +extern void cpuSetReg(ULO da, ULO i, ULO value); +extern ULO cpuGetReg(ULO da, ULO i); +extern void cpuSetPC(ULO address); +extern ULO cpuGetPC(void); +extern void cpuSetStop(BOOLE stop); +extern BOOLE cpuGetStop(void); +extern void cpuSetVbr(ULO vbr); +extern ULO cpuGetVbr(void); +extern void cpuSetSfc(ULO sfc); +extern ULO cpuGetSfc(void); +extern void cpuSetDfc(ULO dfc); +extern ULO cpuGetDfc(void); +extern void cpuSetCacr(ULO cacr); +extern ULO cpuGetCacr(void); +extern void cpuSetCaar(ULO caar); +extern ULO cpuGetCaar(void); +extern void cpuSetSR(ULO sr); +extern ULO cpuGetSR(void); +extern void cpuSetIrqLevel(ULO irq_level); +extern ULO cpuGetIrqLevel(void); +extern void cpuSetIrqAddress(ULO irq_address); +extern ULO cpuGetIrqAddress(void); +extern void cpuSetInstructionTime(ULO cycles); +extern ULO cpuGetInstructionTime(void); +extern void cpuSetOriginalPC(ULO pc); +extern ULO cpuGetOriginalPC(void); + +#ifdef CPU_INSTRUCTION_LOGGING + +extern void cpuSetCurrentOpcode(UWO opcode); +extern UWO cpuGetCurrentOpcode(void); + +#endif + +extern void cpuProfileWrite(void); + +extern void cpuSetModelMask(UBY model_mask); +extern UBY cpuGetModelMask(void); +extern void cpuSetDRegWord(ULO regno, UWO val); +extern void cpuSetDRegByte(ULO regno, UBY val); +extern UWO cpuGetRegWord(ULO i, ULO regno); +extern UWO cpuGetDRegWord(ULO regno); +extern UBY cpuGetDRegByte(ULO regno); +extern ULO cpuGetDRegWordSignExtLong(ULO regno); +extern UWO cpuGetDRegByteSignExtWord(ULO regno); +extern ULO cpuGetDRegByteSignExtLong(ULO regno); +extern UWO cpuGetARegWord(ULO regno); +extern UBY cpuGetARegByte(ULO regno); + +extern UWO cpuGetNextWord(void); +extern ULO cpuGetNextWordSignExt(void); +extern ULO cpuGetNextLong(void); +extern void cpuSkipNextWord(void); +extern void cpuSkipNextLong(void); +extern void cpuClearPrefetch(void); +extern void cpuValidateReadPointer(void); + +extern void cpuInitializeFromNewPC(ULO new_pc); + +// Effective address +extern ULO cpuEA02(ULO regno); +extern ULO cpuEA03(ULO regno, ULO size); +extern ULO cpuEA04(ULO regno, ULO size); +extern ULO cpuEA05(ULO regno); +extern ULO cpuEA06(ULO regno); +extern ULO cpuEA70(void); +extern ULO cpuEA71(void); +extern ULO cpuEA72(void); +extern ULO cpuEA73(void); + +// Flags +extern void cpuSetFlagsAdd(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm); +extern void cpuSetFlagsSub(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm); +extern void cpuSetFlagsCmp(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm); +extern void cpuSetZFlagBitOpsB(UBY res); +extern void cpuSetZFlagBitOpsL(ULO res); + +extern void cpuSetFlagsNZ00NewB(UBY res); +extern void cpuSetFlagsNZ00NewW(UWO res); +extern void cpuSetFlagsNZ00NewL(ULO res); +extern void cpuSetFlagsNZ00New64(LLO res); + +extern void cpuSetFlagZ(BOOLE f); +extern void cpuSetFlagN(BOOLE f); +extern void cpuSetFlagV(BOOLE f); +extern void cpuSetFlagC(BOOLE f); +extern void cpuSetFlagXC(BOOLE f); +extern void cpuSetFlags0100(void); +extern void cpuSetFlagsNeg(BOOLE z, BOOLE rm, BOOLE dm); +extern BOOLE cpuGetFlagX(void); +extern void cpuSetFlagsNegx(BOOLE z, BOOLE rm, BOOLE dm); +extern BOOLE cpuGetFlagV(void); +extern void cpuSetFlagsNZVC(BOOLE z, BOOLE n, BOOLE v, BOOLE c); +extern void cpuSetFlagsVC(BOOLE v, BOOLE c); +extern void cpuSetFlagsShiftZero(BOOLE z, BOOLE rm); +extern void cpuSetFlagsShift(BOOLE z, BOOLE rm, BOOLE c, BOOLE v); +extern void cpuSetFlagsRotate(BOOLE z, BOOLE rm, BOOLE c); +extern void cpuSetFlagsRotateX(UWO z, UWO rm, UWO x); +extern void cpuSetFlagsAddX(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm); +extern void cpuSetFlagsSubX(BOOLE z, BOOLE rm, BOOLE dm, BOOLE sm); +extern void cpuSetFlagsAbs(UWO f); +extern UWO cpuGetZFlagB(UBY res); +extern UWO cpuGetZFlagW(UWO res); +extern UWO cpuGetZFlagL(ULO res); +extern UWO cpuGetNFlagB(UBY res); +extern UWO cpuGetNFlagW(UWO res); +extern UWO cpuGetNFlagL(ULO res); + +extern BOOLE cpuCalculateConditionCode0(void); +extern BOOLE cpuCalculateConditionCode1(void); +extern BOOLE cpuCalculateConditionCode2(void); +extern BOOLE cpuCalculateConditionCode3(void); +extern BOOLE cpuCalculateConditionCode4(void); +extern BOOLE cpuCalculateConditionCode5(void); +extern BOOLE cpuCalculateConditionCode6(void); +extern BOOLE cpuCalculateConditionCode7(void); +extern BOOLE cpuCalculateConditionCode8(void); +extern BOOLE cpuCalculateConditionCode9(void); +extern BOOLE cpuCalculateConditionCode10(void); +extern BOOLE cpuCalculateConditionCode11(void); +extern BOOLE cpuCalculateConditionCode12(void); +extern BOOLE cpuCalculateConditionCode13(void); +extern BOOLE cpuCalculateConditionCode14(void); +extern BOOLE cpuCalculateConditionCode15(void); +extern BOOLE cpuCalculateConditionCode(ULO cc); + +// Logging +#ifdef CPU_INSTRUCTION_LOGGING +extern void cpuCallInstructionLoggingFunc(void); +extern void cpuCallExceptionLoggingFunc(STR *description, ULO original_pc, UWO opcode); +extern void cpuCallInterruptLoggingFunc(ULO level, ULO vector_address); +#endif + +// Interrupt +extern void cpuCallCheckPendingInterruptsFunc(void); +extern ULO cpuActivateSSP(void); +extern void cpuSetRaiseInterrupt(BOOLE raise_irq); +extern BOOLE cpuGetRaiseInterrupt(void); + +// Exceptions +extern void cpuThrowPrivilegeViolationException(void); +extern void cpuThrowIllegalInstructionException(BOOLE executejmp); +extern void cpuThrowFLineException(void); +extern void cpuThrowALineException(void); +extern void cpuThrowTrapVException(void); +extern void cpuThrowTrapException(ULO vector_no); +extern void cpuThrowDivisionByZeroException(BOOLE executejmp); +extern void cpuThrowChkException(void); +extern void cpuThrowTraceException(void); +extern void cpuThrowResetException(void); +extern void cpuCallResetExceptionFunc(void); +extern void cpuFrame1(UWO vector_offset, ULO pc); + +// Private help functions +static ULO cpuSignExtByteToLong(UBY v) {return (ULO)(LON)(BYT) v;} +static UWO cpuSignExtByteToWord(UBY v) {return (UWO)(WOR)(BYT) v;} +static ULO cpuSignExtWordToLong(UWO v) {return (ULO)(LON)(WOR) v;} +static ULO cpuJoinWordToLong(UWO upper, UWO lower) {return (((ULO)upper) << 16) | ((ULO)lower);} +static ULO cpuJoinByteToLong(UBY upper, UBY midh, UBY midl, UBY lower) {return (((ULO)upper) << 24) | (((ULO)midh) << 16) | (((ULO)midl) << 8) | ((ULO)lower);} +static UWO cpuJoinByteToWord(UBY upper, UBY lower) {return (((UWO)upper) << 8) | ((UWO)lower);} +static BOOLE cpuMsbB(UBY v) {return v>>7;} +static BOOLE cpuMsbW(UWO v) {return v>>15;} +static BOOLE cpuMsbL(ULO v) {return v>>31;} +static BOOLE cpuIsZeroB(UBY v) {return v == 0;} +static BOOLE cpuIsZeroW(UWO v) {return v == 0;} +static BOOLE cpuIsZeroL(ULO v) {return v == 0;} + + +#endif \ No newline at end of file diff --git a/cpu/CpuModule_InternalState.c b/cpu/CpuModule_InternalState.c new file mode 100644 index 0000000..2fba027 --- /dev/null +++ b/cpu/CpuModule_InternalState.c @@ -0,0 +1,390 @@ +/* @(#) $Id: CpuModule_InternalState.c,v 1.9 2012/08/12 16:51:02 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* 68000 internal state */ +/* */ +/* Author: Petter Schau */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ +#include "defs.h" +#include "CpuModule.h" +#include "fellow.h" +#include "fmem.h" +#include "CpuModule_Internal.h" + +/* M68k registers */ +static ULO cpu_regs[2][8]; /* 0 - data, 1 - address */ +static ULO cpu_pc; +static ULO cpu_usp; +static ULO cpu_ssp; +static ULO cpu_msp; +static ULO cpu_sfc; +static ULO cpu_dfc; +ULO cpu_sr; // Not static because flags calculation use it extensively +static ULO cpu_vbr; +static UWO cpu_prefetch_word; +static ULO cpu_cacr; +static ULO cpu_caar; + +/* Irq management */ +static BOOLE cpu_raise_irq; +static ULO cpu_irq_level; +static ULO cpu_irq_address; + +/* Reset values */ +static ULO cpu_initial_pc; +static ULO cpu_initial_sp; + +/* Flag set if CPU is stopped */ +static BOOLE cpu_stop; + +/* The current CPU model */ +static ULO cpu_model_major = -1; +static ULO cpu_model_minor; +static UBY cpu_model_mask; + +/* For exception handling */ +#ifdef CPU_INSTRUCTION_LOGGING + +static UWO cpu_current_opcode; + +#endif + +static ULO cpu_original_pc; + +/* Number of cycles taken by the last intstruction */ +static ULO cpu_instruction_time; + +/* Getters and setters */ + +void cpuSetDReg(ULO i, ULO value) {cpu_regs[0][i] = value;} +ULO cpuGetDReg(ULO i) {return cpu_regs[0][i];} + +void cpuSetAReg(ULO i, ULO value) {cpu_regs[1][i] = value;} +ULO cpuGetAReg(ULO i) {return cpu_regs[1][i];} + +void cpuSetReg(ULO da, ULO i, ULO value) {cpu_regs[da][i] = value;} +ULO cpuGetReg(ULO da, ULO i) {return cpu_regs[da][i];} + +/// +/// Get the supervisor bit from sr. +/// +BOOLE cpuGetFlagSupervisor(void) +{ + return cpu_sr & 0x2000; +} + +/// +/// Get the master/irq state bit from sr. +/// +BOOLE cpuGetFlagMaster(void) +{ + return cpu_sr & 0x1000; +} + +void cpuSetUspDirect(ULO usp) {cpu_usp = usp;} +ULO cpuGetUspDirect(void) {return cpu_usp;} +ULO cpuGetUspAutoMap(void) {return (cpuGetFlagSupervisor()) ? cpuGetUspDirect() : cpuGetAReg(7);} + +void cpuSetSspDirect(ULO ssp) {cpu_ssp = ssp;} +ULO cpuGetSspDirect(void) {return cpu_ssp;} +ULO cpuGetSspAutoMap(void) {return (cpuGetFlagSupervisor()) ? cpuGetAReg(7) : cpuGetSspDirect();} + +void cpuSetMspDirect(ULO msp) {cpu_msp = msp;} +ULO cpuGetMspDirect(void) {return cpu_msp;} + +/// +/// Returns the master stack pointer. +/// +ULO cpuGetMspAutoMap(void) +{ + if (cpuGetFlagSupervisor() && cpuGetFlagMaster()) + { + return cpuGetAReg(7); + } + return cpuGetMspDirect(); +} + +/// +/// Sets the master stack pointer. +/// +void cpuSetMspAutoMap(ULO new_msp) +{ + if (cpuGetFlagSupervisor() && cpuGetFlagMaster()) + { + cpuSetAReg(7, new_msp); + } + else + { + cpuSetMspDirect(new_msp); + } +} + +/// +/// Returns the interrupt stack pointer. ssp is used as isp. +/// +ULO cpuGetIspAutoMap(void) +{ + if (cpuGetFlagSupervisor() && !cpuGetFlagMaster()) + { + return cpuGetAReg(7); + } + return cpuGetSspDirect(); +} + +/// +/// Sets the interrupt stack pointer. ssp is used as isp. +/// +void cpuSetIspAutoMap(ULO new_isp) +{ + if (cpuGetFlagSupervisor() && !cpuGetFlagMaster()) + { + cpuSetAReg(7, new_isp); + } + else + { + cpuSetSspDirect(new_isp); + } +} + +void cpuSetPC(ULO address) {cpu_pc = address;} +ULO cpuGetPC(void) {return cpu_pc;} + +void cpuSetStop(BOOLE stop) {cpu_stop = stop;} +BOOLE cpuGetStop(void) {return cpu_stop;} + +void cpuSetVbr(ULO vbr) {cpu_vbr = vbr;} +ULO cpuGetVbr(void) {return cpu_vbr;} + +void cpuSetSfc(ULO sfc) {cpu_sfc = sfc;} +ULO cpuGetSfc(void) {return cpu_sfc;} + +void cpuSetDfc(ULO dfc) {cpu_dfc = dfc;} +ULO cpuGetDfc(void) {return cpu_dfc;} + +void cpuSetCacr(ULO cacr) {cpu_cacr = cacr;} +ULO cpuGetCacr(void) {return cpu_cacr;} + +void cpuSetCaar(ULO caar) {cpu_caar = caar;} +ULO cpuGetCaar(void) {return cpu_caar;} + +void cpuSetSR(ULO sr) {cpu_sr = sr;} +ULO cpuGetSR(void) {return cpu_sr;} + +void cpuSetIrqLevel(ULO irq_level) {cpu_irq_level = irq_level;} +ULO cpuGetIrqLevel(void) {return cpu_irq_level;} + +void cpuSetIrqAddress(ULO irq_address) {cpu_irq_address = irq_address;} +ULO cpuGetIrqAddress(void) {return cpu_irq_address;} + +void cpuSetInstructionTime(ULO cycles) {cpu_instruction_time = cycles;} +ULO cpuGetInstructionTime(void) {return cpu_instruction_time;} + +void cpuSetOriginalPC(ULO pc) {cpu_original_pc = pc;} +ULO cpuGetOriginalPC(void) {return cpu_original_pc;} + +#ifdef CPU_INSTRUCTION_LOGGING + +void cpuSetCurrentOpcode(UWO opcode) {cpu_current_opcode = opcode;} +UWO cpuGetCurrentOpcode(void) {return cpu_current_opcode;} + +#endif + +void cpuSetRaiseInterrupt(BOOLE raise_irq) {cpu_raise_irq = raise_irq;} +BOOLE cpuGetRaiseInterrupt(void) {return cpu_raise_irq;} + +void cpuSetInitialPC(ULO pc) {cpu_initial_pc = pc;} +ULO cpuGetInitialPC(void) {return cpu_initial_pc;} + +void cpuSetInitialSP(ULO sp) {cpu_initial_sp = sp;} +ULO cpuGetInitialSP(void) {return cpu_initial_sp;} + +void cpuSetModelMask(UBY model_mask) {cpu_model_mask = model_mask;} +UBY cpuGetModelMask(void) {return cpu_model_mask;} + +ULO cpuGetModelMajor(void) {return cpu_model_major;} +ULO cpuGetModelMinor(void) {return cpu_model_minor;} + +static void cpuCalculateModelMask(void) +{ + switch (cpuGetModelMajor()) + { + case 0: + cpuSetModelMask(0x01); + break; + case 1: + cpuSetModelMask(0x02); + break; + case 2: + cpuSetModelMask(0x04); + break; + case 3: + cpuSetModelMask(0x08); + break; + } +} + +void cpuSetModel(ULO major, ULO minor) +{ + BOOLE makeOpcodeTable = (cpu_model_major != major); + cpu_model_major = major; + cpu_model_minor = minor; + cpuCalculateModelMask(); + cpuStackFrameInit(); + if (makeOpcodeTable) cpuMakeOpcodeTableForModel(); +} + +void cpuSetDRegWord(ULO regno, UWO val) {*((WOR*)&cpu_regs[0][regno]) = val;} +void cpuSetDRegByte(ULO regno, UBY val) {*((UBY*)&cpu_regs[0][regno]) = val;} +UWO cpuGetRegWord(ULO i, ULO regno) {return (UWO)cpu_regs[i][regno];} + +UWO cpuGetDRegWord(ULO regno) {return (UWO)cpu_regs[0][regno];} +UBY cpuGetDRegByte(ULO regno) {return (UBY)cpu_regs[0][regno];} + +ULO cpuGetDRegWordSignExtLong(ULO regno) {return cpuSignExtWordToLong(cpuGetDRegWord(regno));} +UWO cpuGetDRegByteSignExtWord(ULO regno) {return cpuSignExtByteToWord(cpuGetDRegByte(regno));} +ULO cpuGetDRegByteSignExtLong(ULO regno) {return cpuSignExtByteToLong(cpuGetDRegByte(regno));} + +UWO cpuGetARegWord(ULO regno) {return (UWO)cpu_regs[1][regno];} +UBY cpuGetARegByte(ULO regno) {return (UBY)cpu_regs[1][regno];} + +typedef UWO (*cpuGetWordFunc)(void); +typedef ULO (*cpuGetLongFunc)(void); + +static UWO cpuGetNextWordInternal(void) +{ + UWO data = memoryReadWord(cpuGetPC() + 2); + return data; +} + +static ULO cpuGetNextLongInternal(void) +{ + ULO data = memoryReadLong(cpuGetPC() + 2); + return data; +} + +UWO cpuGetNextWord(void) +{ + UWO tmp = cpu_prefetch_word; + cpu_prefetch_word = cpuGetNextWordInternal(); + cpuSetPC(cpuGetPC() + 2); + return tmp; +} + +ULO cpuGetNextWordSignExt(void) +{ + return cpuSignExtWordToLong(cpuGetNextWord()); +} + +ULO cpuGetNextLong(void) +{ + ULO tmp = cpu_prefetch_word << 16; + ULO data = cpuGetNextLongInternal(); + cpu_prefetch_word = (UWO) data; + cpuSetPC(cpuGetPC() + 4); + return tmp | (data >> 16); +} + +void cpuInitializePrefetch(void) +{ + cpu_prefetch_word = memoryReadWord(cpuGetPC()); +} + +void cpuClearPrefetch(void) +{ + cpu_prefetch_word = 0; +} + +void cpuSkipNextWord(void) +{ + cpuSetPC(cpuGetPC() + 2); + cpuInitializePrefetch(); +} + +void cpuSkipNextLong(void) +{ + cpuSetPC(cpuGetPC() + 4); + cpuInitializePrefetch(); +} + +void cpuInitializeFromNewPC(ULO new_pc) +{ + cpuSetPC(new_pc); + cpuInitializePrefetch(); +} + +void cpuSaveState(FILE *F) +{ + ULO i, j; + + fwrite(&cpu_model_major, sizeof(cpu_model_major), 1, F); + fwrite(&cpu_model_minor, sizeof(cpu_model_minor), 1, F); + for (i = 0; i < 2; i++) + { + for (j = 0; j < 7; j++) + { + fwrite(&cpu_regs[i][j], sizeof(cpu_regs[i][j]), 1, F); + } + } + fwrite(&cpu_pc, sizeof(cpu_pc), 1, F); + fwrite(&cpu_usp, sizeof(cpu_usp), 1, F); + fwrite(&cpu_ssp, sizeof(cpu_ssp), 1, F); + fwrite(&cpu_msp, sizeof(cpu_msp), 1, F); + fwrite(&cpu_sfc, sizeof(cpu_sfc), 1, F); + fwrite(&cpu_dfc, sizeof(cpu_dfc), 1, F); + fwrite(&cpu_sr, sizeof(cpu_sr), 1, F); + fwrite(&cpu_prefetch_word, sizeof(cpu_prefetch_word), 1, F); + fwrite(&cpu_vbr, sizeof(cpu_vbr), 1, F); + fwrite(&cpu_cacr, sizeof(cpu_cacr), 1, F); + fwrite(&cpu_caar, sizeof(cpu_caar), 1, F); + fwrite(&cpu_irq_level, sizeof(cpu_irq_level), 1, F); + fwrite(&cpu_irq_address, sizeof(cpu_irq_address), 1, F); + fwrite(&cpu_initial_pc, sizeof(cpu_initial_pc), 1, F); + fwrite(&cpu_initial_sp, sizeof(cpu_initial_sp), 1, F); +} + +void cpuLoadState(FILE *F) +{ + ULO i, j; + + fread(&cpu_model_major, sizeof(cpu_model_major), 1, F); + fread(&cpu_model_minor, sizeof(cpu_model_minor), 1, F); + for (i = 0; i < 2; i++) + { + for (j = 0; j < 7; j++) + { + fread(&cpu_regs[i][j], sizeof(cpu_regs[i][j]), 1, F); + } + } + fread(&cpu_pc, sizeof(cpu_pc), 1, F); + fread(&cpu_usp, sizeof(cpu_usp), 1, F); + fread(&cpu_ssp, sizeof(cpu_ssp), 1, F); + fread(&cpu_msp, sizeof(cpu_msp), 1, F); + fread(&cpu_sfc, sizeof(cpu_sfc), 1, F); + fread(&cpu_dfc, sizeof(cpu_dfc), 1, F); + fread(&cpu_sr, sizeof(cpu_sr), 1, F); + fread(&cpu_prefetch_word, sizeof(cpu_prefetch_word), 1, F); + fread(&cpu_vbr, sizeof(cpu_vbr), 1, F); + fread(&cpu_cacr, sizeof(cpu_cacr), 1, F); + fread(&cpu_caar, sizeof(cpu_caar), 1, F); + fread(&cpu_irq_level, sizeof(cpu_irq_level), 1, F); + fread(&cpu_irq_address, sizeof(cpu_irq_address), 1, F); + fread(&cpu_initial_pc, sizeof(cpu_initial_pc), 1, F); + fread(&cpu_initial_sp, sizeof(cpu_initial_sp), 1, F); + cpuSetModel(cpu_model_major, cpu_model_minor); // Recalculates stack frames etc. +} diff --git a/cpu/CpuModule_Interrupts.c b/cpu/CpuModule_Interrupts.c new file mode 100644 index 0000000..8558bd1 --- /dev/null +++ b/cpu/CpuModule_Interrupts.c @@ -0,0 +1,107 @@ +/* @(#) $Id: CpuModule_Interrupts.c,v 1.5 2012/08/12 16:51:02 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* 68000 interrupt handling */ +/* */ +/* Author: Petter Schau */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ +#include "defs.h" +#include "fellow.h" +#include "fmem.h" + +#include "CpuModule.h" +#include "CpuModule_Internal.h" + +/* Function for checking pending interrupts */ +cpuCheckPendingInterruptsFunc cpu_check_pending_interrupts_func; + +void cpuCallCheckPendingInterruptsFunc(void) +{ + if (cpuGetRaiseInterrupt()) return; + cpuSetRaiseInterrupt(cpu_check_pending_interrupts_func()); +} + +void cpuCheckPendingInterrupts(void) +{ + cpuCallCheckPendingInterruptsFunc(); +} + +void cpuSetCheckPendingInterruptsFunc(cpuCheckPendingInterruptsFunc func) +{ + cpu_check_pending_interrupts_func = func; +} + +ULO cpuActivateSSP(void) +{ + ULO currentSP = cpuGetAReg(7); + + // check supervisor bit number (bit 13) within the system byte of the status register + if (!cpuGetFlagSupervisor()) + { + // we are in user mode, thus save user stack pointer (USP) + cpuSetUspDirect(currentSP); + currentSP = cpuGetSspDirect(); + + if (cpuGetModelMajor() >= 2) + { + if (cpuGetFlagMaster()) + { + currentSP = cpuGetMspDirect(); + } + } + cpuSetAReg(7, currentSP); + } + return currentSP; +} + +/*============================================================ + Transfers control to an interrupt routine + ============================================================*/ + +// Returns TRUE if the cpu was stopped +void cpuSetUpInterrupt(void) +{ + UWO vector_offset = (UWO) (0x60 + cpuGetIrqLevel()*4); + cpuActivateSSP(); // Switch to using ssp or msp. Loads a7 and preserves usp if we came from user-mode. + + cpuStackFrameGenerate(vector_offset, cpuGetPC()); // This will end up on msp if master is enabled, or on the ssp/isp if not. + + cpuSetSR(cpuGetSR() & 0x38ff); // Clear interrupt level + cpuSetSR(cpuGetSR() | 0x2000); // Set supervisor mode + cpuSetSR(cpuGetSR() | (UWO)(cpuGetIrqLevel() << 8)); // Set interrupt level + +#ifdef CPU_INSTRUCTION_LOGGING + cpuCallInterruptLoggingFunc(cpuGetIrqLevel(), cpuGetIrqAddress()); +#endif + + if (cpuGetModelMajor() >= 2 && cpuGetModelMajor() < 6) + { + if (cpuGetFlagMaster()) + { // If the cpu was in master mode, preserve msp, and switch to using ssp (isp) in a7. + ULO oldA7 = cpuGetAReg(7); + cpuSetMspDirect(oldA7); + cpuSetAReg(7, cpuGetSspDirect()); + cpuFrame1(vector_offset, cpuGetPC()); // Make the throwaway frame on ssp/isp + cpuSetSR(cpuGetSR() & 0xefff); // Clear master bit + } + } + cpuInitializeFromNewPC(cpuGetIrqAddress()); + cpuSetStop(FALSE); + cpuSetRaiseInterrupt(FALSE); +} diff --git a/cpu/CpuModule_Logging.c b/cpu/CpuModule_Logging.c new file mode 100644 index 0000000..1336e06 --- /dev/null +++ b/cpu/CpuModule_Logging.c @@ -0,0 +1,71 @@ +/* @(#) $Id: CpuModule_Logging.c,v 1.3 2012/08/12 16:51:02 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* CPU 68k logging functions */ +/* */ +/* Author: Petter Schau */ +/* */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ + +#include "defs.h" +#include "fellow.h" + +#include "CpuModule.h" + +#ifdef CPU_INSTRUCTION_LOGGING + +/* Function for logging the intruction execution */ +static cpuInstructionLoggingFunc cpu_instruction_logging_func; +static cpuExceptionLoggingFunc cpu_exception_logging_func; +static cpuInterruptLoggingFunc cpu_interrupt_logging_func; + +void cpuSetInstructionLoggingFunc(cpuInstructionLoggingFunc func) +{ + cpu_instruction_logging_func = func; +} + +void cpuCallInstructionLoggingFunc(void) +{ + if (cpu_instruction_logging_func != NULL) + cpu_instruction_logging_func(); +} + +void cpuSetExceptionLoggingFunc(cpuExceptionLoggingFunc func) +{ + cpu_exception_logging_func = func; +} + +void cpuCallExceptionLoggingFunc(STR *description, ULO original_pc, UWO opcode) +{ + if (cpu_exception_logging_func != NULL) + cpu_exception_logging_func(description, original_pc, opcode); +} + +void cpuSetInterruptLoggingFunc(cpuInterruptLoggingFunc func) +{ + cpu_interrupt_logging_func = func; +} + +void cpuCallInterruptLoggingFunc(ULO level, ULO vector_address) +{ + if (cpu_interrupt_logging_func != NULL) + cpu_interrupt_logging_func(level, vector_address); +} + +#endif diff --git a/cpu/CpuModule_Profile.h b/cpu/CpuModule_Profile.h new file mode 100644 index 0000000..02d1f6c --- /dev/null +++ b/cpu/CpuModule_Profile.h @@ -0,0 +1,8 @@ +#ifndef CPUMODULE_PROFILE_H +#define CPUMODULE_PROFILE_H + +#include "fileops.h" +void cpuProfileWrite(void) +{ +} +#endif diff --git a/cpu/CpuModule_StackFrameGen.c b/cpu/CpuModule_StackFrameGen.c new file mode 100644 index 0000000..d68583c --- /dev/null +++ b/cpu/CpuModule_StackFrameGen.c @@ -0,0 +1,259 @@ +/* @(#) $Id: CpuModule_StackFrameGen.c,v 1.3 2011/07/18 17:22:55 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* 68000 stack frame generation */ +/* */ +/* Author: Petter Schau */ +/* */ +/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ +#include "defs.h" +#include "fellow.h" +#include "fmem.h" + +#include "CpuModule.h" +#include "CpuModule_Internal.h" + +/* Exception stack frame jmptables */ +typedef void(*cpuStackFrameGenFunc)(UWO, ULO); +static cpuStackFrameGenFunc cpu_stack_frame_gen_func[64]; + +static void cpuSetStackFrameGenFunc(ULO vector_no, cpuStackFrameGenFunc func) +{ + cpu_stack_frame_gen_func[vector_no] = func; +} + +/*======================================================================== + Group 1 Frame format + + 000: All, except bus and address error + ========================================================================*/ + +static void cpuFrameGroup1(UWO vector_offset, ULO pcPtr) +{ + // save PC + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(pcPtr, cpuGetAReg(7)); + + // save SR + cpuSetAReg(7, cpuGetAReg(7) - 2); + memoryWriteWord((UWO)cpuGetSR(), cpuGetAReg(7)); +} + +/*======================================================================== + Group 2 Frame format + + 000: Bus and address error + + memory_fault_address contains the violating address + memory_fault_read is TRUE if the access was a read + ========================================================================*/ + +static void cpuFrameGroup2(UWO vector_offset, ULO pcPtr) +{ + // save PC + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(pcPtr, cpuGetAReg(7)); + + // save SR + cpuSetAReg(7, cpuGetAReg(7) - 2); + memoryWriteWord((UWO)cpuGetSR(), cpuGetAReg(7)); + + // fault address, skip ireg + cpuSetAReg(7, cpuGetAReg(7) - 6); + memoryWriteLong(memory_fault_address, cpuGetAReg(7)); + + cpuSetAReg(7, cpuGetAReg(7) - 2); + memoryWriteLong(memory_fault_read << 4, cpuGetAReg(7)); +} + +static void cpuFrame4Words(UWO frame_code, UWO vector_offset, ULO pc) +{ + // save vector_offset word + cpuSetAReg(7, cpuGetAReg(7) - 2); + memoryWriteWord(frame_code | vector_offset, cpuGetAReg(7)); + + // save PC + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(pc, cpuGetAReg(7)); + + // save SR + cpuSetAReg(7, cpuGetAReg(7) - 2); + memoryWriteWord((UWO)cpuGetSR(), cpuGetAReg(7)); +} + + +/*======================================================================== + Frame format $0, four word frame + + Stack words: + ------------ + SR + PCHI + PCLO + 0000 Vector offset (4 upper bits are frame no., rest is vector offset) + + 010: All, except bus and address errors + 020: Irq, Format error, Trap #N, Illegal inst., A-line, F-line, + Priv. violation, copr preinst + 030: Same as for 020 + ========================================================================*/ + +static void cpuFrame0(UWO vector_offset, ULO pc) +{ + cpuFrame4Words(0x0000, vector_offset, pc); +} + +/*======================================================================== + Frame format $1, 4 word throwaway frame + + Stack words: + ------------ + SR + PCHI + PCLO + 0000 Vector offset (4 upper bits are frame no., rest is Vvctor offset) + + 020: Irq, second frame created + 030: Same as for 020 + 040: Same as for 020 + ========================================================================*/ + +void cpuFrame1(UWO vector_offset, ULO pc) +{ + cpuFrame4Words(0x1000, vector_offset, pc); +} + +/*======================================================================== + Frame format $2 + + 020: chk, chk2, cpTrapcc, trapcc, trapv, trace, zero divide, MMU config, + copr postinst + 030: Same as for 020 + 040: chk, chk2, FTrapcc, trapcc, trapv, trace, zero divide, address error, + Unimplemented FPU inst. + 060: Same as for 040 + ========================================================================*/ + +static void cpuFrame2(UWO vector_offset, ULO pc) +{ + // save inst address + cpuSetAReg(7, cpuGetAReg(7) - 4); + memoryWriteLong(cpuGetOriginalPC(), cpuGetAReg(7)); + cpuFrame4Words(0x2000, vector_offset, pc); +} + +/*======================================================================== + Frame format $8 + + 010: Bus and address error + + ========================================================================*/ + +static void cpuFrame8(UWO vector_offset, ULO pc) +{ + cpuSetAReg(7, cpuGetAReg(7) - 50); + cpuFrame4Words(0x8000, vector_offset, pc); +} + +/*======================================================================== + Frame format $A + + 020: Address or bus-error on instruction boundrary + 030: Same as for 020 + + Will not set any values beyond the format/offset word + Fellow will always generate this frame for bus/address errors + ========================================================================*/ + +static void cpuFrameA(UWO vector_offset, ULO pc) +{ + // save vector_offset offset + cpuSetAReg(7, cpuGetAReg(7) - 24); + cpuFrame4Words(0xa000, vector_offset, pc); +} + +void cpuStackFrameGenerate(UWO vector_offset, ULO pc) +{ + cpu_stack_frame_gen_func[vector_offset>>2](vector_offset, pc); +} + +/*==================================*/ +/* Initialize stack frame jmptables */ +/*==================================*/ + +static void cpuStackFrameInitSetDefaultFunc(cpuStackFrameGenFunc default_func) +{ + ULO i; + for (i = 0; i < 64; i++) + cpuSetStackFrameGenFunc(i, default_func); +} + +static void cpuStackFrameInit000(void) +{ + cpuStackFrameInitSetDefaultFunc(cpuFrameGroup1); + cpuSetStackFrameGenFunc(2, cpuFrameGroup2); /* 2 - Bus error */ + cpuSetStackFrameGenFunc(3, cpuFrameGroup2); /* 3 - Address error */ +} + +static void cpuStackFrameInit010(void) +{ + cpuStackFrameInitSetDefaultFunc(cpuFrame0); + cpuSetStackFrameGenFunc(2, cpuFrame8); /* 2 - Bus error */ + cpuSetStackFrameGenFunc(3, cpuFrame8); /* 3 - Address error */ +} + +static void cpuStackFrameInit020(void) +{ + cpuStackFrameInitSetDefaultFunc(cpuFrame0); + cpuSetStackFrameGenFunc(2, cpuFrameA); /* 2 - Bus Error */ + cpuSetStackFrameGenFunc(3, cpuFrameA); /* 3 - Addrss Error */ + cpuSetStackFrameGenFunc(5, cpuFrame2); /* 5 - Zero Divide */ + cpuSetStackFrameGenFunc(6, cpuFrame2); /* 6 - CHK, CHK2 */ + cpuSetStackFrameGenFunc(7, cpuFrame2); /* 7 - TRAPV, TRAPcc, cpTRAPcc */ + cpuSetStackFrameGenFunc(9, cpuFrame2); /* 9 - Trace */ +} + +static void cpuStackFrameInit030(void) +{ + cpuStackFrameInitSetDefaultFunc(cpuFrame0); + cpuSetStackFrameGenFunc(2, cpuFrameA); /* 2 - Bus Error */ + cpuSetStackFrameGenFunc(3, cpuFrameA); /* 3 - Addrss Error */ + cpuSetStackFrameGenFunc(5, cpuFrame2); /* 5 - Zero Divide */ + cpuSetStackFrameGenFunc(6, cpuFrame2); /* 6 - CHK, CHK2 */ + cpuSetStackFrameGenFunc(7, cpuFrame2); /* 7 - TRAPV, TRAPcc, cpTRAPcc */ + cpuSetStackFrameGenFunc(9, cpuFrame2); /* 9 - Trace */ +} + +void cpuStackFrameInit(void) +{ + switch (cpuGetModelMajor()) + { + case 0: + cpuStackFrameInit000(); + break; + case 1: + cpuStackFrameInit010(); + break; + case 2: + cpuStackFrameInit020(); + break; + case 3: + cpuStackFrameInit030(); + break; + } +} diff --git a/cpu/defs.h b/cpu/defs.h new file mode 100644 index 0000000..ce67e95 --- /dev/null +++ b/cpu/defs.h @@ -0,0 +1,72 @@ +#ifndef DEFS_H +#define DEFS_H + +#include +#include +#include + +/* Maximum values for memory, don't change */ + +#define CHIPMEM 0x200000 +#define FASTMEM 0x800000 +#define BOGOMEM 0x1c0000 +#define KICKMEM 0x080000 + +/* Fellow types to ensure correct sizes */ + +typedef uint8_t UBY; +typedef uint16_t UWO; +typedef uint32_t ULO; +typedef uint64_t ULL; +typedef int8_t BYT; +typedef int16_t WOR; +typedef int32_t LON; +typedef int64_t LLO; +typedef int BOOLE; +#define FALSE 0 +#define TRUE 1 +typedef char STR; + +/* +#ifndef X64 +#define PTR_TO_INT(i) ((ULO)i) +#endif +#ifdef X64 +#define PTR_TO_INT(i) ((ULL)i) +#endif +*/ + +/* Filename length used throughout the code */ + +#define CFG_FILENAME_LENGTH 256 + +/*------------------------------------*/ +/* The decode routines have this type */ +/*------------------------------------*/ + +typedef void (*decoderoutinetype)(ULO,ULO); + +extern UBY configromname[]; + +typedef union { + ULO *lptr; + UWO *wptr; + UBY *bptr; + ULO lval; + UWO wval[2]; + UBY bval[4]; + } ptunion; + +typedef void (*planar2chunkyroutine)(void); + +typedef void (*playbuffer_routine)(void); +typedef void (*sound_before_emu_routine)(void); +typedef void (*sound_after_emu_routine)(void); + +typedef void (*buseventfunc)(void); + +#define FELLOWVERSION "WinFellow alpha v0.5.0 build 0 (CVS)" +#define FELLOWLONGVERSION "WinFellow Amiga Emulator alpha v0.5.0 - CVS" +#define FELLOWNUMERICVERSION "0.5.0.0" + +#endif diff --git a/cpu/fmem.c b/cpu/fmem.c new file mode 100644 index 0000000..1cac266 --- /dev/null +++ b/cpu/fmem.c @@ -0,0 +1,2094 @@ +/* @(#) $Id: FMEM.C,v 1.17 2013/01/13 18:31:09 peschau Exp $ */ +/*=========================================================================*/ +/* Fellow */ +/* Virtual Memory System */ +/* */ +/* Authors: Petter Schau, Torsten Enderling */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the Free Software Foundation, */ +/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/*=========================================================================*/ + +#include "defs.h" +#include "fellow.h" +#include "draw.h" +#include "CpuModule.h" +#include "CpuIntegration.h" +#include "fhfile.h" +#include "graph.h" +#include "floppy.h" +#include "copper.h" +#include "cia.h" +#include "blit.h" +#include "fmem.h" +#include "fswrap.h" +#include "wgui.h" + +#ifdef WIN32 +#include +#endif + +/*============================================================================*/ +/* Holds configuration for memory */ +/*============================================================================*/ + +ULO memory_chipsize; +ULO memory_fastsize; +ULO memory_slowsize; +BOOLE memory_useautoconfig; +BOOLE memory_address32bit; +STR memory_kickimage[CFG_FILENAME_LENGTH]; +STR memory_key[256]; + + +/*============================================================================*/ +/* Holds actual memory */ +/*============================================================================*/ + +UBY memory_chip[0x200000 + 32]; +UBY memory_slow[0x1c0000 + 32]; +UBY memory_kick[0x080000 + 32]; +UBY *memory_fast = NULL; +ULO memory_fast_baseaddress; +ULO memory_fastallocatedsize; + + +/*============================================================================*/ +/* Autoconfig data */ +/*============================================================================*/ + +#define EMEM_MAXARDS 4 +UBY memory_emem[0x10000]; +memoryEmemCardInitFunc memory_ememard_initfunc[EMEM_MAXARDS]; +memoryEmemCardMapFunc memory_ememard_mapfunc[EMEM_MAXARDS]; +ULO memory_ememardcount; /* Number of cards */ +ULO memory_ememards_finishedcount; /* Current card */ + + +/*============================================================================*/ +/* Device memory data */ +/*============================================================================*/ + +#define MEMORY_DMEM_OFFSET 0xf40000 + +UBY memory_dmem[65536]; +ULO memory_dmemcounter; + + +/*============================================================================*/ +/* Additional Kickstart data */ +/*============================================================================*/ + +ULO memory_initial_PC; +ULO memory_initial_SP; +BOOLE memory_kickimage_none; +ULO memory_kickimage_size; +ULO memory_kickimage_version; +STR memory_kickimage_versionstr[80]; +ULO memory_kickimage_basebank; +const STR *memory_kickimage_versionstrings[14] = { + "Kickstart, version information unavailable", + "Kickstart Pre-V1.0", + "Kickstart V1.0", + "Kickstart V1.1 (NTSC)", + "Kickstart V1.1 (PAL)", + "Kickstart V1.2", + "Kickstart V1.3", + "Kickstart V1.3", + "Kickstart V2.0", + "Kickstart V2.04", + "Kickstart V2.1", + "Kickstart V3.0", + "Kickstart V3.1", + "Kickstart Post-V3.1"}; + void memoryKickSettingsClear(void); + + + /*============================================================================*/ + /* Illegal read / write fault information */ + /*============================================================================*/ + + BOOLE memory_fault_read; /* TRUE - read / FALSE - write */ + ULO memory_fault_address; + + + /*============================================================================*/ + /* Some run-time scratch variables */ + /*============================================================================*/ + + ULO memory_mystery_value; /* Pattern needed in an unknown bank (hmm) */ + ULO memory_noise[2]; /* Returns alternating bitpattern in */ + ULO memory_noisecounter; /* unused IO-registers to keep apps from hanging */ + ULO memory_undefined_io_writecounter = 0; + + void memoryWriteByteToPointer(UBY data, UBY *address) + { + address[0] = data; + } + + void memoryWriteWordToPointer(UWO data, UBY *address) + { + address[0] = (UBY) (data >> 8); + address[1] = (UBY) data; + } + + void memoryWriteLongToPointer(ULO data, UBY *address) + { + address[0] = (UBY) (data >> 24); + address[1] = (UBY) (data >> 16); + address[2] = (UBY) (data >> 8); + address[3] = (UBY) data; + } + + /*---------------------------- + Chip read register functions + ----------------------------*/ + + UWO rintreqr(ULO address) + { + return (UWO) intreq; + } + + /* SERDATR + $dff018 */ + + UWO rserdatr(ULO address) + { + return 0x2000; + } + + /* INTENAR + $dff01c */ + + UWO rintenar(ULO address) + { + return (UWO) intenar; + } + + // To simulate noise, return 0 and -1 every second time. + // Why? Bugged demos test write-only registers for various bit-values + // and to break out of loops, both 0 and 1 values must be returned. + + UWO rdefault(ULO address) + { + memory_noisecounter++; + return (UWO) memory_noise[memory_noisecounter & 0x1]; + } + + void wdefault(UWO data, ULO address) + { + memory_undefined_io_writecounter++; + } + + /* + ====== + INTREQ + ====== + + $dff09c - Read from $dff01e + + Paula + */ + + void wintreq(UWO data, ULO address) + { + if (data & 0x8000) + { + intreq = intreq | (data & 0x7fff); + } + else + { + intreq = intreq & ~(data & 0x7fff); + ciaUpdateIRQ(0); + ciaUpdateIRQ(1); + } + cpuIntegrationCheckPendingInterrupts(); + } + + /* + ====== + INTENA + ====== + + $dff09a - Read from $dff01c + + Paula + */ + + // If master bit is off, then INTENA is 0, else INTENA = INTENAR + // The master bit can not be read, the memory test in the kickstart + // depends on this. + + void wintena(UWO data, ULO address) + { + if (data & 0x8000) + { + intenar = intenar | (data & 0x7fff); + } + else + { + intenar = intenar & ~(data & 0x7fff); + } + + if ((intenar & 0x00004000) == 0x00004000) + { + // Interrupts are enabled, check if any has not been serviced + intena = intenar; + cpuIntegrationCheckPendingInterrupts(); + } + else + { + intena = 0; + } + } + + /*============================================================================*/ + /* Table of register read/write functions */ + /*============================================================================*/ + + memoryIoReadFunc memory_iobank_read[257]; // Account for long writes to the last + memoryIoWriteFunc memory_iobank_write[257]; // word + + /*============================================================================*/ + /* Memory mapping tables */ + /*============================================================================*/ + + memoryReadByteFunc memory_bank_readbyte[65536]; + memoryReadWordFunc memory_bank_readword[65536]; + memoryReadLongFunc memory_bank_readlong[65536]; + memoryWriteByteFunc memory_bank_writebyte[65536]; + memoryWriteWordFunc memory_bank_writeword[65536]; + memoryWriteLongFunc memory_bank_writelong[65536]; + UBY *memory_bank_pointer[65536]; /* Used by the filesystem */ + BOOLE memory_bank_pointer_can_write[65536]; + + /* Variables that correspond to various registers */ + + ULO intenar, intena, intreq; + + + /*============================================================================*/ + /* Memory bank mapping functions */ + /*============================================================================*/ + + /*============================================================================*/ + /* Set read and write stubs for a bank, as well as a direct pointer to */ + /* its memory. NULL pointer is passed when the memory must always be */ + /* read through the stubs, like in a bank of regsters where writing */ + /* or reading the value generates side-effects. */ + /* Datadirect is TRUE when data accesses can be made through a pointer */ + /*============================================================================*/ + + void memoryBankSet(memoryReadByteFunc rb, + memoryReadWordFunc rw, + memoryReadLongFunc rl, + memoryWriteByteFunc wb, + memoryWriteWordFunc ww, + memoryWriteLongFunc wl, + UBY *basep, + ULO bank, + ULO basebank, + BOOLE pointer_can_write) + { + ULO i, j; + + j = (memoryGetAddress32Bit()) ? 65536 : 256; + for (i = bank; i < 65536; i += j) + { + memory_bank_readbyte[i] = rb; + memory_bank_readword[i] = rw; + memory_bank_readlong[i] = rl; + memory_bank_writebyte[i] = wb; + memory_bank_writeword[i] = ww; + memory_bank_writelong[i] = wl; + memory_bank_pointer_can_write[i] = pointer_can_write; + + if (basep != NULL) + { + memory_bank_pointer[i] = basep - (basebank<<16); + } + else + { + memory_bank_pointer[i] = NULL; + } + basebank += j; + } + } + + + /*============================================================================*/ + /* Clear one bank data to safe "do-nothing" values */ + /*============================================================================*/ + + /* Unmapped memory interface */ + + UBY memoryUnmappedReadByte(ULO address) + { + memory_mystery_value = ~memory_mystery_value; + return (UBY) memory_mystery_value; + } + + UWO memoryUnmappedReadWord(ULO address) + { + return 0x6100; + } + + ULO memoryUnmappedReadLong(ULO address) + { + return 0x61006100; + } + + void memoryUnmappedWriteByte(UBY data, ULO address) + { + // NOP + } + + void memoryUnmappedWriteWord(UWO data, ULO address) + { + // NOP + } + + void memoryUnmappedWriteLong(ULO data, ULO address) + { + // NOP + } + + void memoryBankClear(ULO bank) + { + memoryBankSet(memoryUnmappedReadByte, + memoryUnmappedReadWord, + memoryUnmappedReadLong, + memoryUnmappedWriteByte, + memoryUnmappedWriteWord, + memoryUnmappedWriteLong, + NULL, + bank, + 0, + FALSE); + } + + /*============================================================================*/ + /* Clear all bank data to safe "do-nothing" values */ + /*============================================================================*/ + + void memoryBankClearAll(void) + { + ULO bank; + ULO hilim = (memoryGetAddress32Bit()) ? 65536 : 256; + for (bank = 0; bank < hilim; bank++) + memoryBankClear(bank); + } + + + /*============================================================================*/ + /* Expansion cards autoconfig */ + /*============================================================================*/ + + + /*============================================================================*/ + /* Clear the expansion config bank */ + /*============================================================================*/ + + void memoryEmemClear(void) + { + memset(memory_emem, 0xff, 65536); + } + + /*============================================================================*/ + /* Add card to table */ + /*============================================================================*/ + + void memoryEmemCardAdd(memoryEmemCardInitFunc cardinit, + memoryEmemCardMapFunc cardmap) + { + if (memory_ememardcount < EMEM_MAXARDS) + { + memory_ememard_initfunc[memory_ememardcount] = cardinit; + memory_ememard_mapfunc[memory_ememardcount] = cardmap; + memory_ememardcount++; + } + } + + /*============================================================================*/ + /* Advance the card pointer */ + /*============================================================================*/ + + void memoryEmemCardNext(void) + { + memory_ememards_finishedcount++; + } + + + /*============================================================================*/ + /* Init the current card */ + /*============================================================================*/ + + void memoryEmemCardInit(void) + { + memoryEmemClear(); + if (memory_ememards_finishedcount != memory_ememardcount) + memory_ememard_initfunc[memory_ememards_finishedcount](); + } + + /*============================================================================*/ + /* Map this card */ + /* Mapping is bank number set by AmigaOS */ + /*============================================================================*/ + + void memoryEmemCardMap(ULO mapping) + { + if (memory_ememards_finishedcount == memory_ememardcount) + memoryEmemClear(); + else + memory_ememard_mapfunc[memory_ememards_finishedcount](mapping); + } + + /*============================================================================*/ + /* Reset card setup */ + /*============================================================================*/ + + void memoryEmemCardsReset(void) + { + memory_ememards_finishedcount = 0; + memoryEmemCardInit(); + } + + /*============================================================================*/ + /* Clear the card table */ + /*============================================================================*/ + + void memoryEmemCardsRemove(void) + { + memory_ememardcount = memory_ememards_finishedcount = 0; + } + + /*============================================================================*/ + /* Set a byte in autoconfig space, for initfunc routines */ + /* so they can make their configuration visible */ + /*============================================================================*/ + + void memoryEmemSet(ULO index, ULO value) + { + index &= 0xffff; + switch (index) + { + case 0: + case 2: + case 0x40: + case 0x42: + memory_emem[index] = (UBY) (value & 0xf0); + memory_emem[index + 2] = (UBY) ((value & 0xf)<<4); + break; + default: + memory_emem[index] = (UBY) (~(value & 0xf0)); + memory_emem[index + 2] = (UBY) (~((value & 0xf)<<4)); + break; + } + } + + /*============================================================================*/ + /* Copy data into emem space */ + /*============================================================================*/ + + void memoryEmemMirror(ULO emem_offset, UBY *src, ULO size) + { + memcpy(memory_emem + emem_offset, src, size); + } + + /*============================================================================*/ + /* Read/Write stubs for autoconfig memory */ + /*============================================================================*/ + + UBY memoryEmemReadByte(ULO address) + { + UBY *p = memory_emem + (address & 0xffff); + return memoryReadByteFromPointer(p); + } + + UWO memoryEmemReadWord(ULO address) + { + UBY *p = memory_emem + (address & 0xffff); + return memoryReadWordFromPointer(p); + } + + ULO memoryEmemReadLong(ULO address) + { + UBY *p = memory_emem + (address & 0xffff); + return memoryReadLongFromPointer(p); + } + + void memoryEmemWriteByte(UBY data, ULO address) + { + static ULO mapping; + + switch (address & 0xffff) + { + case 0x30: + case 0x32: + mapping = data = 0; + case 0x48: + mapping = (mapping & 0xff) | (((ULO)data) << 8); + memoryEmemCardMap(mapping); + memoryEmemCardNext(); + memoryEmemCardInit(); + break; + case 0x4a: + mapping = (mapping & 0xff00) | ((ULO)data); + break; + case 0x4c: + memoryEmemCardNext(); + memoryEmemCardInit(); + break; + } + } + + void memoryEmemWriteWord(UWO data, ULO address) + { + } + + void memoryEmemWriteLong(ULO data, ULO address) + { + } + + /*===========================================================================*/ + /* Map the autoconfig memory bank into memory */ + /*===========================================================================*/ + + void memoryEmemMap(void) + { + if (memoryGetKickImageBaseBank() >= 0xf8) + memoryBankSet(memoryEmemReadByte, + memoryEmemReadWord, + memoryEmemReadLong, + memoryEmemWriteByte, + memoryEmemWriteWord, + memoryEmemWriteLong, + NULL, + 0xe8, + 0xe8, + FALSE); + } + + + /*===================*/ + /* End of autoconfig */ + /*===================*/ + + + /*============================================================================*/ + /* dmem is the data area used by the hardfile device to communicate info */ + /* about itself with the Amiga */ + /*============================================================================*/ + + /*============================================================================*/ + /* Functions to set data in dmem by the native device drivers */ + /*============================================================================*/ + + UBY memoryDmemReadByte(ULO address) + { + UBY *p = memory_dmem + (address & 0xffff); + return memoryReadByteFromPointer(p); + } + + UWO memoryDmemReadWord(ULO address) + { + UBY *p = memory_dmem + (address & 0xffff); + return memoryReadWordFromPointer(p); + } + + ULO memoryDmemReadLong(ULO address) + { + UBY *p = memory_dmem + (address & 0xffff); + return memoryReadLongFromPointer(p); + } + + void memoryDmemWriteByte(UBY data, ULO address) + { + // NOP + } + + void memoryDmemWriteWord(UWO data, ULO address) + { + // NOP + } + + /*============================================================================*/ + /* Writing a long to $f40000 runs a native function */ + /*============================================================================*/ + + void memoryDmemWriteLong(ULO data, ULO address) + { + if ((address & 0xffffff) == 0xf40000) + { + switch (data>>16) + { + case 0x0001: fhfileDo(data); + break; + default: break; + } + } + } + + void memoryDmemClear(void) + { + memset(memory_dmem, 0, 4096); + } + + void memoryDmemSetCounter(ULO c) + { + memory_dmemcounter = c; + } + + ULO memoryDmemGetCounter(void) + { + return memory_dmemcounter + MEMORY_DMEM_OFFSET; + } + + void memoryDmemSetString(STR *st) + { + strcpy((STR *) (memory_dmem + memory_dmemcounter), st); + memory_dmemcounter += (ULO) strlen(st) + 1; + if (memory_dmemcounter & 1) memory_dmemcounter++; + } + + void memoryDmemSetByte(UBY data) + { + memory_dmem[memory_dmemcounter++] = data; + } + + void memoryDmemSetWord(UWO data) + { + memoryWriteWordToPointer(data, memory_dmem + memory_dmemcounter); + memory_dmemcounter += 2; + } + + void memoryDmemSetLong(ULO data) + { + memoryWriteLongToPointer(data, memory_dmem + memory_dmemcounter); + memory_dmemcounter += 4; + } + + void memoryDmemSetLongNoCounter(ULO data, ULO offset) + { + memoryWriteLongToPointer(data, memory_dmem + offset); + } + + void memoryDmemMap(void) + { + ULO bank = 0xf40000>>16; + + if (memory_useautoconfig && (memory_kickimage_basebank >= 0xf8)) + memoryBankSet(memoryDmemReadByte, + memoryDmemReadWord, + memoryDmemReadLong, + memoryDmemWriteByte, + memoryDmemWriteWord, + memoryDmemWriteLong, + memory_dmem, + bank, + bank, + FALSE); + } + + /*============================================================================*/ + /* Converts an address to a direct pointer to memory. Used by hardfile device */ + /*============================================================================*/ + + UBY *memoryAddressToPtr(ULO address) + { + UBY *result; + + if ((result = memory_bank_pointer[address>>16]) != NULL) + result += address; + return result; + } + + /*============================================================================*/ + /* Chip memory handling */ + /*============================================================================*/ + + UBY memoryChipReadByte(ULO address) + { + UBY *p = memory_chip + (address & 0x1fffff); + return memoryReadByteFromPointer(p); + } + + UWO memoryChipReadWord(ULO address) + { + UBY *p = memory_chip + (address & 0x1fffff); + return memoryReadWordFromPointer(p); + } + + ULO memoryChipReadLong(ULO address) + { + UBY *p = memory_chip + (address & 0x1fffff); + return memoryReadLongFromPointer(p); + } + + void memoryChipWriteByte(UBY data, ULO address) + { + UBY *p = memory_chip + (address & 0x1fffff); + memoryWriteByteToPointer(data, p); + } + + void memoryChipWriteWord(UWO data, ULO address) + { + UBY *p = memory_chip + (address & 0x1fffff); + memoryWriteWordToPointer(data, p); + } + + void memoryChipWriteLong(ULO data, ULO address) + { + UBY *p = memory_chip + (address & 0x1fffff); + memoryWriteLongToPointer(data, p); + } + + void memoryChipClear(void) + { + memset(memory_chip, 0, memoryGetChipSize()); + } + + UBY memoryOverlayReadByte(ULO address) + { + UBY *p = memory_kick + (address & 0xffffff); + return memoryReadByteFromPointer(p); + } + + UWO memoryOverlayReadWord(ULO address) + { + UBY *p = memory_kick + (address & 0xffffff); + return memoryReadWordFromPointer(p); + } + + ULO memoryOverlayReadLong(ULO address) + { + UBY *p = memory_kick + (address & 0xffffff); + return memoryReadLongFromPointer(p); + } + + void memoryOverlayWriteByte(UBY data, ULO address) + { + // NOP + } + + void memoryOverlayWriteWord(UWO data, ULO address) + { + // NOP + } + + void memoryOverlayWriteLong(ULO data, ULO address) + { + // NOP + } + + void memoryChipMap(BOOLE overlay) + { + ULO bank, lastbank; + + if (overlay) + { + for (bank = 0; bank < 8; bank++) + memoryBankSet(memoryOverlayReadByte, + memoryOverlayReadWord, + memoryOverlayReadLong, + memoryOverlayWriteByte, + memoryOverlayWriteWord, + memoryOverlayWriteLong, + memory_kick, + bank, + 0, + FALSE); + } + + if (memoryGetChipSize() > 0x200000) lastbank = 0x200000>>16; + else lastbank = memoryGetChipSize()>>16; + + for (bank = (overlay) ? 8 : 0; bank < lastbank; bank++) + memoryBankSet(memoryChipReadByte, + memoryChipReadWord, + memoryChipReadLong, + memoryChipWriteByte, + memoryChipWriteWord, + memoryChipWriteLong, + memory_chip, + bank, + 0, + TRUE); + } + + /*============================================================================*/ + /* Fast memory handling */ + /*============================================================================*/ + + UBY memoryFastReadByte(ULO address) + { + UBY *p = memory_fast + ((address & 0xffffff) - memory_fast_baseaddress); + return memoryReadByteFromPointer(p); + } + + UWO memoryFastReadWord(ULO address) + { + UBY *p = memory_fast + ((address & 0xffffff) - memory_fast_baseaddress); + return memoryReadWordFromPointer(p); + } + + ULO memoryFastReadLong(ULO address) + { + UBY *p = memory_fast + ((address & 0xffffff) - memory_fast_baseaddress); + return memoryReadLongFromPointer(p); + } + + void memoryFastWriteByte(UBY data, ULO address) + { + UBY *p = memory_fast + ((address & 0xffffff) - memory_fast_baseaddress); + memoryWriteByteToPointer(data, p); + } + + void memoryFastWriteWord(UWO data, ULO address) + { + UBY *p = memory_fast + ((address & 0xffffff) - memory_fast_baseaddress); + memoryWriteWordToPointer(data, p); + } + + void memoryFastWriteLong(ULO data, ULO address) + { + UBY *p = memory_fast + ((address & 0xffffff) - memory_fast_baseaddress); + memoryWriteLongToPointer(data, p); + } + + /*============================================================================*/ + /* Set up autoconfig values for fastmem card */ + /*============================================================================*/ + + void memoryFastCardInit(void) + { + if (memoryGetFastSize() == 0x100000) memoryEmemSet(0, 0xe5); + else if (memoryGetFastSize() == 0x200000) memoryEmemSet(0, 0xe6); + else if (memoryGetFastSize() == 0x400000) memoryEmemSet(0, 0xe7); + else if (memoryGetFastSize() == 0x800000) memoryEmemSet(0, 0xe0); + memoryEmemSet(8, 128); + memoryEmemSet(4, 1); + memoryEmemSet(0x10, 2011>>8); + memoryEmemSet(0x14, 2011 & 0xf); + memoryEmemSet(0x18, 0); + memoryEmemSet(0x1c, 0); + memoryEmemSet(0x20, 0); + memoryEmemSet(0x24, 1); + memoryEmemSet(0x28, 0); + memoryEmemSet(0x2c, 0); + memoryEmemSet(0x40, 0); + } + + /*============================================================================*/ + /* Allocate memory for the fast card memory */ + /*============================================================================*/ + + void memoryFastClear(void) + { + if (memory_fast != NULL) + memset(memory_fast, 0, memoryGetFastSize()); + } + + void memoryFastFree(void) + { + if (memory_fast != NULL) + { + free(memory_fast); + memory_fast = NULL; + memory_fast_baseaddress = 0; + memorySetFastAllocatedSize(0); + } + } + + void memoryFastAllocate(void) + { + if (memoryGetFastSize() != memoryGetFastAllocatedSize()) + { + memoryFastFree(); + memory_fast = (UBY *) malloc(memoryGetFastSize()); + if (memory_fast == NULL) memorySetFastSize(0); + else memoryFastClear(); + memorySetFastAllocatedSize((memory_fast == NULL) ? 0 : memoryGetFastSize()); + } + } + + /*============================================================================*/ + /* Map fastcard. */ + /*============================================================================*/ + + void memoryFastCardMap(ULO mapping) + { + ULO bank, lastbank; + + memory_fast_baseaddress = (mapping >> 8) << 16; + if (memoryGetFastSize() > 0x800000) lastbank = 0xa00000>>16; + else lastbank = (memory_fast_baseaddress + memoryGetFastSize())>>16; + for (bank = memory_fast_baseaddress>>16; bank < lastbank; bank++) + memoryBankSet(memoryFastReadByte, + memoryFastReadWord, + memoryFastReadLong, + memoryFastWriteByte, + memoryFastWriteWord, + memoryFastWriteLong, + memory_fast, + bank, + memory_fast_baseaddress>>16, + TRUE); + memset(memory_fast, 0, memoryGetFastSize()); + } + + void memoryFastCardAdd(void) + { + if (memoryGetFastSize() != 0) + memoryEmemCardAdd(memoryFastCardInit, memoryFastCardMap); + } + + /*============================================================================*/ + /* Slow memory handling */ + /*============================================================================*/ + + UBY memorySlowReadByte(ULO address) + { + UBY *p = memory_slow + ((address & 0xffffff) - 0xc00000); + return memoryReadByteFromPointer(p); + } + + UWO memorySlowReadWord(ULO address) + { + UBY *p = memory_slow + ((address & 0xffffff) - 0xc00000); + return memoryReadWordFromPointer(p); + } + + ULO memorySlowReadLong(ULO address) + { + UBY *p = memory_slow + ((address & 0xffffff) - 0xc00000); + return memoryReadLongFromPointer(p); + } + + void memorySlowWriteByte(UBY data, ULO address) + { + UBY *p = memory_slow + ((address & 0xffffff) - 0xc00000); + memoryWriteByteToPointer(data, p); + } + + void memorySlowWriteWord(UWO data, ULO address) + { + UBY *p = memory_slow + ((address & 0xffffff) - 0xc00000); + memoryWriteWordToPointer(data, p); + } + + void memorySlowWriteLong(ULO data, ULO address) + { + UBY *p = memory_slow + ((address & 0xffffff) - 0xc00000); + memoryWriteLongToPointer(data, p); + } + + void memorySlowClear(void) + { + memset(memory_slow, 0, memoryGetSlowSize()); + } + + void memorySlowMap(void) + { + ULO bank, lastbank; + + if (memoryGetSlowSize() > 0x1c0000) lastbank = 0xdc0000>>16; + else lastbank = (0xc00000 + memoryGetSlowSize())>>16; + for (bank = 0xc00000>>16; bank < lastbank; bank++) + memoryBankSet(memorySlowReadByte, + memorySlowReadWord, + memorySlowReadLong, + memorySlowWriteByte, + memorySlowWriteWord, + memorySlowWriteLong, + memory_slow, + bank, + 0xc00000>>16, + TRUE); + } + + /*============================================================================*/ + /* Probably a disk controller, we need it to pass dummy values to get past */ + /* the bootstrap of some Kickstart versions. */ + /*============================================================================*/ + + UBY memoryMysteryReadByte(ULO address) + { + memory_mystery_value = ~memory_mystery_value; + return (UBY) memory_mystery_value; + } + + UWO memoryMysteryReadWord(ULO address) + { + memory_mystery_value = ~memory_mystery_value; + return (UWO) memory_mystery_value; + } + + ULO memoryMysteryReadLong(ULO address) + { + memory_mystery_value = ~memory_mystery_value; + return memory_mystery_value; + } + + void memoryMysteryWriteByte(UBY data, ULO address) + { + // NOP + } + + void memoryMysteryWriteWord(UWO data, ULO address) + { + // NOP + } + + void memoryMysteryWriteLong(ULO data, ULO address) + { + // NOP + } + + void memoryMysteryMap(void) + { + memoryBankSet(memoryMysteryReadByte, + memoryMysteryReadWord, + memoryMysteryReadLong, + memoryMysteryWriteByte, + memoryMysteryWriteWord, + memoryMysteryWriteLong, + NULL, + 0xe9, + 0, + FALSE); + memoryBankSet(memoryMysteryReadByte, + memoryMysteryReadWord, + memoryMysteryReadLong, + memoryMysteryWriteByte, + memoryMysteryWriteWord, + memoryMysteryWriteLong, + NULL, + 0xde, + 0, + FALSE); + } + + /*============================================================================*/ + /* IO Registers */ + /*============================================================================*/ + + UBY memoryIoReadByte(ULO address) + { + ULO adr = address & 0x1fe; + if (address & 0x1) + { // Odd address + return (UBY) memory_iobank_read[adr >> 1](adr); + } + else + { // Even address + return (UBY) (memory_iobank_read[adr >> 1](adr) >> 8); + } + } + + UWO memoryIoReadWord(ULO address) + { + return memory_iobank_read[(address & 0x1fe) >> 1](address & 0x1fe); + } + + ULO memoryIoReadLong(ULO address) + { + ULO adr = address & 0x1fe; + ULO r1 = (ULO)memory_iobank_read[adr >> 1](adr); + ULO r2 = (ULO)memory_iobank_read[(adr + 2) >> 1](adr + 2); + return (r1 << 16) | r2; + } + + void memoryIoWriteByte(UBY data, ULO address) + { + ULO adr = address & 0x1fe; + if (address & 0x1) + { // Odd address + memory_iobank_write[adr >> 1]((UWO) data, adr); + } + else + { // Even address + memory_iobank_write[adr >> 1](((UWO) data) << 8, adr); + } + } + + void memoryIoWriteWord(UWO data, ULO address) + { + ULO adr = address & 0x1fe; + memory_iobank_write[adr >> 1](data, adr); + } + + void memoryIoWriteLong(ULO data, ULO address) + { + ULO adr = address & 0x1fe; + memory_iobank_write[adr >> 1]((UWO)(data >> 16), adr); + memory_iobank_write[(adr + 2) >> 1]((UWO)data, adr + 2); + } + + void memoryIoMap(void) + { + ULO bank, lastbank; + + if (memoryGetSlowSize() > 0x1c0000) lastbank = 0xdc0000>>16; + else lastbank = (0xc00000 + memoryGetSlowSize())>>16; + for (bank = lastbank; bank < 0xe00000>>16; bank++) + memoryBankSet(memoryIoReadByte, + memoryIoReadWord, + memoryIoReadLong, + memoryIoWriteByte, + memoryIoWriteWord, + memoryIoWriteLong, + NULL, + bank, + 0, + FALSE); + } + + /*===========================================================================*/ + /* Initializes one entry in the IO register access table */ + /*===========================================================================*/ + + void memorySetIoReadStub(ULO index, memoryIoReadFunc ioreadfunction) + { + memory_iobank_read[index>>1] = ioreadfunction; + } + + void memorySetIoWriteStub(ULO index, memoryIoWriteFunc iowritefunction) + { + memory_iobank_write[index>>1] = iowritefunction; + } + + /*===========================================================================*/ + /* Clear all IO-register accessors */ + /*===========================================================================*/ + + void memoryIoClear(void) + { + ULO i; + + // Array has 257 elements to account for long writes to the last address. + for (i = 0; i <= 512; i += 2) { + memorySetIoReadStub(i, rdefault); + memorySetIoWriteStub(i, wdefault); + } + } + + /*============================================================================*/ + /* Kickstart handling */ + /*============================================================================*/ + + /*============================================================================*/ + /* Map the Kickstart image into Amiga memory */ + /*============================================================================*/ + + UBY memoryKickReadByte(ULO address) + { + UBY *p = memory_kick + ((address & 0xffffff) - 0xf80000); + return memoryReadByteFromPointer(p); + } + + UWO memoryKickReadWord(ULO address) + { + UBY *p = memory_kick + ((address & 0xffffff) - 0xf80000); + return memoryReadWordFromPointer(p); + } + + ULO memoryKickReadLong(ULO address) + { + UBY *p = memory_kick + ((address & 0xffffff) - 0xf80000); + return memoryReadLongFromPointer(p); + } + + void memoryKickWriteByte(UBY data, ULO address) + { + // NOP + } + + void memoryKickWriteWord(UWO data, ULO address) + { + // NOP + } + + void memoryKickWriteLong(ULO data, ULO address) + { + // NOP + } + + void memoryKickMap(void) + { + ULO bank, basebank; + + basebank = memory_kickimage_basebank & 0xf8; + for (bank = basebank; + bank < (basebank + 8); + bank++) + memoryBankSet(memoryKickReadByte, + memoryKickReadWord, + memoryKickReadLong, + memoryKickWriteByte, + memoryKickWriteWord, + memoryKickWriteLong, + memory_kick, + bank, + memory_kickimage_basebank, + FALSE); + } + + /*============================================================================*/ + /* An error occured during loading a kickstart file. Uses GUI to display */ + /* an errorstring. */ + /*============================================================================*/ + + void memoryKickError(ULO errorcode, ULO data) + { + static STR error1[80], error2[160], error3[160]; + + sprintf(error1, "Kickstart file could not be loaded"); + sprintf(error2, "%s", memory_kickimage); + error3[0] = '\0'; + switch (errorcode) + { + case MEMORY_ROM_ERROR_SIZE: + sprintf(error3, + "Illegal size: %d bytes, size must be either 256K or 512K", + data); + break; + case MEMORY_ROM_ERROR_AMIROM_VERSION: + sprintf(error3, "Unsupported encryption method, version found was %d", + data); + break; + case MEMORY_ROM_ERROR_AMIROM_READ: + sprintf(error3, "Read error in encrypted Kickstart or keyfile"); + break; + case MEMORY_ROM_ERROR_KEYFILE: + sprintf(error3, "Unable to access keyfile %s", memory_key); + break; + case MEMORY_ROM_ERROR_EXISTS_NOT: + sprintf(error3, "File does not exist"); + break; + case MEMORY_ROM_ERROR_FILE: + sprintf(error3, "File is a directory"); + break; + case MEMORY_ROM_ERROR_KICKDISK_NOT: + sprintf(error3, "The ADF-image is not a kickdisk"); + break; + case MEMORY_ROM_ERROR_CHECKSUM: + sprintf(error3, + "The Kickstart image has a checksum error, checksum is %X", + data); + break; + case MEMORY_ROM_ERROR_KICKDISK_SUPER: + sprintf(error3, + "The ADF-image contains a superkickstart. Fellow can not handle it."); + break; + case MEMORY_ROM_ERROR_BAD_BANK: + sprintf(error3, "The ROM has a bad baseaddress: %X", + memory_kickimage_basebank*0x10000); + break; + } + wguiRequester(error1, error2, error3); + memoryKickSettingsClear(); + } + + /*============================================================================*/ + /* Returns the checksum of the current kickstart image. */ + /*============================================================================*/ + + ULO memoryKickChksum(void) + { + ULO sum, lastsum, i; + + sum = lastsum = 0; + for (i = 0; i < 0x80000; i += 4) { + UBY *p = memory_kick + i; + sum += memoryReadLongFromPointer(p); + if (sum < lastsum) sum++; + lastsum = sum; + } + return ~sum; + } + + /*============================================================================*/ + /* Identifies a loaded Kickstart */ + /*============================================================================*/ + + STR *memoryKickIdentify(STR *s) + { + UBY *rom = memory_kick; + ULO ver, rev; + + ver = (rom[12] << 8) | rom[13]; + rev = (rom[14] << 8) | rom[15]; + if (ver == 65535) memory_kickimage_version = 28; + else if (ver < 29) memory_kickimage_version = 29; + else if (ver > 41) memory_kickimage_version = 41; + else memory_kickimage_version = ver; + sprintf(s, + "%s (%d.%d)", + memory_kickimage_versionstrings[memory_kickimage_version - 28], + ver, + rev); + return s; + } + + /*============================================================================*/ + /* Verifies that a loaded Kickstart is OK */ + /*============================================================================*/ + + void memoryKickOK(void) + { + ULO chksum, basebank; + + if ((chksum = memoryKickChksum()) != 0) + memoryKickError(MEMORY_ROM_ERROR_CHECKSUM, chksum); + else + { + basebank = memory_kick[5]; + if ((basebank == 0xf8) || (basebank == 0xfc)) { + memory_kickimage_basebank = basebank; + memory_kickimage_none = FALSE; + memoryKickIdentify(memory_kickimage_versionstr); + memory_initial_PC = memoryReadLongFromPointer((memory_kick + 4)); + memory_initial_SP = memoryReadLongFromPointer(memory_kick); + } + else + memoryKickError(MEMORY_ROM_ERROR_BAD_BANK, basebank); + } + } + + /*============================================================================*/ + /* Returns size of decoded kickstart */ + /*============================================================================*/ + + int memoryKickDecodeAF(STR *filename, STR *keyfile) + { + STR *keybuffer = NULL; + ULO keysize, filesize = 0, keypos = 0, c; + FILE *KF, *RF; + + /* Read key */ + + if ((KF = fopen(keyfile, "rb")) != NULL) + { + fseek(KF, 0, SEEK_END); + keysize = ftell(KF); + keybuffer = (STR*)malloc(keysize); + if (keybuffer != NULL) + { + fseek(KF, 0, SEEK_SET); + fread(keybuffer, 1, keysize, KF); + } + fclose(KF); + } + else + { +#ifdef WIN32 + HMODULE hAmigaForeverDLL; + STR *strLibName = TEXT("amigaforever.dll"); + STR strPath[CFG_FILENAME_LENGTH]; + + hAmigaForeverDLL = LoadLibrary(strLibName); + if (!hAmigaForeverDLL) + { + DWORD dwRet; + STR strAmigaForeverRoot[CFG_FILENAME_LENGTH] = ""; + dwRet = GetEnvironmentVariable("AMIGAFOREVERROOT", strAmigaForeverRoot, CFG_FILENAME_LENGTH); + if((dwRet > 0) && strAmigaForeverRoot) { + TCHAR strTemp[CFG_FILENAME_LENGTH]; + _tcscpy(strTemp, strAmigaForeverRoot); + if (strTemp[_tcslen(strTemp) - 1] == '/' || strTemp[_tcslen(strTemp) - 1] == '\\') + _tcscat(strTemp, TEXT("\\")); + _stprintf(strPath, TEXT("%sPlayer\\%s"), strTemp, strLibName); + hAmigaForeverDLL = LoadLibrary(strPath); + } + + if (hAmigaForeverDLL) + { + typedef DWORD (STDAPICALLTYPE *PFN_GetKey)(LPVOID lpvBuffer, DWORD dwSize); + PFN_GetKey pfnGetKey = (PFN_GetKey)GetProcAddress(hAmigaForeverDLL, "GetKey"); + if (pfnGetKey) + { + keysize = pfnGetKey(NULL, 0); + if (keysize) + { + keybuffer = (STR*)malloc(keysize); + + if (keybuffer) + { + if (pfnGetKey(keybuffer, keysize) == keysize) + { + // key successfully retrieved + } + else + { + memoryKickError(MEMORY_ROM_ERROR_KEYFILE, 0); + return -1; + } + } + } + } + FreeLibrary(hAmigaForeverDLL); + } +#endif + } + + if (!keybuffer) + { + memoryKickError(MEMORY_ROM_ERROR_KEYFILE, 0); + return -1; + } + } + + if (!keybuffer) + return -1; + + /* Read file */ + + if ((RF = fopen(filename, "rb")) != NULL) + { + fseek(RF, 11, SEEK_SET); + while (((c = fgetc(RF)) != EOF) && filesize < 524288) + { + if (keysize != 0) + c ^= keybuffer[keypos++]; + if (keypos == keysize) + keypos = 0; + memory_kick[filesize++] = (UBY) c; + } + while ((c = fgetc(RF)) != EOF) + filesize++; + fclose(RF); + free(keybuffer); + return filesize; + } + free(keybuffer); + return -1; + } + + /*============================================================================*/ + /* Load Amiga Forever encrypted ROM-files */ + /* Return TRUE if file was handled, that is both if the file is */ + /* valid, or has wrong version */ + /*============================================================================*/ + + int memoryKickLoadAF2(FILE *F) + { + ULO version; + STR IDString[12]; + + fread(IDString, 11, 1, F); + version = IDString[10] - '0'; + IDString[10] = '\0'; + if (stricmp(IDString, "AMIROMTYPE") == 0) + { /* Header seems OK */ + if (version != 1) + { + memoryKickError(MEMORY_ROM_ERROR_AMIROM_VERSION, version); + return TRUE; /* File was handled */ + } + else + { /* Seems to be a file we can handle */ + ULO size; + + fclose(F); + + size = memoryKickDecodeAF(memory_kickimage, + memory_key); + if (size == -1) + { + memoryKickError(MEMORY_ROM_ERROR_AMIROM_READ, 0); + return TRUE; + } + if (size != 262144 && size != 524288) + { + memoryKickError(MEMORY_ROM_ERROR_SIZE, size); + return TRUE; + } + if (size == 262144) + memcpy(memory_kick + 262144, memory_kick, 262144); + memory_kickimage_none = FALSE; + memoryKickIdentify(memory_kickimage_versionstr); + return TRUE; + } + } + /* Here, header was not recognized */ + return FALSE; + } + + /*============================================================================*/ + /* Detect and load kickdisk */ + /* Based on information provided by Jerry Lawrence */ + /*============================================================================*/ + + void memoryKickDiskLoad(FILE *F) + { + STR head[5]; + + /* Check header */ + + fseek(F, 0, SEEK_SET); + fread(head, 4, 1, F); + head[4] = '\0'; + if (strcmp(head, "KICK") != 0) + { + memoryKickError(MEMORY_ROM_ERROR_KICKDISK_NOT, 0); + return; + } + fread(head, 3, 1, F); + head[3] = '\0'; + if (strcmp(head, "SUP") == 0) + { + memoryKickError(MEMORY_ROM_ERROR_KICKDISK_SUPER, 0); + return; + } + fseek(F, 512, SEEK_SET); /* Load image */ + fread(memory_kick, 262144, 1, F); + memcpy(memory_kick + 262144, memory_kick, 262144); + } + + /*============================================================================*/ + /* memory_kickimage is the file we want to load */ + /*============================================================================*/ + + void memoryKickLoad(void) + { + FILE *F; + BOOLE kickdisk = FALSE; + STR *suffix, *lastsuffix; + BOOLE afkick = FALSE; + + /* New file is different from previous */ + /* Must load file */ + + fs_navig_point *fsnp; + + memory_kickimage_none = FALSE;/* Initially Kickstart is expected to be OK */ + if ((fsnp = fsWrapMakePoint(memory_kickimage)) == NULL) + memoryKickError(MEMORY_ROM_ERROR_EXISTS_NOT, 0); + else + { + if (fsnp->type != FS_NAVIG_FILE) + memoryKickError(MEMORY_ROM_ERROR_FILE, 0); + else + { /* File passed initial tests */ + if ((F = fopen(memory_kickimage, "rb")) == NULL) + memoryKickError(MEMORY_ROM_ERROR_EXISTS_NOT, 0); + else memory_kickimage_size = fsnp->size; + } + free(fsnp); + } + + /* Either the file is open, or memory_kickimage_none is TRUE */ + + if (!memory_kickimage_none) + { + + /* File opened successfully */ + + /* Kickdisk flag */ + + suffix = strchr(memory_kickimage, '.'); + if (suffix != NULL) + { + lastsuffix = suffix; + while ((suffix = strchr(lastsuffix + 1, '.')) != NULL) + lastsuffix = suffix; + kickdisk = (stricmp(lastsuffix + 1, "ADF") == 0); + } + /* mem_loadrom_af2 will return TRUE if file was handled */ + /* Handled also means any error conditions */ + /* The result can be that no kickstart was loaded */ + + if (kickdisk) + memoryKickDiskLoad(F); + else + afkick = memoryKickLoadAF2(F); + if (!kickdisk && !afkick) + { /* Normal kickstart image */ + fseek(F, 0, SEEK_SET); + if (memory_kickimage_size == 262144) + { /* Load 256k ROM */ + fread(memory_kick, 1, 262144, F); + memcpy(memory_kick + 262144, memory_kick, 262144); + } + else if (memory_kickimage_size == 524288)/* Load 512k ROM */ + fread(memory_kick, 1, 524288, F); + else + { /* Rom size is wrong */ + memoryKickError(MEMORY_ROM_ERROR_SIZE, memory_kickimage_size); + } + fclose(F); + } + } + if (!memory_kickimage_none) + memoryKickOK(); + } + + /*============================================================================*/ + /* Clear memory used for kickstart image */ + /*============================================================================*/ + + void memoryKickClear(void) + { + memset(memory_kick, 0, 0x80000); + } + + /*============================================================================*/ + /* Top-level memory access functions */ + /*============================================================================*/ + + /*============================================================================== + Raises exception 3 when a word or long is accessing an odd address + and the CPU is < 020 + ==============================================================================*/ + + static void memoryOddRead(ULO address) + { + if (address & 1) + { + if (cpuGetModelMajor() < 2) + { + memory_fault_read = TRUE; + memory_fault_address = address; + cpuThrowAddressErrorException(); + } + } + } + + static void memoryOddWrite(ULO address) + { + if (address & 1) + { + if (cpuGetModelMajor() < 2) + { + memory_fault_read = FALSE; + memory_fault_address = address; + cpuThrowAddressErrorException(); + } + } + } + + UBY memoryReadByteViaBankHandler(ULO address) + { + return memory_bank_readbyte[address >> 16](address); + } + +__inline UBY memoryReadByte(ULO address) + { + UBY *memory_ptr = memory_bank_pointer[address>>16]; + if (memory_ptr != NULL) + { + UBY *p = memory_ptr + address; + return memoryReadByteFromPointer(p); + } + return memoryReadByteViaBankHandler(address); + } + + UWO memoryReadWordViaBankHandler(ULO address) + { + memoryOddRead(address); + return memory_bank_readword[address >> 16](address); + } + +__inline UWO memoryReadWord(ULO address) + { + UBY *memory_ptr = memory_bank_pointer[address>>16]; + if ((memory_ptr != NULL) && !(address & 1)) + { + UBY *p = memory_ptr + address; + return memoryReadWordFromPointer(p); + } + return memoryReadWordViaBankHandler(address); + } + + ULO memoryReadLongViaBankHandler(ULO address) + { + memoryOddRead(address); + return memory_bank_readlong[address >> 16](address); + } + + __inline ULO memoryReadLong(ULO address) + { + UBY *memory_ptr = memory_bank_pointer[address>>16]; + if ((memory_ptr != NULL) && !(address & 1)) + { + UBY *p = memory_ptr + address; + return memoryReadLongFromPointer(p); + } + return memoryReadLongViaBankHandler(address); + } + + void memoryWriteByte(UBY data, ULO address) + { + ULO bank = address>>16; + if (memory_bank_pointer_can_write[bank]) + { + memoryWriteByteToPointer(data, memory_bank_pointer[bank] + address); + } + else + { + memory_bank_writebyte[bank](data, address); + } + } + + void memoryWriteWordViaBankHandler(UWO data, ULO address) + { + memoryOddWrite(address); + memory_bank_writeword[address >> 16](data, address); + } + + void memoryWriteWord(UWO data, ULO address) + { + ULO bank = address>>16; + if (memory_bank_pointer_can_write[bank] && !(address & 1)) + { + memoryWriteWordToPointer(data, memory_bank_pointer[bank] + address); + } + else + { + memoryWriteWordViaBankHandler(data, address); + } + } + + void memoryWriteLongViaBankHandler(ULO data, ULO address) + { + memoryOddWrite(address); + memory_bank_writelong[address >> 16](data, address); + } + + void memoryWriteLong(ULO data, ULO address) + { + ULO bank = address>>16; + if (memory_bank_pointer_can_write[bank] && !(address & 1)) + { + memoryWriteLongToPointer(data, memory_bank_pointer[bank] + address); + } + else + { + memoryWriteLongViaBankHandler(data, address); + } + } + + /*============================================================================*/ + /* Memory configuration interface */ + /*============================================================================*/ + + BOOLE memorySetChipSize(ULO chipsize) + { + BOOLE needreset = (memory_chipsize != chipsize); + memory_chipsize = chipsize; + return needreset; + } + + ULO memoryGetChipSize(void) + { + return memory_chipsize; + } + + BOOLE memorySetFastSize(ULO fastsize) + { + BOOLE needreset = (memory_fastsize != fastsize); + memory_fastsize = fastsize; + if (needreset) memoryFastAllocate(); + return needreset; + } + + ULO memoryGetFastSize(void) + { + return memory_fastsize; + } + + void memorySetFastAllocatedSize(ULO fastallocatedsize) + { + memory_fastallocatedsize = fastallocatedsize; + } + + ULO memoryGetFastAllocatedSize(void) + { + return memory_fastallocatedsize; + } + + BOOLE memorySetSlowSize(ULO slowsize) + { + BOOLE needreset = (memory_slowsize != slowsize); + memory_slowsize = slowsize; + return needreset; + } + + ULO memoryGetSlowSize(void) + { + return memory_slowsize; + } + + BOOLE memorySetUseAutoconfig(BOOLE useautoconfig) + { + BOOLE needreset = memory_useautoconfig != useautoconfig; + memory_useautoconfig = useautoconfig; + return needreset; + } + + BOOLE memoryGetUseAutoconfig(void) + { + return memory_useautoconfig; + } + + BOOLE memorySetAddress32Bit(BOOLE address32bit) + { + BOOLE needreset = memory_address32bit != address32bit; + memory_address32bit = address32bit; + return needreset; + } + + BOOLE memoryGetAddress32Bit(void) + { + return memory_address32bit; + } + + BOOLE memorySetKickImage(STR *kickimage) + { + BOOLE needreset = !!strncmp(memory_kickimage, kickimage, CFG_FILENAME_LENGTH); + strncpy(memory_kickimage, kickimage, CFG_FILENAME_LENGTH); + if (needreset) memoryKickLoad(); + return needreset; + } + + STR *memoryGetKickImage(void) + { + return memory_kickimage; + } + + void memorySetKey(STR *key) + { + strncpy(memory_key, key, CFG_FILENAME_LENGTH); + } + + STR *memoryGetKey(void) + { + return memory_key; + } + + ULO memoryGetKickImageBaseBank(void) + { + return memory_kickimage_basebank; + } + + ULO memoryGetKickImageVersion(void) + { + return memory_kickimage_version; + } + + BOOLE memoryGetKickImageOK(void) + { + return !memory_kickimage_none; + } + + ULO memoryInitialPC(void) + { + return memory_initial_PC; + } + + ULO memoryInitialSP(void) + { + return memory_initial_SP; + } + + /*============================================================================*/ + /* Sets all settings a clean state */ + /*============================================================================*/ + + void memoryChipSettingsClear(void) + { + memorySetChipSize(0x200000); + memoryChipClear(); + } + + void memoryFastSettingsClear(void) + { + memory_fast = NULL; + memory_fast_baseaddress = 0; + memorySetFastAllocatedSize(0); + memorySetFastSize(0); + } + + void memorySlowSettingsClear(void) + { + memorySetSlowSize(0x1c0000); + memorySlowClear(); + } + + void memoryIoSettingsClear(void) + { + memoryIoClear(); + } + + void memoryKickSettingsClear(void) + { + memory_kickimage[0] = '\0'; + memory_kickimage_none = TRUE; + memoryKickClear(); + } + + void memoryEmemSettingsClear(void) + { + memoryEmemCardsRemove(); + memoryEmemClear(); + } + + void memoryDmemSettingsClear(void) + { + memoryDmemSetCounter(0); + memoryDmemClear(); + } + + void memoryNoiseSettingsClear(void) + { + memory_noise[0] = 0; + memory_noise[1] = 0xffffffff; + memory_noisecounter = 0; + } + + void memoryMysterySettingsClear(void) + { + memory_mystery_value = 0xff00ff00; + } + + void memoryBankSettingsClear(void) + { + memoryBankClearAll(); + } + + void memoryIoHandlersInstall(void) + { + memorySetIoReadStub(0x018, rserdatr); + memorySetIoReadStub(0x01c, rintenar); + memorySetIoReadStub(0x01e, rintreqr); + memorySetIoWriteStub(0x09a, wintena); + memorySetIoWriteStub(0x09c, wintreq); + } + + /*==============*/ + /* Generic init */ + /*==============*/ + + void memorySaveState(FILE *F) + { + fwrite(&memory_chipsize, sizeof(memory_chipsize), 1, F); + fwrite(&memory_slowsize, sizeof(memory_slowsize), 1, F); + fwrite(&memory_fastsize, sizeof(memory_fastsize), 1, F); + if (memory_chipsize > 0) + { + fwrite(&memory_chip[0], sizeof(UBY), memory_chipsize, F); + } + if (memory_slowsize > 0) + { + fwrite(&memory_slow[0], sizeof(UBY), memory_slowsize, F); + } + if (memory_fastsize > 0) + { + fwrite(memory_fast, sizeof(UBY), memory_fastsize, F); + } + } + + void memoryLoadState(FILE *F) + { + fread(&memory_chipsize, sizeof(memory_chipsize), 1, F); + fread(&memory_slowsize, sizeof(memory_slowsize), 1, F); + fread(&memory_fastsize, sizeof(memory_fastsize), 1, F); + if (memory_chipsize > 0) + { + fread(&memory_chip[0], sizeof(UBY), memory_chipsize, F); + } + if (memory_slowsize > 0) + { + fread(&memory_slow[0], sizeof(UBY), memory_slowsize, F); + } + if (memory_fastsize > 0) + { + fread(memory_fast, sizeof(UBY), memory_fastsize, F); + } + } + + void memoryEmulationStart(void) + { + memoryIoClear(); + memoryIoHandlersInstall(); + } + + void memoryEmulationStop(void) + { + } + + void memorySoftReset(void) + { + memoryDmemClear(); + memoryEmemClear(); + memoryEmemCardsRemove(); + memoryFastCardAdd(); + intreq = intena = intenar = 0; + memoryBankClearAll(); + memoryChipMap(TRUE); + memorySlowMap(); + memoryIoMap(); + memoryEmemMap(); + memoryDmemMap(); + memoryMysteryMap(); + memoryKickMap(); + } + + void memoryHardReset(void) + { + memoryChipClear(), + memoryFastClear(); + memorySlowClear(); + memoryDmemClear(); + memoryEmemClear(); + memoryEmemCardsRemove(); + memoryFastCardAdd(); + intreq = intena = intenar = 0; + memoryBankClearAll(); + memoryChipMap(TRUE); + memorySlowMap(); + memoryIoMap(); + memoryEmemMap(); + memoryDmemMap(); + memoryMysteryMap(); + memoryKickMap(); + } + + void memoryHardResetPost(void) + { + memoryEmemCardInit(); + } + + void memoryStartup(void) + { + memorySetAddress32Bit(TRUE); + memoryBankSettingsClear(); + memorySetAddress32Bit(FALSE); + memoryChipSettingsClear(); + memoryFastSettingsClear(); + memorySlowSettingsClear(); + memoryIoSettingsClear(); + memoryKickSettingsClear(); + memoryEmemSettingsClear(); + memoryDmemSettingsClear(); + memoryNoiseSettingsClear(); + memoryMysterySettingsClear(); /* ;-) */ + } + + void memoryShutdown(void) + { + memoryFastFree(); + } + diff --git a/cpu/fmem.h b/cpu/fmem.h new file mode 100644 index 0000000..e5b9702 --- /dev/null +++ b/cpu/fmem.h @@ -0,0 +1,152 @@ +#ifndef FMEM_H +#define FMEM_H + +/* Memory access functions */ + +extern UBY memoryReadByte(ULO address); +extern UWO memoryReadWord(ULO address); +extern ULO memoryReadLong(ULO address); +extern void memoryWriteByte(UBY data, ULO address); +extern void memoryWriteWord(UWO data, ULO address); +extern void memoryWriteLong(ULO data, ULO address); + +extern UWO memoryChipReadWord(ULO address); +extern void memoryChipWriteWord(UWO data, ULO address); + +#define memoryReadByteFromPointer(address) (address[0]) +#define memoryReadWordFromPointer(address) ((address[0] << 8) | address[1]) +#define memoryReadLongFromPointer(address) ((address[0] << 24) | (address[1] << 16) | (address[2] << 8) | address[3]) + +/* IO Bank functions */ + +typedef UWO (*memoryIoReadFunc)(ULO address); +typedef void (*memoryIoWriteFunc)(UWO data, ULO address); + +extern void memorySetIoReadStub(ULO index, memoryIoReadFunc ioreadfunction); +extern void memorySetIoWriteStub(ULO index, memoryIoWriteFunc iowritefunction); + +/* For the copper */ +extern memoryIoWriteFunc memory_iobank_write[257]; + +/* Expansion card functions */ + +typedef void (*memoryEmemCardInitFunc)(void); +typedef void (*memoryEmemCardMapFunc)(ULO); + +extern void memoryEmemClear(void); +extern void memoryEmemCardAdd(memoryEmemCardInitFunc cardinit, + memoryEmemCardMapFunc cardmap); +extern void memoryEmemSet(ULO index, ULO data); +extern void memoryEmemMirror(ULO emem_offset, UBY *src, ULO size); + +/* Device memory functions. fhfile is using these. */ + +extern void memoryDmemSetByte(UBY data); +extern void memoryDmemSetWord(UWO data); +extern void memoryDmemSetLong(ULO data); +extern void memoryDmemSetLongNoCounter(ULO data, ULO offset); +extern void memoryDmemSetString(STR *data); +extern void memoryDmemSetCounter(ULO val); +extern ULO memoryDmemGetCounter(void); +extern void memoryDmemClear(void); + +/* Module management functions */ + +extern void memorySaveState(FILE *F); +extern void memoryLoadState(FILE *F); +extern void memorySoftReset(void); +extern void memoryHardReset(void); +extern void memoryHardResetPost(void); +extern void memoryEmulationStart(void); +extern void memoryEmulationStop(void); +extern void memoryStartup(void); +extern void memoryShutdown(void); + +/* Memory bank functions */ + +typedef UBY (*memoryReadByteFunc)(ULO address); +typedef UWO (*memoryReadWordFunc)(ULO address); +typedef ULO (*memoryReadLongFunc)(ULO address); +typedef void (*memoryWriteByteFunc)(UBY data, ULO address); +typedef void (*memoryWriteWordFunc)(UWO data, ULO address); +typedef void (*memoryWriteLongFunc)(ULO data, ULO address); + +extern memoryReadByteFunc memory_bank_readbyte[65536]; +extern memoryReadWordFunc memory_bank_readword[65536]; +extern memoryReadLongFunc memory_bank_readlong[65536]; +extern memoryWriteByteFunc memory_bank_writebyte[65536]; +extern memoryWriteWordFunc memory_bank_writeword[65536]; +extern memoryWriteLongFunc memory_bank_writelong[65536]; + +extern UBY *memory_bank_pointer[65536]; +extern UBY *memory_bank_datapointer[65536]; + +extern void memoryBankSet(memoryReadByteFunc rb, + memoryReadWordFunc rw, + memoryReadLongFunc rl, + memoryWriteByteFunc wb, + memoryWriteWordFunc ww, + memoryWriteLongFunc wl, + UBY *basep, + ULO bank, + ULO basebank, + BOOLE pointer_can_write); +extern UBY *memoryAddressToPtr(ULO address); +extern void memoryChipMap(BOOLE overlay); + +/* Memory configuration properties */ + +extern BOOLE memorySetChipSize(ULO chipsize); +extern ULO memoryGetChipSize(void); +extern BOOLE memorySetFastSize(ULO fastsize); +extern ULO memoryGetFastSize(void); +extern void memorySetFastAllocatedSize(ULO fastallocatedsize); +extern ULO memoryGetFastAllocatedSize(void); +extern BOOLE memorySetSlowSize(ULO bogosize); +extern ULO memoryGetSlowSize(void); +extern BOOLE memorySetUseAutoconfig(BOOLE useautoconfig); +extern BOOLE memoryGetUseAutoconfig(void); +extern BOOLE memorySetAddress32Bit(BOOLE address32bit); +extern BOOLE memoryGetAddress32Bit(void); +extern BOOLE memorySetKickImage(STR *kickimage); +extern STR *memoryGetKickImage(void); +extern void memorySetKey(STR *key); +extern STR *memoryGetKey(void); +extern BOOLE memoryGetKickImageOK(void); + +/* Derived from memory configuration */ + +extern ULO memoryGetKickImageBaseBank(void); +extern ULO memoryGetKickImageVersion(void); +extern ULO memoryInitialPC(void); +extern ULO memoryInitialSP(void); + +/* Kickstart load error handling */ + +#define MEMORY_ROM_ERROR_SIZE 0 +#define MEMORY_ROM_ERROR_AMIROM_VERSION 1 +#define MEMORY_ROM_ERROR_AMIROM_READ 2 +#define MEMORY_ROM_ERROR_KEYFILE 3 +#define MEMORY_ROM_ERROR_EXISTS_NOT 4 +#define MEMORY_ROM_ERROR_FILE 5 +#define MEMORY_ROM_ERROR_KICKDISK_NOT 6 +#define MEMORY_ROM_ERROR_CHECKSUM 7 +#define MEMORY_ROM_ERROR_KICKDISK_SUPER 8 +#define MEMORY_ROM_ERROR_BAD_BANK 9 + +/* Global variables */ + +extern UBY memory_chip[]; +extern UBY *memory_fast; +extern UBY memory_slow[]; +extern UBY memory_kick[]; +extern ULO memory_chipsize; +extern UBY memory_emem[]; + +extern ULO intenar,intena,intreq; +extern ULO potgor; + +extern ULO memory_fault_address; +extern BOOLE memory_fault_read; + +#endif