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459 lines
13 KiB
C
459 lines
13 KiB
C
/* @(#) $Id: CpuIntegration.c,v 1.10 2013/01/08 19:17:33 peschau Exp $ */
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/*=========================================================================*/
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/* Fellow */
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/* Initialization of 68000 core */
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/* Integrates the 68k emulation with custom chips */
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/* */
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/* Author: Petter Schau */
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/* */
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/* Copyright (C) 1991, 1992, 1996 Free Software Foundation, Inc. */
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/* */
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/* This program is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU General Public License as published by */
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/* the Free Software Foundation; either version 2, or (at your option) */
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/* any later version. */
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/* */
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/* This program is distributed in the hope that it will be useful, */
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/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
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/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
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/* GNU General Public License for more details. */
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/* */
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/* You should have received a copy of the GNU General Public License */
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/* along with this program; if not, write to the Free Software Foundation, */
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/* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/*=========================================================================*/
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#include "defs.h"
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#include "fellow.h"
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#include "fmem.h"
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#include "CpuModule.h"
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#include "CpuIntegration.h"
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#include "CpuModule_Internal.h"
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//#include "bus.h"
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//#include "fileops.h"
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jmp_buf cpu_integration_exception_buffer;
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/* custom chip intreq bit-number to irq-level */
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static ULO cpu_integration_int_to_level[16] = {1,1,1,2, 3,3,3,4, 4,4,4,5, 5,6,6,7};
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static ULO cpu_integration_irq_source;
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/* Cycles spent by chips (Blitter) as a result of an instruction */
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static ULO cpu_integration_chip_cycles;
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static ULO cpu_integration_chip_slowdown;
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/*===========================================================================*/
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/* CPU properties */
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/*===========================================================================*/
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ULO cpu_integration_speed; // The speed as expressed in the fellow configuration settings
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ULO cpu_integration_speed_multiplier; // The cycle multiplier used to adjust the cpu-speed, calculated from cpu_integration_speed
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cpu_integration_models cpu_integration_model; // The cpu model as expressed in the fellow configuration settings
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/*===========================================================================*/
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/* CPU properties */
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/*===========================================================================*/
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void cpuIntegrationSetSpeed(ULO speed)
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{
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cpu_integration_speed = speed;
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}
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ULO cpuIntegrationGetSpeed(void)
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{
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return cpu_integration_speed;
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}
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static void cpuIntegrationSetSpeedMultiplier(ULO multiplier)
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{
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cpu_integration_speed_multiplier = multiplier;
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}
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static ULO cpuIntegrationGetSpeedMultiplier(void)
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{
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return cpu_integration_speed_multiplier;
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}
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static void cpuIntegrationCalculateMultiplier(void)
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{
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ULO multiplier = 12;
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switch (cpuGetModelMajor())
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{
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case 0:
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multiplier = 12;
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break;
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case 1:
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multiplier = 12;
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break;
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case 2:
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multiplier = 11;
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break;
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case 3:
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multiplier = 11;
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break;
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}
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if (cpuIntegrationGetSpeed() >= 8) cpuIntegrationSetSpeedMultiplier(multiplier);
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else if (cpuIntegrationGetSpeed() >= 4) cpuIntegrationSetSpeedMultiplier(multiplier - 1);
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else if (cpuIntegrationGetSpeed() >= 2) cpuIntegrationSetSpeedMultiplier(multiplier - 2);
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else if (cpuIntegrationGetSpeed() >= 1) cpuIntegrationSetSpeedMultiplier(multiplier - 3);
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else cpuIntegrationSetSpeedMultiplier(multiplier - 4);
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}
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BOOLE cpuIntegrationSetModel(cpu_integration_models model)
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{
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BOOLE needreset = (cpu_integration_model != model);
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cpu_integration_model = model;
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switch (cpu_integration_model)
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{
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case M68000: cpuSetModel(0, 0); break;
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case M68010: cpuSetModel(1, 0); break;
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case M68020: cpuSetModel(2, 0); break;
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case M68030: cpuSetModel(3, 0); break;
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case M68EC20: cpuSetModel(2, 1); break;
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case M68EC30: cpuSetModel(3, 1); break;
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}
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return needreset;
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}
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cpu_integration_models cpuIntegrationGetModel(void)
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{
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return cpu_integration_model;
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}
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void cpuIntegrationSetChipCycles(ULO chip_cycles)
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{
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cpu_integration_chip_cycles = chip_cycles;
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}
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ULO cpuIntegrationGetChipCycles(void)
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{
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return cpu_integration_chip_cycles;
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}
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void cpuIntegrationSetChipSlowdown(ULO chip_slowdown)
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{
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cpu_integration_chip_slowdown = chip_slowdown;
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}
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ULO cpuIntegrationGetChipSlowdown(void)
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{
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return cpu_integration_chip_slowdown;
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}
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ULO cpuIntegrationGetChipIrqToIntLevel(ULO chip_irq)
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{
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return cpu_integration_int_to_level[chip_irq];
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}
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void cpuIntegrationSetIrqSource(ULO irq_source)
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{
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cpu_integration_irq_source = irq_source;
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}
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ULO cpuIntegrationGetIrqSource(void)
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{
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return cpu_integration_irq_source;
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}
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/*=====================================================
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Checking for waiting interrupts
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=====================================================*/
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static BOOLE cpuIntegrationCheckPendingInterruptsFunc(void)
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{
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ULO current_cpu_level = (cpuGetSR() >> 8) & 7;
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BOOLE chip_irqs_enabled = !!(intena & 0x4000);
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if (chip_irqs_enabled)
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{
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LON highest_chip_irq;
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ULO chip_irqs = intreq & intena;
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if (chip_irqs == 0) return FALSE;
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for (highest_chip_irq = 13; highest_chip_irq >= 0; highest_chip_irq--)
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{
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if (chip_irqs & (1 << highest_chip_irq))
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{
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// Found a chip-irq that is both flagged and enabled.
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ULO highest_chip_level = cpuIntegrationGetChipIrqToIntLevel(highest_chip_irq);
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if (highest_chip_level > current_cpu_level)
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{
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cpuSetIrqLevel(highest_chip_level);
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cpuSetIrqAddress(memoryReadLong(cpuGetVbr() + 0x60 + highest_chip_level*4));
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cpuIntegrationSetIrqSource(highest_chip_irq);
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if (cpuGetStop())
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{
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cpuSetStop(FALSE);
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cpuEvent.cycle = bus.cycle;
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}
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return TRUE;
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}
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}
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}
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}
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return FALSE;
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}
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void cpuIntegrationCheckPendingInterrupts(void)
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{
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cpuCheckPendingInterrupts();
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}
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/*=========================================*/
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/* Exception mid-instruction exit function */
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/*=========================================*/
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void cpuIntegrationMidInstructionExceptionFunc(void)
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{
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longjmp(cpu_integration_exception_buffer, -1);
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}
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/*===================================================*/
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/* Handles reset exception event from the cpu-module */
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/*===================================================*/
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void cpuIntegrationResetExceptionFunc(void)
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{
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fellowSoftReset();
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}
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/*=========*/
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/* Logging */
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/*=========*/
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#ifdef CPU_INSTRUCTION_LOGGING
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FILE *CPUINSTRUCTIONLOG;
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int cpu_disable_instruction_log = TRUE;
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void cpuInstructionLogOpen(void)
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{
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if (CPUINSTRUCTIONLOG == NULL)
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{
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char filename[MAX_PATH];
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fileopsGetGenericFileName(filename, "WinFellow", "cpuinstructions.log");
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CPUINSTRUCTIONLOG = fopen(filename, "w");
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}
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}
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void cpuIntegrationPrintBusCycle(void)
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{
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fprintf(CPUINSTRUCTIONLOG, "%d:%.5d ", bus.frame_no, bus.cycle);
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}
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void cpuIntegrationInstructionLogging(void)
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{
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char saddress[256], sdata[256], sinstruction[256], soperands[256];
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if (cpu_disable_instruction_log) return;
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cpuInstructionLogOpen();
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/*
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fprintf(CPUINSTRUCTIONLOG,
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"D0:%.8X D1:%.8X D2:%.8X D3:%.8X D4:%.8X D5:%.8X D6:%.8X D7:%.8X\n",
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cpuGetDReg(0),
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cpuGetDReg(1),
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cpuGetDReg(2),
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cpuGetDReg(3),
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cpuGetDReg(4),
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cpuGetDReg(5),
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cpuGetDReg(6),
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cpuGetDReg(7));
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fprintf(CPUINSTRUCTIONLOG,
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"A0:%.8X A1:%.8X A2:%.8X A3:%.8X A4:%.8X A5:%.8X A6:%.8X A7:%.8X\n",
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cpuGetAReg(0),
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cpuGetAReg(1),
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cpuGetAReg(2),
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cpuGetAReg(3),
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cpuGetAReg(4),
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cpuGetAReg(5),
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cpuGetAReg(6),
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cpuGetAReg(7));
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*/
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saddress[0] = '\0';
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sdata[0] = '\0';
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sinstruction[0] = '\0';
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soperands[0] = '\0';
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cpuDisOpcode(cpuGetPC(), saddress, sdata, sinstruction, soperands);
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fprintf(CPUINSTRUCTIONLOG, "SSP:%.6X USP:%.6X SP:%.4X %s %s\t%s\t%s\n", cpuGetSspDirect(), cpuGetUspDirect(), cpuGetSR(), saddress, sdata, sinstruction, soperands);
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}
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void cpuIntegrationExceptionLogging(STR *description, ULO original_pc, UWO opcode)
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{
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if (cpu_disable_instruction_log) return;
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cpuInstructionLogOpen();
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cpuIntegrationPrintBusCycle();
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fprintf(CPUINSTRUCTIONLOG, "%s for opcode %.4X at PC %.8X from PC %.8X\n", description, opcode, original_pc, cpuGetPC());
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}
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STR *cpuIntegrationGetInterruptName(ULO chip_irq_no)
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{
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switch (chip_irq_no)
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{
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case 0: return "TBE: Output buffer of the serial port is empty.";
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case 1: return "DSKBLK: Disk DMA transfer ended.";
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case 2: return "SOFT: Software interrupt.";
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case 3: return "PORTS: From CIA-A or expansion port.";
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case 4: return "COPER: Copper interrupt.";
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case 5: return "VERTB: Start of vertical blank.";
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case 6: return "BLIT: Blitter done.";
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case 7: return "AUD0: Audio data on channel 0.";
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case 8: return "AUD1: Audio data on channel 1.";
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case 9: return "AUD2: Audio data on channel 2.";
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case 10: return "AUD3: Audio data on channel 3.";
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case 11: return "RBF: Input buffer of the serial port full.";
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case 12: return "DSKSYN: Disk sync value recognized.";
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case 13: return "EXTER: From CIA-B or expansion port.";
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case 14: return "INTEN: BUG! Not an interrupt.";
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case 15: return "NMI: BUG! Not an interrupt.";
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}
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return "Illegal interrupt source!";
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}
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void cpuIntegrationInterruptLogging(ULO level, ULO vector_address)
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{
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if (cpu_disable_instruction_log) return;
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cpuInstructionLogOpen();
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cpuIntegrationPrintBusCycle();
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fprintf(CPUINSTRUCTIONLOG, "Irq %d to %.6X (%s)\n", level, vector_address, cpuIntegrationGetInterruptName(cpuIntegrationGetIrqSource()));
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}
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#endif
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void cpuIntegrationExecuteInstructionEventHandler68000Fast(void)
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{
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ULO cycles;
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cycles = cpuExecuteInstruction();
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if (cpuGetStop())
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{
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cpuEvent.cycle = BUS_CYCLE_DISABLE;
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}
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else
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{
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cpuEvent.cycle += ((cycles*cpuIntegrationGetChipSlowdown())>>1) + cpuIntegrationGetChipCycles();
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}
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cpuIntegrationSetChipCycles(0);
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}
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void cpuIntegrationExecuteInstructionEventHandler68000General(void)
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{
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ULO cycles = 0;
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ULO time_used = 0;
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do
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{
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cycles = cpuExecuteInstruction();
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cycles = cycles*cpuIntegrationGetChipSlowdown(); // Compensate for blitter time
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time_used += (cpuIntegrationGetChipCycles()<<12) + (cycles<<cpuIntegrationGetSpeedMultiplier());
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}
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while (time_used < 8192 && !cpuGetStop());
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if (cpuGetStop())
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{
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cpuEvent.cycle = BUS_CYCLE_DISABLE;
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}
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else
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{
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cpuEvent.cycle += (time_used>>12);
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}
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cpuIntegrationSetChipCycles(0);
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}
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void cpuIntegrationExecuteInstructionEventHandler68020(void)
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{
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ULO time_used = 0;
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do
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{
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cpuExecuteInstruction();
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time_used += (cpuIntegrationGetChipCycles()<<12) + (4<<cpuIntegrationGetSpeedMultiplier());
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}
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while (time_used < 8192 && !cpuGetStop());
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if (cpuGetStop())
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{
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cpuEvent.cycle = BUS_CYCLE_DISABLE;
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}
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else
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{
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cpuEvent.cycle += (time_used>>12);
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}
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cpuIntegrationSetChipCycles(0);
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}
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void cpuIntegrationSetDefaultConfig(void)
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{
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cpuIntegrationSetModel(M68000);
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cpuIntegrationSetChipCycles(0);
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cpuIntegrationSetChipSlowdown(1);
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cpuIntegrationSetSpeed(4);
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cpuSetCheckPendingInterruptsFunc(cpuIntegrationCheckPendingInterruptsFunc);
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cpuSetMidInstructionExceptionFunc(cpuIntegrationMidInstructionExceptionFunc);
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cpuSetResetExceptionFunc(cpuIntegrationResetExceptionFunc);
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#ifdef CPU_INSTRUCTION_LOGGING
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cpuSetInstructionLoggingFunc(cpuIntegrationInstructionLogging);
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cpuSetExceptionLoggingFunc(cpuIntegrationExceptionLogging);
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cpuSetInterruptLoggingFunc(cpuIntegrationInterruptLogging);
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#endif
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}
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/*=========================*/
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/* Fellow lifecycle events */
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/*=========================*/
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void cpuIntegrationSaveState(FILE *F)
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{
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cpuSaveState(F);
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fwrite(&cpu_integration_chip_slowdown, sizeof(cpu_integration_chip_slowdown), 1, F);
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// Everything else is configuration options which will be set when the associated config-file is loaded.
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}
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void cpuIntegrationLoadState(FILE *F)
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{
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cpuLoadState(F);
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fread(&cpu_integration_chip_slowdown, sizeof(cpu_integration_chip_slowdown), 1, F);
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// Everything else is configuration options which will be set when the associated config-file is loaded.
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}
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void cpuIntegrationEmulationStart(void)
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{
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cpuIntegrationCalculateMultiplier();
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}
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void cpuIntegrationEmulationStop(void)
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{
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}
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void cpuIntegrationHardReset(void)
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{
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cpuIntegrationSetChipCycles(0);
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cpuIntegrationSetChipSlowdown(1);
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cpuSetInitialPC(memoryInitialPC());
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cpuSetInitialSP(memoryInitialSP());
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cpuHardReset();
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}
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void cpuIntegrationStartup(void)
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{
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cpuStartup();
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cpuIntegrationSetDefaultConfig();
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cpuCreateMulTimeTables();
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}
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void cpuIntegrationShutdown(void)
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{
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cpuProfileWrite();
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}
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