2017-11-19 04:11:07 +00:00
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; Contains the table used by Init.s:SetProcessorFlags, and a label to find it with.
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;
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; Using this table, three fields in KDP are set:
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; KDP.CpuSpecificByte1
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; KDP.CpuSpecificByte2 (immediately follows Byte1)
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; KDP.ProcessorInfo.ProcessorFlags
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ProcessorFlagsTable
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dcb.b 32 * (1 + 1 + 4), 0
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ProcessorFlagsTableEnd
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PflgTblCtr set 0
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macro
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PflgTblEnt &CpuSpecificByte1, &CpuSpecificByte2, &ProcessorFlags
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@fb
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org ProcessorFlagsTable + PflgTblCtr
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dc.b &CpuSpecificByte1
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org ProcessorFlagsTable + 32 + PflgTblCtr
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dc.b &CpuSpecificByte2
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org ProcessorFlagsTable + 64 + 4*PflgTblCtr
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dc.l &ProcessorFlags
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org @fb
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PflgTblCtr set PflgTblCtr + 1
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endm
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with NKProcessorInfo
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2018-03-09 11:46:39 +00:00
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; CpuSpecificByte2:
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HID0_NHR_only equ 1 ; Idle Power calls should set the HID0[NHR] bit
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HID0_NHR_and_sleep equ 2 ; ...and the HID0 bit that potentiates MSR[POW]
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HID0_neither equ 0
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; See NKPowerCalls for info on CpuSpecificByte1. Its upper nybble specifies how to idle the CPU.
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; CpuSpecificByte
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; 1 2 ProcessorFlags CPU
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; - - -------------- ---
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PflgTblEnt 0x03, HID0_NHR_only, 0 ; 0**0
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PflgTblEnt 0x00, HID0_neither, 0 ; 0**1 = 601
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PflgTblEnt 0x03, HID0_NHR_only, 0 ; 0**2
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PflgTblEnt 0x1b, HID0_NHR_and_sleep, 0 ; 0**3 = 603
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PflgTblEnt 0x0a, HID0_NHR_only, 0 ; 0**4 = 604
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PflgTblEnt 0x1b, HID0_NHR_and_sleep, 0 ; 0**5
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PflgTblEnt 0x1b, HID0_NHR_and_sleep, 0 ; 0**6 = 603e
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PflgTblEnt 0x1b, HID0_NHR_and_sleep, 0 ; 0**7 = 750FX
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PflgTblEnt 0x1b, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU ; 0**8 = 750
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PflgTblEnt 0x0a, HID0_NHR_only, 0 ; 0**9
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PflgTblEnt 0x0a, HID0_NHR_only, 0 ; 0**a
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PflgTblEnt 0x03, HID0_NHR_only, 0 ; 0**b
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PflgTblEnt 0x1b, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< hasMSSregs ; 0**c = 7400
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PflgTblEnt 0x0b, HID0_NHR_and_sleep, 0 ; 0**d
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 0**e
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 0**f
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< hasMSSregs ; 8**0 = 7450 (see note below)
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PflgTblEnt 0x1b, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< hasMSSregs ; 8**1 = 7445/55
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**2 = 7447 (OS X only)
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**3
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PflgTblEnt 0x03, HID0_NHR_only, 0 ; 8**4
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**5
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**6
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**7
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**8
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**9
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**a
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**b
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PflgTblEnt 0x1b, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< hasMSSregs ; 8**c = 7410
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**d
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**e
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PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**f
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; NB: PPC 7450 ("G4e") and its descendants (744x/745x) lack the HID0[DOZE] bit (they have HID0[HIGH_BAT_EN] instead).
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; Therefore the upper nybble of CpuSpecificByte1 should be 0, or 2 for NAP (works), or 3 for SLEEP (freezes).
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2017-11-19 04:11:07 +00:00
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endwith
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