mirror of
https://github.com/elliotnunn/powermac-rom.git
synced 2024-12-01 09:50:31 +00:00
484 lines
6.6 KiB
ArmAsm
484 lines
6.6 KiB
ArmAsm
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HASH1 equ 978
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HASH2 equ 979
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ICMP equ 981
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DCMP equ 977
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IMISS equ 980
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DMISS equ 976
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RPA equ 982
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macro
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Vanilla &idx
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@start
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b @jump1
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b @jump2
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@jump1
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; r1 -> SPRG1
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; LR -> SPRG2
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; targ -> r1
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; optr -> LR
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mtsprg 1, r1
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mflr r1
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mtsprg 2, r1
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mfsprg r1, 3
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lwz r1, &idx(r1)
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mtlr r1
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blrl
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dc.l @start - TableStart
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mflr r1
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@jump2
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mtsprg 1, r1
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mfsprg r1, 3
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mtsprg 2, r1
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mtlr r1
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lwz r1, &idx(r1)
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dc.l @start - TableStart
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blrl
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endm
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TableStart
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; 0000-00ff: For software use only
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org 0x0000
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mtsprg 1, r1
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mfsprg r1, 3
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lwz r1, 0x00BC(r1)
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mtlr r1
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blrl
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org 0x0080
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dc.l 0x0000D000 ; '....' (invalid instruction)
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; 0100-0fff: Architecture-defined exceptions
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org 0x0100
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b $+0x0008 ; 0x00000108
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b $+0x0050 ; 0x00000154
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mtsprg 1, r1
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mfcr r1
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mtsprg 2, r1
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mfsrr1 r1
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mtcrf 255, r1
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bne cr7, RTASFairyDust
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mfspr r1, HID0
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mtcrf 255, r1
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bns cr3, RTASFairyDust
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mfsprg r1, 2
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mtcrf 255, r1
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mflr r1
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mtsprg 2, r1
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mfsprg r1, 3
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lwz r1, 0x0004(r1)
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mtlr r1
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blrl
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dc.l 0x00000100 ; '....' (invalid instruction)
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org 0x180
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PerfMon
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mtsprg 2, r1
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mfsprg r1, 3
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stw r2, 0x0000(r1)
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mfsprg r2, 2
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rlwinm r2, r2, 26, 24, 29
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lwzx r1, r2, r1
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mflr r2
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mtlr r1
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mfsprg r1, 2
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mtsprg 2, r2
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mfsprg r2, 3
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lwz r2, 0x0000(r2)
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blr
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org 0x0200 ; Machine Check
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Vanilla 0x0008
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org 0x0300 ; Data Storage
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Vanilla 0x000C
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org 0x0400 ; Instruction Storage
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Vanilla 0x0010
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org 0x0500 ; External
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Vanilla 0x0014
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org 0x0600 ; Alignment
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Vanilla 0x0018
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org 0x0700 ; Program
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Vanilla 0x001C
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org 0x0800 ; FP Unavailable
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Vanilla 0x0020
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org 0x0900 ; Decrementer
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Vanilla 0x0024
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org 0x0A00
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Vanilla 0x0028
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org 0x0B00
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Vanilla 0x002C
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org 0x0C00 ; System Call
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Vanilla 0x0030
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org 0x0D00 ; Trace
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Vanilla 0x0034
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org 0x0E00
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Vanilla 0x0038
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; Performance monitor???
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org 0x0F00
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mtsprg 1, r1
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li r1, 0xF00
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b PerfMon
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org 0x0F20
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mtsprg 1, r1
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li r1, 0xF20
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b PerfMon
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; 1000-2fff: Implementation-specific exceptions
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org 0x1000
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mfspr r2, HASH1
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lwz r1, 0x0000(r2)
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mfctr r0
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mfspr r3, ICMP
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cmpw r1, r3
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beq $+0x001C ; 0x00001030
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li r1, 7
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mtctr r1
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lwzu r1, 0x0008(r2)
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cmpw r1, r3
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bdnzf cr0_EQ, $-0x0008 ; 0x00001020
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bne $+0x0038 ; 0x00001064
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lwz r1, 0x0004(r2)
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mtctr r0
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andi. r3, r1, 0x0008
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bne $+0x006C ; 0x000010A8
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mfspr r0, IMISS
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mfsrr1 r3
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mtcrf 128, r3
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mtspr RPA, r1
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ori r1, r1, 0x0100
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srwi r1, r1, 8
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dc.l 0x7C0007E4 ; '|...' (invalid instruction)
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stb r1, 0x0006(r2)
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rfi
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andi. r1, r3, 0x0040
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bne $+0x0014 ; 0x0000107C
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mfspr r2, HASH2
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lwz r1, 0x0000(r2)
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ori r3, r3, 0x0040
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b $-0x0068 ; 0x00001010
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mfsrr1 r3
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clrlwi r2, r3, 16
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oris r2, r2, 0x4000
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mtctr r0
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mtsrr1 r2
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mfmsr r0
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xoris r0, r0, 0x0002
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mtcrf 128, r3
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mtmsr r0
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isync
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b $-0x0CA4 ; 0x00000400
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mfsrr1 r3
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clrlwi r2, r3, 16
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oris r2, r2, 0x1000
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b $-0x0028 ; 0x0000108C
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org 0x1100
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mfspr r2, HASH1
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lwz r1, 0x0000(r2)
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mfctr r0
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mfspr r3, DCMP
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cmpw r1, r3
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beq $+0x001C ; 0x00001130
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li r1, 7
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mtctr r1
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lwzu r1, 0x0008(r2)
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cmpw r1, r3
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bdnzf cr0_EQ, $-0x0008 ; 0x00001120
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bne $+0x0034 ; 0x00001160
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lwz r1, 0x0004(r2)
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mtctr r0
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mfspr r0, DMISS
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mfsrr1 r3
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mtcrf 128, r3
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mtspr RPA, r1
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ori r1, r1, 0x0100
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srwi r1, r1, 8
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dc.l 0x7C0007A4 ; '|...' (invalid instruction)
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stb r1, 0x0006(r2)
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rfi
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nop
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andi. r1, r3, 0x0040
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bne $+0x013C ; 0x000012A0
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mfspr r2, HASH2
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lwz r1, 0x0000(r2)
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ori r3, r3, 0x0040
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b $-0x0064 ; 0x00001110
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org 0x1200
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mfspr r2, HASH1
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lwz r1, 0x0000(r2)
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mfctr r0
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mfspr r3, DCMP
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cmpw r1, r3
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beq $+0x001C ; 0x00001230
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li r1, 7
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mtctr r1
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lwzu r1, 0x0008(r2)
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cmpw r1, r3
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bdnzf cr0_EQ, $-0x0008 ; 0x00001220
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bne $+0x003C ; 0x00001268
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lwz r1, 0x0004(r2)
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mtctr r0
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slwi. r3, r1, 30
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bge $+0x0044 ; 0x00001280
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andi. r3, r1, 0x0001
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bne $+0x0054 ; 0x00001298
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mfspr r0, DMISS
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mfsrr1 r3
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mtcrf 128, r3
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ori r1, r1, 0x0180
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mtspr RPA, r1
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dc.l 0x7C0007A4 ; '|...' (invalid instruction)
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sth r1, 0x0006(r2)
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rfi
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andi. r1, r3, 0x0040
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bne $+0x0034 ; 0x000012A0
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mfspr r2, HASH2
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lwz r1, 0x0000(r2)
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ori r3, r3, 0x0040
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b $-0x006C ; 0x00001210
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mfsrr1 r0
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extrwi r0, r0, 1, 17
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mfspr r3, DMISS
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mfsrin r3, r3
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rlwnm. r3, r3, r0, 1, 1
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beq $-0x004C ; 0x00001248
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lis r1, 2048
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b $+0x000C ; 0x000012A8
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lis r1, 16384
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mtctr r0
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mfsrr1 r3
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rlwimi r1, r3, 9, 6, 6
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clrlwi r2, r3, 16
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mtsrr1 r2
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mtdsisr r1
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mfspr r1, DMISS
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andi. r2, r2, 0x0001
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beq+ $+0x0008 ; 0x000012CC
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xori r1, r1, 0x0007
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mtdar r1
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mfmsr r0
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xoris r0, r0, 0x0002
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mtcrf 128, r3
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mtmsr r0
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isync
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b $-0x0FE4 ; 0x00000300
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org 0x1300
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Vanilla 0x004C
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org 0x1400
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Vanilla 0x0050
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org 0x1500
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Vanilla 0x0054
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org 0x1600
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Vanilla 0x0058
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org 0x1700
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Vanilla 0x005C
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org 0x1800
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Vanilla 0x0060
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org 0x1900
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Vanilla 0x0064
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org 0x1A00
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Vanilla 0x0068
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org 0x1B00
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Vanilla 0x006C
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org 0x1C00
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Vanilla 0x0070
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org 0x1D00
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Vanilla 0x0074
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org 0x1E00
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Vanilla 0x0078
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org 0x1F00
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Vanilla 0x007C
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org 0x2000
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Vanilla 0x0080
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org 0x2100
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Vanilla 0x0084
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org 0x2200
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Vanilla 0x0088
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org 0x2300
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Vanilla 0x008C
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org 0x2400
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Vanilla 0x0090
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org 0x2500
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Vanilla 0x0094
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org 0x2600
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Vanilla 0x0098
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org 0x2700
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Vanilla 0x009C
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org 0x2800
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Vanilla 0x00A0
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org 0x2900
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Vanilla 0x00A4
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org 0x2A00
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Vanilla 0x00A8
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org 0x2B00
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Vanilla 0x00AC
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org 0x2C00
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Vanilla 0x00B0
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org 0x2D00
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Vanilla 0x00B4
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org 0x2E00
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Vanilla 0x00B8
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org 0x2F00
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Vanilla 0x00BC
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; Outside the exception table, but called by it:
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org 0x3000
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RTASFairyDust
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mr r21,r3
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li r0,0
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lwz r5, 0(r21)
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lwz r4, 4(r21)
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lwz r9, 12(r21)
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lwz r3, 12(r9)
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lwz r6, 8(r21)
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lwz r8, 16(r21)
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lwz r22,24(r21)
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lwz r23,28(r21)
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bl @clrbats
|
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lis r7, 'RT'
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ori r7,r7,'AS'
|
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|
; Soo, we jump to *(arg + 24) the ugly way
|
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|
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mtlr r22
|
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|
|
blr
|
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|
|
@clrbats
|
||
|
|
mtdbatl 0,r0
|
||
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mtdbatu 0,r0
|
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mtdbatl 1,r0
|
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mtdbatu 1,r0
|
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mtdbatl 2,r0
|
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mtdbatu 2,r0
|
||
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mtdbatl 3,r0
|
||
|
|
mtdbatu 3,r0
|
||
|
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mtibatl 0,r0
|
||
|
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mtibatu 0,r0
|
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mtibatl 1,r0
|
||
|
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mtibatu 1,r0
|
||
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mtibatl 2,r0
|
||
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mtibatu 2,r0
|
||
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mtibatl 3,r0
|
||
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|
mtibatu 3,r0
|
||
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|
isync
|
||
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|
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|
blr
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