From 45787c7d0a23167e0c45ea65b90be209dfc0f930 Mon Sep 17 00:00:00 2001 From: Elliot Nunn Date: Tue, 22 May 2018 17:44:38 +0800 Subject: [PATCH] archive --- NanoKernel/NKInit.s | 8 +- NanoKernel/NKInterrupts.s | 63 +- NanoKernel/NKPaging.s | 2 +- NanoKernel/NKThud.s | 4 +- NanoKernel/NKVMCalls.s | 2 +- al2.txt | 137 ++ alignments.s | 6 + halfwits.s | 314 ++++ pdp.py | 104 +- translation-remaining.s | 3320 +++++++++++++++++++++++++++++++++++++ vector stuff.s | 256 +++ 11 files changed, 4177 insertions(+), 39 deletions(-) create mode 100644 al2.txt create mode 100644 halfwits.s create mode 100644 translation-remaining.s create mode 100644 vector stuff.s diff --git a/NanoKernel/NKInit.s b/NanoKernel/NKInit.s index 58f15b9..01df917 100644 --- a/NanoKernel/NKInit.s +++ b/NanoKernel/NKInit.s @@ -1885,7 +1885,7 @@ finish_old_world sync setup_0x1160 - bl PagingFunc1 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq lwz r27, 0x0630(r1) lwz r27, 0x009c(r27) bl PagingL2PWithoutBATs @@ -1897,7 +1897,7 @@ setup_0x1160 sync setup_0x1188 - bl PagingFunc1 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq lwz r27, 0x0630(r1) lwz r27, 0x00a0(r27) lis r19, 0x00 @@ -1914,7 +1914,7 @@ setup_0x11a0 sync setup_0x11bc - bl PagingFunc1 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq cmplw r27, r19 addi r27, r27, -0x1000 bgt setup_0x11a0 @@ -1929,7 +1929,7 @@ setup_0x11bc sync setup_0x11f0 - bl PagingFunc1 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq _log 'Nanokernel replaced. Returning to boot process^n' diff --git a/NanoKernel/NKInterrupts.s b/NanoKernel/NKInterrupts.s index cab2940..6e286b5 100644 --- a/NanoKernel/NKInterrupts.s +++ b/NanoKernel/NKInterrupts.s @@ -19,7 +19,7 @@ ecDataPageFault equ 20 ; ExceptionMemRetried ecDataWriteViolation equ 21 ; ExceptionMemRetried ecDataSupAccessViolation equ 22 ; ExceptionMemRetried ecDataSupWriteViolation equ 23 ; ? -ecUnknown24 equ 24 ; ExceptionMemRetried +ecAlignment equ 24 ; ExceptionMemRetried @@ -1070,7 +1070,7 @@ IntAlignment ; OUTSIDE REFERER addi r23, r1, KDP.VecBaseMemRetry - bne major_0x03548_0x20 + bne ThrowAlignmentException ; DSISR for misaligned X-form instruction: @@ -1087,7 +1087,7 @@ FDP_TableBase equ 0xa00 ; Get the FDP and F.O. if we were in MSR_LE mode lwz r25, KDP.PA_FDP(r1) - bne major_0x03548_0x20 + bne ThrowAlignmentException rlwinm. r21, r27, 17, 30, 31 ; evaluate hi two bits of XO (or 0 for d-form?) @@ -1139,7 +1139,8 @@ FDP_TableBase equ 0xa00 -IcbiNextBlock ; msr r14 // ; OUTSIDE REFERER +IcbiNextBlock ; msr r14 // + sync mtmsr r14 isync @@ -1149,14 +1150,18 @@ IcbiNextBlock ; msr r14 // ; OUTSIDE REFERER isync blr -major_0x03548_0x20 ; OUTSIDE REFERER - li r8, 0x00 - lis r17, -0x100 + +ThrowAlignmentException + + li r8, 0 + lis r17, 0xFF00 mtcr r8 mr r19, r18 - rlwimi r17, r27, 7, 31, 31 - xori r17, r17, 0x01 - li r8, ecUnknown24 + + rlwimi r17, r27, 7, 31, 31 ; why ~DSISR[6]... those DSISR bytes are reserved? + xori r17, r17, 1 + + li r8, ecAlignment b ExceptionMemRetried @@ -1250,14 +1255,18 @@ MemRetryDSI_0x100 beql IntPanicIsland mfsprg r28, 2 mtlr r28 - bne cr7, MemRetryDSI_0x144 + + bc BO_IF_NOT, 30, MemRetryDSI_0x144 + + ; "Ignore write to ROM", for example mfspr r28, srr0 - addi r28, r28, 0x04 - lwz r26, 0x0e90(r1) + addi r28, r28, 4 + lwz r26, KDP.NanoKernelInfo + NKNanoKernelInfo.QuietWriteCount(r1) mtspr srr0, r28 - addi r26, r26, 0x01 - stw r26, 0x0e90(r1) - b MemRetryDSI_0x19c + addi r26, r26, 1 + stw r26, KDP.NanoKernelInfo + NKNanoKernelInfo.QuietWriteCount(r1) + + b MemRetryDSI_GracefulExit MemRetryDSI_0x144 andi. r28, r31, 0x03 @@ -1285,7 +1294,7 @@ MemRetryDSI_0x158 mtlr r28 mtspr srr1, r29 -MemRetryDSI_0x19c +MemRetryDSI_GracefulExit mfsprg r1, 1 rlwinm r26, r25, 30, 24, 31 rfi @@ -1296,15 +1305,18 @@ MemRetryDSI_0x1c8 andis. r28, r31, 0x8010 bne MemRetryMachineCheck_0x14c - _Lock PSA.HTABLock, scratch1=r28, scratch2=r31 - - bl PagingFunc1 + _Lock PSA.HTABLock, scratch1=r28, scratch2=r31 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq _AssertAndRelease PSA.HTABLock, scratch=r28 + mfsprg r28, 2 mtlr r28 - beq MemRetryDSI_0x19c + + beq MemRetryDSI_GracefulExit + li r8, ecDataInvalidAddress bge ExceptionMemRetried + li r8, ecDataPageFault b ExceptionMemRetried @@ -1337,10 +1349,13 @@ MemRetryMachineCheck ; OUTSIDE REFERER _log '^n' mr r8, r28 + lwz r1, EWA.PA_KDP(r1) lwz r27, 0x0694(r1) + subf r28, r19, r27 cmpwi r28, -0x10 + blt MemRetryMachineCheck_0x14c cmpwi r28, 0x10 bgt MemRetryMachineCheck_0x14c @@ -1350,7 +1365,9 @@ MemRetryMachineCheck ; OUTSIDE REFERER lwz r28, 0x0e98(r1) addi r28, r28, 0x01 stw r28, 0x0e98(r1) + lwz r29, 0x0698(r1) + li r28, 0x00 stw r28, 0x0000(r29) mfspr r28, pvr @@ -1394,7 +1411,7 @@ IntISI ; OUTSIDE REFERER _Lock PSA.HTABLock, scratch1=r28, scratch2=r31 mr r27, r10 - bl PagingFunc1 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq _AssertAndRelease PSA.HTABLock, scratch=r28 mfsprg r8, 0 bne major_0x039dc @@ -1499,7 +1516,7 @@ PIHDSI ; OUTSIDE REFERER _Lock PSA.HTABLock, scratch1=r28, scratch2=r31 mfspr r27, dar - bl PagingFunc1 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq _AssertAndRelease PSA.HTABLock, scratch=r28 mfsprg r8, 0 bne major_0x039dc diff --git a/NanoKernel/NKPaging.s b/NanoKernel/NKPaging.s index ef97d70..ff03f11 100644 --- a/NanoKernel/NKPaging.s +++ b/NanoKernel/NKPaging.s @@ -5,7 +5,7 @@ Local_Panic set * align 5 -PagingFunc1 ; OUTSIDE REFERER +GetMeAccessToThisPage ; Page *r27 // success cr0.eq ; OUTSIDE REFERER mfsprg r29, 0 mflr r28 stw r8, -0x00dc(r29) diff --git a/NanoKernel/NKThud.s b/NanoKernel/NKThud.s index f0781ce..a272589 100644 --- a/NanoKernel/NKThud.s +++ b/NanoKernel/NKThud.s @@ -940,7 +940,7 @@ print_memory_logical_0x8 print_memory_logical_0x24 mr r27, r16 - bl PagingFunc1 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq beq print_memory_logical_0x5c blt print_memory_logical_0x48 _log '..' @@ -974,7 +974,7 @@ print_memory_logical_0x84 print_memory_logical_0xac mr r27, r16 - bl PagingFunc1 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq li r8, 0x20 bne print_memory_logical_0xdc bl PagingL2PWithoutBATs diff --git a/NanoKernel/NKVMCalls.s b/NanoKernel/NKVMCalls.s index 4bff6f1..a09bb6f 100644 --- a/NanoKernel/NKVMCalls.s +++ b/NanoKernel/NKVMCalls.s @@ -1868,7 +1868,7 @@ VMLastExportedFunc_0xd7 mr r14, r26 mflr r6 slwi r27, r4, 12 - bl PagingFunc1 + bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq bnel Local_Panic mr r27, r7 mr r29, r8 diff --git a/al2.txt b/al2.txt new file mode 100644 index 0000000..2bf3976 --- /dev/null +++ b/al2.txt @@ -0,0 +1,137 @@ +MRLoad1241 + lbz mrScratch, -8(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrHigh, mrScratch, 8, 0xFF000000 + +MRLoad241 + lhz mrScratch, -7(mrBase) + subi mrCtr, mrCtr, 4 + rlwimi mrHigh, mrScratch, 24, 0x00FFFF00 + b MRLoad41 + +MRLoad141 + lbz mrScratch, -6(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrHigh, mrScratch, 24, 0x0000FF00 + +MRLoad41 + lwz mrScratch, -5(mrBase) + subi mrCtr, mrCtr, 8 + rlwimi mrHigh, mrScratch, 24, 0x000000FF + rlwimi mrLow, mrScratch, 24, 0xFFFFFF00 + b MRLoad1 + +MRLoad1421 + lbz mrScratch, -8(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrHigh, mrScratch, 8, 0xFF000000 + +MRLoad421 + lwz mrScratch, -7(mrBase) + subi mrCtr, mrCtr, 8 + rlwimi mrHigh, mrScratch, 8, 0x00FFFFFF + rlwimi mrLow, mrScratch, 8, 0xFF000000 + b MRLoad21 + +MRLoad1221 + lbz mrScratch, -6(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrHigh, mrScratch, 24, 0x0000FF00 + +MRLoad221 + lhz mrScratch, -5(mrBase) + subi mrCtr, mrCtr, 4 + rlwimi mrHigh, mrScratch, 8, 0x000000FF + rlwimi mrLow, mrScratch, 8, 0xFF000000 + b MRLoad21 + +MRLoad121 + lbz mrScratch, -4(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrLow, mrScratch, 8, 0xFF000000 + +MRLoad21 + lhz mrScratch, -3(mrBase) + subi mrCtr, mrCtr, 4 + rlwimi mrLow, mrScratch, 24, 0x00FFFF00 + b MRLoad1 + +MRLoad11 + lbz mrScratch, -2(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrLow, mrScratch, 24, 0x0000FF00 + +MRLoad1 + lbz mrScratch, -1(mrBase) + rlwimi mrLow, mrScratch, 0, 0x000000FF + b MRExecuted + +MRLoad242 + lhz mrScratch, -8(mrBase) + subi mrCtr, mrCtr, 4 + rlwimi mrHigh, mrScratch, 16, 0xFFFF0000 + b MRLoad42 + +MRLoad142 + lbz mrScratch, -7(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrHigh, mrScratch, 16, 0x00FF0000 + +MRLoad42 + lwz mrScratch, -6(mrBase) + subi mrCtr, mrCtr, 8 + rlwimi mrHigh, mrScratch, 16, 0x0000FFFF + rlwimi mrLow, mrScratch, 16, 0xFFFF0000 + b MRLoad2 + +MRLoad122 + lbz mrScratch, -5(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrHigh, mrScratch, 0, 0x000000FF + b MRLoad22 + +MRLoad12 + lbz mrScratch, -3(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrLow, mrScratch, 16, 0x00FF0000 + b MRLoad2 + +MRLoad44 + lwz mrHigh, -8(mrBase) + subi mrCtr, mrCtr, 8 + lwz mrLow, -4(mrBase) + b MRExecuted + +MRLoad124 + lbz mrScratch, -7(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrHigh, mrScratch, 16, 0x00FF0000 + +MRLoad24 + lhz mrScratch, -6(mrBase) + subi mrCtr, mrCtr, 4 + rlwimi mrHigh, mrScratch, 0, 0x0000FFFF + lwz mrLow, -4(mrBase) + b MRExecuted + +MRLoad14 + lbz mrScratch, -5(mrBase) + subi mrCtr, mrCtr, 2 + rlwimi mrHigh, mrScratch, 0, 0x000000FF + lwz mrLow, -4(mrBase) + b MRExecuted + +MRLoad4 + bc BO_IF, 23, @atomic + lwz mrLow, -4(mrBase) + b MRExecuted +@atomic + li mrScratch, -4 + lwarx mrScratch, mrBase + b MRExecuted + +MRLoad8 + lwz mrLow, -8(mrBase) + lwz mrHigh, -4(mrBase) + b MRExecuted + diff --git a/alignments.s b/alignments.s index 574c05d..6cd6b2c 100644 --- a/alignments.s +++ b/alignments.s @@ -151,6 +151,12 @@ MRLoadVector _bset r11, r11, 6 blr + + + + + + MRStore1241 srwi mrScratch, mrHigh, 24 stb mrScratch, -8(mrBase) diff --git a/halfwits.s b/halfwits.s new file mode 100644 index 0000000..4152754 --- /dev/null +++ b/halfwits.s @@ -0,0 +1,314 @@ +FDP_03ec + lbz r23, -0x0008(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 0 +FDP_03f8 + lhz r23, -0x0007(r19) + subi r17, r17, 4 + insrwi r20, r23, 16, 8 + b FDP_0414 + + +FDP_0408 + lbz r23, -0x0006(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 16 +FDP_0414 + lwz r23, -0x0005(r19) + subi r17, r17, 8 + inslwi r20, r23, 8, 24 + insrwi r21, r23, 24, 0 + b FDP_0490 + + +FDP_0428 + lbz r23, -0x0008(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 0 +FDP_0434 + lwz r23, -0x0007(r19) + subi r17, r17, 8 + inslwi r20, r23, 24, 8 + insrwi r21, r23, 8, 0 + b FDP_0474 + + +FDP_0448 + lbz r23, -0x0006(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 16 +FDP_0454 + lhz r23, -0x0005(r19) + subi r17, r17, 4 + rlwimi r20, r23, 24, 24, 31 + insrwi r21, r23, 8, 0 + b FDP_0474 + + +FDP_0468 + lbz r23, -0x0004(r19) + subi r17, r17, 2 + insrwi r21, r23, 8, 0 +FDP_0474 + lhz r23, -0x0003(r19) + subi r17, r17, 4 + insrwi r21, r23, 16, 8 + b FDP_0490 + + +FDP_0484 + lbz r23, -0x0002(r19) + subi r17, r17, 2 + insrwi r21, r23, 8, 16 +FDP_0490 + lbz r23, -0x0001(r19) + insrwi r21, r23, 8, 24 + b FDP_011C + + +FDP_049c + lhz r23, -0x0008(r19) + subi r17, r17, 4 + insrwi r20, r23, 16, 0 + b FDP_04B8 + + +FDP_04ac + lbz r23, -0x0007(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 8 +FDP_04b8 + lwz r23, -0x0006(r19) + subi r17, r17, 8 + inslwi r20, r23, 16, 16 + insrwi r21, r23, 16, 0 + b FDP_0114 + + +FDP_04cc + lbz r23, -0x0005(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 24 + b FDP_0108 + + +FDP_04dc + lbz r23, -0x0003(r19) + subi r17, r17, 2 + insrwi r21, r23, 8, 8 + b FDP_0114 + + +FDP_04ec + lwz r20, -0x0008(r19) + subi r17, r17, 8 + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_04fc + lbz r23, -0x0007(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 8 +FDP_0508 + lhz r23, -0x0006(r19) + subi r17, r17, 4 + insrwi r20, r23, 16, 16 + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_051c + lbz r23, -0x0005(r19) + subi r17, r17, 2 + insrwi r20, r23, 8, 24 + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_0530 + bso cr5, FDP_053C + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_053c + li r23, -4 + lwarx r21, r23, r19 + b FDP_011C + + +FDP_0548 + lwz r20, -0x0008(r19) + lwz r21, -0x0004(r19) + b FDP_011C + + +FDP_0554 + clrrwi r23, r25, 10 + rlwimi r23, r17, 14, 24, 28 + addi r23, r23, 9760 + mtlr r23 + mr r23, r18 + oris r11, r11, 0x0200 + blr + + +FDP_0570 + srwi r23, r20, 24 + stb r23, -0x0008(r19) + subi r17, r17, 2 +FDP_057c + srwi r23, r20, 8 + sth r23, -0x0007(r19) + subi r17, r17, 4 + b FDP_0598 + + +FDP_058c + srwi r23, r20, 8 + stb r23, -0x0006(r19) + subi r17, r17, 2 +FDP_0598 + srwi r23, r21, 8 + insrwi r23, r20, 8, 0 + stw r23, -0x0005(r19) + subi r17, r17, 8 + stb r21, -0x0001(r19) + b FDP_011C + + +FDP_05b0 + srwi r23, r20, 24 + stb r23, -0x0008(r19) + subi r17, r17, 2 +FDP_05bc + srwi r23, r21, 24 + insrwi r23, r20, 24, 0 + stw r23, -0x0007(r19) + subi r17, r17, 8 + b FDP_05FC + + +FDP_05d0 + srwi r23, r20, 8 + stb r23, -0x0006(r19) + subi r17, r17, 2 +FDP_05dc + srwi r23, r21, 24 + insrwi r23, r20, 8, 16 + sth r23, -0x0005(r19) + subi r17, r17, 4 + b FDP_05FC + + +FDP_05f0 + srwi r23, r21, 24 + stb r23, -0x0004(r19) + subi r17, r17, 2 +FDP_05fc + srwi r23, r21, 8 + sth r23, -0x0003(r19) + subi r17, r17, 4 + stb r21, -0x0001(r19) + b FDP_011C + + +FDP_0610 + srwi r23, r21, 8 + stb r23, -0x0002(r19) + subi r17, r17, 2 +FDP_061c + stb r21, -0x0001(r19) + b FDP_011C + + +FDP_0624 + srwi r23, r20, 16 + sth r23, -0x0008(r19) + subi r17, r17, 4 + b FDP_0640 + + +FDP_0634 + srwi r23, r20, 16 + stb r23, -0x0007(r19) + subi r17, r17, 2 +FDP_0640 + srwi r23, r21, 16 + insrwi r23, r20, 16, 0 + stw r23, -0x0006(r19) + subi r17, r17, 8 + sth r21, -0x0002(r19) + b FDP_011C + + +FDP_0658 + stb r20, -0x0005(r19) + subi r17, r17, 2 + b FDP_00F4 + + +FDP_0664 + srwi r23, r21, 16 + stb r23, -0x0003(r19) + subi r17, r17, 2 +FDP_0670 + sth r21, -0x0002(r19) + b FDP_011C + + +FDP_0678 + stw r20, -0x0008(r19) + subi r17, r17, 8 + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_0688 + srwi r23, r20, 16 + stb r23, -0x0007(r19) + subi r17, r17, 2 +FDP_0694 + sth r20, -0x0006(r19) + subi r17, r17, 4 + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_06a4 + stb r20, -0x0005(r19) + subi r17, r17, 2 + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_06b4 + bso cr5, FDP_06C0 + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_06c0 + li r23, -4 + stwcx. r21, r23, r19 + isync + mfcr r23 + rlwimi r13, r23, 0, 0, 3 + b FDP_011C + + +FDP_06d8 + stw r20, -0x0008(r19) + stw r21, -0x0004(r19) + b FDP_011C + + +FDP_06e4 + clrrwi r23, r25, 10 + rlwimi r23, r17, 14, 24, 28 + addi r23, r23, 10784 + mtlr r23 + mr r23, r18 + oris r11, r11, 0x0200 + blr diff --git a/pdp.py b/pdp.py index dab7a50..ef1b897 100644 --- a/pdp.py +++ b/pdp.py @@ -85,22 +85,35 @@ def list_perms_ending_with(x): yield from list_perms_ending_with(nextlet + x) -SPECIAL_LOADSTORE_RETURN_PATHS = ['2', '22'] - -def final_loadstore_list(): +def final_load_list(): """ - Big waterfall of loads/stores! + Big waterfall of loads! """ the_list = [] for ender in '8421': for x in list_perms_ending_with(ender): - if x not in SPECIAL_LOADSTORE_RETURN_PATHS: + if x not in ('2','22'): the_list.append(x) return list(reversed(the_list)) -FINAL_LOADSTORE_LIST = final_loadstore_list() +FINAL_LOAD_LIST = final_load_list() + +def final_store_list(): + """ + Big waterfall of stores! + """ + the_list = [] + + for ender in '8421': + for x in list_perms_ending_with(ender): + if x not in []: + the_list.append(x) + + return list(reversed(the_list)) + +FINAL_STORE_LIST = final_store_list() ################################################################ @@ -160,7 +173,7 @@ def MRVectorAlignDispatchTable(): def MRAlignLoads(): - waterfall = FINAL_LOADSTORE_LIST + waterfall = FINAL_LOAD_LIST for wi in range(len(waterfall)): sizes = waterfall[wi] @@ -230,6 +243,81 @@ def MRAlignLoads(): print() +def MRAlignStores(): + waterfall = FINAL_STORE_LIST + + for wi in range(len(waterfall)): + sizes = waterfall[wi] + + label('MRStore' + sizes) + + sizes_as_list = [int(x) for x in sizes] + this_size = sizes_as_list[0] + total_size = sum(sizes_as_list) + remain_size = sum(sizes_as_list[1:]) -MRAlignLoads() + # PART 1: load a number of bytes equal to the first element in "sizes" + + inst = {1: 'stb', 2: 'sth', 4: 'stw', 8: 'no way'}[this_size] + + if sizes == '8': # special case + directive('stw', 'mrLow', '-8(mrBase)') + directive('stw', 'mrHigh', '-4(mrBase)') + + elif remain_size == 4: # straight store! + directive(inst, 'mrHigh', '-%d(mrBase)' % total_size) + if len(sizes) > 1: directive('subi', 'mrCtr', 'mrCtr', 2 * this_size) + + elif sizes == '4': # special case: emulate lwarx if asked + directive('bc', 'BO_IF', 23, '@atomic') + directive('stw', 'mrLow', '-4(mrBase)') + directive('b', 'MRExecuted') + label('@atomic') + directive('li', 'mrScratch', -4) + directive('stwcx.', 'mrScratch', 'mrBase') + directive('isync') + directive('mfcr', 'mrScratch') + directive('rlwimi', 'r13', 'mrScratch', 0, '0xFF000000') + + else: # arrange intermediate register then store it + fiddler = 'rlwinm' + + for regexponent, regname in [(0,'mrLow'), (4,'mrHigh')]: + thisexponent = remain_size + if regexponent >= thisexponent + this_size: continue + if thisexponent >= regexponent + 4: continue + + lshift = (regexponent - thisexponent) * 8 + + mask = (1 << (8 * this_size)) - 1 + + directive(fiddler, 'mrScratch', regname, normlshift(lshift), '0x%08X' % mask) + fiddler = 'rlwimi' + + directive(inst, 'mrScratch', '-%d(mrBase)' % total_size) + if len(sizes) > 1: directive('subi', 'mrCtr', 'mrCtr', 2 * this_size) + + + # PART 2: jump somewhere that will do the rest of the loads in "sizes" + + if wi + 1 < len(waterfall) and waterfall[wi+1] == sizes[1:] and sizes[1:] != '4': # fall through + # but beware the special case! + pass + + elif len(sizes[1:]) == 1: # special case: inline a single store instead of jumping + inst = {1: 'stb', 2: 'sth', 4: 'stw', 8: 'no way'}[remain_size] + directive(inst, 'mrLow', '-%d(mrBase)' % remain_size) + directive('b', 'MRExecuted') + + elif remain_size == 0: # finished executing + directive('b', 'MRExecuted') + + else: + directive('b', 'MRStore' + sizes[1:]) + + print() + + + +MRAlignStores() diff --git a/translation-remaining.s b/translation-remaining.s new file mode 100644 index 0000000..afeb586 --- /dev/null +++ b/translation-remaining.s @@ -0,0 +1,3320 @@ +; This file is tricky. Along with the file immediately before it, +; Interrupts.s, it emulates unsupported PowerPC instructions. +; This mechanism is heavily optimized, and the jumping between +; tables (which I have tried to describe as well as I can) is +; very confusing. + +; It is called 'FDP' because of a long-ago confusion about what it did. + +; Some of the mnemonics might look a bit odd, because I used MPW +; to disassemble instead of ppcdisasm.py or gas. + +; The init code puts a pointer to 'FDP' in the part of the KDP that is +; mostly shared with NKv1. Therefore this is probably deep Davidianian +; magic. The tables here contain relative references to other tables +; in Interrupts.s. What a mess. + + + align 11 + + +FDP + + +FDP_panic + bl panic + + +FDP_0004 + b FDP_024C + + +; This stuff is for emulating float storage instructions + +FDP_0008 ; stfs(x) + rlwinm r17, r17, 0, 16, 10 + + +FDP_000c ; stfsu(x) + crclr cr7_SO + b FDP_001C + + +FDP_0014 ; stfd(x), stfiwx + rlwinm r17, r17, 0, 16, 10 + + +FDP_0018 ; stfdu(x) + crset cr7_SO + + +FDP_001c ; called from above + clrrwi r19, r25, 10 + rlwimi r19, r17, 14, 24, 28 + addi r19, r19, FloatSaveJumpTable - FDP + mtlr r19 + rlwimi r14, r11, 0, 18, 18 + mtmsr r14 + isync + blr + + +FDP_003c ; Called by the jump table in the previous file + ori r11, r11, 0x2000 + lwz r20, -0x02E0(r1) + lwz r21, -0x02DC(r1) + bso cr7, FDP_00E8 + extrwi r23, r20, 11, 1 + cmpwi r23, 896 + insrwi r20, r20, 27, 2 + inslwi r20, r21, 3, 29 + mr r21, r20 + bgt FDP_00E8 + cmpwi r23, 874 + clrrwi r21, r20, 31 + blt FDP_00E8 + oris r20, r20, 0x0080 + neg r23, r23 + clrlwi r20, r20, 8 + srw r20, r20, r23 + rlwimi r21, r20, 31, 9, 31 + b FDP_00E8 + + +FDP_0088 ; stwbrx + rlwinm r28, r17, 13, 25, 29 + lwbrx r21, r1, r28 + b FDP_00E4 + + +FDP_0094 ; sthbrx + rlwinm r28, r17, 13, 25, 29 + addi r21, r1, 2 + lhbrx r21, r21, r28 + b FDP_00E4 + + +FDP_00a4 ; sthu(x) + rlwinm r28, r17, 13, 25, 29 + lwzx r21, r1, r28 + b FDP_00E8 + + +FDP_00b0 ; stwcx. + rlwinm r28, r17, 13, 25, 29 + lwzx r21, r1, r28 + + +FDP_00b8 ; lwarx + crset cr5_SO + b FDP_00E4 + + +FDP_00c0 ; lbzu(x), stbu(x), lhau(x), stmw + clrrwi r18, r18, 4 + rlwimi r15, r11, 0, 6, 6 + b FDP_00E4 + + +FDP_00cc ; lwzu(x) + clrrwi r18, r18, 1 + b FDP_00E4 + + +FDP_00d4 ; lbz(x) + clrrwi r18, r18, 2 + b FDP_00E4 + + +FDP_00dc ; ecowx, sth(x) + rlwinm r28, r17, 13, 25, 29 + lwzx r21, r1, r28 + + +FDP_00e4 ; eciwx, lwz(x), lbz(x), lhz(x), lha(x), lfs(x), lfd(x) + rlwinm r17, r17, 0, 16, 10 + + +FDP_00e8 ; lwbrx, lhbrx, lmw, lhzu(x), lhfsu(x), lfdu(x) + extrwi. r22, r17, 5, 26 + add r19, r18, r22 + b FDP_03AC + + +MRStore4bToWordMod2 + srwi r23, r21, 16 + sth r23, -4(r19) + subi r17, r17, 4 + sth r21, -4(r19) + b MRExecuted + +MRLoad22 + lhz r23, -4(r19) + subi r17, r17, 4 + insrwi r21, r23, 16, 0 +MRLoad2 + lhz r23, -2(r19) + insrwi r21, r23, 16, 16 + + +FDP_011c ; exported, r25 = address of routine in MixedTable +MRExecuted + li r0, -3 + sc + + bl IcbiNextBlock ; msr r14 // + + rlwinm. r28, r17, 18, 25, 29 + mtlr r25 + mfsprg r1, 0 + cror cr0_EQ, cr0_EQ, cr3_EQ + mtsprg 3, r24 + beqlr + crset cr3_SO + stwx r18, r1, r28 + blr + + +FDP_014C + extsh r21, r21 + + +FDP_0150 + rlwinm r28, r17, 13, 25, 29 + crset cr3_SO + stwx r21, r1, r28 + + +FDP_015C + b FDP_0dA0 + + +FDP_0160 + slwi r21, r21, 16 + + +FDP_0164 + rlwinm r28, r17, 13, 25, 29 + crset cr3_SO + stwbrx r21, r1, r28 + b FDP_0dA0 + + +FDP_0174 + b FDP_0fA8 + +FDP_0178 + clrrwi r23, r25, 10 + rlwimi r23, r17, 14, 24, 28 + addi r23, r23, FloatLoadJumpTable - FDP + mtlr r23 + stw r20, -0x02E0(r1) + stw r21, -0x02DC(r1) + rlwimi r14, r11, 0, 18, 18 + mtmsr r14 + isync + ori r11, r11, 0x2000 + blr + + +FDP_01a4 + rlwinm. r28, r17, 13, 25, 29 + rlwinm r23, r17, 18, 25, 29 + cmpw cr7, r28, r23 + addis r17, r17, 32 + beq FDP_01BC + beq cr7, FDP_01C0 + + +FDP_01bc + stwx r21, r1, r28 + + +FDP_01c0 + cmpwi r28, 124 + li r22, 9 + insrwi r17, r22, 6, 26 + addi r19, r19, 4 + bne FDP_03AC + b FDP_0dA0 + + +FDP_01d8 + addis r17, r17, 32 + rlwinm. r28, r17, 13, 25, 29 + beq FDP_0dA0 + lwzx r21, r1, r28 + li r22, 8 + insrwi r17, r22, 6, 26 + addi r19, r19, 4 + b FDP_03AC + + +FDP_01f8 ; dcbz + lwz r21, -0x0004(r1) + lhz r21, 0x0F4A(r21) + neg r21, r21 + and r19, r18, r21 + b FDP_0224 + + +FDP_020c + lwz r21, -0x0004(r1) + lhz r21, 0x0F4A(r21) + subi r21, r21, 8 + and. r22, r19, r21 + clrrwi r19, r19, 3 + beq FDP_0dA0 + + +FDP_0224 + li r22, 16 + insrwi. r17, r22, 6, 26 + addi r19, r19, 8 + li r20, 0 + li r21, 0 + b FDP_03AC + + +FDP_023c + rlwinm r16, r16, 0, 28, 25 + subi r10, r10, 4 + stw r16, -0x0010(r1) + b FDP_0dA0 + + +FDP_024c + li r8, 18 + b DataLikeException + + +FDP_0254 ; stswi + subi r22, r27, 2048 + extrwi r22, r22, 5, 16 + b FDP_0270 + + +FDP_0260 ; stswx + mfxer r22 + andi. r22, r22, 0x007F + subi r22, r22, 1 + beq FDP_0dA0 + + +FDP_0270 + rlwimi r17, r22, 4, 21, 25 + not r22, r22 + insrwi r17, r22, 2, 4 + mr r19, r18 + b FDP_0e60 + + +FDP_0284 + andi. r22, r17, 0x07C0 + addis r28, r17, 32 + rlwimi r17, r28, 0, 6, 10 + subi r17, r17, 64 + bne FDP_0e60 + b FDP_0dA0 + + +FDP_029c ; lswi + subi r22, r27, 2048 + extrwi r22, r22, 5, 16 + addis r28, r27, 992 + rlwimi r17, r28, 22, 16, 20 + b FDP_02C4 + + +FDP_02b0 ; lswx + mfxer r22 + andi. r22, r22, 0x007F + rlwimi r17, r27, 0, 16, 20 + subi r22, r22, 1 + beq FDP_0dA0 + + +FDP_02c4 + andis. r23, r17, 0x001F + rlwimi r17, r22, 4, 21, 25 + not r22, r22 + insrwi r17, r22, 2, 4 + mr r19, r18 + bne FDP_0eC8 + rlwimi r17, r17, 5, 11, 15 + b FDP_0eC8 + + +FDP_02e4 + andi. r22, r17, 0x07C0 + rlwinm r28, r17, 13, 25, 29 + bne FDP_0e9C + rlwinm r22, r17, 9, 27, 28 + slw r21, r21, r22 + b FDP_0e9C + + +FDP_02fc + rlwinm. r22, r17, 28, 25, 29 + rlwinm r28, r17, 13, 25, 29 + bne FDP_0eF4 + rlwinm r23, r17, 9, 27, 28 + slw r21, r21, r23 + b FDP_0eF4 + + +FDP_0314 ; unknown table entries + mfxer r22 + + +FDP_0318 + andi. r22, r22, 0x007F + rlwimi r17, r27, 0, 16, 20 + insrwi r17, r27, 1, 3 + cmpw cr7, r27, r22 + beq FDP_0f80 + subi r22, r22, 1 + andis. r23, r17, 0x001F + rlwimi r17, r22, 4, 21, 25 + not r22, r22 + insrwi r17, r22, 2, 4 + mr r19, r18 + bne FDP_0eC8 + rlwimi r17, r17, 5, 11, 15 + b FDP_0eC8 + + +FDP_0350 ; stw(x) + li r20, 11040 + b FDP_1024 + + +FDP_0358 ; stwu(x) + clrrwi r18, r18, 1 + li r20, 11296 + b FDP_1024 + + +FDP_0364 ; stb(x) + clrrwi r18, r18, 2 + li r20, 11552 + b FDP_1024 + + +FDP_0370 + subi r23, r1, 736 + li r20, 10016 + insrwi r23, r18, 4, 28 + stb r21, 0x0000(r23) + b FDP_1000 + + +FDP_0384 + subi r23, r1, 736 + li r20, 10272 + insrwi r23, r18, 4, 28 + sth r21, 0x0000(r23) + b FDP_1000 + + +FDP_0398 + subi r23, r1, 736 + li r20, 10528 + insrwi r23, r18, 4, 28 + stw r21, 0x0000(r23) + b FDP_1000 + + +FDP_03ac + lwz r1, -0x0004(r1) + clrrwi r25, r25, 10 + insrwi r25, r19, 3, 28 + insrwi r25, r17, 5, 23 + lha r22, 0x0C00(r25) + addi r23, r1, 1248 + add r22, r22, r25 + mfsprg r1, 0 + mtlr r22 + ori r15, r15, 0x4000 + mtsprg 3, r23 + mtmsr r15 + isync + insrwi r25, r26, 8, 22 + bnelr + b MRExecuted + + + + + + + +MRAlignStores/MRAlignLoads/A little bit of vector stuff + + + +; major_0x05f00 + + ; Which to use? Probably align. + align 9 +; org FDP + 0x800 + + + + macro + MisalignmentOpcodeTableEntry &hihalf, &primaryfunc, &secondaryfunc + + dc.w &hihalf + dc.b (&primaryfunc - FDP) >> 2 + dc.b (&secondaryfunc - FDP) >> 2 + + endm + + + + macro + MisalignmentOpcodeTableMacro &FirstTable + + +; X-form extended opcodes: 0 4 8 12 16 20 24 28 +; lwarx + + MisalignmentOpcodeTableEntry 0x2540, FDP_00b8, FDP_0150 + + +; X-form extended opcodes: 64 68 72 76 80 84 88 92 + + MisalignmentOpcodeTableEntry 0x4550, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 128 132 136 140 144 148 152 156 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 192 196 200 204 208 212 216 220 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 256 260 264 268 272 276 280 284 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 320 324 328 332 336 340 344 348 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 384 388 392 396 400 404 408 412 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 448 452 456 460 464 468 472 476 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 512 516 520 524 528 532 536 540 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 576 580 584 588 592 596 600 604 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 640 644 648 652 656 660 664 668 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 704 708 712 716 720 724 728 732 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 768 772 776 780 784 788 792 796 + + MisalignmentOpcodeTableEntry 0x4430, FDP_00e4, FDP_0150 + + +; X-form extended opcodes: 832 836 840 844 848 852 856 860 + + MisalignmentOpcodeTableEntry 0x2460, FDP_00e4, FDP_0150 + + +; X-form extended opcodes: 896 900 904 908 912 916 920 924 + + MisalignmentOpcodeTableEntry 0x4130, FDP_00dc, FDP_015C + + +; X-form extended opcodes: 960 964 968 972 976 980 984 988 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 32 36 40 44 48 52 56 60 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 96 100 104 108 112 116 120 124 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 160 164 168 172 176 180 184 188 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 224 228 232 236 240 244 248 252 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 288 292 296 300 304 308 312 316 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 352 356 360 364 368 372 376 380 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 416 420 424 428 432 436 440 444 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 480 484 488 492 496 500 504 508 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 544 548 552 556 560 564 568 572 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 608 612 616 620 624 628 632 636 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 672 676 680 684 688 692 696 700 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 736 740 744 748 752 756 760 764 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 800 804 808 812 816 820 824 828 + + MisalignmentOpcodeTableEntry 0x4430, FDP_00e8, FDP_0150 + + +; X-form extended opcodes: 864 868 872 876 880 884 888 892 + + MisalignmentOpcodeTableEntry 0x45b3, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 928 932 936 940 944 948 952 956 + + MisalignmentOpcodeTableEntry 0x4130, FDP_00a4, FDP_015C + + +; X-form extended opcodes: 992 996 1000 1004 1008 1012 1016 1020 + + MisalignmentOpcodeTableEntry 0x41f2, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 1 5 9 13 17 21 25 29 + + MisalignmentOpcodeTableEntry 0x4430, FDP_00e4, FDP_0150 + + +; X-form extended opcodes: 65 69 73 77 81 85 89 93 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 129 133 137 141 145 149 153 157 + + MisalignmentOpcodeTableEntry 0x4130, FDP_00dc, FDP_015C + + +; X-form extended opcodes: 193 197 201 205 209 213 217 221 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 257 261 265 269 273 277 281 285 + + MisalignmentOpcodeTableEntry 0x268b, FDP_0314, FDP_02FC + + +; X-form extended opcodes: 321 325 329 333 337 341 345 349 + + MisalignmentOpcodeTableEntry 0x2460, FDP_00e4, FDP_0150 + + +; X-form extended opcodes: 385 389 393 397 401 405 409 413 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 449 453 457 461 465 469 473 477 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; lswx +; X-form extended opcodes: 513 517 521 525 529 533 537 541 + + MisalignmentOpcodeTableEntry 0x260b, FDP_02b0, FDP_02E4 + + +; lswi +; X-form extended opcodes: 577 581 585 589 593 597 601 605 + + MisalignmentOpcodeTableEntry 0x260f, FDP_029c, FDP_02E4 + + +; stswx +; X-form extended opcodes: 641 645 649 653 657 661 665 669 + + MisalignmentOpcodeTableEntry 0x2242, FDP_0260, FDP_0284 + + +; stswi +; X-form extended opcodes: 705 709 713 717 721 725 729 733 + + MisalignmentOpcodeTableEntry 0x224e, FDP_0254, FDP_0284 + + +; X-form extended opcodes: 769 773 777 781 785 789 793 797 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 833 837 841 845 849 853 857 861 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 897 901 905 909 913 917 921 925 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 961 965 969 973 977 981 985 989 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 33 37 41 45 49 53 57 61 + + MisalignmentOpcodeTableEntry 0x4430, FDP_00e8, FDP_0150 + + +; X-form extended opcodes: 97 101 105 109 113 117 121 125 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 161 165 169 173 177 181 185 189 + + MisalignmentOpcodeTableEntry 0x4130, FDP_00a4, FDP_015C + + +; X-form extended opcodes: 225 229 233 237 241 245 249 253 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 289 293 297 301 305 309 313 317 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 353 357 361 365 369 373 377 381 + + MisalignmentOpcodeTableEntry 0x2460, FDP_00e8, FDP_015C + + +; X-form extended opcodes: 417 421 425 429 433 437 441 445 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 481 485 489 493 497 501 505 509 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 545 549 553 557 561 565 569 573 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 609 613 617 621 625 629 633 637 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 673 677 681 685 689 693 697 701 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 737 741 745 749 753 757 761 765 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 801 805 809 813 817 821 825 829 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 865 869 873 877 881 885 889 893 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 929 933 937 941 945 949 953 957 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 993 997 1001 1005 1009 1013 1017 1021 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 2 6 10 14 18 22 26 30 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 66 70 74 78 82 86 90 94 + + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + + +; X-form extended opcodes: 130 134 138 142 146 150 154 158 +; stwcx. + + MisalignmentOpcodeTableEntry 0x2160, FDP_00b0, FDP_015C + + +; X-form extended opcodes: 194 198 202 206 210 214 218 222 + + MisalignmentOpcodeTableEntry 0x4170, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 258 262 266 270 274 278 282 286 + + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + + +; X-form extended opcodes: 322 326 330 334 338 342 346 350 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 386 390 394 398 402 406 410 414 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 450 454 458 462 466 470 474 478 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; lwbrx +; X-form extended opcodes: 514 518 522 526 530 534 538 542 + + MisalignmentOpcodeTableEntry 0x24a2, FDP_00e8, FDP_0164 + + +; X-form extended opcodes: 578 582 586 590 594 598 602 606 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; stwbrx +; X-form extended opcodes: 642 646 650 654 658 662 666 670 + + MisalignmentOpcodeTableEntry 0x2120, FDP_0088, FDP_015C + + +; X-form extended opcodes: 706 710 714 718 722 726 730 734 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; lhbrx +; X-form extended opcodes: 770 774 778 782 786 790 794 798 + + MisalignmentOpcodeTableEntry 0x1492, FDP_00e8, FDP_0160 + + +; X-form extended opcodes: 834 838 842 846 850 854 858 862 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; sthbrx +; X-form extended opcodes: 898 902 906 910 914 918 922 926 + + MisalignmentOpcodeTableEntry 0x1110, FDP_0094, FDP_015C + + +; X-form extended opcodes: 962 966 970 974 978 982 986 990 + + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + + +; X-form extended opcodes: 34 38 42 46 50 54 58 62 + + if &FirstTable + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + else + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + endif + + +; X-form extended opcodes: 98 102 106 110 114 118 122 126 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 162 166 170 174 178 182 186 190 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 226 230 234 238 242 246 250 254 + + MisalignmentOpcodeTableEntry 0x0fe2, FDP_00e8, FDP_023C + + +; eciwx +; X-form extended opcodes: 290 294 298 302 306 310 314 318 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_00e4, FDP_024C + + +; X-form extended opcodes: 354 358 362 366 370 374 378 382 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; ecowx +; X-form extended opcodes: 418 422 426 430 434 438 442 446 + + MisalignmentOpcodeTableEntry 0x03f0, FDP_00dc, FDP_024C + + +; X-form extended opcodes: 482 486 490 494 498 502 506 510 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 546 550 554 558 562 566 570 574 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 610 614 618 622 626 630 634 638 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 674 678 682 686 690 694 698 702 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 738 742 746 750 754 758 762 766 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 802 806 810 814 818 822 826 830 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 866 870 874 878 882 886 890 894 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 930 934 938 942 946 950 954 958 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; dcbz +; X-form extended opcodes: 994 998 1002 1006 1010 1014 1018 1022 + + MisalignmentOpcodeTableEntry 0x4302, FDP_01f8, FDP_020C + + +; lwzx +; X-form extended opcodes: 3 7 11 15 19 23 27 31 +; D-form opcodes: 0 32 +; lwz + + if &FirstTable + MisalignmentOpcodeTableEntry 0x0f50, FDP_00e4, FDP_0370 + else + MisalignmentOpcodeTableEntry 0x2420, FDP_00e4, FDP_0150 + endif + + +; lbzx +; X-form extended opcodes: 67 71 75 79 83 87 91 95 +; D-form opcodes: 2 34 +; lbz + + if &FirstTable + MisalignmentOpcodeTableEntry 0x2770, FDP_00d4, FDP_0398 + else + MisalignmentOpcodeTableEntry 0x0c00, FDP_00e4, FDP_0150 + endif + + +; stwx +; X-form extended opcodes: 131 135 139 143 147 151 155 159 +; D-form opcodes: 4 36 +; stw + + if &FirstTable + MisalignmentOpcodeTableEntry 0x0b90, FDP_0350, FDP_015C + else + MisalignmentOpcodeTableEntry 0x2120, FDP_00dc, FDP_015C + endif + + +; stbx +; X-form extended opcodes: 195 199 203 207 211 215 219 223 +; D-form opcodes: 6 38 +; stb + + if &FirstTable + MisalignmentOpcodeTableEntry 0x23b0, FDP_0364, FDP_015C + else + MisalignmentOpcodeTableEntry 0x0900, FDP_00dc, FDP_015C + endif + + +; lhzx +; X-form extended opcodes: 259 263 267 271 275 279 283 287 +; D-form opcodes: 8 40 +; lhz + + MisalignmentOpcodeTableEntry 0x1410, FDP_00e4, FDP_0150 + +; lhax +; X-form extended opcodes: 323 327 331 335 339 343 347 351 +; D-form opcodes: 10 42 +; lha + + MisalignmentOpcodeTableEntry 0x1450, FDP_00e4, FDP_014C + + +; sthx +; X-form extended opcodes: 387 391 395 399 403 407 411 415 +; D-form opcodes: 12 44 +; sth + + MisalignmentOpcodeTableEntry 0x1110, FDP_00dc, FDP_015C + + +; X-form extended opcodes: 451 455 459 463 467 471 475 479 +; D-form opcodes: 14 46 +; lmw + + MisalignmentOpcodeTableEntry 0x25a3, FDP_00e8, FDP_01A4 + + +; lfsx +; X-form extended opcodes: 515 519 523 527 531 535 539 543 +; D-form opcodes: 16 48 +; lfs + + MisalignmentOpcodeTableEntry 0x24e0, FDP_00e4, FDP_0174 + + +; lfdx +; X-form extended opcodes: 579 583 587 591 595 599 603 607 +; D-form opcodes: 18 50 +; lfd + + MisalignmentOpcodeTableEntry 0x44f0, FDP_00e4, FDP_0178 + + +; stfsx +; X-form extended opcodes: 643 647 651 655 659 663 667 671 +; D-form opcodes: 20 52 +; stfs + + MisalignmentOpcodeTableEntry 0x2120, FDP_0008, FDP_015C + + +; stfdx +; X-form extended opcodes: 707 711 715 719 723 727 731 735 +; D-form opcodes: 22 54 +; stfd + + MisalignmentOpcodeTableEntry 0x4130, FDP_0014, FDP_015C + + +; X-form extended opcodes: 771 775 779 783 787 791 795 799 +; D-form opcodes: 24 56 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 835 839 843 847 851 855 859 863 +; D-form opcodes: 26 58 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 899 903 907 911 915 919 923 927 +; D-form opcodes: 28 60 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; stfiwx +; X-form extended opcodes: 963 967 971 975 979 983 987 991 +; D-form opcodes: 30 62 + + MisalignmentOpcodeTableEntry 0x2120, FDP_0014, FDP_015C + + +; lwzux +; X-form extended opcodes: 35 39 43 47 51 55 59 63 +; D-form opcodes: 1 33 +; lwzu + + if &FirstTable + MisalignmentOpcodeTableEntry 0x1760, FDP_00cc, FDP_0384 + else + MisalignmentOpcodeTableEntry 0x2420, FDP_00e8, FDP_0150 + endif + + +; lbzux +; X-form extended opcodes: 99 103 107 111 115 119 123 127 +; D-form opcodes: 3 35 +; lbzu + + if &FirstTable + MisalignmentOpcodeTableEntry 0x8740, FDP_00c0, FDP_015C + else + MisalignmentOpcodeTableEntry 0x0c00, FDP_00e8, FDP_0150 + endif + + +; stwux +; X-form extended opcodes: 163 167 171 175 179 183 187 191 +; D-form opcodes: 5 37 +; stwu + + if &FirstTable + MisalignmentOpcodeTableEntry 0x23a0, FDP_0358, FDP_015C + else + MisalignmentOpcodeTableEntry 0x2120, FDP_00a4, FDP_015C + endif + + +; stbux +; X-form extended opcodes: 227 231 235 239 243 247 251 255 +; D-form opcodes: 7 39 +; stbu + + if &FirstTable + MisalignmentOpcodeTableEntry 0x8380, FDP_00c0, FDP_015C + else + MisalignmentOpcodeTableEntry 0x0900, FDP_00a4, FDP_015C + endif + + +; lhzux +; X-form extended opcodes: 291 295 299 303 307 311 315 319 +; D-form opcodes: 9 41 +; lhzu + + MisalignmentOpcodeTableEntry 0x1410, FDP_00e8, FDP_0150 + + +; lhaux +; X-form extended opcodes: 355 359 363 367 371 375 379 383 +; D-form opcodes: 11 43 +; lhau + + if &FirstTable + MisalignmentOpcodeTableEntry 0x8740, FDP_00c0, FDP_015C + else + MisalignmentOpcodeTableEntry 0x1450, FDP_00e8, FDP_014C + endif + + +; sthux +; X-form extended opcodes: 419 423 427 431 435 439 443 447 +; D-form opcodes: 13 45 +; sthu + + MisalignmentOpcodeTableEntry 0x1110, FDP_00a4, FDP_015C + + +; X-form extended opcodes: 483 487 491 495 499 503 507 511 +; D-form opcodes: 15 47 +; stmw + + if &FirstTable + MisalignmentOpcodeTableEntry 0x8380, FDP_00c0, FDP_015C + else + MisalignmentOpcodeTableEntry 0x21e2, FDP_00a4, FDP_01D8 + endif + + +; lfsux +; X-form extended opcodes: 547 551 555 559 563 567 571 575 +; D-form opcodes: 17 49 +; lfsu + + MisalignmentOpcodeTableEntry 0x24e0, FDP_00e8, FDP_0174 + + +; lfdux +; X-form extended opcodes: 611 615 619 623 627 631 635 639 +; D-form opcodes: 19 51 +; lfdu + + MisalignmentOpcodeTableEntry 0x44f0, FDP_00e8, FDP_0178 + + +; stfsux +; X-form extended opcodes: 675 679 683 687 691 695 699 703 +; D-form opcodes: 21 53 +; stfsu + + MisalignmentOpcodeTableEntry 0x2120, FDP_000c, FDP_015C + + +; stfdux +; X-form extended opcodes: 739 743 747 751 755 759 763 767 +; D-form opcodes: 23 55 +; stfdu + + MisalignmentOpcodeTableEntry 0x4130, FDP_0018, FDP_015C + + +; X-form extended opcodes: 803 807 811 815 819 823 827 831 +; D-form opcodes: 25 57 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 867 871 875 879 883 887 891 895 +; D-form opcodes: 27 59 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 931 935 939 943 947 951 955 959 +; D-form opcodes: 29 61 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + +; X-form extended opcodes: 995 999 1003 1007 1011 1015 1019 1023 +; D-form opcodes: 31 63 + + MisalignmentOpcodeTableEntry 0x07f0, FDP_panic, FDP_0004 + + endm + + + + MisalignmentOpcodeTableMacro 1 + MisalignmentOpcodeTableMacro 0 + + + + + + + + + +HalfWordTable removed from here + + + + macro + MixedTableEntry &flags, &target + + dc.b &flags + dc.b (&target - FDP) >> 2 + + endm + +; this is the d20 table +MixedTable + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_014C + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %11, FDP_0160 + MixedTableEntry %11, FDP_0164 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0174 + MixedTableEntry %01, FDP_0178 + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_0150 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %11, FDP_01A4 + MixedTableEntry %11, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %11, FDP_01D8 + MixedTableEntry %11, FDP_0004 + MixedTableEntry %11, FDP_02E4 + MixedTableEntry %11, FDP_02E4 + MixedTableEntry %11, FDP_02E4 + MixedTableEntry %11, FDP_02E4 + MixedTableEntry %11, FDP_0284 + MixedTableEntry %11, FDP_0284 + MixedTableEntry %11, FDP_0284 + MixedTableEntry %11, FDP_0284 + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_02FC + MixedTableEntry %11, FDP_020C + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_0370 + MixedTableEntry %01, FDP_0384 + MixedTableEntry %01, FDP_0398 + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_015C + MixedTableEntry %01, FDP_0004 + MixedTableEntry %01, FDP_0004 + MixedTableEntry %11, FDP_023C + MixedTableEntry %01, FDP_024C + + + +FDP_0DA0 + li r0, -3 + sc + andi. r23, r16, 0x0020 + addi r10, r10, 4 + mfsprg SP, 0 + mtsrr0 r10 + mtsrr1 r11 + bne FDP_0E30 + mtlr r12 + bns cr3, FDP_0DFC + + +FDP_0DC8 + mtcrf 255, r13 + lmw r2, 0x0008(SP) + lwz r0, 0x0000(SP) + lwz SP, 0x0004(SP) + rfi + dcb.b 32, 0 + + +FDP_0DFC + mtcrf 255, r13 + lmw r10, 0x0028(SP) + lwz r0, 0x0000(SP) + lwz SP, 0x0004(SP) + rfi + dcb.b 32, 0 + + +FDP_0E30 + mfsprg r24, 3 + mtsprg 2, r12 + rlwinm r16, r16, 0, 27, 25 + lwz r12, 0x0034(r24) + stw r16, -0x0010(SP) + mtcrf 255, r13 + mtlr r12 + lmw r2, 0x0008(SP) + lwz r0, 0x0000(SP) + lwz SP, 0x0004(SP) + mtsprg 1, SP + blrl + + +FDP_0E60 + andi. r23, r17, 0x07C0 + rlwinm r28, r17, 13, 25, 29 + lwzx r21, SP, r28 + li r22, 8 + insrwi r17, r22, 6, 26 + addi r19, r19, 4 + bne FDP_03AC + rlwinm r22, r17, 9, 27, 28 + srw r21, r21, r22 + extrwi r22, r17, 2, 4 + neg r22, r22 + add r19, r19, r22 + addi r22, r22, 4 + insrwi. r17, r22, 5, 26 + b FDP_03AC + + +FDP_0E9C + rlwinm r23, r17, 18, 25, 29 + cmpw cr7, r28, r23 + rlwinm r23, r17, 23, 25, 29 + cmpw cr6, r28, r23 + beq cr7, FDP_0EB8 + beq cr6, FDP_0EB8 + stwx r21, SP, r28 + + +FDP_0EB8 + addis r28, r17, 32 + rlwimi r17, r28, 0, 6, 10 + subi r17, r17, 64 + beq FDP_0DA0 + + +FDP_0EC8 + andi. r23, r17, 0x07C0 + li r22, 9 + insrwi r17, r22, 6, 26 + addi r19, r19, 4 + bne FDP_03AC + extrwi r22, r17, 2, 4 + neg r22, r22 + add r19, r19, r22 + addi r22, r22, 4 + insrwi. r17, r22, 5, 26 + b FDP_03AC + + +FDP_0EF4 + rlwinm r23, r17, 18, 25, 29 + cmpw cr7, r28, r23 + rlwinm r23, r17, 23, 25, 29 + cmpw cr6, r28, r23 + beq cr7, FDP_0F10 + beq cr6, FDP_0F10 + stwx r21, SP, r28 + + +FDP_0F10 + addis r28, r17, 32 + rlwimi r17, r28, 0, 6, 10 + subi r17, r17, 64 + not r22, r22 + rlwimi r22, r17, 6, 30, 31 + li r28, 1 + mfxer r23 + extrwi r23, r23, 8, 16 + srwi r20, r21, 24 + cmpw cr7, r20, r23 + add. r22, r22, r28 + beq cr7, FDP_0F80 + beq FDP_0F80 + extrwi r20, r21, 8, 8 + cmpw cr7, r20, r23 + add. r22, r22, r28 + beq cr7, FDP_0F80 + beq FDP_0F80 + extrwi r20, r21, 8, 16 + cmpw cr7, r20, r23 + add. r22, r22, r28 + beq cr7, FDP_0F80 + beq FDP_0F80 + clrlwi r20, r21, 24 + cmpw cr7, r20, r23 + add. r22, r22, r28 + beq cr7, FDP_0F80 + bne FDP_0EC8 + + +FDP_0F80 + rlwinm. r28, r17, 0, 3, 3 + mfxer r23 + add r22, r22, r23 + insrwi r23, r22, 7, 25 + mtxer r23 + beq FDP_0DA0 + mfcr r23 + clrlwi r23, r23, 30 + insrwi r13, r23, 4, 0 + b FDP_0DA0 + + +FDP_0FA8 + clrrwi r20, r21, 31 + xor. r21, r20, r21 + beq FDP_0178 + rlwinm. r23, r21, 16, 17, 24 + addi r23, r23, 128 + rlwimi r20, r21, 29, 5, 31 + extsh r23, r23 + rlwimi r20, r21, 0, 1, 1 + slwi r21, r21, 29 + subi r23, r23, 16512 + rlwimi r20, r23, 0, 2, 4 + bne FDP_0178 + srwi r21, r21, 20 + insrwi r21, r20, 20, 0 + cntlzw r23, r21 + slw r21, r21, r23 + neg r23, r23 + rlwimi r20, r21, 21, 12, 31 + addi r23, r23, 896 + slwi r21, r21, 21 + insrwi r20, r23, 11, 1 + b FDP_0178 + + +FDP_1000 + clrrwi r21, r25, 10 + rlwimi r21, r17, 14, 24, 28 + rlwimi r14, r11, 0, 6, 6 + add r21, r21, r20 + mtmsr r14 + mtlr r21 + isync + oris r11, r11, 0x0200 + blr + + +FDP_1024 + clrrwi r19, r25, 10 + rlwimi r19, r17, 14, 24, 28 + add r19, r19, r20 + mtlr r19 + rlwimi r14, r11, 0, 6, 6 + subi r23, SP, 736 + mtmsr r14 + insrwi r23, r18, 4, 28 + isync + blr + + +FDP_104c + oris r11, r11, 0x0200 + lbz r21, 0x0000(r23) + b FDP_00E4 + + +FDP_1058 + oris r11, r11, 0x0200 + lhz r21, 0x0000(r23) + b FDP_00E4 + + +FDP_1064 + oris r11, r11, 0x0200 + lwz r21, 0x0000(r23) + b FDP_00E4 + + + + + + + + + +; Called by setup. QEMU naturally complains. + +; SPRs: +;MMCR0 equ 952 ; monitor control register 0 +MMCR1 equ 956 ; monitor control register 1 +MMCR2 equ 944 ; monitor control register 2 +;PMC1 equ 953 ; performance counter 1 +;PMC2 equ 954 ; performance counter 2 +PMC3 equ 957 ; performance counter 3 +PMC4 equ 958 ; performance counter 4 +BAMR equ 951 ; breakpoint address mask register 1 +;SIA equ 955 ; sampled instruction address 1 +;SDA equ 959 ; sampled data address (604 only?) + + + macro + TestSPR &dest, &goodgpr, &badgpr, &spr + + mtspr &spr, &goodgpr + not &badgpr, &goodgpr + mfspr &badgpr, &spr + xor&dot &dest, &goodgpr, &badgpr + + endm + + + +ProbePerfMonitor ; OUTSIDE REFERER + + ; We will populate r23 with bit fields describing perf monitor capabilities + li r23, 0 + + + ; Temporarily disable program interrupts (leave old handler in r20) + lwz r21, KDP.PA_NanoKernelCode(r1) + lwz r20, KDP.VecBaseSystem + VecTable.ProgramIntVector(r1) + llabel r18, IgnoreSoftwareInt + add r21, r18, r21 + stw r21, KDP.VecBaseSystem + VecTable.ProgramIntVector(r1) + + + + ; SET BIT 31 if all the 604 perf monitor registers work + + li r18, 0 + + TestSPR r17, r18, r19, MMCR0 + TestSPR r19, r18, r19, PMC1 + or r17, r17, r19 + TestSPR r19, r18, r19, PMC2 + or r17, r17, r19 + TestSPR r19, r18, r19, SIA + or. r17, r17, r19 + + bne @dont_set_bit_31 + _bset r23, r23, 31 +@dont_set_bit_31 + + ; ONLY test for bits 28-30 if bit 31 was just set... + + mr. r23, r23 + beq @stop_testing_perf_monitor + + ; SET BIT 30 if all the 750 perf monitor registers work + + TestSPR r17, r18, r19, MMCR1 + TestSPR r19, r18, r19, PMC3 + or r17, r17, r19 + TestSPR r19, r18, r19, PMC4 + or. r17, r17, r19 + + bne @dont_set_bit_30 + _bset r23, r23, 30 +@dont_set_bit_30 + + ; SET BIT 29 if SDA (604 but not 750) works + + li r18, 0xaaa0 + TestSPR. r17, r18, r19, SDA + + beq @dont_set_bit_29 + _bset r23, r23, 29 +@dont_set_bit_29 + + ; SET BIT 28 if EVEN MORE perf monitor registers work + + li r18, 0x00 + TestSPR r17, r18, r19, MMCR2 + + li r18, 0x00 + TestSPR r19, r18, r19, BAMR + + or. r17, r17, r19 + + bne @dont_set_bit_28 + _bset r23, r23, 28 +@dont_set_bit_28 + +@stop_testing_perf_monitor + + + ; Restore program interrupts + stw r20, KDP.VecBaseSystem + VecTable.ProgramIntVector(r1) + + + ; Test r23 and save + mr. r23, r23 + stw r23, KDP.PerfMonitorBits(r1) + + + ; Set HiLevelPerfMonitorBits + li r23, 0 + _bset r23, r23, 14 + _bset r23, r23, 15 + + + ; SET BIT 18 if any perf monitor features present + beq * + 8 + _bset r23, r23, 18 + + + ; And save + stw r23, KDP.HiLevelPerfMonitorBits(r1) + + + ; Now do some insane arithmetic with the decrementer clock. TBE. + + lisori r20, 0x80587ff3 + lisori r21, 0xd62611e3 + + ; Left-justify the decrementer clock rate + lwz r19, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1) + cntlzw r23, r19 + slw r19, r19, r23 + + cmpw cr1, r20, r19 + addi r23, r23, 0x02 + xor. r24, r24, r24 + bge cr1, ProbePerfMonitor_0x180 + addi r23, r23, -0x01 + +ProbePerfMonitor_0x160 + cmpwi cr1, r20, 0x00 + slwi r20, r20, 1 + rlwimi r20, r21, 1, 31, 31 + cmplw cr2, r20, r19 + rlwinm. r24, r24, 1, 0, 30 + slwi r21, r21, 1 + blt cr1, ProbePerfMonitor_0x180 + blt cr2, ProbePerfMonitor_0x188 + +ProbePerfMonitor_0x180 + subf r20, r19, r20 + ori r24, r24, 0x01 + +ProbePerfMonitor_0x188 + bge ProbePerfMonitor_0x160 + stw r24, 0x05bc(r1) + stb r23, 0x05b8(r1) + li r21, 0x20 + subf r21, r23, r21 + stb r21, 0x05bb(r1) + blr + + + +FDPEmulateInstruction + + mfsprg r1, 0 + lwz r8, 0x0104(r6) + stw r8, 0x0000(r1) + stw r2, 0x0008(r1) + stw r3, 0x000c(r1) + stw r4, 0x0010(r1) + stw r5, 0x0014(r1) + stmw r14, 0x0038(r1) + mr r16, r7 + lwz r7, 0x013c(r6) + stw r7, 0x001c(r1) + lwz r8, 0x0144(r6) + stw r8, 0x0020(r1) + lwz r9, 0x014c(r6) + stw r9, 0x0024(r1) + lwz r23, 0x0154(r6) + stw r23, 0x0028(r1) + lwz r23, 0x015c(r6) + stw r23, 0x002c(r1) + lwz r23, 0x0164(r6) + stw r23, 0x0030(r1) + lwz r23, 0x016c(r6) + stw r23, 0x0034(r1) + lwz r1, -0x0004(r1) + addi r22, r6, 0xc4 + lwz r23, 0x0ea0(r1) + lwz r25, 0x0650(r1) + addi r23, r23, 0x01 + stw r23, 0x0ea0(r1) + mfsprg r24, 3 + addi r23, r1, 0x4e0 + mfmsr r14 + ori r15, r14, 0x10 + mtsprg 3, r23 + mtmsr r15 + isync + lwz r27, 0x0000(r10) + mtmsr r14 + isync + mtsprg 3, r24 + srwi r23, r27, 26 + cmpwi cr6, r23, 0x09 + cmpwi r23, 0x16 + cmpwi cr1, r23, 0x1f + lwz r20, 0x05b8(r1) + rlwinm r21, r16, 15, 14, 14 + neg r21, r21 + rlwimi r21, r16, 14, 16, 16 + or r21, r21, r20 + rlwimi r21, r27, 0, 21, 31 + rlwimi r16, r16, 27, 26, 26 + mfsprg r1, 0 + rlwinm r17, r27, 13, 25, 29 + rlwinm r18, r27, 18, 25, 29 + beq cr6, FDP_1214_0x2b4 + mtcrf 0x3f, r21 + rlwinm r19, r27, 23, 25, 29 + beq FDP_1bd0 + bne cr1, FDP_1324 + rlwinm r21, r27, 2, 24, 28 + add r21, r21, r25 + lwz r20, 0x1374(r21) + rlwinm r23, r27, 26, 27, 31 + lwz r21, 0x1378(r21) + rotlw. r20, r20, r23 + add r21, r21, r25 + mtlr r21 + bltlr + +FDP_1324 + ble cr1, FDP_1338 + lis r20, 0x5556 + ori r20, r20, 0x5500 + rotlw. r20, r20, r23 + blt FDP_1c18 + +FDP_1338 + mtcrf 0x70, r11 + li r8, 0x04 + ble cr3, FDP_1354 + + +FDP_1344 + mtcrf 0x0f, r11 + li r8, 0x04 + ble cr4, FDP_1354 + li r8, 0x05 + +FDP_1354 + lwz r6, -0x0004(r1) + lwz r9, 0x0ea0(r6) + lmw r14, 0x0038(r1) + addi r9, r9, -0x01 + stw r9, 0x0ea0(r6) + lwz r6, -0x0014(r1) + lwz r7, -0x0010(r1) + b CodeLikeException + + + +; What the hell is this? +ProgramIntTable + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00910091, FDP_148c - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x10301030, 0x0000151c + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00328000, 0x000016d0 + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x0080a000, 0x00001c18 + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x55545502, 0x00001c20 + dc.l 0x0f000f0c, 0x00001ad0 + dc.l 0x0a008a08, 0x00001aa8 + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x80008000, 0x00001b8c + dc.l 0x00000000, FDP_1338 - FDP + dc.l 0x00000000, FDP_1338 - FDP + +FDP_1474 + stw r20, 0(r22) + + +FDP_1478 + bns cr7, FDP_1484 + mfcr r23 + rlwimi r13, r23, 0, 0, 3 + +FDP_1484 + stwx r21, r1, r17 + b FDP_0da0 + +FDP_148c + bns cr2, FDP_1338 + lwzx r18, SP, r18 + bge cr6, FDP_14EC + bgt cr5, FDP_14B0 + mr. r21, r18 + crxor cr5_SO, cr5_SO, cr0_LT + bns cr5, FDP_1478 + neg. r21, r18 + b FDP_1478 + +FDP_14b0 + li r21, 0 + addo. r21, r18, r21 + crxor cr5_SO, cr5_SO, cr0_LT + bns cr5, FDP_1478 + nego. r21, r18 + b FDP_1478 + +FDP_1214_0x2b4 + mtcrf 0x3f, r21 + bns cr2, FDP_1338 + lwzx r18, r1, r18 + extsh r19, r27 + cmpw cr1, r19, r18 + subf r21, r21, r21 + blt cr1, FDP_1484 + subf r21, r18, r19 + b FDP_1484 + +FDP_14ec + lwzx r19, SP, r19 + bgt cr5, FDP_1508 + cmpw cr1, r19, r18 + sub. r21, r21, r21 + blt cr1, FDP_1478 + sub. r21, r19, r18 + b FDP_1478 + + +FDP_1508 + cmpw cr1, r19, r18 + subo. r21, r21, r21 + blt cr1, FDP_1478 + subo. r21, r19, r18 + b FDP_1478 + bge cr2, FDP_1338 + lwzx r19, SP, r19 + lwzx r18, SP, r18 + bne cr5, FDP_16B8 + cmpwi cr1, r19, 0 + bgt cr6, FDP_1548 + lwz r24, 0(r22) + srwi r21, r24, 31 + add. r21, r21, r18 + bne FDP_1590 + mr r18, r24 + + +FDP_1548 + cmpwi r19, -1 + bgt cr5, FDP_1574 + beq FDP_1568 + beq cr1, FDP_1580 + divw r21, r18, r19 + + +FDP_155c + mullw r20, r21, r19 + sub. r20, r18, r20 + b FDP_1474 + + +FDP_1568 + neg r21, r18 + sub. r20, r18, r18 + b FDP_1474 + + +FDP_1574 + divwo r21, r18, r19 + beq FDP_1568 + bne cr1, FDP_155C + + +FDP_1580 + rlwinm r23, r18, 2, 30, 30 + subi r21, r23, 1 + mr. r20, r18 + b FDP_1474 + + +FDP_1590 + mfxer r26 ; XER = 1 + beq cr1, FDP_1698 + cmpwi r19, 0 + cmpwi cr1, r18, 0 + crxor cr1_SO, cr0_LT, cr1_LT + bge FDP_15AC + neg r19, r19 + + +FDP_15ac + bge cr1, FDP_15B8 + subfic r24, r24, 0 + subfze r18, r18 + + +FDP_15b8 + cmplw r18, r19 + bge FDP_1698 + cntlzw r21, r19 + xor r18, r18, r24 + slw r19, r19, r21 + rotlw r18, r18, r21 + slw r24, r24, r21 + xor r18, r18, r24 + srwi r23, r19, 16 + divwu r20, r18, r23 + mullw r23, r20, r23 + sub r18, r18, r23 + slwi r18, r18, 16 + inslwi r18, r24, 16, 16 + slwi r24, r24, 16 + clrlwi r23, r19, 16 + mullw r23, r20, r23 + subc r18, r18, r23 + subfe. r23, r23, r23 + add r24, r24, r20 + bge FDP_161C + + +FDP_160c + addc r18, r18, r19 + addze. r23, r23 + subi r24, r24, 1 + blt FDP_160C + + +FDP_161c + srwi r23, r19, 16 + divwu r20, r18, r23 + mullw r23, r20, r23 + sub r18, r18, r23 + slwi r18, r18, 16 + inslwi r18, r24, 16, 16 + slwi r24, r24, 16 + clrlwi r23, r19, 16 + mullw r23, r20, r23 + subc r18, r18, r23 + subfe. r23, r23, r23 + add r24, r24, r20 + bge FDP_1660 + + +FDP_1650 + addc r18, r18, r19 + addze. r23, r23 + subi r24, r24, 1 + blt FDP_1650 + + +FDP_1660 + srw r20, r18, r21 + mr. r21, r24 + bge cr1, FDP_1670 + neg r20, r20 + + +FDP_1670 + bns cr1, FDP_1678 + neg. r21, r21 + + +FDP_1678 + ble cr5, FDP_168C + crxor cr0_LT, cr0_LT, cr1_SO + rlwinm r26, r26, 0, 2, 0 + bge FDP_168C + oris r26, r26, 0xC000 + + +FDP_168c + mtxer r26 ; XER = 1 + mr. r20, r20 + b FDP_1474 + + +FDP_1698 + ble cr5, FDP_16A0 + oris r26, r26, 0xC000 + + +FDP_16a0 + mtxer r26 ; XER = 1 + not r21, r18 + srwi r23, r18, 31 + mr. r20, r24 + add r21, r23, r21 + b FDP_1474 + + +FDP_16b8 + mulhw r21, r18, r19 + bgt cr5, FDP_16C8 + mullw. r20, r18, r19 + b FDP_1474 + + +FDP_16c8 + mullwo. r20, r18, r19 + b FDP_1474 + bgt cr6, FDP_18D8 + bgt cr5, FDP_1A64 + cmpwi r18, 64 + cmpwi cr1, r18, 0 + cmpwi cr6, r18, 4 + bso cr5, FDP_1938 + bge FDP_17F8 + crclr cr0_LT + beq cr1, FDP_1734 + beq cr6, FDP_1740 + cmpwi cr1, r18, 20 + cmpwi cr6, r18, 24 + beq cr1, FDP_1750 + beq cr6, FDP_17C8 + cmpwi cr1, r18, 32 + cmpwi cr6, r18, 36 + beq cr1, FDP_17D4 + beq cr6, FDP_17E8 + cmpwi cr6, r18, 16 + lwzx r18, SP, r18 + lwzx r19, SP, r19 + add. r21, r18, r19 + beq cr6, FDP_1750 + bne cr3, FDP_1338 + b FDP_1B54 + + +FDP_1734 + bge cr2, FDP_1338 + lwz r21, 0(r22) + b FDP_1478 + + +FDP_1740 + bne cr3, FDP_1338 + mtcrf %10000000, r13 + dc.l 0x7EA102A7 ; mfxer r21 | bit 31 + b FDP_1478 + + +FDP_1750 + ble cr2, FDP_1338 + lwz r22, -0x0004(SP) + + +FDP_1758 + mftbu r20 + mftb r21 + mftbu r23 + cmplw cr1, r23, r20 + bne- cr1, FDP_1758 + lwz r23, 0x05BC(r22) + lbz r18, 0x05B8(r22) + lbz r19, 0x05BB(r22) + mullw r22, r20, r23 + mulhwu r24, r21, r23 + add r22, r22, r24 + bne cr6, FDP_17A8 + cmplw cr1, r22, r24 + srw r22, r22, r19 + mulhwu r21, r20, r23 + bge+ cr1, FDP_179C + addi r21, r21, 1 + + +FDP_179c + slw r21, r21, r18 + add r21, r21, r22 + b FDP_1478 + + +FDP_17a8 + mullw r21, r21, r23 + srw r21, r21, r19 + slw r22, r22, r18 + add r21, r21, r22 + lis r23, 15258 + ori r23, r23, 0xCA00 + mulhwu r21, r21, r23 + b FDP_1478 + + +FDP_17c8 + bne cr2, FDP_1338 + mfdec r21 ; DEC = 22 + b FDP_1478 + + +FDP_17d4 + bne cr3, FDP_1338 + mtcrf %10000000, r13 + mtlr r12 ; LR = 8 + dc.l 0x7EA802A7 ; mflr r21 | bit 31 + b FDP_1478 + + +FDP_17e8 + bne cr3, FDP_1338 + mtcrf %10000000, r13 + dc.l 0x7EA902A7 ; mfctr r21 | bit 31 + b FDP_1478 + + +FDP_17f8 + lwz r23, -0x0004(SP) + mtcrf %10000000, r13 + lwz r23, 0x05C0(r23) + extrwi r19, r27, 10, 11 + cmplwi cr1, r19, 0x03E8 + beq cr1, FDP_187C + clrlslwi r23, r23, 28, 20 + bne cr4, FDP_1344 + mtcrf 32, r23 + cmplwi cr1, r19, 0x031D + beq cr1, FDP_1898 + cmplwi cr1, r19, 0x033D + beq cr1, FDP_18A0 + cmplwi cr1, r19, 0x035D + beq cr1, FDP_18A8 + cmplwi cr1, r19, 0x037D + beq cr1, FDP_18B0 + bgt cr2, FDP_1848 + cmplwi cr1, r19, 0x03FD + beq cr1, FDP_18D0 + + +FDP_1848 + bne cr2, FDP_1344 + cmplwi cr1, r19, 0x039D + beq cr1, FDP_18B8 + cmplwi cr1, r19, 0x03BD + beq cr1, FDP_18C0 + cmplwi cr1, r19, 0x03DD + beq cr1, FDP_18C8 + bge cr2, FDP_1344 + cmplwi cr1, r19, 0x021D + beq cr1, FDP_1888 + cmplwi cr1, r19, 0x02FD + beq cr1, FDP_1890 + b FDP_1344 + + +FDP_187c + ble cr4, FDP_1344 + dc.l 0x7EBF42A7 ; mfpvr r21 | bit 31 + b FDP_1478 + + +FDP_1888 + dc.l 0x7EB0EAA7 ; mfspr r21, MMCR2 | bit 31 + b FDP_1478 + + +FDP_1890 + dc.l 0x7EB7EAA7 ; mfspr r21, BAMR | bit 31 + b FDP_1478 + + +FDP_1898 + dc.l 0x7EB8EAA7 ; mfspr r21, MMCR0 | bit 31 + b FDP_1478 + + +FDP_18a0 + dc.l 0x7EB9EAA7 ; mfspr r21, PMC1 | bit 31 + b FDP_1478 + + +FDP_18a8 + dc.l 0x7EBAEAA7 ; mfspr r21, PMC2 | bit 31 + b FDP_1478 + + +FDP_18b0 + dc.l 0x7EBBEAA7 ; mfspr r21, SIA | bit 31 + b FDP_1478 + + +FDP_18b8 + dc.l 0x7EBCEAA7 ; mfspr r21, MMCR1 | bit 31 + b FDP_1478 + + +FDP_18c0 + dc.l 0x7EBDEAA7 ; mfspr r21, PMC3 | bit 31 + b FDP_1478 + + +FDP_18c8 + dc.l 0x7EBEEAA7 ; mfspr r21, PMC4 | bit 31 + b FDP_1478 + + +FDP_18d0 + dc.l 0x7EBFEAA7 ; mfspr r21, SDA | bit 31 + b FDP_1478 + + +FDP_18d8 + extrwi r23, r27, 10, 11 + cmplwi cr1, r23, 0x0188 + cmplwi cr6, r23, 0x01A8 + cror cr0_EQ, cr1_EQ, cr6_EQ + bne FDP_1338 + + +FDP_18ec + DIALECT POWER + mfrtcu r20 ; RTCU = 4 + mfrtcl r21 ; RTCL = 5 + mfrtcu r23 ; RTCU = 4 + DIALECT PowerPC + + xor. r23, r23, r20 + lis r23, 15258 + ori r23, r23, 0xCA00 + bne- FDP_18EC + mfspr r24, MQ ; 0 + crset cr3_SO + mullw r19, r20, r23 + mtspr MQ, r24 ; 0 + add r21, r21, r19 + beq cr1, FDP_1484 + cmplw r21, r19 + mulhwu r21, r20, r23 + mtspr MQ, r24 ; 0 + bge FDP_1484 + addi r21, r21, 1 + b FDP_1484 + + +FDP_1938 + lwzx r17, SP, r17 + bge FDP_1998 + mr. r17, r17 + beq cr1, FDP_1964 + bne cr3, FDP_1338 + beq cr6, FDP_1970 + cmpwi cr1, r18, 32 + cmpwi cr6, r18, 36 + beq cr1, FDP_197C + beq cr6, FDP_198C + b FDP_1B54 + + +FDP_1964 + bge cr2, FDP_1338 + stw r17, 0(r22) + b FDP_1B54 + + +FDP_1970 + mtcrf %10000000, r13 + dc.l 0x7E2103A7 ; mtxer r17 | bit 31 + b FDP_1B54 + + +FDP_197c + mtcrf %10000000, r13 + mr r12, r17 + dc.l 0x7E2803A7 ; mtlr r17 | bit 31 + b FDP_1B54 + + +FDP_198c + mtcrf %10000000, r13 + dc.l 0x7E2903A7 ; mtctr r17 | bit 31 + b FDP_1B54 + + +FDP_1998 + lwz r23, -0x0004(SP) + bne cr4, FDP_1344 + lwz r23, 0x05C0(r23) + mtcrf %10000000, r13 + clrlslwi r23, r23, 28, 20 + extrwi r19, r27, 10, 11 + mtcrf 32, r23 + cmplwi cr1, r19, 0x031D + beq cr1, FDP_1A24 + cmplwi cr1, r19, 0x033D + beq cr1, FDP_1A2C + cmplwi cr1, r19, 0x035D + beq cr1, FDP_1A34 + cmplwi cr1, r19, 0x037D + beq cr1, FDP_1A3C + bgt cr2, FDP_19E0 + cmplwi cr1, r19, 0x03FD + beq cr1, FDP_1A5C + + +FDP_19e0 + bne cr2, FDP_1344 + cmplwi cr1, r19, 0x039D + beq cr1, FDP_1A44 + cmplwi cr1, r19, 0x03BD + beq cr1, FDP_1A4C + cmplwi cr1, r19, 0x03DD + beq cr1, FDP_1A54 + bge cr2, FDP_1344 + cmplwi cr1, r19, 0x021D + beq cr1, FDP_1A14 + cmplwi cr1, r19, 0x02FD + beq cr1, FDP_1A1C + b FDP_1344 + + +FDP_1a14 + dc.l 0x7E30EBA7 ; mtspr r17, MMCR2 | bit 31 + b FDP_1B54 + + +FDP_1a1c + dc.l 0x7E37EBA7 ; mtspr r17, BAMR | bit 31 + b FDP_1B54 + + +FDP_1a24 + dc.l 0x7E38EBA7 ; mtspr r17, MMCR0 | bit 31 + b FDP_1B54 + + +FDP_1a2c + dc.l 0x7E39EBA7 ; mtspr r17, PMC1 | bit 31 + b FDP_1B54 + + +FDP_1a34 + dc.l 0x7E3AEBA7 ; mtspr r17, PMC2 | bit 31 + b FDP_1B54 + + +FDP_1a3c + dc.l 0x7E3BEBA7 ; mtspr r17, SIA | bit 31 + b FDP_1B54 + + +FDP_1a44 + dc.l 0x7E3CEBA7 ; mtspr r17, MMCR1 | bit 31 + b FDP_1B54 + + +FDP_1a4c + dc.l 0x7E3DEBA7 ; mtspr r17, PMC3 | bit 31 + b FDP_1B54 + + +FDP_1a54 + dc.l 0x7E3EEBA7 ; mtspr r17, PMC4 | bit 31 + b FDP_1B54 + + +FDP_1a5c + dc.l 0x7E3FEBA7 ; mtspr r17, SDA | bit 31 + b FDP_1B54 + + +FDP_1a64 + lwz r23, -0x0004(SP) + bge cr3, FDP_1338 + extrwi. r18, r27, 4, 12 + rlwinm r21, r27, 16, 28, 30 + cmpwi cr1, r21, 10 + addi r18, r18, 6808 + lbzx r18, r25, r18 + addi r21, r23, 3872 + beq cr1, FDP_1A90 + lhzx r21, r21, r18 + b FDP_1478 + + +FDP_1a90 + lwzx r21, r21, r18 + b FDP_1478 + + DIALECT POWER + dozi SP, r4, 9252 + dozi r17, r8, 10784 + dc.l 0x2c2e1814 ; cmpdi r14, 6164 + DIALECT PowerPC + + subfic r17, r4, 9252 + lwzx r19, SP, r19 + clrlwi r19, r19, 27 + bso cr5, FDP_1B1C + bns cr2, FDP_1338 + lwzx r17, SP, r17 + lis r23, -32768 + lwzx r21, SP, r18 + srw r23, r23, r19 + srw r17, r17, r19 + b FDP_1C08 + bgt cr6, FDP_1B18 + lwzx r19, SP, r19 + clrlwi r19, r19, 26 + bge cr6, FDP_1B1C + cmpwi r19, 31 + crnot cr5_SO, cr5_SO + ble FDP_1B1C + bge cr2, FDP_1338 + lwz r20, 0(r22) + li r23, -1 + clrlwi r19, r19, 27 + bgt cr5, FDP_1B0C + slw r23, r23, r19 + and. r21, r20, r23 + b FDP_1B50 + + +FDP_1b0c + srw r23, r23, r19 + and. r21, r20, r23 + b FDP_1B50 + + +FDP_1b18 + extrwi r19, r27, 5, 16 + + +FDP_1b1c + bge cr2, FDP_1338 + lwzx r17, SP, r17 + bgt cr5, FDP_1B64 + slw. r21, r17, r19 + rotlw r20, r17, r19 + bge cr6, FDP_1B4C + li r23, -1 + slw r23, r23, r19 + + +FDP_1b3c + lwz r19, 0(r22) + andc r23, r19, r23 + or. r21, r21, r23 + bns cr5, FDP_1B50 + + +FDP_1b4c + stw r20, 0(r22) + + +FDP_1b50 + stwx r21, r1, r18 + + +FDP_1b54 + bns cr7, FDP_0da0 + mfcr r23 + rlwimi r13, r23, 0, 0, 3 + b FDP_0da0 + + +FDP_1b64 + neg r20, r19 + rotlw r20, r17, r20 + beq cr5, FDP_1B84 + srw. r21, r17, r19 + bge cr6, FDP_1B4C + li r23, -1 + srw r23, r23, r19 + b FDP_1B3C + + +FDP_1b84 + sraw. r21, r17, r19 + b FDP_1B4C + bns cr2, FDP_1338 + lwzx r19, SP, r19 + lwzx r17, SP, r17 + bgt cr5, FDP_1BBC + li r21, -1 + sub r19, r19, r17 + not r19, r19 + clrlwi r19, r19, 27 + neg r17, r17 + slw r21, r21, r19 + rotlw. r21, r21, r17 + b FDP_1B50 + + +FDP_1bbc + lwzx r21, SP, r18 + and r17, r17, r19 + andc r21, r21, r19 + or. r21, r21, r17 + b FDP_1B50 + + +FDP_1bd0 + bns cr2, FDP_1338 + lwzx r17, r1, r17 + rlwinm r20, r27, 26, 27, 31 + lwzx r19, r1, r19 + rlwinm r21, r27, 31, 27, 31 + li r23, -0x01 + subf r21, r20, r21 + not r21, r21 + clrlwi r21, r21, 0x1b + neg r20, r20 + slw r23, r23, r21 + lwzx r21, r1, r18 + rotlw r23, r23, r20 + rotlw r17, r17, r19 + + +FDP_1c08 + and r17, r17, r23 + andc r21, r21, r23 + or. r21, r21, r17 + b FDP_1b50 + + +FDP_1c18 + ble cr3, FDP_1338 + b major_0x03324 + bgt cr6, FDP_1C18 + bge cr4, FDP_1338 + b major_0x03324 + + + + align 5 + +FDP_1c40 ; OUTSIDE REFERER +; r6 = saved at *(ewa + 0x18) +; sprg1 = saved at *(ewa + 4) +; rN (0,7,8,9,10,11,12,13, not r1) = saved at *(*(ewa - 0x14) + 0x104 + 8*N) + bl LoadInterruptRegisters +; r0 = 0 +; r1 = *(ewa - 4) +; r6 = kdp +; r7 = *(ewa - 0x10) # flags? +; r8 = ewa +; r10 = srr0 +; r11 = srr1 +; r12 = sprg2 +; r13 = cr + + mfsprg r1, 0 + lwz r8, 0x0104(r6) + stw r8, 0x0000(r1) + stw r2, 0x0008(r1) + stw r3, 0x000c(r1) + stw r4, 0x0010(r1) + stw r5, 0x0014(r1) + stmw r14, 0x0038(r1) + mr r16, r7 + lwz r7, 0x013c(r6) + stw r7, 0x001c(r1) + lwz r8, 0x0144(r6) + stw r8, 0x0020(r1) + lwz r9, 0x014c(r6) + stw r9, 0x0024(r1) + lwz r23, 0x0154(r6) + stw r23, 0x0028(r1) + lwz r23, 0x015c(r6) + stw r23, 0x002c(r1) + lwz r23, 0x0164(r6) + stw r23, 0x0030(r1) + lwz r23, 0x016c(r6) + stw r23, 0x0034(r1) + lwz r1, -0x0004(r1) + addi r22, r6, 0xc4 + mfsprg r24, 3 + addi r23, r1, 0x4e0 + mfmsr r14 + oris r14, r14, 0x200 + ori r15, r14, 0x10 + mtsprg 3, r23 + mtmsr r15 + isync + lwz r27, 0x0000(r10) + mtmsr r14 + isync + mtsprg 3, r24 + lwz r24, 0x00d8(r6) + addi r24, r24, 0x00 + li r8, 0x00 + stvx v0, r24, r8 + li r9, 0x10 + stvx v1, r24, r9 + li r8, 0x20 + stvx v2, r24, r8 + li r9, 0x30 + stvx v3, r24, r9 + li r8, 0x40 + stvx v4, r24, r8 + li r9, 0x50 + stvx v5, r24, r9 + li r8, 0x60 + stvx v6, r24, r8 + li r9, 0x70 + stvx v7, r24, r9 + li r8, 0x80 + stvx v8, r24, r8 + li r9, 0x90 + stvx v9, r24, r9 + li r8, 160 + stvx v10, r24, r8 + li r9, 0xb0 + stvx v11, r24, r9 + li r8, 0xc0 + stvx v12, r24, r8 + li r9, 0xd0 + stvx v13, r24, r9 + li r8, 0xe0 + stvx v14, r24, r8 + li r9, 240 + stvx v15, r24, r9 + li r8, 0x100 + stvx v16, r24, r8 + li r9, 0x110 + stvx v17, r24, r9 + li r8, 0x120 + stvx v18, r24, r8 + li r9, 0x130 + stvx v19, r24, r9 + li r8, 320 + stvx v20, r24, r8 + li r9, 0x150 + stvx v21, r24, r9 + li r8, 0x160 + stvx v22, r24, r8 + li r9, 0x170 + stvx v23, r24, r9 + li r8, 0x180 + stvx v24, r24, r8 + li r9, 400 + stvx v25, r24, r9 + li r8, 0x1a0 + stvx v26, r24, r8 + li r9, 0x1b0 + stvx v27, r24, r9 + li r8, 0x1c0 + stvx v28, r24, r8 + li r9, 0x1d0 + stvx v29, r24, r9 + li r8, 480 + stvx v30, r24, r8 + li r9, 0x1f0 + stvx v31, r24, r9 + lwz r23, 0x0ed8(r1) + lwz r25, 0x0650(r1) + addi r23, r23, 0x01 + stw r23, 0x0ed8(r1) + rlwinm. r8, r27, 26, 0, 0 + rlwinm r9, r27, 24, 30, 31 + cmpwi cr1, r9, 0x03 + cmpwi cr2, r9, 0x00 + rlwinm r17, r27, 15, 23, 27 + rlwinm r18, r27, 20, 23, 27 + rlwinm r19, r27, 25, 23, 27 + blt FDP_1c40_0x398 + beq cr2, FDP_1c40_0x43c + bgt cr1, FDP_1c40_0x278 + lvx v3, r24, r19 + vspltisw v31, 0x00 + vspltisw v29, 0x01 + vcfux v29, v29, 0x00 + vspltisw v30, -0x01 + vspltisw v22, 0x09 + vsrw v28, v30, v22 + vslw v27, v30, v30 + vnor v26, v28, v27 + vsraw v24, v3, v30 + vand v23, v3, v28 + vcmpequw v23, v23, v31 + vand v22, v3, v26 + vcmpequw v22, v22, v31 + vandc v25, v22, v23 + lwz r9, 0x064c(r1) + llabel r8, blergh + add r9, r9, r8 + rlwinm r8, r27, 28, 26, 29 + add r9, r9, r8 + mtlr r9 + blr + +blergh + b panic + b panic + b panic + b panic + b major_0x07ac0_0x14c + b major_0x07ac0_0x100 + b major_0x07ac0_0x24c + b major_0x07ac0_0x220 + b FDP_1c40_0x4d0 + b FDP_1c40_0x4e0 + b FDP_1c40_0x4f0 + b FDP_1c40_0x500 + b panic + b panic + b FDP_1c40_0x514 + b major_0x07980_0x100 + +FDP_1c40_0x274 ; OUTSIDE REFERER + stvx v1, r24, r17 + +FDP_1c40_0x278 + li r8, 0x00 + lvx v0, r24, r8 + li r8, 0x10 + lvx v1, r24, r8 + li r8, 0x20 + lvx v2, r24, r8 + li r8, 0x30 + lvx v3, r24, r8 + li r8, 0x40 + lvx v4, r24, r8 + li r8, 0x50 + lvx v5, r24, r8 + li r8, 0x60 + lvx v6, r24, r8 + li r8, 0x70 + lvx v7, r24, r8 + li r8, 0x80 + lvx v8, r24, r8 + li r8, 0x90 + lvx v9, r24, r8 + li r8, 160 + lvx v10, r24, r8 + li r8, 0xb0 + lvx v11, r24, r8 + li r8, 0xc0 + lvx v12, r24, r8 + li r8, 0xd0 + lvx v13, r24, r8 + li r8, 0xe0 + lvx v14, r24, r8 + li r8, 240 + lvx v15, r24, r8 + li r8, 0x100 + lvx v16, r24, r8 + li r8, 0x110 + lvx v17, r24, r8 + li r8, 0x120 + lvx v18, r24, r8 + li r8, 0x130 + lvx v19, r24, r8 + li r8, 320 + lvx v20, r24, r8 + li r8, 0x150 + lvx v21, r24, r8 + li r8, 0x160 + lvx v22, r24, r8 + li r8, 0x170 + lvx v23, r24, r8 + li r8, 0x180 + lvx v24, r24, r8 + li r8, 400 + lvx v25, r24, r8 + li r8, 0x1a0 + lvx v26, r24, r8 + li r8, 0x1b0 + lvx v27, r24, r8 + li r8, 0x1c0 + lvx v28, r24, r8 + li r8, 0x1d0 + lvx v29, r24, r8 + li r8, 480 + lvx v30, r24, r8 + li r8, 0x1f0 + lvx v31, r24, r8 + andi. r23, r16, 0x20 + addi r10, r10, 0x04 + mfsprg r1, 0 + mtspr srr0, r10 + mtspr srr1, r11 + bne FDP_0E30 + mtlr r12 + b FDP_0DC8 + +FDP_1c40_0x398 + rlwinm r22, r27, 30, 23, 27 + mfmsr r14 + ori r15, r14, 0x2000 + mtmsr r15 + isync + rlwinm. r8, r11, 0, 18, 18 + beq FDP_1c40_0x3cc + stfd f0, 0x0200(r6) + mffs f0 + stfd f1, 0x0208(r6) + stfd f2, 0x0210(r6) + stfd f3, 0x0218(r6) + stfd f0, 0x00e0(r6) + +FDP_1c40_0x3cc + dc.l 0xff80010c + crmove 30, 2 + rlwinm. r9, r27, 31, 0, 0 + li r8, 0x03 + crmove 26, 0 + +FDP_1c40_0x3e0 + lfsx f0, r24, r18 + addic. r8, r8, -0x01 + lfsx f1, r24, r19 + lfsx f2, r24, r22 + bne cr6, FDP_1c40_0x408 + fnmsubs f3, f0, f2, f1 + stfsx f3, r24, r17 + addi r24, r24, 0x04 + bge FDP_1c40_0x3e0 + b FDP_1c40_0x418 + +FDP_1c40_0x408 + fmadds f3, f0, f2, f1 + stfsx f3, r24, r17 + addi r24, r24, 0x04 + bge FDP_1c40_0x3e0 + +FDP_1c40_0x418 + addi r24, r24, -0x10 + beq cr7, FDP_1c40_0x278 + lfd f0, 0x00e0(r6) + mtfsf 0xff, f0 + lfd f0, 0x0200(r6) + lfd f1, 0x0208(r6) + lfd f2, 0x0210(r6) + lfd f3, 0x0218(r6) + b FDP_1c40_0x278 + +FDP_1c40_0x43c + mfmsr r14 + ori r15, r14, 0x2000 + mtmsr r15 + isync + rlwinm. r8, r11, 0, 18, 18 + beq FDP_1c40_0x468 + stfd f0, 0x0200(r6) + mffs f0 + stfd f1, 0x0208(r6) + stfd f3, 0x0218(r6) + stfd f0, 0x00e0(r6) + +FDP_1c40_0x468 + dc.l 0xff80010c + crmove 30, 2 + rlwinm. r9, r27, 25, 0, 0 + li r8, 0x03 + crmove 26, 0 + +FDP_1c40_0x47c + lfsx f0, r24, r18 + addic. r8, r8, -0x01 + lfsx f1, r24, r19 + bne cr6, FDP_1c40_0x4a0 + fsubs f3, f0, f1 + stfsx f3, r24, r17 + addi r24, r24, 0x04 + bge FDP_1c40_0x47c + b FDP_1c40_0x4b0 + +FDP_1c40_0x4a0 + fadds f3, f0, f1 + stfsx f3, r24, r17 + addi r24, r24, 0x04 + bge FDP_1c40_0x47c + +FDP_1c40_0x4b0 + addi r24, r24, -0x10 + beq cr7, FDP_1c40_0x278 + lfd f0, 0x00e0(r6) + mtfsf 0xff, f0 + lfd f0, 0x0200(r6) + lfd f1, 0x0208(r6) + lfd f3, 0x0218(r6) + b FDP_1c40_0x278 + +FDP_1c40_0x4d0 + vsel v22, v31, v27, v24 + vsel v23, v3, v22, v25 + vrfin v1, v23 + b FDP_1c40_0x274 + +FDP_1c40_0x4e0 + vsel v22, v31, v27, v24 + vsel v23, v3, v22, v25 + vrfiz v1, v23 + b FDP_1c40_0x274 + +FDP_1c40_0x4f0 + vsel v22, v29, v27, v24 + vsel v23, v3, v22, v25 + vrfip v1, v23 + b FDP_1c40_0x274 + +FDP_1c40_0x500 + vor v29, v29, v27 + vsel v22, v31, v29, v24 + vsel v23, v3, v22, v25 + vrfim v1, v23 + b FDP_1c40_0x274 + +FDP_1c40_0x514 + vsel v23, v3, v31, v25 + lwz r9, 0x064c(r1) + llabel r8, FDP_2180 + add r8, r8, r9 + srwi r9, r18, 1 + add r8, r8, r9 + mtlr r8 + blr + + + + align 6 + +FDP_2180 + dc.l 0x1020BB8A + b FDP_1c40_0x274 + dc.l 0x1021BB8A + b FDP_1c40_0x274 + dc.l 0x1022BB8A + b FDP_1c40_0x274 + dc.l 0x1023BB8A + b FDP_1c40_0x274 + dc.l 0x1024BB8A + b FDP_1c40_0x274 + dc.l 0x1025BB8A + b FDP_1c40_0x274 + dc.l 0x1026BB8A + b FDP_1c40_0x274 + dc.l 0x1027BB8A + b FDP_1c40_0x274 + dc.l 0x1028BB8A + b FDP_1c40_0x274 + dc.l 0x1029BB8A + b FDP_1c40_0x274 + dc.l 0x102ABB8A + b FDP_1c40_0x274 + dc.l 0x102BBB8A + b FDP_1c40_0x274 + dc.l 0x102CBB8A + b FDP_1c40_0x274 + dc.l 0x102DBB8A + b FDP_1c40_0x274 + dc.l 0x102EBB8A + b FDP_1c40_0x274 + dc.l 0x102FBB8A + b FDP_1c40_0x274 + dc.l 0x1030BB8A + b FDP_1c40_0x274 + dc.l 0x1031BB8A + b FDP_1c40_0x274 + dc.l 0x1032BB8A + b FDP_1c40_0x274 + dc.l 0x1033BB8A + b FDP_1c40_0x274 + dc.l 0x1034BB8A + b FDP_1c40_0x274 + dc.l 0x1035BB8A + b FDP_1c40_0x274 + dc.l 0x1036BB8A + b FDP_1c40_0x274 + dc.l 0x1037BB8A + b FDP_1c40_0x274 + dc.l 0x1038BB8A + b FDP_1c40_0x274 + dc.l 0x1039BB8A + b FDP_1c40_0x274 + dc.l 0x103ABB8A + b FDP_1c40_0x274 + dc.l 0x103BBB8A + b FDP_1c40_0x274 + dc.l 0x103CBB8A + b FDP_1c40_0x274 + dc.l 0x103DBB8A + b FDP_1c40_0x274 + dc.l 0x103EBB8A + b FDP_1c40_0x274 + dc.l 0x103FBB8A + b FDP_1c40_0x274 + +major_0x07980_0x100 ; OUTSIDE REFERER + vsel v23, v3, v31, v25 + lwz r9, 0x064c(r1) + llabel r8, FDP_22c0 + add r8, r8, r9 + srwi r9, r18, 1 + add r8, r8, r9 + mtlr r8 + blr + + + + align 6 + +FDP_22c0 + dc.l 0x1020BBCA + b FDP_1c40_0x274 + dc.l 0x1021BBCA + b FDP_1c40_0x274 + dc.l 0x1022BBCA + b FDP_1c40_0x274 + dc.l 0x1023BBCA + b FDP_1c40_0x274 + dc.l 0x1024BBCA + b FDP_1c40_0x274 + dc.l 0x1025BBCA + b FDP_1c40_0x274 + dc.l 0x1026BBCA + b FDP_1c40_0x274 + dc.l 0x1027BBCA + b FDP_1c40_0x274 + dc.l 0x1028BBCA + b FDP_1c40_0x274 + dc.l 0x1029BBCA + b FDP_1c40_0x274 + dc.l 0x102ABBCA + b FDP_1c40_0x274 + dc.l 0x102BBBCA + b FDP_1c40_0x274 + dc.l 0x102CBBCA + b FDP_1c40_0x274 + dc.l 0x102DBBCA + b FDP_1c40_0x274 + dc.l 0x102EBBCA + b FDP_1c40_0x274 + dc.l 0x102FBBCA + b FDP_1c40_0x274 + dc.l 0x1030BBCA + b FDP_1c40_0x274 + dc.l 0x1031BBCA + b FDP_1c40_0x274 + dc.l 0x1032BBCA + b FDP_1c40_0x274 + dc.l 0x1033BBCA + b FDP_1c40_0x274 + dc.l 0x1034BBCA + b FDP_1c40_0x274 + dc.l 0x1035BBCA + b FDP_1c40_0x274 + dc.l 0x1036BBCA + b FDP_1c40_0x274 + dc.l 0x1037BBCA + b FDP_1c40_0x274 + dc.l 0x1038BBCA + b FDP_1c40_0x274 + dc.l 0x1039BBCA + b FDP_1c40_0x274 + dc.l 0x103ABBCA + b FDP_1c40_0x274 + dc.l 0x103BBBCA + b FDP_1c40_0x274 + dc.l 0x103CBBCA + b FDP_1c40_0x274 + dc.l 0x103DBBCA + b FDP_1c40_0x274 + dc.l 0x103EBBCA + b FDP_1c40_0x274 + dc.l 0x103FBBCA + b FDP_1c40_0x274 + +major_0x07ac0_0x100 ; OUTSIDE REFERER + bl major_0x07d80_0x20 + vspltisw v19, 0x01 + vadduwm v22, v22, v19 + vspltisw v23, -0x07 + vsrw v21, v23, v23 + vsubuwm v23, v21, v22 + vspltisw v21, -0x09 + vslw v23, v23, v21 + vrsqrtefp v19, v23 + vslw v20, v3, v22 + vor v23, v29, v27 + vsel v23, v31, v23, v24 + vsel v21, v3, v23, v25 + vandc v25, v25, v24 + vrsqrtefp v20, v20 + vrsqrtefp v21, v21 + vmaddfp v1, v20, v19, v27 + vsel v1, v21, v1, v25 + b FDP_1c40_0x274 + +major_0x07ac0_0x14c ; OUTSIDE REFERER + bl major_0x07d80_0x20 + vspltisw v19, 0x01 + vadduwm v22, v22, v19 + vslw v20, v3, v22 + vsel v20, v31, v20, v25 + vrefp v20, v20 + vspltisw v21, -0x09 + vandc v23, v20, v27 + vsrw v23, v23, v21 + mfvscr v29 + vsrw v19, v30, v19 + vsrw v19, v19, v21 + vaddubs v23, v22, v23 + mtvscr v29 + vcmpequw v22, v23, v19 + vslw v23, v23, v21 + vsel v23, v20, v23, v26 + vand v22, v22, v28 + vsel v23, v23, v31, v22 + vsel v20, v31, v27, v24 + vsel v1, v23, v30, v20 + vspltisw v19, 0x01 + vslw v22, v3, v19 + vspltisw v23, -0x04 + vsraw v22, v22, v21 + vsraw v22, v22, v19 + vcmpgtuw v23, v22, v23 + vcmpequw v19, v22, v30 + vandc v23, v23, v19 + vspltisw v19, 0x02 + vsubuwm v22, v22, v19 + vslw v22, v22, v21 + vsel v22, v3, v22, v26 + vsel v22, v31, v22, v23 + vrefp v22, v22 + vspltisw v19, 0x01 + vandc v22, v22, v27 + vslw v29, v19, v21 + vor v28, v28, v29 + vcmpgtuw v28, v22, v28 + vsrw v29, v29, v19 + vsel v22, v22, v31, v26 + vsrw v22, v22, v19 + vor v22, v22, v29 + vsel v19, v19, v31, v28 + vsrw v22, v22, v19 + vor v22, v22, v20 + vsel v1, v1, v22, v23 + vor v25, v25, v23 + vsel v23, v3, v31, v25 + vrefp v23, v23 + vsel v1, v23, v1, v25 + b FDP_1c40_0x274 + +major_0x07ac0_0x220 ; OUTSIDE REFERER + bl major_0x07d80_0x20 + vspltisw v19, 0x01 + vadduwm v22, v22, v19 + vslw v20, v3, v22 + vsel v23, v3, v20, v25 + vlogefp v23, v23 + vsubsws v22, v31, v22 + vcfsx v22, v22, 0x00 + vaddfp v1, v22, v23 + vsel v1, v23, v1, v25 + b FDP_1c40_0x274 + +major_0x07ac0_0x24c ; OUTSIDE REFERER + lwz r9, 0x064c(r1) + llabel r8, FDP_2590 + add r8, r8, r9 + lvx v23, 0, r8 + vspltw v21, v23, 0x03 + vspltw v20, v23, 0x00 + vcmpgefp v21, v3, v21 + vcmpgtfp v20, v3, v20 + vspltw v19, v23, 0x02 + vandc v22, v21, v20 + vsel v29, v31, v3, v22 + vaddfp v29, v29, v19 + vsel v19, v3, v29, v22 + vexptefp v1, v19 + vspltisw v25, -0x09 + vspltw v23, v23, 0x01 + vsrw v19, v1, v25 + vspltisw v29, 0x01 + vsubuwm v19, v23, v19 + vslw v26, v29, v25 + vsel v28, v31, v1, v28 + vor v28, v28, v26 + vsrw v28, v28, v19 + vsel v1, v1, v28, v22 + b FDP_1c40_0x274 + + + + align 5 + +FDP_2580 + dc.l 0x17030202 + dc.l 0x01010101 + dc.l 0x00000000 + dc.l 0x00000000 + +FDP_2590 + dc.l 0xc2fc0004 + dc.l 0x00000041 + dc.l 0x42800000 + dc.l 0xc3150001 + +major_0x07d80_0x20 ; OUTSIDE REFERER + vspltisw v23, 9 + vslw v19, v3, v23 + lwz r9, 0x064c(r1) + llabel r8, FDP_2580 + add r8, r8, r9 + lvx v23, 0, r8 + vperm v22, v23, v23, v19 + vspltisw v21, 4 + vsrw v21, v19, v21 + vperm v21, v23, v23, v21 + li r8, 0 + lvsl v20, r8, r8 + vspltisw v23, 3 + vslw v20, v20, v23 + vspltisb v23, 4 + vaddubm v19, v20, v23 + vspltw v20, v20, 0 + vspltw v19, v19, 0 + vaddubm v21, v21, v20 + vaddubm v22, v22, v19 + vminub v22, v22, v21 + vsldoi v21, v22, v22, 2 + vminub v22, v22, v21 + vsldoi v21, v22, v22,1 + vminub v22, v22, v21 + vspltisw v21, -8 + vsrw v22, v22, v21 + blr + + +Very long vector table (HalfWordTable -> Small bits of glue near int loads/stores -> here) \ No newline at end of file diff --git a/vector stuff.s b/vector stuff.s new file mode 100644 index 0000000..abedf42 --- /dev/null +++ b/vector stuff.s @@ -0,0 +1,256 @@ +lvx v0, 0, r23 +lvx v1, 0, r23 +lvx v2, 0, r23 +lvx v3, 0, r23 +lvx v4, 0, r23 +lvx v5, 0, r23 +lvx v6, 0, r23 +lvx v7, 0, r23 +lvx v8, 0, r23 +lvx v9, 0, r23 +lvx v10, 0, r23 +lvx v11, 0, r23 +lvx v12, 0, r23 +lvx v13, 0, r23 +lvx v14, 0, r23 +lvx v15, 0, r23 +lvx v16, 0, r23 +lvx v17, 0, r23 +lvx v18, 0, r23 +lvx v19, 0, r23 +lvx v20, 0, r23 +lvx v21, 0, r23 +lvx v22, 0, r23 +lvx v23, 0, r23 +lvx v24, 0, r23 +lvx v25, 0, r23 +lvx v26, 0, r23 +lvx v27, 0, r23 +lvx v28, 0, r23 +lvx v29, 0, r23 +lvx v30, 0, r23 +lvx v31, 0, r23 +lvebx v0, 0, r23 +lvebx v1, 0, r23 +lvebx v2, 0, r23 +lvebx v3, 0, r23 +lvebx v4, 0, r23 +lvebx v5, 0, r23 +lvebx v6, 0, r23 +lvebx v7, 0, r23 +lvebx v8, 0, r23 +lvebx v9, 0, r23 +lvebx v10, 0, r23 +lvebx v11, 0, r23 +lvebx v12, 0, r23 +lvebx v13, 0, r23 +lvebx v14, 0, r23 +lvebx v15, 0, r23 +lvebx v16, 0, r23 +lvebx v17, 0, r23 +lvebx v18, 0, r23 +lvebx v19, 0, r23 +lvebx v20, 0, r23 +lvebx v21, 0, r23 +lvebx v22, 0, r23 +lvebx v23, 0, r23 +lvebx v24, 0, r23 +lvebx v25, 0, r23 +lvebx v26, 0, r23 +lvebx v27, 0, r23 +lvebx v28, 0, r23 +lvebx v29, 0, r23 +lvebx v30, 0, r23 +lvebx v31, 0, r23 +lvehx v0, 0, r23 +lvehx v1, 0, r23 +lvehx v2, 0, r23 +lvehx v3, 0, r23 +lvehx v4, 0, r23 +lvehx v5, 0, r23 +lvehx v6, 0, r23 +lvehx v7, 0, r23 +lvehx v8, 0, r23 +lvehx v9, 0, r23 +lvehx v10, 0, r23 +lvehx v11, 0, r23 +lvehx v12, 0, r23 +lvehx v13, 0, r23 +lvehx v14, 0, r23 +lvehx v15, 0, r23 +lvehx v16, 0, r23 +lvehx v17, 0, r23 +lvehx v18, 0, r23 +lvehx v19, 0, r23 +lvehx v20, 0, r23 +lvehx v21, 0, r23 +lvehx v22, 0, r23 +lvehx v23, 0, r23 +lvehx v24, 0, r23 +lvehx v25, 0, r23 +lvehx v26, 0, r23 +lvehx v27, 0, r23 +lvehx v28, 0, r23 +lvehx v29, 0, r23 +lvehx v30, 0, r23 +lvehx v31, 0, r23 +lvewx v0, 0, r23 +lvewx v1, 0, r23 +lvewx v2, 0, r23 +lvewx v3, 0, r23 +lvewx v4, 0, r23 +lvewx v5, 0, r23 +lvewx v6, 0, r23 +lvewx v7, 0, r23 +lvewx v8, 0, r23 +lvewx v9, 0, r23 +lvewx v10, 0, r23 +lvewx v11, 0, r23 +lvewx v12, 0, r23 +lvewx v13, 0, r23 +lvewx v14, 0, r23 +lvewx v15, 0, r23 +lvewx v16, 0, r23 +lvewx v17, 0, r23 +lvewx v18, 0, r23 +lvewx v19, 0, r23 +lvewx v20, 0, r23 +lvewx v21, 0, r23 +lvewx v22, 0, r23 +lvewx v23, 0, r23 +lvewx v24, 0, r23 +lvewx v25, 0, r23 +lvewx v26, 0, r23 +lvewx v27, 0, r23 +lvewx v28, 0, r23 +lvewx v29, 0, r23 +lvewx v30, 0, r23 +lvewx v31, 0, r23 +stvx v0, 0, r23 +stvx v1, 0, r23 +stvx v2, 0, r23 +stvx v3, 0, r23 +stvx v4, 0, r23 +stvx v5, 0, r23 +stvx v6, 0, r23 +stvx v7, 0, r23 +stvx v8, 0, r23 +stvx v9, 0, r23 +stvx v10, 0, r23 +stvx v11, 0, r23 +stvx v12, 0, r23 +stvx v13, 0, r23 +stvx v14, 0, r23 +stvx v15, 0, r23 +stvx v16, 0, r23 +stvx v17, 0, r23 +stvx v18, 0, r23 +stvx v19, 0, r23 +stvx v20, 0, r23 +stvx v21, 0, r23 +stvx v22, 0, r23 +stvx v23, 0, r23 +stvx v24, 0, r23 +stvx v25, 0, r23 +stvx v26, 0, r23 +stvx v27, 0, r23 +stvx v28, 0, r23 +stvx v29, 0, r23 +stvx v30, 0, r23 +stvx v31, 0, r23 +stvebx v0, 0, r23 +stvebx v1, 0, r23 +stvebx v2, 0, r23 +stvebx v3, 0, r23 +stvebx v4, 0, r23 +stvebx v5, 0, r23 +stvebx v6, 0, r23 +stvebx v7, 0, r23 +stvebx v8, 0, r23 +stvebx v9, 0, r23 +stvebx v10, 0, r23 +stvebx v11, 0, r23 +stvebx v12, 0, r23 +stvebx v13, 0, r23 +stvebx v14, 0, r23 +stvebx v15, 0, r23 +stvebx v16, 0, r23 +stvebx v17, 0, r23 +stvebx v18, 0, r23 +stvebx v19, 0, r23 +stvebx v20, 0, r23 +stvebx v21, 0, r23 +stvebx v22, 0, r23 +stvebx v23, 0, r23 +stvebx v24, 0, r23 +stvebx v25, 0, r23 +stvebx v26, 0, r23 +stvebx v27, 0, r23 +stvebx v28, 0, r23 +stvebx v29, 0, r23 +stvebx v30, 0, r23 +stvebx v31, 0, r23 +stvehx v0, 0, r23 +stvehx v1, 0, r23 +stvehx v2, 0, r23 +stvehx v3, 0, r23 +stvehx v4, 0, r23 +stvehx v5, 0, r23 +stvehx v6, 0, r23 +stvehx v7, 0, r23 +stvehx v8, 0, r23 +stvehx v9, 0, r23 +stvehx v10, 0, r23 +stvehx v11, 0, r23 +stvehx v12, 0, r23 +stvehx v13, 0, r23 +stvehx v14, 0, r23 +stvehx v15, 0, r23 +stvehx v16, 0, r23 +stvehx v17, 0, r23 +stvehx v18, 0, r23 +stvehx v19, 0, r23 +stvehx v20, 0, r23 +stvehx v21, 0, r23 +stvehx v22, 0, r23 +stvehx v23, 0, r23 +stvehx v24, 0, r23 +stvehx v25, 0, r23 +stvehx v26, 0, r23 +stvehx v27, 0, r23 +stvehx v28, 0, r23 +stvehx v29, 0, r23 +stvehx v30, 0, r23 +stvehx v31, 0, r23 +stvewx v0, 0, r23 +stvewx v1, 0, r23 +stvewx v2, 0, r23 +stvewx v3, 0, r23 +stvewx v4, 0, r23 +stvewx v5, 0, r23 +stvewx v6, 0, r23 +stvewx v7, 0, r23 +stvewx v8, 0, r23 +stvewx v9, 0, r23 +stvewx v10, 0, r23 +stvewx v11, 0, r23 +stvewx v12, 0, r23 +stvewx v13, 0, r23 +stvewx v14, 0, r23 +stvewx v15, 0, r23 +stvewx v16, 0, r23 +stvewx v17, 0, r23 +stvewx v18, 0, r23 +stvewx v19, 0, r23 +stvewx v20, 0, r23 +stvewx v21, 0, r23 +stvewx v22, 0, r23 +stvewx v23, 0, r23 +stvewx v24, 0, r23 +stvewx v25, 0, r23 +stvewx v26, 0, r23 +stvewx v27, 0, r23 +stvewx v28, 0, r23 +stvewx v29, 0, r23 +stvewx v30, 0, r23 +stvewx v31, 0, r23