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https://github.com/elliotnunn/powermac-rom.git
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intelligent structures
This commit is contained in:
Elliot Nunn
parent
87797ccff0
commit
4d3f6fe0b2
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@ -171,46 +171,8 @@ Bank16Start ds.l 1 ; 0b0, irp+e70 ; Starting address of RAM bank 16
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Bank16Size ds.l 1 ; 0b4, irp+e74 ; Number of bytes in RAM bank 16
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Bank17Start ds.l 1 ; 0b8, irp+e78 ; Starting address of RAM bank 17
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Bank17Size ds.l 1 ; 0bc, irp+e7c ; Number of bytes in RAM bank 17
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Bank18Start ds.l 1 ; 0c0, irp+e80 ; Starting address of RAM bank 18
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Bank18Size ds.l 1 ; 0c4, irp+e84 ; Number of bytes in RAM bank 18
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Bank19Start ds.l 1 ; 0c8, irp+e88 ; Starting address of RAM bank 19
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Bank19Size ds.l 1 ; 0cc, irp+e8c ; Number of bytes in RAM bank 19
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Bank20Start ds.l 1 ; 0d0, irp+e90 ; Starting address of RAM bank 20
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Bank20Size ds.l 1 ; 0d4, irp+e94 ; Number of bytes in RAM bank 20
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Bank21Start ds.l 1 ; 0d8, irp+e98 ; Starting address of RAM bank 21
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Bank21Size ds.l 1 ; 0dc, irp+e9c ; Number of bytes in RAM bank 21
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Bank22Start ds.l 1 ; 0e0, irp+ea0 ; Starting address of RAM bank 22
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Bank22Size ds.l 1 ; 0e4, irp+ea4 ; Number of bytes in RAM bank 22
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Bank23Start ds.l 1 ; 0e8, irp+ea8 ; Starting address of RAM bank 23
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Bank23Size ds.l 1 ; 0ec, irp+eac ; Number of bytes in RAM bank 23
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Bank24Start ds.l 1 ; 0f0, irp+eb0 ; Starting address of RAM bank 24
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Bank24Size ds.l 1 ; 0f4, irp+eb4 ; Number of bytes in RAM bank 24
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Bank25Start ds.l 1 ; 0f8, irp+eb8 ; Starting address of RAM bank 25
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Bank25Size ds.l 1 ; 0fc, irp+ebc ; Number of bytes in RAM bank 25
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EndOfBanks
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MaxBanks equ 16 ; Pads out to old struct len (cache block), more to come...
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; Interrupt Support Data
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IntCntrBaseAddr ds.l 1 ; 100, irp+ec0 ; Interrupt Controller Base Address (variable is used since this is a PCI Dev and address is relocatable)
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IntPendingReg ds.l 2 ; 104, irp+ec4 ; Data of current interrupts pending register
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; These fields were added to report information about tightly-coupled L2 caches.
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; The inline L2 information should be used in situations where there is a CPU
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; card L2 cache that can coexist with a motherboard L2.
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InlineL2DSize ds.l 1 ; 10c, irp+ecc ; Size of in-line L2 Dcache
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InlineL2ISize ds.l 1 ; 110, irp+ed0 ; Size of in-line L2 Icache
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InlineL2Combined ds.w 1 ; 114, irp+ed4 ; 1 <- combined or no cache, 0 <- split cache
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InlineL2IBlockSize ds.w 1 ; 116, irp+ed6 ; Block size of in-line I L2 cache
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InlineL2DBlockSize ds.w 1 ; 118, irp+ed8 ; Block size of in-line D L2 cache
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InlineL2IAssoc ds.w 1 ; 11a, irp+eda ; Associativity of L2 I
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InlineL2DAssoc ds.w 1 ; 11c, irp+edc ; Associativity of L2 D
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ds.w 1 ; 11e, irp+ede ; pad
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; More Interrupt Support Data
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IntsCompleted ds.l 2 ; 120, irp+ee0 ; completed interrupts
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align 5 ; pad to nice cache block alignment
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endr
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@ -301,37 +263,6 @@ ExceptionPropagateCount ds.l 1 ; 0e8, kdp+ea8 ; count of Exceptions propagated
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ExceptionForcedCount ds.l 1 ; 0ec, kdp+eac ; count of Exceptions forced to system
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SysContextCpuTime ds.l 2 ; 0f0, kdp+eb0 ; CPU Time used by System Context
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AltContextCpuTime ds.l 2 ; 0f8, kdp+eb4 ; CPU Time used by Alternate Context
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; This stuff is new (starts at 0x100)
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blueProcessID ds.l 1 ; 100, kdp+ec0 ; ID of the blue process.
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blueTaskID ds.l 1 ; 104, kdp+ec4 ; ID of the blue task.
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pageQueueID ds.l 1 ; 108, kdp+ec8 ; ID of the page fault queue.
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TaskCount ds.l 1 ; 10c, kdp+ecc ; Number of tasks.
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FreePoolExtendCount ds.l 1 ; 110, kdp+ed0 ; Number of pages given to the nanokernel.
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;rsrv1 ds.l 3 ; 114, kdp+ed4 ; reserved???
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; My additions
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org 0x11c
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ConfigFlags ds.l 1 ; 11c, kdp+edc ; includes ScreenConsole ... TODO put flag equs here
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NanodbgrFlagShift equ 1
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NanodbgrFlagBit equ 31 - NanodbgrFlagShift
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LogFlagShift equ 3
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LogFlagBit equ 31 - LogFlagShift
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; bit 31 always set on replacement, bit 27 set on replacement with ROM 2.7f3 or later
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AlertCount ds.l 1 ; 120, kdp+ee0 ; interprocessor alerts
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SchEvalCount ds.l 1 ; 124, kdp+ee4
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VMDispatchCountTblPtr ds.l 1 ; 128, kdp+ee8
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ds.l 1
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ds.l 1
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MPDispatchCountTblPtr ds.l 1 ; 134, kdp+ef4 ; ???????
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AddrSpcSetCtr ds.l 1 ; 138, kdp+ef8 ; incremented by SchSwitchSpace
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IDCtr ds.l 1 ; 13c, kdp+efc
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org 0x160
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endr
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@ -372,35 +303,7 @@ DataCacheAssociativity ds.w 1 ; 02e, kdp+f4e ; Associativity of the Data Cache
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TransCacheTotalSize ds.w 1 ; 030, kdp+f50 ; number of entries in the Translation Cache
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TransCacheAssociativity ds.w 1 ; 032, kdp+f52 ; Associativity of the Translation Cache
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OvrEnd
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; These fields were added to report information about back-side L2 caches
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ProcessorL2DSize ds.l 1 ; 034, kdp+f54 ; Size of back-side L2 Dcache
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ProcessorL2ISize ds.l 1 ; 038, kdp+f58 ; Size of back-side L2 Icache
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ProcessorL2Combined ds.w 1 ; 03c, kdp+f5c ; 1 <- combined or no cache, 0 <- split cache
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ProcessorL2IBlockSize ds.w 1 ; 03e, kdp+f5e ; Block size of back-side I L2 cache
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ProcessorL2DBlockSize ds.w 1 ; 040, kdp+f60 ; Block size of back-side D L2 cache
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ProcessorL2IAssoc ds.w 1 ; 042, kdp+f62 ; Associativity of L2 I
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ProcessorL2DAssoc ds.w 1 ; 044, kdp+f64 ; Associativity of L2 D
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filler1 ds.w 1 ; 046, kdp+f66 ; align to long
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; ProcessorFlags - Definitions for the processor flags field. These are bit positions,
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; as in 1 << hasVMX, and not masks.
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hasL2CR equ 0
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hasPLRUL1 equ 1
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hasTAU equ 2
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hasVMX equ 3
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hasMSSregs equ 4
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hasExtraBATs equ 5
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ProcessorFlags ds.l 1 ; 048, kdp+f68 ; flags to specify processor features
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align 5 ; pad to nice cache block alignment
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org 0x05e
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SetToZero ds.w 1 ; 05e, kdp+f7e ; by same code that sets below
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ClockRates ds.b 16*4 ; 060:0a0, kdp:f80:fc0 ; 16b blks of cpu/bus/dec/?? speeds (Hz)
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org 0x40
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endr
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@ -704,10 +704,10 @@ ZeroWord ds.l 1 ; 910 ; Only NewWorld and Unknown PIHes touch this
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ds.l 1 ; 918
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ds.l 1 ; 91c
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ds.b 0x3a0 ; 920:cc0
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SystemInfo ds.b 192 ; cc0:d80
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DiagnosticInfo ds.b 256 ; d80:e80
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NanoKernelInfo ds.b 256 ; e80:f80 ; see NKNanoKernelInfo in PPCInfoRecordsPriv
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ProcessorInfo ds.b 64 ; f80:fc0
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SysInfo ds NKSystemInfo ; cc0:d80
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DiagInfo ds NKDiagInfo ; d80:e80
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NKInfo ds NKNanoKernelInfo; e80:f80 ; see NKNanoKernelInfo in PPCInfoRecordsPriv
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ProcInfo ds NKProcessorInfo ; f80:fc0
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InfoRecord ds.b 64 ; fc0:1000 ; was main copy in NKv1, now vestigial?
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endr
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@ -288,7 +288,7 @@ CreateAreasFromPageMap
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add r15, r15, r26 ; add a page, I think
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slwi r16, r16, 12
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lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.blueProcessID(r1)
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lwz r8, KDP.NKInfo.blueProcessID(r1)
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stw r8, Area.ProcessID(r31)
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lwz r8, EWA.PA_CurAddressSpace(r1)
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@ -526,7 +526,7 @@ MPGetPageSize
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cmpwi r3, 1
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bne ReturnParamErrFromMPCall
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lwz r3, KDP.ProcessorInfo + NKProcessorInfo.PageSize(r1)
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lwz r3, KDP.ProcInfo.PageSize(r1)
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b CommonMPCallReturnPath
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@ -4646,7 +4646,7 @@ DeletePTE ; PTE *r18, PLE *r30
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_InvalNCBPointerCache scratch=r16
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foo set KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount
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foo set KDP.NKInfo.HashTableDeleteCount
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lwz r16, foo(r1)
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_bclr r14, r14, Area.kPLEFlagIsInHTAB
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addi r16, r16, 1
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@ -422,13 +422,13 @@ InitBuiltin
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; If CI.Debug >= 257 && CI.DebugFlags & 2 ...
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cmplwi r8, NKConfigurationInfo.DebugThreshold
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lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
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lwz r8, KDP.NKInfo.ConfigFlags(r1)
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if &TYPE('NKShowLog') = 'UNDEFINED'
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blt @no_screen_log
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lwz r8, NKConfigurationInfo.DebugFlags(r9)
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rlwinm. r8, r8, 0, NKConfigurationInfo.LogFlagBit, NKConfigurationInfo.LogFlagBit
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lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
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lwz r8, KDP.NKInfo.ConfigFlags(r1)
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beq @no_screen_log
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endif
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@ -439,7 +439,7 @@ InitBuiltin
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; Switch on two other flags
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ori r8, r8, 1<< 0 ; not sure
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ori r8, r8, 1<< 4 ; to do with interrupts
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stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
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stw r8, KDP.NKInfo.ConfigFlags(r1)
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@ -800,10 +800,10 @@ InitBuiltin
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; ProcessorInfoTable.s
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mfpvr r12
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stw r12, KDP.ProcessorInfo + NKProcessorInfo.ProcessorVersionReg(r1)
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stw r12, KDP.ProcInfo.ProcessorVersionReg(r1)
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srwi r12, r12, 16
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lwz r11, KDP.PA_NanoKernelCode(r1)
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addi r10, r1, KDP.ProcessorInfo + NKProcessorInfo.Ovr
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addi r10, r1, KDP.ProcInfo.Ovr
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li r9, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
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; check for several (some unknown) pre-7410 CPUs, and load their info
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@ -63,7 +63,7 @@ kcCacheDispatch
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cmplwi r8, 2
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bgt @fail_bad_selector
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
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lwz r8, KDP.ProcInfo.ProcessorFlags(r1)
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andi. r8, r8, 1 << NKProcessorInfo.hasL2CR
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beq CacheCallFailNoL2 ; no L2CR => fail (what about 601?)
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@ -186,7 +186,7 @@ CacheCallL2EnableSelected
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andis. r21, r21, 0x8000
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bne CacheCallReturn
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1)
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lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
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and. r8, r8, r8
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beq CacheCallFailNoL2 ; fail if zero-sized cache reported
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@ -323,7 +323,7 @@ CacheCallGetInfoForReturnValue
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blr
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@level2
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1)
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lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
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and. r8, r8, r8
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beq CacheCallFailNoL2
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@ -375,17 +375,17 @@ FlushCaches
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; Flush level 1
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lhz r25, KDP.ProcessorInfo + NKProcessorInfo.DataCacheLineSize(r1)
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lhz r25, KDP.ProcInfo.DataCacheLineSize(r1)
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and. r25, r25, r25 ; r25 = L1-D line size
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cntlzw r8, r25
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beq @return
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subfic r9, r8, 31 ; r9 = logb(L1-D line size)
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DataCacheTotalSize(r1)
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lwz r8, KDP.ProcInfo.DataCacheTotalSize(r1)
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and. r8, r8, r8 ; r8 = L1-D size
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beq @return
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lwz r24, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
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lwz r24, KDP.ProcInfo.ProcessorFlags(r1)
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mtcr r24
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bc BO_IF, 31 - NKProcessorInfo.hasMSSregs, @use_SPRs_to_invalidate
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@ -411,7 +411,7 @@ FlushCaches
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; Flush level 2 (very similar to above)
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lwz r24, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
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lwz r24, KDP.ProcInfo.ProcessorFlags(r1)
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andi. r24, r24, 1 << NKProcessorInfo.hasL2CR
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beq @return ; return if L2CR unavailable
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@ -419,13 +419,13 @@ FlushCaches
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andis. r24, r24, 0x8000
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beq @return ; return if L2 off (per L2CR[L2E])
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lhz r25, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DBlockSize(r1)
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lhz r25, KDP.ProcInfo.ProcessorL2DBlockSize(r1)
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and. r25, r25, r25 ; r25 = L2-D line size
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cntlzw r8, r25
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beq @return
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subfic r9, r8, 31 ; r9 = logb(L2-D line size)
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1)
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lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
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and. r8, r8, r8 ; r8 = L2-D size
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beq @return
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@ -515,7 +515,7 @@ FlushL1CacheUsingMSSCR0
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; Return if MSSCR0 unavailable
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
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lwz r8, KDP.ProcInfo.ProcessorFlags(r1)
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mtcr r8
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bclr BO_IF_NOT, 31-NKProcessorInfo.hasMSSregs
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@ -23,9 +23,9 @@ ExceptionAfterRetry
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slwi r8, r8, 2 ; increment counter
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add r8, r8, r1
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lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionCauseCounts(r8)
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lwz r9, KDP.NKInfo.ExceptionCauseCounts(r8)
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addi r9, r9, 1
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stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionCauseCounts(r8)
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stw r9, KDP.NKInfo.ExceptionCauseCounts(r8)
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; Move regs from KDP to ContextBlock
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lwz r8, EWA.r7(r1)
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@ -100,10 +100,10 @@ PreferRegistersFromKDPSavingContextBlock
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_alignToCacheBlock
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KCallReturnFromExceptionFastPath
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lwz r11, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r1)
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lwz r11, KDP.NKInfo.NanoKernelCallCounts(r1)
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mr r10, r12
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addi r11, r11, 1
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stw r11, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r1)
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stw r11, KDP.NKInfo.NanoKernelCallCounts(r1)
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mfsrr1 r11
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rlwimi r7, r7, 27, 26, 26 ; ?re-enable single stepping
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@ -115,10 +115,10 @@ KCallReturnFromException
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;force to system context ; Handler returned >= 1
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subi r8, r3, 32
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lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionForcedCount(r1)
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lwz r9, KDP.NKInfo.ExceptionForcedCount(r1)
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cmplwi r8, 256-32
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addi r9, r9, 1
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stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionForcedCount(r1)
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stw r9, KDP.NKInfo.ExceptionForcedCount(r1)
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insrwi r7, r3, 8, 0
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blt RunSystemContext ; Handler returned 1-255: force that exception number to System
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li r8, ecTrapInstr
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@ -145,10 +145,10 @@ KCallReturnFromException
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b IntReturn
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@propagate ; Handler returned 1: propagate exception
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lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionPropagateCount(r1)
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lwz r9, KDP.NKInfo.ExceptionPropagateCount(r1)
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lwz r8, CB.ExceptionOriginFlags(r6)
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addi r9, r9, 1
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stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionPropagateCount(r1)
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stw r9, KDP.NKInfo.ExceptionPropagateCount(r1)
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lwz r10, CB.ExceptionOriginAddr(r6)
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rlwimi r7, r8, 0, 0xFF00FFFF ; restore most Flags to pre-exception state
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lwz r8, CB.ExceptionOriginEnables(r6)
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@ -226,9 +226,9 @@ Exception
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slwi r8, r8, 2 ; Increment counter, easy enough
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add r8, r8, r1
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lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionCauseCounts(r8)
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lwz r9, KDP.NKInfo.ExceptionCauseCounts(r8)
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addi r9, r9, 1
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stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.ExceptionCauseCounts(r8)
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stw r9, KDP.NKInfo.ExceptionCauseCounts(r8)
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blt RunExceptionHandler ; exception enabled => run userspace handler
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;fall through ; Alt Context has left exception disabled => Sys Context
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@ -8,10 +8,10 @@ IntFPUnavail
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mfsprg r1, 0
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stw r11, KDP.FloatingPtTemp1(r1)
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lwz r11, KDP.NanoKernelInfo + NKNanoKernelInfo.FPUReloadCount(r1)
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lwz r11, KDP.NKInfo.FPUReloadCount(r1)
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stw r6, KDP.FloatingPtTemp2(r1)
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addi r11, r11, 1
|
||||
stw r11, KDP.NanoKernelInfo + NKNanoKernelInfo.FPUReloadCount(r1)
|
||||
stw r11, KDP.NKInfo.FPUReloadCount(r1)
|
||||
|
||||
mfsrr1 r11
|
||||
_bset r11, r11, bitMsrFP
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ InitIDIndex
|
|||
beq Local_Panic
|
||||
|
||||
li r9, 0
|
||||
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
|
||||
stw r9, KDP.NKInfo.IDCtr(r1)
|
||||
|
||||
sth r9, Index.HalfOne(r22)
|
||||
sth r9, Index.HalfTwo(r22)
|
||||
|
|
@ -158,9 +158,9 @@ MakeID
|
|||
@_f0
|
||||
stw r8, 0x0004(r22)
|
||||
stb r9, 0x0000(r22)
|
||||
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
|
||||
lwz r9, KDP.NKInfo.IDCtr(r1)
|
||||
addi r9, r9, 0x01
|
||||
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
|
||||
stw r9, KDP.NKInfo.IDCtr(r1)
|
||||
lhz r20, 0x0000(r18)
|
||||
lhz r8, 0x0002(r22)
|
||||
lwz r21, PSA.IndexPtr(r1)
|
||||
|
|
@ -206,9 +206,9 @@ DeleteID
|
|||
cmpw cr1, r23, r20
|
||||
beqlr
|
||||
bnelr cr1
|
||||
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
|
||||
lwz r9, KDP.NKInfo.IDCtr(r1)
|
||||
addi r9, r9, -0x01
|
||||
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
|
||||
stw r9, KDP.NKInfo.IDCtr(r1)
|
||||
lhz r20, 0x0002(r18)
|
||||
stb r8, 0x0000(r22)
|
||||
addi r20, r20, 0x01
|
||||
|
|
|
|||
|
|
@ -273,19 +273,19 @@ FinishInitBuiltin
|
|||
|
||||
; Copy some choice values out of KDP's copy of NKProcessorInfo
|
||||
|
||||
lwz r9, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1)
|
||||
stw r9, KDP.ProcessorInfo + NKProcessorInfo.ClockRates + 8(r1)
|
||||
lwz r9, KDP.ProcInfo.DecClockRateHz(r1)
|
||||
stw r9, KDP.ProcInfo.ClockRates + 8(r1)
|
||||
|
||||
lwz r9, KDP.ProcessorInfo + NKProcessorInfo.BusClockRateHz(r1)
|
||||
stw r9, KDP.ProcessorInfo + NKProcessorInfo.ClockRates + 4(r1)
|
||||
lwz r9, KDP.ProcInfo.BusClockRateHz(r1)
|
||||
stw r9, KDP.ProcInfo.ClockRates + 4(r1)
|
||||
|
||||
lwz r9, KDP.ProcessorInfo + NKProcessorInfo.CpuClockRateHz(r1)
|
||||
stw r9, KDP.ProcessorInfo + NKProcessorInfo.ClockRates + 0(r1)
|
||||
lwz r9, KDP.ProcInfo.CpuClockRateHz(r1)
|
||||
stw r9, KDP.ProcInfo.ClockRates + 0(r1)
|
||||
|
||||
li r9, 0
|
||||
sth r9, KDP.ProcessorInfo + NKProcessorInfo.SetToZero(r1)
|
||||
sth r9, KDP.ProcInfo.SetToZero(r1)
|
||||
|
||||
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1)
|
||||
lwz r8, KDP.ProcInfo.DecClockRateHz(r1)
|
||||
stw r8, PSA.DecClockRateHzCopy(r1)
|
||||
|
||||
|
||||
|
|
@ -757,7 +757,7 @@ SetProcessorFlags
|
|||
slwi r23, r23, 2
|
||||
add r8, r25, r23
|
||||
lwz r23, ProcessorFlagsTable - NKTop + 64(r8)
|
||||
stw r23, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
|
||||
stw r23, KDP.ProcInfo.ProcessorFlags(r1)
|
||||
b @done
|
||||
|
||||
@pvr_has_high_bit_set
|
||||
|
|
@ -779,7 +779,7 @@ SetProcessorFlags
|
|||
slwi r23, r23, 2
|
||||
add r8, r25, r23
|
||||
lwz r23, ProcessorFlagsTable - NKTop + 128(r8)
|
||||
stw r23, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
|
||||
stw r23, KDP.ProcInfo.ProcessorFlags(r1)
|
||||
b @done
|
||||
|
||||
@done
|
||||
|
|
@ -870,7 +870,7 @@ SetProcessorFlags
|
|||
|
||||
; Save ID in self and KDP
|
||||
stw r8, Process.ID(r31)
|
||||
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.blueProcessID(r1)
|
||||
stw r8, KDP.NKInfo.blueProcessID(r1)
|
||||
|
||||
; Sign it
|
||||
lisori r8, Process.kSignature
|
||||
|
|
@ -1164,7 +1164,7 @@ SetProcessorFlags
|
|||
stw r8, LLL.Freeform(r9)
|
||||
|
||||
; ...which the blue task will probably want to know about
|
||||
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.pageQueueID(r1)
|
||||
stw r8, KDP.NKInfo.pageQueueID(r1)
|
||||
|
||||
InitList r9, 'PAGQ', scratch=r16
|
||||
|
||||
|
|
@ -1215,7 +1215,7 @@ SetProcessorFlags
|
|||
beq Init_Panic
|
||||
|
||||
lwz r8, Task.ID(r31)
|
||||
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.blueTaskID(r1)
|
||||
stw r8, KDP.NKInfo.blueTaskID(r1)
|
||||
|
||||
|
||||
; Can equal -1 or a 68k interrupt number. PIHes touch it.
|
||||
|
|
|
|||
|
|
@ -138,9 +138,9 @@ IntAlignment
|
|||
mfsprg r1, 0
|
||||
stmw r2, EWA.r2(r1)
|
||||
|
||||
lwz r11, KDP.NanoKernelInfo + NKNanoKernelInfo.MisalignmentCount(r1)
|
||||
lwz r11, KDP.NKInfo.MisalignmentCount(r1)
|
||||
addi r11, r11, 1
|
||||
stw r11, KDP.NanoKernelInfo + NKNanoKernelInfo.MisalignmentCount(r1)
|
||||
stw r11, KDP.NKInfo.MisalignmentCount(r1)
|
||||
|
||||
mfsprg r11, 1
|
||||
stw r0, EWA.r0(r1)
|
||||
|
|
|
|||
|
|
@ -243,7 +243,7 @@ VMInit_0x110
|
|||
|
||||
stw r4, KDP.VMLogicalPages(r1)
|
||||
slwi r7, r4, 12
|
||||
stw r7, KDP.SystemInfo + NKSystemInfo.LogicalMemorySize(r1) ; bug in NKv2??
|
||||
stw r7, KDP.SysInfo.LogicalMemorySize(r1) ; bug in NKv2??
|
||||
slwi r7, r4, 2
|
||||
li r8, 0x00
|
||||
|
||||
|
|
@ -873,8 +873,8 @@ VMAllocateMemory_0xf4
|
|||
stw r7, KDP.TotalPhysicalPages(r1)
|
||||
stw r7, KDP.VMLogicalPages(r1)
|
||||
slwi r8, r7, 12
|
||||
stw r8, KDP.SystemInfo + NKSystemInfo.UsableMemorySize(r1)
|
||||
stw r8, KDP.SystemInfo + NKSystemInfo.LogicalMemorySize(r1)
|
||||
stw r8, KDP.SysInfo.UsableMemorySize(r1)
|
||||
stw r8, KDP.SysInfo.LogicalMemorySize(r1)
|
||||
|
||||
addi r14, r1, 120
|
||||
lwz r15, KDP.PARPageListPtr(r1)
|
||||
|
|
@ -1040,10 +1040,10 @@ EditPTEOnlyInHTAB ; OUTSIDE REFERER
|
|||
;r15 is address of stored PTE
|
||||
;r16 is PTE value
|
||||
RemovePTEFromHTAB ; OUTSIDE REFERER
|
||||
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1);update a value in NanoKernelInfo
|
||||
lwz r8, KDP.NKInfo.HashTableDeleteCount(r1);update a value in NanoKernelInfo
|
||||
rlwinm r16, r16, 0, 21, 19 ;update PTE flags to indicate not in HTAB
|
||||
addi r8, r8, 0x01
|
||||
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1)
|
||||
stw r8, KDP.NKInfo.HashTableDeleteCount(r1)
|
||||
rlwimi r16, r9, 0, 0, 19 ;move page# back into PTE
|
||||
|
||||
_InvalNCBPointerCache scratch=r8
|
||||
|
|
@ -1102,10 +1102,10 @@ VMLastExportedFunc_0x83
|
|||
addi r14, r14, 0x08
|
||||
|
||||
VMLastExportedFunc_0x87
|
||||
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableCreateCount(r1)
|
||||
lwz r9, KDP.NKInfo.HashTableCreateCount(r1)
|
||||
rlwinm r8, r6, 7, 1, 24
|
||||
addi r9, r9, 0x01
|
||||
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableCreateCount(r1)
|
||||
stw r9, KDP.NKInfo.HashTableCreateCount(r1)
|
||||
rlwimi r8, r4, 22, 26, 31
|
||||
lwz r9, KDP.PageAttributeInit(r1)
|
||||
oris r8, r8, 0x8000
|
||||
|
|
|
|||
|
|
@ -179,7 +179,7 @@ MPCallTableEnd
|
|||
|
||||
; Not sure where this counter table is?
|
||||
|
||||
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.MPDispatchCountTblPtr(r1)
|
||||
lwz r16, KDP.NKInfo.MPDispatchCountTblPtr(r1)
|
||||
rlwinm r17, r15, 2, 20, 29
|
||||
cmplwi r16, 0
|
||||
beq @no_count
|
||||
|
|
@ -816,7 +816,7 @@ MPDelayUntil
|
|||
MPDelayUntilSys
|
||||
|
||||
rlwinm. r8, r7, 0, EWA.kFlagBlue, EWA.kFlagBlue
|
||||
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1)
|
||||
lwz r16, KDP.NKInfo.ExternalIntCount(r1)
|
||||
beq _MPDelayUntilCommon
|
||||
|
||||
; Why the hell are we counting interrupts?
|
||||
|
|
@ -1796,7 +1796,7 @@ NKSetPrInfoClockRates
|
|||
bge ReturnParamErrFromMPCall
|
||||
|
||||
mulli r17, r3, 16
|
||||
addi r18, r1, KDP.ProcessorInfo + NKProcessorInfo.ClockRates
|
||||
addi r18, r1, KDP.ProcInfo.ClockRates
|
||||
add r18, r17, r18
|
||||
|
||||
lwz r16, ContextBlock.r6(r6)
|
||||
|
|
@ -2114,7 +2114,7 @@ MPCall_133 ; OUTSIDE REFERER
|
|||
_Lock PSA.SchLock, scratch1=r16, scratch2=r17
|
||||
|
||||
cmpw r3, r0
|
||||
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
|
||||
lwz r16, KDP.NKInfo.ConfigFlags(r1)
|
||||
li r17, 0x0b
|
||||
blt MPCall_133_0x34
|
||||
and r3, r3, r17
|
||||
|
|
|
|||
|
|
@ -90,10 +90,10 @@ PopulateHTAB ; LogicalAddress r28 // Success cr0.eq
|
|||
sync ; because we just wanged the page table
|
||||
stwu r30, -24(r29) ; PTE[hi] = r30
|
||||
|
||||
lwz r28, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableCreateCount(r1)
|
||||
lwz r28, KDP.NKInfo.HashTableCreateCount(r1)
|
||||
stw r29, KDP.ApproxCurrentPTEG(r1)
|
||||
addi r28, r28, 1
|
||||
stw r28, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableCreateCount(r1)
|
||||
stw r28, KDP.NKInfo.HashTableCreateCount(r1)
|
||||
beqlr ; >>>>> RETURN "BEQ" if we got to "Case 1" directly
|
||||
|
||||
cmpwi r26, 0x5A5A ; Special value set so that we take note of this new temporary PTE?
|
||||
|
|
@ -115,10 +115,10 @@ PopulateHTAB ; LogicalAddress r28 // Success cr0.eq
|
|||
########################################################################
|
||||
; Helpful code that jumps back to roughly where it started
|
||||
@remove_temp_pte
|
||||
lwz r28, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1)
|
||||
lwz r28, KDP.NKInfo.HashTableDeleteCount(r1)
|
||||
lwz r29, KDP.HtabTempEntryPtr(r1)
|
||||
addi r28, r28, 1
|
||||
stw r28, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1)
|
||||
stw r28, KDP.NKInfo.HashTableDeleteCount(r1)
|
||||
li r28, 0
|
||||
stw r28, 0(r29)
|
||||
lwz r29, KDP.HtabTempPage(r1)
|
||||
|
|
@ -257,14 +257,14 @@ PopulateHTAB ; LogicalAddress r28 // Success cr0.eq
|
|||
extrwi r31, r26, 2, 20
|
||||
cmpwi cr7, r31, 3 ; not a DaddyFlag + CountingFlag? Try again!
|
||||
|
||||
lwz r31, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableOverflowCount(r1)
|
||||
lwz r31, KDP.NKInfo.HashTableOverflowCount(r1)
|
||||
stw r29, KDP.OverflowingPTEG(r1)
|
||||
addi r31, r31, 1
|
||||
stw r31, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableOverflowCount(r1)
|
||||
lwz r31, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1)
|
||||
stw r31, KDP.NKInfo.HashTableOverflowCount(r1)
|
||||
lwz r31, KDP.NKInfo.HashTableDeleteCount(r1)
|
||||
stw r30, 0(r29)
|
||||
addi r31, r31, 1
|
||||
stw r31, KDP.NanoKernelInfo + NKNanoKernelInfo.HashTableDeleteCount(r1)
|
||||
stw r31, KDP.NKInfo.HashTableDeleteCount(r1)
|
||||
|
||||
sync
|
||||
tlbie r28
|
||||
|
|
@ -530,7 +530,7 @@ nobats
|
|||
########################################################################
|
||||
|
||||
FlushTLB
|
||||
lhz r29, KDP.ProcessorInfo + NKProcessorInfo.TransCacheTotalSize(r1)
|
||||
lhz r29, KDP.ProcInfo.TransCacheTotalSize(r1)
|
||||
slwi r29, r29, 11
|
||||
@loop
|
||||
subi r29, r29, 4096
|
||||
|
|
|
|||
|
|
@ -457,9 +457,9 @@ _pool_page_seg equ 0x1000
|
|||
|
||||
; Counter can be viewed from Apple System Profiler
|
||||
|
||||
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.FreePoolExtendCount(r1)
|
||||
lwz r16, KDP.NKInfo.FreePoolExtendCount(r1)
|
||||
addi r16, r16, 1
|
||||
stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.FreePoolExtendCount(r1)
|
||||
stw r16, KDP.NKInfo.FreePoolExtendCount(r1)
|
||||
|
||||
|
||||
; Bit of palaver
|
||||
|
|
|
|||
|
|
@ -290,7 +290,7 @@ PwrSuspendSystem
|
|||
|
||||
; Disable L2 cache (via L2CR, if present)
|
||||
|
||||
lwz r26, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
|
||||
lwz r26, KDP.ProcInfo.ProcessorFlags(r1)
|
||||
andi. r26, r26, 1 << NKProcessorInfo.hasL2CR
|
||||
beq @no_need_to_deactivate_l2
|
||||
mfspr r9, l2cr
|
||||
|
|
@ -459,10 +459,10 @@ PwrSuspendSystem
|
|||
|
||||
; Reactivate L2 cache
|
||||
|
||||
lwz r26, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
|
||||
lwz r26, KDP.ProcInfo.ProcessorFlags(r1)
|
||||
andi. r26, r26, 1 << NKProcessorInfo.hasL2CR
|
||||
beq @no_need_to_reactivate_l2
|
||||
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1)
|
||||
lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
|
||||
mr. r8, r8
|
||||
beq @no_need_to_reactivate_l2
|
||||
|
||||
|
|
|
|||
|
|
@ -199,7 +199,7 @@ CommonPIHPath_0xc ; OUTSIDE REFERER
|
|||
addi r8, r31, Task.Timer
|
||||
bl DequeueTimer
|
||||
@task_timer_not_in_use
|
||||
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1)
|
||||
lwz r16, KDP.NKInfo.ExternalIntCount(r1)
|
||||
stw r16, PSA.OtherSystemContextPtr(r1)
|
||||
|
||||
@now_reschedule_task
|
||||
|
|
@ -327,9 +327,9 @@ PDM_PIH
|
|||
mfsprg r30, 3
|
||||
|
||||
bne @nocount
|
||||
lwz r21, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1)
|
||||
lwz r21, KDP.NKInfo.ExternalIntCount(r1)
|
||||
addi r21, r21, 0x01
|
||||
stw r21, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1)
|
||||
stw r21, KDP.NKInfo.ExternalIntCount(r1)
|
||||
@nocount
|
||||
|
||||
; Switch to Blue vector table
|
||||
|
|
|
|||
|
|
@ -362,14 +362,14 @@ replace_old_kernel_0x198
|
|||
sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r1)
|
||||
|
||||
|
||||
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1)
|
||||
lwz r8, KDP.ProcInfo.DecClockRateHz(r1)
|
||||
stw r8, PSA.DecClockRateHzCopy(r1)
|
||||
|
||||
|
||||
|
||||
; Play with ConfigFlags
|
||||
|
||||
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
|
||||
lwz r8, KDP.NKInfo.ConfigFlags(r1)
|
||||
|
||||
_bset r8, r8, 31 ; always set bit 31
|
||||
|
||||
|
|
@ -382,7 +382,7 @@ replace_old_kernel_0x198
|
|||
_bset r8, r8, 27
|
||||
@oldrom
|
||||
|
||||
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
|
||||
stw r8, KDP.NKInfo.ConfigFlags(r1)
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -338,7 +338,7 @@ CreatePageList
|
|||
lwz r20, KDP.KernelMemoryEnd(r1)
|
||||
subi r29, r21, 4 ; ptr to last added entry
|
||||
|
||||
addi r19, r1, KDP.SystemInfo + NKSystemInfo.Bank0Start - 8
|
||||
addi r19, r1, KDP.SysInfo.Bank0Start - 8
|
||||
|
||||
lwz r23, KDP.PageAttributeInit(r1) ; default WIMG/PP settings in PTEs
|
||||
|
||||
|
|
@ -394,9 +394,9 @@ CreatePARInPageMap
|
|||
addi r19, r22, 4
|
||||
slwi r19, r19, 10
|
||||
ori r30, r30, 0xffff
|
||||
stw r19, KDP.SystemInfo + NKSystemInfo.UsableMemorySize(r1)
|
||||
stw r19, KDP.SysInfo.UsableMemorySize(r1)
|
||||
srwi r22, r22, 2
|
||||
stw r19, KDP.SystemInfo + NKSystemInfo.LogicalMemorySize(r1)
|
||||
stw r19, KDP.SysInfo.LogicalMemorySize(r1)
|
||||
|
||||
; convert r19 to pages, and save in some places
|
||||
srwi r19, r19, 12
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ Local_Panic set *
|
|||
SchInit
|
||||
|
||||
li r16, 0
|
||||
stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.TaskCount(r1)
|
||||
stw r16, KDP.NKInfo.TaskCount(r1)
|
||||
|
||||
mflr r20
|
||||
|
||||
|
|
@ -883,9 +883,9 @@ _SchRdyTaskCommon
|
|||
SchSwitchSpace
|
||||
|
||||
; This is the only function that hits this counter
|
||||
lwz r17, KDP.NanoKernelInfo + NKNanoKernelInfo.AddrSpcSetCtr(r1)
|
||||
lwz r17, KDP.NKInfo.AddrSpcSetCtr(r1)
|
||||
addi r17, r17, 1
|
||||
stw r17, KDP.NanoKernelInfo + NKNanoKernelInfo.AddrSpcSetCtr(r1)
|
||||
stw r17, KDP.NKInfo.AddrSpcSetCtr(r1)
|
||||
|
||||
; Check that we have the right guy (a 'SPAC')
|
||||
lwz r16, AddressSpace.Signature(r8)
|
||||
|
|
@ -1026,7 +1026,7 @@ SchSwitchSpace
|
|||
; This is weird. If the hasExtraBATs flag (my name) is set in ProcessorInfo,
|
||||
; populate a second (undocumented?) set of BATs from the same struct.
|
||||
|
||||
lwz r17, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
|
||||
lwz r17, KDP.ProcInfo.ProcessorFlags(r1)
|
||||
lwz r16, AddressSpace.ExtraBAT0U(r8)
|
||||
rlwinm. r17, r17, 0, 31-NKProcessorInfo.hasExtraBATs, 31-NKProcessorInfo.hasExtraBATs
|
||||
lwz r17, AddressSpace.ExtraBAT0U(r9)
|
||||
|
|
@ -1199,9 +1199,9 @@ SchEval
|
|||
lwz r31, EWA.PA_CurTask(r14)
|
||||
lwz r1, EWA.PA_KDP(r14)
|
||||
|
||||
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.SchEvalCount(r1)
|
||||
lwz r9, KDP.NKInfo.SchEvalCount(r1)
|
||||
addi r9, r9, 1
|
||||
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.SchEvalCount(r1)
|
||||
stw r9, KDP.NKInfo.SchEvalCount(r1)
|
||||
|
||||
bl SchFiddlePriorityShifty
|
||||
lbz r27, 0x0019(r31)
|
||||
|
|
@ -2006,9 +2006,9 @@ FlagSchEval
|
|||
; To force a scheduler evaluation to run on *another* CPU, we interrupt it
|
||||
|
||||
AlertSchEvalOnOtherCPU
|
||||
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.AlertCount(r1)
|
||||
lwz r9, KDP.NKInfo.AlertCount(r1)
|
||||
addi r9, r9, 1
|
||||
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.AlertCount(r1)
|
||||
stw r9, KDP.NKInfo.AlertCount(r1)
|
||||
|
||||
li r16, kAlert
|
||||
stw r16, EWA.SIGPSelector(r15)
|
||||
|
|
|
|||
|
|
@ -71,10 +71,10 @@ IllegalInstruction
|
|||
addc r21, r21, r8
|
||||
addze r20, r20
|
||||
mtxer r23
|
||||
lwz r23, KDP.NanoKernelInfo + NKNanoKernelInfo.EmulatedUnimpInstCount(r1)
|
||||
lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
||||
rlwimi r7, r7, 27, 26, 26
|
||||
addi r23, r23, 1
|
||||
stw r23, KDP.NanoKernelInfo + NKNanoKernelInfo.EmulatedUnimpInstCount(r1)
|
||||
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
||||
|
||||
stwx r21, r1, r28 ; save register into EWA
|
||||
mr r16, r7
|
||||
|
|
@ -84,10 +84,10 @@ IllegalInstruction
|
|||
|
||||
|
||||
@STFIWX
|
||||
lwz r23, KDP.NanoKernelInfo + NKNanoKernelInfo.EmulatedUnimpInstCount(r1)
|
||||
lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
||||
mr r27, r8
|
||||
addi r23, r23, 1
|
||||
stw r23, KDP.NanoKernelInfo + NKNanoKernelInfo.EmulatedUnimpInstCount(r1)
|
||||
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
||||
mfmsr r14
|
||||
_bset r15, r14, bitMsrDR
|
||||
b loc_A38
|
||||
|
|
@ -178,9 +178,9 @@ KCallRunAlternateContext
|
|||
|
||||
; Found a non-cached physical address for this NCB!
|
||||
|
||||
lwz r23, KDP.NanoKernelInfo + NKNanoKernelInfo.NCBPtrCacheMissCount(r1)
|
||||
lwz r23, KDP.NKInfo.NCBPtrCacheMissCount(r1)
|
||||
addi r23, r23, 1
|
||||
stw r23, KDP.NanoKernelInfo + NKNanoKernelInfo.NCBPtrCacheMissCount(r1)
|
||||
stw r23, KDP.NKInfo.NCBPtrCacheMissCount(r1)
|
||||
|
||||
|
||||
; Stick it in cache slot 3
|
||||
|
|
@ -358,10 +358,10 @@ IntProgram
|
|||
; SUCCESSFUL TRAP from emulator KCall table
|
||||
; => Service call then return to link register
|
||||
add r8, r8, r1
|
||||
lwz r11, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
||||
lwz r11, KDP.NKInfo.NanoKernelCallCounts(r8)
|
||||
lwz r10, KDP.NanoKernelCallTable(r8)
|
||||
addi r11, r11, 1
|
||||
stw r11, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
||||
stw r11, KDP.NKInfo.NanoKernelCallCounts(r8)
|
||||
mtlr r10
|
||||
mr r10, r12 ; ret addr: LR was saved to SPRG2, SPRG2 to r12 above, r12 to r10 now, r10 to SRR0 to program ctr later
|
||||
mfsrr1 r11
|
||||
|
|
@ -386,9 +386,9 @@ IntProgram
|
|||
; SUCCESSFUL TRAP from outside emulator KCall table
|
||||
; => Service call then return to following instruction
|
||||
add r8, r8, r1
|
||||
lwz r10, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
||||
lwz r10, KDP.NKInfo.NanoKernelCallCounts(r8)
|
||||
addi r10, r10, 1
|
||||
stw r10, KDP.NanoKernelInfo + NKNanoKernelInfo.NanoKernelCallCounts(r8)
|
||||
stw r10, KDP.NKInfo.NanoKernelCallCounts(r8)
|
||||
lwz r8, KDP.NanoKernelCallTable(r8)
|
||||
mtlr r8
|
||||
addi r10, r10, 4 ; continue executing the next instruction
|
||||
|
|
|
|||
|
|
@ -298,9 +298,9 @@ CreateTask
|
|||
stw r8, Task.CreateTime3(r28)
|
||||
stw r9, Task.CreateTime3 + 4(r28)
|
||||
|
||||
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.TaskCount(r1)
|
||||
lwz r16, KDP.NKInfo.TaskCount(r1)
|
||||
addi r16, r16, 1
|
||||
stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.TaskCount(r1)
|
||||
stw r16, KDP.NKInfo.TaskCount(r1)
|
||||
|
||||
; Squeeze some info (including my owning process) out of the passed PROC ptr
|
||||
stw r27, Task.OwningProcessPtr(r28)
|
||||
|
|
|
|||
|
|
@ -115,9 +115,9 @@ InitTMRQs_0xb4
|
|||
rlwinm. r8, r31, 0, NKConfigurationInfo.NanodbgrFlagBit, NKConfigurationInfo.NanodbgrFlagBit
|
||||
beq @nodebug
|
||||
|
||||
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
|
||||
lwz r8, KDP.NKInfo.ConfigFlags(r1)
|
||||
_bset r8, r8, NKNanoKernelInfo.NanodbgrFlagBit
|
||||
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
|
||||
stw r8, KDP.NKInfo.ConfigFlags(r1)
|
||||
|
||||
mflr r30
|
||||
|
||||
|
|
@ -587,12 +587,12 @@ TimerFire5_0x8 ; OUTSIDE REFERER
|
|||
; Dead code -- probably removed from TimerTable
|
||||
|
||||
_log 'Heartbeat: Ext '
|
||||
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.ExternalIntCount(r1)
|
||||
lwz r16, KDP.NKInfo.ExternalIntCount(r1)
|
||||
mr r8, r16
|
||||
bl printd
|
||||
|
||||
_log 'Alerts '
|
||||
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.AlertCount(r1)
|
||||
lwz r16, KDP.NKInfo.AlertCount(r1)
|
||||
mr r8, r16
|
||||
bl printd
|
||||
|
||||
|
|
@ -886,7 +886,7 @@ DequeueTimer
|
|||
TimebaseTicksPerPeriod
|
||||
mr. r17, r8
|
||||
li r19, 250
|
||||
lwz r9, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1)
|
||||
lwz r9, KDP.ProcInfo.DecClockRateHz(r1)
|
||||
|
||||
bgt+ @period_positive
|
||||
blt+ @period_negative
|
||||
|
|
|
|||
|
|
@ -2243,7 +2243,7 @@ ProbePerfMonitor ; OUTSIDE REFERER
|
|||
lisori r21, 0xd62611e3
|
||||
|
||||
; Left-justify the decrementer clock rate
|
||||
lwz r19, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1)
|
||||
lwz r19, KDP.ProcInfo.DecClockRateHz(r1)
|
||||
cntlzw r23, r19
|
||||
slw r19, r19, r23
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user