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Elliot Nunn 2018-08-08 22:23:59 +08:00
parent 25297816eb
commit 83c2a47a2c
15 changed files with 993 additions and 1246 deletions
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2
NanoKernel/MROptabCode.s
View File

@ -217,7 +217,7 @@ MRSecDone
@trace ; Jump to Trace int handler
mfsprg r24, 3
mtsprg 2, r12
_clear r16, r16, bitContextFlagTraceWhenDone
rlwinm r16, r16, 0, ~ContextFlagTraceWhenDone
lwz r12, VecTbl.Trace(r24)
stw r16, KDP.Flags(r1)
mtcr r13

2
NanoKernel/NKColdInts.s
View File

@ -25,7 +25,7 @@ InstStorageInt
mfsprg r24, 3
mfmsr r14
_set r15, r14, bitMsrDR
_ori r15, r14, MsrDR
addi r23, r1, KDP.VecTblMemRetry
mtsprg 3, r23
mr r19, r10

693
NanoKernel/NKEquates.s
View File

@ -1,110 +1,56 @@
;_______________________________________________________________________
; Equates for the whole NanoKernel
;_______________________________________________________________________
kVersion equ 0x0101
########################################################################
; Helps with making equates
; X = 0x00008000, Xbit=16, Xshift=15
macro
_bitEqu &bit, &name
&name equ 1 << (31-&bit)
bit&name equ &bit
shift&name equ 31 - &bit
endm
; Machine Status Register (MSR)
_bitequate 13, MsrPOW
_bitequate 15, MsrILE
_bitequate 16, MsrEE
_bitequate 17, MsrPR
_bitequate 18, MsrFP
_bitequate 19, MsrME
_bitequate 20, MsrFE0
_bitequate 21, MsrSE
_bitequate 22, MsrBE
_bitequate 23, MsrFE1
_bitequate 25, MsrIP
_bitequate 26, MsrIR
_bitequate 27, MsrDR
_bitequate 30, MsrRI
_bitequate 31, MsrLE
########################################################################
; BO field values for "bc" (condition branch) instructions
BO_IF equ 12
BO_IF_NOT equ 4
kNanoKernelVersion equ $0101
########################################################################
; "Exception cause" codes
ecNoException equ 0
ecSystemCall equ 1
ecTrapInstr equ 2
ecFloatException equ 3
ecInvalidInstr equ 4
ecPrivilegedInstr equ 5
ecMachineCheck equ 7
ecInstTrace equ 8
ecInstInvalidAddress equ 10
ecInstHardwareFault equ 11
ecInstPageFault equ 12
ecInstSupAccessViolation equ 14
ecDataInvalidAddress equ 18
ecDataHardwareFault equ 19
ecDataPageFault equ 20
ecDataWriteViolation equ 21
ecDataSupAccessViolation equ 22
ecDataSupWriteViolation equ 23
ecUnknown24 equ 24
; PowerPC Machine Status Register (MSR) bits
; (borrowing the _bitEqu macro from NKInfoRecordsPriv.s)
_bitEqu 13, MsrPOW
_bitEqu 15, MsrILE
_bitEqu 16, MsrEE
_bitEqu 17, MsrPR
_bitEqu 18, MsrFP
_bitEqu 19, MsrME
_bitEqu 20, MsrFE0
_bitEqu 21, MsrSE
_bitEqu 22, MsrBE
_bitEqu 23, MsrFE1
_bitEqu 25, MsrIP
_bitEqu 26, MsrIR
_bitEqu 27, MsrDR
_bitEqu 30, MsrRI
_bitEqu 31, MsrLE
; Special Purpose Registers (SPRs) not understood by MPW
l2cr equ 1017
; Alignment for NanoKernel interrupt routines (mostly Interrupts.s)
kIntAlign equ 5
; Junk
; IRP is 10 pages below KDP (measured start to start)
; This should be neatened up to describe the kernel global area
IRPOffset equ (-10) * 4096
kKDPfromIRP equ 10 * 4096
kPoolOffsetFromGlobals equ (-7) * 4096 ; goes all the way up to 24 bytes short of PSA
; Branch instruction BO fields
; (disregarding static prediction :)
BO_IF equ 12
BO_IF_NOT equ 4
Z equ 0x80000000
; SIGP (SIGnal Plugin) selectors used by the kernel:
kStartProcessor equ 1 ; r4 = target CPU idx, r5 = cpu's entry point, r6 = entry point's r3 (CPU struct ptr)
kStopProcessor equ 3 ; r4 = target CPU idx
kResetProcessor equ 4 ; r4 = target CPU idx
kAlert equ 5 ; r4 = target CPU idx? ; my name, has something to do with timers
kSIGP6 equ 6 ; r4 = target CPU idx?
kSIGP7 equ 7 ; r4 = target CPU idx?
kSynchClock equ 8 ; r4 = target CPU idx,
kSIGP9 equ 9 ; no args?
kGetProcessorTemp equ 12 ; r4 = selector (ignored on Core99), r5 = cpu ID ; my name
kSIGP17 equ 17 ; r4 = target CPU idx?
; Exception cause equates
; System = FFFFFFFF, Alt = 7DF2F700 (ecInstPageFault and ecDataPageFault disabled), same +/- VM
ecNoException equ 0
ecSystemCall equ 1
ecTrapInstr equ 2
ecFloatException equ 3
ecInvalidInstr equ 4
ecPrivilegedInstr equ 5
ecMachineCheck equ 7
ecInstTrace equ 8
ecInstInvalidAddress equ 10
ecInstHardwareFault equ 11
ecInstPageFault equ 12
ecInstSupAccessViolation equ 14
ecDataInvalidAddress equ 18
ecDataHardwareFault equ 19
ecDataPageFault equ 20
ecDataWriteViolation equ 21
ecDataSupAccessViolation equ 22
ecDataSupWriteViolation equ 23
ecUnknown24 equ 24
; FLAGS r7/cr
########################################################################
; NanoKernel flags (often in Cond Reg or r7)
crMaskAll equ %11111111
; Bits 0-7 (CR0-CR1): Exception Cause Number (see equates)
@ -117,8 +63,8 @@ maskFlags equ 0x00FFFFFF
; Bits 8-15 (CR2-CR3) Global Flags
crMaskGlobalFlags equ %00110000
maskGlobalFlags equ 0x00FF0000
_bitEqu 8, GlobalFlagSystem ; raised when System (Emulator) Context is running
_bitEqu 13, GlobalFlagMQReg ; raised when POWER "Multiply-Quotient" register is present
_bitequate 8, GlobalFlagSystem ; raised when System (Emulator) Context is running
_bitequate 13, GlobalFlagMQReg ; raised when pre-PowerPC MQ register is present
; Bits 24-31 (CR6-CR7) Context Flags
crMaskContextFlags equ %00001111
@ -127,12 +73,551 @@ maskContextFlags equ 0x0000FFFF
crMaskMsrFlags equ %00000100
maskMsrFlags equ 0x00000F00
; Bits 24-31 (CR6-CR7) Other Context Flags:
_bitEqu 26, ContextFlagTraceWhenDone ; raised when MSR[SE] is up but we get an unrelated interrupt
_bitEqu 27, ContextFlagMemRetryErr ; raised when an exception is raised during MemRetry
_bitEqu 31, ContextFlagResumeMemRetry ; allows MemRetry to be resumed (raised by userspace?)
_bitequate 26, ContextFlagTraceWhenDone ; raised when MSR[SE] is up but we get an unrelated interrupt
_bitequate 27, ContextFlagMemRetryErr ; raised when an exception is raised during MemRetry
_bitequate 31, ContextFlagResumeMemRetry ; allows MemRetry to be resumed (raised by userspace?)
########################################################################
; MemRetry flags in CR3
mrOpflag1 equ cr3_lt
mrOpflag2 equ cr3_gt
mrOpflag3 equ cr3_eq
mrFlagDidLoad equ cr3_so
########################################################################
; PowerPC Page Table Entries
; (The Page Table is called the "HTAB" for "Hash Table", but Page Table
; Entries and Entry Groups are called "PTEs" and "PTEGs".)
; Upper word of a Page Table Entry (PTE):
_bitequate 0, UpteValid ; if valid then a signed compare will raise the LT bit
; bits 1-24 hold the Virtual Segment ID (VSID, allows one HTAB to hold many addr spaces)
_bitequate 25, UpteHash ; set if this PTE is placed according to secondary hash
; bits 26-31 hold the Abbreviated Page Index (API, the EA bits that aren't implicit in the hash)
; Lower word of a Page Table Entry (PTE):
; bits 0-19 hold the Real Page Number (RPN, the address of the physical page)
; bits 20-22 are reserved
_bitequate 23, LpteReference ; set by arch when page is read
_bitequate 24, LpteChange ; set by arch when page is written
_bitequate 25, LpteWritethru ; these are the "WIMG" memory access policy bits
_bitequate 26, LpteInhibcache
_bitequate 27, LpteMemcoher
_bitequate 28, LpteGuardwrite
; bit 29 is reserved
_bitequate 30, LpteP1 ; supervisor and user access policy bits (check these)
_bitequate 31, LpteP2
; Some combinations from the v1 Trampoline:
ATTR_RW_Locked equ LpteMemcoher
ATTR_RW equ LpteMemcoher | LpteP1
ATTR_RO equ LpteMemcoher | LpteP1 | LpteP2
ATTR_IO_Locked equ LpteInhibcache | LpteGuardwrite
ATTR_IO equ LpteInhibcache | LpteGuardwrite | LpteP1
ATTR_RO_Quiet equ LpteWritethru | LpteMemcoher | LpteP1 | LpteP2
ATTR_RO_Locked equ LpteChange | LpteMemcoher | LpteP1 | LpteP2
ATTR_RO_LockedQuiet equ LpteWritethru | LpteChange | LpteMemcoher | LpteP1 | LpteP2
; "PMDTs" (described below) imitate the lower word of a PTE.
########################################################################
; "PMDTs" (PageMap somethings?) are the elements of the global PageMap.
; Each one describes how a contiguous range of effective addresses is
; stored in physical memory.
; A PMDT itself does not say which 256MB "segment" of the logical space
; space contains its area, but only describes the location and size of the
; area within a segment. Each of the four system "address spaces"
; (Supervisor, User, CPU and Overlay) has a "Segment Map": an array of 16
; pointer/segment-register pairs, one per segment. Each segment pointer
; refers to a location within the PageMap. To list the PMDTs associated
; with a segment, it is necessary to start at the referenced location
; within the PageMap and iterate over PMDTs until a special end-of-segment
; value is encountered. The SegMaps and the PageMap are initialized from
; templates in the ConfigInfo when the NanoKernel starts.
PMDT RECORD 0, INCR
PageIdx ds.w 1 ; area location within 256MB segment
PageCount ds.w 1 ; area size in pages, minus one
Word2 ds.l 1 ; second word is similar to a lower PTE word (20-bit RPN + 12-bit Attrs)
Size equ 8
ENDR
; bits 0-19 of Word2, like a PTE, contain a Real Page Number (RPN) that can actually have several uses
; bits 20-31 of Word2 contain bits ("Pattrs") that guide PMDT interpretation (especially of RPN)
EveryPattr equ 0xE01 ; The union of every bit below (NB: E00 bits are reserved in a PTE)
; When Pattr_NotPTE=1, the PMDT is a pageable area or another special value:
Pattr_NotPTE equ 0x800
Pattr_68k equ 0x400 ; Pageable area with RPN pointing to 68k PTE array
PMDT_InvalidAddress equ 0xA00 ; Known combinations when Pattr_NotPTE=1...
PMDT_Available equ 0xA01
PMDT_68k equ 0xC00
; When Pattr_NotPTE=0, the PMDT describes a non-pageable area, and these apply:
Pattr_PTE_Single equ 0x400 ; Only one page
Pattr_PTE_Rel equ 0x200 ; RPN is ConfigInfo-relative
PMDT_PTE_Range equ 0x000 ; Known combinations when Pattr_NotPTE=0...
PMDT_PTE_Range_Rel equ 0x200
PMDT_PTE_Single equ 0x400
PMDT_PTE_Single_Rel equ 0x600
; Other attrs (not in EveryPattr) are used, but they tend to be copied
; directly into the PTE.
########################################################################
; 68k Page Table Entries
; A handful of special PMDTs describe the MacOS "Primary Address Range"
; (the contiguous RAM starting at address 0 and containing the sys and app
; heaps etc). Instead of referring directly to physical pages, each of
; these PMDTs has in its RPN field a pointer to an array of 68k Page Table
; Entries! Besides being friendly to old Virtual Memory Manger code, this
; provides a convenient way to store state for individual logical pages
; and to allow them to use discontiguous physical backing.
; Bits 0-9:
; if M68pteInHTAB: PTE offset (in 8b increments from HTABORG)
; else: Real Page Number (RPN)
_bitequate 20, M68pteInHTAB ; (unlike 68k)
_bitequate 21, M68pte21
_bitequate 22, M68pteSavedUpdate
_bitequate 23, M68pte23
_bitequate 24, M68pte24
_bitequate 25, M68pteInhibcache ; (unlike 68k) like PPC Inhibcache
_bitequate 26, M68pteNonwritethru ; (unlike 68k) like inverse of PPC Writethru
_bitequate 27, M68pteModified ; like PPC Change
_bitequate 28, M68pteUpdate ; like PPC Reference
_bitequate 29, M68pteWriteProtect
_bitequate 30, M68pte30
_bitequate 31, M68pteResident ; (unlike 68k) there is a physical page
########################################################################
VecTbl RECORD 0, INCR ; SPRG3 vector table (looked up by ROM vectors)
ds.l 1 ; 00 ; scratch for IVT
SystemReset ds.l 1 ; 04 ; from IVT+100
MachineCheck ds.l 1 ; 08 ; from IVT+200
DSI ds.l 1 ; 0c ; from IVT+300
ISI ds.l 1 ; 10 ; from IVT+400
External ds.l 1 ; 14 ; from IVT+500
Alignment ds.l 1 ; 18 ; from IVT+600
Program ds.l 1 ; 1c ; from IVT+700
FPUnavail ds.l 1 ; 20 ; from IVT+800
Decrementer ds.l 1 ; 24 ; from IVT+900
ReservedVector1 ds.l 1 ; 28 ; from IVT+a00
ReservedVector2 ds.l 1 ; 2c ; from IVT+b00
Syscall ds.l 1 ; 30 ; from IVT+c00
Trace ds.l 1 ; 34 ; from IVT+d00
FPAssist ds.l 1 ; 38 ; from IVT+e00
PerfMonitor ds.l 1 ; 3c ; from IVT+f00
ds.l 1 ; 40
ds.l 1 ; 44
ds.l 1 ; 48
ds.l 1 ; 4c ; Vectors from here downwards are called from
ds.l 1 ; 50 ; odd places in the IVT
ds.l 1 ; 54
ds.l 1 ; 58 ; seems AltiVec-related
ThermalEvent ds.l 1 ; 5c
ds.l 1 ; 60
ds.l 1 ; 64
ds.l 1 ; 68
ds.l 1 ; 6c
ds.l 1 ; 70
ds.l 1 ; 74
ds.l 1 ; 78
ds.l 1 ; 7c
OtherTrace ds.l 1 ; 80
ds.l 1 ; 84
ds.l 1 ; 88
ds.l 1 ; 8c
ds.l 1 ; 90
ds.l 1 ; 94
ds.l 1 ; 98
ds.l 1 ; 9c
ds.l 1 ; a0
ds.l 1 ; a4
ds.l 1 ; a8
ds.l 1 ; ac
ds.l 1 ; b0
ds.l 1 ; b4
ds.l 1 ; b8
ds.l 1 ; bc ; from IVT+0
Size equ *
ENDR
########################################################################
KCallTbl RECORD 0, INCR ; NanoKernel call table
ReturnFromException ds.l 1 ; 00, trap 0
RunAlternateContext ds.l 1 ; 04, trap 1
ResetSystem ds.l 1 ; 08, trap 2 ; 68k RESET
VMDispatch ds.l 1 ; 0c, trap 3 ; 68k $FE0A
PrioritizeInterrupts ds.l 1 ; 10, trap 4
PowerDispatch ds.l 1 ; 14, trap 5 ; 68k $FEOF
RTASDispatch ds.l 1 ; 18, trap 6
CacheDispatch ds.l 1 ; 1c, trap 7
MPDispatch ds.l 1 ; 20, trap 8
ds.l 1 ; 24, trap 9
ds.l 1 ; 28, trap 10
ds.l 1 ; 2c, trap 11
CallAdapterProcPPC ds.l 1 ; 30, trap 12
ds.l 1 ; 34, trap 13
CallAdapterProc68k ds.l 1 ; 38, trap 14
SystemCrash ds.l 1 ; 3c, trap 15
Size equ *
ENDR
########################################################################
MemMap RECORD 0, INCR
SegMapPtr ds.l 1 ; ptr to array of sixteen 8-byte (ptr/flags) records; ptr is to first PMDT for seg
BatMap ds.l 1 ; packed array of 4-bit indices into BATs
ENDR
########################################################################
KDP RECORD 0, INCR ; Kernel Data Page
r0 ds.l 1 ; 000 ; used for quick register saves at interrupt time
r1 ds.l 1 ; 004
r2 ds.l 1 ; 008
r3 ds.l 1 ; 00c
r4 ds.l 1 ; 010
r5 ds.l 1 ; 014
r6 ds.l 1 ; 018
r7 ds.l 1 ; 01c
r8 ds.l 1 ; 020
r9 ds.l 1 ; 024
r10 ds.l 1 ; 028
r11 ds.l 1 ; 02c
r12 ds.l 1 ; 030
r13 ds.l 1 ; 034
r14 ds.l 1 ; 038
r15 ds.l 1 ; 03c
r16 ds.l 1 ; 040
r17 ds.l 1 ; 044
r18 ds.l 1 ; 048
r19 ds.l 1 ; 04c
r20 ds.l 1 ; 050
r21 ds.l 1 ; 054
r22 ds.l 1 ; 058
r23 ds.l 1 ; 05c
r24 ds.l 1 ; 060
r25 ds.l 1 ; 064
r26 ds.l 1 ; 068
r27 ds.l 1 ; 06c
r28 ds.l 1 ; 070
r29 ds.l 1 ; 074
r30 ds.l 1 ; 078
r31 ds.l 1 ; 07c
SegMaps
SegMap32SupInit ds.l 32 ; 080:100
SegMap32UsrInit ds.l 32 ; 100:180
SegMap32CPUInit ds.l 32 ; 180:200
SegMap32OvlInit ds.l 32 ; 200:280
BATs ds.l 32 ; 280:300
CurIBAT0 ds BAT ; 300:308
CurIBAT1 ds BAT ; 308:310
CurIBAT2 ds BAT ; 310:318
CurIBAT3 ds BAT ; 318:320
CurDBAT0 ds BAT ; 320:328
CurDBAT1 ds BAT ; 328:330
CurDBAT2 ds BAT ; 330:338
CurDBAT3 ds BAT ; 338:340
NCBPointerCache
NCBCacheLA0 ds.l 1 ; 340
NCBCachePA0 ds.l 1 ; 344
NCBCacheLA1 ds.l 1 ; 348
NCBCachePA1 ds.l 1 ; 34c
NCBCacheLA2 ds.l 1 ; 350
NCBCachePA2 ds.l 1 ; 354
NCBCacheLA3 ds.l 1 ; 358
NCBCachePA3 ds.l 1 ; 35c
NCBPointerCacheEnd
VecTblSystem ds VecTbl ; 360:420 ; when 68k emulator is running, *or* any MTask
VecTblAlternate ds VecTbl ; 420:4e0 ; native PowerPC in blue task
VecTblMemRetry ds VecTbl ; 4e0:5a0 ; "FDP" instruction emulation
FloatScratch ds.d 1 ; 5a0:5a8
TopOfFreePages ds.l 1 ; 5a8 ; gotten from the old SPRG0
ds.l 1 ; 5ac
PARPerSegmentPLEPtrs ds.l 4 ; 5b0:5c0 ; for each PAR segment, a ptr into the PAR PageList
FloatingPtTemp1 ds.l 1 ; 5c0
FloatingPtTemp2 ds.l 1 ; 5c4
SupervisorMap ds MemMap ; 5c8:5d0
UserMap ds MemMap ; 5d0:5d8
CpuMap ds MemMap ; 5d8:5e0
OverlayMap ds MemMap ; 5e0:5e8
CurMap ds MemMap ; 5e8:5f0
KCallTbl ds KCallTbl ; 5f0:630
ConfigInfoPtr ds.l 1 ; 630
EDPPtr ds.l 1 ; 634
KernelMemoryBase ds.l 1 ; 638
KernelMemoryEnd ds.l 1 ; 63c
LowMemPtr ds.l 1 ; 640 ; physical address of PAR Low Memory
SharedMemoryAddr ds.l 1 ; 644 ; debug?
EmuKCallTblPtrLogical ds.l 1 ; 648
CodeBase ds.l 1 ; 64c
MRBase ds.l 1 ; 650
ECBPtrLogical ds.l 1 ; 654 ; Emulator/System ContextBlock
ECBPtr ds.l 1 ; 658
ContextPtr ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2
Flags ds.l 1 ; 660 ; moved to EWA (per-CPU) in NKv2
Enables ds.l 1 ; 664 ; moved to EWA (per-CPU) in NKv2
OtherContextDEC ds.l 1 ; 668 ; ticks that the *inactive* context has left out of 1s
PageMapEndPtr ds.l 1 ; 66c ; et at the same time as PageMapStartPtr below
TestIntMaskInit ds.l 1 ; 670
PostIntMaskInit ds.l 1 ; 674 ; CR flags to set when posting an interrupt to the Emulator
ClearIntMaskInit ds.l 1 ; 678 ; CR flags to clear (as mask) when clearing an interrupt
EmuIntLevelPtr ds.l 1 ; 67c ; physical ptr to an Emulator global
DebugIntPtr ds.l 1 ; 680 ; within (debug?) shared memory
PageMapStartPtr ds.l 1 ; 684
PageAttributeInit ds.l 1 ; 688 ; defaults for PLE/PTE?
HtabSingleEA ds.l 1 ; 68c ; PMDT_PTE_Single page most recently put into HTAB
HtabSinglePTE ds.l 1 ; 690 ; and a ptr to its PTE
HtabLastEA ds.l 1 ; 694
HtabLastPTE ds.l 1 ; 698
HtabLastOverflow ds.l 1 ; 69c
PTEGMask ds.l 1 ; 6a0
HTABORG ds.l 1 ; 6a4
VMLogicalPages ds.l 1 ; 6a8 ; size of VM Manager's address space
VMPhysicalPages ds.l 1 ; 6ac ; how many pages VM Manager may use
VMPageArray ds.l 1 ; 6b0 ; array of 68k Page Table Entries
org 0x700
CrashTop
CrashR0 ds.l 1 ; 700
CrashR1 ds.l 1 ; 704
CrashR2 ds.l 1 ; 708
CrashR3 ds.l 1 ; 70c
CrashR4 ds.l 1 ; 710
CrashR5 ds.l 1 ; 714
CrashR6 ds.l 1 ; 718
CrashR7 ds.l 1 ; 71c
CrashR8 ds.l 1 ; 720
CrashR9 ds.l 1 ; 724
CrashR10 ds.l 1 ; 728
CrashR11 ds.l 1 ; 72c
CrashR12 ds.l 1 ; 730
CrashR13 ds.l 1 ; 734
CrashR14 ds.l 1 ; 738
CrashR15 ds.l 1 ; 73c
CrashR16 ds.l 1 ; 740
CrashR17 ds.l 1 ; 744
CrashR18 ds.l 1 ; 748
CrashR19 ds.l 1 ; 74c
CrashR20 ds.l 1 ; 750
CrashR21 ds.l 1 ; 754
CrashR22 ds.l 1 ; 758
CrashR23 ds.l 1 ; 75c
CrashR24 ds.l 1 ; 760
CrashR25 ds.l 1 ; 764
CrashR26 ds.l 1 ; 768
CrashR27 ds.l 1 ; 76c
CrashR28 ds.l 1 ; 770
CrashR29 ds.l 1 ; 774
CrashR30 ds.l 1 ; 778
CrashR31 ds.l 1 ; 77c
CrashCR ds.l 1 ; 780
CrashMQ ds.l 1 ; 784
CrashXER ds.l 1 ; 788
CrashLR ds.l 1 ; 78c
CrashCTR ds.l 1 ; 790
CrashPVR ds.l 1 ; 794
CrashDSISR ds.l 1 ; 798
CrashDAR ds.l 1 ; 79c
CrashRTCU ds.l 1 ; 7a0
CrashRTCL ds.l 1 ; 7a4
CrashDEC ds.l 1 ; 7a8
CrashHID0 ds.l 1 ; 7ac
CrashSDR1 ds.l 1 ; 7b0
CrashSRR0 ds.l 1 ; 7b4
CrashSRR1 ds.l 1 ; 7b8
CrashMSR ds.l 1 ; 7bc
CrashSR0 ds.l 1 ; 7c0
CrashSR1 ds.l 1 ; 7c4
CrashSR2 ds.l 1 ; 7c8
CrashSR3 ds.l 1 ; 7cc
CrashSR4 ds.l 1 ; 7d0
CrashSR5 ds.l 1 ; 7d4
CrashSR6 ds.l 1 ; 7d8
CrashSR7 ds.l 1 ; 7dc
CrashSR8 ds.l 1 ; 7e0
CrashSR9 ds.l 1 ; 7e4
CrashSR10 ds.l 1 ; 7e8
CrashSR11 ds.l 1 ; 7ec
CrashSR12 ds.l 1 ; 7f0
CrashSR13 ds.l 1 ; 7f4
CrashSR14 ds.l 1 ; 7f8
CrashSR15 ds.l 1 ; 7fc
CrashF0 ds.d 1 ; 800
CrashF1 ds.d 1 ; 808
CrashF2 ds.d 1 ; 810
CrashF3 ds.d 1 ; 818
CrashF4 ds.d 1 ; 820
CrashF5 ds.d 1 ; 828
CrashF6 ds.d 1 ; 830
CrashF7 ds.d 1 ; 838
CrashF8 ds.d 1 ; 840
CrashF9 ds.d 1 ; 848
CrashF10 ds.d 1 ; 850
CrashF11 ds.d 1 ; 858
CrashF12 ds.d 1 ; 860
CrashF13 ds.d 1 ; 868
CrashF14 ds.d 1 ; 870
CrashF15 ds.d 1 ; 878
CrashF16 ds.d 1 ; 880
CrashF17 ds.d 1 ; 888
CrashF18 ds.d 1 ; 890
CrashF19 ds.d 1 ; 898
CrashF20 ds.d 1 ; 8a0
CrashF21 ds.d 1 ; 8a8
CrashF22 ds.d 1 ; 8b0
CrashF23 ds.d 1 ; 8b8
CrashF24 ds.d 1 ; 8c0
CrashF25 ds.d 1 ; 8c8
CrashF26 ds.d 1 ; 8d0
CrashF27 ds.d 1 ; 8d8
CrashF28 ds.d 1 ; 8e0
CrashF29 ds.d 1 ; 8e8
CrashF30 ds.d 1 ; 8f0
CrashF31 ds.d 1 ; 8f8
CrashFPSCR ds.l 1 ; 900
CrashKernReturn ds.l 1 ; 904
CrashUnknown1 ds.l 1 ; 908
CrashUnknown2 ds.l 1 ; 90c
CrashBtm
PageMap ds.b 0x1a8 ; 910:ab8
org 0xCC0
SysInfo ds NKSystemInfo ; cc0:d80
DiagInfo ds NKDiagInfo ; d80:e80
NKInfo ds NKNanoKernelInfo ; e80:f80
ProcInfo ds NKProcessorInfo ; f80:fc0
InfoRecBlk ds.b 64 ; fc0:1000 ; Access using ptr equates in InfoRecords
ENDR
########################################################################
KernelState RECORD 0,INCR
Flags ds.l 1 ; 00
Enables ds.l 1 ; 04
Handler ds.d 1 ; 08
HandlerArg ds.d 1 ; 10
HandlerReturn ds.d 1 ; 18
MemRet17 ds.d 1 ; 20 ; MemRetry state
MemRetData ds.d 1 ; 28
MemRet19 ds.d 1 ; 30
MemRet18 ds.d 1 ; 38
ENDR
########################################################################
CB RECORD 0,INCR ; ContextBlock (Emulator/System or Native/Alternate)
InterState ds KernelState ; 000:040 ; for switching between contexts
IntraState ds KernelState ; 040:080 ; for raising/disposing exceptions within a context
FaultSrcPC ds.d 1 ; 080 ; saved when starting an exception handler
FaultSrcLR ds.d 1 ; 088
FaultSrcR3 ds.d 1 ; 090
FaultSrcR4 ds.d 1 ; 098
MSR ds.d 1 ; 0a0
ds.d 1 ; 0a8
ds.d 1 ; 0b0
ds.d 1 ; 0b8
MQ ds.d 1 ; 0c0 ; 601 only
ds.d 1 ; 0c8
XER ds.d 1 ; 0d0
CR ds.d 1 ; 0d8
FPSCR ds.d 1 ; 0e0 ; unsure, mffs/mtfs?
LR ds.d 1 ; 0e8
CTR ds.d 1 ; 0f0
PC ds.d 1 ; 0f8
r0 ds.d 1 ; 100 ; big-endian, so 32-bit value stored in second word
r1 ds.d 1 ; 108
r2 ds.d 1 ; 110
r3 ds.d 1 ; 118
r4 ds.d 1 ; 120
r5 ds.d 1 ; 128
r6 ds.d 1 ; 130
r7 ds.d 1 ; 138
r8 ds.d 1 ; 140
r9 ds.d 1 ; 148
r10 ds.d 1 ; 150
r11 ds.d 1 ; 158
r12 ds.d 1 ; 160
r13 ds.d 1 ; 168
r14 ds.d 1 ; 170
r15 ds.d 1 ; 178
r16 ds.d 1 ; 180
r17 ds.d 1 ; 188
r18 ds.d 1 ; 190
r19 ds.d 1 ; 198
r20 ds.d 1 ; 1a0
r21 ds.d 1 ; 1a8
r22 ds.d 1 ; 1b0
r23 ds.d 1 ; 1b8
r24 ds.d 1 ; 1c0
r25 ds.d 1 ; 1c8
r26 ds.d 1 ; 1d0
r27 ds.d 1 ; 1d8
r28 ds.d 1 ; 1e0
r29 ds.d 1 ; 1e8
r30 ds.d 1 ; 1f0
r31 ds.d 1 ; 1f8
f0 ds.d 1 ; 200
f1 ds.d 1 ; 208
f2 ds.d 1 ; 210
f3 ds.d 1 ; 218
f4 ds.d 1 ; 220
f5 ds.d 1 ; 228
f6 ds.d 1 ; 230
f7 ds.d 1 ; 238
f8 ds.d 1 ; 240
f9 ds.d 1 ; 248
f10 ds.d 1 ; 250
f11 ds.d 1 ; 258
f12 ds.d 1 ; 260
f13 ds.d 1 ; 268
f14 ds.d 1 ; 270
f15 ds.d 1 ; 278
f16 ds.d 1 ; 280
f17 ds.d 1 ; 288
f18 ds.d 1 ; 290
f19 ds.d 1 ; 298
f20 ds.d 1 ; 2a0
f21 ds.d 1 ; 2a8
f22 ds.d 1 ; 2b0
f23 ds.d 1 ; 2b8
f24 ds.d 1 ; 2c0
f25 ds.d 1 ; 2c8
f26 ds.d 1 ; 2d0
f27 ds.d 1 ; 2d8
f28 ds.d 1 ; 2e0
f29 ds.d 1 ; 2e8
f30 ds.d 1 ; 2f0
f31 ds.d 1 ; 2f8
Size equ *
ENDR

36
NanoKernel/NKExceptions.s
View File

@ -34,7 +34,7 @@ MRException
lwz r6, KDP.ContextPtr(r1)
_set r7, r16, bitContextFlagMemRetryErr
_ori r7, r16, ContextFlagMemRetryErr
neg r23, r23
mtcrf crMaskFlags, r7
add r19, r19, r23 ; convert r19 from end address back to start address??
@ -82,12 +82,12 @@ ExceptionCommon
lwz r10, CB.IntraState.Handler+4(r6) ; SRR0 = handler addr
lwz r4, CB.IntraState.HandlerArg+4(r6) ; r4 = arbitrary second argument
lwz r3, KDP.ECBPtrLogical(r1) ; r3 = ContextBlock ptr
bc BO_IF, bitGlobalFlagSystem, @sys
bc BO_IF, bGlobalFlagSystem, @sys
lwz r3, KDP.NCBCacheLA0(r1)
@sys
lwz r12, KDP.EmuKCallTblPtrLogical(r1) ; r12/LR = address of KCallReturnFromException trap
bcl BO_IF, bitContextFlagMemRetryErr, SaveFailingMemRetryState
bcl BO_IF, bContextFlagMemRetryErr, SaveFailingMemRetryState
rlwinm r7, r7, 0, 29, 15 ; unset flags 16-28
stw r8, KDP.Enables(r1)
@ -116,14 +116,14 @@ SaveFailingMemRetryState
########################################################################
_alignToCacheBlock
_align 5
KCallReturnFromExceptionFastPath
lwz r11, KDP.NKInfo.NanoKernelCallCounts(r1)
mr r10, r12
addi r11, r11, 1
stw r11, KDP.NKInfo.NanoKernelCallCounts(r1)
mfsrr1 r11
rlwimi r7, r7, 32+bitMsrSE-bitContextFlagTraceWhenDone, ContextFlagTraceWhenDone
rlwimi r7, r7, 32+bMsrSE-bContextFlagTraceWhenDone, ContextFlagTraceWhenDone
KCallReturnFromException
cmplwi cr1, r3, 1 ; exception handler return value
@ -180,7 +180,7 @@ KCallReturnFromException
lwz r3, CB.FaultSrcR3+4(r6)
lwz r4, CB.FaultSrcR4+4(r6)
bc BO_IF_NOT, bitContextFlagMemRetryErr, RunSystemContext
bc BO_IF_NOT, bContextFlagMemRetryErr, RunSystemContext
stmw r14, KDP.r14(r1) ; When we *do* get back to this context,
lwz r17, CB.IntraState.MemRet17+4(r6) ; make sure MemRetry state can be resumed
lwz r20, CB.IntraState.MemRetData(r6) ; from InterState
@ -261,7 +261,7 @@ RunSystemContext
addi r8, r1, KDP.VecTblSystem ; System VecTbl
mtsprg 3, r8
bcl BO_IF, bitGlobalFlagSystem, SystemCrash ; System Context already running!
bcl BO_IF, bGlobalFlagSystem, SystemCrash ; System Context already running!
; Fallthru (new CB in r9, old CB in r6)
@ -273,7 +273,7 @@ SwitchContext ; OldCB *r6, NewCB *r9
stw r7, CB.InterState.Flags(r6)
stw r8, CB.InterState.Enables(r6)
bc BO_IF_NOT, bitContextFlagMemRetryErr, @can_dispose_mr_state
bc BO_IF_NOT, bContextFlagMemRetryErr, @can_dispose_mr_state
stw r17, CB.InterState.MemRet17+4(r6)
stw r20, CB.InterState.MemRetData(r6)
stw r21, CB.InterState.MemRetData+4(r6)
@ -290,7 +290,7 @@ SwitchContext ; OldCB *r6, NewCB *r9
stw r10, CB.PC+4(r6)
stw r8, CB.CTR+4(r6)
bc BO_IF_NOT, bitGlobalFlagMQReg, @no_mq
bc BO_IF_NOT, bGlobalFlagMQReg, @no_mq
lwz r8, CB.MQ+4(r9)
mfspr r12, mq
mtspr mq, r8
@ -306,7 +306,7 @@ SwitchContext ; OldCB *r6, NewCB *r9
lwz r8, KDP.r6(r1)
stw r5, CB.r5+4(r6)
stw r8, CB.r6+4(r6)
_band. r8, r11, bitMsrFP
andi. r8, r11, MsrFP
stw r14, CB.r14+4(r6)
stw r15, CB.r15+4(r6)
stw r16, CB.r16+4(r6)
@ -409,15 +409,15 @@ ReturnFromInt ; If ContextFlagMemRetryErr && ContextFlagResumeMemRetry, please p
@special_cases
mtcrf crMaskFlags, r7
bc BO_IF_NOT, bitContextFlagMemRetryErr, @no_memretry ; If MemRetry had to be paused for an exception
_clear r7, r7, bitContextFlagMemRetryErr ; which is now finished, finish MemRetry.
bc BO_IF, bitContextFlagResumeMemRetry, @resume_memretry
_clear r7, r7, bitContextFlagTraceWhenDone
bc BO_IF_NOT, bContextFlagMemRetryErr, @no_memretry ; If MemRetry had to be paused for an exception
rlwinm r7, r7, 0, ~ContextFlagMemRetryErr ; which is now finished, finish MemRetry.
bc BO_IF, bContextFlagResumeMemRetry, @resume_memretry
rlwinm r7, r7, 0, ~ContextFlagTraceWhenDone
b @justreturn
@no_memretry
bc BO_IF_NOT, bitContextFlagTraceWhenDone, @justreturn ; If this current interrupt was raised when
_clear r7, r7, bitContextFlagTraceWhenDone ; every instruction should be followed by a
bc BO_IF_NOT, bContextFlagTraceWhenDone, @justreturn ; If this current interrupt was raised when
rlwinm r7, r7, 0, ~ContextFlagTraceWhenDone ; every instruction should be followed by a
stw r7, KDP.Flags(r1) ; Trace exception, then raise one.
li r8, ecInstTrace
b Exception
@ -456,7 +456,7 @@ ReturnFromInt ; If ContextFlagMemRetryErr && ContextFlagResumeMemRetry, please p
lwz r21, KernelState.MemRetData+4(r9) ; we are now switching back to Alternate Context).
lwz r19, KernelState.MemRet19+4(r9)
lwz r18, KernelState.MemRet18+4(r9)
_clear r16, r7, bitContextFlagMemRetryErr
rlwinm r16, r7, 0, ~ContextFlagMemRetryErr
lwz r25, KDP.MRBase(r1) ; MRRestab is indexed by the first arg of MROptab?
extrwi. r22, r17, 4, 27 ;
@ -477,7 +477,7 @@ ReturnFromInt ; If ContextFlagMemRetryErr && ContextFlagResumeMemRetry, please p
mtlr r22
mtsprg 3, r23
mfmsr r14
_set r15, r14, bitMsrDR
_ori r15, r14, MsrDR
mtmsr r15
rlwimi r25, r26, 2, 22, 29 ; Second byte of MRRestab is a secondary routine
bnelr

14
NanoKernel/NKFloatingPt.s
View File

@ -13,7 +13,7 @@
########################################################################
_alignToCacheBlock
_align 5
FPUnavailInt
; Reload the FPU
@ -25,11 +25,11 @@ FPUnavailInt
stw r11, KDP.NKInfo.FPUReloadCount(r1)
mfsrr1 r11
_set r11, r11, bitMsrFP
_ori r11, r11, MsrFP
mtsrr1 r11
mfmsr r11 ; need this to access float registers
_set r11, r11, bitMsrFP
_ori r11, r11, MsrFP
lwz r6, KDP.ContextPtr(r1)
mtmsr r11
@ -55,11 +55,11 @@ ReloadFPU
rlwinm. r8, r8, 1, 0, 0
mfmsr r8
_set r8, r8, bitMsrFP
_ori r8, r8, MsrFP
beqlr
mtmsr r8
_set r11, r11, bitMsrFP
_ori r11, r11, MsrFP
########################################################################
@ -105,10 +105,10 @@ LoadFloats
DisableFPU
mfmsr r8
_set r8, r8, bitMsrFP
_ori r8, r8, MsrFP
mtmsr r8
_clear r11, r11, bitMsrFP
rlwinm r11, r11, 0, ~MsrFP
stfd f0, CB.f0(r6)
stfd f1, CB.f1(r6)

12
NanoKernel/NKHotInts.s
View File

@ -27,7 +27,7 @@ ExternalInt0
mfmsr r2 ; Save a self-ptr to FF880000... why?
lis r3, 0xFF88
_set r0, r2, bitMsrDR
_ori r0, r2, MsrDR
stw r4, KDP.r4(r1)
stw r5, KDP.r5(r1)
mfsrr0 r4
@ -94,7 +94,7 @@ ExternalInt1
lis r2, 0x50F3 ; Query OpenPIC at 50F2A000
mfmsr r3
_set r0, r3, bitMsrDR
_ori r0, r3, MsrDR
stw r4, KDP.r4(r1)
stw r5, KDP.r5(r1)
mfsrr0 r4
@ -152,7 +152,7 @@ ExternalInt2
lis r2, 0xF300 ; Query OpenPIC at F3000028/C
mfmsr r0
_set r3, r0, bitMsrDR
_ori r3, r0, MsrDR
stw r4, KDP.r4(r1)
stw r5, KDP.r5(r1)
mfsrr0 r4
@ -288,7 +288,7 @@ DataStorageInt
mfcr r13
mfmsr r14
_set r15, r14, bitMsrDR
_ori r15, r14, MsrDR
mtmsr r15
lwz r27, 0(r10) ; r27 = INSTRUCTION
mtmsr r14
@ -372,7 +372,7 @@ AlignmentInt
mfmsr r14
rlwimi r25, r26, 26, 22, 29 ; third byte of lookup value is a /4 code offset in FDP
mtlr r25 ; so get ready to go there
_set r15, r14, bitMsrDR
_ori r15, r14, MsrDR
mtcr r26
rlwimi r17, r26, 6, 26, 5 ; wrap some shite around the register values
blr
@ -382,7 +382,7 @@ AlignmentInt
mfmsr r14
rlwimi r25, r26, 26, 22, 29
mtlr r25
_set r15, r14, bitMsrDR
_ori r15, r14, MsrDR
mtcr r26
rlwimi r17, r26, 6, 26, 5
bclr BO_IF_NOT, mrOpflag1

4
NanoKernel/NKInit.s
View File

@ -233,7 +233,7 @@ InitInfoRecords
addi r12, r11, KDP.NKInfo
stw r12, NKNanoKernelInfoPtr & 0xFFF(r1)
li r12, kNanoKernelVersion
li r12, kVersion
sth r12, NKNanoKernelInfoVer & 0xFFF(r1)
li r12, NKNanoKernelInfo.Size
sth r12, NKNanoKernelInfoLen & 0xFFF(r1)
@ -400,7 +400,7 @@ InitEmulator
cmpwi r7, 1
lis r7, GlobalFlagSystem >> 16 ; we will enter System Context (all CPUs)
bne @not_601
_set r7, r7, bitGlobalFlagMQReg ; but only 601 has MQ register
_ori r7, r7, GlobalFlagMQReg ; but only 601 has MQ register
@not_601
stw r7, KDP.Flags(r1)

447
NanoKernel/NKLegacyVM.s
View File

@ -11,6 +11,18 @@
; This file is a horrible mess. It needs a do-over.
ispaged equ cr4_lt
;r4=pg, r9=areapgcnt // cr[16]=ispaged, r16/r15/cr[20-31]=68kPTE/ptr/attrs, r8/r9/r14=PTE-hi/lo/ptr
; Registers used throughout: (maybe we'll just call these "conventions")
vmrMisc1 equ r8
vmrMisc2 equ r9
vmrPtePtr equ r14
vmr68PtePtr equ r15
vmr68Pte equ r16
########################################################################
KCallVMDispatch
@ -29,7 +41,7 @@ KCallVMDispatch
stw r16, KDP.r16(r1)
bltlr
b vmReturnMinus1
b vmRetNeg1
VMTab ; Placeholders indented
MACRO
@ -38,22 +50,25 @@ VMTab ; Placeholders indented
ENDM
vmtabLine VMInit ; 0 VMInit: init the MMU virtual space
vmtabLine vmReturn ; 1 VMUnInit: un-init the MMU virtual space
vmtabLine vmReturn ; 2 VMFinalInit: last chance to init after new memory dispatch is installed
vmtabLine vmRet ; 1 VMUnInit: un-init the MMU virtual space
vmtabLine vmRet ; 2 VMFinalInit: last chance to init after new memory dispatch is installed
vmtabLine VMIsResident ; 3 VMIsResident: ask about page status
vmtabLine VMIsUnmodified ; 4 VMIsUnmodified: ask about page status
vmtabLine VMIsInited ; 5 VMIsInited: ask about page status
vmtabLine VMShouldClean ; 6 VMShouldClean: ask about page status
vmtabLine VMMarkResident ; 7 VMMarkResident: set page status
vmtabLine VMMarkResident ; 7 VMMarkResident: set page status
vmtabLine VMMarkBacking ; 8 VMMarkBacking: set page status
vmtabLine VMMarkCleanUnused ; 9 VMMarkCleanUnused: set page status
vmtabLine VMGetPhysicalPage ; 10 VMGetPhysicalPage: return phys page given log page
vmtabLine vmReturnMinus1 ; 11 VMGetPhysicalAddress: return phys address given log page (can be different from above!)
vmtabLine vmRetNeg1 ; 11 VMGetPhysicalAddress: return phys address given log page (can be different from above!)
vmtabLine VMExchangePages ; 12 VMExchangePages: exchange physical page contents
vmtabLine vmReturn ; 13 VMReload: reload the ATC with specified page
vmtabLine vmReturn ; 14 VMFlushAddressTranslationCache: just do it
vmtabLine vmReturn ; 15 VMFlushDataCache: wack the data cache
vmtabLine vmReturn ; 16 VMFlushCodeCache: wack the code cache
vmtabLine vmRet ; 13 VMReload: reload the ATC with specified page
vmtabLine vmRet ; 14 VMFlushAddressTranslationCache: just do it
vmtabLine vmRet ; 15 VMFlushDataCache: wack the data cache
vmtabLine vmRet ; 16 VMFlushCodeCache: wack the code cache
vmtabLine VMMakePageCacheable ; 17 VMMakePageCacheable: make it so...
vmtabLine VMMakePageNonCacheable ; 18 VMMakePageNonCacheable: make it so...
vmtabLine getPTEntryGivenPage ; 19 getPTEntryGivenPage: given a page, get its 68K PTE
@ -66,15 +81,15 @@ VMTab ; Placeholders indented
########################################################################
vmReturnMinus1
vmRetNeg1
li r3, -1
b vmReturn
vmNoErr
b vmRet
vmRet0
li r3, 0
b vmReturn
vmReturn1
b vmRet
vmRet1
li r3, 1
vmReturn
vmRet
lwz r14, KDP.r14(r1)
lwz r15, KDP.r15(r1)
lwz r16, KDP.r16(r1)
@ -85,14 +100,14 @@ vmReturn
########################################################################
VMInit
lwz r7, KDP.PageListPtr(r1) ; check that zero seg isn't empty
lwz r7, KDP.VMPageArray(r1) ; check that zero seg isn't empty
lwz r8, KDP.PARPerSegmentPLEPtrs + 0(r1)
cmpw r7, r8
bne vmReturn1
bne vmRet1
stw r4, KDP.VMLogicalPages(r1) ; resize PAR
stw r5, KDP.PageListPtr(r1) ; where did NK find this???
stw r5, KDP.VMPageArray(r1) ; where did NK find this???
lwz r6, KDP.CurMap.SegMapPtr(r1)
li r5, 0x00
@ -155,10 +170,10 @@ VMInit_0x110
lwz r7, KDP.TotalPhysicalPages(r1)
lwz r7, KDP.VMPhysicalPages(r1)
cmpw r4, r7
bnel SystemCrash
lwz r5, KDP.PageListPtr(r1)
lwz r5, KDP.VMPageArray(r1)
lwz r4, KDP.VMLogicalPages(r1)
andi. r7, r5, 0xfff
@ -175,7 +190,7 @@ VMInit_0x110
srwi r6, r7, 10
srwi r8, r5, 12
add r8, r8, r6
lwz r9, KDP.TotalPhysicalPages(r1)
lwz r9, KDP.VMPhysicalPages(r1)
cmplw r8, r9
li r3, 0x04
@ -188,7 +203,7 @@ VMInit_0x110
srwi r7, r5, 12
bl major_0x09c9c
stw r9, KDP.PageListPtr(r1)
stw r9, KDP.VMPageArray(r1)
mr r15, r9
srwi r7, r5, 12
add r7, r7, r6
@ -213,7 +228,7 @@ VMInit_0x1d4
cmpwi r7, 0x00
stwx r8, r15, r7
bne VMInit_0x1d4
lwz r7, KDP.TotalPhysicalPages(r1)
lwz r7, KDP.VMPhysicalPages(r1)
slwi r6, r7, 2
VMInit_0x1ec
@ -224,7 +239,7 @@ VMInit_0x1ec
ori r16, r9, 0x21
stwx r16, r15, r6
bne VMInit_0x1ec
lwz r15, KDP.PageListPtr(r1)
lwz r15, KDP.VMPageArray(r1)
srwi r7, r5, 10
add r15, r15, r7
lwz r5, KDP.VMLogicalPages(r1)
@ -256,7 +271,7 @@ VMInit_0x250
ble VMInit_0x250
lwz r6, KDP.CurMap.SegMapPtr(r1)
lwz r9, KDP.VMLogicalPages(r1)
lwz r15, KDP.PageListPtr(r1)
lwz r15, KDP.VMPageArray(r1)
VMInit_0x288
lwz r8, 0x0000(r6)
@ -276,164 +291,176 @@ VMInit_0x29c
addi r6, r6, 0x08
bne VMInit_0x288
b vmNoErr
b vmRet0
VMInit_Fail
lwz r7, KDP.TotalPhysicalPages(r1)
lwz r7, KDP.VMPhysicalPages(r1)
lwz r8, KDP.PARPerSegmentPLEPtrs + 0(r1)
stw r7, KDP.VMLogicalPages(r1)
stw r8, KDP.PageListPtr(r1)
stw r8, KDP.VMPageArray(r1)
b vmReturn
b vmRet
########################################################################
VMExchangePages
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bc BO_IF_NOT, 16, vmReturnMinus1
bc BO_IF, 21, vmReturnMinus1
bc BO_IF_NOT, 31, vmReturnMinus1
bc BO_IF, 25, vmReturnMinus1
bc BO_IF_NOT, 26, vmReturnMinus1
bcl BO_IF, 20, RemovePTEFromHTAB
mr r6, r15
mr r4, r5
mr r5, r16
lwz r9, KDP.VMLogicalPages(r1)
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bc BO_IF_NOT, 16, vmReturnMinus1
bc BO_IF, 21, vmReturnMinus1
bc BO_IF_NOT, 31, vmReturnMinus1
bc BO_IF, 25, vmReturnMinus1
bc BO_IF_NOT, 26, vmReturnMinus1
bcl BO_IF, 20, RemovePTEFromHTAB
stw r5, 0x0000(r15)
stw r16, 0x0000(r6)
rlwinm r4, r5, 0, 0, 19
rlwinm r5, r16, 0, 0, 19
li r9, 0x1000
li r6, 0x04
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1 ; must be in pageable area
bc BO_IF, 21, vmRetNeg1
bc BO_IF_NOT, bM68pteResident, vmRetNeg1 ; must be resident
bc BO_IF, bM68pteInhibcache, vmRetNeg1 ; must not have special properties
bc BO_IF_NOT, bM68pteNonwritethru, vmRetNeg1
bcl BO_IF, M68pteInHTAB, RemovePTEFromHTAB ; if in HTAB, must be removed
mr r6, r15 ; r6 = src 68k PTE ptr
VMExchangePages_0x68
mr r4, r5
mr r5, r16 ; r5 = src 68k PTE
lwz r9, KDP.VMLogicalPages(r1)
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1
bc BO_IF, 21, vmRetNeg1
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
bc BO_IF, bM68pteInhibcache, vmRetNeg1
bc BO_IF_NOT, bM68pteNonwritethru, vmRetNeg1
bcl BO_IF, M68pteInHTAB, RemovePTEFromHTAB
stw r5, 0(r15) ; swap 68k PTEs (in that big flat list)
stw r16, 0(r6)
rlwinm r4, r5, 0, 0xFFFFF000 ; get clean physical ptrs to both pages
rlwinm r5, r16, 0, 0xFFFFF000
li r9, 0x1000
li r6, 4
@copyloop
subf. r9, r6, r9
lwzx r7, r4, r9
lwzx r8, r5, r9
stwx r7, r5, r9
stwx r8, r4, r9
bne VMExchangePages_0x68
b vmReturn
bne @copyloop
b vmRet
########################################################################
VMGetPhysicalPage
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bc BO_IF_NOT, 31, vmReturnMinus1
bl PageInfo
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
srwi r3, r9, 12
b vmReturn
b vmRet
########################################################################
getPTEntryGivenPage
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bl PageInfo
mr r3, r16
bc BO_IF_NOT, 31, vmReturn
rlwimi r3, r9, 0, 0, 19
b vmReturn
bc BO_IF_NOT, bM68pteResident, vmRet
rlwimi r3, r9, 0, 0xFFFFF000
b vmRet
########################################################################
VMIsInited
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bc BO_IF, 31, vmReturn1
bl PageInfo
bc BO_IF, bM68pteResident, vmRet1
rlwinm r3, r16, 16, 31, 31
b vmReturn
b vmRet
########################################################################
VMIsResident
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
clrlwi r3, r16, 0x1f
b vmReturn
bl PageInfo
rlwinm r3, r16, 0, 1 ; M68pteResident
b vmRet
########################################################################
VMIsUnmodified
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
rlwinm r3, r16, 28, 31, 31
xori r3, r3, 0x01
b vmReturn
bl PageInfo
rlwinm r3, r16, bM68pteModified + 1, 1
xori r3, r3, 1
b vmRet
########################################################################
VMLRU
rlwinm. r9, r9, 2, 0, 29
lwz r15, KDP.PageListPtr(r1)
VMLRU ; For each resident page: save Update bit and clear original
slwi r9, r9, 2 ; (r9 is VMLogicalPages)
lwz r15, KDP.VMPageArray(r1)
lwz r14, KDP.HTABORG(r1)
add r15, r15, r9
srwi r4, r9, 2
li r5, 0x100
li r6, 0x08
add r15, r15, r9 ; r15 = loop PageArray ptr
srwi r4, r9, 2 ; r4 = loop counter
VMLRU_0x1c
lwzu r16, -0x0004(r15)
addi r4, r4, -0x01
mtcr r16
cmpwi r4, 0x00
rlwinm r7, r16, 23, 9, 28
bc BO_IF_NOT, 31, VMLRU_0x5c
bc BO_IF_NOT, 20, VMLRU_0x50
add r14, r14, r7
lwz r9, 4(r14)
rlwimi r16, r9, 27, 28, 28
li r5, LpteReference ; for clearing bits with andc
li r6, M68pteUpdate
@loop ; over every logical page
lwzu r16, -4(r15)
subi r4, r4, 1
mtcr r16
cmpwi r4, 0
rlwinm r7, r16, 23, 7FFFFFF8 ; r7 = offset of PPC PTE (if any)
bc BO_IF_NOT, bM68pteResident, @nonresident
bc BO_IF_NOT, bM68pteInHTAB, @not_in_htab
add r14, r14, r7 ; If PPC PTE in HTAB, copy its Ref
lwz r9, 4(r14) ; bit back to 68k PTE and clear
_mvbit r16, bM68pteUpdate, r9, bLpteReference
andc r9, r9, r5
bl EditPTEOnlyInHTAB
bl ChangeNativeLowerPTE
subf r14, r7, r14
@not_in_htab
VMLRU_0x50
rlwimi r16, r16, 6, 22, 22
andc r16, r16, r6
stw r16, 0x0000(r15)
_mvbit r16, bM68pteSavedUpdate, r16, bM68pteUpdate
andc r16, r16, r6 ; save Update and clear original
stw r16, 0(r15) ; save changed 68k PTE
@nonresident
VMLRU_0x5c
bne VMLRU_0x1c
b vmReturn
bne @loop
b vmRet
########################################################################
VMMakePageCacheable
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
rlwinm r7, r16, 0, 25, 26
cmpwi r7, 0x20
bc BO_IF_NOT, 31, vmReturnMinus1
beq vmReturn
bc BO_IF_NOT, 16, vmReturnMinus1
bcl BO_IF_NOT, 20, VMSecondLastExportedFunc
rlwinm r16, r16, 0, 27, 24
rlwinm r9, r9, 0, 27, 24
ori r16, r16, 0x20
bl EditPTEInHTAB
b vmReturn
; PPC: W=0, I=0
; 68k: Nonwritethru=0, Inhibcache=0
bl PageInfo
rlwinm r7, r16, 0, M68pteInhibcache | M68pteNonwritethru
cmpwi r7, M68pteNonwritethru
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
beq vmRet
bc BO_IF_NOT, ispaged, vmRetNeg1
bcl BO_IF_NOT, M68pteInHTAB, VMSecondLastExportedFunc
rlwinm r16, r16, 0, ~(M68pteInhibcache | M68pteNonwritethru)
rlwinm r9, r9, 0, ~(LpteWritethru | LpteInhibcache)
ori r16, r16, M68pteNonwritethru
bl ChangeNativeAnd68kPTEs
b vmRet
########################################################################
VMMakePageWriteThrough
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bl PageInfo
rlwinm. r7, r16, 0, 25, 26
bc BO_IF_NOT, 31, vmReturnMinus1
beq vmReturn
bc BO_IF_NOT, 16, VMMakePageWriteThrough_0x3c
bcl BO_IF_NOT, 20, VMSecondLastExportedFunc
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
beq vmRet
bc BO_IF_NOT, ispaged, VMMakePageWriteThrough_0x3c
bcl BO_IF_NOT, M68pteInHTAB, VMSecondLastExportedFunc
rlwinm r16, r16, 0, 27, 24
rlwinm r9, r9, 0, 27, 24
ori r9, r9, 0x40
bl EditPTEInHTAB
bl ChangeNativeAnd68kPTEs
b VMMakePageNonCacheable_0x3c
VMMakePageWriteThrough_0x3c
rlwinm r7, r4, 16, 28, 31
cmpwi r7, 0x09
blt vmReturnMinus1
bc BO_IF_NOT, 25, vmReturnMinus1
blt vmRetNeg1
bc BO_IF_NOT, M68pteInhibcache, vmRetNeg1
lwz r5, 0x000c(r15)
andi. r6, r5, 0xe01
cmpwi r6, 0xa01
@ -443,12 +470,12 @@ VMMakePageWriteThrough_0x3c
lhz r6, 0x0000(r15)
andi. r5, r5, 0xc00
lhz r5, 0x0002(r15)
bne vmReturnMinus1
bne vmRetNeg1
addi r5, r5, 0x01
add r6, r6, r5
xor r6, r6, r4
andi. r6, r6, 0xffff
bne vmReturnMinus1
bne vmRetNeg1
sth r5, 0x0002(r15)
b PageSetCommon
@ -514,7 +541,7 @@ PageSetCommon_0x2c
and r15, r15, r7
xori r8, r8, 0x40
bne PageSetCommon_0x2c
b vmReturn
b vmRet
PageSetCommon_0xbc
addi r14, r14, 0x08
@ -529,23 +556,23 @@ PageSetCommon_0xc8
; bl RemovePageFromTLB
li r8, 0x00
li r9, 0x00
bl EditLowerPTEOnlyInHTAB
b vmReturn
bl ChangeNativePTE
b vmRet
########################################################################
VMMakePageNonCacheable
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bl PageInfo
rlwinm r7, r16, 0, 25, 26
cmpwi r7, 0x60
bc BO_IF_NOT, 31, vmReturnMinus1
beq vmReturn
bc BO_IF_NOT, 16, vmReturnMinus1
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
beq vmRet
bc BO_IF_NOT, ispaged, vmRetNeg1
bl BO_IF_NOT, 20, VMSecondLastExportedFunc
rlwinm r9, r9, 0, 27, 24
ori r16, r16, 0x60
ori r9, r9, 0x20
bl EditPTEInHTAB
bl ChangeNativeAnd68kPTEs
VMMakePageNonCacheable_0x3c
rlwinm r4, r9, 0, 0, 19
@ -558,33 +585,33 @@ VMMakePageNonCacheable_0x50
dcbf r7, r4
dcbf r7, r5
bne VMMakePageNonCacheable_0x50
b vmReturn
b vmRet
########################################################################
VMMarkBacking
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bc BO_IF_NOT, 16, vmReturnMinus1
bc BO_IF, 21, vmReturnMinus1
bcl BO_IF, 20, RemovePTEFromHTAB
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1
bc BO_IF, 21, vmRetNeg1
bcl BO_IF, M68pteInHTAB, RemovePTEFromHTAB
rlwimi r16, r5, 16, 15, 15
li r7, 0x01
andc r16, r16, r7
stw r16, 0x0000(r15)
b vmReturn
b vmRet
########################################################################
VMMarkCleanUnused
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bc BO_IF_NOT, 16, vmReturnMinus1
bc BO_IF_NOT, 31, vmReturnMinus1
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
bl BO_IF_NOT, 20, VMSecondLastExportedFunc
li r7, 0x180
andc r9, r9, r7
ori r16, r16, 0x100
bl EditPTEInHTAB
b vmReturn
bl ChangeNativeAnd68kPTEs
b vmRet
########################################################################
@ -593,10 +620,10 @@ VMMarkUndefined
cmplw cr1, r5, r9
add r7, r4, r5
cmplw cr2, r7, r9
bge vmReturnMinus1
bgt cr1, vmReturnMinus1
bgt cr2, vmReturnMinus1
lwz r15, KDP.PageListPtr(r1)
bge vmRetNeg1
bgt cr1, vmRetNeg1
bgt cr2, vmRetNeg1
lwz r15, KDP.VMPageArray(r1)
slwi r8, r7, 2
li r7, 0x01
@ -604,7 +631,7 @@ VMMarkUndefined_0x28
subi r8, r8, 4
subf. r5, r7, r5
lwzx r16, r15, r8
blt vmReturn
blt vmRet
rlwimi r16, r6, 7, 24, 24
stwx r16, r15, r8
b VMMarkUndefined_0x28
@ -612,16 +639,16 @@ VMMarkUndefined_0x28
########################################################################
VMMarkResident
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bc BO_IF_NOT, 16, vmReturnMinus1
bc BO_IF, 31, vmReturnMinus1
bcl BO_IF, 20, SystemCrash
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1
bc BO_IF, bM68pteResident, vmRetNeg1
bcl BO_IF, M68pteInHTAB, SystemCrash
rlwimi r16, r5, 12, 0, 19
ori r16, r16, 0x01
stw r16, 0x0000(r15)
bl VMSecondLastExportedFunc
bl EditPTEInHTAB
b vmReturn
bl ChangeNativeAnd68kPTEs
b vmRet
########################################################################
@ -629,78 +656,78 @@ VMPTest
srwi r4, r4, 12
cmplw r4, r9
li r3, 0x4000
bge vmReturn
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bge vmRet
bl PageInfo
li r3, 0x400
bc BO_IF_NOT, 31, vmReturn
bc BO_IF_NOT, bM68pteResident, vmRet
li r3, 0x00
ori r3, r3, 0x8000
bc BO_IF_NOT, 29, vmReturn
bc BO_IF_NOT, bM68pteWriteProtect, vmRet
cmpwi r6, 0x00
beq vmReturn
beq vmRet
li r3, 0x800
b vmReturn
b vmRet
########################################################################
setPTEntryGivenPage
mr r6, r4
mr r4, r5
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bc BO_IF_NOT, 16, vmReturnMinus1
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1
xor r7, r16, r6
li r3, 0x461
rlwimi r3, r16, 24, 29, 29
and. r3, r3, r7
bne vmReturnMinus1
bne vmRetNeg1
andi. r7, r7, 0x11c
xor r16, r16, r7
stw r16, 0x0000(r15)
bc BO_IF_NOT, 20, vmReturn
bc BO_IF_NOT, bM68pteInHTAB, vmRet
rlwimi r9, r16, 5, 23, 23
rlwimi r9, r16, 3, 24, 24
rlwimi r9, r16, 30, 31, 31
bl EditPTEOnlyInHTAB
b vmReturn
bl ChangeNativeLowerPTE
b vmRet
########################################################################
VMShouldClean
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bc BO_IF_NOT, 31, vmNoErr
bc BO_IF, 28, vmNoErr
bc BO_IF_NOT, 27, vmNoErr
bc BO_IF_NOT, 16, vmReturnMinus1
bl PageInfo
bc BO_IF_NOT, bM68pteResident, vmRet0
bc BO_IF, bM68pteUpdate, vmRet0
bc BO_IF_NOT, bM68pteModified, vmRet0
bc BO_IF_NOT, ispaged, vmRetNeg1
xori r16, r16, 0x10
ori r16, r16, 0x100
stw r16, 0x0000(r15)
bc BO_IF_NOT, 20, vmReturn1
bc BO_IF_NOT, bM68pteInHTAB, vmRet1
xori r9, r9, 0x80
bl EditPTEOnlyInHTAB
b vmReturn1
bl ChangeNativeLowerPTE
b vmRet1
########################################################################
VMAllocateMemory
lwz r7, KDP.PageListPtr(r1)
lwz r7, KDP.VMPageArray(r1)
lwz r8, KDP.PARPerSegmentPLEPtrs + 0(r1)
cmpwi cr6, r5, 0x00
cmpw cr7, r7, r8
or r7, r4, r6
rlwinm. r7, r7, 0, 0, 11
bc BO_IF_NOT, 25, vmReturnMinus1
bc BO_IF_NOT, M68pteInhibcache, vmRetNeg1
lwz r9, KDP.VMLogicalPages(r1)
bne cr7, vmReturnMinus1
bne cr7, vmRetNeg1
mr r7, r4
bne vmReturnMinus1
bne vmRetNeg1
mr r4, r9
slwi r6, r6, 12
addi r5, r5, -0x01
VMAllocateMemory_0x74
addi r4, r4, -0x01
bl PageInfo ; pgidx r4, pgcnt r9 // flags CR, PTE r9/r9, PLE r16, PTE *r14, PLE *r15
bcl BO_IF, 20, RemovePTEFromHTAB
bl PageInfo
bcl BO_IF, M68pteInHTAB, RemovePTEFromHTAB
lwz r9, KDP.VMLogicalPages(r1)
subf r8, r4, r9
cmplw cr7, r5, r8
@ -721,8 +748,8 @@ VMAllocateMemory_0xc0
lis r9, 4
cmplw cr7, r7, r9
rlwinm. r9, r7, 0, 0, 11
bge cr7, vmReturnMinus1
bne vmReturnMinus1
bge cr7, vmRetNeg1
bne vmRetNeg1
lwz r14, KDP.CurMap.SegMapPtr(r1)
rlwinm r9, r7, 19, 25, 28
lwzx r14, r14, r9
@ -740,29 +767,29 @@ VMAllocateMemory_0xf4
ble cr7, VMAllocateMemory_0xf0
add r8, r8, r5
cmplw cr7, r8, r16
ble cr7, vmReturnMinus1
ble cr7, vmRetNeg1
lwz r16, 0x0004(r14)
slwi r8, r7, 16
andi. r16, r16, 0xe01
cmpwi r16, 0xa01
or r8, r8, r5
addi r5, r5, 0x01
bne vmReturnMinus1
bne vmRetNeg1
stw r8, 0x0000(r14)
bnel cr6, VMAllocateMemory_0x2e8
rotlwi r15, r15, 0x0a
ori r15, r15, 0xc00
stw r15, 0x0004(r14)
lwz r7, KDP.TotalPhysicalPages(r1)
lwz r7, KDP.VMPhysicalPages(r1)
subf r7, r5, r7
stw r7, KDP.TotalPhysicalPages(r1)
stw r7, KDP.VMPhysicalPages(r1)
stw r7, KDP.VMLogicalPages(r1)
slwi r8, r7, 12
stw r8, KDP.SysInfo.UsableMemorySize(r1)
stw r8, KDP.SysInfo.LogicalMemorySize(r1)
addi r14, r1, 120
lwz r15, KDP.PageListPtr(r1)
lwz r15, KDP.VMPageArray(r1)
li r8, 0
addi r7, r7, -0x01
ori r8, r8, 0xffff
@ -778,14 +805,14 @@ VMAllocateMemory_0x34c
addis r7, r7, -0x01
bgt VMAllocateMemory_0x34c
sth r7, 0x0002(r16)
b vmReturn1
b vmRet1
VMAllocateMemory_0x2e8
lwz r16, 0x0000(r15)
lwz r7, KDP.TotalPhysicalPages(r1)
lwz r8, KDP.PageListPtr(r1)
lwz r7, KDP.VMPhysicalPages(r1)
lwz r8, KDP.VMPageArray(r1)
slwi r7, r7, 2
add r7, r7, r8
slwi r8, r5, 2
@ -817,9 +844,9 @@ VMAllocateMemory_0x324
; residence is determined by bit 20 (value 0x800) of the PTE. This is
; often checked by a bltl cr5
PageInfo ; pgidx r4, pgcnt r9 // flags CR (20-31), PTE r8/r9, PLE r16, PTE *r14, PLE *r15
PageInfo ; r4=pg, r9=areapgcnt // cr[16]=ispaged, r16/r15/cr[20-31]=68kPTE/ptr/attrs, r8/r9/r14=PTE-hi/lo/ptr
cmplw cr4, r4, r9
lwz r15, KDP.PageListPtr(r1) ; r15 = Page List base
lwz r15, KDP.VMPageArray(r1) ; r15 = Page List base
slwi r8, r4, 2 ; r18 = Page List Entry offset
bge cr4, @not_par
@ -829,8 +856,8 @@ PageInfo ; pgidx r4, pgcnt r9 // flags CR (20-31), PTE r8/r9, PLE r16, PTE *r14,
mtcrf %00000111, r16 ; Set all flags in CR (but not RealPgNum)
rlwinm r8, r16, 23, 9, 28 ; r8 = Page Table Entry offset
rlwinm r9, r16, 0, 0, 19
bclr BO_IF_NOT, 20 ; Page not in Page Table, so return the Page List Entry.
bc BO_IF_NOT, 31, SystemCrash ; panic if the PTE is in the HTAB but isn't mapped to a real page??
bclr BO_IF_NOT, bM68pteInHTAB ; Page not in Page Table, so return the Page List Entry.
bc BO_IF_NOT, bM68pteResident, SystemCrash ; panic if the PTE is in the HTAB but isn't mapped to a real page??
lwzux r8, r14, r8 ; r8/r9 = PTE
lwz r9, 4(r14)
@ -845,8 +872,8 @@ PageInfo ; pgidx r4, pgcnt r9 // flags CR (20-31), PTE r8/r9, PLE r16, PTE *r14,
lis r9, 4 ; Check that page is outside VM Manager's 0-1GB area but
cmplw cr4, r4, r9 ; still a valid page number (i.e. under 0x100000)
rlwinm. r9, r4, 0, 0xFFF00000
blt cr4, vmReturnMinus1 ; (Else return -1)
bne vmReturnMinus1
blt cr4, vmRetNeg1 ; (Else return -1)
bne vmRetNeg1
lwz r15, KDP.CurMap.SegMapPtr(r1) ; r15 = Segment Map base
rlwinm r9, r4, 19, 25, 28 ; r9 = offset into Segment Map = segment number * 8
@ -863,13 +890,13 @@ PageInfo ; pgidx r4, pgcnt r9 // flags CR (20-31), PTE r8/r9, PLE r16, PTE *r14,
cmplw cr4, r8, r16
bgt cr4, @pmloop ; Nope, not this entry
lwz r9, PMDT.RPN(r15)
andi. r16, r9, Pflag_NotPTE | Pflag_PTE_Single
cmpwi cr6, r16, Pflag_PTE_Single
cmpwi cr7, r16, Pflag_NotPTE | Pflag_PTE_Single
lwz r9, PMDT.Word2(r15)
andi. r16, r9, Pattr_NotPTE | Pattr_PTE_Single
cmpwi cr6, r16, Pattr_PTE_Single
cmpwi cr7, r16, Pattr_NotPTE | Pattr_PTE_Single
beq @range
beq cr6, @single
bne cr7, vmReturnMinus1
bne cr7, vmRetNeg1
slwi r8, r8, 2
rlwinm r15, r9, 22, 0, 29
@ -902,23 +929,23 @@ PageInfo ; pgidx r4, pgcnt r9 // flags CR (20-31), PTE r8/r9, PLE r16, PTE *r14,
;r8 is lower word of HTAB entry
;r9 is upper word of HTAB entry
;r14 is address of HTAB entry
EditPTEInHTAB
stw r16, 0x0000(r15)
;just updates HTAB entry
EditLowerPTEOnlyInHTAB
stw r8, 0x0000(r14)
EditPTEOnlyInHTAB
stw r9, 0x0004(r14);upper word of HTAB entry contains valid bit
ChangeNativeAnd68kPTEs
stw r16, 0(r15)
ChangeNativePTE
stw r8, 0(r14)
ChangeNativeLowerPTE
stw r9, 4(r14) ;upper word of HTAB entry contains valid bit
slwi r8, r4, 12
sync
tlbie r8
sync
blr
########################################################################
;Removes a page from the HTAB.
;Called right after PageInfo, with either a bl or a bltl cr5
;
;also updates NK statistics?
;r9 is low word of HTAB entry
@ -932,11 +959,11 @@ RemovePTEFromHTAB
stw r8, KDP.NKInfo.HashTableDeleteCount(r1)
rlwimi r16, r9, 0, 0, 19 ;move page# back into PTE
_InvalNCBPointerCache scratch=r8
_clrNCBCache scr=r8
li r8, 0x00 ;0 upper HTAB word
li r9, 0x00 ;0 lower HTAB word
b EditPTEInHTAB ;update stored PTE and invalidate HTAB entry
b ChangeNativeAnd68kPTEs ;update stored PTE and invalidate HTAB entry
########################################################################
@ -1029,12 +1056,12 @@ VMLastExportedFunc_0xd7
major_0x09c9c
addi r8, r1, KDP.PARPerSegmentPLEPtrs
lwz r9, KDP.TotalPhysicalPages(r1)
lwz r9, KDP.VMPhysicalPages(r1)
rlwimi r8, r7, 18, 28, 29
cmplw r7, r9
lwz r8, 0x0000(r8)
rlwinm r7, r7, 2, 14, 29
bge vmReturnMinus1
bge vmRetNeg1
lwzx r9, r8, r7
rlwinm r9, r9, 0, 0, 19
blr

372
NanoKernel/NKMacros.s
View File

@ -1,330 +1,13 @@
MACRO
_log &s
BL @paststring
STRING AsIs
DC.B &s, 0, 0
ALIGN 2
@paststring
mflr r8
BL PrintS
_bitequate &bitnum, &name ; _bitequate 16, MyLabel => MyLabel=0x00008000, bMyLabel=16
&name equ 1 << (31-&bitnum)
b&name equ &bitnum
ENDM
; Cool macro for one-line debug calls
MACRO
_wlog &s1, &reg, &s2, &scratch==r8
if &TYPE('ExtraNKLogging') != 'UNDEFINED'
mr &scratch, r8
_log &s1
_log '[ '
mr r8, &reg
bl PrintW
_log ']'
_log &s2
mr r8, &scratch
endif
ENDM
########################################################################
MACRO
_wlogh &s1, &reg, &s2, &scratch==r8
if &TYPE('ExtraNKLogging') != 'UNDEFINED'
mr &scratch, r8
_log &s1
_log '[ '
mr r8, &reg
bl PrintH
_log ']'
_log &s2
mr r8, &scratch
endif
ENDM
MACRO
_clog &s
if &TYPE('ExtraNKLogging') != 'UNDEFINED'
_log &s
endif
ENDM
MACRO
LHHI &reg, &val
lis (&reg), ((&val) >> 16) & 0xffff
ENDM
MACRO
LLHI &reg, &val
ori (&reg), (&reg), (&val) & 0xffff
ENDM
MACRO
lisori &reg, &val
lis &reg, ((&val) >> 16) & 0xffff
ori &reg, &reg, (&val) & 0xffff
ENDM
MACRO
llabel &reg, &val
lisori &reg, &val - CodeBase
ENDM
MACRO
_lstart &reg, &val
LHHI (&reg), (&val)
HalfLoadedWord set (&val)
HalfLoadedReg set (&reg)
ENDM
MACRO
_lfinish
LLHI HalfLoadedReg, HalfLoadedWord
ENDM
MACRO
InitList &ptr, &sig, &scratch==r8
_lstart &scratch, &sig
stw &ptr, LLL.Next(&ptr)
_lfinish
stw &ptr, LLL.Prev(&ptr)
stw &scratch, LLL.Signature(&ptr)
ENDM
; Next is 8, Prev is C
MACRO
InsertAsPrev &el, &next, &scratch==r18
stw &next, LLL.Next(&el)
lwz &scratch, LLL.Prev(&next)
stw &scratch, LLL.Prev(&el)
stw &el, LLL.Next(&scratch)
stw &el, LLL.Prev(&next)
ENDM
MACRO
InsertAsNext &el, &prev, &scratch==r18
stw &prev, LLL.Prev(&el)
lwz &scratch, LLL.Next(&prev)
stw &scratch, LLL.Next(&el)
stw &el, LLL.Prev(&scratch)
stw &el, LLL.Next(&prev)
ENDM
MACRO
RemoveFromList &el, &scratch1==r17, &scratch2==r18
; Point neighbours of el up and down at each other
lwz &scratch1, 8(&el)
lwz &scratch2, 12(&el)
stw &scratch1, 8(&scratch2)
stw &scratch2, 12(&scratch1)
; Zero out the pointers in el
li &scratch1, 0
stw &scratch1, 8(&el)
stw &scratch1, 12(&el)
ENDM
MACRO
_Lock &lockoffset, &scratch1==r17, &scratch2==r18
mr &scratch1, r8
mr &scratch2, r9
addi r8, r1, &lockoffset
bl AcquireLock
mr r8, &scratch1
mr r9, &scratch2
ENDM
MACRO
_AssertAndRelease &lockoffset, &scratch==r18
sync
lwz &scratch, &lockoffset(r1)
cmpwi cr1, &scratch, 0
li &scratch, 0
bne+ cr1, @okay
mflr &scratch
bl panic
@okay stw &scratch, &lockoffset(r1)
ENDM
MACRO
_set &dest, &src, &bit
IF &bit < 16
oris&dot &dest, &src, 1 << (15 - (&bit))
ELSE
ori&dot &dest, &src, 1 << (31 - (&bit))
ENDIF
ENDM
MACRO
_clear &dest, &src, &bit
_clear_rbit set &bit+1
if _clear_rbit > 31
_clear_rbit set 0
endif
_clear_lbit set &bit-1
if _clear_lbit < 0
_clear_lbit set 31
endif
rlwinm&dot &dest, &src, 0, _clear_rbit, _clear_lbit
ENDM
MACRO
_band &dest, &src, &bit
IF &bit < 16
andis&dot &dest, &src, 1 << (15 - (&bit))
ELSE
andi&dot &dest, &src, 1 << (31 - (&bit))
ENDIF
ENDM
MACRO
_b_if_time_gt &lhi, &rhi, &targ
cmpw &lhi, &rhi
cmplw cr1, &lhi + 1, &rhi + 1
bgt &targ
blt @fallthru
bgt cr1, &targ
@fallthru
ENDM
MACRO
_b_if_time_le &lhi, &rhi, &targ
cmpw &lhi, &rhi
cmplw cr1, &lhi + 1, &rhi + 1
blt &targ
bgt @fallthru
ble cr1, &targ
@fallthru
ENDM
MACRO
_RegRangeToContextBlock &first, &last
stw &first, $104+8*(&first)(r6)
IF &first != &last
_RegRangeToContextBlock &first+1, &last
ENDIF
ENDM
MACRO
_RegRangeFromContextBlock &first, &last
lwz &first, $104+8*(&first)(r6)
IF &first != &last
_RegRangeFromContextBlock &first+1, &last
ENDIF
ENDM
MACRO
_FloatRangeToContextBlock &first, &last
stfd &first, CB.FloatRegisters+8*(&first)(r6)
IF &first != &last
_FloatRangeToContextBlock &first+1, &last
ENDIF
ENDM
MACRO
_FloatRangeFromContextBlock &first, &last
lfd &first, CB.FloatRegisters+8*(&first)(r6)
IF &first != &last
_FloatRangeFromContextBlock &first+1, &last
ENDIF
ENDM
MACRO
_InvalNCBPointerCache &scratch==r0, &offset==0
IF &offset = 0
li &scratch, -1
ENDIF
IF KDP.NCBPointerCache + &offset < KDP.NCBPointerCacheEnd
stw &scratch, KDP.NCBPointerCache + &offset(r1)
_InvalNCBPointerCache scratch=&scratch, offset=(&offset+8)
ENDIF
ENDM
MACRO
_kaddr &rd, &rs, &label
addi &rd, &rs, (&label-CodeBase)
ENDM
MACRO
_alignToCacheBlock
IF (*-CodeBase) & 0x1f
b * + 4
_alignToCacheBlock
ENDIF
ENDM
MACRO
_align &arg
_align &arg ; Macro necessary because PPCAsm versions vary
my_align set 1 << (&arg)
my_mask set my_align - 1
@ -333,5 +16,48 @@ my_pad set (my_align - (my_offset & my_mask)) & my_mask
IF my_pad
dcb.l my_pad>>2, 0x48000004
ENDIF
ENDM
########################################################################
MACRO
lisori &reg, &val ; NK's preferred way to load 32-bit immediate
lis &reg, ((&val) >> 16) & 0xffff
ori &reg, &reg, (&val) & 0xffff
ENDM
########################################################################
MACRO
_kaddr &rd, &rs, &label ; Get address of label given CodeBase reg
addi &rd, &rs, (&label-CodeBase)
ENDM
########################################################################
MACRO
_ori &rd, &rs, &imm
IF (&imm) > 0xFFFF
oris&dot &rd, &rs, (&imm) >> 16
ELSE
ori&dot &rd, &rs, &imm
ENDIF
ENDM
########################################################################
MACRO
_mvbit &rd, &bd, &rs, &bs
rlwimi &rd, &rs, (32 + &bs - &bd) % 32, &bd, &bd
ENDM
########################################################################
MACRO
_clrNCBCache &scr==r0
li &scr, -1
stw &scr, KDP.NCBCacheLA0
stw &scr, KDP.NCBCacheLA1
stw &scr, KDP.NCBCacheLA2
stw &scr, KDP.NCBCacheLA3
ENDM

82
NanoKernel/NKMemory.s
View File

@ -29,19 +29,19 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
########################################################################
lwz r28, KDP.HtabSinglePTE(r1) ; 2. Parse the PMDT into a PTE (three major code paths)
lwz r31, PMDT.RPN(r29)
lwz r31, PMDT.Word2(r29)
cmpwi cr7, r28, 0 ; always delete the previous PMDT_PTE_Single entry from the HTAB
extlwi. r26, r31, 2, 20 ; use the Cond Reg to branch on Pflag_NotPTE/Pflag_PTE_Single
extlwi. r26, r31, 2, 20 ; use the Cond Reg to branch on Pattr_NotPTE/Pattr_PTE_Single
bne cr7, @del_single_pte
blt @pagelist ; PMDT_PageList is the probable meaning of Pflag_NotPTE (will return to @parsed_pmdt)
blt @pagelist ; PMDT_68k is the probable meaning of Pattr_NotPTE (will return to @parsed_pmdt)
@did_del_single_pte ; (optimized return: if LT then @del_single_pte falls thru to @pagelist)
bgt @single_pte ; PMDT_PTE_Single is the probable meaning of Pflag_PTE_Single (will return to @parsed_pmdt)
bgt @single_pte ; PMDT_PTE_Single is the probable meaning of Pattr_PTE_Single (will return to @parsed_pmdt)
slwi r28, r30, 12 ; PMDT_PTE_Range is likely otherwise, requiring us to add an offset to the PMDT
add r31, r31, r28
@parsed_pmdt ; Save draft PTE in r31 (points to actual page, has PTE-style flags), and r26 =
; 0 (if PMDT_PTE_Range)
; 0x5A5A (if PMDT_PTE_Single)
; PageListEntry ptr (if PMDT_PageList)
; PageListEntry ptr (if PMDT_68k)
########################################################################
@ -143,41 +143,41 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
########################################################################
; r30 = page index within area, r31 = RPN
@pagelist ; Probably PMDT_PageList
@pagelist ; Probably PMDT_68k
extlwi. r28, r31, 2, 21 ; Put remaining two flags into top bits and set Cond Reg
bge @not_actually_pagelist ; Not PMDT_PageList! (e.g. PMDT_InvalidAddress/PMDT_Available)
bge @not_actually_pagelist ; Not PMDT_68k! (e.g. PMDT_InvalidAddress/PMDT_Available)
rlwinm r28, r30, 2, 0xFFFFFFFC ; page index in segment * 4
rlwinm r26, r31, 22, 0xFFFFFFFC ; ptr to first PLE belonging to this segment
lwzux r28, r26, r28 ; r26 = PLE ptr, r28 = PLE
lwz r31, KDP.PageAttributeInit(r1)
andi. r30, r28, 0x881 ; 20(expected), 24/31(unexpected)
andi. r30, r28, M68pteInHTAB | M68pte24 | M68pteResident
rlwimi r31, r28, 0, 0xFFFFF000
cmplwi r30, 1
cmplwi cr7, r30, 0x81
cmplwi r30, M68pteResident
cmplwi cr7, r30, M68pte24 | M68pteResident
ori r31, r31, 0x100
rlwimi r31, r28, 3, 24, 24
rlwimi r31, r28, 31, 26, 26
rlwimi r31, r28, 1, 25, 25
xori r31, r31, 0x40
rlwimi r31, r28, 30, 31, 31 ; r31 gets "default WIMG/PP settings for PTE creation"
ori r31, r31, LpteReference
_mvbit r31, bLpteChange, r28, bM68pteModified
_mvbit r31, bLpteInhibcache, r28, bM68pteInhibcache
_mvbit r31, bLpteWritethru, r28, bM68pteNonwritethru
xori r31, r31, LpteWritethru
_mvbit r31, bLpteP2, r28, bM68pteWriteProtect
beq @parsed_pmdt ; if PLE flag 31 only, go ahead and put in HTAB
beq @parsed_pmdt ; if resident but outside HTAB, put in HTAB
bltlr cr7 ; if no flags, return invalid (GT)
bl SystemCrash ; but if flag 20/24 (i.e. already in HTAB), crash hard!
bl SystemCrash ; crash hard in any other case
########################################################################
@single_pte ; PMDT_PTE_Single
ori r28, r27, 0xfff ; r27 = EA, r31 = PMDT (low word, RPN)
stw r28, KDP.HtabSingleEA(r1)
rlwinm r31, r31, 0, ~Pflag_PTE_Single ; clear the flag that got us here, leaving none
rlwinm r31, r31, 0, ~Pattr_PTE_Single ; clear the flag that got us here, leaving none
li r26, 0x5A5A ; so that KDP.HtabSinglePTE gets set and we return correctly
b @parsed_pmdt ; RTS with r26 = 0x5A5A and r31 having flags cleared
########################################################################
@not_actually_pagelist ; Pflag_NotPTE set, but not PMDT_PageList
@not_actually_pagelist ; Pattr_NotPTE set, but not PMDT_68k
bgtlr ; PMDT_InvalidAddress/PMDT_Available: return invalid (GT)
addi r29, r1, KDP.SupervisorMap
b SetMap ; 800 (unknown) -> SetMap returns success (EQ)
@ -262,16 +262,16 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
lhz r31, PMDT.PageCount(r26)
addi r26, r26, 8
cmplw cr7, r30, r31
lwz r31, PMDT.RPN - 8(r26)
andi. r31, r31, EveryPflag
lwz r31, PMDT.Word2 - 8(r26)
andi. r31, r31, EveryPattr
cmpwi r31, PMDT_Available
bgt cr7, @oflow_next_pmdt ; addr not in this PMDT -> try other PMDT
beq @oflow_next_pmdt ; not PMDT_Available -> try other PMDT
lwz r26, PMDT.RPN - PMDT.Size(r26) ; If PMDT_PageList then we must wang the PLE pre-return
lwz r26, PMDT.Word2 - PMDT.Size(r26) ; If PMDT_68k then we must wang the PLE pre-return
slwi r30, r30, 2 ; (r30 = PLE offset relative to first PLE in segment)
extrwi r31, r26, 2, 20
cmpwi cr7, r31, PMDT_PageList >> 10 ; (save that little tidbit in cr7)
cmpwi cr7, r31, PMDT_68k >> 10 ; (save that little tidbit in cr7)
lwz r31, KDP.NKInfo.HashTableOverflowCount(r1)
stw r29, KDP.HtabLastOverflow(r1)
@ -286,7 +286,7 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
tlbie r28
sync
_InvalNCBPointerCache scratch=r28 ; Also clobber NCB cache if page could get moved
_clrNCBCache scr=r28 ; Also clobber NCB cache if page could get moved
bne cr7, PutPTE ; Is there a PageListEntry we need to edit?
rlwinm r26, r26, 22, 0xFFFFFFFC ; r26 = RPN * 4
@ -330,64 +330,64 @@ SetMap ; MemMap r29
beq @601
rlwimi r29, r28, 7, 0x00000078 ; BATS, non-601
lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29)
lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29)
mtspr ibat0u, r30
mtspr ibat0l, r31
stw r30, KDP.CurIBAT0.U(r1)
stw r31, KDP.CurIBAT0.L(r1)
rlwimi r29, r28, 11, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29)
lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29)
mtspr ibat1u, r30
mtspr ibat1l, r31
stw r30, KDP.CurIBAT1.U(r1)
stw r31, KDP.CurIBAT1.L(r1)
rlwimi r29, r28, 15, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29)
lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29)
mtspr ibat2u, r30
mtspr ibat2l, r31
stw r30, KDP.CurIBAT2.U(r1)
stw r31, KDP.CurIBAT2.L(r1)
rlwimi r29, r28, 19, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29)
lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29)
mtspr ibat3u, r30
mtspr ibat3l, r31
stw r30, KDP.CurIBAT3.U(r1)
stw r31, KDP.CurIBAT3.L(r1)
rlwimi r29, r28, 23, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29)
lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29)
mtspr dbat0u, r30
mtspr dbat0l, r31
stw r30, KDP.CurDBAT0.U(r1)
stw r31, KDP.CurDBAT0.L(r1)
rlwimi r29, r28, 27, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29)
lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29)
mtspr dbat1u, r30
mtspr dbat1l, r31
stw r30, KDP.CurDBAT1.U(r1)
stw r31, KDP.CurDBAT1.L(r1)
rlwimi r29, r28, 31, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29)
lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29)
mtspr dbat2u, r30
mtspr dbat2l, r31
stw r30, KDP.CurDBAT2.U(r1)
stw r31, KDP.CurDBAT2.L(r1)
rlwimi r29, r28, 3, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29)
lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29)
mtspr dbat3u, r30
mtspr dbat3l, r31
stw r30, KDP.CurDBAT3.U(r1)

56
NanoKernel/NKReset.s
View File

@ -178,7 +178,7 @@ InitKCalls
; Init the NCB Pointer Cache
_InvalNCBPointerCache scratch=r23
_clrNCBCache scr=r23
########################################################################
@ -217,10 +217,10 @@ InitPageMap
subi r22, r22, 4
lwzx r21, r9, r22 ; Get RealPgNum/Flags word
andi. r23, r21, Pflag_NotPTE | Pflag_PTE_Rel
cmpwi r23, Pflag_PTE_Rel ; Change if physical
andi. r23, r21, Pattr_NotPTE | Pattr_PTE_Rel
cmpwi r23, Pattr_PTE_Rel ; Change if physical
bne @notrelative ; address is relative.
rlwinm r21, r21, 0, ~Pflag_PTE_Rel
rlwinm r21, r21, 0, ~Pattr_PTE_Rel
add r21, r21, rCI
@notrelative
stwx r21, rPgMap, r22 ; ...Save
@ -235,22 +235,22 @@ InitPageMap
InitSegMaps
lwz r8, NKConfigurationInfo.PageMapIRPOffset(rCI)
add r8, rPgMap, r8 ; The NK chooses the physical
lwz r23, PMDT.RPN(r8) ; addresses of these pages
lwz r23, PMDT.Word2(r8) ; addresses of these pages
rlwimi r23, r1, 0, 0xFFFFF000
stw r23, PMDT.RPN(r8)
stw r23, PMDT.Word2(r8)
lwz r8, NKConfigurationInfo.PageMapKDPOffset(rCI)
add r8, rPgMap, r8
lwz r23, PMDT.RPN(r8)
lwz r23, PMDT.Word2(r8)
rlwimi r23, r1, 0, 0xFFFFF000
stw r23, PMDT.RPN(r8)
stw r23, PMDT.Word2(r8)
lwz r19, KDP.EDPPtr(r1)
lwz r8, NKConfigurationInfo.PageMapEDPOffset(rCI)
add r8, rPgMap, r8
lwz r23, PMDT.RPN(r8)
lwz r23, PMDT.Word2(r8)
rlwimi r23, r19, 0, 0xFFFFF000
stw r23, PMDT.RPN(r8)
stw r23, PMDT.Word2(r8)
addi r9, rCI, NKConfigurationInfo.SegMaps-4 ; SegMaps
@ -278,7 +278,7 @@ CopyBATRangeInit
lwzu r21, 4(r9) ; grab LBAT
stwu r20, 4(r8) ; store UBAT
rlwinm r23, r21, 0, ~Pflag_PTE_Rel
rlwinm r23, r21, 0, ~Pattr_PTE_Rel
cmpw r21, r23
beq @bitnotset
add r21, r23, rCI ; then LBAT[BRPN] is relative to ConfigInfo struct
@ -313,10 +313,11 @@ CopyBATRangeInit
stw r23, KDP.OverlayMap.BatMap(r1)
########################################################################
CreatePageList
; Create a PageList from usable physical pages, i.e. those
; inside a RAM bank, and
; outside the kernel's reserved physical memory
Create68kPTEs
; Create a 68k PTE for every page in the initial logical area.
; (The logical area will equal physical RAM size, so make a PTE for
; every physical page inside a RAM bank but outside kernel memory.
; Later on, the VM Manager can replace this table with its own.)
lwz r21, KDP.KernelMemoryBase(r1) ; this range is forbidden
lwz r20, KDP.KernelMemoryEnd(r1)
subi r29, r21, 4 ; ptr to last added entry
@ -324,12 +325,13 @@ CreatePageList
addi r19, r1, KDP.SysInfo.Bank0Start - 8
lwz r23, KDP.PageAttributeInit(r1) ; "default WIMG/PP settings for PTE creation"
li r30, 1
rlwimi r30, r23, 1, 25, 25
rlwimi r30, r23, 31, 26, 26
xori r30, r30, 0x20
rlwimi r30, r23, 29, 27, 27
rlwimi r30, r23, 27, 28, 28 ; r30 = the flags to use for every PLE
li r30, M68pteResident
_mvbit r30, bM68pteInhibcache, r23, bLpteInhibcache
_mvbit r30, bM68pteNonwritethru, r23, bLpteWritethru
xori r30, r30, bM68pteNonwritethru
_mvbit r30, bM68pteModified, r23, bLpteChange
_mvbit r30, bM68pteUpdate, r23, bLpteReference
li r23, NKSystemInfo.MaxBanks
@next_bank
@ -357,8 +359,10 @@ CreatePageList
; Now r21/r29 point to first/last element of PageList
EditPageMap
; Set up the PMDTs for an initial logical area sized to use up the PageList
PutLogicalAreaInPageMap
; Overwrite the dummy PMDT in every logical-area segment (0-3)
; to point into the logical-area 68k PTE array
; (Overwrite first PMDT in each segment)
subf r22, r21, r29
li r30, 0
@ -372,12 +376,12 @@ EditPageMap
; convert r19 to pages, and save in some places
srwi r19, r19, 12
stw r19, KDP.VMLogicalPages(r1)
stw r19, KDP.TotalPhysicalPages(r1)
stw r19, KDP.VMPhysicalPages(r1)
addi r29, r1, KDP.PARPerSegmentPLEPtrs - 4 ; where to save per-segment PLE ptr
addi r19, r1, KDP.SegMap32SupInit - 8 ; which part of PageMap to update
stw r21, KDP.PageListPtr(r1)
stw r21, KDP.VMPageArray(r1)
@next_segment
cmplwi r22, 0xffff ; continue (bgt) while there are still pages left
@ -385,7 +389,7 @@ EditPageMap
; Rewrite the first PMDT in this segment
lwzu r8, 8(r19) ; find PMDT using SegMap32SupInit
rotlwi r31, r21, 10
ori r31, r31, Pflag_NotPTE_PageList
ori r31, r31, Pattr_68k
stw r30, 0(r8) ; use entire segment (PageIdx = 0, PageCount = 0xFFFF)
stw r31, 4(r8) ; RPN = PLE ptr | PMDT_NotPTE_PageList

20
NanoKernel/NKSoftInts.s
View File

@ -27,7 +27,7 @@
IllegalInstruction
mfmsr r9
_set r8, r9, bitMsrDR
_ori r8, r9, MsrDR
mtmsr r8
lwz r8, 0(r10)
mtmsr r9
@ -109,12 +109,12 @@ IllegalInstruction
addi r23, r23, 1
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
mfmsr r14
_set r15, r14, bitMsrDR
_ori r15, r14, MsrDR
b EmulateDataAccess
########################################################################
_alignToCacheBlock
_align 5
KCallRunAlternateContext
; ARG ContextBlock *r3, flags r4
@ -260,7 +260,7 @@ KCallRunAlternateContext
########################################################################
_alignToCacheBlock
_align 5
KCallResetSystem
; PPC trap 1, or indirectly, 68k RESET
@ -287,7 +287,7 @@ Reset
########################################################################
_alignToCacheBlock
_align 5
KCallPrioritizeInterrupts
; Left side: roll back the interrupt preparation before the int handler repeats is
; Right side: jump to the external interrupt handler (PIH or ProgramInt)
@ -343,7 +343,7 @@ KCallSystemCrash
########################################################################
_alignToCacheBlock
_align 5
ProgramInt
; (also called when the Alternate Context gets an External Int => Exception)
@ -369,7 +369,7 @@ ProgramInt
lwz r7, KDP.Flags(r1)
mfsprg r12, 2
beq KCallReturnFromExceptionFastPath ; KCall in Emulator table => fast path
rlwimi. r7, r7, bitGlobalFlagSystem, 0, 0
rlwimi. r7, r7, bGlobalFlagSystem, 0, 0
cmplwi cr7, r8, 16 * 4
bge cr0, @fromAltContext ; Alt Context cannot make KCalls; this might be an External Int
bge cr7, @notFromEmulatorTrapTable ; from Emulator but not from its KCall table => do more checks
@ -393,7 +393,7 @@ ProgramInt
bc BO_IF_NOT, 14, @notTrap
mfmsr r9 ; fetch the instruction to get the "trap number"
_set r8, r9, bitMsrDR
_ori r8, r9, MsrDR
mtmsr r8
lwz r8, 0(r10)
mtmsr r9
@ -442,7 +442,7 @@ ProgramInt
########################################################################
_alignToCacheBlock
_align 5
SyscallInt
bl LoadInterruptRegisters
mfmsr r8
@ -453,7 +453,7 @@ SyscallInt
########################################################################
_alignToCacheBlock
_align 5
TraceInt ; here because of MSR[SE/BE], possibly thanks to ContextFlagTraceWhenDone
bl LoadInterruptRegisters
li r8, ecInstTrace

494
NanoKernel/NKStructs.s
View File

@ -1,494 +0,0 @@
VecTbl RECORD 0, INCR ; SPRG3 vector table (looked up by ROM vectors)
ds.l 1 ; 00 ; scratch for IVT
SystemReset ds.l 1 ; 04 ; from IVT+100
MachineCheck ds.l 1 ; 08 ; from IVT+200
DSI ds.l 1 ; 0c ; from IVT+300
ISI ds.l 1 ; 10 ; from IVT+400
External ds.l 1 ; 14 ; from IVT+500
Alignment ds.l 1 ; 18 ; from IVT+600
Program ds.l 1 ; 1c ; from IVT+700
FPUnavail ds.l 1 ; 20 ; from IVT+800
Decrementer ds.l 1 ; 24 ; from IVT+900
ReservedVector1 ds.l 1 ; 28 ; from IVT+a00
ReservedVector2 ds.l 1 ; 2c ; from IVT+b00
Syscall ds.l 1 ; 30 ; from IVT+c00
Trace ds.l 1 ; 34 ; from IVT+d00
FPAssist ds.l 1 ; 38 ; from IVT+e00
PerfMonitor ds.l 1 ; 3c ; from IVT+f00
ds.l 1 ; 40
ds.l 1 ; 44
ds.l 1 ; 48
ds.l 1 ; 4c ; Vectors from here downwards are called from
ds.l 1 ; 50 ; odd places in the IVT
ds.l 1 ; 54
ds.l 1 ; 58 ; seems AltiVec-related
ThermalEvent ds.l 1 ; 5c
ds.l 1 ; 60
ds.l 1 ; 64
ds.l 1 ; 68
ds.l 1 ; 6c
ds.l 1 ; 70
ds.l 1 ; 74
ds.l 1 ; 78
ds.l 1 ; 7c
OtherTrace ds.l 1 ; 80
ds.l 1 ; 84
ds.l 1 ; 88
ds.l 1 ; 8c
ds.l 1 ; 90
ds.l 1 ; 94
ds.l 1 ; 98
ds.l 1 ; 9c
ds.l 1 ; a0
ds.l 1 ; a4
ds.l 1 ; a8
ds.l 1 ; ac
ds.l 1 ; b0
ds.l 1 ; b4
ds.l 1 ; b8
ds.l 1 ; bc ; from IVT+0
Size equ *
ENDR
########################################################################
KCallTbl RECORD 0, INCR ; NanoKernel call table
ReturnFromException ds.l 1 ; 00, trap 0
RunAlternateContext ds.l 1 ; 04, trap 1
ResetSystem ds.l 1 ; 08, trap 2 ; 68k RESET
VMDispatch ds.l 1 ; 0c, trap 3 ; 68k $FE0A
PrioritizeInterrupts ds.l 1 ; 10, trap 4
PowerDispatch ds.l 1 ; 14, trap 5 ; 68k $FEOF
RTASDispatch ds.l 1 ; 18, trap 6
CacheDispatch ds.l 1 ; 1c, trap 7
MPDispatch ds.l 1 ; 20, trap 8
ds.l 1 ; 24, trap 9
ds.l 1 ; 28, trap 10
ds.l 1 ; 2c, trap 11
CallAdapterProcPPC ds.l 1 ; 30, trap 12
ds.l 1 ; 34, trap 13
CallAdapterProc68k ds.l 1 ; 38, trap 14
SystemCrash ds.l 1 ; 3c, trap 15
Size equ *
ENDR
########################################################################
; Lower word of Page Table Entry
; Approximates Page Map Entry and Page List Entry
; Page Table Page Map Page List
; -------------------- ------------- -----------
; 0-19 FFFFF000 Real Page Number
; 20 00000800 rsrv Daddy is in htab
; 21 00000400 rsrv Counting
; 22 00000200 rsrv PhysIsRel set when inserting
; 23 00000100 Reference
; 24 00000080 Change
; 25 00000040 W writethru
; 26 00000020 I cache-inhibited
; 27 00000010 M memory coherence saved Change?
; 28 00000008 G guarded writes saved Reference?
; 29 00000004 rsrv
; 30 00000002 P user
; 31 00000001 P supervisor allows to be in HTAB
; Important consideration: does SegMap get put permanently in HTAB?
_bitEqu 23, PTFlagReference
_bitEqu 24, PTFlagChange
_bitEqu 25, PTFlagWritethru
_bitEqu 26, PTFlagInhibcache
_bitEqu 27, PTFlagMemcoher
_bitEqu 28, PTFlagGuardwrite
_bitEqu 30, PTFlagP1
_bitEqu 31, PTFlagP2
########################################################################
PMDT RECORD 0, INCR ; 8-byte PageMap entry (why "PMDT"?)
PageIdx ds.w 1 ; within the segment
PageCount ds.w 1 ; minus one
RPN ds.l 1 ; like PTE: RealPgNum (0-19) + Pflags (20-31)
Size equ *
ENDR
; The union of every flag below:
EveryPflag equ 0xE01
; When Pflag_NotPTE=1, the PMDT is a pageable area or another special value:
Pflag_NotPTE equ 0x800 ; Special
Pflag_NotPTE_PageList equ 0x400 ; Pageable area (RPN points to PageList)
PMDT_PageList equ 0xC00 ; Combinations when Pflag_NotPTE=1...
PMDT_InvalidAddress equ 0xA00
PMDT_Available equ 0xA01
; When Pflag_NotPTE=0, the PMDT describes a non-pageable area, and these apply:
Pflag_PTE_Single equ 0x400 ; Only one page
Pflag_PTE_Rel equ 0x200 ; RPN is ConfigInfo-relative
PMDT_PTE_Range equ 0x000 ; Combinations when Pflag_NotPTE=0...
PMDT_PTE_Range_Rel equ 0x200
PMDT_PTE_Single equ 0x400
PMDT_PTE_Single_Rel equ 0x600
########################################################################
BAT RECORD 0, INCR
U ds.l 1
L ds.l 1
ENDR
########################################################################
MemMap RECORD 0, INCR
SegMapPtr ds.l 1 ; ptr to array of sixteen 8-byte (ptr/flags) records; ptr is to first PMDT for seg
BatMap ds.l 1 ; packed array of 4-bit indices into BATs
ENDR
########################################################################
KDP RECORD 0, INCR ; Kernel Data Page
r0 ds.l 1 ; 000 ; used for quick register saves at interrupt time
r1 ds.l 1 ; 004
r2 ds.l 1 ; 008
r3 ds.l 1 ; 00c
r4 ds.l 1 ; 010
r5 ds.l 1 ; 014
r6 ds.l 1 ; 018
r7 ds.l 1 ; 01c
r8 ds.l 1 ; 020
r9 ds.l 1 ; 024
r10 ds.l 1 ; 028
r11 ds.l 1 ; 02c
r12 ds.l 1 ; 030
r13 ds.l 1 ; 034
r14 ds.l 1 ; 038
r15 ds.l 1 ; 03c
r16 ds.l 1 ; 040
r17 ds.l 1 ; 044
r18 ds.l 1 ; 048
r19 ds.l 1 ; 04c
r20 ds.l 1 ; 050
r21 ds.l 1 ; 054
r22 ds.l 1 ; 058
r23 ds.l 1 ; 05c
r24 ds.l 1 ; 060
r25 ds.l 1 ; 064
r26 ds.l 1 ; 068
r27 ds.l 1 ; 06c
r28 ds.l 1 ; 070
r29 ds.l 1 ; 074
r30 ds.l 1 ; 078
r31 ds.l 1 ; 07c
SegMaps
SegMap32SupInit ds.l 32 ; 080:100
SegMap32UsrInit ds.l 32 ; 100:180
SegMap32CPUInit ds.l 32 ; 180:200
SegMap32OvlInit ds.l 32 ; 200:280
BATs ds.l 32 ; 280:300
CurIBAT0 ds BAT ; 300:308
CurIBAT1 ds BAT ; 308:310
CurIBAT2 ds BAT ; 310:318
CurIBAT3 ds BAT ; 318:320
CurDBAT0 ds BAT ; 320:328
CurDBAT1 ds BAT ; 328:330
CurDBAT2 ds BAT ; 330:338
CurDBAT3 ds BAT ; 338:340
NCBPointerCache
NCBCacheLA0 ds.l 1 ; 340
NCBCachePA0 ds.l 1 ; 344
NCBCacheLA1 ds.l 1 ; 348
NCBCachePA1 ds.l 1 ; 34c
NCBCacheLA2 ds.l 1 ; 350
NCBCachePA2 ds.l 1 ; 354
NCBCacheLA3 ds.l 1 ; 358
NCBCachePA3 ds.l 1 ; 35c
NCBPointerCacheEnd
VecTblSystem ds VecTbl ; 360:420 ; when 68k emulator is running, *or* any MTask
VecTblAlternate ds VecTbl ; 420:4e0 ; native PowerPC in blue task
VecTblMemRetry ds VecTbl ; 4e0:5a0 ; "FDP" instruction emulation
FloatScratch ds.d 1 ; 5a0:5a8
TopOfFreePages ds.l 1 ; 5a8 ; gotten from the old SPRG0
ds.l 1 ; 5ac
PARPerSegmentPLEPtrs ds.l 4 ; 5b0:5c0 ; for each PAR segment, a ptr into the PAR PageList
FloatingPtTemp1 ds.l 1 ; 5c0
FloatingPtTemp2 ds.l 1 ; 5c4
SupervisorMap ds MemMap ; 5c8:5d0
UserMap ds MemMap ; 5d0:5d8
CpuMap ds MemMap ; 5d8:5e0
OverlayMap ds MemMap ; 5e0:5e8
CurMap ds MemMap ; 5e8:5f0
KCallTbl ds KCallTbl ; 5f0:630
ConfigInfoPtr ds.l 1 ; 630
EDPPtr ds.l 1 ; 634
KernelMemoryBase ds.l 1 ; 638
KernelMemoryEnd ds.l 1 ; 63c
LowMemPtr ds.l 1 ; 640 ; physical address of PAR Low Memory
SharedMemoryAddr ds.l 1 ; 644 ; debug?
EmuKCallTblPtrLogical ds.l 1 ; 648
CodeBase ds.l 1 ; 64c
MRBase ds.l 1 ; 650
ECBPtrLogical ds.l 1 ; 654 ; Emulator/System ContextBlock
ECBPtr ds.l 1 ; 658
ContextPtr ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2
Flags ds.l 1 ; 660 ; moved to EWA (per-CPU) in NKv2
Enables ds.l 1 ; 664 ; moved to EWA (per-CPU) in NKv2
OtherContextDEC ds.l 1 ; 668 ; ticks that the *inactive* context has left out of 1s
PageMapEndPtr ds.l 1 ; 66c ; et at the same time as PageMapStartPtr below
TestIntMaskInit ds.l 1 ; 670
PostIntMaskInit ds.l 1 ; 674 ; CR flags to set when posting an interrupt to the Emulator
ClearIntMaskInit ds.l 1 ; 678 ; CR flags to clear (as mask) when clearing an interrupt
EmuIntLevelPtr ds.l 1 ; 67c ; physical ptr to an Emulator global
DebugIntPtr ds.l 1 ; 680 ; within (debug?) shared memory
PageMapStartPtr ds.l 1 ; 684
PageAttributeInit ds.l 1 ; 688 ; defaults for PLE/PTE?
HtabSingleEA ds.l 1 ; 68c ; PMDT_PTE_Single page most recently put into HTAB
HtabSinglePTE ds.l 1 ; 690 ; and a ptr to its PTE
HtabLastEA ds.l 1 ; 694
HtabLastPTE ds.l 1 ; 698
HtabLastOverflow ds.l 1 ; 69c
PTEGMask ds.l 1 ; 6a0
HTABORG ds.l 1 ; 6a4
VMLogicalPages ds.l 1 ; 6a8 ; set at init and changed by VMInit
TotalPhysicalPages ds.l 1 ; 6ac ; does not take into acct maximum MacOS memory
PageListPtr ds.l 1 ; 6b0 ; VM puts this in system heap
VMMaxVirtualPages ds.l 1 ; 6b4 ; always 5fffe000, even with VM on
org 0x700
CrashTop
CrashR0 ds.l 1 ; 700
CrashR1 ds.l 1 ; 704
CrashR2 ds.l 1 ; 708
CrashR3 ds.l 1 ; 70c
CrashR4 ds.l 1 ; 710
CrashR5 ds.l 1 ; 714
CrashR6 ds.l 1 ; 718
CrashR7 ds.l 1 ; 71c
CrashR8 ds.l 1 ; 720
CrashR9 ds.l 1 ; 724
CrashR10 ds.l 1 ; 728
CrashR11 ds.l 1 ; 72c
CrashR12 ds.l 1 ; 730
CrashR13 ds.l 1 ; 734
CrashR14 ds.l 1 ; 738
CrashR15 ds.l 1 ; 73c
CrashR16 ds.l 1 ; 740
CrashR17 ds.l 1 ; 744
CrashR18 ds.l 1 ; 748
CrashR19 ds.l 1 ; 74c
CrashR20 ds.l 1 ; 750
CrashR21 ds.l 1 ; 754
CrashR22 ds.l 1 ; 758
CrashR23 ds.l 1 ; 75c
CrashR24 ds.l 1 ; 760
CrashR25 ds.l 1 ; 764
CrashR26 ds.l 1 ; 768
CrashR27 ds.l 1 ; 76c
CrashR28 ds.l 1 ; 770
CrashR29 ds.l 1 ; 774
CrashR30 ds.l 1 ; 778
CrashR31 ds.l 1 ; 77c
CrashCR ds.l 1 ; 780
CrashMQ ds.l 1 ; 784
CrashXER ds.l 1 ; 788
CrashLR ds.l 1 ; 78c
CrashCTR ds.l 1 ; 790
CrashPVR ds.l 1 ; 794
CrashDSISR ds.l 1 ; 798
CrashDAR ds.l 1 ; 79c
CrashRTCU ds.l 1 ; 7a0
CrashRTCL ds.l 1 ; 7a4
CrashDEC ds.l 1 ; 7a8
CrashHID0 ds.l 1 ; 7ac
CrashSDR1 ds.l 1 ; 7b0
CrashSRR0 ds.l 1 ; 7b4
CrashSRR1 ds.l 1 ; 7b8
CrashMSR ds.l 1 ; 7bc
CrashSR0 ds.l 1 ; 7c0
CrashSR1 ds.l 1 ; 7c4
CrashSR2 ds.l 1 ; 7c8
CrashSR3 ds.l 1 ; 7cc
CrashSR4 ds.l 1 ; 7d0
CrashSR5 ds.l 1 ; 7d4
CrashSR6 ds.l 1 ; 7d8
CrashSR7 ds.l 1 ; 7dc
CrashSR8 ds.l 1 ; 7e0
CrashSR9 ds.l 1 ; 7e4
CrashSR10 ds.l 1 ; 7e8
CrashSR11 ds.l 1 ; 7ec
CrashSR12 ds.l 1 ; 7f0
CrashSR13 ds.l 1 ; 7f4
CrashSR14 ds.l 1 ; 7f8
CrashSR15 ds.l 1 ; 7fc
CrashF0 ds.d 1 ; 800
CrashF1 ds.d 1 ; 808
CrashF2 ds.d 1 ; 810
CrashF3 ds.d 1 ; 818
CrashF4 ds.d 1 ; 820
CrashF5 ds.d 1 ; 828
CrashF6 ds.d 1 ; 830
CrashF7 ds.d 1 ; 838
CrashF8 ds.d 1 ; 840
CrashF9 ds.d 1 ; 848
CrashF10 ds.d 1 ; 850
CrashF11 ds.d 1 ; 858
CrashF12 ds.d 1 ; 860
CrashF13 ds.d 1 ; 868
CrashF14 ds.d 1 ; 870
CrashF15 ds.d 1 ; 878
CrashF16 ds.d 1 ; 880
CrashF17 ds.d 1 ; 888
CrashF18 ds.d 1 ; 890
CrashF19 ds.d 1 ; 898
CrashF20 ds.d 1 ; 8a0
CrashF21 ds.d 1 ; 8a8
CrashF22 ds.d 1 ; 8b0
CrashF23 ds.d 1 ; 8b8
CrashF24 ds.d 1 ; 8c0
CrashF25 ds.d 1 ; 8c8
CrashF26 ds.d 1 ; 8d0
CrashF27 ds.d 1 ; 8d8
CrashF28 ds.d 1 ; 8e0
CrashF29 ds.d 1 ; 8e8
CrashF30 ds.d 1 ; 8f0
CrashF31 ds.d 1 ; 8f8
CrashFPSCR ds.l 1 ; 900
CrashKernReturn ds.l 1 ; 904
CrashUnknown1 ds.l 1 ; 908
CrashUnknown2 ds.l 1 ; 90c
CrashBtm
PageMap ds.b 0x1a8 ; 910:ab8
org 0xCC0
SysInfo ds NKSystemInfo ; cc0:d80
DiagInfo ds NKDiagInfo ; d80:e80
NKInfo ds NKNanoKernelInfo ; e80:f80
ProcInfo ds NKProcessorInfo ; f80:fc0
InfoRecBlk ds.b 64 ; fc0:1000 ; Access using ptr equates in InfoRecords
ENDR
########################################################################
KernelState RECORD 0,INCR
Flags ds.l 1 ; 00
Enables ds.l 1 ; 04
Handler ds.d 1 ; 08
HandlerArg ds.d 1 ; 10
HandlerReturn ds.d 1 ; 18
MemRet17 ds.d 1 ; 20 ; MemRetry state
MemRetData ds.d 1 ; 28
MemRet19 ds.d 1 ; 30
MemRet18 ds.d 1 ; 38
ENDR
########################################################################
CB RECORD 0,INCR ; ContextBlock (Emulator/System or Native/Alternate)
InterState ds KernelState ; 000:040 ; for switching between contexts
IntraState ds KernelState ; 040:080 ; for raising/disposing exceptions within a context
FaultSrcPC ds.d 1 ; 080 ; saved when starting an exception handler
FaultSrcLR ds.d 1 ; 088
FaultSrcR3 ds.d 1 ; 090
FaultSrcR4 ds.d 1 ; 098
MSR ds.d 1 ; 0a0
ds.d 1 ; 0a8
ds.d 1 ; 0b0
ds.d 1 ; 0b8
MQ ds.d 1 ; 0c0 ; 601 only
ds.d 1 ; 0c8
XER ds.d 1 ; 0d0
CR ds.d 1 ; 0d8
FPSCR ds.d 1 ; 0e0 ; unsure, mffs/mtfs?
LR ds.d 1 ; 0e8
CTR ds.d 1 ; 0f0
PC ds.d 1 ; 0f8
r0 ds.d 1 ; 100 ; big-endian, so 32-bit value stored in second word
r1 ds.d 1 ; 108
r2 ds.d 1 ; 110
r3 ds.d 1 ; 118
r4 ds.d 1 ; 120
r5 ds.d 1 ; 128
r6 ds.d 1 ; 130
r7 ds.d 1 ; 138
r8 ds.d 1 ; 140
r9 ds.d 1 ; 148
r10 ds.d 1 ; 150
r11 ds.d 1 ; 158
r12 ds.d 1 ; 160
r13 ds.d 1 ; 168
r14 ds.d 1 ; 170
r15 ds.d 1 ; 178
r16 ds.d 1 ; 180
r17 ds.d 1 ; 188
r18 ds.d 1 ; 190
r19 ds.d 1 ; 198
r20 ds.d 1 ; 1a0
r21 ds.d 1 ; 1a8
r22 ds.d 1 ; 1b0
r23 ds.d 1 ; 1b8
r24 ds.d 1 ; 1c0
r25 ds.d 1 ; 1c8
r26 ds.d 1 ; 1d0
r27 ds.d 1 ; 1d8
r28 ds.d 1 ; 1e0
r29 ds.d 1 ; 1e8
r30 ds.d 1 ; 1f0
r31 ds.d 1 ; 1f8
f0 ds.d 1 ; 200
f1 ds.d 1 ; 208
f2 ds.d 1 ; 210
f3 ds.d 1 ; 218
f4 ds.d 1 ; 220
f5 ds.d 1 ; 228
f6 ds.d 1 ; 230
f7 ds.d 1 ; 238
f8 ds.d 1 ; 240
f9 ds.d 1 ; 248
f10 ds.d 1 ; 250
f11 ds.d 1 ; 258
f12 ds.d 1 ; 260
f13 ds.d 1 ; 268
f14 ds.d 1 ; 270
f15 ds.d 1 ; 278
f16 ds.d 1 ; 280
f17 ds.d 1 ; 288
f18 ds.d 1 ; 290
f19 ds.d 1 ; 298
f20 ds.d 1 ; 2a0
f21 ds.d 1 ; 2a8
f22 ds.d 1 ; 2b0
f23 ds.d 1 ; 2b8
f24 ds.d 1 ; 2c0
f25 ds.d 1 ; 2c8
f26 ds.d 1 ; 2d0
f27 ds.d 1 ; 2d8
f28 ds.d 1 ; 2e0
f29 ds.d 1 ; 2e8
f30 ds.d 1 ; 2f0
f31 ds.d 1 ; 2f8
Size equ *
ENDR

2
NanoKernel/NKSystemCrash.s
View File

@ -92,7 +92,7 @@ SystemCrash
stw r0, KDP.CrashSR15(r1)
mfmsr r0
_set r0, r0, bitMsrFP
_ori r0, r0, MsrFP
mtmsr r0
stfd f0, KDP.CrashF0(r1)
stfd f1, KDP.CrashF1(r1)

3
NanoKernel/NanoKernel.s
View File

@ -1,8 +1,7 @@
include 'InfoRecords.a'
include 'NKStructs.s'
include 'NKEquates.s'
include 'NKMacros.s'
include 'NKEquates.s'
CodeBase
include 'NKInit.s'