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refactor

This commit is contained in:
Elliot Nunn 2018-08-14 00:04:37 +08:00
parent 88a023729f
commit d3cf56d401
21 changed files with 595 additions and 633 deletions
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458
Internal/InfoRecords.a
View File

@ -1,458 +0,0 @@
;_______________________________________________________________________
; Configuration Info Record
; Used to pass Configuration information from the Boot Program to the
; NanoKernel for data structure and address mapping initialization.
;_______________________________________________________________________
NKConfigurationInfo record 0,increment
ROMByteCheckSums ds.l 8 ; 000 ; ROM Checksums - one word for each of 8 byte lanes
ROMCheckSum64 ds.l 2 ; 020 ; ROM Checksum - 64 bit sum of doublewords
ROMImageBaseOffset ds.l 1 ; 028 ; Offset of Base of total ROM image
ROMImageSize ds.l 1 ; 02c ; Number of bytes in ROM image
ROMImageVersion ds.l 1 ; 030 ; ROM Version number for entire ROM
Mac68KROMOffset ds.l 1 ; 034 ; Offset of base of Macintosh 68K ROM
Mac68KROMSize ds.l 1 ; 038 ; Number of bytes in Macintosh 68K ROM
ExceptionTableOffset ds.l 1 ; 03c ; Offset of base of PowerPC Exception Table Code
ExceptionTableSize ds.l 1 ; 040 ; Number of bytes in PowerPC Exception Table Code
HWInitCodeOffset ds.l 1 ; 044 ; Offset of base of Hardware Init Code (field moved!)
HWInitCodeSize ds.l 1 ; 048 ; Number of bytes in Hardware Init Code
KernelCodeOffset ds.l 1 ; 04c ; Offset of base of NanoKernel Code
KernelCodeSize ds.l 1 ; 050 ; Number of bytes in NanoKernel Code
EmulatorCodeOffset ds.l 1 ; 054 ; Offset of base of Emulator Code
EmulatorCodeSize ds.l 1 ; 058 ; Number of bytes in Emulator Code
OpcodeTableOffset ds.l 1 ; 05c ; Offset of base of Opcode Table
OpcodeTableSize ds.l 1 ; 060 ; Number of bytes in Opcode Table
BootstrapVersion ds.b 16 ; 064 ; Bootstrap loader version info
BootVersionOffset ds.l 1 ; 074 ; offset within EmulatorData of BootstrapVersion
ECBOffset ds.l 1 ; 078 ; offset within EmulatorData of ECB
IplValueOffset ds.l 1 ; 07c ; offset within EmulatorData of IplValue
EmulatorEntryOffset ds.l 1 ; 080 ; offset within Emulator Code of entry point
KernelTrapTableOffset ds.l 1 ; 084 ; offset within Emulator Code of KernelTrapTable
TestIntMaskInit ds.l 1 ; 088 ; initial value for test interrupt mask
ClearIntMaskInit ds.l 1 ; 08c ; initial value for clear interrupt mask
PostIntMaskInit ds.l 1 ; 090 ; initial value for post interrupt mask
LA_InterruptCtl ds.l 1 ; 094 ; logical address of Interrupt Control I/O page
InterruptHandlerKind ds.b 1 ; 098 ; kind of handler to use
ds.b 3 ; 099 ; filler
LA_InfoRecord ds.l 1 ; 09c ; logical address of InfoRecord page
LA_KernelData ds.l 1 ; 0a0 ; logical address of KernelData page
LA_EmulatorData ds.l 1 ; 0a4 ; logical address of EmulatorData page
LA_DispatchTable ds.l 1 ; 0a8 ; logical address of Dispatch Table
LA_EmulatorCode ds.l 1 ; 0ac ; logical address of Emulator Code
MacLowMemInitOffset ds.l 1 ; 0b0 ; offset to list of LowMem addr/data values
PageAttributeInit ds.l 1 ; 0b4 ; default WIMG/PP settings for PTE creation
PageMapInitSize ds.l 1 ; 0b8 ; size of page mapping info
PageMapInitOffset ds.l 1 ; 0bc ; offset to page mapping info (from base of ConfigInfo)
PageMapIRPOffset ds.l 1 ; 0c0 ; offset of InfoRecord map info (from base of PageMap)
PageMapKDPOffset ds.l 1 ; 0c4 ; offset of KernelData map info (from base of PageMap)
PageMapEDPOffset ds.l 1 ; 0c8 ; offset of EmulatorData map info (from base of PageMap)
SegMaps
SegMap32SupInit ds.l 32 ; 0cc ; 32 bit mode Segment Map Supervisor space
SegMap32UsrInit ds.l 32 ; 14c ; 32 bit mode Segment Map User space
SegMap32CPUInit ds.l 32 ; 1cc ; 32 bit mode Segment Map CPU space
SegMap32OvlInit ds.l 32 ; 24c ; 32 bit mode Segment Map Overlay mode
BATRangeInit ds.l 32 ; 2cc ; BAT mapping ranges
BatMap32SupInit ds.l 1 ; 34c ; 32 bit mode BAT Map Supervisor space
BatMap32UsrInit ds.l 1 ; 350 ; 32 bit mode BAT Map User space
BatMap32CPUInit ds.l 1 ; 354 ; 32 bit mode BAT Map CPU space
BatMap32OvlInit ds.l 1 ; 358 ; 32 bit mode BAT Map Overlay mode
SharedMemoryAddr ds.l 1 ; 35c ; physical address of Mac/Smurf shared message mem
PA_RelocatedLowMemInit ds.l 1 ; 360 ; physical address of RelocatedLowMem
OpenFWBundleOffset ds.l 1 ; 364 ; Offset of base of OpenFirmware PEF Bundle
OpenFWBundleSize ds.l 1 ; 368 ; Number of bytes in OpenFirmware PEF Bundle
LA_OpenFirmware ds.l 1 ; 36c ; logical address of Open Firmware
PA_OpenFirmware ds.l 1 ; 370 ; physical address of Open Firmware
LA_HardwarePriv ds.l 1 ; 374 ; logical address of HardwarePriv callback
; Used to stop here, plus 8 bytes for cache block alignment (0x380 bytes).
; Now there be more!
Debug ds.w 1 ; 378 ; > 256 required for screen log
DebugThreshold equ 257
org 0x388
DebugFlags ds.l 1 ; 388 ; bit 1<< 1 required for screen log
NanodbgrFlagShift equ 0
NanodbgrFlagBit equ 31 - NanodbgrFlagShift
LogFlagShift equ 1
LogFlagBit equ 31 - LogFlagShift
Size equ *
endr
;_______________________________________________________________________
; System Info Record
;
; Used to pass System information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKSystemInfoPtr equ $5FFFEFF0 ; logical address of NKSystemInfo record
NKSystemInfoVer equ $5FFFEFF4 ; version number of NKSystemInfo record
NKSystemInfoLen equ $5FFFEFF6 ; length of NKSystemInfo record
NKSystemInfo record 0,increment
PhysicalMemorySize ds.l 1 ; 000, irp+dc0 ; Number of bytes in Physical RAM
UsableMemorySize ds.l 1 ; 004, irp+dc4 ; Number of bytes in Usable RAM
LogicalMemorySize ds.l 1 ; 008, irp+dc8 ; Number of bytes in Logical RAM
HashTableSize ds.l 1 ; 00c, irp+dcc ; Number of bytes in Memory Hash Table
L2DataCacheTotalSize ds.l 1 ; 010, irp+dd0 ; number of bytes in the L2 Data Cache
L2InstCacheTotalSize ds.l 1 ; 014, irp+dd4 ; number of bytes in the L2 Instruction Cache
L2CombinedCaches ds.w 1 ; 018, irp+dd8 ; 1 <- combined or no cache, 0 <- split cache
L2InstCacheBlockSize ds.w 1 ; 01a, irp+dda ; number of bytes in a Block of the L2 Instruction Cache
L2DataCacheBlockSize ds.w 1 ; 01c, irp+ddc ; number of bytes in a Block of the L2 Data Cache
L2InstCacheAssociativity ds.w 1 ; 01e, irp+dde ; Associativity of the L2 Instruction Cache
L2DataCacheAssociativity ds.w 1 ; 020, irp+de0 ; Associativity of the L2 Data Cache
ds.b 2 ; 022, irp+de2 ; unused
ds.b 2 ; 024, irp+de4 ; unused
FlashManufacturerCode ds.b 1 ; 026, irp+de6 ; Flash ROM Manufacturer code
FlashDeviceCode ds.b 1 ; 027, irp+de7 ; Flash ROM Device code
FlashStart ds.l 1 ; 028, irp+de8 ; Starting address of Flash ROM
FlashSize ds.l 1 ; 02c, irp+dec ; Number of bytes in Flash ROM
Bank0Start ds.l 1 ; 030, irp+df0 ; Starting address of RAM bank 0
Bank0Size ds.l 1 ; 034, irp+df4 ; Number of bytes in RAM bank 0
Bank1Start ds.l 1 ; 038, irp+df8 ; Starting address of RAM bank 1
Bank1Size ds.l 1 ; 03c, irp+dfc ; Number of bytes in RAM bank 1
Bank2Start ds.l 1 ; 040, irp+e00 ; Starting address of RAM bank 2
Bank2Size ds.l 1 ; 044, irp+e04 ; Number of bytes in RAM bank 2
Bank3Start ds.l 1 ; 048, irp+e08 ; Starting address of RAM bank 3
Bank3Size ds.l 1 ; 04c, irp+e0c ; Number of bytes in RAM bank 3
Bank4Start ds.l 1 ; 050, irp+e10 ; Starting address of RAM bank 4
Bank4Size ds.l 1 ; 054, irp+e14 ; Number of bytes in RAM bank 4
Bank5Start ds.l 1 ; 058, irp+e18 ; Starting address of RAM bank 5
Bank5Size ds.l 1 ; 05c, irp+e1c ; Number of bytes in RAM bank 5
Bank6Start ds.l 1 ; 060, irp+e20 ; Starting address of RAM bank 6
Bank6Size ds.l 1 ; 064, irp+e24 ; Number of bytes in RAM bank 6
Bank7Start ds.l 1 ; 068, irp+e28 ; Starting address of RAM bank 7
Bank7Size ds.l 1 ; 06c, irp+e2c ; Number of bytes in RAM bank 7
Bank8Start ds.l 1 ; 070, irp+e30 ; Starting address of RAM bank 8
Bank8Size ds.l 1 ; 074, irp+e34 ; Number of bytes in RAM bank 8
Bank9Start ds.l 1 ; 078, irp+e38 ; Starting address of RAM bank 9
Bank9Size ds.l 1 ; 07c, irp+e3c ; Number of bytes in RAM bank 9
Bank10Start ds.l 1 ; 080, irp+e40 ; Starting address of RAM bank 10
Bank10Size ds.l 1 ; 084, irp+e44 ; Number of bytes in RAM bank 10
Bank11Start ds.l 1 ; 088, irp+e48 ; Starting address of RAM bank 11
Bank11Size ds.l 1 ; 08c, irp+e4c ; Number of bytes in RAM bank 11
Bank12Start ds.l 1 ; 090, irp+e50 ; Starting address of RAM bank 12
Bank12Size ds.l 1 ; 094, irp+e54 ; Number of bytes in RAM bank 12
Bank13Start ds.l 1 ; 098, irp+e58 ; Starting address of RAM bank 13
Bank13Size ds.l 1 ; 09c, irp+e5c ; Number of bytes in RAM bank 13
Bank14Start ds.l 1 ; 0a0, irp+e60 ; Starting address of RAM bank 14
Bank14Size ds.l 1 ; 0a4, irp+e64 ; Number of bytes in RAM bank 14
Bank15Start ds.l 1 ; 0a8, irp+e68 ; Starting address of RAM bank 15
Bank15Size ds.l 1 ; 0ac, irp+e6c ; Number of bytes in RAM bank 15
EndOfBanks
align 5 ; pad to nice cache block alignment
MaxBanks equ 16 ; Pads out to old struct len (cache block), more to come...
Size equ *
endr
;_______________________________________________________________________
; Diagnostic Info Record
;
; Used to pass Diagnostic information from the power on Diagnostics to
; the NanoKernel, and from the NanoKernel to user mode software.
;_______________________________________________________________________
NKDiagInfoPtr equ $5FFFEFE8 ; logical address of DiagnosticInfo record
NKDiagInfoVer equ $5FFFEFEC ; version number of DiagnosticInfo record
NKDiagInfoLen equ $5FFFEFEE ; length of DiagnosticInfo record
NKDiagInfo record 0,increment
BankMBFailOffset ds.l 1 ; 000 ; Mother Board RAM failure code
BankAFailOffset ds.l 1 ; 004 ; Bank A RAM failure code
BankBFailOffset ds.l 1 ; 008 ; Bank B RAM failure code
BankCFailOffset ds.l 1 ; 00c ; Bank C RAM failure code
BankDFailOffset ds.l 1 ; 010 ; Bank D RAM failure code
BankEFailOffset ds.l 1 ; 014 ; Bank E RAM failure code
BankFFailOffset ds.l 1 ; 018 ; Bank F RAM failure code
BankGFailOffset ds.l 1 ; 01c ; Bank G RAM failure code
BankHFailOffset ds.l 1 ; 020 ; Bank H RAM failure code
CacheFailOffset ds.l 1 ; 024 ; cache failure code
LongBootParamOffset ds.l 1 ; 028 ; on longBoot this is where the params will be
POSTTraceOffset ds.l 1 ; 02c ; this tells us what route the POST took
POSTOldWarmOffset ds.l 1 ; 030 ; logged address of old warmstart flag
POSTOldLongOffset ds.l 1 ; 034 ; logged address of old long boot flag
POSTOldGlobbOffset ds.l 1 ; 038 ; logged address of old Diagnostic Info Record
POSTOldParamOffset ds.l 1 ; 03c ; the params from the old diag globb
POSTStartRTCUOffset ds.l 1 ; 040 ; PPC Real Time Clock Upper at start of POST
POSTStartRTCLOffset ds.l 1 ; 044 ; PPC Real Time Clock Lower at start of POST
POSTEndRTCUOffset ds.l 1 ; 048 ; PPC Real Time Clock Upper at end of POST
POSTEndRTCLOffset ds.l 1 ; 04c ; PPC Real Time Clock Lower at end of POST
POSTTestTypeOffset ds.l 1 ; 050 ; when long RAM tests fail test type which failed is put here
POSTError2Offset ds.l 1 ; 054 ; result codes from tests
POSTError3Offset ds.l 1 ; 058 ; result codes from tests
POSTError4Offset ds.l 1 ; 05c ; result codes from tests
RegistersStore ds.b 140 ; 060 ; store all 60x registers here, still fit into 256 bytes size.
; Everything BEFORE here is new (hence the funny-sized register store)
DiagPOSTResult2 ds.l 1 ; 0ec ; POST results
DiagPOSTResult1 ds.l 1 ; 0f0 ; POST results
DiagLongBootSig ds.l 1 ; 0f4 ; Burn in restart flag
DiagWarmStartHigh ds.l 1 ; 0f8 ; First long of native warm start (WLSC) <SM44>
DiagWarmStartLow ds.l 1 ; 0fc ; Second long of native warm start (SamB) <SM44>
align 5 ; pad to nice cache block alignment
Size equ *
endr
;_______________________________________________________________________
; NanoKernel Info Record
;
; Used to pass NanoKernel statistics from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKNanoKernelInfoPtr equ $5FFFEFE0 ; logical address of NanoKernelInfo record
NKNanoKernelInfoVer equ $5FFFEFE4 ; version number of NanoKernelInfo record
NKNanoKernelInfoLen equ $5FFFEFE6 ; length of NanoKernelInfo record
NKNanoKernelInfo record 0,increment
ExceptionCauseCounts ds.l 32 ; 000, kdp+dc0 ; counters per exception cause
NanoKernelCallCounts ds.l 16 ; 080, kdp+e40 ; counters per NanoKernel call
ExternalIntCount ds.l 1 ; 0c0, kdp+e80 ; count of External Interrupts
MisalignmentCount ds.l 1 ; 0c4, kdp+e84 ; count of Misalignment Interrupts
FPUReloadCount ds.l 1 ; 0c8, kdp+e88 ; count of FPU reloads on demand
DecrementerIntCount ds.l 1 ; 0cc, kdp+e8c ; count of Decrementer Interrupts
QuietWriteCount ds.l 1 ; 0d0, kdp+e90 ; count of Writes to Quiet Read-Only memory
HashTableCreateCount ds.l 1 ; 0d4, kdp+e94 ; count of Hash Table Entry creations
HashTableDeleteCount ds.l 1 ; 0d8, kdp+e98 ; count of Hash Table Entry deletions
HashTableOverflowCount ds.l 1 ; 0dc, kdp+e9c ; count of Hash Table Entry overflows
EmulatedUnimpInstCount ds.l 1 ; 0e0, kdp+ea0 ; count of Emulated unimplemented instructions
NCBPtrCacheMissCount ds.l 1 ; 0e4, kdp+ea4 ; count of NCB Pointer cache misses
ExceptionPropagateCount ds.l 1 ; 0e8, kdp+ea8 ; count of Exceptions propagated to system
ExceptionForcedCount ds.l 1 ; 0ec, kdp+eac ; count of Exceptions forced to system
SysContextCpuTime ds.l 2 ; 0f0, kdp+eb0 ; CPU Time used by System Context
AltContextCpuTime ds.l 2 ; 0f8, kdp+eb4 ; CPU Time used by Alternate Context
Size equ *
endr
;_______________________________________________________________________
; Processor Info Record
;
; Used to pass Processor information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKProcessorInfoPtr equ $5FFFEFD8 ; logical address of ProcessorInfo record
NKProcessorInfoVer equ $5FFFEFDC ; version number of ProcessorInfo record
NKProcessorInfoLen equ $5FFFEFDE ; length of ProcessorInfo record
NKProcessorInfo record 0,increment
ProcessorVersionReg ds.l 1 ; 000, kdp+f20 ; contents of the PVR special purpose register
CpuClockRateHz ds.l 1 ; 004, kdp+f24 ; CPU Clock frequency
BusClockRateHz ds.l 1 ; 008, kdp+f28 ; Bus Clock frequency
DecClockRateHz ds.l 1 ; 00c, kdp+f2c ; Decrementer Clock frequency
Ovr
PageSize ds.l 1 ; 010, kdp+f30 ; number of bytes in a memory page
DataCacheTotalSize ds.l 1 ; 014, kdp+f34 ; number of bytes in the Data Cache
InstCacheTotalSize ds.l 1 ; 018, kdp+f38 ; number of bytes in the Instruction Cache
CoherencyBlockSize ds.w 1 ; 01c, kdp+f3c ; number of bytes in a Coherency Block
ReservationGranuleSize ds.w 1 ; 01e, kdp+f3e ; number of bytes in a Reservation Granule
CombinedCaches ds.w 1 ; 020, kdp+f40 ; 1 <- combined or no cache, 0 <- split cache
InstCacheLineSize ds.w 1 ; 022, kdp+f42 ; number of bytes in a Line of the Instruction Cache
DataCacheLineSize ds.w 1 ; 024, kdp+f44 ; number of bytes in a Line of the Data Cache
DataCacheBlockSizeTouch ds.w 1 ; 026, kdp+f46 ; number of bytes in a Block for DCBT DCBTST
InstCacheBlockSize ds.w 1 ; 028, kdp+f48 ; number of bytes in a Block of the Instruction Cache
DataCacheBlockSize ds.w 1 ; 02a, kdp+f4a ; number of bytes in a Block of the Data Cache
InstCacheAssociativity ds.w 1 ; 02c, kdp+f4c ; Associativity of the Instruction Cache
DataCacheAssociativity ds.w 1 ; 02e, kdp+f4e ; Associativity of the Data Cache
TransCacheTotalSize ds.w 1 ; 030, kdp+f50 ; number of entries in the Translation Cache
TransCacheAssociativity ds.w 1 ; 032, kdp+f52 ; Associativity of the Translation Cache
OvrEnd
org 0x40
Size equ *
endr
;_______________________________________________________________________
; Hardware Info Record
;
; Used to pass hardware information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKHWInfoPtr equ $5FFFEFD0 ; logical address of HWInfo record
NKHWInfoVer equ $5FFFEFD4 ; version number of HWInfo record
NKHWInfoLen equ $5FFFEFD6 ; length of HWInfo record
NKHWInfo record 0,increment
MacROM_Base ds.l 1 ; 000, irp+f00 ; base address (physical) of Mac ROM
DeviceTreeBase ds.l 1 ; 004, irp+f04 ; base address of the copied device tree properties
UniversalInfoTableBase ds.l 1 ; 008, irp+f08 ; base address of the Universal Info Table
ConfigInfoTableBase ds.l 1 ; 00c, irp+f0c ; base address of the Config Info Table
VectorLookupTable ds.l 1 ; 010, irp+f10 ; base address of the interrupt vector lookup table (short *)
VectorMaskTable ds.l 1 ; 014, irp+f14 ; base address of the interrupt vector mask table (long *)
OpenPICBaseAddr ds.l 1 ; 018, irp+f18 ; OpenPIC base address
ISAMaster8259 ds.l 1 ; 01c, irp+f1c ; ISA Master 8259 ports (char *)
ISASlave8259 ds.l 1 ; 020, irp+f20 ; ISA Slave 8259 ports (char *)
InterruptAck8259 ds.l 1 ; 024, irp+f24 ; address to read to ack 8259 interrupt (long *)
; interrupt pending bits (actively changing)
PendingInts ds.l 2 ; 028, irp+f28 ; 64 bits of pending interrupts
; some Mac I/O device base addresses
ADB_Base ds.l 1 ; 030, irp+f30 ; base address of ADB
SCSI_DMA_Base ds.l 1 ; 034, irp+f34 ; base address of SCSI DMA registers
; RTAS related stuff
RTAS_PrivDataArea ds.l 1 ; 038, irp+f38 ; RTAS private data area
MacOS_NVRAM_Offset ds.l 1 ; 03c, irp+f3c ; offset into nvram to MacOS data
RTAS_NVRAM_Fetch ds.l 1 ; 040, irp+f40 ; token for RTAS NVRAM fetch
RTAS_NVRAM_Store ds.l 1 ; 044, irp+f44 ; token for RTAS NVRAM store
RTAS_Get_Clock ds.l 1 ; 048, irp+f48 ; token for RTAS clock get
RTAS_Set_Clock ds.l 1 ; 04c, irp+f4c ; token for RTAS clock set
RTAS_Restart ds.l 1 ; 050, irp+f50 ; token for RTAS Restart
RTAS_Shutdown ds.l 1 ; 054, irp+f54 ; token for RTAS Shutdown
RTAS_Restart_At ds.l 1 ; 058, irp+f58 ; token for RTAS system startup at specified time
RTAS_EventScan ds.l 1 ; 05c, irp+f5c ; token for RTAS event scan
RTAS_Check_Exception ds.l 1 ; 060, irp+f60 ; token for RTAS check exception
RTAS_Read_PCI_Config ds.l 1 ; 064, irp+f64 ; token for RTAS read PCI config
RTAS_Write_PCI_Config ds.l 1 ; 068, irp+f68 ; token for RTAS write PCI config
; SIO interrupt source numbers for the MPIC
SIOIntVect ds.w 1 ; 06c, irp+f6c ; SIO (8259 cascade vector) vector number
SIOIntBit ds.w 1 ; 06e, irp+f6e ; SIO (8259 cascade vector) bit number
Signature ds.l 1 ; 070, irp+f70 ; signature for this record ('Hnfo')
; more interrupt source numbers
SpuriousIntVect ds.w 1 ; 074, irp+f74 ; spurious vector number
CPU_ID ds.w 1 ; 076, irp+f76 ; the ID of this CPU (universal-tables-related)
SCCAIntVect ds.w 1 ; 078, irp+f78 ; SCC A (non-DMA) vector number
SCCBIntVect ds.w 1 ; 07a, irp+f7a ; SCC B (non-DMA) vector number
SCSIIntVect ds.w 1 ; 07c, irp+f7c ; SCSI vector number
SCSIDMAIntVect ds.w 1 ; 07e, irp+f7e ; SCSI DMA vector number
VIAIntVect ds.w 1 ; 080, irp+f80 ; VIA vector number
VIAIntBit ds.w 1 ; 082, irp+f82 ; VIA bit number
ADBIntVect ds.w 1 ; 084, irp+f84 ; vector number
NMIIntVect ds.w 1 ; 086, irp+f86 ; NMI vector number
NMIIntBit ds.w 1 ; 088, irp+f88 ; NMI bit number
; current (actively changing) interrupt handling variables
ISAPendingInt ds.w 1 ; 08a, irp+f8a ; currently pending ISA/8259 interrupt
CompletedInts ds.b 8 ; 08c, irp+f8c ; completed interrupts
nkHWInfoFlagSlowMESH equ 1 ; set if fast MESH doesn't work on this box
nkHWInfoFlagAsynchMESH equ 2 ; set if Synchronous MESH doesn't work on this box
nkHWInfoFlagNoCopySWTLB equ 4 ; set if the software TLB walk code for 603 should NOT be copied
HardwareInfoFlags ds.l 1 ; 094, irp+f94 ; 32 bits of flags (see enum above)
RTAS_Get_PowerOn_Time ds.l 1 ; 098, irp+f98 ; token for RTAS getting time for system startup
align 5 ; pad to nice cache block alignment (did i get this right?)
Size equ *
endr
;_______________________________________________________________________
; Processor State Record
;
; Used to save the state of the processor across sleep.
;_______________________________________________________________________
NKProcessorStatePtr equ $5FFFEFC8 ; logical address of ProcessorState record
NKProcessorStateVer equ $5FFFEFCC ; version number of ProcessorState record
NKProcessorStateLen equ $5FFFEFCE ; length of ProcessorState record
NKProcessorState record 0,increment
saveDBAT0u ds.l 1 ; 000 ; place to store DBAT0U
saveDBAT0l ds.l 1 ; 004 ; place to store DBAT0L
saveDBAT1u ds.l 1 ; 008 ; place to store DBAT1U
saveDBAT1l ds.l 1 ; 00c ; place to store DBAT1L
saveDBAT2u ds.l 1 ; 010 ; place to store DBAT2U
saveDBAT2l ds.l 1 ; 014 ; place to store DBAT2L
saveDBAT3u ds.l 1 ; 018 ; place to store DBAT3U
saveDBAT3l ds.l 1 ; 01c ; place to store DBAT3L
saveIBAT0u ds.l 1 ; 020 ; place to store IBAT0U
saveIBAT0l ds.l 1 ; 024 ; place to store IBAT0L
saveIBAT1u ds.l 1 ; 028 ; place to store IBAT1U
saveIBAT1l ds.l 1 ; 02c ; place to store IBAT1L
saveIBAT2u ds.l 1 ; 030 ; place to store IBAT2U
saveIBAT2l ds.l 1 ; 034 ; place to store IBAT2L
saveIBAT3u ds.l 1 ; 038 ; place to store IBAT3U
saveIBAT3l ds.l 1 ; 03c ; place to store IBAT3L
saveSPRG0 ds.l 1 ; 040 ; place to store SPRG0
saveSPRG1 ds.l 1 ; 044 ; place to store SPRG1
saveSPRG2 ds.l 1 ; 048 ; place to store SPRG2
saveSPRG3 ds.l 1 ; 04c ; place to store SPRG3
saveL2CR ds.l 1 ; 050 ; place to store Arthur's L2CR
saveSRR0 ds.l 1 ; 054 ; place to store SRR0
saveSRR1 ds.l 1 ; 058 ; place to store SRR1
saveTBU ds.l 1 ; 05c ; place to store TBU
saveTBL ds.l 1 ; 060 ; place to store TBL
saveHID0 ds.l 1 ; 064 ; place to store HID0
saveDEC ds.l 1 ; 068 ; place to store DEC
saveMSR ds.l 1 ; 06c ; place to store MSR
saveSDR1 ds.l 1 ; 070 ; place to store SDR1
; saveKernelDataPtr needs to always be right after saveReturnAddr
; because of how the code works. DO NOT CHANGE THIS ORDERING!
saveReturnAddr ds.l 1 ; 074 ; place to store the addr to jump to.
saveKernelDataPtr ds.l 1 ; 078 ; place to store the KernelDataPtr
saveContextPtr ds.l 1 ; 07c ; place to store the ContextPtr
Size equ *
endr

0
NanoKernel/NKColdInts.s → NanoKernel/ColdInts.s
View File

5
NanoKernel/NKSystemCrash.s → NanoKernel/Crash.s
View File

@ -1,4 +1,4 @@
SystemCrash
Crash
mfsprg r1, 0
stw r0, KDP.CrashR0(r1)
@ -128,8 +128,7 @@ SystemCrash
mflr r0
stw r0, KDP.CrashKernReturn(r1)
########################################################################
; Now spin
lis r2, 2 ; Count down from 64k to find a zero
@nonzero
lwzu r0, -4(r2)

2
NanoKernel/NKEquates.s → NanoKernel/Defines.s
View File

@ -80,7 +80,7 @@ maskMsrFlags equ 0x00000F00
########################################################################
; MemRetry flags in CR3
mrSkipInstLoad equ cr3_lt ; misalignment handler need not read the instruction
mrSkipInstLoad equ cr3_lt ; misalignment handler can get what it needs from DSISR
mrXformIgnoreIdxReg equ cr3_gt ; instruction is X-form but without an rB field
mrSuppressUpdate equ cr3_eq ; instruction may not update base reg in-place
mrChangedRegInEWA equ cr3_so ; have "loaded" a new reg value (i.e. saved into EWA)

17
NanoKernel/NKExceptions.s → NanoKernel/Exceptions.s
View File

@ -1,5 +1,9 @@
; MemRetry error
MRException
; Exception was mid-MemRetry, so save MemRetry state to resume later
; MR registers to save: r17 (MR status)
; r18 (EA)
; r19 (EA of byte after memory)
; r20/r21 (loaded data/data to store)
mtsprg 3, r24
lwz r9, KDP.Enables(r1)
@ -42,8 +46,9 @@ MRException
;fall through ; exception enabled => run userspace handler
########################################################################
; Exception or MRException that is Enabled (i.e. not being auto-forced to System)
ExceptionCommon
; (MR)Exception that is Enabled (i.e. not being auto-forced to System)
stw r10, CB.FaultSrcPC+4(r6) ; Save r10/SRR0, r12/LR, r3, r4
stw r12, CB.FaultSrcLR+4(r6)
stw r3, CB.FaultSrcR3+4(r6)
@ -232,19 +237,20 @@ Exception
########################################################################
RunSystemContext
; Switch back from the Alternate context to the 68k Emulator
lwz r9, KDP.ECBPtr(r1) ; System ("Emulator") ContextBlock
addi r8, r1, KDP.VecTblSystem ; System VecTbl
mtsprg 3, r8
bcl BO_IF, bGlobalFlagSystem, SystemCrash ; System Context already running!
bcl BO_IF, bGlobalFlagSystem, CrashExceptions ; System Context already running!
; Fallthru (new CB in r9, old CB in r6)
########################################################################
SwitchContext ; OldCB *r6, NewCB *r9
; Run the System or Alternate Context
; Run the System or Alternate Context
lwz r8, KDP.Enables(r1)
stw r7, CB.InterState.Flags(r6)
stw r8, CB.InterState.Enables(r6)
@ -363,7 +369,8 @@ SwitchContext ; OldCB *r6, NewCB *r9
########################################################################
ReturnFromInt ; If ContextFlagMemRetryErr && ContextFlagResumeMemRetry, please pass KernelState ptr in r9
ReturnFromInt
; (if ContextFlagMemRetryErr && ContextFlagResumeMemRetry, pass KernelState ptr in r9)
andi. r8, r7, ContextFlagTraceWhenDone | ContextFlagMemRetryErr
bnel @special_cases ; Keep rare cases out of the hot path

5
NanoKernel/NKFloatingPt.s → NanoKernel/Floats.s
View File

@ -1,7 +1,6 @@
_align 5
FPUnavailInt
; Reload the FPU
; Reload the FPU
mfsprg r1, 0
stw r11, KDP.FloatingPtTemp1(r1)
lwz r11, KDP.NKInfo.FPUReloadCount(r1)
@ -134,7 +133,7 @@ DisableFPU
########################################################################
; This is used by MemRetry
; Interface between MemRetry integer and float code
MACRO
MakeFloatJumpTable &OPCODE, &DEST, &highest==31

84
NanoKernel/NKHotInts.s → NanoKernel/HotInts.s
View File

@ -1,4 +1,10 @@
_align 6
; Frequently-used interrupt handlers
kHotIntAlign equ 6
########################################################################
_align kHotIntAlign
ExternalInt0
mfsprg r1, 0 ; Init regs and increment ctr
stw r0, KDP.r0(r1)
@ -54,7 +60,7 @@ ExternalInt0
########################################################################
_align 6
_align kHotIntAlign
IntLookupTable
dc.b 0, 1, 2, 2, 4, 4, 4, 4
dc.b 3, 3, 3, 3, 4, 4, 4, 4
@ -65,7 +71,7 @@ IntLookupTable
dc.b 7, 7, 7, 7, 7, 7, 7, 7
dc.b 7, 7, 7, 7, 7, 7, 7, 7
_align 6
_align kHotIntAlign
ExternalInt1
mfsprg r1, 0 ; Init regs and increment ctr
stw r0, KDP.r0(r1)
@ -123,7 +129,7 @@ ExternalInt1
########################################################################
_align 6
_align kHotIntAlign
ExternalInt2
mfsprg r1, 0 ; Init regs and increment ctr
stw r0, KDP.r0(r1)
@ -200,9 +206,9 @@ ExternalInt2
########################################################################
; Increment the Sys/Alt CPU clocks, and the Dec-int counter
_align 6
_align kHotIntAlign
DecrementerIntSys
; Increment the Sys/Alt CPU clocks, and the Dec-int counter
mfsprg r1, 0
stmw r2, KDP.r2(r1)
mfdec r31
@ -257,8 +263,8 @@ DecrementerIntAlt
########################################################################
_align 6
DataStorageInt
_align kHotIntAlign
DataStorageInt ; to MemRetry! (see MROptab.s for register info)
mfsprg r1, 0
stmw r2, KDP.r2(r1)
mfsprg r11, 1
@ -273,47 +279,47 @@ DataStorageInt
mfmsr r14
_ori r15, r14, MsrDR
mtmsr r15
lwz r27, 0(r10) ; r27 = INSTRUCTION
lwz r27, 0(r10) ; r27 = instruction
mtmsr r14
EmulateDataAccess
rlwinm. r18, r27, 18, 25, 29 ; r16 = 4 * rA (r0 wired to 0)
rlwinm. r18, r27, 18, 25, 29 ; r16 = 4 * rA (r0 wired to 0)
lwz r25, KDP.MRBase(r1)
li r21, 0
beq @r0
lwzx r18, r1, r18 ; r16 = contents of rA
lwzx r18, r1, r18 ; r16 = contents of rA
@r0
andis. r26, r27, 0xec00 ; intended to extract the major opcode? seems wrong though!
andis. r26, r27, 0xec00 ; determine instruction form
lwz r16, KDP.Flags(r1)
mfsprg r24, 3
rlwinm r17, r27, 0, 6, 15 ; r17 = rS/D and rA fields
rlwimi r16, r16, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE
rlwinm r17, r27, 0, 6, 15 ; set MR status reg
_mvbit r16, bContextFlagTraceWhenDone, r16, bMsrSE
bge @xform
;dform
rlwimi r25, r27, 7, 26, 29
rlwimi r25, r27, 12, 25, 25
lwz r26, MROptabD-MRBase(r25) ; table of 4b elements, index = major opcode bits 51234 (this is the last quarter of MROptabX)
extsh r23, r27 ; r23 = register offset field, sign-extended
lwz r26, MROptabD-MRBase(r25) ; last quarter of the X-form table, index = major opcode bits 51234
extsh r23, r27 ; r23 = register offset field, sign-extended
rlwimi r25, r26, 26, 22, 29
mtlr r25 ; dest = r25 = first of two function ptrs in table entry
mtcr r26 ; using the flags in the arbitrary upper 16 bits of the table entry?
add r18, r18, r23 ; r18 = effective address attempted by instruction
rlwimi r17, r26, 6, 26, 5 ; r17 = pretend X-form inst with: maj opcode (from tbl), rS/D and RA (from inst), min opcode (from tbl)
mtlr r25 ; dest = r25 = first of two function ptrs in table entry
mtcr r26 ; using the flags in the arbitrary upper 16 bits of the table entry?
add r18, r18, r23 ; r18 = EA
rlwimi r17, r26, 6, 26, 5 ; set MR status reg
blr
@xform
rlwimi r25, r27, 27, 26, 29
rlwimi r25, r27, 0, 25, 25
rlwimi r25, r27, 6, 23, 24
lwz r26, MROptabX-MRBase(r25) ; table of 4b elements, index = minor (x-form) opcode bits 8940123
rlwinm r23, r27, 23, 25, 29 ; r23 = 4 * rB
rlwimi r25, r26, 26, 22, 29
mtlr r25 ; dest = r25 = first of two function ptrs in table entry
lwz r26, MROptabX-MRBase(r25) ; index = extended opcode bits 8940123
rlwinm r23, r27, 23, 25, 29 ; need to calculate EA (this part gets rB)
rlwimi r25, r26, 26, 22, 29 ; prepare to jump to the primary routine
mtlr r25
mtcr r26
lwzx r23, r1, r23 ; get rB from saved registers
rlwimi r17, r26, 6, 26, 5 ; r17 = pretend X-form inst with: maj opcode (from tbl), rS/D and RA (from inst), min opcode (from tbl)
add r18, r18, r23 ; r18 = effective address attempted by instruction
lwzx r23, r1, r23 ; get rB from saved registers
rlwimi r17, r26, 6, 26, 5 ; set MR status reg)
add r18, r18, r23 ; r18 = EA
bclr BO_IF_NOT, mrXformIgnoreIdxReg
neg r23, r23
add r18, r18, r23
@ -321,8 +327,8 @@ EmulateDataAccess
########################################################################
_align 6
AlignmentInt
_align kHotIntAlign
AlignmentInt ; to MemRetry! (see MROptab.s for register info)
mfsprg r1, 0
stmw r2, KDP.r2(r1)
@ -342,28 +348,28 @@ AlignmentInt
mfdsisr r27
mfdar r18
extrwi. r21, r27, 2, 15 ; evaluate hi two bits of XO (or 0 for d-form?)
extrwi. r21, r27, 2, 15 ; determine instruction form using DSISR
lwz r25, KDP.MRBase(r1)
rlwinm r17, r27, 16, 0x03FF0000
rlwinm r17, r27, 16, 0x03FF0000 ; insert rS/rD field from DSISR into MR status reg
lwz r16, KDP.Flags(r1)
rlwimi r25, r27, 24, 23, 29 ; add constant fields from dsisr (*4) to FDP
rlwimi r16, r16, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE
rlwimi r25, r27, 24, 23, 29 ; look up DSISR opcode field in MROptab
_mvbit r16, bContextFlagTraceWhenDone, r16, bMsrSE
bne @xform
;dform
lwz r26, MROptabD-MRBase(r25) ; use upper quarter of table
lwz r26, MROptabD-MRBase(r25) ; last quarter of the X-form table, index = major opcode bits 51234
mfmsr r14
rlwimi r25, r26, 26, 22, 29 ; third byte of lookup value is a /4 code offset in FDP
mtlr r25 ; so get ready to go there
rlwimi r25, r26, 26, 22, 29 ; prepare to jump to the primary routine
mtlr r25
_ori r15, r14, MsrDR
mtcr r26
rlwimi r17, r26, 6, 26, 5 ; wrap some shite around the register values
rlwimi r17, r26, 6, 26, 5 ; set the rest of the MR status register
blr
@xform
lwz r26, MROptabX-MRBase(r25)
lwz r26, MROptabX-MRBase(r25) ; index = extended opcode bits 8940123
mfmsr r14
rlwimi r25, r26, 26, 22, 29
rlwimi r25, r26, 26, 22, 29 ; prepare to jump to the primary routine
mtlr r25
_ori r15, r14, MsrDR
mtcr r26

2
NanoKernel/NKInit.s → NanoKernel/Init.s
View File

@ -1,4 +1,4 @@
; Registers passed in by HardwareInit
; Entry point of kernel. Registers on entry:
rCI set r3 ; NKConfigurationInfo
rPI set r4 ; NKProcessorInfo
rSI set r5 ; NKSystemInfo

2
NanoKernel/MRInterrupts.s → NanoKernel/MRInts.s
View File

@ -11,7 +11,7 @@ MRDataStorageInt ; Consult DSISR and the page table to decide what to do
li r28, 0x43 ; Filter Writethru and Protection bits
and r28, r31, r28
cmpwi cr7, r28, 0x43
beql SystemCrash ; Not illegal data access => Crash
beql CrashMRInts ; Not illegal data access => Crash
mfsprg r28, 2
mtlr r28
bne cr7, @access_exception ; Any filtered bit unset => Exception

2
NanoKernel/MRMemtab.s
View File

@ -1,5 +1,5 @@
; Indexing this table:
; bits 0-23 MRCode
; bits 0-23 MRBase
; bits 24-26 number of bytes to access minus one
; bit 27 one for load, zero for store
; bits 28-30 bottom three bits of adjusted EA

15
NanoKernel/MROptab.s
View File

@ -1,3 +1,18 @@
; MemRetry entry point from DSI and Alignment interrupt handlers
; The interrupt handler that calls one of the "primary" routines
; should store all userspace registers in the EWA and set these:
; r14 = saved MSR
; r14 = saved MSR + MSR[DR]
; r16 = flags
; r17 = MR status (0-5 MRRestab entry || 6-10 src/dest register || 11-15 base register || 21-25 ?? || 26-30 access len || 31 0=Store/1=Load)
; r18 = EA being accessed
; r24 = saved VecBase
; r25 = MRCode pointer (lower 10 bits can be "dirty")
; r26 = MROptab entry (sec routine ptr in low 8 bits might be set on DSI)
; r27 = instruction (optional if mrSkipInstLoad is set below)
; r28 = offset of register field in EWA (= reg num * 4)
MACRO
optabRow &myAccLen, &myLoadStore, &resLabel, &myFlags, &primLabel, &secLabel
_L set 1

2
NanoKernel/MROptabCode.s
View File

@ -1,5 +1,5 @@
MRPriCrash
bl SystemCrash
bl Crash
MRSecException
b MRSecException2

2
NanoKernel/MRRestab.s
View File

@ -1,3 +1,5 @@
; Lookup table when resuming MemRetry after an MRException has been handled
MACRO
restabLine &myFlags, &secLabel
DC.B &myFlags

0
NanoKernel/NKMacros.s → NanoKernel/Macros.s
View File

27
NanoKernel/NKMakeFile
View File

@ -1,27 +0,0 @@
# I expect these variables to be set already:
# NKDir, NKIncDir, NKBin
NKFiles = ¶
{NKDir}NanoKernel.s ¶
{NKDir}NKMacros.s ¶
{NKDir}NKEquates.s ¶
{NKDir}NKInit.s ¶
{NKDir}NKSystemCrash.s ¶
{NKDir}NKHotInts.s ¶
{NKDir}NKColdInts.s ¶
{NKDir}MROptabCode.s ¶
{NKDir}MRMemtabCode.s ¶
{NKDir}MRInterrupts.s ¶
{NKDir}MROptab.s ¶
{NKDir}MRMemtab.s ¶
{NKDir}MRRestab.s ¶
{NKDir}NKMemory.s ¶
{NKDir}NKExceptions.s ¶
{NKDir}NKFloatingPt.s ¶
{NKDir}NKSoftInts.s ¶
{NKDir}NKReset.s ¶
{NKDir}NKLegacyVM.s ¶
# We get warning 3202 from ALIGN directives -- kill it
{NKBin} Ä {NKDir}NanoKernel.s {NKFiles}
PPCAsm -o {Targ} -w 3202 -i {NKIncDir} -i "{AIncludes}" {NKDir}NanoKernel.s

52
NanoKernel/NanoKernel.s
View File

@ -1,43 +1,27 @@
include 'InfoRecords.a'
include 'NKMacros.s'
include 'NKEquates.s'
; These "include" directives mean "Insert this file's contents here."
include 'PPCInfoRecordsPriv.s'
include 'Macros.s'
include 'Defines.s'
CodeBase
include 'NKInit.s'
include 'NKSystemCrash.s'
include 'NKHotInts.s'
; Persistent MemRetry registers:
; r17 = status (0-5 MRRestab entry || 6-10 src/dest register || 11-15 base register || 21-25 ?? || 26-30 access len || 31 0=Store/1=Load)
; r18 = EA of memory
; r19 = EA of byte after memory
; r20/r21 = loaded data/data to store
; Other MemRetry registers:
; r14 = saved MSR
; r15 = temp MSR
; r16 = Flags
; r22/r23 = scratch
; r24 = saved VecBase
; r25 = MemRetry ptr (do not trust low 10 bits)
; r26 = Optab entry (sec routine ptr in low 8 bits might be set on DSI)
; r27 = instruction
; r28 = offset of register field in EWA (= reg num * 4)
; r29/r31 = scratch
include 'Init.s'
CrashMRInts
CrashPageTable
CrashExceptions
CrashVirtualMem
include 'Crash.s'
include 'HotInts.s'
_align 10
MRBase
include 'MROptabCode.s'
include 'MRMemtabCode.s'
include 'MRInterrupts.s'
include 'MRInts.s'
include 'MROptab.s'
include 'MRMemtab.s'
include 'MRRestab.s'
include 'NKColdInts.s'
include 'NKMemory.s'
include 'NKExceptions.s'
include 'NKFloatingPt.s'
include 'NKSoftInts.s'
include 'NKLegacyVM.s'
include 'ColdInts.s'
include 'PageTable.s'
include 'Exceptions.s'
include 'Floats.s'
include 'SoftInts.s'
include 'VirtualMem.s'

440
NanoKernel/PPCInfoRecordsPriv.s Normal file
View File

@ -0,0 +1,440 @@
;_______________________________________________________________________
; Configuration Info Record
; Used to pass Configuration information from the Boot Program to the
; NanoKernel for data structure and address mapping initialization.
;_______________________________________________________________________
NKConfigurationInfo record 0,increment
ROMByteCheckSums ds.l 8 ; 000 ; ROM Checksums - one word for each of 8 byte lanes
ROMCheckSum64 ds.l 2 ; 020 ; ROM Checksum - 64 bit sum of doublewords
ROMImageBaseOffset ds.l 1 ; 028 ; Offset of Base of total ROM image
ROMImageSize ds.l 1 ; 02c ; Number of bytes in ROM image
ROMImageVersion ds.l 1 ; 030 ; ROM Version number for entire ROM
Mac68KROMOffset ds.l 1 ; 034 ; Offset of base of Macintosh 68K ROM
Mac68KROMSize ds.l 1 ; 038 ; Number of bytes in Macintosh 68K ROM
ExceptionTableOffset ds.l 1 ; 03c ; Offset of base of PowerPC Exception Table Code
ExceptionTableSize ds.l 1 ; 040 ; Number of bytes in PowerPC Exception Table Code
HWInitCodeOffset ds.l 1 ; 044 ; Offset of base of Hardware Init Code (field moved!)
HWInitCodeSize ds.l 1 ; 048 ; Number of bytes in Hardware Init Code
KernelCodeOffset ds.l 1 ; 04c ; Offset of base of NanoKernel Code
KernelCodeSize ds.l 1 ; 050 ; Number of bytes in NanoKernel Code
EmulatorCodeOffset ds.l 1 ; 054 ; Offset of base of Emulator Code
EmulatorCodeSize ds.l 1 ; 058 ; Number of bytes in Emulator Code
OpcodeTableOffset ds.l 1 ; 05c ; Offset of base of Opcode Table
OpcodeTableSize ds.l 1 ; 060 ; Number of bytes in Opcode Table
BootstrapVersion ds.b 16 ; 064 ; Bootstrap loader version info
BootVersionOffset ds.l 1 ; 074 ; offset within EmulatorData of BootstrapVersion
ECBOffset ds.l 1 ; 078 ; offset within EmulatorData of ECB
IplValueOffset ds.l 1 ; 07c ; offset within EmulatorData of IplValue
EmulatorEntryOffset ds.l 1 ; 080 ; offset within Emulator Code of entry point
KernelTrapTableOffset ds.l 1 ; 084 ; offset within Emulator Code of KernelTrapTable
TestIntMaskInit ds.l 1 ; 088 ; initial value for test interrupt mask
ClearIntMaskInit ds.l 1 ; 08c ; initial value for clear interrupt mask
PostIntMaskInit ds.l 1 ; 090 ; initial value for post interrupt mask
LA_InterruptCtl ds.l 1 ; 094 ; logical address of Interrupt Control I/O page
InterruptHandlerKind ds.b 1 ; 098 ; kind of handler to use
ds.b 3 ; 099 ; filler
LA_InfoRecord ds.l 1 ; 09c ; logical address of InfoRecord page
LA_KernelData ds.l 1 ; 0a0 ; logical address of KernelData page
LA_EmulatorData ds.l 1 ; 0a4 ; logical address of EmulatorData page
LA_DispatchTable ds.l 1 ; 0a8 ; logical address of Dispatch Table
LA_EmulatorCode ds.l 1 ; 0ac ; logical address of Emulator Code
MacLowMemInitOffset ds.l 1 ; 0b0 ; offset to list of LowMem addr/data values
PageAttributeInit ds.l 1 ; 0b4 ; default WIMG/PP settings for PTE creation
PageMapInitSize ds.l 1 ; 0b8 ; size of page mapping info
PageMapInitOffset ds.l 1 ; 0bc ; offset to page mapping info (from base of ConfigInfo)
PageMapIRPOffset ds.l 1 ; 0c0 ; offset of InfoRecord map info (from base of PageMap)
PageMapKDPOffset ds.l 1 ; 0c4 ; offset of KernelData map info (from base of PageMap)
PageMapEDPOffset ds.l 1 ; 0c8 ; offset of EmulatorData map info (from base of PageMap)
SegMaps
SegMap32SupInit ds.l 32 ; 0cc ; 32 bit mode Segment Map Supervisor space
SegMap32UsrInit ds.l 32 ; 14c ; 32 bit mode Segment Map User space
SegMap32CPUInit ds.l 32 ; 1cc ; 32 bit mode Segment Map CPU space
SegMap32OvlInit ds.l 32 ; 24c ; 32 bit mode Segment Map Overlay mode
BATRangeInit ds.l 32 ; 2cc ; BAT mapping ranges
BatMap32SupInit ds.l 1 ; 34c ; 32 bit mode BAT Map Supervisor space
BatMap32UsrInit ds.l 1 ; 350 ; 32 bit mode BAT Map User space
BatMap32CPUInit ds.l 1 ; 354 ; 32 bit mode BAT Map CPU space
BatMap32OvlInit ds.l 1 ; 358 ; 32 bit mode BAT Map Overlay mode
SharedMemoryAddr ds.l 1 ; 35c ; physical address of Mac/Smurf shared message mem
PA_RelocatedLowMemInit ds.l 1 ; 360 ; physical address of RelocatedLowMem
OpenFWBundleOffset ds.l 1 ; 364 ; Offset of base of OpenFirmware PEF Bundle
OpenFWBundleSize ds.l 1 ; 368 ; Number of bytes in OpenFirmware PEF Bundle
LA_OpenFirmware ds.l 1 ; 36c ; logical address of Open Firmware
PA_OpenFirmware ds.l 1 ; 370 ; physical address of Open Firmware
LA_HardwarePriv ds.l 1 ; 374 ; logical address of HardwarePriv callback
align 5 ; pad to nice cache block alignment
endr
;_______________________________________________________________________
; System Info Record
;
; Used to pass System information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKSystemInfoPtr equ $5FFFEFF0 ; logical address of NKSystemInfo record
NKSystemInfoVer equ $5FFFEFF4 ; version number of NKSystemInfo record
NKSystemInfoLen equ $5FFFEFF6 ; length of NKSystemInfo record
NKSystemInfo record 0,increment
PhysicalMemorySize ds.l 1 ; 000 ; Number of bytes in Physical RAM
UsableMemorySize ds.l 1 ; 004 ; Number of bytes in Usable RAM
LogicalMemorySize ds.l 1 ; 008 ; Number of bytes in Logical RAM
HashTableSize ds.l 1 ; 00c ; Number of bytes in Memory Hash Table
L2DataCacheTotalSize ds.l 1 ; 010 ; number of bytes in the L2 Data Cache
L2InstCacheTotalSize ds.l 1 ; 014 ; number of bytes in the L2 Instruction Cache
L2CombinedCaches ds.w 1 ; 018 ; 1 <- combined or no cache, 0 <- split cache
L2InstCacheBlockSize ds.w 1 ; 01a ; number of bytes in a Block of the L2 Instruction Cache
L2DataCacheBlockSize ds.w 1 ; 01c ; number of bytes in a Block of the L2 Data Cache
L2InstCacheAssociativity ds.w 1 ; 01e ; Associativity of the L2 Instruction Cache
L2DataCacheAssociativity ds.w 1 ; 020 ; Associativity of the L2 Data Cache
ds.b 2 ; 022 ; unused
ds.b 2 ; 024 ; unused
FlashManufacturerCode ds.b 1 ; 026 ; Flash ROM Manufacturer code
FlashDeviceCode ds.b 1 ; 027 ; Flash ROM Device code
FlashStart ds.l 1 ; 028 ; Starting address of Flash ROM
FlashSize ds.l 1 ; 02c ; Number of bytes in Flash ROM
Bank0Start ds.l 1 ; 030 ; Starting address of RAM bank 0
Bank0Size ds.l 1 ; 034 ; Number of bytes in RAM bank 0
Bank1Start ds.l 1 ; 038 ; Starting address of RAM bank 1
Bank1Size ds.l 1 ; 03c ; Number of bytes in RAM bank 1
Bank2Start ds.l 1 ; 040 ; Starting address of RAM bank 2
Bank2Size ds.l 1 ; 044 ; Number of bytes in RAM bank 2
Bank3Start ds.l 1 ; 048 ; Starting address of RAM bank 3
Bank3Size ds.l 1 ; 04c ; Number of bytes in RAM bank 3
Bank4Start ds.l 1 ; 050 ; Starting address of RAM bank 4
Bank4Size ds.l 1 ; 054 ; Number of bytes in RAM bank 4
Bank5Start ds.l 1 ; 058 ; Starting address of RAM bank 5
Bank5Size ds.l 1 ; 05c ; Number of bytes in RAM bank 5
Bank6Start ds.l 1 ; 060 ; Starting address of RAM bank 6
Bank6Size ds.l 1 ; 064 ; Number of bytes in RAM bank 6
Bank7Start ds.l 1 ; 068 ; Starting address of RAM bank 7
Bank7Size ds.l 1 ; 06c ; Number of bytes in RAM bank 7
Bank8Start ds.l 1 ; 070 ; Starting address of RAM bank 8
Bank8Size ds.l 1 ; 074 ; Number of bytes in RAM bank 8
Bank9Start ds.l 1 ; 078 ; Starting address of RAM bank 9
Bank9Size ds.l 1 ; 07c ; Number of bytes in RAM bank 9
Bank10Start ds.l 1 ; 080 ; Starting address of RAM bank 10
Bank10Size ds.l 1 ; 084 ; Number of bytes in RAM bank 10
Bank11Start ds.l 1 ; 088 ; Starting address of RAM bank 11
Bank11Size ds.l 1 ; 08c ; Number of bytes in RAM bank 11
Bank12Start ds.l 1 ; 090 ; Starting address of RAM bank 12
Bank12Size ds.l 1 ; 094 ; Number of bytes in RAM bank 12
Bank13Start ds.l 1 ; 098 ; Starting address of RAM bank 13
Bank13Size ds.l 1 ; 09c ; Number of bytes in RAM bank 13
Bank14Start ds.l 1 ; 0a0 ; Starting address of RAM bank 14
Bank14Size ds.l 1 ; 0a4 ; Number of bytes in RAM bank 14
Bank15Start ds.l 1 ; 0a8 ; Starting address of RAM bank 15
Bank15Size ds.l 1 ; 0ac ; Number of bytes in RAM bank 15
align 32 ; pad to nice cache block alignment
MaxBanks equ 16 ; 16 banks, 0...15
Size equ *
endr
;_______________________________________________________________________
; Diagnostic Info Record
;
; Used to pass Diagnostic information from the power on Diagnostics to
; the NanoKernel, and from the NanoKernel to user mode software.
;_______________________________________________________________________
NKDiagInfoPtr equ $5FFFEFE8 ; logical address of DiagnosticInfo record
NKDiagInfoVer equ $5FFFEFEC ; version number of DiagnosticInfo record
NKDiagInfoLen equ $5FFFEFEE ; length of DiagnosticInfo record
NKDiagInfo record 0,increment
BankMBFailOffset ds.l 1 ; 000 ; Mother Board RAM failure code
BankAFailOffset ds.l 1 ; 004 ; Bank A RAM failure code
BankBFailOffset ds.l 1 ; 008 ; Bank B RAM failure code
BankCFailOffset ds.l 1 ; 00c ; Bank C RAM failure code
BankDFailOffset ds.l 1 ; 010 ; Bank D RAM failure code
BankEFailOffset ds.l 1 ; 014 ; Bank E RAM failure code
BankFFailOffset ds.l 1 ; 018 ; Bank F RAM failure code
BankGFailOffset ds.l 1 ; 01c ; Bank G RAM failure code
BankHFailOffset ds.l 1 ; 020 ; Bank H RAM failure code
CacheFailOffset ds.l 1 ; 024 ; cache failure code
LongBootParamOffset ds.l 1 ; 028 ; on longBoot this is where the params will be
POSTTraceOffset ds.l 1 ; 02c ; this tells us what route the POST took
POSTOldWarmOffset ds.l 1 ; 030 ; logged address of old warmstart flag
POSTOldLongOffset ds.l 1 ; 034 ; logged address of old long boot flag
POSTOldGlobbOffset ds.l 1 ; 038 ; logged address of old Diagnostic Info Record
POSTOldParamOffset ds.l 1 ; 03c ; the params from the old diag globb
POSTStartRTCUOffset ds.l 1 ; 040 ; PPC Real Time Clock Upper at start of POST
POSTStartRTCLOffset ds.l 1 ; 044 ; PPC Real Time Clock Lower at start of POST
POSTEndRTCUOffset ds.l 1 ; 048 ; PPC Real Time Clock Upper at end of POST
POSTEndRTCLOffset ds.l 1 ; 04c ; PPC Real Time Clock Lower at end of POST
POSTTestTypeOffset ds.l 1 ; 050 ; when long RAM tests fail test type which failed is put here
POSTError2Offset ds.l 1 ; 054 ; result codes from tests
POSTError3Offset ds.l 1 ; 058 ; result codes from tests
POSTError4Offset ds.l 1 ; 05c ; result codes from tests
RegistersStore ds.b 140 ; 060 ; store all 60x registers here, still fit into 256 bytes size.
; Everything BEFORE here is new (hence the funny-sized register store)
DiagPOSTResult2 ds.l 1 ; 0ec ; POST results
DiagPOSTResult1 ds.l 1 ; 0f0 ; POST results
DiagLongBootSig ds.l 1 ; 0f4 ; Burn in restart flag
DiagWarmStartHigh ds.l 1 ; 0f8 ; First long of native warm start (WLSC) <SM44>
DiagWarmStartLow ds.l 1 ; 0fc ; Second long of native warm start (SamB) <SM44>
align 5 ; pad to nice cache block alignment
Size equ *
endr
;_______________________________________________________________________
; NanoKernel Info Record
;
; Used to pass NanoKernel statistics from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKNanoKernelInfoPtr equ $5FFFEFE0 ; logical address of NanoKernelInfo record
NKNanoKernelInfoVer equ $5FFFEFE4 ; version number of NanoKernelInfo record
NKNanoKernelInfoLen equ $5FFFEFE6 ; length of NanoKernelInfo record
NKNanoKernelInfo record 0,increment
ExceptionCauseCounts ds.l 32 ; 000 ; counters per exception cause
NanoKernelCallCounts ds.l 16 ; 080 ; counters per NanoKernel call
ExternalIntCount ds.l 1 ; 0c0 ; count of External Interrupts
MisalignmentCount ds.l 1 ; 0c4 ; count of Misalignment Interrupts
FPUReloadCount ds.l 1 ; 0c8 ; count of FPU reloads on demand
DecrementerIntCount ds.l 1 ; 0cc ; count of Decrementer Interrupts
QuietWriteCount ds.l 1 ; 0d0 ; count of Writes to Quiet Read-Only memory
HashTableCreateCount ds.l 1 ; 0d4 ; count of Hash Table Entry creations
HashTableDeleteCount ds.l 1 ; 0d8 ; count of Hash Table Entry deletions
HashTableOverflowCount ds.l 1 ; 0dc ; count of Hash Table Entry overflows
EmulatedUnimpInstCount ds.l 1 ; 0e0 ; count of Emulated unimplemented instructions
NCBPtrCacheMissCount ds.l 1 ; 0e4 ; count of NCB Pointer cache misses
ExceptionPropagateCount ds.l 1 ; 0e8 ; count of Exceptions propagated to system
ExceptionForcedCount ds.l 1 ; 0ec ; count of Exceptions forced to system
SysContextCpuTime ds.l 2 ; 0f0 ; CPU Time used by System Context
AltContextCpuTime ds.l 2 ; 0f8 ; CPU Time used by Alternate Context
Size equ *
endr
;_______________________________________________________________________
; Processor Info Record
;
; Used to pass Processor information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKProcessorInfoPtr equ $5FFFEFD8 ; logical address of ProcessorInfo record
NKProcessorInfoVer equ $5FFFEFDC ; version number of ProcessorInfo record
NKProcessorInfoLen equ $5FFFEFDE ; length of ProcessorInfo record
NKProcessorInfo record 0,increment
ProcessorVersionReg ds.l 1 ; 000 ; contents of the PVR special purpose register
CpuClockRateHz ds.l 1 ; 004 ; CPU Clock frequency
BusClockRateHz ds.l 1 ; 008 ; Bus Clock frequency
DecClockRateHz ds.l 1 ; 00c ; Decrementer Clock frequency
PageSize ds.l 1 ; 010 ; number of bytes in a memory page
DataCacheTotalSize ds.l 1 ; 014 ; number of bytes in the Data Cache
InstCacheTotalSize ds.l 1 ; 018 ; number of bytes in the Instruction Cache
CoherencyBlockSize ds.w 1 ; 01c ; number of bytes in a Coherency Block
ReservationGranuleSize ds.w 1 ; 01e ; number of bytes in a Reservation Granule
CombinedCaches ds.w 1 ; 020 ; 1 <- combined or no cache, 0 <- split cache
InstCacheLineSize ds.w 1 ; 022 ; number of bytes in a Line of the Instruction Cache
DataCacheLineSize ds.w 1 ; 024 ; number of bytes in a Line of the Data Cache
DataCacheBlockSizeTouch ds.w 1 ; 026 ; number of bytes in a Block for DCBT DCBTST
InstCacheBlockSize ds.w 1 ; 028 ; number of bytes in a Block of the Instruction Cache
DataCacheBlockSize ds.w 1 ; 02a ; number of bytes in a Block of the Data Cache
InstCacheAssociativity ds.w 1 ; 02c ; Associativity of the Instruction Cache
DataCacheAssociativity ds.w 1 ; 02e ; Associativity of the Data Cache
TransCacheTotalSize ds.w 1 ; 030 ; number of entries in the Translation Cache
TransCacheAssociativity ds.w 1 ; 032 ; Associativity of the Translation Cache
align 5 ; pad to nice cache block alignment
Size equ *
endr
;_______________________________________________________________________
; Hardware Info Record
;
; Used to pass hardware information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKHWInfoPtr equ $5FFFEFD0 ; logical address of HWInfo record
NKHWInfoVer equ $5FFFEFD4 ; version number of HWInfo record
NKHWInfoLen equ $5FFFEFD6 ; length of HWInfo record
NKHWInfo record 0,increment
MacROM_Base ds.l 1 ; 000 ; base address (physical) of Mac ROM
DeviceTreeBase ds.l 1 ; 004 ; base address of the copied device tree properties
UniversalInfoTableBase ds.l 1 ; 008 ; base address of the Universal Info Table
ConfigInfoTableBase ds.l 1 ; 00c ; base address of the Config Info Table
VectorLookupTable ds.l 1 ; 010 ; base address of the interrupt vector lookup table (short *)
VectorMaskTable ds.l 1 ; 014 ; base address of the interrupt vector mask table (long *)
OpenPICBaseAddr ds.l 1 ; 018 ; OpenPIC base address
ISAMaster8259 ds.l 1 ; 01c ; ISA Master 8259 ports (char *)
ISASlave8259 ds.l 1 ; 020 ; ISA Slave 8259 ports (char *)
InterruptAck8259 ds.l 1 ; 024 ; address to read to ack 8259 interrupt (long *)
; interrupt pending bits (actively changing)
PendingInts ds.l 2 ; 028 ; 64 bits of pending interrupts
; some Mac I/O device base addresses
ADB_Base ds.l 1 ; 030 ; base address of ADB
SCSI_DMA_Base ds.l 1 ; 034 ; base address of SCSI DMA registers
; RTAS related stuff
RTAS_PrivDataArea ds.l 1 ; 038 ; RTAS private data area
MacOS_NVRAM_Offset ds.l 1 ; 03c ; offset into nvram to MacOS data
RTAS_NVRAM_Fetch ds.l 1 ; 040 ; token for RTAS NVRAM fetch
RTAS_NVRAM_Store ds.l 1 ; 044 ; token for RTAS NVRAM store
RTAS_Get_Clock ds.l 1 ; 048 ; token for RTAS clock get
RTAS_Set_Clock ds.l 1 ; 04c ; token for RTAS clock set
RTAS_Restart ds.l 1 ; 050 ; token for RTAS Restart
RTAS_Shutdown ds.l 1 ; 054 ; token for RTAS Shutdown
RTAS_Restart_At ds.l 1 ; 058 ; token for RTAS system startup at specified time
RTAS_EventScan ds.l 1 ; 05c ; token for RTAS event scan
RTAS_Check_Exception ds.l 1 ; 060 ; token for RTAS check exception
RTAS_Read_PCI_Config ds.l 1 ; 064 ; token for RTAS read PCI config
RTAS_Write_PCI_Config ds.l 1 ; 068 ; token for RTAS write PCI config
; SIO interrupt source numbers for the MPIC
SIOIntVect ds.w 1 ; 06c ; SIO (8259 cascade vector) vector number
SIOIntBit ds.w 1 ; 06e ; SIO (8259 cascade vector) bit number
Signature ds.l 1 ; 070 ; signature for this record ('Hnfo')
; more interrupt source numbers
SpuriousIntVect ds.w 1 ; 074 ; spurious vector number
CPU_ID ds.w 1 ; 076 ; the ID of this CPU (universal-tables-related)
SCCAIntVect ds.w 1 ; 078 ; SCC A (non-DMA) vector number
SCCBIntVect ds.w 1 ; 07a ; SCC B (non-DMA) vector number
SCSIIntVect ds.w 1 ; 07c ; SCSI vector number
SCSIDMAIntVect ds.w 1 ; 07e ; SCSI DMA vector number
VIAIntVect ds.w 1 ; 080 ; VIA vector number
VIAIntBit ds.w 1 ; 082 ; VIA bit number
ADBIntVect ds.w 1 ; 084 ; vector number
NMIIntVect ds.w 1 ; 086 ; NMI vector number
NMIIntBit ds.w 1 ; 088 ; NMI bit number
; current (actively changing) interrupt handling variables
ISAPendingInt ds.w 1 ; 08a ; currently pending ISA/8259 interrupt
CompletedInts ds.b 8 ; 08c ; completed interrupts
nkHWInfoFlagSlowMESH equ 1 ; set if fast MESH doesn't work on this box
nkHWInfoFlagAsynchMESH equ 2 ; set if Synchronous MESH doesn't work on this box
nkHWInfoFlagNoCopySWTLB equ 4 ; set if the software TLB walk code for 603 should NOT be copied
HardwareInfoFlags ds.l 1 ; 094 ; 32 bits of flags (see enum above)
RTAS_Get_PowerOn_Time ds.l 1 ; 098 ; token for RTAS getting time for system startup
align 5 ; pad to nice cache block alignment
Size equ *
endr
;_______________________________________________________________________
; Processor State Record
;
; Used to save the state of the processor across sleep.
;_______________________________________________________________________
NKProcessorStatePtr equ $5FFFEFC8 ; logical address of ProcessorState record
NKProcessorStateVer equ $5FFFEFCC ; version number of ProcessorState record
NKProcessorStateLen equ $5FFFEFCE ; length of ProcessorState record
NKProcessorState record 0,increment
saveDBAT0u ds.l 1 ; 000 ; place to store DBAT0U
saveDBAT0l ds.l 1 ; 004 ; place to store DBAT0L
saveDBAT1u ds.l 1 ; 008 ; place to store DBAT1U
saveDBAT1l ds.l 1 ; 00c ; place to store DBAT1L
saveDBAT2u ds.l 1 ; 010 ; place to store DBAT2U
saveDBAT2l ds.l 1 ; 014 ; place to store DBAT2L
saveDBAT3u ds.l 1 ; 018 ; place to store DBAT3U
saveDBAT3l ds.l 1 ; 01c ; place to store DBAT3L
saveIBAT0u ds.l 1 ; 020 ; place to store IBAT0U
saveIBAT0l ds.l 1 ; 024 ; place to store IBAT0L
saveIBAT1u ds.l 1 ; 028 ; place to store IBAT1U
saveIBAT1l ds.l 1 ; 02c ; place to store IBAT1L
saveIBAT2u ds.l 1 ; 030 ; place to store IBAT2U
saveIBAT2l ds.l 1 ; 034 ; place to store IBAT2L
saveIBAT3u ds.l 1 ; 038 ; place to store IBAT3U
saveIBAT3l ds.l 1 ; 03c ; place to store IBAT3L
saveSPRG0 ds.l 1 ; 040 ; place to store SPRG0
saveSPRG1 ds.l 1 ; 044 ; place to store SPRG1
saveSPRG2 ds.l 1 ; 048 ; place to store SPRG2
saveSPRG3 ds.l 1 ; 04c ; place to store SPRG3
saveL2CR ds.l 1 ; 050 ; place to store Arthur's L2CR
saveSRR0 ds.l 1 ; 054 ; place to store SRR0
saveSRR1 ds.l 1 ; 058 ; place to store SRR1
saveTBU ds.l 1 ; 05c ; place to store TBU
saveTBL ds.l 1 ; 060 ; place to store TBL
saveHID0 ds.l 1 ; 064 ; place to store HID0
saveDEC ds.l 1 ; 068 ; place to store DEC
saveMSR ds.l 1 ; 06c ; place to store MSR
saveSDR1 ds.l 1 ; 070 ; place to store SDR1
; saveKernelDataPtr needs to always be right after saveReturnAddr
; because of how the code works. DO NOT CHANGE THIS ORDERING!
saveReturnAddr ds.l 1 ; 074 ; place to store the addr to jump to.
saveKernelDataPtr ds.l 1 ; 078 ; place to store the KernelDataPtr
saveContextPtr ds.l 1 ; 07c ; place to store the ContextPtr
Size equ *
endr

52
NanoKernel/NKMemory.s → NanoKernel/PageTable.s
View File

@ -1,5 +1,10 @@
; Code to populate the PowerPC "HTAB"/"Hash Table"
########################################################################
PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
lwz r29, KDP.CurMap.SegMapPtr(r1) ; 1. Find which Segment and PMDT cover this Effective Address
; 1. Find which Segment and PMDT cover this Effective Address
lwz r29, KDP.CurMap.SegMapPtr(r1)
rlwinm r28, r27, 7, 0x0000000F << 3 ; get offset into SegMap based on EA
lwzx r29, r29, r28 ; r29 is now our iterating PMDT ptr
rlwinm r28, r27, 20, 0x0000FFFF ; r27 = page index within Segment
@ -13,15 +18,14 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
cmplw cr7, r30, r31
bgt cr7, @next_pmdt ; Save "found PMDT pointer" in r29, "page index within PMDT" in r30
########################################################################
lwz r28, KDP.HtabSinglePTE(r1) ; 2. Parse the PMDT into a PTE (three major code paths)
; 2. Parse the PMDT into a PTE (three major code paths)
lwz r28, KDP.HtabSinglePTE(r1)
lwz r31, PMDT.Word2(r29)
cmpwi cr7, r28, 0 ; always delete the previous PMDT_PTE_Single entry from the HTAB
extlwi. r26, r31, 2, 20 ; use the Cond Reg to branch on Pattr_NotPTE/Pattr_PTE_Single
bne cr7, @del_single_pte
blt @pagelist ; PMDT_Paged is the probable meaning of Pattr_NotPTE (will return to @parsed_pmdt)
@did_del_single_pte ; (optimized return: if LT then @del_single_pte falls thru to @pagelist)
blt @paged ; PMDT_Paged is the probable meaning of Pattr_NotPTE (will return to @parsed_pmdt)
@did_del_single_pte ; (optimized return: if LT then @del_single_pte falls thru to @paged)
bgt @single_pte ; PMDT_PTE_Single is the probable meaning of Pattr_PTE_Single (will return to @parsed_pmdt)
slwi r28, r30, 12 ; PMDT_PTE_Range is likely otherwise, requiring us to add an offset to the PMDT
add r31, r31, r28
@ -30,9 +34,8 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
; 0x5A5A (if PMDT_PTE_Single)
; PageListEntry ptr (if PMDT_Paged)
########################################################################
mfsrin r30, r27 ; 3. Find free slot in HTAB for new entry
; 3. Find free slot in HTAB for new entry
mfsrin r30, r27
rlwinm r28, r27, 26, 10, 25 ; r28 = (1st arg of XOR) * 64b
rlwinm r30, r30, 6, 7, 25 ; r30 = (2nd arg of XOR) * 64b
xor r28, r28, r30 ; r28 = (hash output) * 64b = r28 ^ r30
@ -72,9 +75,8 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
blt cr7, @pteg_full ; @pteg_full *may* return to @try_secondary_pteg
@found_free_pte ; Save PTE ptr + 24 in r29
########################################################################
cmpwi r26, 0 ; 4. Save the new PTE and return
; 4. Save the new PTE and return
cmpwi r26, 0
mfsrin r28, r27
extrwi r30, r27, 6, 4 ; PTE[26-31=API] = high 6 bits of offset-within-segment
stw r27, KDP.HtabLastEA(r1)
@ -110,10 +112,7 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
stw r28, 0(r26)
blr ; return success (EQ)
########################################################################
; Delete the PTE most recently created from a PMDT_PTE_Single entry,
; then jump back up to our caller (but see the optimization below).
@del_single_pte
@del_single_pte ; Delete the PTE most recently created from a PMDT_PTE_Single entry.
lwz r28, KDP.NKInfo.HashTableDeleteCount(r1)
lwz r29, KDP.HtabSinglePTE(r1)
addi r28, r28, 1
@ -128,9 +127,8 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
sync
bge @did_del_single_pte ; Optimization: would otherwise branch to a "blt @par"
########################################################################
@paged ; Probably PMDT_Paged
; r30 = page index within area, r31 = RPN
@pagelist ; Probably PMDT_Paged
extlwi. r28, r31, 2, 21 ; Put remaining two flags into top bits and set Cond Reg
bge @not_actually_pagelist ; Not PMDT_Paged! (e.g. PMDT_InvalidAddress/PMDT_Available)
@ -153,9 +151,8 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
beq @parsed_pmdt ; if resident but outside HTAB, put in HTAB
bltlr cr7 ; if no flags, return invalid (GT)
bl SystemCrash ; crash hard in any other case
bl CrashPageTable ; crash hard in any other case
########################################################################
@single_pte ; PMDT_PTE_Single
ori r28, r27, 0xfff ; r27 = EA, r31 = PMDT (low word, RPN)
stw r28, KDP.HtabSingleEA(r1)
@ -163,14 +160,12 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
li r26, 0x5A5A ; so that KDP.HtabSinglePTE gets set and we return correctly
b @parsed_pmdt ; RTS with r26 = 0x5A5A and r31 having flags cleared
########################################################################
@not_actually_pagelist ; Pattr_NotPTE set, but not PMDT_Paged
bgtlr ; PMDT_InvalidAddress/PMDT_Available: return invalid (GT)
addi r29, r1, KDP.SupervisorMap
b SetMap ; 800 (unknown) -> SetMap returns success (EQ)
########################################################################
@pteg_full ; So try the secondary hashing function, if we haven't already
@pteg_full ; Try the secondary hashing function, if we haven't already
cmplw cr6, r28, r26 ; r26 is as set by PMDT interpretation, r28 = bit 26 of draft PTE r31
subi r29, r29, 64 + 16 ; Make r29 the actual PTEG ptr (PTE search code is very tight)
ble cr6, @both_ptegs_full ; Not sure why r26/r28 could force the sec hash to be skipped...
@ -182,19 +177,16 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
beq @try_secondary_pteg ; Go back in with CR0.EQ set this time (or fall through...)
; On fallthru, r29 = prim PTEG ptr
########################################################################
@both_ptegs_full ; So choose a slot in this PTEG to overflow
lwz r26, KDP.HtabLastOverflow(r1) ; this could be zero
crclr cr6_eq ; cr6.eq means "hell, we're desperate"
rlwimi r26, r29, 0, 0xFFFFFFC0 ; r26 points to the PTE we should try to protext from overflow
addi r29, r26, 8 ; r29 points to the following PTE (gets clobbered straight away)
b @first_pte
@redo_search
bne cr6, @nomr
mr r26, r29
@nomr
@next_pte
cmpw cr6, r29, r26
addi r29, r29, 8
@ -228,7 +220,6 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
extlwi r28, r30, 4, 1
beq @redo_search
########################################################################
; Okay... now do the dirty job of actually overflowing a PTEG (the one at r29)
; (this may well mean tweaking a PLE or even a PMDT)
neg r31, r31 ; Inscrutable... extracting PMDT offset?
@ -282,10 +273,10 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
andi. r30, r28, M68pdInHTAB ; Crash if this PLE wasn't marked as HTAB'd!
rlwinm r30, r28, 32-9, 0x007FFFF8
xor r30, r30, r29 ; Crash if this 68k-PD's pointer didn't match this PTE!
beq SystemCrash
beq CrashPageTable
andi. r30, r30, 0xffff
xori r28, r28, M68pdInHTAB ; Edit the 68k-PD's HTAB flag, physical ptr, and "usage" flags
bne SystemCrash
bne CrashPageTable
rlwimi r28, r31, 0, 0xFFFFF000
_mvbit r28, bM68pdModified, r31, bLpteChange
_mvbit r28, bM68pdUsed, r31, bLpteReference
@ -294,7 +285,6 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
b PutPTE ; PTEG overflow complete. Redo PutPTE!
########################################################################
########################################################################
SetMap ; MemMap r29
lwz r28, MemMap.SegMapPtr(r29)
@ -440,7 +430,6 @@ SetMap ; MemMap r29
blr
########################################################################
########################################################################
GetPhysical ; EA r27, batPtr r29 // PA r31, EQ=Fail
lwz r30, 0(r29)
@ -529,7 +518,6 @@ GetPhysicalFromHTAB ; EA r27 // PA r31, EQ=Fail
blr
########################################################################
########################################################################
FlushTLB
lhz r29, KDP.ProcInfo.TransCacheTotalSize(r1)

11
NanoKernel/NKReset.s → NanoKernel/Reset.s
View File

@ -1,14 +1,13 @@
; These registers will be used throughout
; Code that inits the NanoKernel after Init.s runs,
; or re-inits the NanoKernel after a 68k RESET trap
; These registers will be used throughout:
rCI set r26
lwz rCI, KDP.ConfigInfoPtr(r1)
rNK set r25
lwz rNK, KDP.CodeBase(r1)
rPgMap set r18
lwz rPgMap, KDP.PageMapStartPtr(r1)
rXER set r17
mfxer rXER
@ -17,7 +16,7 @@ rXER set r17
InitVectorTables
; System/Alternate Context tables
_kaddr r23, rNK, SystemCrash
_kaddr r23, rNK, Crash
addi r8, r1, KDP.VecTblSystem
li r22, 3 * VecTbl.Size
@vectab_initnext_segment
@ -33,7 +32,7 @@ rAlt set r8
addi rAlt, r1, KDP.VecTblAlternate
_kaddr r23, rNK, SystemCrash
_kaddr r23, rNK, Crash
stw r23, VecTbl.SystemReset(rSys)
stw r23, VecTbl.SystemReset(rAlt)

22
NanoKernel/NKSoftInts.s → NanoKernel/SoftInts.s
View File

@ -1,3 +1,9 @@
; "Program" and related interrupts
kSoftIntAlign equ 5
########################################################################
IllegalInstruction
mfmsr r9
_ori r8, r9, MsrDR
@ -87,7 +93,7 @@ IllegalInstruction
########################################################################
_align 5
_align kSoftIntAlign
KCallRunAlternateContext
; ARG ContextBlock *r3, flags r4
@ -233,7 +239,7 @@ KCallRunAlternateContext
########################################################################
_align 5
_align kSoftIntAlign
KCallResetSystem
; PPC trap 1, or indirectly, 68k RESET
@ -253,14 +259,14 @@ KCallResetSystem
b ReturnFromInt
Reset
include 'NKReset.s'
include 'Reset.s'
lmw r14, KDP.r14(r1)
b KCallPrioritizeInterrupts
########################################################################
_align 5
_align kSoftIntAlign
KCallPrioritizeInterrupts
; Left side: roll back the interrupt preparation before the int handler repeats is
; Right side: jump to the external interrupt handler (PIH or ProgramInt)
@ -312,11 +318,11 @@ KCallSystemCrash
stmw r14, KDP.r14(r1)
bl SystemCrash
bl Crash
########################################################################
_align 5
_align kSoftIntAlign
ProgramInt
; (also called when the Alternate Context gets an External Int => Exception)
@ -415,7 +421,7 @@ ProgramInt
########################################################################
_align 5
_align kSoftIntAlign
SyscallInt
bl LoadInterruptRegisters
mfmsr r8
@ -426,7 +432,7 @@ SyscallInt
########################################################################
_align 5
_align kSoftIntAlign
TraceInt ; here because of MSR[SE/BE], possibly thanks to ContextFlagTraceWhenDone
bl LoadInterruptRegisters
li r8, ecInstTrace

28
NanoKernel/NKLegacyVM.s → NanoKernel/VirtualMem.s
View File

@ -1,3 +1,5 @@
; Legacy 68k Virtual Memory interface, accessed via 68k FE0A trap
KCallVMDispatch
stw r7, KDP.Flags(r1)
lwz r7, KDP.CodeBase(r1)
@ -16,7 +18,7 @@ KCallVMDispatch
bltlr
b vmRetNeg1
VMTab ; Placeholders indented
VMTab
MACRO
vmtabLine &label
DC.W (&label-CodeBase) - (* - VMtab)
@ -96,7 +98,7 @@ VMInit ; logicalpages a0/r4, pagearray (logical ptr) a1/r5
andi. r3, r8, PMDT_Paged
cmpwi r3, PMDT_Paged
bne @skip_segment ; (skip segment if not paged!)
bnel cr1, SystemCrash ; (first PMDT in segment must start at offset 0!)
bnel cr1, CrashVirtualMem ; (first PMDT in segment must start at offset 0!)
rlwinm r15, r8, 32-10, ~(PMDT_Paged>>10); seg's PhysicalPageArray ptr := PMDT's RPN, times 4
addi r3, r1, KDP.PhysicalPageArray
@ -105,13 +107,13 @@ VMInit ; logicalpages a0/r4, pagearray (logical ptr) a1/r5
slwi r3, r5, 16 ; (confirm that the inner loop is synced with the outer loop)
cmpw r3, r4
bnel SystemCrash
bnel CrashVirtualMem
@pageloop
lwz r16, 0(r15)
subi r7, r7, 1
andi. r3, r16, M68pdResident ; all pages must be resident before VM starts
beql SystemCrash
beql CrashVirtualMem
andi. r3, r16, M68pdInHTAB ; (if page is in htab, check the pte and remove)
beq @not_in_htab
@ -120,15 +122,15 @@ VMInit ; logicalpages a0/r4, pagearray (logical ptr) a1/r5
lwzux r8, r14, r3
lwz r9, 4(r14)
andis. r3, r8, 0x8000;UpteValid ; that pte must be valid, and one of P0/P1 must be set!
beql SystemCrash
beql CrashVirtualMem
andi. r3, r9, LpteP0 | LpteP1
cmpwi r3, 0
beql SystemCrash
beql CrashVirtualMem
rlwinm r3, r16, 17, 22, 31 ; bits 7-16 of the 68k Page Descriptor (<= MYSTERIOUS)
rlwimi r3, r8, 10, 16, 21 ; API from Upte
rlwimi r3, r8, 21, 12, 15 ; top 4 bits of VSID
cmpw r3, r4 ; why would we compare this to r4, our inner loop counter?
bnel SystemCrash
bnel CrashVirtualMem
bl DeletePTE
@not_in_htab
cmpwi r7, 0
@ -143,7 +145,7 @@ VMInit ; logicalpages a0/r4, pagearray (logical ptr) a1/r5
lwz r7, KDP.VMPhysicalPages(r1) ; (final check: did we actually iterate over every page in the VM area?)
cmpw r4, r7
bnel SystemCrash
bnel CrashVirtualMem
lwz r5, KDP.VMPageArray(r1) ; Restore the two arguments that this loop clobbered
lwz r4, KDP.VMLogicalPages(r1)
@ -212,7 +214,7 @@ VMInit ; logicalpages a0/r4, pagearray (logical ptr) a1/r5
@checkloop
lwz r16, 0(r15)
andi. r7, r16, M68pdResident
beql SystemCrash
beql CrashVirtualMem
ori r16, r16, M68pdGlobal | M68pdWriteProtect
stw r16, 0(r15)
subi r5, r5, 1024
@ -628,7 +630,7 @@ VMMarkResident ; page a0/r4, p_page a1/r5
bl PageInfo
bc BO_IF_NOT, cr4_lt, vmRetNeg1 ; not a paged area!
bc BO_IF, bM68pdResident, vmRetNeg1 ; already resident!
bcl BO_IF, bM68pdInHTAB, SystemCrash ; corrupt 68k PD!
bcl BO_IF, bM68pdInHTAB, CrashVirtualMem; corrupt 68k PD!
rlwimi r16, r5, 12, 0xFFFFF000 ; make up a 68k PD
ori r16, r16, M68pdResident ; save it
@ -888,7 +890,7 @@ PageInfo
rlwinm r9, r16, 0, 0xFFFFF000 ; failing a real PTE, this will do do
bclr BO_IF_NOT, bM68pdInHTAB ; No PTE? Fine, we have enough info.
bc BO_IF_NOT, bM68pdResident, SystemCrash ; PD corrupt!
bc BO_IF_NOT, bM68pdResident, CrashVirtualMem ; PD corrupt!
lwzux r8, r14, r8 ; Get PTE in r8/r9 (the usual registers for this file)
lwz r9, 4(r14)
mtcrf %10000000, r8 ; set CR bit 0 to Valid bit
@ -896,7 +898,7 @@ PageInfo
_mvbit r16, bM68pdUsed, r9, bLpteReference ; with info from PPC "touch" bits
mtcrf %00000111, r16
bclr BO_IF, bUpteValid ; Return
bl SystemCrash ; (But crash if PTE is invalid)
bl CrashVirtualMem ; (But crash if PTE is invalid)
@outside_vm_area ; Code outside VM Manager address space
lis r9, 4 ; Check that page is outside VM Manager's segments (0-4)
@ -1066,7 +1068,7 @@ QuickCalcPTE
mflr r6
slwi r27, r4, 12
bl PutPTE
bnel SystemCrash
bnel CrashVirtualMem
mr r27, r7
mr r29, r8
mr r30, r9