mirror of
https://github.com/elliotnunn/powermac-rom.git
synced 2024-05-28 22:41:35 +00:00
everything perfect except one last MR table
This commit is contained in:
Elliot Nunn
parent
6a0bf28b6d
commit
dbf0af7ab9
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@ -167,11 +167,8 @@ Bank14Start ds.l 1 ; 0a0, irp+e60 ; Starting address of RAM bank 14
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Bank14Size ds.l 1 ; 0a4, irp+e64 ; Number of bytes in RAM bank 14
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Bank15Start ds.l 1 ; 0a8, irp+e68 ; Starting address of RAM bank 15
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Bank15Size ds.l 1 ; 0ac, irp+e6c ; Number of bytes in RAM bank 15
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Bank16Start ds.l 1 ; 0b0, irp+e70 ; Starting address of RAM bank 16
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Bank16Size ds.l 1 ; 0b4, irp+e74 ; Number of bytes in RAM bank 16
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Bank17Start ds.l 1 ; 0b8, irp+e78 ; Starting address of RAM bank 17
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Bank17Size ds.l 1 ; 0bc, irp+e7c ; Number of bytes in RAM bank 17
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EndOfBanks
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align 5 ; pad to nice cache block alignment
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MaxBanks equ 16 ; Pads out to old struct len (cache block), more to come...
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Size equ *
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endr
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@ -9,7 +9,7 @@ MRDataStorageInt ; Consult DSISR and the page table to decide what to do
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andis. r28, r31, 0x0800 ; Illegal data access (else crash!)
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addi r29, r1, 0x320 ; ?bug -> PutPTE used to accept this arg
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bnel PutPTE ; Read the failing PTE to r30/r31
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bnel GetPhysical ; Read the failing PTE to r30/r31 ; TODO fix!
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li r28, 0x43 ; Filter Writethru and Protection bits
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and r28, r31, r28
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cmpwi cr7, r28, 0x43
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@ -20,10 +20,10 @@ MRDataStorageInt ; Consult DSISR and the page table to decide what to do
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mfsrr0 r28 ; Writethru and Protection bits set => ROM write nop
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addi r28, r28, 4
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lwz r26, KDP.NKInfo.QuietWrite(r1)
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lwz r26, KDP.NKInfo.QuietWriteCount(r1)
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mtsrr0 r28
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addi r26, r26, 1
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stw r26, KDP.NKInfo.QuietWrite(r1)
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stw r26, KDP.NKInfo.QuietWriteCount(r1)
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@return
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extrwi r26, r25, 8, 22 ; Signal to some MemRetry code?
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@ -14,10 +14,27 @@
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MACRO
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memtabRow &label
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DC.W (&label-MRTop) - (*-MRMemtab)
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DC.W (&label-MRBase) - (*-MRMemtab)
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ENDM
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MRMemtab
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memtabRow MRStore8 ; 8-byte stores
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memtabRow MRStore1241 ; mod 1
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memtabRow MRStore242 ; mod 2
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memtabRow MRStore1421 ; mod 3
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memtabRow MRStore44 ; mod 4
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memtabRow MRStore1241 ; mod 5
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memtabRow MRStore242 ; mod 6
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memtabRow MRStore1421 ; mod 7
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memtabRow MRLoad8 ; 8-byte loads
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memtabRow MRLoad1241 ; mod 1
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memtabRow MRLoad242 ; mod 2
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memtabRow MRLoad1421 ; mod 3
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memtabRow MRLoad44 ; mod 4
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memtabRow MRLoad1241 ; mod 5
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memtabRow MRLoad242 ; mod 6
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memtabRow MRLoad1421 ; mod 7
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memtabRow MRStore1 ; 1-byte stores
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memtabRow MRStore1 ; mod 1
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memtabRow MRStore1 ; mod 2
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@ -43,13 +60,13 @@ MRMemtab
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memtabRow MRStore11 ; mod 5
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memtabRow MRStore2 ; mod 6
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memtabRow MRStore11 ; mod 7
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memtabRow MRLoad2Fast ; 2-byte loads
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memtabRow MRLoad2 ; 2-byte loads
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memtabRow MRLoad11 ; mod 1
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memtabRow MRLoad2Fast ; mod 2
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memtabRow MRLoad2 ; mod 2
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memtabRow MRLoad11 ; mod 3
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memtabRow MRLoad2Fast ; mod 4
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memtabRow MRLoad2 ; mod 4
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memtabRow MRLoad11 ; mod 5
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memtabRow MRLoad2Fast ; mod 6
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memtabRow MRLoad2 ; mod 6
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memtabRow MRLoad11 ; mod 7
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memtabRow MRStore12 ; 3-byte stores
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@ -71,28 +88,28 @@ MRMemtab
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memtabRow MRStore4 ; 4-byte stores
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memtabRow MRStore121 ; mod 1
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memtabRow MRStore22Fast ; mod 2
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memtabRow MRStore22 ; mod 2
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memtabRow MRStore121 ; mod 3
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memtabRow MRStore4 ; mod 4
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memtabRow MRStore121 ; mod 5
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memtabRow MRStore22Fast ; mod 6
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memtabRow MRStore22 ; mod 6
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memtabRow MRStore121 ; mod 7
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memtabRow MRLoad4 ; 4-byte loads
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memtabRow MRLoad121 ; mod 1
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memtabRow MRLoad22Fast ; mod 2
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memtabRow MRLoad22 ; mod 2
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memtabRow MRLoad121 ; mod 3
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memtabRow MRLoad4 ; mod 4
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memtabRow MRLoad121 ; mod 5
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memtabRow MRLoad22Fast ; mod 6
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memtabRow MRLoad22 ; mod 6
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memtabRow MRLoad121 ; mod 7
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memtabRow MRStore14 ; 5-byte stores
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memtabRow MRStore41 ; mod 1
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memtabRow MRStore14 ; mod 2
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memtabRow MRStore122 ; mod 2
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memtabRow MRStore221 ; mod 3
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memtabRow MRStore14 ; mod 4
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memtabRow MRStore41 ; mod 5
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memtabRow MRStore14 ; mod 6
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memtabRow MRStore122 ; mod 6
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memtabRow MRStore221 ; mod 7
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memtabRow MRLoad14 ; 5-byte loads
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memtabRow MRLoad41 ; mod 1
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@ -136,20 +153,3 @@ MRMemtab
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memtabRow MRLoad241 ; mod 5
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memtabRow MRLoad142 ; mod 6
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memtabRow MRLoad421 ; mod 7
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memtabRow MRStore8 ; 8-byte stores
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memtabRow MRStore1241 ; mod 1
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memtabRow MRStore242 ; mod 2
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memtabRow MRStore1421 ; mod 3
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memtabRow MRStore44 ; mod 4
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memtabRow MRStore1241 ; mod 5
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memtabRow MRStore242 ; mod 6
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memtabRow MRStore1421 ; mod 7
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memtabRow MRLoad8 ; 8-byte loads
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memtabRow MRLoad1241 ; mod 1
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memtabRow MRLoad242 ; mod 2
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memtabRow MRLoad1421 ; mod 3
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memtabRow MRLoad44 ; mod 4
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memtabRow MRLoad1241 ; mod 5
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memtabRow MRLoad242 ; mod 6
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memtabRow MRLoad1421 ; mod 7
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@ -1,272 +1,275 @@
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; Each routine accepts:
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; r17 = pretend inst with (byteCount-1) in bits 28-30 (will be decremented)
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; r19 = address of byte to the right of the string to be loaded/saved
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; r26 as a scratch register
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; r23 as a scratch register
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; r20/r21 = right-justified data (stores only)
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; Before jumping to MRDoneMemAccess or one of the MRFast paths, each routine sets:
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; Before jumping to MRDoSecondary or one of the MRFast paths, each routine sets:
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; r20/r21 = right-justified data (loads only)
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; r17 has byteCount field decremented
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; r26 = junk, not to be trusted
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; r23 = junk, not to be trusted
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########################################################################
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MRLoad1241
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lbz r26, -8(r19)
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lbz r23, -8(r19)
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subi r17, r17, 2
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insrwi r20, r26, 8, 0
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insrwi r20, r23, 8, 0
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MRLoad241
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lhz r26, -7(r19)
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lhz r23, -7(r19)
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subi r17, r17, 4
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insrwi r20, r26, 16, 8
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insrwi r20, r23, 16, 8
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b MRLoad41
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MRLoad141
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lbz r26, -6(r19)
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lbz r23, -6(r19)
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subi r17, r17, 2
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insrwi r20, r26, 8, 16
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insrwi r20, r23, 8, 16
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MRLoad41
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lwz r26, -5(r19)
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lwz r23, -5(r19)
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subi r17, r17, 8
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inslwi r20, r26, 8, 24
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insrwi r21, r26, 24, 0
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inslwi r20, r23, 8, 24
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insrwi r21, r23, 24, 0
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b MRLoad1
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MRLoad1421
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lbz r26, -8(r19)
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lbz r23, -8(r19)
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subi r17, r17, 2
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insrwi r20, r26, 8, 0
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insrwi r20, r23, 8, 0
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MRLoad421
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lwz r26, -7(r19)
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lwz r23, -7(r19)
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subi r17, r17, 8
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inslwi r20, r26, 24, 8
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insrwi r21, r26, 8, 0
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inslwi r20, r23, 24, 8
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insrwi r21, r23, 8, 0
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b MRLoad21
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MRLoad1221
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lbz r26, -6(r19)
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lbz r23, -6(r19)
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subi r17, r17, 2
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insrwi r20, r26, 8, 16
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insrwi r20, r23, 8, 16
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MRLoad221
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lhz r26, -5(r19)
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lhz r23, -5(r19)
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subi r17, r17, 4
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rlwimi r20, r26, 24, 24, 31
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insrwi r21, r26, 8, 0
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rlwimi r20, r23, 24, 24, 31
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insrwi r21, r23, 8, 0
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b MRLoad21
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MRLoad121
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lbz r26, -4(r19)
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lbz r23, -4(r19)
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subi r17, r17, 2
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insrwi r21, r26, 8, 0
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insrwi r21, r23, 8, 0
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MRLoad21
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lhz r26, -3(r19)
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lhz r23, -3(r19)
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subi r17, r17, 4
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insrwi r21, r26, 16, 8
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insrwi r21, r23, 16, 8
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b MRLoad1
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MRLoad11
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lbz r26, -2(r19)
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lbz r23, -2(r19)
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subi r17, r17, 2
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insrwi r21, r26, 8, 16
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insrwi r21, r23, 8, 16
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MRLoad1
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lbz r26, -1(r19)
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insrwi r21, r26, 8, 24
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b MRDoneMemAccess
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lbz r23, -1(r19)
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insrwi r21, r23, 8, 24
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b MRDoSecondary
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MRLoad242
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lhz r26, -8(r19)
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lhz r23, -8(r19)
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subi r17, r17, 4
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insrwi r20, r26, 16, 0
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insrwi r20, r23, 16, 0
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b MRLoad42
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MRLoad142
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lbz r26, -7(r19)
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lbz r23, -7(r19)
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subi r17, r17, 2
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insrwi r20, r26, 8, 8
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insrwi r20, r23, 8, 8
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MRLoad42
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lwz r26, -6(r19)
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lwz r23, -6(r19)
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subi r17, r17, 8
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inslwi r20, r26, 16, 16
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insrwi r21, r26, 16, 0
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b MRLoad2Fast
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inslwi r20, r23, 16, 16
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insrwi r21, r23, 16, 0
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b MRLoad2
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MRLoad122
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lbz r26, -5(r19)
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lbz r23, -5(r19)
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subi r17, r17, 2
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insrwi r20, r26, 8, 24
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b MRLoad22Fast
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insrwi r20, r23, 8, 24
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b MRLoad22
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MRLoad12
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lbz r26, -3(r19)
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lbz r23, -3(r19)
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subi r17, r17, 2
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insrwi r21, r26, 8, 8
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b MRLoad2Fast
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insrwi r21, r23, 8, 8
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b MRLoad2
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MRLoad44
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lwz r20, -8(r19)
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subi r17, r17, 8
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lwz r21, -4(r19)
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b MRDoneMemAccess
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b MRDoSecondary
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MRLoad124
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lbz r26, -7(r19)
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lbz r23, -7(r19)
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subi r17, r17, 2
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insrwi r20, r26, 8, 8
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insrwi r20, r23, 8, 8
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MRLoad24
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lhz r26, -6(r19)
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lhz r23, -6(r19)
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subi r17, r17, 4
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insrwi r20, r26, 16, 16
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insrwi r20, r23, 16, 16
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lwz r21, -4(r19)
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b MRDoneMemAccess
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b MRDoSecondary
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MRLoad14
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lbz r26, -5(r19)
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lbz r23, -5(r19)
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subi r17, r17, 2
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insrwi r20, r26, 8, 24
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insrwi r20, r23, 8, 24
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MRLoad4
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lwz r21, -4(r19)
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b MRDoneMemAccess
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b MRDoSecondary
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MRLoad8
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lwz r20, -8(r19)
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lwz r21, -4(r19)
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b MRDoneMemAccess
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b MRDoSecondary
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########################################################################
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MRStore1241
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srwi r26, r20, 24
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stb r26, -8(r19)
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srwi r23, r20, 24
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stb r23, -8(r19)
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subi r17, r17, 2
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MRStore241
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srwi r26, r20, 8
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sth r26, -7(r19)
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srwi r23, r20, 8
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sth r23, -7(r19)
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subi r17, r17, 4
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b MRStore41
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MRStore141
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srwi r26, r20, 8
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stb r26, -6(r19)
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srwi r23, r20, 8
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stb r23, -6(r19)
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subi r17, r17, 2
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MRStore41
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srwi r26, r21, 8
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insrwi r26, r20, 8, 0
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stw r26, -5(r19)
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srwi r23, r21, 8
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insrwi r23, r20, 8, 0
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stw r23, -5(r19)
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subi r17, r17, 8
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stb r21, -1(r19)
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b MRDoneMemAccess
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b MRDoSecondary
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MRStore1421
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srwi r26, r20, 24
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stb r26, -8(r19)
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srwi r23, r20, 24
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stb r23, -8(r19)
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subi r17, r17, 2
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MRStore421
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srwi r26, r21, 24
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insrwi r26, r20, 24, 0
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stw r26, -7(r19)
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srwi r23, r21, 24
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insrwi r23, r20, 24, 0
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stw r23, -7(r19)
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subi r17, r17, 8
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b MRStore21
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MRStore1221
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srwi r26, r20, 8
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stb r26, -6(r19)
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srwi r23, r20, 8
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stb r23, -6(r19)
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subi r17, r17, 2
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MRStore221
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srwi r26, r21, 24
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insrwi r26, r20, 8, 16
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sth r26, -5(r19)
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srwi r23, r21, 24
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insrwi r23, r20, 8, 16
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sth r23, -5(r19)
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subi r17, r17, 4
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b MRStore21
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MRStore121
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srwi r26, r21, 24
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stb r26, -4(r19)
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srwi r23, r21, 24
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stb r23, -4(r19)
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subi r17, r17, 2
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MRStore21
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srwi r26, r21, 8
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sth r26, -3(r19)
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srwi r23, r21, 8
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sth r23, -3(r19)
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subi r17, r17, 4
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stb r21, -1(r19)
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b MRDoneMemAccess
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b MRDoSecondary
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MRStore11
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srwi r26, r21, 8
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stb r26, -2(r19)
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srwi r23, r21, 8
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stb r23, -2(r19)
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subi r17, r17, 2
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MRStore1
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stb r21, -1(r19)
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b MRDoneMemAccess
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b MRDoSecondary
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MRStore242
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srwi r26, r20, 16
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sth r26, -8(r19)
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srwi r23, r20, 16
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sth r23, -8(r19)
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subi r17, r17, 4
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b MRStore42
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MRStore142
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srwi r26, r20, 16
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stb r26, -7(r19)
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srwi r23, r20, 16
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stb r23, -7(r19)
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subi r17, r17, 2
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MRStore42
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srwi r26, r21, 16
|
||||
insrwi r26, r20, 16, 0
|
||||
stw r26, -6(r19)
|
||||
srwi r23, r21, 16
|
||||
insrwi r23, r20, 16, 0
|
||||
stw r23, -6(r19)
|
||||
subi r17, r17, 8
|
||||
sth r21, -2(r19)
|
||||
b MRDoneMemAccess
|
||||
b MRDoSecondary
|
||||
|
||||
MRStore122
|
||||
stb r20, -5(r19)
|
||||
subi r17, r17, 2
|
||||
b MRStore22Fast
|
||||
b MRStore22
|
||||
|
||||
MRStore12
|
||||
srwi r26, r21, 16
|
||||
stb r26, -3(r19)
|
||||
srwi r23, r21, 16
|
||||
stb r23, -3(r19)
|
||||
subi r17, r17, 2
|
||||
|
||||
MRStore2
|
||||
sth r21, -2(r19)
|
||||
b MRDoneMemAccess
|
||||
b MRDoSecondary
|
||||
|
||||
MRStore44
|
||||
stw r20, -8(r19)
|
||||
subi r17, r17, 8
|
||||
stw r21, -4(r19)
|
||||
b MRDoneMemAccess
|
||||
b MRDoSecondary
|
||||
|
||||
MRStore124
|
||||
srwi r26, r20, 16
|
||||
stb r26, -7(r19)
|
||||
srwi r23, r20, 16
|
||||
stb r23, -7(r19)
|
||||
subi r17, r17, 2
|
||||
|
||||
MRStore24
|
||||
sth r20, -6(r19)
|
||||
subi r17, r17, 4
|
||||
stw r21, -4(r19)
|
||||
b MRDoneMemAccess
|
||||
b MRDoSecondary
|
||||
|
||||
MRStore14
|
||||
stb r20, -5(r19)
|
||||
subi r17, r17, 2
|
||||
|
||||
MRStore4
|
||||
stw r21, -4(r19)
|
||||
b MRDoneMemAccess
|
||||
b MRDoSecondary
|
||||
|
||||
MRStore8
|
||||
stw r20, -8(r19)
|
||||
stw r21, -4(r19)
|
||||
b MRDoneMemAccess
|
||||
b MRDoSecondary
|
||||
|
|
|
|||
|
|
@ -1,136 +1,156 @@
|
|||
MACRO
|
||||
optabRow &upperSix, &lowerSix, &flags, &primLabel, &secLabel
|
||||
DC.W (&lowerSix << 10) | (&upperSix << 4) | &flags ; 0-5 lowerSix, 6-11 upperSix, 12-15 flags
|
||||
DC.W ((&primLabel - MRTop) << 6) | ((&secLabel - MRTop) >> 2) ; 16-23 primary routine, 24-31 secondary routine
|
||||
DC.W ((&lowerSix) << 10) | (&upperSix << 4) | &flags ; 0-5 lowerSix, 6-11 upperSix, 12-15 flags
|
||||
IF &TYPE('&primLabel') = 'UNDEFINED' ; 16-23 primary routine
|
||||
DC.B (MRPriCrash - MRBase) >> 2
|
||||
ELSE
|
||||
DC.B (&primLabel - MRBase) >> 2
|
||||
ENDIF
|
||||
IF &TYPE('&secLabel') = 'UNDEFINED' ; 24-31 secondary routine
|
||||
DC.B (MRSecException - MRBase) >> 2
|
||||
ELSE
|
||||
DC.B (&secLabel - MRBase) >> 2
|
||||
ENDIF
|
||||
ENDM
|
||||
|
||||
; LEGEND .. top 6 bits of r17
|
||||
; .. bottom 6 bits of r17
|
||||
; . mrOpflag1
|
||||
; . mrOpflag2
|
||||
; . mrOpflag3
|
||||
; . mrFlagDidLoad
|
||||
;
|
||||
; primary routine secondary routine
|
||||
; (dflt=MRPriCrash) (dflt=MRSecException)
|
||||
; ................ ................
|
||||
|
||||
MROptabX
|
||||
optabRow 20, 09, %0000, MRPrimPlainLoad, MRSecLWARX ; Xopcd=00000(101)00=020=LWARX
|
||||
optabRow 21, 17, %0000, MRCrash, MRSecFail ; Xopcd=00010(101)00=084
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00100(101)00=148
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00110(101)00=212
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01000(101)00=276
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01010(101)00=340
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01100(101)00=404
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01110(101)00=468
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10000(101)00=532
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10010(101)00=596
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10100(101)00=660
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10110(101)00=724
|
||||
optabRow 03, 17, %0000, MRPrimPlainLoad, MRSecLoad ; Xopcd=11000(101)00=788
|
||||
optabRow 06, 09, %0000, MRPrimPlainLoad, MRSecLoad ; Xopcd=11010(101)00=852
|
||||
optabRow 19, 16, %0000, MRPrimPlainStore, MRExit ; Xopcd=11100(101)00=916
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11110(101)00=980
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00001(101)00=052
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00011(101)00=116
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00101(101)00=180
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00111(101)00=244
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01001(101)00=308
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01011(101)00=372
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01101(101)00=436
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01111(101)00=500
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10001(101)00=564
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10011(101)00=628
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10101(101)00=692
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10111(101)00=756
|
||||
optabRow 03, 17, %0000, MRPrimUpdLoad, MRSecLoad ; Xopcd=11001(101)00=820
|
||||
optabRow 27, 17, %0011, MRCrash, MRSecFail ; Xopcd=11011(101)00=884
|
||||
optabRow 19, 16, %0000, MRPrimUpdStore, MRExit ; Xopcd=11101(101)00=948
|
||||
optabRow 31, 16, %0010, MRCrash, MRSecFail ; Xopcd=11111(101)00=1012
|
||||
optabRow 03, 17, %0000, MRPrimPlainLoad, MRSecLoad ; Xopcd=00000(101)01=021=LDX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00010(101)01=085
|
||||
optabRow 19, 16, %0000, MRPrimPlainStore, MRExit ; Xopcd=00100(101)01=149=STDX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00110(101)01=213
|
||||
optabRow 40, 09, %1011, MRPrimUnknown, MRSecUnknown ; Xopcd=01000(101)01=277
|
||||
optabRow 06, 09, %0000, MRPrimPlainLoad, MRSecLoad ; Xopcd=01010(101)01=341
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01100(101)01=405
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01110(101)01=469
|
||||
optabRow 32, 09, %1011, MRPrimLSWX, MRSecLSWix ; Xopcd=10000(101)01=533=LSWX
|
||||
optabRow 32, 09, %1111, MRPrimLSWI, MRSecLSWix ; Xopcd=10010(101)01=597=LSWI
|
||||
optabRow 36, 08, %0010, MRPrimSTSWX, MRSecStrStore ; Xopcd=10100(101)01=661=STSWX
|
||||
optabRow 36, 08, %1110, MRPrimSTSWI, MRSecStrStore ; Xopcd=10110(101)01=725=STSWI
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11000(101)01=789
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11010(101)01=853
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11100(101)01=917
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11110(101)01=981
|
||||
optabRow 03, 17, %0000, MRPrimUpdLoad, MRSecLoad ; Xopcd=00001(101)01=053=LDUX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00011(101)01=117
|
||||
optabRow 19, 16, %0000, MRPrimUpdStore, MRExit ; Xopcd=00101(101)01=181=STDUX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00111(101)01=245
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01001(101)01=309
|
||||
optabRow 06, 09, %0000, MRPrimUpdLoad, MRExit ; Xopcd=01011(101)01=373=LWAUX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01101(101)01=437
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01111(101)01=501
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10001(101)01=565
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10011(101)01=629
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10101(101)01=693
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10111(101)01=757
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11001(101)01=821
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11011(101)01=885
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11101(101)01=949
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11111(101)01=1013
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00000(101)10=022
|
||||
optabRow 62, 03, %0010, MRPrimUpdLoad, MRSecCacheWang ; Xopcd=00010(101)10=086
|
||||
optabRow 22, 09, %0000, MRPrimPlainStore, MRSecSTWCX ; Xopcd=00100(101)10=150=STWCX.
|
||||
optabRow 23, 16, %0000, MRCrash, MRSecFail ; Xopcd=00110(101)10=214
|
||||
optabRow 62, 03, %0010, MRPrimUpdLoad, MRSecCacheWang ; Xopcd=01000(101)10=278=DCBT
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01010(101)10=342
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01100(101)10=406
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01110(101)10=470
|
||||
optabRow 10, 09, %0010, MRPrimUpdLoad, MRSecLWBRX ; Xopcd=10000(101)10=534=LWBRX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10010(101)10=598
|
||||
optabRow 18, 08, %0000, MRPrimSTWBRX, MRExit ; Xopcd=10100(101)10=662=STWBRX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10110(101)10=726
|
||||
optabRow 09, 05, %0010, MRPrimUpdLoad, MRSecLHBRX ; Xopcd=11000(101)10=790=LHBRX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11010(101)10=854
|
||||
optabRow 17, 04, %0000, MRPrimSTHBRX, MRExit ; Xopcd=11100(101)10=918=STHBRX
|
||||
optabRow 62, 03, %0010, MRPrimUpdLoad, MRSecCacheWang ; Xopcd=11110(101)10=982=ICBI
|
||||
optabRow 62, 03, %0010, MRPrimUpdLoad, MRSecCacheWang ; Xopcd=00001(101)10=054=DCBST
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00011(101)10=118
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=00101(101)10=182
|
||||
optabRow 62, 03, %0010, MRPrimUpdLoad, MRSecCacheWang ; Xopcd=00111(101)10=246=DCBTST
|
||||
optabRow 63, 01, %0000, MRPrimPlainLoad, MRIOInstFail ; Xopcd=01001(101)10=310=ECIWX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01011(101)10=374
|
||||
optabRow 63, 00, %0000, MRPrimPlainStore, MRIOInstFail ; Xopcd=01101(101)10=438=ECOWX
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=01111(101)10=502
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10001(101)10=566
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10011(101)10=630
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10101(101)10=694
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=10111(101)10=758
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11001(101)10=822
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11011(101)10=886
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11101(101)10=950
|
||||
optabRow 48, 16, %0010, MRPrimDCBZ, MRSecDCBZ ; Xopcd=11111(101)10=1014=DCBZ
|
||||
optabRow 20, 9, %0000, MRPriPlainLoad, MRSecLWARX ; Xopcd=00000(101)00=020=LWARX
|
||||
optabRow 21, 17, %0000, , ; Xopcd=00010(101)00=084
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00100(101)00=148
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00110(101)00=212
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01000(101)00=276
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01010(101)00=340
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01100(101)00=404
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01110(101)00=468
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10000(101)00=532
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10010(101)00=596
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10100(101)00=660
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10110(101)00=724
|
||||
optabRow 3, 17, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=11000(101)00=788
|
||||
optabRow 6, 9, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=11010(101)00=852
|
||||
optabRow 19, 16, %0000, MRPriPlainStore, MRSecDone ; Xopcd=11100(101)00=916
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11110(101)00=980
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00001(101)00=052
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00011(101)00=116
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00101(101)00=180
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00111(101)00=244
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01001(101)00=308
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01011(101)00=372
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01101(101)00=436
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01111(101)00=500
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10001(101)00=564
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10011(101)00=628
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10101(101)00=692
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10111(101)00=756
|
||||
optabRow 3, 17, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=11001(101)00=820
|
||||
optabRow 27, 17, %0011, , ; Xopcd=11011(101)00=884
|
||||
optabRow 19, 16, %0000, MRPriUpdStore, MRSecDone ; Xopcd=11101(101)00=948
|
||||
optabRow 31, 16, %0010, , ; Xopcd=11111(101)00=1012
|
||||
optabRow 3, 17, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=00000(101)01=021=LDX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00010(101)01=085
|
||||
optabRow 19, 16, %0000, MRPriPlainStore, MRSecDone ; Xopcd=00100(101)01=149=STDX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00110(101)01=213
|
||||
optabRow 40, 9, %1011, MRPriUnknown, MRSecUnknown ; Xopcd=01000(101)01=277
|
||||
optabRow 6, 9, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=01010(101)01=341
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01100(101)01=405
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01110(101)01=469
|
||||
optabRow 32, 9, %1011, MRPriLSWX, MRSecLSWix ; Xopcd=10000(101)01=533=LSWX
|
||||
optabRow 32, 9, %1111, MRPriLSWI, MRSecLSWix ; Xopcd=10010(101)01=597=LSWI
|
||||
optabRow 36, 8, %0010, MRPriSTSWX, MRSecStrStore ; Xopcd=10100(101)01=661=STSWX
|
||||
optabRow 36, 8, %1110, MRPriSTSWI, MRSecStrStore ; Xopcd=10110(101)01=725=STSWI
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11000(101)01=789
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11010(101)01=853
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11100(101)01=917
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11110(101)01=981
|
||||
optabRow 3, 17, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=00001(101)01=053=LDUX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00011(101)01=117
|
||||
optabRow 19, 16, %0000, MRPriUpdStore, MRSecDone ; Xopcd=00101(101)01=181=STDUX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00111(101)01=245
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01001(101)01=309
|
||||
optabRow 6, 9, %0000, MRPriUpdLoad, MRSecDone ; Xopcd=01011(101)01=373=LWAUX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01101(101)01=437
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01111(101)01=501
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10001(101)01=565
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10011(101)01=629
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10101(101)01=693
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10111(101)01=757
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11001(101)01=821
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11011(101)01=885
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11101(101)01=949
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11111(101)01=1013
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00000(101)10=022
|
||||
optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=00010(101)10=086
|
||||
optabRow 22, 9, %0000, MRPriPlainStore, MRSecSTWCX ; Xopcd=00100(101)10=150=STWCX.
|
||||
optabRow 23, 16, %0000, , ; Xopcd=00110(101)10=214
|
||||
optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=01000(101)10=278=DCBT
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01010(101)10=342
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01100(101)10=406
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01110(101)10=470
|
||||
optabRow 10, 9, %0010, MRPriUpdLoad, MRSecLWBRX ; Xopcd=10000(101)10=534=LWBRX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10010(101)10=598
|
||||
optabRow 18, 8, %0000, MRPriSTWBRX, MRSecDone ; Xopcd=10100(101)10=662=STWBRX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10110(101)10=726
|
||||
optabRow 9, 5, %0010, MRPriUpdLoad, MRSecLHBRX ; Xopcd=11000(101)10=790=LHBRX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11010(101)10=854
|
||||
optabRow 17, 4, %0000, MRPriSTHBRX, MRSecDone ; Xopcd=11100(101)10=918=STHBRX
|
||||
optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=11110(101)10=982=ICBI
|
||||
optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=00001(101)10=054=DCBST
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00011(101)10=118
|
||||
optabRow 63, 1, %0000, , ; Xopcd=00101(101)10=182
|
||||
optabRow 62, 3, %0010, MRPriUpdLoad, MRSecCacheWang ; Xopcd=00111(101)10=246=DCBTST
|
||||
optabRow 63, 1, %0000, MRPriPlainLoad, MRSecIOInstFail ; Xopcd=01001(101)10=310=ECIWX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01011(101)10=374
|
||||
optabRow 63, 0, %0000, MRPriPlainStore, MRSecIOInstFail ; Xopcd=01101(101)10=438=ECOWX
|
||||
optabRow 63, 1, %0000, , ; Xopcd=01111(101)10=502
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10001(101)10=566
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10011(101)10=630
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10101(101)10=694
|
||||
optabRow 63, 1, %0000, , ; Xopcd=10111(101)10=758
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11001(101)10=822
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11011(101)10=886
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11101(101)10=950
|
||||
optabRow 48, 16, %0010, MRPriDCBZ, MRSecDCBZ ; Xopcd=11111(101)10=1014=DCBZ
|
||||
MROptabD
|
||||
optabRow 02, 09, %0000, MRPrimPlainLoad, MRSecLoad ; Xopcd=00000(101)11=023=LWZX Dopcd=(1)00000=32=LWZ
|
||||
optabRow 00, 03, %0000, MRPrimPlainLoad, MRSecLoad ; Xopcd=00010(101)11=087=LBZX Dopcd=(1)00010=34=LBZ
|
||||
optabRow 18, 08, %0000, MRPrimPlainStore, MRExit ; Xopcd=00100(101)11=151=STWX Dopcd=(1)00100=36=STW
|
||||
optabRow 16, 02, %0000, MRPrimPlainStore, MRExit ; Xopcd=00110(101)11=215=STBX Dopcd=(1)00110=38=STB
|
||||
optabRow 01, 05, %0000, MRPrimPlainLoad, MRSecLoad ; Xopcd=01000(101)11=279=LHZX Dopcd=(1)01000=40=LHZ
|
||||
optabRow 05, 05, %0000, MRPrimPlainLoad, MRSecLoadExt ; Xopcd=01010(101)11=343=LHAX Dopcd=(1)01010=42=LHA
|
||||
optabRow 17, 04, %0000, MRPrimPlainStore, MRExit ; Xopcd=01100(101)11=407=STHX Dopcd=(1)01100=44=STH
|
||||
optabRow 26, 09, %0011, MRPrimUpdLoad, MRSecLMW ; Xopcd=01110(101)11=471 Dopcd=(1)01110=46=LMW
|
||||
optabRow 14, 09, %0000, MRPrimPlainLoad, MRSecLFSu ; Xopcd=10000(101)11=535=LFSX Dopcd=(1)10000=48=LFS
|
||||
optabRow 15, 17, %0000, MRPrimPlainLoad, MRSecLFDu ; Xopcd=10010(101)11=599=LFDX Dopcd=(1)10010=50=LFD
|
||||
optabRow 18, 08, %0000, MRPrimSTFSx, MRExit ; Xopcd=10100(101)11=663=STFSX Dopcd=(1)10100=52=STFS
|
||||
optabRow 19, 16, %0000, MRPrimSTFDx, MRExit ; Xopcd=10110(101)11=727=STFDX Dopcd=(1)10110=54=STFD
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11000(101)11=791 Dopcd=(1)11000=56
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11010(101)11=855 Dopcd=(1)11010=58
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11100(101)11=919 Dopcd=(1)11100=60
|
||||
optabRow 18, 08, %0000, MRPrimSTFDx, MRExit ; Xopcd=11110(101)11=983=STFIWX Dopcd=(1)11110=62
|
||||
optabRow 02, 09, %0000, MRPrimUpdLoad, MRSecLoad ; Xopcd=00001(101)11=055=LWZUX Dopcd=(1)00001=33=LWZU
|
||||
optabRow 00, 03, %0000, MRPrimUpdLoad, MRSecLoad ; Xopcd=00011(101)11=119=LBZUX Dopcd=(1)00011=35=LBZU
|
||||
optabRow 18, 08, %0000, MRPrimUpdStore, MRExit ; Xopcd=00101(101)11=183=STWUX Dopcd=(1)00101=37=STWU
|
||||
optabRow 16, 02, %0000, MRPrimUpdStore, MRExit ; Xopcd=00111(101)11=247=STBUX Dopcd=(1)00111=39=STBU
|
||||
optabRow 01, 05, %0000, MRPrimUpdLoad, MRSecLoad ; Xopcd=01001(101)11=311=LHZUX Dopcd=(1)01001=41=LHZU
|
||||
optabRow 05, 05, %0000, MRPrimUpdLoad, MRSecLoadExt ; Xopcd=01011(101)11=375=LHAUX Dopcd=(1)01011=43=LHAU
|
||||
optabRow 17, 04, %0000, MRPrimUpdStore, MRExit ; Xopcd=01101(101)11=439=STHUX Dopcd=(1)01101=45=STHU
|
||||
optabRow 30, 08, %0010, MRPrimUpdStore, MRSecSTMW ; Xopcd=01111(101)11=503 Dopcd=(1)01111=47=STMW
|
||||
optabRow 14, 09, %0000, MRPrimUpdLoad, MRSecLFSu ; Xopcd=10001(101)11=567=LFSUX Dopcd=(1)10001=49=LFSU
|
||||
optabRow 15, 17, %0000, MRPrimUpdLoad, MRSecLFDu ; Xopcd=10011(101)11=631=LFDUX Dopcd=(1)10011=51=LFDU
|
||||
optabRow 18, 08, %0000, MRPrimSTFSUx, MRExit ; Xopcd=10101(101)11=695=STFSUX Dopcd=(1)10101=53=STFSU
|
||||
optabRow 19, 16, %0000, MRPrimSTFDUx, MRExit ; Xopcd=10111(101)11=759=STFDUX Dopcd=(1)10111=55=STFDU
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11001(101)11=823 Dopcd=(1)11001=57
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11011(101)11=887 Dopcd=(1)11011=59
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11101(101)11=951 Dopcd=(1)11101=61
|
||||
optabRow 63, 01, %0000, MRCrash, MRSecFail ; Xopcd=11111(101)11=1015 Dopcd=(1)11111=63
|
||||
optabRow 2, 9, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=00000(101)11=023=LWZX Dopcd=(1)00000=32=LWZ
|
||||
optabRow 0, 3, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=00010(101)11=087=LBZX Dopcd=(1)00010=34=LBZ
|
||||
optabRow 18, 8, %0000, MRPriPlainStore, MRSecDone ; Xopcd=00100(101)11=151=STWX Dopcd=(1)00100=36=STW
|
||||
optabRow 16, 2, %0000, MRPriPlainStore, MRSecDone ; Xopcd=00110(101)11=215=STBX Dopcd=(1)00110=38=STB
|
||||
optabRow 1, 5, %0000, MRPriPlainLoad, MRSecLoad ; Xopcd=01000(101)11=279=LHZX Dopcd=(1)01000=40=LHZ
|
||||
optabRow 5, 5, %0000, MRPriPlainLoad, MRSecLoadExt ; Xopcd=01010(101)11=343=LHAX Dopcd=(1)01010=42=LHA
|
||||
optabRow 17, 4, %0000, MRPriPlainStore, MRSecDone ; Xopcd=01100(101)11=407=STHX Dopcd=(1)01100=44=STH
|
||||
optabRow 26, 9, %0011, MRPriUpdLoad, MRSecLMW ; Xopcd=01110(101)11=471 Dopcd=(1)01110=46=LMW
|
||||
optabRow 14, 9, %0000, MRPriPlainLoad, MRSecLFSu ; Xopcd=10000(101)11=535=LFSX Dopcd=(1)10000=48=LFS
|
||||
optabRow 15, 17, %0000, MRPriPlainLoad, MRSecLFDu ; Xopcd=10010(101)11=599=LFDX Dopcd=(1)10010=50=LFD
|
||||
optabRow 18, 8, %0000, MRPriSTFSx, MRSecDone ; Xopcd=10100(101)11=663=STFSX Dopcd=(1)10100=52=STFS
|
||||
optabRow 19, 16, %0000, MRPriSTFDx, MRSecDone ; Xopcd=10110(101)11=727=STFDX Dopcd=(1)10110=54=STFD
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11000(101)11=791 Dopcd=(1)11000=56
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11010(101)11=855 Dopcd=(1)11010=58
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11100(101)11=919 Dopcd=(1)11100=60
|
||||
optabRow 18, 8, %0000, MRPriSTFDx, MRSecDone ; Xopcd=11110(101)11=983=STFIWX Dopcd=(1)11110=62
|
||||
optabRow 2, 9, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=00001(101)11=055=LWZUX Dopcd=(1)00001=33=LWZU
|
||||
optabRow 0, 3, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=00011(101)11=119=LBZUX Dopcd=(1)00011=35=LBZU
|
||||
optabRow 18, 8, %0000, MRPriUpdStore, MRSecDone ; Xopcd=00101(101)11=183=STWUX Dopcd=(1)00101=37=STWU
|
||||
optabRow 16, 2, %0000, MRPriUpdStore, MRSecDone ; Xopcd=00111(101)11=247=STBUX Dopcd=(1)00111=39=STBU
|
||||
optabRow 1, 5, %0000, MRPriUpdLoad, MRSecLoad ; Xopcd=01001(101)11=311=LHZUX Dopcd=(1)01001=41=LHZU
|
||||
optabRow 5, 5, %0000, MRPriUpdLoad, MRSecLoadExt ; Xopcd=01011(101)11=375=LHAUX Dopcd=(1)01011=43=LHAU
|
||||
optabRow 17, 4, %0000, MRPriUpdStore, MRSecDone ; Xopcd=01101(101)11=439=STHUX Dopcd=(1)01101=45=STHU
|
||||
optabRow 30, 8, %0010, MRPriUpdStore, MRSecSTMW ; Xopcd=01111(101)11=503 Dopcd=(1)01111=47=STMW
|
||||
optabRow 14, 9, %0000, MRPriUpdLoad, MRSecLFSu ; Xopcd=10001(101)11=567=LFSUX Dopcd=(1)10001=49=LFSU
|
||||
optabRow 15, 17, %0000, MRPriUpdLoad, MRSecLFDu ; Xopcd=10011(101)11=631=LFDUX Dopcd=(1)10011=51=LFDU
|
||||
optabRow 18, 8, %0000, MRPriSTFSUx, MRSecDone ; Xopcd=10101(101)11=695=STFSUX Dopcd=(1)10101=53=STFSU
|
||||
optabRow 19, 16, %0000, MRPriSTFDUx, MRSecDone ; Xopcd=10111(101)11=759=STFDUX Dopcd=(1)10111=55=STFDU
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11001(101)11=823 Dopcd=(1)11001=57
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11011(101)11=887 Dopcd=(1)11011=59
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11101(101)11=951 Dopcd=(1)11101=61
|
||||
optabRow 63, 1, %0000, , ; Xopcd=11111(101)11=1015 Dopcd=(1)11111=63
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
MRCrash ; C00
|
||||
MRPriCrash ; C00
|
||||
bl SystemCrash
|
||||
MRSecFail ; C04
|
||||
b MRIOInstFail
|
||||
MRSecException ; C04
|
||||
b MRSecIOInstFail
|
||||
|
||||
########################################################################
|
||||
|
||||
MRPrimSTFSx ; C08
|
||||
MRPriSTFSx ; C08
|
||||
rlwinm r17, r17, 0,16,10
|
||||
|
||||
MRPrimSTFSUx ; C0C
|
||||
MRPriSTFSUx ; C0C
|
||||
crclr cr7_so
|
||||
b MRDoTableSTFD
|
||||
|
||||
MRPrimSTFDx ; C14
|
||||
MRPriSTFDx ; C14
|
||||
rlwinm r17, r17, 0,16,10
|
||||
|
||||
MRPrimSTFDUx ; C18
|
||||
MRPriSTFDUx ; C18
|
||||
crset cr7_so
|
||||
|
||||
MRDoTableSTFD ; C1C
|
||||
; This table is of the form:
|
||||
; stfd <reg>, KDP.FloatEmScratch(r1)
|
||||
; stfd <reg>, KDP.FloatScratch(r1)
|
||||
; b
|
||||
|
||||
clrrwi r19, r25, 10
|
||||
rlwimi r19, r17, 14,24,28
|
||||
addi r19, r19, STFDTable-MRTop
|
||||
addi r19, r19, STFDTable-MRBase
|
||||
mtlr r19
|
||||
rlwimi r14, r11, 0,18,18
|
||||
mtmsr r14
|
||||
|
|
@ -33,63 +33,63 @@ MRDoTableSTFD ; C1C
|
|||
|
||||
MRDoneTableSTFD ; c38
|
||||
ori r11, r11, 0x2000
|
||||
lwz r20, KDP.FloatEmScratch(r1)
|
||||
lwz r21, KDP.FloatEmScratch+4(r1)
|
||||
bso cr7, MRPrimUpdLoad
|
||||
lwz r20, KDP.FloatScratch(r1)
|
||||
lwz r21, KDP.FloatScratch+4(r1)
|
||||
bso cr7, MRPriUpdLoad
|
||||
extrwi r23, r20, 11,1
|
||||
cmpwi r23, 0x380
|
||||
insrwi r20, r20, 27,2
|
||||
inslwi r20, r21, 3,29
|
||||
mr r21, r20
|
||||
bgt MRPrimUpdLoad
|
||||
bgt MRPriUpdLoad
|
||||
cmpwi r23, 0x36A
|
||||
clrrwi r21, r20, 31
|
||||
blt MRPrimUpdLoad
|
||||
blt MRPriUpdLoad
|
||||
oris r20, r20, 0x80
|
||||
neg r23, r23
|
||||
clrlwi r20, r20, 8
|
||||
srw r20, r20, r23
|
||||
rlwimi r21, r20, 31,9,31
|
||||
b MRPrimUpdLoad
|
||||
b MRPriUpdLoad
|
||||
|
||||
########################################################################
|
||||
|
||||
MRPrimSTWBRX ; C84
|
||||
MRPriSTWBRX ; C84
|
||||
rlwinm r28, r17, 13,25,29
|
||||
lwbrx r21, r1, r28
|
||||
b MRPrimPlainLoad
|
||||
b MRPriPlainLoad
|
||||
|
||||
MRPrimSTHBRX ; C90
|
||||
MRPriSTHBRX ; C90
|
||||
rlwinm r28, r17, 13,25,29
|
||||
addi r21, r1, 2
|
||||
lhbrx r21, r21, r28
|
||||
b MRPrimPlainLoad
|
||||
b MRPriPlainLoad
|
||||
|
||||
########################################################################
|
||||
|
||||
MRPrimUpdStore ; CA0
|
||||
MRPriUpdStore ; CA0
|
||||
rlwinm r28, r17, 13,25,29
|
||||
lwzx r21, r1, r28
|
||||
b MRPrimUpdLoad
|
||||
b MRPriUpdLoad
|
||||
|
||||
MRPrimPlainStore ; CAC
|
||||
MRPriPlainStore ; CAC
|
||||
rlwinm r28, r17, 13,25,29
|
||||
lwzx r21, r1, r28
|
||||
|
||||
MRPrimPlainLoad ; CB4
|
||||
MRPriPlainLoad ; CB4
|
||||
rlwinm r17, r17, 0,16,10
|
||||
|
||||
MRPrimUpdLoad ; CB8
|
||||
MRPriUpdLoad ; CB8
|
||||
extrwi. r22, r17, 4,27
|
||||
add r19, r18, r22
|
||||
|
||||
########################################################################
|
||||
|
||||
MRDoMemAccess ; CC0
|
||||
MRPriDone ; CC0
|
||||
clrrwi r25, r25, 10
|
||||
insrwi r25, r19, 3,28
|
||||
insrwi r25, r17, 4,24
|
||||
lha r22, MRMemtab-MRTop(r25)
|
||||
lha r22, MRMemtab-MRBase(r25)
|
||||
addi r23, r1, KDP.VecTblMemRetry
|
||||
add r22, r22, r25
|
||||
mtlr r22
|
||||
|
|
@ -97,31 +97,33 @@ MRDoMemAccess ; CC0
|
|||
mtmsr r15
|
||||
insrwi r25, r26, 8,22
|
||||
bnelr
|
||||
b MRDoneMemAccess
|
||||
b MRDoSecondary
|
||||
|
||||
MRStore22Fast ; Fast return paths from MemAccess code
|
||||
########################################################################
|
||||
|
||||
MRStore22 ; Fast return paths from MemAccess code
|
||||
srwi r23, r21, 16
|
||||
sth r23, -4(r19)
|
||||
addi r17, r17, -4
|
||||
sth r21, -2(r19)
|
||||
b MRDoneMemAccess
|
||||
MRLoad22Fast
|
||||
b MRDoSecondary
|
||||
MRLoad22
|
||||
lhz r23, -4(r19)
|
||||
addi r17, r17, -4
|
||||
insrwi r21, r23, 16,0
|
||||
MRLoad2Fast
|
||||
MRLoad2
|
||||
lhz r23, -2(r19)
|
||||
insrwi r21, r23, 16,16
|
||||
|
||||
MRDoneMemAccess ; D18
|
||||
MRDoSecondary ; D18
|
||||
sync
|
||||
rlwinm. r28, r17, 18,25,29
|
||||
mtlr r25
|
||||
cror cr0_eq, cr0_eq, cr3_eq
|
||||
cror cr0_eq, cr0_eq, mrOpflag3
|
||||
mtmsr r14
|
||||
mtsprg 3, r24
|
||||
beqlr
|
||||
crset cr3_so
|
||||
crset mrFlagDidLoad
|
||||
stwx r18, r1, r28
|
||||
blr
|
||||
|
||||
|
|
@ -132,27 +134,25 @@ MRSecLoadExt ; D40
|
|||
|
||||
MRSecLoad ; D44
|
||||
rlwinm r28, r17, 13,25,29
|
||||
crset cr3_so
|
||||
crset mrFlagDidLoad
|
||||
stwx r21, r1, r28
|
||||
|
||||
########################################################################
|
||||
|
||||
MRExit ; D50
|
||||
andi. r23, r16, 0x20
|
||||
MRSecDone ; D50
|
||||
andi. r23, r16, FlagTrace
|
||||
addi r10, r10, 4
|
||||
mtsrr0 r10
|
||||
mtsrr1 r11
|
||||
bne @trace
|
||||
mtlr r12
|
||||
|
||||
bns cr3, @otherway
|
||||
|
||||
bc BO_IF_NOT, mrFlagDidLoad, @otherway
|
||||
mtcr r13
|
||||
lmw r2, KDP.r2(r1)
|
||||
lwz r0, KDP.r0(r1)
|
||||
lwz r1, KDP.r1(r1)
|
||||
rfi
|
||||
|
||||
@otherway
|
||||
mtcr r13
|
||||
lmw r10, KDP.r10(r1)
|
||||
|
|
@ -162,7 +162,7 @@ MRExit ; D50
|
|||
@trace
|
||||
mfsprg r24, 3
|
||||
mtsprg 2, r12
|
||||
rlwinm r16, r16, 0,27,25
|
||||
_bclr r16, r16, bitFlagTrace
|
||||
lwz r12, VecTbl.Trace(r24)
|
||||
stw r16, KDP.Flags(r1)
|
||||
mtcr r13
|
||||
|
|
@ -180,9 +180,9 @@ MRSecLHBRX ; DC0
|
|||
|
||||
MRSecLWBRX ; DC4
|
||||
rlwinm r28, r17, 13,25,29
|
||||
crset cr3_so
|
||||
crset mrFlagDidLoad
|
||||
stwbrx r21, r1, r28
|
||||
b MRExit
|
||||
b MRSecDone
|
||||
|
||||
########################################################################
|
||||
|
||||
|
|
@ -211,13 +211,14 @@ MRSecLFSu ; DD4
|
|||
|
||||
MRSecLFDu ; E28
|
||||
; This table is of the form:
|
||||
; lfd <reg>, KDP.FloatEmScratch(r1)
|
||||
; b MRExit
|
||||
; lfd <reg>, KDP.FloatScratch(r1)
|
||||
; b MRSecDone
|
||||
clrrwi r23, r25, 10
|
||||
rlwimi r23, r17, 14,24,28
|
||||
addi r23, r23, LFDTable-MRTop
|
||||
addi r23, r23, LFDTable-MRBase
|
||||
mtlr r23
|
||||
stw r20, KDP.FloatEmScratch(r1)
|
||||
stw r21, KDP.FloatEmScratch+4(r1)
|
||||
stw r20, KDP.FloatScratch(r1)
|
||||
stw r21, KDP.FloatScratch+4(r1)
|
||||
rlwimi r14, r11, 0,18,18
|
||||
mtmsr r14
|
||||
ori r11, r11, 0x2000
|
||||
|
|
@ -241,29 +242,29 @@ loc_E6C ; E6C
|
|||
li r22, 9
|
||||
insrwi r17, r22, 6,26
|
||||
addi r19, r19, 4
|
||||
bne MRDoMemAccess
|
||||
b MRExit
|
||||
bne MRPriDone
|
||||
b MRSecDone
|
||||
|
||||
MRSecSTMW ; E84
|
||||
addis r17, r17, 0x20
|
||||
rlwinm. r28, r17, 13,25,29
|
||||
beq MRExit
|
||||
beq MRSecDone
|
||||
lwzx r21, r1, r28
|
||||
li r22, 8
|
||||
insrwi r17, r22, 6,26
|
||||
addi r19, r19, 4
|
||||
b MRDoMemAccess
|
||||
b MRPriDone
|
||||
|
||||
########################################################################
|
||||
|
||||
MRPrimDCBZ ; Zero four 8b chunks of the cache blk
|
||||
MRPriDCBZ ; Zero four 8b chunks of the cache blk
|
||||
clrrwi r19, r18, 5 ; r19 = address of chunk to zero
|
||||
b MRComDCBZ ; (for use by this code only)
|
||||
|
||||
MRSecDCBZ ; EAC
|
||||
andi. r22, r19, 0x18
|
||||
clrrwi r19, r19, 3 ; MemAccess code decrements this reg
|
||||
beq MRExit ; Zeroed all foun chunks -> done!
|
||||
beq MRSecDone ; Zeroed all foun chunks -> done!
|
||||
|
||||
MRComDCBZ ; EB8
|
||||
li r22, 0x10 ; Set 8 bytes (? set bit 27)
|
||||
|
|
@ -271,50 +272,50 @@ MRComDCBZ ; EB8
|
|||
addi r19, r19, 8 ; Align ptr to right hand size of chunk
|
||||
li r20, 0 ; Contents = zeros
|
||||
li r21, 0
|
||||
b MRDoMemAccess ; Go, then come back to MRSecDCBZ
|
||||
b MRPriDone ; Go, then come back to MRSecDCBZ
|
||||
|
||||
########################################################################
|
||||
|
||||
MRSecLWARX ; ED0
|
||||
rlwinm r28, r17, 13,25,29
|
||||
crset cr3_so
|
||||
crset mrFlagDidLoad
|
||||
stwx r21, r1, r28
|
||||
stwcx. r21, r1, r28
|
||||
b MRExit
|
||||
b MRSecDone
|
||||
|
||||
MRSecSTWCX ; EE4
|
||||
stwcx. r0, 0, r1
|
||||
mfcr r23
|
||||
rlwinm r23, r23, 0,3,1
|
||||
rlwimi r13, r23, 0,0,3
|
||||
b MRExit
|
||||
b MRSecDone
|
||||
|
||||
########################################################################
|
||||
|
||||
MRSecCacheWang ; EF8
|
||||
rlwinm r16, r16, 0,28,25
|
||||
rlwinm r16, r16, 0, ~(FlagTrace | FlagLowSaves)
|
||||
addi r10, r10, -4
|
||||
stw r16, KDP.Flags(r1)
|
||||
b MRExit
|
||||
b MRSecDone
|
||||
|
||||
########################################################################
|
||||
|
||||
MRIOInstFail ; F08
|
||||
MRSecIOInstFail ; F08
|
||||
li r8, ecDataInvalidAddress
|
||||
b ExceptionMemRetried
|
||||
b ExceptionAfterRetry
|
||||
|
||||
########################################################################
|
||||
|
||||
MRPrimSTSWI ; F10
|
||||
MRPriSTSWI ; F10
|
||||
addi r22, r27, -0x800
|
||||
extrwi r22, r22, 5,16
|
||||
b loc_F2C
|
||||
|
||||
MRPrimSTSWX ; F1C
|
||||
MRPriSTSWX ; F1C
|
||||
mfxer r22
|
||||
andi. r22, r22, 0x7F
|
||||
addi r22, r22, -1
|
||||
beq MRExit
|
||||
beq MRSecDone
|
||||
|
||||
loc_F2C ; F2C
|
||||
rlwimi r17, r22, 4,21,25
|
||||
|
|
@ -329,23 +330,23 @@ MRSecStrStore ; F40
|
|||
rlwimi r17, r28, 0,6,10
|
||||
addi r17, r17, -0x40
|
||||
bne loc_1008
|
||||
b MRExit
|
||||
b MRSecDone
|
||||
|
||||
########################################################################
|
||||
|
||||
MRPrimLSWI ; F58
|
||||
MRPriLSWI ; F58
|
||||
addi r22, r27, -0x800
|
||||
extrwi r22, r22, 5,16
|
||||
addis r28, r27, 0x3E0
|
||||
rlwimi r17, r28, 22,16,20
|
||||
b loc_F80
|
||||
|
||||
MRPrimLSWX ; F6C
|
||||
MRPriLSWX ; F6C
|
||||
mfxer r22
|
||||
andi. r22, r22, 0x7F
|
||||
rlwimi r17, r27, 0,16,20
|
||||
addi r22, r22, -1
|
||||
beq MRExit
|
||||
beq MRSecDone
|
||||
|
||||
loc_F80 ; F80
|
||||
andis. r23, r17, 0x1F
|
||||
|
|
@ -367,13 +368,13 @@ MRSecLSWix ; FA0
|
|||
|
||||
########################################################################
|
||||
|
||||
MRPrimUnknown ; FB8
|
||||
MRPriUnknown ; FB8
|
||||
mfxer r22
|
||||
andi. r22, r22, 0x7F
|
||||
rlwimi r17, r27, 0,16,20
|
||||
insrwi r17, r27, 1,3
|
||||
addi r22, r22, -1
|
||||
beq MRExit
|
||||
beq MRSecDone
|
||||
andis. r23, r17, 0x1F
|
||||
rlwimi r17, r22, 4,21,25
|
||||
not r22, r22
|
||||
|
|
@ -400,7 +401,7 @@ loc_1008 ; 1008
|
|||
li r22, 8
|
||||
insrwi r17, r22, 6,26
|
||||
addi r19, r19, 4
|
||||
bne MRDoMemAccess
|
||||
bne MRPriDone
|
||||
rlwinm r22, r17, 9,27,28
|
||||
srw r21, r21, r22
|
||||
extrwi r22, r17, 2,4
|
||||
|
|
@ -408,7 +409,7 @@ loc_1008 ; 1008
|
|||
add r19, r19, r22
|
||||
addi r22, r22, 4
|
||||
insrwi. r17, r22, 5,26
|
||||
b MRDoMemAccess
|
||||
b MRPriDone
|
||||
|
||||
loc_1044 ; 1044
|
||||
rlwinm r23, r17, 18,25,29
|
||||
|
|
@ -423,20 +424,20 @@ loc_1060 ; 1060
|
|||
addis r28, r17, 0x20
|
||||
rlwimi r17, r28, 0,6,10
|
||||
addi r17, r17, -0x40
|
||||
beq MRExit
|
||||
beq MRSecDone
|
||||
|
||||
loc_1070 ; 1070
|
||||
andi. r23, r17, 0x7C0
|
||||
li r22, 9
|
||||
insrwi r17, r22, 6,26
|
||||
addi r19, r19, 4
|
||||
bne MRDoMemAccess
|
||||
bne MRPriDone
|
||||
extrwi r22, r17, 2,4
|
||||
neg r22, r22
|
||||
add r19, r19, r22
|
||||
addi r22, r22, 4
|
||||
insrwi. r17, r22, 5,26
|
||||
b MRDoMemAccess
|
||||
b MRPriDone
|
||||
|
||||
loc_109C ; 109C
|
||||
rlwinm r23, r17, 18,25,29
|
||||
|
|
@ -451,7 +452,7 @@ loc_10B8 ; 10B8
|
|||
addis r28, r17, 0x20
|
||||
rlwimi r17, r28, 0,6,10
|
||||
addi r17, r17, -0x40
|
||||
beq MRExit
|
||||
beq MRSecDone
|
||||
|
||||
loc_10C8 ; 10C8
|
||||
not r22, r22
|
||||
|
|
@ -486,8 +487,8 @@ loc_112C ; 112C
|
|||
add r22, r22, r23
|
||||
insrwi r23, r22, 7,25
|
||||
mtxer r23
|
||||
beq MRExit
|
||||
beq MRSecDone
|
||||
mfcr r23
|
||||
clrlwi r23, r23, 30
|
||||
insrwi r13, r23, 4,0
|
||||
b MRExit
|
||||
b MRSecDone
|
||||
|
|
|
|||
|
|
@ -136,3 +136,9 @@ ecUnknown24 equ 24
|
|||
_bitEqu 29, Flag29
|
||||
_bitEqu 30, Flag30
|
||||
_bitEqu 31, Flag31
|
||||
|
||||
|
||||
mrOpflag1 equ cr3_lt
|
||||
mrOpflag2 equ cr3_gt
|
||||
mrOpflag3 equ cr3_eq
|
||||
mrFlagDidLoad equ cr3_so
|
||||
|
|
|
|||
|
|
@ -367,45 +367,42 @@ SwitchContext ; OldCB *r6, NewCB *r9
|
|||
########################################################################
|
||||
|
||||
IntReturn
|
||||
andi. r8, r7, (1 << (31 - 26)) | (1 << (31 - 27))
|
||||
bnel @do_trace ; Keep single-step code out of hot path
|
||||
andi. r8, r7, FlagTrace | FlagLowSaves
|
||||
bnel @do_trace
|
||||
|
||||
stw r7, KDP.Flags(r1)
|
||||
|
||||
mtlr r12 ; restore user SPRs from kernel GPRs
|
||||
stw r7, KDP.Flags(r1) ; Save kernel flags for next interrupt
|
||||
mtlr r12 ; Restore user SPRs from kernel GPRs
|
||||
mtsrr0 r10
|
||||
mtsrr1 r11
|
||||
mtcr r13
|
||||
|
||||
lwz r10, CB.r10(r6) ; restore user GPRs from ContextBlock
|
||||
lwz r10, CB.r10(r6) ; Restore user GPRs from ContextBlock
|
||||
lwz r11, CB.r11(r6)
|
||||
lwz r12, CB.r12(r6)
|
||||
lwz r13, CB.r13(r6)
|
||||
lwz r7, CB.r7(r6)
|
||||
lwz r8, CB.r8(r6)
|
||||
lwz r9, CB.r9(r6)
|
||||
|
||||
lwz r6, KDP.r6(r1) ; restore last two registers from EWA
|
||||
lwz r6, KDP.r6(r1) ; Restore last two registers from EWA
|
||||
lwz r1, KDP.r1(r1)
|
||||
|
||||
rfi
|
||||
rfi ; Return from interrupt
|
||||
|
||||
|
||||
@do_trace
|
||||
mtcrf 0x3f, r7
|
||||
|
||||
bc BO_IF_NOT, bitFlagLowSaves, @Trace_0x18
|
||||
_bclr r7, r7, bitFlagLowSaves
|
||||
bc BO_IF_NOT, bitFlagLowSaves, @no_low_saves
|
||||
|
||||
bc BO_IF, bitFlag31, Trace_0x30
|
||||
_bclr r7, r7, bitFlagTrace
|
||||
_bclr r7, r7, bitFlagLowSaves ; LowSaves set with flag 31 -> unset and do some emulation
|
||||
bc BO_IF, bitFlag31, @last_minute_memretry
|
||||
|
||||
_bclr r7, r7, bitFlagTrace ; But if flag 31 is unset, disable tracing and go home
|
||||
b @return
|
||||
@Trace_0x18
|
||||
|
||||
@no_low_saves
|
||||
bc BO_IF_NOT, bitFlagTrace, @return
|
||||
_bclr r7, r7, bitFlagTrace
|
||||
|
||||
_bclr r7, r7, bitFlagTrace ; Trace flag set with no LowSaves -> unset that flag, and do Trace Exception
|
||||
stw r7, KDP.Flags(r1)
|
||||
li r8, ecInstTrace
|
||||
b Exception
|
||||
|
|
@ -413,9 +410,7 @@ IntReturn
|
|||
@return
|
||||
blr
|
||||
|
||||
Trace_0x30
|
||||
; according to my counter, this point is never reached
|
||||
|
||||
@last_minute_memretry
|
||||
stw r7, KDP.Flags(r1)
|
||||
stw r0, 0x0000(r1)
|
||||
stw r2, 0x0008(r1)
|
||||
|
|
@ -436,35 +431,40 @@ Trace_0x30
|
|||
stw r8, 0x0030(r1)
|
||||
lwz r8, 0x016c(r6)
|
||||
stw r8, 0x0034(r1)
|
||||
stmw r14, 0x0038(r1)
|
||||
lwz r17, 0x0024(r9)
|
||||
lwz r20, 0x0028(r9)
|
||||
lwz r21, 0x002c(r9)
|
||||
lwz r19, 0x0034(r9)
|
||||
lwz r18, 0x003c(r9)
|
||||
|
||||
stmw r14, KDP.r14(r1)
|
||||
|
||||
lwz r17, CB.LowSave17(r9) ; LowSave means "MemRetry in ContextBlock"
|
||||
lwz r20, CB.LowSave20(r9)
|
||||
lwz r21, CB.LowSave21(r9)
|
||||
lwz r19, CB.LowSave19(r9)
|
||||
lwz r18, CB.LowSave18(r9)
|
||||
_bclr r16, r7, bitFlagLowSaves
|
||||
lwz r25, 0x0650(r1)
|
||||
extrwi. r22, r17, 4, 27
|
||||
add r19, r19, r22
|
||||
rlwimi r25, r17, 7, 25, 30
|
||||
lhz r26, 0x0d20(r25) ; leaving this incorrect as a reminder!
|
||||
insrwi r25, r19, 3, 28
|
||||
|
||||
lwz r25, KDP.MRBase(r1) ; MRUnknown is indexed by the first arg of MROptab?
|
||||
extrwi. r22, r17, 4, 27 ;
|
||||
add r19, r19, r22 ; Correct r19 (EA) by adding byteCount from r17
|
||||
rlwimi r25, r17, 7, 25, 30 ; The top of MRUnknown is... mysterious!
|
||||
lhz r26, MRUnknown-MRBase(r25) ; leaving this incorrect as a reminder!
|
||||
|
||||
insrwi r25, r19, 3, 28 ; Set Memtab alignment modulus
|
||||
stw r16, KDP.Flags(r1)
|
||||
rlwimi r26, r26, 8, 8, 15 ; copy hi byte of entry to second byte of word
|
||||
insrwi r25, r17, 4, 24
|
||||
mtcrf 0x10, r26 ; so the second nybble of the entry is copied to cr3
|
||||
lha r22, 0x0c00(r25)
|
||||
rlwimi r26, r26, 8, 8, 15 ; First byte of MRUnknown is for cr3/cr4
|
||||
insrwi r25, r17, 4, 24 ; byteCount and load/store from second arg of MROptab?
|
||||
mtcrf 0x10, r26 ; Set CR3
|
||||
lha r22, MRMemtab-MRBase(r25) ; Jump to MRMemtab...
|
||||
|
||||
addi r23, r1, KDP.VecTblMemRetry
|
||||
add r22, r22, r25
|
||||
mfsprg r24, 3
|
||||
mtlr r22
|
||||
mtsprg 3, r23
|
||||
mfmsr r14
|
||||
ori r15, r14, 0x10
|
||||
_bset r15, r14, bitMsrDR
|
||||
mtmsr r15
|
||||
rlwimi r25, r26, 2, 22, 29 ; apparently the lower byte of the entry is an FDP (code?) offset, /4!
|
||||
rlwimi r25, r26, 2, 22, 29 ; Second byte of MRUnknown is
|
||||
bnelr
|
||||
b FDP_011c
|
||||
b MRDoSecondary
|
||||
|
||||
########################################################################
|
||||
|
||||
|
|
|
|||
|
|
@ -145,11 +145,11 @@ DisableFPU
|
|||
if &highest > 0
|
||||
MakeFloatJumpTable &OPCODE, &DEST, highest = (&highest) - 1
|
||||
endif
|
||||
&OPCODE &highest, KDP.FloatEmScratch(r1)
|
||||
&OPCODE &highest, KDP.FloatScratch(r1)
|
||||
b &DEST
|
||||
ENDM
|
||||
|
||||
LFDTable
|
||||
MakeFloatJumpTable lfd, MRExit
|
||||
MakeFloatJumpTable lfd, MRSecDone
|
||||
STFDTable
|
||||
MakeFloatJumpTable stfd, MRDoneTableSTFD
|
||||
|
|
|
|||
|
|
@ -169,10 +169,10 @@ InitKernelGlobals
|
|||
bl * + 4
|
||||
mflr r12
|
||||
addi r12, r12, 4 - *
|
||||
stw r12, KDP.NKCodePtr(r1)
|
||||
stw r12, KDP.CodeBase(r1)
|
||||
|
||||
_kaddr r12, r12, FDP
|
||||
stw r12, KDP.RetryCodePtr(r1)
|
||||
_kaddr r12, r12, MRBase
|
||||
stw r12, KDP.MRBase(r1)
|
||||
|
||||
lwz r12, NKConfigurationInfo.LA_EmulatorData(rCI)
|
||||
lwz r11, NKConfigurationInfo.ECBOffset(rCI)
|
||||
|
|
@ -265,7 +265,7 @@ InitProcessorInfo
|
|||
mfpvr r12
|
||||
stw r12, KDP.ProcInfo.ProcessorVersionReg(r1)
|
||||
srwi r12, r12, 16
|
||||
lwz r11, KDP.NKCodePtr(r1)
|
||||
lwz r11, KDP.CodeBase(r1)
|
||||
addi r10, r1, KDP.ProcInfo.Ovr
|
||||
li r9, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
########################################################################
|
||||
|
||||
_align 6
|
||||
IntExternal0
|
||||
ExternalInt0
|
||||
mfsprg r1, 0 ; Init regs and increment ctr
|
||||
stw r0, KDP.r0(r1)
|
||||
stw r2, KDP.r2(r1)
|
||||
|
|
@ -70,7 +70,7 @@ IntLookupTable
|
|||
dc.b 7, 7, 7, 7, 7, 7, 7, 7
|
||||
|
||||
_align 6
|
||||
IntExternal1
|
||||
ExternalInt1
|
||||
mfsprg r1, 0 ; Init regs and increment ctr
|
||||
stw r0, KDP.r0(r1)
|
||||
stw r2, KDP.r2(r1)
|
||||
|
|
@ -97,7 +97,7 @@ IntExternal1
|
|||
lwz r4, KDP.r4(r1)
|
||||
lwz r5, KDP.r5(r1)
|
||||
|
||||
lwz r3, KDP.NKCodePtr(r1) ; Loop that number up in the table
|
||||
lwz r3, KDP.CodeBase(r1) ; Loop that number up in the table
|
||||
rlwimi r3, r0, 0, 0x0000003F
|
||||
lbz r2, IntLookupTable-NKTop(r3)
|
||||
mfcr r0
|
||||
|
|
@ -128,7 +128,7 @@ IntExternal1
|
|||
########################################################################
|
||||
|
||||
_align 6
|
||||
IntExternal2
|
||||
ExternalInt2
|
||||
mfsprg r1, 0 ; Init regs and increment ctr
|
||||
stw r0, KDP.r0(r1)
|
||||
stw r2, KDP.r2(r1)
|
||||
|
|
@ -282,7 +282,7 @@ DataStorageInt
|
|||
|
||||
EmulateDataAccess
|
||||
rlwinm. r18, r27, 18, 25, 29 ; r16 = 4 * rA (r0 wired to 0)
|
||||
lwz r25, KDP.RetryCodePtr(r1)
|
||||
lwz r25, KDP.MRBase(r1)
|
||||
li r21, 0
|
||||
beq @r0
|
||||
lwzx r18, r1, r18 ; r16 = contents of rA
|
||||
|
|
@ -297,7 +297,7 @@ EmulateDataAccess
|
|||
;dform
|
||||
rlwimi r25, r27, 7, 26, 29 ; opcode >= 32
|
||||
rlwimi r25, r27, 12, 25, 25
|
||||
lwz r26, MROptabD - MRTop(r25) ; table of 4b elements, index = major opcode bits 51234 (this is the last quarter of MROptabX)
|
||||
lwz r26, MROptabD - MRBase(r25) ; table of 4b elements, index = major opcode bits 51234 (this is the last quarter of MROptabX)
|
||||
extsh r23, r27 ; r23 = register offset field, sign-extended
|
||||
rlwimi r25, r26, 26, 22, 29
|
||||
mtlr r25 ; dest = r25 = first of two function ptrs in table entry
|
||||
|
|
@ -310,7 +310,7 @@ EmulateDataAccess
|
|||
rlwimi r25, r27, 27, 26, 29
|
||||
rlwimi r25, r27, 0, 25, 25
|
||||
rlwimi r25, r27, 6, 23, 24
|
||||
lwz r26, MROptabX - MRTop(r25) ; table of 4b elements, index = minor (x-form) opcode bits 8940123
|
||||
lwz r26, MROptabX - MRBase(r25) ; table of 4b elements, index = minor (x-form) opcode bits 8940123
|
||||
rlwinm r23, r27, 23, 25, 29 ; r23 = 4 * rB
|
||||
rlwimi r25, r26, 26, 22, 29
|
||||
mtlr r25 ; dest = r25 = first of two function ptrs in table entry
|
||||
|
|
@ -318,7 +318,7 @@ EmulateDataAccess
|
|||
lwzx r23, r1, r23 ; get rB from saved registers
|
||||
rlwimi r17, r26, 6, 26, 5 ; r17 = pretend X-form inst with: maj opcode (from tbl), rS/D and RA (from inst), min opcode (from tbl)
|
||||
add r18, r18, r23 ; r18 = effective address attempted by instruction
|
||||
bclr BO_IF_NOT, 13
|
||||
bclr BO_IF_NOT, mrOpflag2
|
||||
neg r23, r23
|
||||
add r18, r18, r23
|
||||
blr
|
||||
|
|
@ -347,7 +347,7 @@ AlignmentInt
|
|||
mfdar r18
|
||||
|
||||
extrwi. r21, r27, 2, 15 ; evaluate hi two bits of XO (or 0 for d-form?)
|
||||
lwz r25, KDP.RetryCodePtr(r1)
|
||||
lwz r25, KDP.MRBase(r1)
|
||||
rlwinm r17, r27, 16, 0x03FF0000
|
||||
lwz r16, KDP.Flags(r1)
|
||||
rlwimi r25, r27, 24, 23, 29 ; add constant fields from dsisr (*4) to FDP
|
||||
|
|
@ -355,7 +355,7 @@ AlignmentInt
|
|||
bne @X_form
|
||||
|
||||
; D- or DS-form (immediate-indexed) instruction
|
||||
lwz r26, MROptabD - MRTop(r25) ; use upper quarter of table
|
||||
lwz r26, MROptabD - MRBase(r25) ; use upper quarter of table
|
||||
mfmsr r14
|
||||
rlwimi r25, r26, 26, 22, 29 ; third byte of lookup value is a /4 code offset in FDP
|
||||
mtlr r25 ; so get ready to go there
|
||||
|
|
@ -366,14 +366,14 @@ AlignmentInt
|
|||
|
||||
@X_form
|
||||
; X-form (register-indexed) instruction
|
||||
lwz r26, MROptabX - MRTop(r25)
|
||||
lwz r26, MROptabX - MRBase(r25)
|
||||
mfmsr r14
|
||||
rlwimi r25, r26, 26, 22, 29
|
||||
mtlr r25
|
||||
_bset r15, r14, bitMsrDR
|
||||
mtcr r26
|
||||
rlwimi r17, r26, 6, 26, 5
|
||||
bclr BO_IF_NOT, 12
|
||||
bclr BO_IF_NOT, mrOpflag1
|
||||
mtmsr r15
|
||||
lwz r27, 0(r10)
|
||||
mtmsr r14
|
||||
|
|
@ -391,7 +391,7 @@ InstStorageInt
|
|||
andis. r8, r11, 0x4020 ; what the hell are these MSR bits?
|
||||
beq major_0x039dc_0x14
|
||||
|
||||
stmw r14, KDP.r14(r8)
|
||||
stmw r14, KDP.r14(r1)
|
||||
mr r27, r10
|
||||
bl PutPTE
|
||||
bne @not_in_htab
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ MaxVMCallCount equ 26
|
|||
KCallVMDispatch ; OUTSIDE REFERER
|
||||
|
||||
stw r7, KDP.Flags(r1)
|
||||
lwz r7, KDP.NKCodePtr(r1)
|
||||
lwz r7, KDP.CodeBase(r1)
|
||||
cmplwi r3, MaxVMCallCount
|
||||
insrwi r7, r3, 7, 24
|
||||
lhz r8, VMDispatchTable - NKTop(r7)
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
; r15 = MSR | MSR[DR]
|
||||
; r17 = pretend inst: 0-5 from optab || 6-10 rS/rD || 11-15 rA || 21-25 zero || 26-31 from optab
|
||||
; r18 = effective address attempted
|
||||
; r25 = dirty MRTop ptr
|
||||
; r25 = dirty MRBase ptr
|
||||
; r26 = OpTab entry
|
||||
; r27 = instruction
|
||||
; LR = r25 = address of primary routine (jumped to)
|
||||
|
|
@ -13,14 +13,14 @@
|
|||
; PRIMARY ROUTINE
|
||||
|
||||
; LOOP until SECONDARY ROUTINE calls, or is, an exit routine
|
||||
; MRDoMemAccess accepts:
|
||||
; MRPriDone accepts:
|
||||
; r17 = pretend inst: 0-5 from optab || 6-10 rS/rD || 11-15 rA || 21-27 ?? || 28-30 byteCount-1 || 31 isLoad (NB: what about bottom 6 bits??)
|
||||
; r19 = address first byte *after* the string to be accessed
|
||||
; r25 = dirty MRTop ptr
|
||||
; r25 = dirty MRBase ptr
|
||||
; r26 = the original OpTab entry
|
||||
; EQ = should continue (NE => skip to MRDoneMemAccess)
|
||||
; EQ = should continue (NE => skip to MRDoSecondary)
|
||||
|
||||
; MRDoMemAccess sets:
|
||||
; MRPriDone sets:
|
||||
; r25 = address of secondary routine
|
||||
; MSR = r15
|
||||
; SPRG3 = VecTblMemRetry
|
||||
|
|
@ -36,7 +36,7 @@
|
|||
; r20/r21 = right-justified data (loads only)
|
||||
; r26 = scratch
|
||||
|
||||
; MRDoneMemAccess sets:
|
||||
; MRDoSecondary sets:
|
||||
; r17 = pretend inst as above
|
||||
; MSR = r14
|
||||
; SPRG3 = r24
|
||||
|
|
@ -48,10 +48,12 @@
|
|||
; EXIT ROUTINE
|
||||
|
||||
_align 10
|
||||
MRTop
|
||||
MRBase
|
||||
INCLUDE 'MROptabCode.s' ; c00:1154
|
||||
INCLUDE 'MRMemtabCode.s' ; 1154:13f4
|
||||
INCLUDE 'MRInterrupts.s' ; 13f4:14f4
|
||||
INCLUDE 'MROptab.s' ; 14f4:16f4
|
||||
INCLUDE 'MRMemtab.s' ; 16f4:17f4
|
||||
INCLUDE 'MRUnknown.s' ; 17f4:1874
|
||||
; INCLUDE 'MRUnknown.s' ; 17f4:1874
|
||||
MRUnknown
|
||||
dcb.b 128, 0
|
||||
|
|
|
|||
|
|
@ -294,8 +294,8 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
|
|||
########################################################################
|
||||
########################################################################
|
||||
|
||||
SetMap ; MapPtrBlk r29
|
||||
lwz r28, MapPtrBlkSegMapPtr(r29)
|
||||
SetMap ; MemMap r29
|
||||
lwz r28, MemMap.SegMapPtr(r29)
|
||||
stw r28, KDP.CurMap.SegMapPtr(r1)
|
||||
addi r28, r28, 16*8 + 4
|
||||
lis r31, 0
|
||||
|
|
@ -308,7 +308,7 @@ SetMap ; MapPtrBlk r29
|
|||
bne @next_seg
|
||||
|
||||
mfpvr r31
|
||||
lwz r28, MapPtrBlkBatMap(r29)
|
||||
lwz r28, MemMap.BatMap(r29)
|
||||
andis. r31, r31, 0xFFFE
|
||||
addi r29, r1, 0
|
||||
stw r28, KDP.CurMap.BatMap(r1)
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ rCI set r26
|
|||
lwz rCI, KDP.ConfigInfoPtr(r1)
|
||||
|
||||
rNK set r25
|
||||
lwz rNK, KDP.NKCodePtr(r1)
|
||||
lwz rNK, KDP.CodeBase(r1)
|
||||
|
||||
rPgMap set r18
|
||||
lwz rPgMap, KDP.PageMapStartPtr(r1)
|
||||
|
|
@ -103,10 +103,10 @@ rAlt set r8
|
|||
|
||||
addi r8, r1, KDP.VecTblMemRetry
|
||||
|
||||
_kaddr r23, rNK, MemRetryMachineCheck
|
||||
_kaddr r23, rNK, MRMachineCheckInt
|
||||
stw r23, VecTbl.MachineCheck(r8)
|
||||
|
||||
_kaddr r23, rNK, MemRetryDSI
|
||||
_kaddr r23, rNK, MRDataStorageInt
|
||||
stw r23, VecTbl.DSI(r8)
|
||||
|
||||
########################################################################
|
||||
|
|
|
|||
|
|
@ -75,9 +75,9 @@ IllegalInstruction
|
|||
|
||||
stwx r21, r1, r28 ; save register into EWA
|
||||
mr r16, r7
|
||||
beq cr7, loc_D50 ; TBL
|
||||
beq cr7, MRSecDone ; TBL
|
||||
stwx r20, r1, r28
|
||||
b loc_D50 ; TBU
|
||||
b MRSecDone ; TBU
|
||||
|
||||
|
||||
@STFIWX
|
||||
|
|
@ -87,7 +87,7 @@ IllegalInstruction
|
|||
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
|
||||
mfmsr r14
|
||||
_bset r15, r14, bitMsrDR
|
||||
b loc_A38
|
||||
b EmulateDataAccess
|
||||
|
||||
########################################################################
|
||||
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ L ds.l 1
|
|||
|
||||
########################################################################
|
||||
|
||||
MapPtrBlk RECORD 0, INCR
|
||||
MemMap RECORD 0, INCR
|
||||
SegMapPtr ds.l 1
|
||||
BatMap ds.l 1 ; packed array of 4-bit indices into BATs
|
||||
ENDR
|
||||
|
|
@ -175,18 +175,18 @@ VecTblSystem ds VecTbl ; 360:420 ; when 68k emulator is running, *or* any MTas
|
|||
VecTblAlternate ds VecTbl ; 420:4e0 ; native PowerPC in blue task
|
||||
VecTblMemRetry ds VecTbl ; 4e0:5a0 ; "FDP" instruction emulation
|
||||
|
||||
FloatEmScratch ds.d 1 ; 5a0:5a8
|
||||
FloatScratch ds.d 1 ; 5a0:5a8
|
||||
TopOfFreePages ds.l 1 ; 5a8 ; gotten from the old SPRG0
|
||||
ds.l 1 ; 5ac
|
||||
PARPerSegmentPLEPtrs ds.l 4 ; 5b0:5c0 ; for each PAR segment, a ptr into the PAR PageList
|
||||
FloatingPtTemp1 ds.l 1 ; 5c0
|
||||
FloatingPtTemp2 ds.l 1 ; 5c4
|
||||
|
||||
SupervisorMap ds MapPtrBlk ; 5c8:5d0
|
||||
UserMap ds MapPtrBlk ; 5d0:5d8
|
||||
CpuMap ds MapPtrBlk ; 5d8:5e0
|
||||
OverlayMap ds MapPtrBlk ; 5e0:5e8
|
||||
CurMap ds MapPtrBlk ; 5e8:5f0
|
||||
SupervisorMap ds MemMap ; 5c8:5d0
|
||||
UserMap ds MemMap ; 5d0:5d8
|
||||
CpuMap ds MemMap ; 5d8:5e0
|
||||
OverlayMap ds MemMap ; 5e0:5e8
|
||||
CurMap ds MemMap ; 5e8:5f0
|
||||
|
||||
KCallTbl ds KCallTbl ; 5f0:630
|
||||
|
||||
|
|
@ -197,8 +197,8 @@ KernelMemoryEnd ds.l 1 ; 63c
|
|||
LowMemPtr ds.l 1 ; 640 ; physical address of PAR Low Memory
|
||||
SharedMemoryAddr ds.l 1 ; 644 ; debug?
|
||||
EmuKCallTblPtrLogical ds.l 1 ; 648
|
||||
NKCodePtr ds.l 1 ; 64c
|
||||
RetryCodePtr ds.l 1 ; 650
|
||||
CodeBase ds.l 1 ; 64c
|
||||
MRBase ds.l 1 ; 650
|
||||
ECBPtrLogical ds.l 1 ; 654 ; Emulator/System ContextBlock
|
||||
ECBPtr ds.l 1 ; 658
|
||||
CurCBPtr ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user