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neaten

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neaten structures and delete old files
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Elliot Nunn 2018-07-15 18:10:37 +08:00
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commit e11b02a8a8
32 changed files with 479 additions and 25631 deletions
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;_______________________________________________________________________
; Data structures internal to the NanoKernel
;_______________________________________________________________________
;_______________________________________________________________________
; PRIMARY SYSTEM AREA
;
; The PSA is Rene's homage to the ESA390's prefix storage area.
; It contains "the PowerPC IVT and some NK pointers."
;
; New to NKv2, it lives in the page below the KDP. On CPU0, this is
; also just below the below-SPRG0 part of the Exception Work Area.
; It is almost always accessed by negative offset from GPR1, hence
; the negative offsets.
;_______________________________________________________________________
PSA record {EndOfPSA},INCR
Base
HTABLock ds.l 8 ; -b90:-b70
PIHLock ds.l 8 ; -b70:-b50
SchLock ds.l 8 ; -b50:-b30
ThudLock ds.l 8 ; -b30:-b10 ; for the interactive debugger
RTASLock ds.l 8 ; -b10:-af0
DbugLock ds.l 8 ; -af0:-ad0
PoolLock ds.l 8 ; -ad0:-ab0
FreePool ds.l 4 ; -ab0 ; LLL with signature 'POOL'
FirstPoolSeg ds.l 1 ; -aa0 ; singly linked list (=>BGN=>END=>BGN...)
FirstPoolSegLogical ds.l 1 ; -a9c
IndexPtr ds.l 1 ; -a98 ; index of opaque IDs
CoherenceGrpList ds.l 4 ; -a94:-a84 ; signature 'GRPS'
TimerQueue ds.l 16 ; -a84:-a44 ; there are more of these in the pool
DelayQueue ds.l 4 ; -a44:-a34
DbugQueue ds.l 4 ; -a34:-a24
PageQueue ds.l 4 ; -a24:-a14
NotQueue ds.l 4 ; -a14:-a04
_a04 ds.l 1 ; -a04
QueueRelatedZero1 ds.l 1 ; -a00 ; set to zero when queues are inited
QueueRelatedZero2 ds.l 1 ; -9fc ; same again
_9f8 ds.l 1 ; -9f8
_9f4 ds.l 1 ; -9f4
ReadyQueues
CriticalReadyQ ds.l 8 ; -9f0:-9d0 ; unblocked tasks with priority 0
LatencyProtectReadyQ ds.l 8 ; -9d0:-9b0 ; unblocked tasks with priority 1
NominalReadyQ ds.l 8 ; -9b0:-990 ; unblocked tasks with priority 2
IdleReadyQ ds.l 8 ; -990:-970 ; unblocked tasks with priority 3
PriorityFlags ds.l 1 ; -970 ; bit 0 is 0, bit 1 is 1, etc...
ScrambledMPCallTime ds.l 1 ; -96c ; by MP call return
FlagsTemplate ds.l 1 ; -968 ; typically just bitFlagVec
UserModeMSR ds.l 1 ; -964
ThudBuffer ds.b 96 ; -960:-900 ; that's the kernel debugger
NoIdeaR23 ds.l 1 ; -900 ; r23 copies here... replated to RTAS?
_8fc ds.l 1 ; -8fc
_8f8 ds.l 1 ; -8f8
_8f4 ds.w 1 ; -8f4
_8f2 ds.w 1 ; -8f2
PA_BlueTask ds.l 1 ; -8f0 ; set at the same time as the one below
_8ec ds.l 1 ; -8ec
_8e8 ds.l 1 ; -8e8
OtherSystemContextPtr ds.l 1 ; -8e4 ; sometimes set to PA_ECB
VectorRegInitWord ds.l 1 ; -8e0 ; task vector regs get inited with this word x 4
SevenFFFDead2 ds.l 1 ; -8dc
SevenFFFDead3 ds.l 1 ; -8d8
SevenFFFDead4 ds.l 1 ; -8d4
VioletVecBase ds.l 48 ; -8d0:-810
VecBaseIdle ds.l 48 ; -810:-750 ; to wake from DOZE/NAP/SLEEP state
VecBasePIH ds.l 48 ; -750:-690 ; gets enabled by PDM PIH
VecBaseScreenConsole ds.l 48 ; -690:-5d0
DiagInfo ds.b 256 ; -5d0:-4d0
ProcessorState ds.b 128 ; -4d0:-450 ; interesting what this gets used by
FreeList ds.l 4 ; -450:-440
MCR ds.l 1 ; -440 ; reported by heartbeat code
Pending68kInt ds.w 1 ; -43c ; used when Sch interrupts blue task (-1 means "none")
_43a ds.w 1 ; -43a
DecClockRateHzCopy ds.l 1 ; -438 ; copied by Init.s
OtherTimerQueuePtr ds.l 1 ; -434 ; unsigned timer queue in the pool, set by InitTMRQs
FreePageCount ds.l 1 ; -430 ; zeroed by InitFreePageList
UnheldFreePageCount ds.l 1 ; -42c
ExternalHandlerID ds.l 1 ; -428 ; notification for PIH to bump
SystemAddressSpaceID ds.l 1 ; -424
AgerID ds.l 1 ; -420
blueProcessPtr ds.l 1 ; -41c ; physical ptr to first type-1 struct created
ThermalHandlerID ds.l 1 ; -418 ; is a Note struct
PMFHandlerID ds.l 1 ; -414 ; also a Note struct
BlueSpinningOn ds.l 1 ; -410 ; ID or 0 or -1
_40c ds.l 1 ; -40c
_408 ds.l 1 ; -408
_404 ds.l 1 ; -404
_400 ds.l 1 ; -400
OtherSystemAddrSpcPtr ds.l 1 ; -3fc
OtherSystemAddrSpcPtr2 ds.l 1 ; -3f8 ; copied from the one above by InitFreePageList
ZeroedByInitFreeList3 ds.l 1 ; -3f4
_3f0 ds.l 1 ; -3f0
_3ec ds.l 1 ; -3ec
_3e8 ds.l 1 ; -3e8
_3e4 ds.l 1 ; -3e4
_3e0 ds.l 1 ; -3e0
_3dc ds.l 1 ; -3dc
_3d8 ds.l 1 ; -3d8
_3d4 ds.l 1 ; -3d4
_3d0 ds.l 1 ; -3d0
_3cc ds.l 1 ; -3cc
_3c8 ds.l 1 ; -3c8
_3c4 ds.l 1 ; -3c4
_3c0 ds.l 1 ; -3c0
_3bc ds.l 1 ; -3bc
_3b8 ds.l 1 ; -3b8
_3b4 ds.l 1 ; -3b4
_3b0 ds.l 1 ; -3b0
_3ac ds.l 1 ; -3ac
_3a8 ds.l 1 ; -3a8
_3a4 ds.l 1 ; -3a4
_3a0 ds.l 1 ; -3a0
_39c ds.l 1 ; -39c
_398 ds.l 1 ; -398
_394 ds.l 1 ; -394
_390 ds.l 1 ; -390
_38c ds.l 1 ; -38c
_388 ds.l 1 ; -388
_384 ds.l 1 ; -384
_380 ds.l 1 ; -380
_37c ds.l 1 ; -37c
_378 ds.l 1 ; -378
_374 ds.l 1 ; -374
_370 ds.l 1 ; -370
_36c ds.l 1 ; -36c
_368 ds.l 1 ; -368
_364 ds.l 1 ; -364
_360 ds.w 1 ; -360
_35e ds.w 1 ; -35e
_35c ds.w 1 ; -35c
_35a ds.w 1 ; -35a
_358 ds.w 1 ; -358
_356 ds.w 1 ; -356
_354 ds.l 1 ; -354
_350 ds.l 1 ; -350
_34c ds.l 1 ; -34c
_348 ds.l 1 ; -348
_344 ds.l 1 ; -344
EWAFiller ds.b 0x340
EndOfPSA
endr
;_______________________________________________________________________
; EXCEPTION WORK AREA
;
; Each CPU has one of these. It is half-heartedly enclosed by a "CPU"
; MP struct. Along with the SPRG registers, it is essential in order
; for the CPU to get its bearings at interrupt time. Each CPU's SPRG0
; always points *into* that CPU's EWA.
;_______________________________________________________________________
EWA record -0x340,INCR
; Fun fact: offsets before here contain the additional kernel globals
; ("Primary System Area"), but only on CPU-0.
; It's kind of complicated, but the CPU MP struct of CPU-0
; starts life as a chunk of the kernel globals, carefully placed
; so the "middle" (zero offset) of the Exception Work Area
; within that CPU struct will equal the "middle" (zero offset)
; of the kernel globals (i.e. between the negative-index v2-only
; Primary System Area and the positive-offset Kernel Data Page).
; Subsequent CPU structs are just large allocations in the kernel
; pool, with the CPU's SPRG0 register being pointed to the zero
; point of that CPU struct's EWA.
CPUBase ds.b 32 ; -340:-320 ; not really part of the EWA, but more an MP struct
Base ; used when init'ed as part of the enclosing CPU struct
; Now for the actual meat of sandwich.
; Many of these fields are used by functions at interrupt time
; to save/restore registers, in lieu of a stack.
TimeList ds.l 4 ; -320:-310, cpu+020
ds.l 1 ; -310, cpu+030
ds.b 1 ; -30c, cpu+034
ds.b 1 ; -30b, cpu+035
ds.b 1 ; -30a, cpu+036
GlobalTimeIsValid ds.b 1 ; -309, cpu+037
ds.l 1 ; -308, cpu+038
ds.l 1 ; -304, cpu+03c
ds.l 1 ; -300, cpu+040
ds.l 1 ; -2fc, cpu+044
ds.l 1 ; -2f8, cpu+048
ds.l 1 ; -2f4, cpu+04c
ds.l 1 ; -2f0, cpu+050
ds.l 1 ; -2ec, cpu+054
GlobalTime ds.l 2 ; -2e8, cpu+058
ThudSavedR29 ds.l 1 ; -2e0, cpu+060
ThudSavedR30 ds.l 1 ; -2dc, cpu+064
ThudSavedR31 ds.l 1 ; -2d8, cpu+068
ds.l 1 ; -2d4, cpu+06c
SIGPSavedR10 ds.l 1 ; -2d0, cpu+070
SIGPSavedR11 ds.l 1 ; -2cc, cpu+074
SIGPSavedR12 ds.l 1 ; -2c8, cpu+078
SIGPSavedR13 ds.l 1 ; -2c4, cpu+07c
SIGPSavedXER ds.l 1 ; -2c0, cpu+080
SIGPSavedCTR ds.l 1 ; -2bc, cpu+084
SIGPSavedLR ds.l 1 ; -2b8, cpu+088
SIGPSavedR6 ds.l 1 ; -2b4, cpu+08c
SIGPSavedR7 ds.l 1 ; -2b0, cpu+090
SIGPSpacOnResume ds.l 1 ; -2ac, cpu+094 ; address space ptr to switch to when plug has executed
ds.l 1 ; -2a8, cpu+098
ds.l 1 ; -2a4, cpu+09c
ds.l 1 ; -2a0, cpu+0a0
ds.l 1 ; -29c, cpu+0a4
ds.l 1 ; -298, cpu+0a8
ds.l 1 ; -294, cpu+0ac
ds.l 1 ; -290, cpu+0b0
ds.l 1 ; -28c, cpu+0b4
ds.l 1 ; -288, cpu+0b8
ds.l 1 ; -284, cpu+0bc
ds.l 1 ; -280, cpu+0c0
ds.l 1 ; -27c, cpu+0c4
SpacesSavedLR ds.l 1 ; -278, cpu+0c8
SpacesSavedCR ds.l 1 ; -274, cpu+0cc
SpacesSavedAreaBase ds.l 1 ; -270, cpu+0d0
SpacesDeferredAreaPtr ds.l 1 ; -26c, cpu+0d4
ds.l 1 ; -268, cpu+0d8
ds.l 1 ; -264, cpu+0dc
SchSavedIncomingTask ds.l 1 ; -260, cpu+0e0
ds.l 1 ; -25c, cpu+0e4
TimerDispatchLR ds.l 1 ; -258, cpu+0e8
ds.l 1 ; -254, cpu+0ec
ds.l 1 ; -250, cpu+0f0
ds.l 1 ; -24c, cpu+0f4
ds.l 1 ; -248, cpu+0f8
ds.l 1 ; -244, cpu+0fc
ds.l 1 ; -240, cpu+100
ds.l 1 ; -23c, cpu+104
SIGPSelector ds.l 1 ; -238, cpu+108
SIGPCallR4 ds.l 1 ; -234, cpu+10c
SIGPCallR5 ds.l 1 ; -230, cpu+110
SIGPCallR6 ds.l 1 ; -22c, cpu+114
SIGPCallR7 ds.l 1 ; -228, cpu+118
SIGPCallR8 ds.l 1 ; -224, cpu+11c
SIGPCallR9 ds.l 1 ; -220, cpu+120
SIGPCallR10 ds.l 1 ; -21c, cpu+124
ds.l 1 ; -218, cpu+128
ds.l 1 ; -214, cpu+12c
ds.l 1 ; -210, cpu+130
ds.l 1 ; -20c, cpu+134
ds.l 1 ; -208, cpu+138
ds.l 1 ; -204, cpu+13c
ds.l 1 ; -200, cpu+140
ds.l 1 ; -1fc, cpu+144
ds.l 1 ; -1f8, cpu+148
ds.l 1 ; -1f4, cpu+14c
ds.l 1 ; -1f0, cpu+150
ds.l 1 ; -1ec, cpu+154
ds.l 1 ; -1e8, cpu+158
ds.l 1 ; -1e4, cpu+15c
ds.l 1 ; -1e0, cpu+160
ds.l 1 ; -1dc, cpu+164
ds.l 1 ; -1d8, cpu+168
ds.l 1 ; -1d4, cpu+16c
ds.l 1 ; -1d0, cpu+170
ds.l 1 ; -1cc, cpu+174
ds.l 1 ; -1c8, cpu+178
ds.l 1 ; -1c4, cpu+17c
ds.l 1 ; -1c0, cpu+180
ds.l 1 ; -1bc, cpu+184
ds.l 1 ; -1b8, cpu+188
ds.l 1 ; -1b4, cpu+18c
ds.l 1 ; -1b0, cpu+190
ds.l 1 ; -1ac, cpu+194
ds.l 1 ; -1a8, cpu+198
ds.l 1 ; -1a4, cpu+19c
ds.l 1 ; -1a0, cpu+1a0
ds.l 1 ; -19c, cpu+1a4
ds.l 1 ; -198, cpu+1a8
ds.l 1 ; -194, cpu+1ac
ds.l 1 ; -190, cpu+1b0
ds.l 1 ; -18c, cpu+1b4
ds.l 1 ; -188, cpu+1b8
ds.l 1 ; -184, cpu+1bc
ds.l 1 ; -180, cpu+1c0
ds.l 1 ; -17c, cpu+1c4
ds.l 1 ; -178, cpu+1c8
ds.l 1 ; -174, cpu+1cc
ds.l 1 ; -170, cpu+1d0
ds.l 1 ; -16c, cpu+1d4
ds.l 1 ; -168, cpu+1d8
ds.l 1 ; -164, cpu+1dc
ds.l 1 ; -160, cpu+1e0
ds.l 1 ; -15c, cpu+1e4
ds.l 1 ; -158, cpu+1e8
ds.l 1 ; -154, cpu+1ec
ds.l 1 ; -150, cpu+1f0
ds.l 1 ; -14c, cpu+1f4
ds.l 1 ; -148, cpu+1f8
ds.l 1 ; -144, cpu+1fc
ds.l 1 ; -140, cpu+200
ds.l 1 ; -13c, cpu+204
ds.l 1 ; -138, cpu+208
ds.l 1 ; -134, cpu+20c
ds.l 1 ; -130, cpu+210
ds.l 1 ; -12c, cpu+214
ds.l 1 ; -128, cpu+218
ds.l 1 ; -124, cpu+21c
ds.l 1 ; -120, cpu+220
ds.l 1 ; -11c, cpu+224
SchEvalFlag ds.b 1 ; -118, cpu+228
TaskPriority ds.b 1 ; -117, cpu+229
CPUIndex ds.w 1 ; -116, cpu+22a
WeMightClear ds.l 1 ; -114, cpu+22c ; still boots if not cleared
ds.l 1 ; -110, cpu+230
ds.l 1 ; -10c, cpu+234
ds.l 1 ; -108, cpu+238
ds.l 1 ; -104, cpu+23c
ds.l 1 ; -100, cpu+240
ds.l 1 ; -0fc, cpu+244
ds.l 1 ; -0f8, cpu+248
ds.l 1 ; -0f4, cpu+24c
ds.l 1 ; -0f0, cpu+250
ds.l 1 ; -0ec, cpu+254
ds.l 1 ; -0e8, cpu+258
SpecialAreaPtr ds.l 1 ; -0e4, cpu+25c ; will panic on page fault if this is not valid
ds.l 1 ; -0e0, cpu+260
ds.l 1 ; -0dc, cpu+264
ds.l 1 ; -0d8, cpu+268
ds.l 1 ; -0d4, cpu+26c
ds.l 1 ; -0d0, cpu+270
ds.l 1 ; -0cc, cpu+274
ds.l 1 ; -0c8, cpu+278
ds.l 1 ; -0c4, cpu+27c
ds.l 1 ; -0c0, cpu+280
ds.l 1 ; -0bc, cpu+284
ds.l 1 ; -0b8, cpu+288
ds.l 1 ; -0b4, cpu+28c
ds.l 1 ; -0b0, cpu+290
ds.l 1 ; -0ac, cpu+294
ds.l 1 ; -0a8, cpu+298
ds.l 1 ; -0a4, cpu+29c
ds.l 1 ; -0a0, cpu+2a0
ds.l 1 ; -09c, cpu+2a4
ds.l 1 ; -098, cpu+2a8
ds.l 1 ; -094, cpu+2ac
ds.l 1 ; -090, cpu+2b0
ds.l 1 ; -08c, cpu+2b4
ds.l 1 ; -088, cpu+2b8
ds.l 1 ; -084, cpu+2bc
ds.l 1 ; -080, cpu+2c0
ds.l 1 ; -07c, cpu+2c4
ds.l 1 ; -078, cpu+2c8
ds.l 1 ; -074, cpu+2cc
ds.l 1 ; -070, cpu+2d0
ds.l 1 ; -06c, cpu+2d4
ds.l 1 ; -068, cpu+2d8
ds.l 1 ; -064, cpu+2dc
PoolSavedLR ds.l 1 ; -060, cpu+2e0
PoolSavedSizeArg ds.l 1 ; -05c, cpu+2e4
ds.l 1 ; -058, cpu+2e8
ds.l 1 ; -054, cpu+2ec
ds.l 1 ; -050, cpu+2f0
ds.l 1 ; -04c, cpu+2f4
ds.l 1 ; -048, cpu+2f8
ds.l 1 ; -044, cpu+2fc
CreateAreaSavedLR ds.l 1 ; -040, cpu+300
CreateAreaSavedR25 ds.l 1 ; -03c, cpu+304 ; ???!!!
CreateAreaSavedR26 ds.l 1 ; -038, cpu+308
CreateAreaSavedR27 ds.l 1 ; -034, cpu+30c
CreateAreaSavedR28 ds.l 1 ; -030, cpu+310
CreateAreaSavedR29 ds.l 1 ; -02c, cpu+314
CreateAreaSavedR30 ds.l 1 ; -028, cpu+318
CreateAreaSavedR31 ds.l 1 ; -024, cpu+31c
PA_IRP ds.l 1 ; -020, cpu+320
PA_CurAddressSpace ds.l 1 ; -01c, cpu+324
PA_PSA ds.l 1 ; -018, cpu+328
PA_ContextBlock ds.l 1 ; -014, cpu+32c
Flags ds.l 1 ; -010, cpu+330
Enables ds.l 1 ; -00c, cpu+334
PA_CurTask ds.l 1 ; -008, cpu+338
PA_KDP ds.l 1 ; -004, cpu+33c
; ZERO (SPRG0 points here)
r0 ds.l 1 ; 000, cpu+340 ; used for quick register saves at exception time...
r1 ds.l 1 ; 004, cpu+344
r2 ds.l 1 ; 008, cpu+348
r3 ds.l 1 ; 00c, cpu+34c
r4 ds.l 1 ; 010, cpu+350
r5 ds.l 1 ; 014, cpu+354
r6 ds.l 1 ; 018, cpu+358
r7 ds.l 1 ; 01c, cpu+35c
r8 ds.l 1 ; 020, cpu+360
r9 ds.l 1 ; 024, cpu+364
r10 ds.l 1 ; 028, cpu+368
r11 ds.l 1 ; 02c, cpu+36c
r12 ds.l 1 ; 030, cpu+370
r13 ds.l 1 ; 034, cpu+374
r14 ds.l 1 ; 038, cpu+378
r15 ds.l 1 ; 03c, cpu+37c
r16 ds.l 1 ; 040, cpu+380
r17 ds.l 1 ; 044, cpu+384
r18 ds.l 1 ; 048, cpu+388
r19 ds.l 1 ; 04c, cpu+38c
r20 ds.l 1 ; 050, cpu+390
r21 ds.l 1 ; 054, cpu+394
r22 ds.l 1 ; 058, cpu+398
r23 ds.l 1 ; 05c, cpu+39c
r24 ds.l 1 ; 060, cpu+3a0
r25 ds.l 1 ; 064, cpu+3a4
r26 ds.l 1 ; 068, cpu+3a8
r27 ds.l 1 ; 06c, cpu+3ac
r28 ds.l 1 ; 070, cpu+3b0
r29 ds.l 1 ; 074, cpu+3b4
r30 ds.l 1 ; 078, cpu+3b8
r31 ds.l 1 ; 07c, cpu+3bc
; Fun fact: offsets past here contain the main kernel globals
; ("Kernel Data Page"), but only on CPU-0.
endr
MemLayout record 0,INCR
SegMapPtr ds.l 1
BatMap ds.l 1 ; packed array of 4-bit indices into BATs
endr
BAT record 0,INCR
U ds.l 1
L ds.l 1
endr
;_______________________________________________________________________
; KERNEL DATA PAGE
;
; Positive offsets from the kernel global pointer (which can be found
; in the PA_KDP field of any CPU's EWA, and directly in the SPRG0 of
; CPU-0). Except for offsets < 128 bytes, which belong to the GPR save
; area of CPU-0's EWA (see the r0, r1 etc. directly above here?)
;_______________________________________________________________________
KDP record 0x80,INCR
SegMaps
SegMap32SupInit ds.l 32 ; 080:100
SegMap32UsrInit ds.l 32 ; 100:180
SegMap32CPUInit ds.l 32 ; 180:200
SegMap32OvlInit ds.l 32 ; 200:280
BATs ds.l 32 ; 280:300
CurIBAT0 ds BAT ; 300:308
CurIBAT1 ds BAT ; 308:310
CurIBAT2 ds BAT ; 310:318
CurIBAT3 ds BAT ; 318:320
CurDBAT0 ds BAT ; 320:328
CurDBAT1 ds BAT ; 328:330
CurDBAT2 ds BAT ; 330:338
CurDBAT3 ds BAT ; 338:340
NCBPointerCache
NCBCacheLA0 ds.l 1 ; 340
NCBCachePA0 ds.l 1 ; 344
NCBCacheLA1 ds.l 1 ; 348
NCBCachePA1 ds.l 1 ; 34c
NCBCacheLA2 ds.l 1 ; 350
NCBCachePA2 ds.l 1 ; 354
NCBCacheLA3 ds.l 1 ; 358
NCBCachePA3 ds.l 1 ; 35c
NCBPointerCacheEnd
VecBaseSystem ds.l 48 ; 360:420 ; when 68k emulator is running, *or* any MTask
VecBaseAlternate ds.l 48 ; 420:4e0 ; native PowerPC in blue task
VecBaseMemRetry ds.l 48 ; 4e0:5a0 ; "FDP" instruction emulation
FloatEmScratch ds.d 1 ; 5a0:5a8
TopOfFreePages ds.l 1 ; 5a8 ; gotten from the old SPRG0
ds.l 1 ; 5ac
PARPerSegmentPLEPtrs ds.l 4 ; 5b0:5c0 ; for each PAR segment, a ptr into the PAR PageList
FloatingPtTemp1 ds.l 1 ; 5c0
FloatingPtTemp2 ds.l 1 ; 5c4
SupervisorMemLayout ds MemLayout ; 5c8:5d0
UserMemLayout ds MemLayout ; 5d0:5d8
CpuMemLayout ds MemLayout ; 5d8:5e0
OverlayMemLayout ds MemLayout ; 5e0:5e8
CurrentMemLayout ds MemLayout ; 5e8:5f0
NanoKernelCallTable ds.l 16 ; 5f0:630
PA_ConfigInfo ds.l 1 ; 630
PA_EmulatorData ds.l 1 ; 634
KernelMemoryBase ds.l 1 ; 638
KernelMemoryEnd ds.l 1 ; 63c ; Top of HTAB (and entire kernel reserved area). Set by Init.s
PA_RelocatedLowMemInit ds.l 1 ; 640 ; From ConfigInfo. Ptr to Mac LowMem vars, which Init.s sets up
SharedMemoryAddr ds.l 1 ; 644 ; From ConfigInfo. Not sure what latest use is.
LA_EmulatorKernelTrapTable ds.l 1 ; 648 ; Calculated from ConfigInfo.
PA_NanoKernelCode ds.l 1 ; 64c ; Calculated by NanoKernel itself.
PA_FDP ds.l 1 ; 650 ; See notes in NanoKernel. Very interesting.
LA_ECB ds.l 1 ; 654 ; Logical ptr into EDP.
PA_ECB ds.l 1 ; 658 ; gets called "system context"
PA_ContextBlock ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2
Flags ds.l 1 ; 660 ; moved to EWA (per-CPU) in NKv2
Enables ds.l 1 ; 664 ; moved to EWA (per-CPU) in NKv2
OtherContextDEC ds.l 1 ; 668 ; ticks the *inactive* context has left out of 1s
PA_PageMapEnd ds.l 1 ; 66c ; Set at the same time as PA_PageMapStart below...
TestIntMaskInit ds.l 1 ; 670 ; These are all copied from ConfigInfo...
PostIntMaskInit ds.l 1 ; 674
ClearIntMaskInit ds.l 1 ; 678
PA_EmulatorIplValue ds.l 1 ; 67c ; Physical ptr into EDP
DebugIntPtr ds.l 1 ; 680 ; Within (debug?) shared memory
PA_PageMapStart ds.l 1 ; 684 ; Physical ptr to PageMap (= KDP+0x920)
PageAttributeInit ds.l 1 ; 688 ; defaults for page table entries (see ConfigInfo)
HtabTempPage ds.l 1 ; 68c
HtabTempEntryPtr ds.l 1 ; 690
NewestPageInHtab ds.l 1 ; 694
ApproxCurrentPTEG ds.l 1 ; 698
OverflowingPTEG ds.l 1 ; 69c
PTEGMask ds.l 1 ; 6a0
HTABORG ds.l 1 ; 6a4
VMLogicalPages ds.l 1 ; 6a8 ; set at init and changed by VMInit
TotalPhysicalPages ds.l 1 ; 6ac ; does not take into acct maximum MacOS memory
PARPageListPtr ds.l 1 ; 6b0 ; VM puts this in system heap
VMMaxVirtualPages ds.l 1 ; 6b4 ; always 5fffe000, even with VM on
CpuSpecificBytes
CpuSpecificByte1 ds.b 1 ; 6b8 ; seems to contain flags (set from PVR & tbl by Init.s)
CpuSpecificByte2 ds.b 1 ; 6b9 ; probably not flags (set in same way)
ds.b 1 ; 6ba
ds.b 1 ; 6bb
ds.l 1 ; 6bc
ds.l 16 ; 6c0 ; was PARPerSegmentPLEPtrs
StartOfPanicArea ; PROTECTED BY THUD LOCK
ThudSavedR0 ds.l 1 ; 700
ThudSavedR1 ds.l 1 ; 704 ; via SPRG1
ThudSavedR2 ds.l 1 ; 708
ThudSavedR3 ds.l 1 ; 70c
ThudSavedR4 ds.l 1 ; 710
ThudSavedR5 ds.l 1 ; 714
ThudSavedR6 ds.l 1 ; 718
ThudSavedR7 ds.l 1 ; 71c
ThudSavedR8 ds.l 1 ; 720
ThudSavedR9 ds.l 1 ; 724
ThudSavedR10 ds.l 1 ; 728
ThudSavedR11 ds.l 1 ; 72c
ThudSavedR12 ds.l 1 ; 730
ThudSavedR13 ds.l 1 ; 734
ThudSavedR14 ds.l 1 ; 738
ThudSavedR15 ds.l 1 ; 73c
ThudSavedR16 ds.l 1 ; 740
ThudSavedR17 ds.l 1 ; 744
ThudSavedR18 ds.l 1 ; 748
ThudSavedR19 ds.l 1 ; 74c
ThudSavedR20 ds.l 1 ; 750
ThudSavedR21 ds.l 1 ; 754
ThudSavedR22 ds.l 1 ; 758
ThudSavedR23 ds.l 1 ; 75c
ThudSavedR24 ds.l 1 ; 760
ThudSavedR25 ds.l 1 ; 764
ThudSavedR26 ds.l 1 ; 768
ThudSavedR27 ds.l 1 ; 76c
ThudSavedR28 ds.l 1 ; 770
ThudSavedR29 ds.l 1 ; 774
ThudSavedR30 ds.l 1 ; 778
ThudSavedR31 ds.l 1 ; 77c
ThudSavedCR ds.l 1 ; 780
ThudSavedMQ ds.l 1 ; 784
ThudSavedXER ds.l 1 ; 788
ThudSavedSPRG2 ds.l 1 ; 78c ; 'LR'
ThudSavedCTR ds.l 1 ; 790
ThudSavedPVR ds.l 1 ; 794
ThudSavedDSISR ds.l 1 ; 798
ThudSavedDAR ds.l 1 ; 79c
ThudSavedTBU ds.l 1 ; 7a0 ; RTCU on 601
ThudSavedTB ds.l 1 ; 7a4 ; RTCL on 601
ThudSavedDEC ds.l 1 ; 7a8
ThudSavedHID0 ds.l 1 ; 7ac
ThudSavedSDR1 ds.l 1 ; 7b0
ThudSavedSRR0 ds.l 1 ; 7b4
ThudSavedSRR1 ds.l 1 ; 7b8
ThudSavedMSR ds.l 1 ; 7bc
ThudSavedSR0 ds.l 1 ; 7c0
ThudSavedSR1 ds.l 1 ; 7c4
ThudSavedSR2 ds.l 1 ; 7c8
ThudSavedSR3 ds.l 1 ; 7cc
ThudSavedSR4 ds.l 1 ; 7d0
ThudSavedSR5 ds.l 1 ; 7d4
ThudSavedSR6 ds.l 1 ; 7d8
ThudSavedSR7 ds.l 1 ; 7dc
ThudSavedSR8 ds.l 1 ; 7e0
ThudSavedSR9 ds.l 1 ; 7e4
ThudSavedSR10 ds.l 1 ; 7e8
ThudSavedSR11 ds.l 1 ; 7ec
ThudSavedSR12 ds.l 1 ; 7f0
ThudSavedSR13 ds.l 1 ; 7f4
ThudSavedSR14 ds.l 1 ; 7f8
ThudSavedSR15 ds.l 1 ; 7fc
ThudSavedF0 ds.d 1 ; KDP.BATs + 0xa0
ThudSavedF1 ds.d 1 ; 808
ThudSavedF2 ds.d 1 ; 810
ThudSavedF3 ds.d 1 ; 818
ThudSavedF4 ds.d 1 ; 820
ThudSavedF5 ds.d 1 ; 828
ThudSavedF6 ds.d 1 ; 830
ThudSavedF7 ds.d 1 ; 838
ThudSavedF8 ds.d 1 ; 840
ThudSavedF9 ds.d 1 ; 848
ThudSavedF10 ds.d 1 ; 850
ThudSavedF11 ds.d 1 ; 858
ThudSavedF12 ds.d 1 ; 860
ThudSavedF13 ds.d 1 ; 868
ThudSavedF14 ds.d 1 ; 870
ThudSavedF15 ds.d 1 ; 878
ThudSavedF16 ds.d 1 ; 880
ThudSavedF17 ds.d 1 ; 888
ThudSavedF18 ds.d 1 ; 890
ThudSavedF19 ds.d 1 ; 898
ThudSavedF20 ds.d 1 ; 8a0
ThudSavedF21 ds.d 1 ; 8a8
ThudSavedF22 ds.d 1 ; 8b0
ThudSavedF23 ds.d 1 ; 8b8
ThudSavedF24 ds.d 1 ; 8c0
ThudSavedF25 ds.d 1 ; 8c8
ThudSavedF26 ds.d 1 ; 8d0
ThudSavedF27 ds.d 1 ; 8d8
ThudSavedF28 ds.d 1 ; 8e0
ThudSavedF29 ds.d 1 ; 8e8
ThudSavedF30 ds.d 1 ; 8f0
ThudSavedF31 ds.d 1 ; 8f8
SomethingSerial ds.l 1 ; 900 ; 'fpscr'
ThudSavedLR ds.l 1 ; 904 ; 'caller'
RTAS_Proc ds.l 1 ; 908 ; r8 on kernel entry
EndOfPanicArea
RTAS_PrivDataArea ds.l 1 ; 90c ; copied from HWInfo
ZeroWord ds.l 1 ; 910 ; Only NewWorld and Unknown PIHes touch this
ds.l 1 ; 914
ds.l 1 ; 918
ds.l 1 ; 91c
ds.b 0x3a0 ; 920:cc0
SysInfo ds NKSystemInfo ; cc0:d80
DiagInfo ds NKDiagInfo ; d80:e80
NKInfo ds NKNanoKernelInfo; e80:f80 ; see NKNanoKernelInfo in PPCInfoRecordsPriv
ProcInfo ds NKProcessorInfo ; f80:fc0
InfoRecBlk
endr
;_______________________________________________________________________
; KERNEL VECTOR TABLE
;
; The kernel creates several of these, and activates one by pointing
; a CPU's SPRG3 ("vecBase") register at it. Find them in PSA and KDP.
; (For want of more information, I have colour coded them for now.)
;
; Each entry is a (hopefully 64-byte aligned) physical pointer to an
; interrupt service routine in the kernel. One entry roughly
; corresponds with one of the 256-byte aligned entry points into
; the PowerPC interrupt (="exception") vector table. Code for those
; can be found in :RISC:ExceptionTable.s.
;_______________________________________________________________________
VecTable record 0,INCR
; VBGYOR
ds.l 1 ; 00 ; scratch for IVT?
SystemResetVector ds.l 1 ; 04 ; called by IVT+100 (system reset)
MachineCheckVector ds.l 1 ; 08 ; called by IVT+200 (machine check)
DSIVector ds.l 1 ; 0c ; called by IVT+300 (DSI)
ISIVector ds.l 1 ; 10 ; called by IVT+400 (ISI)
ExternalIntVector ds.l 1 ; 14 ; called by IVT+500 (external interrupt)
AlignmentIntVector ds.l 1 ; 18 ; called by IVT+600 (alignment)
ProgramIntVector ds.l 1 ; 1c ; called by IVT+700 (program)
FPUnavailVector ds.l 1 ; 20 ; called by IVT+KDP.BATs + 0xa0 (FP unavail)
DecrementerVector ds.l 1 ; 24 ; called by IVT+900 (decrementer)
ReservedVector1 ds.l 1 ; 28 ; called by IVT+a00 (reserved)
ReservedVector2 ds.l 1 ; 2c ; called by IVT+b00 (reserved)
SyscallVector ds.l 1 ; 30 ; called by IVT+c00 (system call)
TraceVector ds.l 1 ; 34 ; called by IVT+d00 (trace)
FPAssistVector ds.l 1 ; 38 ; called by IVT+e00 (FP assist)
PerfMonitorVector ds.l 1 ; 3c ; called by IVT+f00 (perf monitor)
ds.l 1 ; 40 ;
ds.l 1 ; 44 ;
ds.l 1 ; 48 ;
ds.l 1 ; 4c ; Vectors from here downwards are called from
ds.l 1 ; 50 ; odd places in the IVT????
ds.l 1 ; 54 ;
ds.l 1 ; 58 ; seems AltiVec-related
ThermalEventVector ds.l 1 ; 5c ;
ds.l 1 ; 60 ;
ds.l 1 ; 64 ;
ds.l 1 ; 68 ;
ds.l 1 ; 6c ;
ds.l 1 ; 70 ;
ds.l 1 ; 74 ;
ds.l 1 ; 78 ;
ds.l 1 ; 7c ;
ds.l 1 ; 80 ; shares with TraceVector in Y and G
ds.l 1 ; 84 ;
ds.l 1 ; 88 ;
ds.l 1 ; 8c ;
ds.l 1 ; 90 ;
ds.l 1 ; 94 ;
ds.l 1 ; 98 ;
ds.l 1 ; 9c ;
ds.l 1 ; a0 ;
ds.l 1 ; a4 ;
ds.l 1 ; a8 ;
ds.l 1 ; ac ;
ds.l 1 ; b0 ;
ds.l 1 ; b4 ;
ds.l 1 ; b8 ;
ds.l 1 ; bc ; called by IVT+0 (reserved)
Size equ *
endr
;_______________________________________________________________________
; NANOKERNEL CALL (KCALL) TABLE
;
; You can also use this record to index the NanoKernelCallCounts in
; PPCInfoRecordsPriv.s:NKNanoKernelInfo.
;_______________________________________________________________________
NanoKernelCallTable record 0,INCR
ReturnFromException ds.l 1 ; 00, kdp+5f0, trap 0 ; SS replaces with jump to emu+f900
RunAlternateContext ds.l 1 ; 04, kdp+5f4, trap 1
ResetSystem ds.l 1 ; 08, kdp+5f8, trap 2 ; SS replaces with jump to emu+fb00
VMDispatch ds.l 1 ; 0c, kdp+5fc, trap 3 ; FE0A (VM/MMU/NK) trap
PrioritizeInterrupts ds.l 1 ; 10, kdp+600, trap 4 ; SS forbids
PowerDispatch ds.l 1 ; 14, kdp+604, trap 5 ; FEOF
RTASDispatch ds.l 1 ; 18, kdp+608, trap 6 ; SS forbids the use of this trap and below
CacheDispatch ds.l 1 ; 1c, kdp+60c, trap 7
MPDispatch ds.l 1 ; 20, kdp+610, trap 8 ; also accessible via syscall interface
ds.l 1 ; 24, kdp+614, trap 9 ; unused
ds.l 1 ; 28, kdp+618, trap 10 ; unused
ds.l 1 ; 2c, kdp+61c, trap 11 ; unused
CallAdapterProcPPC ds.l 1 ; 30, kdp+620, trap 12 ; unused
ds.l 1 ; 34, kdp+624, trap 13 ; unused
CallAdapterProc68k ds.l 1 ; 38, kdp+628, trap 14 ; unused
Thud ds.l 1 ; 3c, kdp+62c, trap 15 ; basically just panic
Size equ *
endr
;_______________________________________________________________________
; PAGEMAP DESCRIPTOR TABLE
;
; An 8-byte entry in the PageMap tables passed to the NanoKernel via
; ConfigInfo. Roughly corresponds with a contiguous logical address
; range lying within 256MB (segment) boundaries, and therefore
; roughly corresponds with the NKv2 MP "Area" struct.
;
; It could be that these are actually PageMap Descriptor *Entries*,
; and I have misunderstood.
;_______________________________________________________________________
PME record 0,INCR
LBase ds.w 1 ; 0 ; (base - segment) >> 12
PageCount ds.w 1 ; 2 ; page count MINUS ONE
PBaseAndFlags ds.l 1 ; 4 ; PBase page aligned
PBaseBits equ 20
FirstFlagBit equ 20
FirstFlag equ 0x800
DaddyFlag equ 0x800
CountingFlag equ 0x400
PhysicalIsRelativeFlag equ 0x200
; try not to use the equates above; they are dicey
TopFieldMask equ 0xe00
Size equ *
endr
;_______________________________________________________________________
; KERNEL SPINLOCK
;
; Seven of these, each with a four-byte signature, live in the PSA.
; The signatures describe the protected structures adequately.
;
; The function to acquire a lock seems to have been inlined, because
; it always saves and restores r8 and r9 (even to and from themselves)
; around a bl to NanoKernelInit.s:AcquireLock. It has therefore been
; macrofied as NanoKernelMacros.s:_Lock.
;_______________________________________________________________________
Lock record 0,INCR
Count ds.l 1 ; 00 ; target for lwarx/stwcx
Signature ds.l 1 ; 04
kHTABLockSignature equ 'htab'
kPIHLockSignature equ 'pih '
kSchLockSignature equ 'sch '
kThudLockSignature equ 'thud'
kRTASLockSignature equ 'rtas'
kDbugLockSignature equ 'dbug'
kPoolLockSignature equ 'pool'
org 0x10
Holder ds.l 1 ; 10
org 0x20
endr
; Structs after this point are inadequately commented. Sorry!
Index record 0,INCR
kSignature equ 'INDX'
HalfOne ds.w 1 ; 000
HalfTwo ds.w 1 ; 002
Signature ds.l 1 ; 004
IDsPtr ds.l 1 ; 008
org 520
Size equ *
endr
; Special opaque NanoKernel stuff!
; These seem to go in a notification queue?
LLL record 0,INCR
Freeform ds.l 1 ; 0
Signature ds.l 1 ; 4
Next ds.l 1 ; 8
Prev ds.l 1 ; c
endr
; Special case of LLL
; Init'ed by InitTMRQs (called by Init.s)
; There is one copy of this struct at kdp-a84 below the (shorter) queue structs,
; and two copies in the pool, pointed to by kdp-434 and kdp-364.
TimerQueueStruct record 0,INCR
LLL ds.l 4 ; 00
Unused ds.l 1 ; 10
ZeroByte ds.b 1 ; 14 ; can also be set to 7 or 8
UnusedByte ds.b 1 ; 15
OneByte1 ds.b 1 ; 16
OneByte2 ds.b 1 ; 17 ; can also be unset
; GAP
org 0x38
TimeCtr ds.d 1 ; 38 ; high half in DEC reg or whole thing in TB
endr
; For altivec, mofo
VectorSaveArea record 0,INCR
org 23*16
;RegisterAreaSize equ *-VectorSaveArea
RegisterAreaSize equ 23*16
org 32*16 + 20
endr

2
Linker/LinkPowerROM
View File

@ -86,7 +86,7 @@ End
Echo ------------------------------
Echo "Running PPCLink..."
PPCLink -xm library -codestart 0 -warn -o "{DEST_X}" {LinkList}
PPCLink -xm library -dead off -codestart 0 -warn -o "{DEST_X}" {LinkList}
Echo "Dumping temp xcoff to DEST..."
"{CTOOL}" fromx "{DEST_X}" "{DEST}"

61
NanoKernel/NKAdditions.s
View File

@ -1,61 +0,0 @@
;_______________________________________________________________________
; My additions to the NanoKernel, to go at the end of the code image
;_______________________________________________________________________
if &TYPE('NKDebugShim') != 'UNDEFINED'
DeclareMPCall 200, NKDebug
NKDebug
; Lifted from NKxprintf:
; Put the physical address of the r3 arg in r8
rlwinm. r9, r11, 0, MSR_DRbit, MSR_DRbit ; IntSyscall sets this
mr r8, r3
beq @already_physical
li r9, 0
bl SpaceL2PUsingBATs ; LogicalPage *r8, MPAddressSpace *r9 // PhysicalPage *r17
beq @fail
rlwimi r8, r17, 0, 0, 19
@already_physical
; Copy the command into the KDP buffer reserved for this purpose:
; r8 = src
; r29 = dest
; r30 = ctr
; r31 = val
mfsprg r1, 0
lwz r1, EWA.PA_KDP(r1)
li r30, 0
addi r29, r1, PSA.ThudBuffer
@cmdloop
lbzx r31, r8, r30
stbx r31, r29, r30
addi r30, r30, 1
cmpwi r31, 0
bne @cmdloop
lwz r31, PSA._404(r1)
stw r8, PSA._404(r1)
bl panic
lwz r8, PSA._404(r1)
li r0, 0
stw r0, 0(r8)
stw r31, PSA._404(r1)
b ReturnZeroFromMPCall
@fail
b ReturnMPCallOOM
endif

4846
NanoKernel/NKAddressSpaces.s
View File

File diff suppressed because it is too large Load Diff

1393
NanoKernel/NKBuiltinInit.s
View File

File diff suppressed because it is too large Load Diff

538
NanoKernel/NKCache.s
View File

@ -1,538 +0,0 @@
###### ### ###### ## ## ######## ###### ### ## ##
## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ## ## ## ## ##
## ## ## ## ######### ###### ## ## ## ## ##
## ######### ## ## ## ## ## ######### ## ##
## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
###### ## ## ###### ## ## ######## ###### ## ## ######## ########
; Enable/disable/probe the L1/2 data/inst cache
; Probably called using an unknown 68k F-trap. Not usually called on my
; G4, but can be tested by hacking the MPCall table. Uses fancy new CPU
; features (MSSCR0), so probably not legacy code. For CPU accelerator
; cards? `FlushCache` needs to be nopped out to prevent a crash.
; ARGUMENT (r3)
; r3.hi = action flags
; enable specified caches $8000
; disable specified caches $4000
; report pre-change state $2000
; also enable (???) $1000
; enable/disable I-cache $0800
; enable/disable D-cache $0400
;
; r3.lo = which cache (L1/2)
; level 1 1
; level 2 2
;
; RETURN VALUE (r3)
; r3.hi = pre-change state flags (resemble action flags)
; both caches disabled $4000
; either cache enabled $8000
; I-cache enabled $0800
; D-cache enabled $0400
;
; r3.lo = return status
; success 0
; failure < 0
; checked L1 but did not set 1
; checked L2 but did not set 2
; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKExceptions
; IntReturn
; EXPORTS:
; FlushCaches (=> NKPowerCalls)
; FlushL1CacheUsingMSSCR0 (=> NKIntHandlers)
; kcCacheDispatch (=> NKInit)
; DeclareMPCall 199, kcCacheDispatch ; DEBUG
kcCacheDispatch
_RegRangeToContextBlock r21, r23 ; get some breathing room
; _log 'kcCacheDispatch ' ; DEBUG
; mr r8, r3 ; DEBUG
; bl printw ; DEBUG
; _log '^n' ; DEBUG
clrlwi r8, r3, 16 ; bad selector
cmplwi r8, 2
bgt @fail_bad_selector
lwz r8, KDP.ProcInfo.ProcessorFlags(r1)
andi. r8, r8, 1 << NKProcessorInfo.hasL2CR
beq CacheCallFailNoL2 ; no L2CR => fail (what about 601?)
rlwinm. r9, r3, 0, 2, 2 ; if flagged, get cache state in r23
bnel CacheCallGetInfoForReturnValue ; (otherwise, r23 is undefined)
srwi r8, r3, 30 ; cannot enable *and* disable
cmpwi r8, 3
beq CacheCallFailBadFlags
clrlwi r8, r3, 16 ; go to main code for level 1/2 cache
cmplwi r8, 1
beq CacheCallDispatchL1
cmplwi r8, 2
beq CacheCallDispatchL2
@fail_bad_selector ; fall through => bad selector
lisori r3, -2
b CacheCallReturn
### ## ## ###
## ## #### ##
## ## ## ##
## ## ## ##
## ## ## ##
## ## ## ##
### ######## ###### ###
CacheCallDispatchL1
rlwinm. r9, r3, 0, 1, 1
bne CacheCallL1DisableSelected
rlwinm. r9, r3, 0, 0, 0
bne CacheCallL1EnableSelected
rlwinm. r9, r3, 0, 3, 3 ; ???
bl FlushCaches
b CacheCallReturn
CacheCallL1DisableSelected
bl FlushCaches
rlwinm r22, r3, 0, 4, 5 ; shift arg bits to align with HID0[DCE/ICE]
srwi r22, r22, 12
mfspr r21, hid0
andc r21, r21, r22 ; HID0 &= ~mybits
sync
mtspr hid0, r21
li r3, 0
b CacheCallReturn
CacheCallL1EnableSelected
rlwinm r22, r3, 0, 4, 5 ; shift arg bits to align with HID0[DCE/ICE]
srwi r22, r22, 12
mfspr r21, hid0
or r21, r21, r22 ; HID0 |= mybits
sync
mtspr hid0, r21
li r3, 0
b CacheCallReturn
### ## ####### ###
## ## ## ## ##
## ## ## ##
## ## ####### ##
## ## ## ##
## ## ## ##
### ######## ######### ###
CacheCallDispatchL2
rlwinm. r9, r3, 0, 1, 1
bne CacheCallL2DisableSelected
rlwinm. r9, r3, 0, 0, 0
bne CacheCallL2EnableSelected
rlwinm. r9, r3, 0, 3, 3
bne CacheCallL2Flag3 ; goes to DisableSelected
rlwinm. r9, r3, 0, 2, 2
;bne removed?
bne CacheCallReturn
CacheCallFailBadFlags
lisori r3, -4
b CacheCallReturn
CacheCallL2Flag3
bl CacheCallL2DisableSelected ; typo? should be `b`
CacheCallL2EnableSelected
mfspr r21, l2cr ; fail if L2CR[L2E] already set
sync
andis. r21, r21, 0x8000
bne CacheCallReturn
lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
and. r8, r8, r8
beq CacheCallFailNoL2 ; fail if zero-sized cache reported
mfspr r21, hid0 ; save HID0
rlwinm r8, r21, 0, 12, 10 ; clear HID0[DPM] (dynamic power management)
mtspr hid0, r8 ; presumably to keep L2 working while we wait?
sync
addi r8, r1, PSA.ProcessorState
lwz r8, NKProcessorState.saveL2CR(r8)
and. r8, r8, r8
beq CacheCallReturn ; fail if zero L2CR was saved?
sync
lis r9, 0x0020 ; set L2CR[GI] (global invalidate)
or r8, r8, r9
mtspr l2cr, r8
sync
@inval_loop
mfspr r8, l2cr ; check L2CR[IP] (invalidate progress)
sync
andi. r9, r8, 1
bne @inval_loop
lis r9, 0x0020 ; clear L2CR[GI]
andc r8, r8, r9
mtspr l2cr, r8
sync
lis r9, 0x8000 ; set L2CR[L2E] (L2 enable)
or r8, r8, r9
mtspr l2cr, r8
sync
mtspr hid0, r21 ; restore HID0
sync
li r3, 0 ; return successfully
b CacheCallReturn
CacheCallFailNoL2
li r3, -2
b CacheCallReturn
CacheCallL2DisableSelected
mfspr r22, l2cr ; return if already disabled per L2CR[L2E]
sync
andis. r22, r22, 0x8000
beq CacheCallReturn
bl FlushCaches
mfspr r22, l2cr ; clear L2CR[L2E]
sync
clrlwi r22, r22, 1
mtspr l2cr, r22
sync
addi r8, r1, PSA.ProcessorState
stw r22, NKProcessorState.saveL2CR(r8) ; update saveL2CR
sync
rlwinm r22, r22, 0, 7, 3 ; clear L2CR[3/5/6] (all reserved)
oris r22, r22, 0x0010 ; set L2CR[13] (also reserved)
mtspr l2cr, r22
sync
;b CacheCallReturn ; fall through
### ######## ######## ######## ## ## ######## ## ## ###
## ## ## ## ## ## ## ## ## ### ## ##
## ## ## ## ## ## ## ## ## #### ## ##
## ######## ###### ## ## ## ######## ## ## ## ##
## ## ## ## ## ## ## ## ## ## #### ##
## ## ## ## ## ## ## ## ## ## ### ##
### ## ## ######## ## ####### ## ## ## ## ###
CacheCallReturn
ori r23, r23, 0xffff ; put the r23.hi from CacheCallGetInfoForReturnValue into r3.hi
oris r3, r3, 0xffff
and r3, r3, r23
CacheCallReturnWithoutFlags
_RegRangeFromContextBlock r21, r23
sync
; _log 'Return ' ; DEBUG
; mr r8, r3 ; DEBUG
; bl printw ; DEBUG
; _log '^n' ; DEBUG
b IntReturn
### ######## ######## ####### ######## ######## ###
## ## ## ## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ## ## ## ##
## ######## ######## ## ## ######## ###### ##
## ## ## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ## ## ##
### ## ## ## ####### ######## ######## ###
; RET r23.hi = flags describing state of specified cache (see top of file)
CacheCallGetInfoForReturnValue
clrlwi r8, r3, 16
cmplwi r8, 1
beq @level1
cmplwi r8, 2
beq @level2
lisori r3, -5
b CacheCallReturnWithoutFlags
@level1
mfspr r21, hid0
rlwinm. r21, r21, 12, 4, 5
beq @all_off
oris r23, r21, 0x8000
blr
@level2
lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
and. r8, r8, r8
beq CacheCallFailNoL2
mfspr r21, hid0 ; same bits as above
rlwinm r21, r21, 12, 4, 5
mfspr r22, l2cr ; L2-D is on if L1-D is on and L2CR[DO] is cleared
rlwinm r22, r22, 5, 4, 4
andc r21, r21, r22
mfspr r22, l2cr ; then again, both L2s are off if L2CR[L2E] is cleared
andis. r22, r22, 0x8000
beq @all_off
or r23, r21, r22
blr
@all_off
lisori r23, 0x40000000
blr
######## ## ## ## ###### ## ## ######## ## ## ## ## ###### ######
## ## ## ## ## ## ## ## ## ## ## ### ## ## ## ## ##
## ## ## ## ## ## ## ## ## ## #### ## ## ##
###### ## ## ## ###### ######### ###### ## ## ## ## ## ## ######
## ## ## ## ## ## ## ## ## ## ## #### ## ##
## ## ## ## ## ## ## ## ## ## ## ## ### ## ## ## ##
## ######## ####### ###### ## ## ## ####### ## ## ###### ######
; Flush L1 and L2 caches
; Also used by NKPowerCalls.s
; ARG KDP *r1, ContextBlock *r6
; CLOB r8, r9, cr
FlushCaches
; blr ; DEBUG
; Be cautious
mfctr r8
stw r25, ContextBlock.r25(r6)
stw r24, ContextBlock.r24(r6)
stw r8, ContextBlock.KernelCTR(r6)
; Flush level 1
lhz r25, KDP.ProcInfo.DataCacheLineSize(r1)
and. r25, r25, r25 ; r25 = L1-D line size
cntlzw r8, r25
beq @return
subfic r9, r8, 31 ; r9 = logb(L1-D line size)
lwz r8, KDP.ProcInfo.DataCacheTotalSize(r1)
and. r8, r8, r8 ; r8 = L1-D size
beq @return
lwz r24, KDP.ProcInfo.ProcessorFlags(r1)
mtcr r24
bc BO_IF, 31 - NKProcessorInfo.hasMSSregs, @use_SPRs_to_invalidate
; => go away to handle weird CPUs
bc BO_IF_NOT, 31 - NKProcessorInfo.hasPLRUL1, @no_pseudo_lru
slwi r24, r8, 1
add r8, r8, r24
srwi r8, r8, 1 ; be generous with pseudo-LRU caches
@no_pseudo_lru
srw r8, r8, r9
mtctr r8 ; loop counter = cache/line
lwz r8, KDP.PA_ConfigInfo(r1) ; fill the cache with Mac ROM
lwz r9, NKConfigurationInfo.ROMImageBaseOffset(r8)
add r8, r8, r9
@loop_L1
lwzux r9, r8, r25
bdnz @loop_L1
; Flush level 2 (very similar to above)
lwz r24, KDP.ProcInfo.ProcessorFlags(r1)
andi. r24, r24, 1 << NKProcessorInfo.hasL2CR
beq @return ; return if L2CR unavailable
mfspr r24, l2cr
andis. r24, r24, 0x8000
beq @return ; return if L2 off (per L2CR[L2E])
lhz r25, KDP.ProcInfo.ProcessorL2DBlockSize(r1)
and. r25, r25, r25 ; r25 = L2-D line size
cntlzw r8, r25
beq @return
subfic r9, r8, 31 ; r9 = logb(L2-D line size)
lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
and. r8, r8, r8 ; r8 = L2-D size
beq @return
srw r8, r8, r9
mtctr r8 ; loop counter = cache/line
mfspr r24, l2cr ; set L2CR[DO] (disables L2-I)
oris r24, r24, 0x0040
mtspr l2cr, r24
isync
lwz r8, KDP.PA_ConfigInfo(r1) ; fill the cache with Mac ROM
lwz r9, NKConfigurationInfo.ROMImageBaseOffset(r8)
add r8, r8, r9
addis r8, r8, 0x19 ; start high in ROM and count backwards
neg r25, r25
@loop_L2
lwzux r9, r8, r25
bdnz @loop_L2
rlwinm r24, r24, 0, 10, 8
mtspr l2cr, r24 ; clear L2CR[DO] (reenables L2-I)
isync
; Done (this return path is also called from the sneaky code below)
@return
lwz r8, ContextBlock.KernelCTR(r6)
lwz r25, ContextBlock.r25(r6)
lwz r24, ContextBlock.r24(r6)
sync
mtctr r8
blr
; If "hasMSSregs" flag (my name) is set in ProcessorFlags, L1 and L2 can
; instead be flushed by clobbering reserved bits in MSSCR0 and L2CR
; respectively.
@use_SPRs_to_invalidate
; Flush level 1: set MSSCR0[8] and spin until it clears
dssall ; AltiVec needs to know
sync
mfspr r8, msscr0
oris r8, r8, 0x0080
mtspr msscr0, r8
sync
@loop_msscr0
mfspr r8, msscr0
sync
andis. r8, r8, 0x0080
bne @loop_msscr0
; Flush level 2: set L2CR[4] and spin until it clears
mfspr r8, l2cr
ori r8, r8, 0x0800
mtspr l2cr, r8
sync
@loop_l2cr
mfspr r8, l2cr
sync
andi. r8, r8, 0x0800
bne @loop_l2cr
; Jump back up to main code path to return
b @return
; Called when we cop a machine check with the "L1 data cache error"
; flag set in SRR1, followed by an interrupt return. Same trick as
; above.
; CLOB r8, cr
FlushL1CacheUsingMSSCR0
; Return if MSSCR0 unavailable
lwz r8, KDP.ProcInfo.ProcessorFlags(r1)
mtcr r8
bclr BO_IF_NOT, 31-NKProcessorInfo.hasMSSregs
; Flush level 1: set MSSCR0[8] and spin until it clears
dssall ; AltiVec needs to know
sync
mfspr r8, msscr0
oris r8, r8, 0x0080
mtspr msscr0, r8
sync
@loop_msscr0
mfspr r8, msscr0
sync
andis. r8, r8, 0x0080
bne @loop_msscr0
blr

662
NanoKernel/NKConsoleLog.s
View File

@ -1,662 +0,0 @@
; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKScreenConsole
; ScreenConsole_putchar
; ScreenConsole_redraw
; EXPORTS:
; getchar (=> NKThud, NKTimers)
; print_unknown (=> NKThud)
; printb (=> NKInit, NKMPCalls, NKTimers)
; printc (=> NKInit, NKPoolAllocator, NKThud)
; printd (=> NKInit, NKMPCalls, NKPoolAllocator, NKTimers)
; printh (=> NKBuiltinInit, NKMPCalls, NKReplacementInit, NKScheduler, NKThud, NKTimers)
; prints (=> NKMPCalls, NKThud)
; printw (=> NKAddressSpaces, NKExceptions, NKInit, NKIntHandlers, NKIntMisc, NKMPCalls, NKPaging, NKPoolAllocator, NKReplacementInit, NKScheduler, NKThud, NKTimers)
; prints
; _log null-terminated string with a few special escapes.
; Not done figuring this out, with the serial and stuff.
prints ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
lwz r1, -0x0004(r1)
lwz r28, PSA.NoIdeaR23(r1)
lwz r29, 0x0edc(r1)
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
cmpwi cr7, r28, 0x00
andi. r29, r29, 0x02
beq cr7, prints_skip_serial
crmove 30, 2
beq PrintS_skip_serial
mfmsr r31
bl serial_io
bl serial_flush
prints_skip_serial
addi r8, r8, -0x01
prints_next_char
bl serial_busywait
lbzu r29, 0x0001(r8)
cmpwi r29, 0x00
beq print_common
cmpwi r29, 10
beq PrintS_newline
cmpwi r29, 13
beq PrintS_newline
cmpwi r29, '\\'
beq PrintS_escape_code
cmpwi r29, '^'
bne PrintS_normal_char
prints_escape_code
lbzu r29, 0x0001(r8)
cmpwi r29, 'n'
beq PrintS_newline
cmpwi r29, 'r'
beq PrintS_newline
cmpwi r29, 'b'
bne PrintS_literal_backslash_or_caret
li r29, 0x07
b PrintS_normal_char
prints_literal_backslash_or_caret
lbzu r29, -0x0001(r8)
addi r8, r8, 0x01
prints_normal_char
mr r24, r29
; r1 = kdp
bl ScreenConsole_putchar
beq cr7, prints_0xe4
ori r30, r31, 0x10
mtmsr r30
isync
stb r24, 0x0006(r28)
eieio
mtmsr r31
isync
prints_0xe4
b PrintS_next_char
prints_newline
li r29, 0x0d
; r1 = kdp
bl ScreenConsole_putchar
li r29, 0x0a
; r1 = kdp
bl ScreenConsole_putchar
; r1 = kdp
bl ScreenConsole_redraw
beq cr7, prints_0x13c
ori r30, r31, 0x10
mtmsr r30
isync
li r29, 0x0d
stb r29, 0x0006(r28)
eieio
prints_0x118
lbz r29, 0x0002(r28)
eieio
andi. r29, r29, 0x04
beq PrintS_0x118
li r29, 0x0a
stb r29, 0x0006(r28)
eieio
mtmsr r31
isync
prints_0x13c
b PrintS_next_char
print_common ; OUTSIDE REFERER
beq cr7, print_common_0x8c
mtmsr r31
isync
lwz r29, PSA.DecClockRateHzCopy(r1)
srwi r29, r29, 8
mfspr r30, dec
subf r29, r29, r30
ori r30, r31, 0x10
mtmsr r30
isync
print_common_0x28
mfspr r30, dec
subf. r30, r29, r30
ble print_common_0x50
li r30, 0x01
stb r30, 0x0002(r28)
eieio
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x01
beq print_common_0x28
print_common_0x50
sync
mtmsr r31
isync
mfspr r30, pvr
rlwinm. r30, r30, 0, 0, 14
li r31, 0x00
beq print_common_0x78
mtspr dbat3u, r31
mtspr dbat3l, r31
b print_common_0x80
print_common_0x78
mtspr ibat3l, r31
mtspr ibat3u, r31
print_common_0x80
isync
mtspr srr0, r26
mtspr srr1, r27
print_common_0x8c
_AssertAndRelease PSA.DbugLock, scratch=r30
; print_return
; Restores registers from EWA and returns.
print_return ; OUTSIDE REFERER
mfsprg r1, 0
lwz r24, -0x0110(r1)
lwz r25, -0x010c(r1)
mtlr r24
mtcr r25
lmw r24, -0x0108(r1)
lwz r1, -0x0004(r1)
blr
; printd
; _log decimal
printd ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
lwz r1, -0x0004(r1)
lwz r28, PSA.NoIdeaR23(r1)
lwz r29, 0x0edc(r1)
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
cmpwi cr7, r28, 0x00
andi. r29, r29, 0x02
beq cr7, printd_0x58
crmove 30, 2
beq Printd_0x58
bl serial_io
bl serial_flush
printd_0x58
cmpwi r8, 0x00
li r25, 0x2d
blt Printd_0x9c
printd_0x64
mr. r24, r8
li r25, 0x30
beq Printd_0x9c
lis r24, 0x3b9a
ori r24, r24, 0xca00
printd_0x78
divw. r25, r8, r24
bne Printd_0x8c
li r25, 0x0a
divw r24, r24, r25
b Printd_0x78
printd_0x8c
divw r29, r8, r24
addi r25, r29, 0x30
mullw r29, r29, r24
subf r8, r29, r8
printd_0x9c
bl serial_busywait
mr r29, r25
; r1 = kdp
bl ScreenConsole_putchar
beq cr7, printd_0xc8
ori r30, r31, 0x10
mtmsr r30
isync
stb r25, 0x0006(r28)
eieio
mtmsr r31
isync
printd_0xc8
cmpwi r8, 0x00
bge Printd_0xd8
neg r8, r8
b Printd_0x64
printd_0xd8
li r25, 0x0a
divw. r24, r24, r25
bne Printd_0x8c
li r29, 0x20
; r1 = kdp
bl ScreenConsole_putchar
beq cr7, printd_0x120
ori r30, r31, 0x10
mtmsr r30
isync
printd_0xfc
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x04
beq Printd_0xfc
li r29, 0x20
stb r29, 0x0006(r28)
eieio
mtmsr r31
isync
printd_0x120
b print_common
; printw
; _log word (hex) then a space
printw ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
li r24, 0x08
crset cr6_eq
b print_digity_common
; printh
; _log halfword (hex) then a space
printh ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
li r24, 0x04
rotlwi r8, r8, 0x10
crset cr6_eq
b print_digity_common
; printb
; _log byte (hex) then a space
printb ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
li r24, 0x02
rotlwi r8, r8, 0x18
crset cr6_eq
b print_digity_common
print_unknown ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
li r24, 0x02
rotlwi r8, r8, 0x18
crclr cr6_eq
b print_digity_common
print_digity_common ; OUTSIDE REFERER
lwz r1, -0x0004(r1)
lwz r28, PSA.NoIdeaR23(r1)
lwz r29, 0x0edc(r1)
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
cmpwi cr7, r28, 0x00
andi. r29, r29, 0x02
beq cr7, print_digity_common_0x40
crmove 30, 2
beq print_digity_common_0x40
bl serial_io
bl serial_flush
print_digity_common_0x40
bl serial_busywait
li r25, 0x30
rlwimi r25, r8, 4, 28, 31
rotlwi r8, r8, 0x04
cmpwi r25, 0x39
ble print_digity_common_0x5c
addi r25, r25, 0x27
print_digity_common_0x5c
mr r29, r25
; r1 = kdp
bl ScreenConsole_putchar
beq cr7, print_digity_common_0x84
ori r30, r31, 0x10
mtmsr r30
isync
stb r25, 0x0006(r28)
eieio
mtmsr r31
isync
print_digity_common_0x84
addi r24, r24, -0x01
mr. r24, r24
bne print_digity_common_0x40
bne cr6, print_digity_common_0xd0
li r29, 0x20
; r1 = kdp
bl ScreenConsole_putchar
beq cr7, print_digity_common_0xd0
ori r30, r31, 0x10
mtmsr r30
isync
print_digity_common_0xac
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x04
beq print_digity_common_0xac
li r29, 0x20
stb r29, 0x0006(r28)
eieio
mtmsr r31
isync
print_digity_common_0xd0
b print_common
getchar ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
lwz r1, EWA.PA_KDP(r1)
lwz r28, PSA.NoIdeaR23(r1)
cmpwi cr7, r28, 0x00
li r8, -0x01
beq cr7, print_return
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
bl serial_io
ori r30, r31, 0x10
mtmsr r30
isync
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x01
beq print_common
lbz r8, 0x0006(r28)
b print_common
; printc
; _log char
printc ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
lwz r1, -0x0004(r1)
lwz r28, PSA.NoIdeaR23(r1)
lwz r29, 0x0edc(r1)
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
cmpwi cr7, r28, 0x00
andi. r29, r29, 0x02
beq cr7, printc_0x58
crmove 30, 2
beq Printc_0x58
bl serial_io
bl serial_flush
printc_0x58
mr r29, r8
; r1 = kdp
bl ScreenConsole_putchar
beq cr7, printc_0x90
ori r30, r31, 0x10
mtmsr r30
isync
printc_0x70
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x04
beq Printc_0x70
stb r8, 0x0006(r28)
eieio
mtmsr r31
isync
printc_0x90
b print_common
; serial_flush
; This and the following func are a bit speculative, but
; whatever.
; Whoa. Turns on data but not code paging. Crikey.
serial_flush ; OUTSIDE REFERER
ori r30, r31, MSR_DR
mtmsr r30
isync
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x09
stb r29, 0x0002(r28);set register pointer to 9 (next write goes to WR9)
eieio
li r29, 0x80;load code for channel A (also disables interrupts)
stb r29, 0x0002(r28);reset channel A
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x04
stb r29, 0x0002(r28);set register pointer to 4 (next write goes to WR4)
eieio
li r29, 0x48;X16 clock, 8-bit sync, 1.5 stop bits, parity off
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x03
stb r29, 0x0002(r28);set reg pointer to 3 (next write to WR3)
eieio
li r29, 0xc0;recieve 8 bits per character (but recieve off)
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x05
stb r29, 0x0002(r28);set reg pointer to 5 (next write to WR5)
eieio
li r29, 0x60;transmit 8 bits per char (but transmit off)
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x09
stb r29, 0x0002(r28);set reg pointer to 9 (next write to WR9)
eieio
li r29, 0x00
stb r29, 0x0002(r28);stop channel A reset?
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x0a
stb r29, 0x0002(r28);set reg pointer to 10 (next write to WR10)
eieio
li r29, 0x00;8-bit sync, NRZ encoding
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x0b
stb r29, 0x0002(r28);set reg pointer to 11 (next write to WR11)
eieio
li r29, 0x50;rx and tx using BR Generator
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x0c
stb r29, 0x0002(r28);set reg pointer to 12 (next write to WR12)
eieio
li r29, 0x00;0 time constant low byte
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x0d
stb r29, 0x0002(r28);set reg pointer to 13 (next write to WR13)
eieio
li r29, 0x00;0 time constant high byte
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x0e
stb r29, 0x0002(r28);set reg pointer to 14 (next write to WR14)
eieio
li r29, 0x01;enable Baud Rate generator
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x03
stb r29, 0x0002(r28);set reg pointer to 3 (next write to WR3)
eieio
li r29, 0xc1;enable reciever
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28);make sure next write goes to command register
li r29, 0x05
stb r29, 0x0002(r28);set reg pointer to 5 (next write to WR5)
eieio
li r29, 0xea;assert DTR and RTS, set 8 bit characters, and enable transmitter
stb r29, 0x0002(r28)
eieio
mtmsr r31 ;restore previous MSR
isync
blr
; serial_io
;appears to set BAT 3 so the scc can be accessed from logical memory space.
serial_io ; OUTSIDE REFERER
mfspr r26, srr0
mfspr r27, srr1
isync
mfspr r30, pvr
rlwinm. r30, r30, 0, 0, 14
rlwinm r29, r28, 0, 0, 14
beq serial_io_0x38
li r30, 0x03
or r30, r30, r29
li r31, 0x3a
or r31, r31, r29
mtspr dbat3l, r31
mtspr dbat3u, r30
b serial_io_0x50
serial_io_0x38
li r30, 0x32
or r30, r30, r29
li r31, 0x40
or r31, r31, r29
mtspr ibat3u, r30
mtspr ibat3l, r31
serial_io_0x50
isync
mfmsr r31
blr
; serial_busywait
; See disclaimer above.
serial_busywait ; OUTSIDE
beqlr cr7
ori r30, r31, 0x10
mtmsr r30
isync
serial_busywait_0x10
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x04
beq serial_busywait_0x10
mtmsr r31
isync
blr

8
NanoKernel/NKExceptions.s
View File

@ -66,7 +66,7 @@ RunExceptionHandler
bc BO_IF, bitFlagEmu, @sys
lwz r3, KDP.NCBCacheLA0(r1)
@sys
lwz r12, KDP.LA_EmulatorKernelTrapTable + NanoKernelCallTable.ReturnFromException(r1)
lwz r12, KDP.LA_EmulatorKernelTrapTable + KCallTbl.ReturnFromException(r1)
; r12/LR = address of KCallReturnFromException trap
bcl BO_IF, bitFlagLowSaves, PreferRegistersFromKDPSavingContextBlock ; ???
@ -173,7 +173,7 @@ KCallReturnFromException
; BEFORE
; PowerPC exception vector saved r1/LR in SPRG1/2 and
; jumped where directed by the vecTable pointed to by
; jumped where directed by the VecTbl pointed to by
; SPRG3. That function bl'ed here.
;
; AFTER
@ -238,7 +238,7 @@ Exception
RunSystemContext
lwz r9, KDP.PA_ECB(r1) ; System ("Emulator") ContextBlock
addi r8, r1, KDP.VecBaseSystem ; System VecTable
addi r8, r1, KDP.VecTblSystem ; System VecTbl
mtsprg 3, r8
bcl BO_IF, bitFlagEmu, SystemCrash ; System Context already running!
@ -455,7 +455,7 @@ Trace_0x30
insrwi r25, r17, 4, 24
mtcrf 0x10, r26 ; so the second nybble of the entry is copied to cr3
lha r22, 0x0c00(r25)
addi r23, r1, KDP.VecBaseMemRetry
addi r23, r1, KDP.VecTblMemRetry
add r22, r22, r25
mfsprg r24, 3
mtlr r22

311
NanoKernel/NKIndex.s
View File

@ -1,311 +0,0 @@
;_______________________________________________________________________
; NanoKernel Opaque ID Index
;
; Creates opaque structure IDs and stores them in the Pool. An opaque
; ID maps back to the (type, pointer) pair passed to MakeID.
;
; This abstraction is very important to the Multiprocessing Services.
;
; Rene on comp.sys.mac.programmer.help, 26 Oct 01:
;
; Total opaque IDs - The number of IDs currently in use. All MP
; objects: address spaces, areas, processors, memory coherence groups,
; queues, semaphores, critical regions, event groups, timers,
; notifications, etc. are assigned an ID when created, and they are
; accessed by way of this ID. The kernel presently handles 65,000
; simultaneous IDs with a bit pattern reuse probability of 1 in 4
; billion.
;
; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKPoolAllocator
; PoolAllocClear
; NKThud
; panic
; EXPORTS:
; DeleteID (=> NKAddressSpaces, NKMPCalls, NKSync, NKTasks, NKTimers)
; GetNextIDOfClass (=> NKAddressSpaces, NKMPCalls, NKThud)
; InitIDIndex (=> NKInit)
; LookupID (=> NKAddressSpaces, NKExceptions, NKIntMisc, NKMPCalls, NKPrimaryIntHandlers, NKSync, NKTasks, NKThud, NKTimers)
; MakeID (=> NKAddressSpaces, NKInit, NKMPCalls, NKSync, NKTasks)
;_______________________________________________________________________
Local_Panic set *
b panic
; ARG KDP *r1
InitIDIndex
mflr r23
li r8, Index.Size
bl PoolAllocClear
mr. r22, r8
stw r8, PSA.IndexPtr(r1)
beq Local_Panic
li r9, 0
stw r9, KDP.NKInfo.IDCtr(r1)
sth r9, Index.HalfOne(r22)
sth r9, Index.HalfTwo(r22)
lisori r9, Index.kSignature
stw r9, Index.Signature(r22)
; Then what the hell is this?
li r8, 0xfd8
bl PoolAllocClear
cmpwi r8, 0
stw r8, Index.IDsPtr(r22)
beq Local_Panic
mtlr r23
li r9, 0x00
sth r9, 0x0000(r8)
li r9, 0x1fa
sth r9, 0x0002(r8)
lisori r9, 'IDs '
stw r9, 0x0004(r8)
blr
; ARG void *r8, IDClass r9
; RET ID r8
MakeID
lwz r18, PSA.IndexPtr(r1)
lhz r19, 0x0000(r18)
mr r21, r19
@_c
lwz r18, PSA.IndexPtr(r1)
rlwinm r20, r19, 25, 23, 29
addi r20, r20, 0x08
clrlwi. r19, r19, 0x17
lwzx r18, r18, r20
slwi r22, r19, 3
addi r20, r18, 0x08
cmpwi r18, 0x00
add r22, r22, r20
bne @_48
li r19, 0x00
b @_c
@_3c
add r20, r20, r19
cmpw r20, r21
beq @_70
@_48
lbz r23, 0x0000(r22)
cmpwi r23, 0x00
beq @_f0
addi r19, r19, 0x01
cmpwi cr1, r19, 0x1fa
addi r22, r22, 0x08
lhz r20, 0x0000(r18)
blt cr1, @_3c
addi r19, r20, 0x200
b @_c
@_70
lwz r18, PSA.IndexPtr(r1)
mr r21, r8
lhz r19, 0x0002(r18)
mr r22, r9
addi r19, r19, 0x200
rlwinm. r20, r19, 25, 23, 29
li r8, 0x00
beqlr
mflr r23
li r8, 0xfd8
; r1 = kdp
; r8 = size
bl PoolAllocClear
; r8 = ptr
mr. r18, r8
mtlr r23
li r8, 0x00
beqlr
lwz r17, PSA.IndexPtr(r1)
lhz r19, 0x0002(r17)
addi r19, r19, 0x200
rlwinm r20, r19, 25, 23, 29
addi r20, r20, 0x08
sth r19, 0x0002(r17)
stwx r18, r20, r17
sth r19, 0x0000(r18)
li r9, 0x1fa
sth r9, 0x0002(r18)
lis r9, 0x4944
ori r9, r9, 0x7320
stw r9, 0x0004(r18)
li r19, 0x00
mr r8, r21
mr r9, r22
addi r22, r18, 0x08
@_f0
stw r8, 0x0004(r22)
stb r9, 0x0000(r22)
lwz r9, KDP.NKInfo.IDCtr(r1)
addi r9, r9, 0x01
stw r9, KDP.NKInfo.IDCtr(r1)
lhz r20, 0x0000(r18)
lhz r8, 0x0002(r22)
lwz r21, PSA.IndexPtr(r1)
add r19, r19, r20
addi r8, r8, 0x01
lhz r20, 0x0002(r18)
sth r8, 0x0002(r22)
addi r20, r20, -0x01
rlwimi. r8, r19, 16, 0, 15
sth r20, 0x0002(r18)
sth r19, 0x0000(r21)
bnelr+
lhz r8, 0x0002(r22)
addi r8, r8, 0x01
sth r8, 0x0002(r22)
rlwimi r8, r19, 16, 0, 15
blr
; ARG ID r8
align 5
DeleteID
rlwinm r20, r8, 9, 23, 29
lwz r18, PSA.IndexPtr(r1)
addi r20, r20, 0x08
rlwinm. r19, r8, 16, 23, 31
lwzx r18, r18, r20
cmplwi cr1, r19, 0x1fa
cmpwi r18, 0x00
addi r20, r18, 0x08
slwi r22, r19, 3
add r22, r22, r20
clrlwi r20, r8, 0x10
li r8, 0x00
bgelr cr1
beqlr
lbz r19, 0x0000(r22)
lhz r23, 0x0002(r22)
cmpwi r19, 0x00
cmpw cr1, r23, r20
beqlr
bnelr cr1
lwz r9, KDP.NKInfo.IDCtr(r1)
addi r9, r9, -0x01
stw r9, KDP.NKInfo.IDCtr(r1)
lhz r20, 0x0002(r18)
stb r8, 0x0000(r22)
addi r20, r20, 0x01
li r8, 0x01
sth r20, 0x0002(r18)
blr
; ARG ID r8
; RET Ptr r8, IDClass r9
align 5
LookupID
rlwinm r20, r8, 9, 23, 29
lwz r18, PSA.IndexPtr(r1)
addi r20, r20, 0x08
rlwinm. r19, r8, 16, 23, 31
lwzx r18, r18, r20
cmplwi cr1, r19, 0x1fa
cmpwi r18, 0x00
addi r20, r18, 0x08
slwi r22, r19, 3
add r22, r22, r20
clrlwi r20, r8, 0x10
li r8, 0x00
li r9, 0x00
bgelr cr1
beqlr
lbz r19, 0x0000(r22)
lhz r23, 0x0002(r22)
cmpwi r19, 0x00
cmpw cr1, r23, r20
beqlr
bnelr cr1
lwz r8, 0x0004(r22)
mr r9, r19
blr
; ARG ID r8, IDClass r9
; RET ID r8
align 5
GetNextIDOfClass
rlwinm r20, r8, 9, 23, 29
lwz r18, PSA.IndexPtr(r1)
addi r20, r20, 0x08
rlwinm. r19, r8, 16, 23, 31
lwzx r18, r18, r20
cmplwi cr1, r19, 0x1fa
cmpwi r18, 0x00
cmpwi cr2, r8, 0x00
addi r20, r18, 0x08
slwi r22, r19, 3
li r8, 0x00
bgelr cr1
beqlr
add r22, r22, r20
bne cr2, @_48
@_3c
lbz r23, 0x0000(r22)
cmpwi r23, 0x00
bne @_8c
@_48
addi r19, r19, 0x01
cmpwi r19, 0x1fa
addi r22, r22, 0x08
blt @_3c
lhz r20, 0x0000(r18)
addi r20, r20, 0x200
rlwinm. r20, r20, 25, 23, 29
lwz r18, PSA.IndexPtr(r1)
beqlr
addi r20, r20, 0x08
li r19, 0x00
lwzx r18, r18, r20
cmpwi r18, 0x00
addi r22, r18, 0x08
bne @_3c
li r8, 0x00
blr
@_8c
cmpwi r9, 0x00
cmpw cr1, r9, r23
beq @_9c
bne cr1, @_48
@_9c
lhz r20, 0x0000(r18)
lhz r8, 0x0002(r22)
add r19, r19, r20
rlwimi r8, r19, 16, 0, 15
blr

5
NanoKernel/NKInit.s
View File

@ -9,7 +9,6 @@ rED set r8 ; Emulator Data Page
########################################################################
b *+0x1234
li r0, 0 ; Zero lots of fields
########################################################################
@ -100,7 +99,7 @@ InitKernelMemory
lis r11, 0x7fff
bne @did_not_panic
subf r11, r13, r1
addi r11, r11, KDP.StartOfPanicArea
addi r11, r11, KDP.CrashTop
@did_not_panic
subf r12, r14, r15 ; Erase all of kernel globals, except crash data
@ -108,7 +107,7 @@ InitKernelMemory
@eraseloop
subic. r12, r12, 4
subf r10, r11, r12
cmplwi cr7, r10, KDP.EndOfPanicArea - KDP.StartOfPanicArea - 4
cmplwi cr7, r10, KDP.CrashBtm - KDP.CrashTop - 4
ble cr7, @skipwrite
stwx r0, r13, r12
@skipwrite

2
NanoKernel/NKIntHandlers.s
View File

@ -402,7 +402,7 @@ IntISI
mfsprg r24, 3
mfmsr r14
_bset r15, r14, bitMsrDR
addi r23, r1, KDP.VecBaseMemRetry
addi r23, r1, KDP.VecTblMemRetry
mtsprg 3, r23
mr r19, r10
mtmsr r15

2179
NanoKernel/NKMPCalls.s
View File

File diff suppressed because it is too large Load Diff

695
NanoKernel/NKPoolAllocator.s
View File

@ -1,695 +0,0 @@
; SEGMENTS
;
; The pool is made up of segments of contiguous memory. The first segment
; to be created is about 25k, running from 0x7000 below r1 to the start of
; the Primary System Area. It is initialised by InitPool. Every subsequent
; segment occupies a single page, plucked from the system free list by
; ExtendPool.
;
;
; BLOCKS
;
; Each segment is an array of variously sized blocks, with no gaps between
; them. The first block is a Begin (‡BGN) block, the last block is an End
; block (‡END), and all others are Allocated (‡loc) or Free (free) blocks.
; To allow the data in each Allocated block to be 16b-aligned, all
; Allocated and Free blocks start 8b below a 16b boundary.
;
;
; SINGLY LINKED LIST OF SEGMENTS
;
; PSA.FirstPoolSeg points to the start of the most recently added pool
; segment, i.e. to its Begin block. The OffsetToNext field of a Begin
; block points not to the block immediately beyond it in memory, but to
; the segment's End block. The OffsetToNext field of the End block points
; to the start of the next most recently added pool segment. If there is
; none, it contains zero.
;
;
; DOUBLY LINKED LIST OF FREE BLOCKS
;
; Every free block is a member of PSA.FreePool, a doubly linked list of
; free segments. The "LLL" structure occupies the first 16 bytes of the
; block.
; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKConsoleLog
; printc
; printd
; printw
; NKThud
; panic
; EXPORTS:
; ExtendPool (=> NKMPCalls)
; InitPool (=> NKInit)
; PoolAlloc (=> NKExceptions, NKSync, NKTasks)
; PoolAllocClear (=> NKAddressSpaces, NKIndex, NKInit, NKMPCalls, NKSync, NKTasks, NKTimers)
; PoolFree (=> NKAddressSpaces, NKMPCalls, NKSync, NKTasks, NKTimers)
Block record
kBeginSize equ 8
kEndSize equ 24
kPoolSig equ 'POOL'
kBeginSig equ '‡BGN'
kEndSig equ '‡END'
kAllocSig equ '‡loc'
kFreeSig equ 'free'
; For free and allocated blocks, points to the next block
; For begin blocks, points to corresponding end block
; For end blocks, points to another begin block (or zero)
OffsetToNext ds.l 1 ; 0
Signature ds.l 1 ; 4
Data
LogiNextSeg
FreeNext ds.l 1 ; 8
FreePrev ds.l 1 ; c
endr
_PoolPanic
b panic
; Use all the memory from r1 - 0x7000 to PSA
InitPool
; Add first segment to global singly linked list
lwz r8, KDP.PA_ConfigInfo(r1)
lwz r8, NKConfigurationInfo.LA_KernelData(r8)
lisori r9, -kPoolOffsetFromGlobals
subf r9, r9, r8
stw r9, PSA.FirstPoolSegLogical(r1)
lisori r9, kPoolOffsetFromGlobals
add r9, r9, r1
stw r9, PSA.FirstPoolSeg(r1)
; Decide how big the segment will be
_pool_first_seg equ PSA.Base - kPoolOffsetFromGlobals
; Begin block (leave ptr to End in r23)
lisori r8, _pool_first_seg - Block.kEndSize
add r23, r8, r9
stw r8, Block.OffsetToNext(r9)
lisori r8, Block.kBeginSig
stw r8, Block.Signature(r9)
; Free block (leave ptr in r9)
addi r9, r9, Block.kBeginSize
lisori r8, _pool_first_seg - Block.kEndSize - Block.kBeginSize
stw r8, Block.OffsetToNext(r9)
lisori r8, Block.kFreeSig
stw r8, Block.Signature(r9)
; End block
li r8, 0
stw r8, Block.OffsetToNext(r23)
lisori r8, Block.kEndSig
stw r8, Block.Signature(r23)
; Add Free block to global doubly linked list
addi r8, r1, PSA.FreePool
stw r9, Block.FreeNext(r8)
stw r9, Block.FreePrev(r8)
stw r8, Block.FreeNext(r9)
stw r8, Block.FreePrev(r9)
lisori r9, Block.kPoolSig
stw r9, Block.Signature(r8)
; Return
blr
; The NanoKernel's malloc
; ARG size r8
; RET ptr r8
_poolalloc_noclr_cr_bit equ 30
PoolAllocClear
crclr _poolalloc_noclr_cr_bit
b _PoolAllocCommon
PoolAlloc
crset _poolalloc_noclr_cr_bit
_PoolAllocCommon
; Save LR and arg to EWA. Get lock.
mflr r17
mfsprg r18, 0
_Lock PSA.PoolLock, scratch1=r15, scratch2=r16
; These saves are my first real hint at the contents of that
; large unexplored area of the EWA. This file, then, owns
; part of the EWA, for its CPU-scoped globals. Because the
; kernel runs stackless.
stw r17, EWA.PoolSavedLR(r18)
stw r8, EWA.PoolSavedSizeArg(r18)
@recheck_for_new_block
; Sanity checks
cmpwi r8, 0
cmpwi cr1, r8, 0xfd8
ble _PoolPanic
bgt cr1, @request_too_large
; Up-align to 32b boundary and snatch an extra 8b
; This is our minimum OffsetToNext field
addi r8, r8, 8 + 31
rlwinm r8, r8, 0, 0xffffffe0
; Iterate the free-block list
addi r14, r1, PSA.FreePool
lwz r15, LLL.Next(r14)
@next_block
cmpw r14, r15
bne+ @try_block
; Global free-block list is empty (not great news)
; Got a free page in the system free list? It's ours.
li r8, 0 ; return zero if there is no page at all
li r9, 1 ; number of pages to grab
lwz r16, PSA.FreePageCount(r1)
lwz r17, PSA.UnheldFreePageCount(r1)
subf. r16, r9, r16
subf r17, r9, r17
blt _PoolReturn
stw r16, PSA.FreePageCount(r1)
stw r17, PSA.UnheldFreePageCount(r1)
; Get that page, mofo. Macros FTW.
lwz r8, PSA.FreeList + LLL.Next(r1)
RemoveFromList r8, scratch1=r17, scratch2=r18
; There was probably once a mechanism for virtual addressing of the pool!
li r9, 0
bl ExtendPool ; r8=page, r9=virt=0
; Now that the pool is not empty, start over.
mfsprg r18, 0
lwz r8, EWA.PoolSavedSizeArg(r18)
b @recheck_for_new_block
; Request was greater than the maximum block size
@request_too_large
li r8, 0
b _PoolReturn
; Try the free block that r15 points to
@try_block
@retry_newly_expanded_block
lwz r16, Block.OffsetToNext(r15)
cmplw r16, r8
lis r20, 'fr'
bgt @decide_whether_to_split
beq @do_not_split
ori r20, r20, 'ee'
; This block is too small to fit our allocation, but can it be mashed together
; with a physically adjacent free block? This might happen a few times before
; we decide to give up and search for another block.
lwz r16, Block.OffsetToNext(r15)
add r18, r16, r15
lwz r19, Block.Signature(r18)
cmplw cr1, r18, r15
cmpw r19, r20
ble cr1, _PoolPanic
bne @physically_adjacent_block_is_not_free
lwz r17, Block.OffsetToNext(r18)
rotlwi r19, r19, 8
add r17, r17, r16
stw r17, Block.OffsetToNext(r15)
stw r19, Block.Signature(r18) ; scramble old signature to clarify mem dumps
lwz r17, Block.FreePrev(r18)
lwz r16, Block.FreeNext(r18)
stw r16, Block.FreeNext(r17)
stw r17, Block.FreePrev(r16)
b @retry_newly_expanded_block
@physically_adjacent_block_is_not_free
lwz r15, Block.FreeNext(r15)
b @next_block
; Success: split the block if there is >=40b left over
@decide_whether_to_split
subf r16, r8, r16
cmpwi r16, 40
blt @do_not_split
; Use the rightmost part of the block, leaving ptr in r15
; (Leaving the leftmost part saves us touching the free block list)
stw r16, Block.OffsetToNext(r15)
add r15, r15, r16
stw r8, Block.OffsetToNext(r15)
b @proceed_with_block
; Success: use the entire block, leaving ptr in r15
@do_not_split
lwz r14, 0x000c(r15)
lwz r16, LLL.Next(r15)
stw r16, LLL.Next(r14)
stw r14, 0x000c(r16)
; Sign the block and return data ptr in r8
@proceed_with_block
lisori r8, Block.kAllocSig
stw r8, Block.Signature(r15)
addi r8, r15, Block.Data
; Optionally clear the block (quicker if we don't)
bc BO_IF, _poolalloc_noclr_cr_bit, _PoolReturn
lwz r16, Block.OffsetToNext(r15)
subi r16, r16, Block.Data
li r14, 0
add r16, r16, r15
addi r15, r15, 4
@clrloop
stwu r14, 4(r15)
cmpw r15, r16
ble @clrloop
b _PoolReturn
; The NanoKernel's free
; ARG r8 = ptr to contents of pool block
PoolFree
mflr r17
mfsprg r18, 0
_Lock PSA.PoolLock, scratch1=r15, scratch2=r16
stw r17, EWA.PoolSavedLR(r18)
bl _PoolAddBlockToFreeList
bl _PoolMergeAdjacentFreeBlocks
; Fall through...
; PoolAlloc and PoolFree save LR on entry, then return this way
_PoolReturn
mfsprg r18, 0
_AssertAndRelease PSA.PoolLock, scratch=r15
lwz r17, EWA.PoolSavedLR(r18)
mtlr r17
blr
; Re-label an Allocated block as Free, and add it to the global list
; Panics if block is not Allocated to start with!
; ARG r8 = ptr to contents of pool block
; RET r15 = ptr to pool block itself (r8 - 8)
_PoolAddBlockToFreeList
; Get the block containing the data
subi r15, r8, Block.Data
; Change the signature
_lstart r20, Block.kFreeSig
lhz r16, Block.Signature(r15)
_lfinish
cmplwi r16, 0x876c ; Block.kAllocSig >> 16
bne _PoolPanic
stw r20, Block.Signature(r15)
; Insert into the global free block list
addi r16, r1, PSA.FreePool
InsertAsPrev r15, r16, scratch=r17
blr
; Merge a free block with any free blocks to the right
; (Cannot look to the left because list is singly linked)
; ARG r15 = ptr to free block
_PoolMergeAdjacentFreeBlocks
@next_segment
_lstart r20, Block.kFreeSig
lwz r16, Block.OffsetToNext(r15)
_lfinish
add r18, r16, r15 ; r18 = block to the right
lwz r19, Block.Signature(r18) ; r19 = signature of that block
cmplw cr1, r18, r15
cmpw r19, r20
ble cr1, _PoolPanic ; die if block was of non-positive size!
bnelr ; return if block to right is not free
lwz r17, Block.OffsetToNext(r18)
rotlwi r19, r19, 8 ; scramble old signature to clarify mem dumps
add r17, r17, r16
stw r17, Block.OffsetToNext(r15) ; increase the size of the main block
stw r19, Block.Signature(r18)
lwz r17, Block.FreePrev(r18) ; remove the absorbed block from the list of free blocks
lwz r16, Block.FreeNext(r18)
stw r16, Block.FreeNext(r17)
stw r17, Block.FreePrev(r16)
b @next_segment
; Create a new pool segment from a physical page
; ARG PhysPtr r8, LogiPtr r9
ExtendPool
mflr r14
; This segment will occupy a page
_pool_page_seg equ 0x1000
rlwinm r17, r8, 0, -(_pool_page_seg)
; Counter can be viewed from Apple System Profiler
lwz r16, KDP.NKInfo.FreePoolExtendCount(r1)
addi r16, r16, 1
stw r16, KDP.NKInfo.FreePoolExtendCount(r1)
; Bit of palaver
_log 'Extend free pool: phys 0x'
mr r8, r17
bl Printw
_log ' virt 0x'
mr r8, r9
bl Printw
_log ' count: '
mr r8, r16
bl Printd
_log '^n'
; Clear the page
li r16, _pool_page_seg
@zeroloop
subi r16, r16, 32
cmpwi r16, 0
dcbz r16, r17
bgt @zeroloop
; Begin block
li r16, _pool_page_seg - Block.kEndSize
stw r16, Block.OffsetToNext(r17)
lisori r16, Block.kBeginSig
stw r16, Block.Signature(r17)
; Alloc block (_PoolAddBlockToFreeList will convert to Free)
addi r15, r17, Block.kBeginSize
li r16, _pool_page_seg - Block.kEndSize - Block.kBeginSize
stw r16, Block.OffsetToNext(r15)
lisori r16, Block.kAllocSig
stw r16, Block.Signature(r15)
; End block
addi r15, r17, _pool_page_seg - Block.kEndSize
lwz r18, PSA.FirstPoolSeg(r1)
subf r18, r15, r18
stw r18, Block.OffsetToNext(r15) ; point to next-most-recently-added segment
lisori r16, Block.kEndSig
stw r16, Block.Signature(r15)
lwz r16, PSA.FirstPoolSegLogical(r1) ; vestigial?
stw r16, Block.LogiNextSeg(r15)
; Add new segment to global singly linked list
stw r9, PSA.FirstPoolSegLogical(r1)
stw r17, PSA.FirstPoolSeg(r1)
; Free the Alloc block and add it to the global doubly linked list
addi r8, r17, Block.kBeginSize + Block.Data
bl _PoolAddBlockToFreeList
; This won't do anything, because there is no other free block in the segment
bl _PoolMergeAdjacentFreeBlocks
; Return
mtlr r14
blr
; Check the pool for corruption (dead code)
PoolCheck
mflr r19
lwz r20, PSA.FirstPoolSeg(r1)
; Check this segment, starting with first Allocated block
@next_segment
addi r8, r20, Block.kBeginSize
bl _PoolCheckBlocks
; Get End block
lwz r17, Block.OffsetToNext(r20)
add r17, r17, r20
; Use that to get another Begin block
lwz r18, Block.OffsetToNext(r17)
cmpwi r18, 0
add r20, r18, r17
bne @next_segment
; If there are no more Begins, we are done
mtlr r19
blr
; Only called by the above function
; Called on data ptrs? Or on block ptrs?
; ARG ptr r8
_PoolCheckBlocks
mflr r14
subi r16, r8, 8 ; Block.kBeginSize or Block.Data?
@loop
lwz r17, Block.Signature(r16)
lisori r18, Block.kEndSig
cmpw r17, r18
li r9, 0
beq @return
lisori r18, Block.kAllocSig
cmpw r17, r18
beq @block_is_allocated
lisori r18, Block.kFreeSig
li r9, 4
cmpw r17, r18
bne @block_corrupt
; From now we assume Free
lwz r17, Block.FreePrev(r16)
cmpwi r17, 0
li r9, 5
beq @block_corrupt
lwz r17, Block.FreeNext(r16)
cmpwi r17, 0
li r9, 6
beq @block_corrupt
@block_is_allocated
;or block is free (fallthru)
lwz r17, Block.OffsetToNext(r16)
add r16, r16, r17
cmpwi r17, 0
li r9, 7
bgt @loop
; 4: neither Allocated nor Free
; 5: Free with bad FreePrev ptr
; 6: Free with bad FreeNext ptr
; 7: bad OffsetToNext ptr
@block_corrupt
mr r18, r8
_log 'Heap segment corrupt '
mr r8, r9
bl Printd
_log 'at '
mr r8, r16
bl Printw
_log '^n'
; Dump some memory
subi r16, r16, 64
li r17, 8 ; 8 lines, 16 bytes each
@dump_next_line
mr r8, r16
bl Printw
_log ' '
lwz r8, 0(r16)
bl Printw
lwz r8, 4(r16)
bl Printw
lwz r8, 8(r16)
bl Printw
lwz r8, 12(r16)
bl Printw
_log ' *'
li r8, 16
subi r16, r16, 1
mtctr r8
@dump_next_char
lbzu r8, 1(r16)
cmpwi r8, ' '
bgt @dont_use_space
li r8, ' '
@dont_use_space
bl Printc
bdnz @dump_next_char
_log '*^n'
subi r17, r17, 1
addi r16, r16, 1
cmpwi r17, 0x00
bne @dump_next_line
mr r8, r18
@return
mtlr r14
blr

742
NanoKernel/NKPowerCalls.s
View File

@ -1,742 +0,0 @@
; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKCache
; FlushCaches
; NKExceptions
; IntReturn
; NKIntMisc
; wordfill
; NKThud
; panic
; EXPORTS:
; InitIdleVecTable (=> NKInit)
; kcPowerDispatch (=> NKInit)
#### ## ## #### ######## ## ## ######## ###### ######## ######## ##
## ### ## ## ## ## ## ## ## ## ## ## ## ##
## #### ## ## ## ## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ## ###### ## ## ######## ##
## ## #### ## ## ## ## ## ## ## ## ## ##
## ## ### ## ## ## ## ## ## ## ## ## ## ##
#### ## ## #### ## ### ######## ###### ## ######## ########
; When we are asked via a PowerDispatch call to put a CPU into a non-full-
; on pwrmgt state, we will point its SPRG3 to this table. Any of these
; three interrupts will return the CPU to full-on mode, and we will return
; from the PowerDispatch call. Called at NK init time.
_alignToCacheBlock
InitIdleVecTable
mflr r9
llabel r23, panic
add r23, r23, r25
addi r8, r1, PSA.VecBaseIdle
li r22, VecTable.Size
bl wordfill
mtlr r9
llabel r23, IntReturnToFullOn
add r23, r23, r25
stw r23, VecTable.SystemResetVector(r8)
stw r23, VecTable.ExternalIntVector(r8)
stw r23, VecTable.DecrementerVector(r8)
blr
######## #### ###### ######## ### ######## ###### ## ##
## ## ## ## ## ## ## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ## ## ## ## ##
## ## ## ###### ######## ## ## ## ## #########
## ## ## ## ## ######### ## ## ## ##
## ## ## ## ## ## ## ## ## ## ## ## ##
######## #### ###### ## ## ## ## ###### ## ##
; Called using 68k `$FE0F` or PPC `twi ... 5`
; ARG selector r3 (0-11), ...
_alignToCacheBlock
kcPowerDispatch
mtcr r7
lwz r4, KDP.TestIntMaskInit(r1)
cmplwi cr7, r3, 11
mr r9, r13
bc BO_IF, 8, @use_provided_mcr
lwz r9, PSA.MCR(r1)
@use_provided_mcr
and. r8, r4, r9
bgt cr7, PowerEarlyReturnError ; invalid selector
bne PowerEarlyReturnSuccess
cmplwi cr7, r3, 11
beq cr7, PwrInfiniteLoop
cmplwi cr7, r3, 8
beq cr7, PwrSuspendSystem
cmplwi cr7, r3, 9
beq cr7, PwrSetICTC
; Fall through to 0-7: PwrIdle
##### ######## #### ######## ## ########
## ## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ##
## ## ####### ## ## ## ## ## ######
## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ##
##### ## #### ######## ######## ########
; Selector 0-7
; Set the CPU static pwrmgt state to doze, idle or sleep, then return to
; full-on when we get an interrupt.
; ARG r3 & 1: which of the two pre-programmed pwrmgt states to invoke (see NKProcFlagsTbl.s)
; r3 & 4: whether to flush L1 and L2 caches
; Different 603+ chips have static power management states named "doze",
; "nap" and "sleep". A state is selected by setting the corresponding bit
; in HID0. The state is then invoked by setting MSR[POW]. The state is
; ended by a decrementer interrupt (doze/nap only) or external interrupt.
; This is a short term CPU-specific state, *not* system-wide "sleep".
; Because the NK timer code sets the decrementer, we can be sure that we
; will not miss a timer firing.
PwrIdle
; Get us some breathing room
_RegRangeToContextBlock r26, r31
; Activate the interrupt table that will rouse the CPU
mfsprg r31, 3 ; will restore r31 => SPRG3 after state exited
addi r8, r1, PSA.VecBaseIdle
mtsprg 3, r8
; Save argument & 4 (run-cache-code flag)
rlwinm r26, r3, 0, 29, 29
; Choose from the NK's two pre-programmed pwrmgt states for this CPU.
; Fail if we find zero (e.g. on the 601).
; arg pwrmgt state selector => r3
; r3 & 1 0=fail 1=DOZE 2=NAP 3=SLEEP
; ------ ---------------------------
; 0 (CpuSpecificByte1 >> 6) & 3
; 1 (CpuSpecificByte1 >> 4) & 3
clrlwi r3, r3, 30
lbz r8, KDP.CpuSpecificByte1(r1)
slwi r3, r3, 1
addi r3, r3, 26
rlwnm r3, r8, r3, 30, 31
cmpwi r3, 0
beq PowerEarlyRestoreReturnError
; Depending on pre-programmed flags, set:
; HID0[NHR] ("not hard reset" flag)
; HID0[ptrmgt state selected above]
lbz r9, KDP.CpuSpecificByte2(r1)
cmpwi r9, 0
beq @set_neither
mfspr r27, hid0 ; will restore r27 => HID0 when system wakes below
mr r8, r27
cmpwi r9, 1
beq @set_only_nhr
oris r9, r3, 0x0100 ; set bit 7
srw r9, r9, r9 ; shift right by 0-3
rlwimi r8, r9, 0, 8, 10 ; keep bits 8/9/10
@set_only_nhr
oris r8, r8, 1 ; also set NHR
mtspr hid0, r8
@set_neither
; Flush L1 and L2 caches if argument & 4
cmplwi r26, 4
beql FlushCaches
; Set MSR bits to enter the selected pwrmgt state
mfmsr r8
ori r8, r8, 0x8002 ; Always set MSR[EE] and MSR[RI] so we can wake!
cmplwi r3, 0 ; If using HID0[pwrmgt state], set MSR[POW] so it takes effect
beq @no_pow
oris r8, r8, 4
@no_pow
sync ; Apply MSR!
mtmsr r8
isync
; Loop while the state takes effect, then jump 4 bytes forward when we cop an interrupt
b *
IntReturnToFullOn
; Restore HID0 from r27, assuming that we mangled it
lbz r8, KDP.CpuSpecificByte2(r1)
cmpwi r8, 0
beq @hid_was_not_changed
mtspr hid0, r27
@hid_was_not_changed
; Restore registers and return successfully to caller.
; Not sure about the decrementer stuff.
mfsprg r1, 2
mtlr r1
mfsprg r1, 1
lis r9, 0x7fff
mfspr r8, dec
mtspr dec, r9
mtspr dec, r8
li r3, 0
PowerCallRestoreReturn
mtsprg 3, r31 ; saved SPRG3 above
_RegRangeFromContextBlock r26, r31
b IntReturn
; Return islands for other calls
PowerEarlyRestoreReturnError
li r3, -0x7267
b PowerCallRestoreReturn
PowerEarlyReturnSuccess
li r3, 0
b IntReturn
PowerEarlyReturnError
li r3, -1
b IntReturn
####### ###### ## ## ###### ######## ######## ## ## ########
## ## ## ## ## ## ## ## ## ## ## ### ## ## ##
## ## ## ## ## ## ## ## ## #### ## ## ##
####### ###### ## ## ###### ######## ###### ## ## ## ## ##
## ## ## ## ## ## ## ## ## #### ## ##
## ## ## ## ## ## ## ## ## ## ## ### ## ##
####### ###### ####### ###### ## ######## ## ## ########
; Selector 8
; Put this, the last scheduled CPU, into SLEEP mode.
; Save state. Call ActuallySuspend. Restore state. Return.
PwrSuspendSystem
; Cannot sleep if multiple CPUs are scheduled
mfsprg r9, 0
lwz r8, EWA.CPUBase + CPU.LLL + LLL.Freeform(r9)
lwz r9, CoherenceGroup.ScheduledCpuCount(r8)
cmpwi r9, 1
li r3, -0x7267
bgt IntReturn
; Some breathing room
_RegRangeToContextBlock r26, r31
bl FlushCaches
; Disable both L1 caches (via HID0)
mfspr r9, hid0
rlwinm r9, r9, 0, 18, 16 ; unset HID0[DCE] (data cache enable)
rlwinm r9, r9, 0, 17, 15 ; unset HID0[ICE] (inst cache enable)
mtspr hid0, r9
sync
isync
; Disable L2 cache (via L2CR, if present)
lwz r26, KDP.ProcInfo.ProcessorFlags(r1)
andi. r26, r26, 1 << NKProcessorInfo.hasL2CR
beq @no_need_to_deactivate_l2
mfspr r9, l2cr
clrlwi r9, r9, 1 ; unset L2CR[L2E]
mtspr l2cr, r9
sync
isync
addi r8, r1, PSA.ProcessorState
stw r9, NKProcessorState.saveL2CR(r8)
@no_need_to_deactivate_l2
; Save some GPRs
stw r7, ContextBlock.Flags(r6)
_RegRangeToContextBlock r2, r5
_RegRangeToContextBlock r14, r25
stw r13, ContextBlock.CR(r6)
; Save floats
andi. r8, r11, 0x2000 ; MSR[FP]
beq @no_save_float
mfmsr r8
ori r8, r8, 0x2000 ; ensure that MSR bit is set?
mtmsr r8
isync
_FloatRangeToContextBlock f0, f16
mffs f0
_FloatRangeToContextBlock f17, f31
stfd f0, ContextBlock.PageInSystemHeap(r6) ; ???
@no_save_float
; Save misc SPRs
mfxer r9
addi r16, r1, PSA.ProcessorState
stw r9, ContextBlock.XER(r6)
mfctr r9
stw r9, ContextBlock.CTR(r6)
stw r12, ContextBlock.FE000000(r6)
stw r10, NKProcessorState.saveSRR0(r16)
stw r11, NKProcessorState.saveSRR1(r16)
mfspr r9, hid0
stw r9, NKProcessorState.saveHID0(r16)
; Save timebase
@tb_retry
mftbu r9
stw r9, NKProcessorState.saveTBU(r16)
mftb r9
stw r9, NKProcessorState.saveTBL(r16)
mftbu r8
lwz r9, NKProcessorState.saveTBU(r16)
cmpw r8, r9
bne @tb_retry
; Save MSR
mfmsr r9
stw r9, NKProcessorState.saveMSR(r16)
; Save SDR1
mfspr r9, sdr1
stw r9, NKProcessorState.saveSDR1(r16)
; Save BAT registers
mfspr r9, dbat0u
stw r9, NKProcessorState.saveDBAT0u(r16)
mfspr r9, dbat0l
stw r9, NKProcessorState.saveDBAT0l(r16)
mfspr r9, dbat1u
stw r9, NKProcessorState.saveDBAT1u(r16)
mfspr r9, dbat1l
stw r9, NKProcessorState.saveDBAT1l(r16)
mfspr r9, dbat2u
stw r9, NKProcessorState.saveDBAT2u(r16)
mfspr r9, dbat2l
stw r9, NKProcessorState.saveDBAT2l(r16)
mfspr r9, dbat3u
stw r9, NKProcessorState.saveDBAT3u(r16)
mfspr r9, dbat3l
stw r9, NKProcessorState.saveDBAT3l(r16)
mfspr r9, ibat0u
stw r9, NKProcessorState.saveIBAT0u(r16)
mfspr r9, ibat0l
stw r9, NKProcessorState.saveIBAT0l(r16)
mfspr r9, ibat1u
stw r9, NKProcessorState.saveIBAT1u(r16)
mfspr r9, ibat1l
stw r9, NKProcessorState.saveIBAT1l(r16)
mfspr r9, ibat2u
stw r9, NKProcessorState.saveIBAT2u(r16)
mfspr r9, ibat2l
stw r9, NKProcessorState.saveIBAT2l(r16)
mfspr r9, ibat3u
stw r9, NKProcessorState.saveIBAT3u(r16)
mfspr r9, ibat3l
stw r9, NKProcessorState.saveIBAT3l(r16)
; Save SPRGs
mfsprg r9, 0
stw r9, NKProcessorState.saveSPRG0(r16)
mfsprg r9, 1
stw r9, NKProcessorState.saveSPRG1(r16)
mfsprg r9, 2
stw r9, NKProcessorState.saveSPRG2(r16)
mfsprg r9, 3
stw r9, NKProcessorState.saveSPRG3(r16)
; Save ContextBlock ptr
stw r6, NKProcessorState.saveContextPtr(r16)
; Do the thing. The BL gives us a useful restore address.
bl ActuallySuspend
lwz r1, EWA.r1(r1)
addi r16, r1, PSA.ProcessorState
; Do something evil to the segment registers?
lisori r8, 0x1000000
lis r9, 0
@srin_loop
subis r9, r9, 0x1000
addis r8, r8, -0x10
mr. r9, r9
mtsrin r8, r9
bne @srin_loop
isync
; Reactivate L1 cache
mfspr r9, hid0
li r8, 0x800 ; HID0[ICFI] invalidate icache
ori r8, r8, 0x200 ; HID0[SPD] disable spec cache accesses
or r9, r9, r8
mtspr hid0, r9
isync
andc r9, r9, r8 ; now undo that?
mtspr hid0, r9
isync
ori r9, r9, 0x8000 ; set HID0[ICE]
ori r9, r9, 0x4000 ; set HID0[DCE]
mtspr hid0, r9
isync
; Reactivate L2 cache
lwz r26, KDP.ProcInfo.ProcessorFlags(r1)
andi. r26, r26, 1 << NKProcessorInfo.hasL2CR
beq @no_need_to_reactivate_l2
lwz r8, KDP.ProcInfo.ProcessorL2DSize(r1)
mr. r8, r8
beq @no_need_to_reactivate_l2
mfspr r9, hid0
rlwinm r9, r9, 0, 12, 10
mtspr hid0, r9
isync
lwz r9, NKProcessorState.saveL2CR(r16)
mtspr l2cr, r9
sync
isync
lis r8, 0x20 ; set L2CR[L2I] to invalidate L2 cache
or r8, r9, r8
mtspr l2cr, r8
sync
isync
; spin while bottom bit (reserved) is set???
@l2_reactivate_loop
mfspr r8, l2cr
rlwinm. r8, r8, 31, 0, 0
bne @l2_reactivate_loop
mfspr r8, l2cr
lisori r9, 0xffdfffff ; unset bit 6 (reserved?)
and r8, r8, r9
mtspr l2cr, r8
sync
mfspr r8, hid0
oris r8, r8, 0x0010 ; set HID0[HIGH_BAT_EN] (was HID0[DOZE])
mtspr hid0, r8
isync
mfspr r8, l2cr
oris r8, r8, 0x8000 ; set L2CR[L2E]
mtspr l2cr, r8
sync
isync
@no_need_to_reactivate_l2
; Still working on this...
lwz r6, NKProcessorState.saveContextPtr(r16)
lwz r7, ContextBlock.Flags(r6)
lwz r13, ContextBlock.CR(r6)
lwz r9, ContextBlock.CTR(r6)
mtctr r9
lwz r12, ContextBlock.FE000000(r6)
lwz r9, ContextBlock.XER(r6)
mtxer r9
lwz r10, NKProcessorState.saveSRR0(r16)
lwz r11, NKProcessorState.saveSRR1(r16)
; Load some GPRs
_RegRangeFromContextBlock r2, r5
_RegRangeFromContextBlock r14, r15
_RegRangeFromContextBlock r17, r31
; Load floats
andi. r8, r11, 0x2000 ; MSR[FP]
beq @no_restore_float
mfmsr r8
ori r8, r8, 0x2000 ; ensure that MSR bit is set?
mtmsr r8
isync
lfd f31, ContextBlock.PageInSystemHeap(r6) ; bit odd
_FloatRangeFromContextBlock f0, f8
mtfsf 0xff, f31
_FloatRangeFromContextBlock f9, f31
@no_restore_float
; Load HID0, plus ICE and DCE bits
lwz r9, NKProcessorState.saveHID0(r16)
ori r9, r9, 0x8000
ori r9, r9, 0x4000
mtspr hid0, r9
sync
isync
; Load timebase
lwz r9, NKProcessorState.saveTBU(r16)
mtspr tbu, r9
lwz r9, NKProcessorState.saveTBL(r16)
mtspr tbl, r9
; Set decrementer quite low?
li r9, 1
mtspr dec, r9
; Load MSR
lwz r9, NKProcessorState.saveMSR(r16)
mtmsr r9
sync
isync
; Load SDR1
lwz r9, NKProcessorState.saveSDR1(r16)
mtspr sdr1, r9
; Load SPRGs
lwz r9, NKProcessorState.saveSPRG0(r16)
mtsprg 0, r9
lwz r9, NKProcessorState.saveSPRG1(r16)
mtsprg 1, r9
lwz r9, NKProcessorState.saveSPRG2(r16)
mtsprg 2, r9
lwz r9, NKProcessorState.saveSPRG3(r16)
mtsprg 3, r9
; Load BAT registers
lwz r9, NKProcessorState.saveDBAT0u(r16)
mtspr dbat0u, r9
lwz r9, NKProcessorState.saveDBAT0l(r16)
mtspr dbat0l, r9
lwz r9, NKProcessorState.saveDBAT1u(r16)
mtspr dbat1u, r9
lwz r9, NKProcessorState.saveDBAT1l(r16)
mtspr dbat1l, r9
lwz r9, NKProcessorState.saveDBAT2u(r16)
mtspr dbat2u, r9
lwz r9, NKProcessorState.saveDBAT2l(r16)
mtspr dbat2l, r9
lwz r9, NKProcessorState.saveDBAT3u(r16)
mtspr dbat3u, r9
lwz r9, NKProcessorState.saveDBAT3l(r16)
mtspr dbat3l, r9
lwz r9, NKProcessorState.saveIBAT0u(r16)
mtspr ibat0u, r9
lwz r9, NKProcessorState.saveIBAT0l(r16)
mtspr ibat0l, r9
lwz r9, NKProcessorState.saveIBAT1u(r16)
mtspr ibat1u, r9
lwz r9, NKProcessorState.saveIBAT1l(r16)
mtspr ibat1l, r9
lwz r9, NKProcessorState.saveIBAT2u(r16)
mtspr ibat2u, r9
lwz r9, NKProcessorState.saveIBAT2l(r16)
mtspr ibat2l, r9
lwz r9, NKProcessorState.saveIBAT3u(r16)
mtspr ibat3u, r9
lwz r9, NKProcessorState.saveIBAT3l(r16)
mtspr ibat3l, r9
; And reclaim the register we were using for ProcessorState
_RegRangeFromContextBlock r16, r16
; Hooray! We're back!
li r3, 0
b IntReturn
### ###### ## ## ###### ######## ######## ## ## ######## ###
## ## ## ## ## ## ## ## ## ## ### ## ## ## ##
## ## ## ## ## ## ## ## #### ## ## ## ##
## ###### ## ## ###### ######## ###### ## ## ## ## ## ##
## ## ## ## ## ## ## ## #### ## ## ##
## ## ## ## ## ## ## ## ## ## ### ## ## ##
### ###### ####### ###### ## ######## ## ## ######## ###
ActuallySuspend
mflr r9
stw r9, NKProcessorState.saveReturnAddr(r16)
stw r1, NKProcessorState.saveKernelDataPtr(r16)
addi r9, r16, NKProcessorState.saveKernelDataPtr - 4 ; so that 4(r9) goes to r1?
li r0, 0
stw r9, 0(0)
lisori r9, 'Lars'
stw r9, 4(0)
mfspr r9, hid0
andis. r9, r9, 0x0020 ; mask: only HID0[SLEEP]
mtspr hid0, r9
mfmsr r8
oris r8, r8, 0x0004 ; set MSR[POW] (but not yet)
mfspr r9, hid0
ori r9, r9, 0x8000 ; set HID0[ICE]
mtspr hid0, r9
; Get address of this table => r9
bl @l
@l mflr r9
addi r9, r9, @table_of_sixteen_zeros - @l
lisori r1, 0xcafebabe
b @evil_aligned_sleep_loop
align 8
@evil_aligned_sleep_loop
sync
mtmsr r8 ; sleep now
isync
cmpwi r1, 0
beq @evil_aligned_sleep_loop ; re-sleep until the world is sane?
lwz r0, 0(r9)
andi. r1, r1, 0
b @evil_aligned_sleep_loop ; actually, there is no escape
align 8
@table_of_sixteen_zeros
dcb.b 16, 0
####### ###### ######## ######## #### ###### ######## ######
## ## ## ## ## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ## ##
######## ###### ###### ## ## ## ## ##
## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ## ## ## ## ##
####### ###### ######## ## #### ###### ## ######
; Selector 9
; Set ICTC (Instruction Cache Throttling Control) register
; (used to reduce temp without adjusting clock)
; ARG value r5
PwrSetICTC
mtspr 1019, r5
li r3, 0
b IntReturn
## ## ## ####### ####### ########
#### #### ## ## ## ## ## ## ##
## ## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ########
## ## ## ## ## ## ## ##
## ## ## ## ## ## ## ##
###### ###### ######## ####### ####### ##
; Selector 11
PwrInfiniteLoop
b *

1226
NanoKernel/NKPrimaryIntHandlers.s
View File

File diff suppressed because it is too large Load Diff

86
NanoKernel/NKProcFlagsTbl.s
View File

@ -1,86 +0,0 @@
; AUTO-GENERATED SYMBOL LIST
; EXPORTS:
; ProcessorFlagsTable (=> NKInit)
; Contains the table used by Init.s:SetProcessorFlags, and a label to find it with.
;
; Using this table, three fields in KDP are set:
; KDP.CpuSpecificByte1
; KDP.CpuSpecificByte2 (immediately follows Byte1)
; KDP.ProcessorInfo.ProcessorFlags
ProcessorFlagsTable
dcb.b 32 * (1 + 1 + 4), 0
ProcessorFlagsTableEnd
PflgTblCtr set 0
macro
PflgTblEnt &CpuSpecificByte1, &CpuSpecificByte2, &ProcessorFlags
@fb
org ProcessorFlagsTable + PflgTblCtr
dc.b &CpuSpecificByte1
org ProcessorFlagsTable + 32 + PflgTblCtr
dc.b &CpuSpecificByte2
org ProcessorFlagsTable + 64 + 4*PflgTblCtr
dc.l &ProcessorFlags
org @fb
PflgTblCtr set PflgTblCtr + 1
endm
with NKProcessorInfo
; CpuSpecificByte2:
HID0_NHR_only equ 1 ; Idle Power calls should set the HID0[NHR] bit
HID0_NHR_and_sleep equ 2 ; ...and the HID0 bit that potentiates MSR[POW]
HID0_neither equ 0
; See NKPowerCalls for info on CpuSpecificByte1. Its upper nybble specifies how to idle the CPU.
; CpuSpecificByte
; 1 2 ProcessorFlags CPU
; - - -------------- ---
PflgTblEnt 0x03, HID0_NHR_only, 0 ; 0**0
PflgTblEnt 0x00, HID0_neither, 0 ; 0**1 = 601
PflgTblEnt 0x03, HID0_NHR_only, 0 ; 0**2
PflgTblEnt 0x1b, HID0_NHR_and_sleep, 0 ; 0**3 = 603
PflgTblEnt 0x0a, HID0_NHR_only, 0 ; 0**4 = 604
PflgTblEnt 0x1b, HID0_NHR_and_sleep, 0 ; 0**5
PflgTblEnt 0x1b, HID0_NHR_and_sleep, 0 ; 0**6 = 603e
PflgTblEnt 0x1b, HID0_NHR_and_sleep, 0 ; 0**7 = 750FX
PflgTblEnt 0x1b, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU ; 0**8 = 750
PflgTblEnt 0x0a, HID0_NHR_only, 0 ; 0**9
PflgTblEnt 0x0a, HID0_NHR_only, 0 ; 0**a
PflgTblEnt 0x03, HID0_NHR_only, 0 ; 0**b
PflgTblEnt 0x1b, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< hasMSSregs ; 0**c = 7400
PflgTblEnt 0x0b, HID0_NHR_and_sleep, 0 ; 0**d
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 0**e
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 0**f
PflgTblEnt 0x03, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< hasMSSregs ; 8**0 = 7450 (see note below)
PflgTblEnt 0x1b, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< hasMSSregs ; 8**1 = 7445/55
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**2 = 7447 (OS X only)
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**3
PflgTblEnt 0x03, HID0_NHR_only, 0 ; 8**4
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**5
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**6
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**7
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**8
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**9
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**a
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**b
PflgTblEnt 0x1b, HID0_NHR_and_sleep, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< hasMSSregs ; 8**c = 7410
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**d
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**e
PflgTblEnt 0x03, HID0_NHR_and_sleep, 0 ; 8**f
; NB: PPC 7450 ("G4e") and its descendants (744x/745x) lack the HID0[DOZE] bit (they have HID0[HIGH_BAT_EN] instead).
; Therefore the upper nybble of CpuSpecificByte1 should be 0, or 2 for NAP (works), or 3 for SLEEP (freezes).
endwith

57
NanoKernel/NKProcInfoTbl.s
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@ -1,57 +0,0 @@
; AUTO-GENERATED SYMBOL LIST
; EXPORTS:
; OverrideProcessorInfo (=> NKBuiltinInit)
; ProcessorInfoTable (=> NKBuiltinInit)
; Contains the table used by InitBuiltin.s:OverrideProcessorInfo
;
; If the Trampoline fails to pass in a signed HardwareInfo struct,
; this is our first choice for populating ProcessorInfo.
;
; Also contains a 'function' that will do the populating
; (not very clever), and fall through to the end of the file,
; where we expect to find Init.s:FinishInitBuiltin.
macro ; just to make the table below look nicer...
PnfoTblEnt &a, &b, &c, &d, &e, &f, &g, &h, &i, &j, &k, &l, &m, &n, &o
dc.l &a * 1024, &b * 1024, &c * 1024
dc.w &d, &e, &f, &g, &h, &i, &j, &k, &l, &m, &n, &o
endm
ProcessorInfoTable
; - PageSize, KB
; | - DataCacheTotalSize, KB
; | | - InstCacheTotalSize, KB
; | | | - CoherencyBlockSize
; | | | | - ReservationGranuleSize
; | | | | | - CombinedCaches
; | | | | | | - InstCacheLineSize
; | | | | | | | - DataCacheLineSize
; | | | | | | | | - DataCacheBlockSizeTouch
; | | | | | | | | | - InstCacheBlockSize
; | | | | | | | | | | - DataCacheBlockSize
; | | | | | | | | | | | - InstCacheAssociativity
; | | | | | | | | | | | | - DataCacheAssociativity
; | | | | | | | | | | | | | - TransCacheTotalSize
; | | | | | | | | | | | | | | - TransCacheAssociativity
PnfoTblEnt 4, 32, 32, 32, 32, 1, 64, 64, 32, 32, 32, 8, 8, 256, 2 ; 0001 = 601
PnfoTblEnt 4, 8, 8, 32, 32, 0, 32, 32, 32, 32, 32, 2, 2, 64, 2 ; 0003 = 603
PnfoTblEnt 4, 16, 16, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 128, 2 ; 0004 = 604
PnfoTblEnt 4, 16, 16, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 64, 2 ; 0006 = 603e
PnfoTblEnt 4, 16, 16, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 64, 2 ; 0007 = 750FX
PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 8, 8, 128, 2 ; 0008 = 750
PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 128, 2 ; 0009/a = ???
PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 8, 8, 128, 2 ; 000c = 7400
PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 8, 8, 256, 4 ; 000d = ???
OverrideProcessorInfo
@loop
subic. r9, r9, 4
lwzx r12, r11, r9
stwx r12, r10, r9
bgt @loop

193
NanoKernel/NKRTASCalls.s
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@ -1,193 +0,0 @@
; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKExceptions
; IntReturn
; NKFloatInts
; IntHandleSpecialFPException
; bugger_around_with_floats
; NKPaging
; PagingL2PWithBATs
; NKThud
; panic
; EXPORTS:
; kcRTASDispatch (=> NKInit)
Local_Panic set *
b panic
; kcRTASDispatch
; Only major that hits the RTAS globals.
; RTAS requires some specific context stuff.
; > r1 = kdp
; > r6 = some kind of place
; > r7 = some kind of flags
align 5
kcRTASDispatch ; OUTSIDE REFERER
lwz r8, 0x0908(r1)
cmpwi r8, 0x00
bne rtas_is_available
li r3, -0x01
b IntReturn
rtas_is_available
_Lock PSA.RTASLock, scratch1=r8, scratch2=r9
mtcrf 0x3f, r7
lwz r9, KDP.PA_ECB(r1)
lwz r8, EWA.Enables(r1)
stw r7, 0x0000(r6)
stw r8, 0x0004(r6)
bns cr6, kcRTASDispatch_0x5c
stw r17, 0x0024(r6)
stw r20, 0x0028(r6)
stw r21, 0x002c(r6)
stw r19, 0x0034(r6)
stw r18, 0x003c(r6)
lmw r14, 0x0038(r1)
kcRTASDispatch_0x5c
mfxer r8
stw r13, 0x00dc(r6)
stw r8, 0x00d4(r6)
stw r12, 0x00ec(r6)
mfctr r8
stw r10, 0x00fc(r6)
stw r8, 0x00f4(r6)
ble cr3, kcRTASDispatch_0x8c
lwz r8, 0x00c4(r9)
mfspr r12, mq
mtspr mq, r8
stw r12, 0x00c4(r6)
kcRTASDispatch_0x8c
lwz r8, 0x0004(r1)
stw r8, 0x010c(r6)
stw r2, 0x0114(r6)
stw r3, 0x011c(r6)
stw r4, 0x0124(r6)
lwz r8, 0x0018(r1)
stw r5, 0x012c(r6)
stw r8, 0x0134(r6)
andi. r8, r11, 0x2000
stw r14, 0x0174(r6)
stw r15, 0x017c(r6)
stw r16, 0x0184(r6)
stw r17, 0x018c(r6)
stw r18, 0x0194(r6)
stw r19, 0x019c(r6)
stw r20, 0x01a4(r6)
stw r21, 0x01ac(r6)
stw r22, 0x01b4(r6)
stw r23, 0x01bc(r6)
stw r24, 0x01c4(r6)
stw r25, 0x01cc(r6)
stw r26, 0x01d4(r6)
stw r27, 0x01dc(r6)
stw r28, 0x01e4(r6)
stw r29, 0x01ec(r6)
stw r30, 0x01f4(r6)
stw r31, 0x01fc(r6)
bnel bugger_around_with_floats
stw r11, 0x00a4(r6)
mr r27, r3
addi r29, r1, KDP.BATs + 0xa0
bl PagingL2PWithBATs
beql Local_Panic
rlwimi r3, r31, 0, 0, 19
lhz r8, 0x0004(r3)
cmpwi r8, 0x00
beq kcRTASDispatch_0x14c
slwi r8, r8, 2
lwzx r27, r8, r3
addi r29, r1, KDP.BATs + 0xa0
bl PagingL2PWithBATs
beql Local_Panic
lwzx r9, r8, r3
rlwimi r9, r31, 0, 0, 19
stwx r9, r8, r3
li r9, 0x00
sth r9, 0x0004(r3)
dcbf r8, r3
kcRTASDispatch_0x14c
li r9, 0x04
dcbf r9, r3
sync
isync
lwz r4, 0x090c(r1)
mfmsr r8
andi. r8, r8, 0x10cf
mtmsr r8
isync
mr r28, r3
lwz r9, 0x0908(r1)
bl rtas_make_actual_call
mfsprg r1, 0
lwz r6, -0x0014(r1)
clrlwi r29, r28, 0x14
subfic r29, r29, 0x1000
lhz r27, 0x0f4a(r1)
kcRTASDispatch_0x190
subf. r29, r27, r29
dcbf r29, r28
sync
icbi r29, r28
bge kcRTASDispatch_0x190
sync
isync
lwz r8, 0x0000(r6)
lwz r11, 0x00a4(r6)
mr r7, r8
andi. r8, r11, 0x900
lwz r8, 0x0004(r6)
lwz r13, 0x00dc(r6)
stw r8, EWA.Enables(r1)
lwz r8, 0x00d4(r6)
lwz r12, 0x00ec(r6)
mtxer r8
lwz r8, 0x00f4(r6)
lwz r10, 0x00fc(r6)
mtctr r8
bnel IntHandleSpecialFPException
lwz r8, 0x010c(r6)
stw r8, 0x0004(r1)
lwz r2, 0x0114(r6)
lwz r3, 0x011c(r6)
lwz r4, 0x0124(r6)
lwz r8, 0x0134(r6)
lwz r5, 0x012c(r6)
stw r8, 0x0018(r1)
lwz r14, 0x0174(r6)
lwz r15, 0x017c(r6)
lwz r16, 0x0184(r6)
lwz r17, 0x018c(r6)
lwz r18, 0x0194(r6)
lwz r19, 0x019c(r6)
lwz r20, 0x01a4(r6)
lwz r21, 0x01ac(r6)
lwz r22, 0x01b4(r6)
lwz r23, 0x01bc(r6)
lwz r24, 0x01c4(r6)
lwz r25, 0x01cc(r6)
lwz r26, 0x01d4(r6)
lwz r27, 0x01dc(r6)
lwz r28, 0x01e4(r6)
lwz r29, 0x01ec(r6)
lwz r30, 0x01f4(r6)
lwz r31, 0x01fc(r6)
_AssertAndRelease PSA.RTASLock, scratch=r8
li r3, 0x00
b IntReturn
rtas_make_actual_call
mtctr r9
bctr

497
NanoKernel/NKReplacementInit.s
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@ -1,497 +0,0 @@
; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKConsoleLog
; printh
; printw
; NKInit
; CancelReplacement
; InitHighLevel
; InitIRP
; NKPrimaryIntHandlers
; LookupInterruptHandler
; NKScreenConsole
; InitScreenConsole
; NKTranslation
; FDP
; EXPORTS:
; InitReplacement (=> NKInit)
; sprg0 = old KDP/EWA/r1 ptr
; r3 = PA_NanoKernelCode
; r4 = physical base of our global area
; r5 = NoIdeaR23
; r6 = PA_EDP or zero?
; r7 = probably ROMHeader.ROMRelease ('rom vers', e.g. 0x10B5 is 1.0§5)
InitReplacement
crset cr5_eq
li r0, 0
; Position and initialise the kernel globals, IRP to KDP inclusive.
; (subset of builtin kernel)
; Zero from IRP (r4) to KDP (r4 + 10 pages)
lisori r12, kKDPfromIRP
mr r13, r4
@wipeloop
subic. r12, r12, 4
stwx r0, r13, r12
bgt @wipeloop
; Copy the old KDP to r4 + 10 pages.
; (r1 becomes our main ptr and r4 is discarded)
mfsprg r11, 0
lisori r1, kKDPfromIRP
add r1, r1, r4
li r12, 4096
@kdp_copyloop
subic. r12, r12, 4
lwzx r10, r11, r12
stwx r10, r1, r12
bgt @kdp_copyloop
; IRP goes at the base of the area we were given.
; Fill with repeating pattern and point EWA at it.
lisori r12, -kKDPfromIRP
add r12, r12, r1
stw r12, EWA.PA_IRP(r1)
bl InitIRP ; clobbers r10 and r12
; Play with some of the other values we were given
; Leave ROMRelease in r23.
mr r23, r7
; If no EDP (Emulator Data Page) pointer was provided,
; then put the EDP above our new KDP.
cmpwi r6, 0
stw r11, KDP.OldKDP(r1)
stw r9, 0x05a4(r1)
; discarded
bne @emulatordata_ptr_provided
addi r6, r1, 0x1000
@emulatordata_ptr_provided
; Save a few bits
stw r6, 0x05a8(r1)
stw r3, KDP.PA_NanoKernelCode(r1)
stw r5, PSA.NoIdeaR23(r1)
stw r1, EWA.PA_KDP(r1)
addi r12, r1, -0x340 ; get the base of the main CPU struct
li r10, -1
stw r10, CPU.ID(r12)
lwz r3, KDP.PA_ConfigInfo(r1)
bl LookupInterruptHandler
stw r7, KDP.PA_InterruptHandler(r1)
; Clearly changed our mind about where we might be.
bl @x
@x mflr r12
subi r12, r12, @x - NKTop
stw r12, KDP.PA_NanoKernelCode(r1)
; FDP
llabel r10, FDP
add r12, r10, r12
stw r12, KDP.PA_FDP(r1)
; Do something terrible with the CPU features
lwz r12, EWA.Flags(r1)
li r10, 0x00
rlwimi r10, r12, 0, 12, 15
rlwimi r10, r12, 0, 28, 30
stw r10, PSA.FlagsTemplate(r1)
; Cook up a MSR:
; MSR_EE = 1
; MSR_PR = 1
; MSR_FP = 0
; MSR_ME = 0
; MSR_FE0 = 0
; MSR_SE = 0
; MSR_BE = 0
; MSR_FE1 = 0
; MSR_IP = preserved
; MSR_IR = 1
; MSR_DR = 1
; MSR_RI = 0
; MSR_LE = 0
mfmsr r12
andi. r12, r12, 0x0040
ori r12, r12, 0xd032
stw r12, PSA.UserModeMSR(r1)
; Set SPRG0 (for this CPU at least)
mtsprg 0, r1
; r11 still contains the OLD EWA ptr (which is also KDP/PSA ptr?)
lhz r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r11)
cmpwi r12, 0x0101
bgt @replaces_later_than_0101
; Move some per-cpu values from KDP to EWA
lwz r12, KDP.PA_ContextBlock(r1)
stw r12, EWA.PA_ContextBlock(r1)
lwz r12, KDP.Flags(r1)
_bset r12, r12, EWA.kFlag9
stw r12, EWA.Flags(r1)
lwz r12, KDP.Enables(r1)
stw r12, EWA.Enables(r1)
b @endif
@replaces_later_than_0101
; Obviously cannot replace a v2 NanoKernel like myself
cmpwi r12, 0x0200
bge CancelReplacement
lwz r12, EWA.PA_ContextBlock(r11)
stw r12, EWA.PA_ContextBlock(r1)
lwz r12, EWA.Flags(r11)
oris r12, r12, 0x20
stw r12, EWA.Flags(r1)
lwz r12, -0x000c(r11)
stw r12, EWA.Enables(r1)
@endif
lwz r12, 0x0340(r11)
lwz r10, KDP.LA_NCB(r11)
cmpw r12, r10
beq replace_old_kernel_0x198
stw r12, KDP.LA_NCB(r1)
stw r0, 0x06b4(r1)
lwz r10, 0x05b0(r11)
stw r10, 0x06c0(r1)
lwz r10, KDP.LA_NCB(r11)
stw r10, 0x06c4(r1)
lwz r10, 0x05b8(r11)
stw r10, 0x06c8(r1)
lwz r10, 0x05bc(r11)
stw r10, 0x06cc(r1)
stw r0, 0x06d0(r1)
stw r0, 0x06d4(r1)
stw r0, 0x06d8(r1)
stw r0, 0x06dc(r1)
stw r0, 0x06e0(r1)
stw r0, 0x06e4(r1)
stw r0, 0x06e8(r1)
stw r0, 0x06ec(r1)
stw r0, 0x06f0(r1)
stw r0, 0x06f4(r1)
stw r0, 0x06f8(r1)
stw r0, 0x06fc(r1)
replace_old_kernel_0x198
; Adjust a few KDP pointers to point into the new KDP
lwz r12, KDP.PA_PageMapStart(r1)
subf r12, r11, r12
add r12, r12, r1
stw r12, KDP.PA_PageMapStart(r1)
lwz r12, KDP.PA_PageMapEnd(r1)
subf r12, r11, r12
add r12, r12, r1
stw r12, KDP.PA_PageMapEnd(r1)
lwz r12, 0x05e8(r1)
subf r12, r11, r12
add r12, r12, r1
stw r12, 0x05e8(r1)
; Wipe KDP's NKInfo and ProcessorInfo
li r12, 0x200
addi r10, r1, KDP.NanoKernelInfo
@wipeloop
subic. r12, r12, 4
stwx r0, r10, r12
bgt @wipeloop
; r9 = physical base of kernel
li r12, 0
addi r10, r1, KDP.InfoRecord
bl MoveRecord ; (NanoKernelCode, NewKDPInfoRecord, OldKDP, 0)
stw r10, KDP.InfoRecord + InfoRecord.InfoRecordPtr(r1)
stw r0, KDP.InfoRecord + InfoRecord.Zero(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKProcessorStateLen(r1)
addi r10, r1, PSA.ProcessorState
lwz r9, KDP.InfoRecord + InfoRecord.NKProcessorStatePtr(r1)
bl MoveRecord ; (OldProcessorState, NewPSAProcessorState, OldKDP, ProcessorStateLen)
stw r10, KDP.InfoRecord + InfoRecord.NKProcessorStatePtr(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKHWInfoLen(r1)
lwz r10, EWA.PA_IRP(r1)
addi r10, r10, IRP.HWInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKHWInfoPtr(r1)
bl MoveRecord ; (OldHWInfo, NewIRPHWInfo, OldKDP, HWInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKHWInfoPtr(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen(r1)
addi r10, r1, KDP.ProcessorInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr(r1)
bl MoveRecord ; (OldProcessorInfo, NewKDPProcessorInfo, OldKDP, ProcessorInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr(r1)
stw r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr2(r1)
lhz r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer(r1)
cmplwi r10, 0x0112
bge @ProcessorInfo_version_already_current
li r12, 160
li r10, 0x0112
sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen(r1)
sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen2(r1)
sth r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer(r1)
sth r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer2(r1)
@ProcessorInfo_version_already_current
lhz r12, KDP.InfoRecord + InfoRecord.NKDiagInfoLen(r1)
addi r10, r1, PSA.DiagInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKDiagInfoPtr(r1)
bl MoveRecord ; (OldDiagInfo, NewPSADiagInfo, OldKDP, DiagInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKDiagInfoPtr(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKSystemInfoLen(r1)
lwz r10, EWA.PA_IRP(r1)
addi r10, r10, IRP.SystemInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKSystemInfoPtr(r1)
bl MoveRecord ; (OldSystemInfo, NewIRPSystemInfo, OldKDP, SystemInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKSystemInfoPtr(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoLen(r1)
addi r10, r1, KDP.NanoKernelInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoPtr(r1)
bl MoveRecord ; (OldNanoKernelInfo, NewKDPNanoKernelInfo, OldKDP, NanoKernelInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoPtr(r1)
li r12, 0x160
sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoLen(r1)
li r12, kNanoKernelVersion
sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r1)
lwz r8, KDP.ProcInfo.DecClockRateHz(r1)
stw r8, PSA.DecClockRateHzCopy(r1)
; Play with ConfigFlags
lwz r8, KDP.NKInfo.ConfigFlags(r1)
_bset r8, r8, 31 ; always set bit 31
if &TYPE('NKShowLog') != 'UNDEFINED'
_bset r8, r8, 28 ; see if someone can test this
endif
cmplwi r23, 0x27f3 ; set bit 27 on ROM 2.7f3 or later
blt @oldrom ; means later than PDM and Cordyceps
_bset r8, r8, 27
@oldrom
stw r8, KDP.NKInfo.ConfigFlags(r1)
; Say hello.
bl InitScreenConsole
_log 'Hello from the replacement multitasking NanoKernel. Version: '
mr r8, r12
bl printh
_log '^n Old KDP: '
mr r8, r11
bl printw
_log ' new KDP: '
mr r8, r1
bl printw
_log ' new irp: '
lwz r8, EWA.PA_IRP(r1)
mr r8, r8
bl printw
_log 'ROM vers: '
mr r8, r23
bl printh
_log '^n'
; Jump back into the common code path of Init.s
; The Emulator ContextBlock is expected in r6.
lwz r6, KDP.PA_ECB(r1)
b InitHighLevel
; MoveRecord
; r9 = base of kernel???
; Seems to be code to relocate some old structures.
MoveRecord ; OUTSIDE REFERER
; Check whether the old structure is in KDP
;
lwz r22, KDP.PA_ConfigInfo(r1)
lwz r22, NKConfigurationInfo.LA_InfoRecord(r22)
subf r9, r22, r9 ; r9 = offset of old address in irp
cmplwi r9, 0x1000
bge @kdp
add r21, r9, r11 ; r21 = the old address if it had been in KDP instead?
@0x18
; r9 = offset of old structure in old parent page
; r10 = destination
; r12 = length
;
@loop
subic. r12, r12, 4
blt @exit_loop
lwzx r9, r21, r12
stwx r9, r10, r12
bgt @loop
@exit_loop
lwz r22, KDP.PA_ConfigInfo(r1)
lwz r22, NKConfigurationInfo.LA_KernelData(r22)
subf r10, r1, r10
lisori r21, -9 * 4096
cmpw r10, r21 ; if dest is nearer than 9 pages below kdp...
blt @0x50
add r10, r10, r22
blr
@0x50
lwz r22, KDP.PA_ConfigInfo(r1)
lwz r22, NKConfigurationInfo.LA_InfoRecord(r22)
lwz r21, EWA.PA_IRP(r1)
add r10, r10, r1
subf r10, r21, r10
add r10, r10, r22
blr
@kdp
add r9, r9, r22
lwz r22, KDP.PA_ConfigInfo(r1)
lwz r22, NKConfigurationInfo.LA_KernelData(r22)
subf r9, r22, r9 ; r9 now equals an offset from old_kdp
add r21, r9, r11 ; r21 = address in new_kdp
b @0x18

92
NanoKernel/NKReset.s
View File

@ -23,8 +23,8 @@ InitVectorTables
; System/Alternate Context tables
_kaddr r23, rNK, SystemCrash
addi r8, r1, KDP.VecBaseSystem
li r22, 3 * VecTable.Size
addi r8, r1, KDP.VecTblSystem
li r22, 3 * VecTbl.Size
@vectab_initnext_segment
subic. r22, r22, 4
stwx r23, r8, r22
@ -33,26 +33,26 @@ InitVectorTables
rSys set r9 ; to clarify which table is which
rAlt set r8
addi rSys, r1, KDP.VecBaseSystem
addi rSys, r1, KDP.VecTblSystem
mtsprg 3, rSys
addi rAlt, r1, KDP.VecBaseAlternate
addi rAlt, r1, KDP.VecTblAlternate
_kaddr r23, rNK, SystemCrash
stw r23, VecTable.SystemResetVector(rSys)
stw r23, VecTable.SystemResetVector(rAlt)
stw r23, VecTbl.SystemResetVector(rSys)
stw r23, VecTbl.SystemResetVector(rAlt)
_kaddr r23, rNK, IntMachineCheck
stw r23, VecTable.MachineCheckVector(rSys)
stw r23, VecTable.MachineCheckVector(rAlt)
stw r23, VecTbl.MachineCheckVector(rSys)
stw r23, VecTbl.MachineCheckVector(rAlt)
_kaddr r23, rNK, IntDSI
stw r23, VecTable.DSIVector(rSys)
stw r23, VecTable.DSIVector(rAlt)
stw r23, VecTbl.DSIVector(rSys)
stw r23, VecTbl.DSIVector(rAlt)
_kaddr r23, rNK, IntISI
stw r23, VecTable.ISIVector(rSys)
stw r23, VecTable.ISIVector(rAlt)
stw r23, VecTbl.ISIVector(rSys)
stw r23, VecTbl.ISIVector(rAlt)
lbz r22, NKConfigurationInfo.InterruptHandlerKind(rCI)
@ -67,88 +67,78 @@ rAlt set r8
beq @chosenIntHandler
@chosenIntHandler
stw r23, VecTable.ExternalIntVector(rSys)
stw r23, VecTbl.ExternalIntVector(rSys)
_kaddr r23, rNK, IntProgram
stw r23, VecTable.ExternalIntVector(rAlt)
stw r23, VecTbl.ExternalIntVector(rAlt)
_kaddr r23, rNK, IntAlignment
stw r23, VecTable.AlignmentIntVector(rSys)
stw r23, VecTable.AlignmentIntVector(rAlt)
stw r23, VecTbl.AlignmentIntVector(rSys)
stw r23, VecTbl.AlignmentIntVector(rAlt)
_kaddr r23, rNK, IntProgram
stw r23, VecTable.ProgramIntVector(rSys)
stw r23, VecTable.ProgramIntVector(rAlt)
stw r23, VecTbl.ProgramIntVector(rSys)
stw r23, VecTbl.ProgramIntVector(rAlt)
_kaddr r23, rNK, IntFPUnavail
stw r23, VecTable.FPUnavailVector(rSys)
stw r23, VecTable.FPUnavailVector(rAlt)
stw r23, VecTbl.FPUnavailVector(rSys)
stw r23, VecTbl.FPUnavailVector(rAlt)
_kaddr r23, rNK, IntDecrementerSystem
stw r23, VecTable.DecrementerVector(rSys)
stw r23, VecTbl.DecrementerVector(rSys)
_kaddr r23, rNK, IntDecrementerAlternate
stw r23, VecTable.DecrementerVector(rAlt)
stw r23, VecTbl.DecrementerVector(rAlt)
_kaddr r23, rNK, IntSyscall
stw r23, VecTable.SyscallVector(rSys)
stw r23, VecTable.SyscallVector(rAlt)
stw r23, VecTbl.SyscallVector(rSys)
stw r23, VecTbl.SyscallVector(rAlt)
_kaddr r23, rNK, IntTrace
stw r23, VecTable.TraceVector(rSys)
stw r23, VecTable.TraceVector(rAlt)
stw r23, VecTbl.TraceVector(rSys)
stw r23, VecTbl.TraceVector(rAlt)
stw r23, 0x0080(rSys) ; Unexplored parts of vecBase
stw r23, 0x0080(rAlt)
; MemRetry vector table
addi r8, r1, KDP.VecBaseMemRetry
addi r8, r1, KDP.VecTblMemRetry
_kaddr r23, rNK, MemRetryMachineCheck
stw r23, VecTable.MachineCheckVector(r8)
stw r23, VecTbl.MachineCheckVector(r8)
_kaddr r23, rNK, MemRetryDSI
stw r23, VecTable.DSIVector(r8)
stw r23, VecTbl.DSIVector(r8)
########################################################################
; Fill the NanoKernelCallTable, the IntProgram interface to the NanoKernel
; Fill the KCallTbl, the IntProgram interface to the NanoKernel
InitKCalls
; Start with a default function
_kaddr r23, rNK, KCallSystemCrash
addi r8, r1, KDP.NanoKernelCallTable
li r22, NanoKernelCallTable.Size
@kctab_initnext_segment
_kaddr r23, rNK, KCallSystemCrash ; Uninited call -> crash
addi r8, r1, KDP.KCallTbl
li r22, KCallTbl.Size
@loop
subic. r22, r22, 4
stwx r23, r8, r22
bne @kctab_initnext_segment
; Then some overrides (names still pretty poor)
bne @loop
_kaddr r23, rNK, KCallReturnFromException
stw r23, NanoKernelCallTable.ReturnFromException(r8)
stw r23, KCallTbl.ReturnFromException(r8)
_kaddr r23, rNK, KCallRunAlternateContext
stw r23, NanoKernelCallTable.RunAlternateContext(r8)
stw r23, KCallTbl.RunAlternateContext(r8)
_kaddr r23, rNK, KCallResetSystem
stw r23, NanoKernelCallTable.ResetSystem(r8)
stw r23, KCallTbl.ResetSystem(r8)
_kaddr r23, rNK, KCallVMDispatch
stw r23, NanoKernelCallTable.VMDispatch(r8)
stw r23, KCallTbl.VMDispatch(r8)
_kaddr r23, rNK, KCallPrioritizeInterrupts
stw r23, NanoKernelCallTable.PrioritizeInterrupts(r8)
stw r23, KCallTbl.PrioritizeInterrupts(r8)
_kaddr r23, rNK, KCallSystemCrash
stw r23, NanoKernelCallTable.Thud(r8)
stw r23, KCallTbl.SystemCrash(r8)
########################################################################

2292
NanoKernel/NKScheduler.s
View File

File diff suppressed because it is too large Load Diff

1244
NanoKernel/NKScreenConsole.s
View File

File diff suppressed because it is too large Load Diff

654
NanoKernel/NKSleep.s
View File

@ -1,654 +0,0 @@
; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKIntMisc
; SIGP
; NKMPCalls
; CommonMPCallReturnPath
; ReturnMPCallOOM
; ReturnParamErrFromMPCall
; ReturnZeroFromMPCall
; NKPaging
; PagingFlushTLB
; PagingFunc2AndAHalf
; PagingL2PWithBATs
; NKScheduler
; Save_f0_f31
; Save_v0_v31
; SchSwitchSpace
; NKThud
; panic
; Implements two MPCalls that seem to have something to do with COHGs
; Make conditional calls easier
Local_Panic set *
b panic
Local_ReturnParamErrFromMPCall
b ReturnParamErrFromMPCall
Local_ReturnInsufficientResourcesErrFromMPCall
b ReturnMPCallOOM
Local_CommonMPCallReturnPath
b CommonMPCallReturnPath
; RET OSStatus r3, something r4, something r4
DeclareMPCall 102, MPGetKernelStateSize
MPGetKernelStateSize
mfsprg r9, 0
lwz r8, EWA.CPUBase + CPU.LLL + LLL.Freeform(r9)
lwz r9, CoherenceGroup.ScheduledCpuCount(r8)
cmpwi r9, 1
bgt Local_ReturnInsufficientResourcesErrFromMPCall
bl KernelStateSize
mr r4, r8
mr r5, r9
b ReturnZeroFromMPCall
; ARG r3/r4/r5
; RET OSStatus r3
DeclareMPCall 103, MPGetKernelState
MPGetKernelState
mfsprg r9, 0
lwz r8, EWA.CPUBase + CPU.LLL + LLL.Freeform(r9)
lwz r9, CoherenceGroup.ScheduledCpuCount(r8)
cmpwi r9, 1
bgt Local_ReturnInsufficientResourcesErrFromMPCall
clrlwi. r8, r5, 20
bne Local_ReturnParamErrFromMPCall
bl KernelStateSize
cmpw r3, r8
blt Local_ReturnParamErrFromMPCall
cmpw r4, r9
blt Local_ReturnParamErrFromMPCall
bl PagingFlushTLB
mfsprg r9, 0
mfxer r8
stw r13, 0x00dc(r6)
stw r8, 0x00d4(r6)
stw r12, 0x00ec(r6)
mfctr r8
stw r10, 0x00fc(r6)
stw r8, 0x00f4(r6)
mfpvr r8
rlwinm. r8, r8, 0, 0, 14
bne @not_601
mfspr r8, mq
stw r8, ContextBlock.MQ(r6)
@not_601
lwz r8, EWA.r1(r9)
stw r8, ContextBlock.r1(r6)
stw r2, ContextBlock.r2(r6)
stw r3, ContextBlock.r3(r6)
andi. r8, r11, MSR_FP
stw r4, ContextBlock.r4(r6)
lwz r8, EWA.r6(r9)
stw r5, ContextBlock.r5(r6)
stw r8, ContextBlock.r6(r6)
bnel Save_f0_f31
rlwinm. r8, r7, 0, EWA.kFlagVec, EWA.kFlagVec ; flags
bnel+ Save_v0_v31
lwz r3, ContextBlock.r3(r6)
lwz r4, ContextBlock.r4(r6)
lwz r5, ContextBlock.r5(r6)
stw r11,ContextBlock.MSR(r6)
mr r27, r5
addi r29, r1, KDP.BATs + 0xa0
bl PagingL2PWithBATs
beq Local_ReturnInsufficientResourcesErrFromMPCall
rlwimi r27, r31, 0, 0, 19
mr r17, r27
addi r15, r17, 0x34
srwi r3, r3, 12
MPGetKernelState_0xc8
mr r27, r5
addi r29, r1, KDP.BATs + 0xa0
bl PagingL2PWithBATs
beq Local_ReturnInsufficientResourcesErrFromMPCall
rlwimi r27, r31, 0, 0, 19
stwu r27, 0x0004(r15)
addi r3, r3, -0x01
addi r5, r5, 0x1000
cmpwi r3, 0x00
bge MPGetKernelState_0xc8
addi r15, r15, 0x04
subf r15, r17, r15
stw r15, 0x0034(r17)
mfsprg r15, 0
stw r15, 0x0024(r17)
mfsprg r8, 3
stw r8, 0x0028(r17)
@retry_time
mftbu r8
mftb r9
mftbu r16
cmpw r16, r8
bne- @retry_time
stw r8, EWA.SpacesSavedLR(r15)
stw r9, EWA.SpacesSavedCR(r15)
mr r29, r17
li r16, kSIGP6
stw r16, EWA.SIGPSelector(r15)
lhz r16, EWA.CPUIndex(r15)
stw r16, EWA.SIGPCallR4(r15)
li r8, 2 ; args in EWA
bl SIGP
mr r17, r29
mfsdr1 r8
stw r8, 0x002c(r17)
rlwinm r9, r8, 16, 7, 15
cntlzw r18, r9
li r9, -0x01
srw r9, r9, r18
addi r9, r9, 0x01
stw r9, 0x000c(r17)
rlwinm r8, r8, 0, 0, 15
stw r8, 0x0010(r17)
lis r8, 0x00
ori r8, r8, 0xc000
stw r8, 0x0018(r17)
lis r9, 0x00
ori r9, r9, 0xa000
subf r8, r9, r1
stw r8, 0x001c(r17)
addi r9, r1, 120
lis r31, 0x00
li r14, 0x00
lwz r29, 0x0034(r17)
add r29, r29, r17
MPGetKernelState_0x1a0
lwzu r30, 0x0008(r9)
MPGetKernelState_0x1a4
lwz r18, 0x0004(r30)
lhz r15, 0x0000(r30)
andi. r19, r18, 0xe00
lhz r16, 0x0002(r30)
cmplwi r19, 0xc00
bne MPGetKernelState_0x1dc
addi r16, r16, 0x01
slwi r16, r16, 2
stw r16, 0x0000(r29)
rlwinm r18, r18, 22, 0, 29
stw r18, 0x0004(r29)
addi r29, r29, 0x0c
addi r14, r14, 0x01
b MPGetKernelState_0x1fc
MPGetKernelState_0x1dc
cmpwi r15, 0x00
bne MPGetKernelState_0x1fc
cmplwi r16, 0xffff
bne MPGetKernelState_0x1fc
addis r31, r31, 0x1000
cmpwi r31, 0x00
bne MPGetKernelState_0x1a0
b MPGetKernelState_0x204
MPGetKernelState_0x1fc
addi r30, r30, 0x08
b MPGetKernelState_0x1a4
MPGetKernelState_0x204
lwz r16, PSA.FirstPoolSeg(r1)
MPGetKernelState_0x208
lwz r31, 0x0000(r16)
add r18, r31, r16
lwz r19, 0x0000(r18)
addi r31, r31, 0x18
stw r31, 0x0000(r29)
stw r16, 0x0004(r29)
addi r29, r29, 0x0c
addi r14, r14, 0x01
cmpwi r19, 0x00
beq MPGetKernelState_0x238
add r16, r19, r18
b MPGetKernelState_0x208
MPGetKernelState_0x238
addi r19, r1, PSA.FreeList
lwz r31, PSA.FreeList + LLL.Next(r1)
MPGetKernelState_0x240
cmpw r31, r19
beq MPGetKernelState_0x264
li r18, 0x10
stw r18, 0x0000(r29)
stw r31, 0x0004(r29)
addi r29, r29, 0x0c
addi r14, r14, 0x01
lwz r31, 0x0008(r31)
b MPGetKernelState_0x240
MPGetKernelState_0x264
stw r14, 0x0030(r17)
lwz r30, 0x0034(r17)
add r30, r30, r17
MPGetKernelState_0x270
subf r8, r17, r29
stw r8, 0x0008(r30)
lwz r24, 0x0004(r30)
mr r25, r8
lwz r26, 0x0000(r30)
add r29, r29, r26
bl AnotherCoherenceFunc
addi r30, r30, 0x0c
addi r14, r14, -0x01
cmpwi r14, 0x00
bne MPGetKernelState_0x270
subf r8, r17, r29
stw r8, 0x0020(r17)
lwz r24, 0x001c(r17)
mr r25, r8
lwz r26, 0x0018(r17)
add r29, r29, r26
bl AnotherCoherenceFunc
subf r8, r17, r29
stw r8, 0x0014(r17)
lwz r24, 0x0010(r17)
mr r25, r8
lwz r26, 0x000c(r17)
add r29, r29, r26
bl AnotherCoherenceFunc
bl LoadStateRestoreFunc
mflr r9
stw r9, 0x0000(r17)
lwz r8, PSA.NoIdeaR23(r1)
stw r8, 0x0008(r17)
li r8, 0x00
stw r8, 0x0004(r17)
mfsprg r15, 0
li r16, kSIGP17
stw r16, EWA.SIGPSelector(r15)
lhz r16, EWA.CPUIndex(r15)
stw r16, EWA.SIGPCallR4(r15)
li r8, 2 ; args in EWA
bl SIGP
li r3, 0
b Local_CommonMPCallReturnPath
LoadStateRestoreFunc
blrl
mr r17, r3
lwz r24, 0x0014(r17)
lwz r25, 0x0010(r17)
lwz r26, 0x000c(r17)
bl YetAnotherCoherenceFunc
lwz r24, 0x002c(r17)
mtsdr1 r24
lwz r24, 0x0020(r17)
lwz r25, 0x001c(r17)
lwz r26, 0x0018(r17)
bl YetAnotherCoherenceFunc
lwz r14, 0x0030(r17)
lwz r30, 0x0034(r17)
add r30, r30, r17
RestoreKernelState_0x38
lwz r24, 0x0008(r30)
lwz r25, 0x0004(r30)
lwz r26, 0x0000(r30)
bl YetAnotherCoherenceFunc
addi r30, r30, 0x0c
addi r14, r14, -0x01
cmpwi r14, 0x00
bne RestoreKernelState_0x38
lwz r16, 0x0024(r17)
mtsprg 0, r16
lwz r8, 0x0028(r17)
mtsprg 3, r8
lwz r1, -0x0004(r16)
lwz r6, -0x0014(r16)
lwz r7, -0x0010(r16)
li r8, -0x01
stw r8, 0x0004(r17)
lwz r8, EWA.SpacesSavedLR(r16)
lwz r9, EWA.SpacesSavedCR(r16)
li r16, 0x01
mttb r16
mttbu r8
mttb r9
mtdec r16
_log 'Resuming saved kernel state^n'
lwz r8, 0x00d4(r6)
lwz r13, 0x00dc(r6)
mtxer r8
lwz r12, 0x00ec(r6)
lwz r8, 0x00f4(r6)
lwz r10, 0x00fc(r6)
mtctr r8
lwz r11, 0x00a4(r6)
mfpvr r8
rlwinm. r8, r8, 0, 0, 14
bne RestoreKernelState_0xf8
lwz r8, 0x00c4(r6)
DIALECT POWER
mtmq r8
DIALECT PowerPC
RestoreKernelState_0xf8
lwz r4, -0x0020(r1)
li r2, 0x01
sth r2, 0x0910(r1)
li r2, -0x01
stw r2, 0x0912(r1)
stw r2, 0x0f90(r4)
xoris r2, r2, 0x100
stw r2, 0x0f8c(r4)
li r2, 0x00
stw r2, 0x0f28(r4)
stw r2, 0x0f2c(r4)
lwz r2, 0x0114(r6)
lwz r4, 0x0124(r6)
lwz r5, 0x012c(r6)
lwz r29, 0x00d8(r6)
cmpwi r29, 0x00
lwz r8, 0x0210(r29)
beq RestoreKernelState_0x144
mtspr vrsave, r8
RestoreKernelState_0x144
bl PagingFlushTLB
addi r29, r1, 0x5e0
bl PagingFunc2AndAHalf
mfsprg r15, 0
lwz r8, -0x001c(r15)
li r9, 0x00
bl SchSwitchSpace
isync
mfsprg r15, 0
li r16, kSIGP7
stw r16, EWA.SIGPSelector(r15)
lhz r16, EWA.CPUIndex(r15)
stw r16, EWA.SIGPCallR4(r15)
li r8, 2 ; args in EWA
bl SIGP
mfsprg r15, 0
li r16, kSIGP17
stw r16, EWA.SIGPSelector(r15)
lhz r16, EWA.CPUIndex(r15)
stw r16, EWA.SIGPCallR4(r15)
li r8, 2 ; args in EWA
bl SIGP
li r3, 0
b Local_CommonMPCallReturnPath
; RET r8/r9
KernelStateSize
; Counter
li r24, 0
; Start with hash table
; Also inits counter r8 (bytes!)
mfsdr1 r16
rlwinm r16, r16, 16, 7, 15
cntlzw r17, r16
li r16, -1
srw r16, r16, r17
addi r8, r16, 1
addi r9, r1, KDP.SegMaps - 8
lis r31, 0 ; segment address counter
li r19, 0 ; page counter (to use later)
li r14, 0 ; entry counter (to use later)
@next_segment
lwzu r17, 8(r9)
@next_entry
lwz r18, PMDT.PBaseAndFlags(r17) ; PhysicalPage(20b) || pageAttr(12b)
lhz r15, PMDT.LBase(r17) ; LogicalPageIndexInSegment(16b)
; Same as usual: if
andi. r18, r18, PMDT.TopFieldMask ; r18 = 3b field at top of pageAttr
lhz r16, PMDT.PageCount(r17) ; PageCountMinus1(16b)
cmplwi r18, PMDT.DaddyFlag | PMDT.CountingFlag
bne @entry_seems_blank
addi r16, r16, 1
add r19, r19, r16
addi r14, r14, 1
b @continue_next_entry
@entry_seems_blank
cmpwi r15, 0 ; if not full-segment, might not be blank?
bne @continue_next_entry
cmplwi r16, 0xffff
bne @continue_next_entry
; This is the "normal" way to loop to the next segment
addis r31, r31, 0x1000
cmpwi r31, 0
bne @next_segment
b @exit
@continue_next_entry
addi r17, r17, 8
b @next_entry
@exit
slwi r19, r19, 2 ; 4 bytes per mapped page
add r8, r8, r19
cmpwi r14, 0x00 ; no entries? fail!
beq Local_ReturnInsufficientResourcesErrFromMPCall
mulli r9, r14, 12
add r8, r8, r9 ; 12 bytes per SegMap entry
add r24, r24, r9 ; also in the secondary counter?
; Count pool segments
li r9, 0 ; total size of pool segments
li r14, 0 ; count of pool segments
lwz r16, PSA.FirstPoolSeg(r1) ; current pool segment
@next_pool_segment
lwz r17, Block.OffsetToNext(r16) ; of Begin block
add r18, r17, r16
lwz r19, Block.OffsetToNext(r18) ; of End block
add r9, r9, r17
addi r9, r9, Block.kEndSize
addi r14, r14, 1
cmpwi r19, 0 ; last segment?
add r16, r19, r18
beq @exit_pool_counter
b @next_pool_segment ; odd... what happened here?
@exit_pool_counter
; Count pages in the system free list
addi r16, r1, PSA.FreeList
lwz r18, PSA.FreeList + LLL.Next(r1)
@next_page_in_freelist
cmpw r18, r16
beq @exit_freelist_counter
addi r9, r9, 16
addi r14, r14, 1
lwz r18, LLL.Next(r18)
b @next_page_in_freelist
@exit_freelist_counter
add r8, r8, r9 ; byte counter
mulli r9, r14, 12 ; 12 bytes per thing
add r8, r8, r9
add r24, r24, r9
lisori r9, 0xc000
add r8, r8, r9
lisori r9, 0x3c
add r8, r8, r9
add r24, r24, r9
srwi r9, r8, 12
slwi r9, r9, 2
addi r9, r9, 4
add r8, r8, r9
add r24, r24, r9
mr r9, r24
blr
CoherenceFunc_0x138 ; OUTSIDE REFERER
srwi r23, r28, 12
slwi r23, r23, 2
add r23, r23, r17
lwz r23, 0x0038(r23)
rlwimi r23, r28, 0, 20, 31
blr
AnotherCoherenceFunc ; OUTSIDE REFERER
cmpwi r26, 0x00
beqlr
mflr r22
addi r24, r24, -0x01
mr r28, r25
AnotherCoherenceFunc_0x14
bl CoherenceFunc_0x138
clrlwi r25, r23, 0x14
subfic r25, r25, 0x1000
cmplw r25, r26
blt AnotherCoherenceFunc_0x2c
mr r25, r26
AnotherCoherenceFunc_0x2c
mr r19, r23
mr r20, r25
addi r23, r23, -0x01
mtctr r25
AnotherCoherenceFunc_0x3c
lbzu r27, 0x0001(r24)
stbu r27, 0x0001(r23)
bdnz AnotherCoherenceFunc_0x3c
bl YetAnotherCoherenceFunc_0x64
subf r26, r25, r26
add r28, r28, r25
cmpwi r26, 0x00
bne AnotherCoherenceFunc_0x14
mtlr r22
blr
YetAnotherCoherenceFunc ; OUTSIDE REFERER
cmpwi r26, 0x00
beqlr
mr r19, r25
mr r20, r26
mflr r22
addi r25, r25, -0x01
mr r28, r24
YetAnotherCoherenceFunc_0x1c
bl CoherenceFunc_0x138
clrlwi r24, r23, 0x14
subfic r24, r24, 0x1000
cmplw r24, r26
blt YetAnotherCoherenceFunc_0x34
mr r24, r26
YetAnotherCoherenceFunc_0x34
addi r23, r23, -0x01
mtctr r24
YetAnotherCoherenceFunc_0x3c
lbzu r27, 0x0001(r23)
stbu r27, 0x0001(r25)
bdnz YetAnotherCoherenceFunc_0x3c
add r28, r28, r24
subf r26, r24, r26
cmpwi r26, 0x00
bne YetAnotherCoherenceFunc_0x1c
bl YetAnotherCoherenceFunc_0x64
mtlr r22
blr
YetAnotherCoherenceFunc_0x64 ; OUTSIDE REFERER
sync
isync
lhz r21, 0x0f4a(r1)
addi r15, r21, -0x01
add r20, r19, r20
add r20, r20, r15
neg r15, r21
and r19, r19, r15
and r20, r20, r15
YetAnotherCoherenceFunc_0x88
dcbst 0, r19
sync
icbi 0, r19
add r19, r19, r21
cmpw r19, r20
blt YetAnotherCoherenceFunc_0x88
sync
isync
blr

8
NanoKernel/NKSoftInt.s
View File

@ -113,7 +113,7 @@ KCallRunAlternateContext
@found_physical_in_cache ; can come here from below after a more thorough search
addi r8, r1, KDP.VecBaseAlternate ; the only use of this vector table?
addi r8, r1, KDP.VecTblAlternate ; the only use of this vector table?
mtsprg 3, r8
lwz r8, KDP.LA_EmulatorKernelTrapTable(r1)
@ -282,7 +282,7 @@ KCallPrioritizeInterrupts
lwz r7, CB.r7(r6)
lwz r8, EWA.r1(r1)
mfsprg r9, 3
lwz r9, VecTable.ExternalIntVector(r9)
lwz r9, VecTbl.ExternalIntVector(r9)
mtsprg 1, r8
mtlr r9
lwz r8, CB.r8(r6)
@ -359,7 +359,7 @@ IntProgram
; => Service call then return to link register
add r8, r8, r1
lwz r11, KDP.NKInfo.NanoKernelCallCounts(r8)
lwz r10, KDP.NanoKernelCallTable(r8)
lwz r10, KDP.KCallTbl(r8)
addi r11, r11, 1
stw r11, KDP.NKInfo.NanoKernelCallCounts(r8)
mtlr r10
@ -389,7 +389,7 @@ IntProgram
lwz r10, KDP.NKInfo.NanoKernelCallCounts(r8)
addi r10, r10, 1
stw r10, KDP.NKInfo.NanoKernelCallCounts(r8)
lwz r8, KDP.NanoKernelCallTable(r8)
lwz r8, KDP.KCallTbl(r8)
mtlr r8
addi r10, r10, 4 ; continue executing the next instruction
rlwimi r7, r7, 32-5, 26, 26 ; something about MSR[SE]

340
NanoKernel/NKStructs.s Normal file
View File

@ -0,0 +1,340 @@
BAT RECORD 0, INCR
U ds.l 1
L ds.l 1
ENDR
########################################################################
MemLayout RECORD 0, INCR
SegMapPtr ds.l 1
BatMap ds.l 1 ; packed array of 4-bit indices into BATs
ENDR
########################################################################
VecTbl RECORD 0, INCR
ds.l 1 ; 00 ; scratch for IVT?
SystemResetVector ds.l 1 ; 04 ; called by IVT+100 (system reset)
MachineCheckVector ds.l 1 ; 08 ; called by IVT+200 (machine check)
DSIVector ds.l 1 ; 0c ; called by IVT+300 (DSI)
ISIVector ds.l 1 ; 10 ; called by IVT+400 (ISI)
ExternalIntVector ds.l 1 ; 14 ; called by IVT+500 (external interrupt)
AlignmentIntVector ds.l 1 ; 18 ; called by IVT+600 (alignment)
ProgramIntVector ds.l 1 ; 1c ; called by IVT+700 (program)
FPUnavailVector ds.l 1 ; 20 ; called by IVT+KDP.BATs + 0xa0 (FP unavail)
DecrementerVector ds.l 1 ; 24 ; called by IVT+900 (decrementer)
ReservedVector1 ds.l 1 ; 28 ; called by IVT+a00 (reserved)
ReservedVector2 ds.l 1 ; 2c ; called by IVT+b00 (reserved)
SyscallVector ds.l 1 ; 30 ; called by IVT+c00 (system call)
TraceVector ds.l 1 ; 34 ; called by IVT+d00 (trace)
FPAssistVector ds.l 1 ; 38 ; called by IVT+e00 (FP assist)
PerfMonitorVector ds.l 1 ; 3c ; called by IVT+f00 (perf monitor)
ds.l 1 ; 40 ;
ds.l 1 ; 44 ;
ds.l 1 ; 48 ;
ds.l 1 ; 4c ; Vectors from here downwards are called from
ds.l 1 ; 50 ; odd places in the IVT????
ds.l 1 ; 54 ;
ds.l 1 ; 58 ; seems AltiVec-related
ThermalEventVector ds.l 1 ; 5c ;
ds.l 1 ; 60 ;
ds.l 1 ; 64 ;
ds.l 1 ; 68 ;
ds.l 1 ; 6c ;
ds.l 1 ; 70 ;
ds.l 1 ; 74 ;
ds.l 1 ; 78 ;
ds.l 1 ; 7c ;
ds.l 1 ; 80 ; shares with TraceVector in Y and G
ds.l 1 ; 84 ;
ds.l 1 ; 88 ;
ds.l 1 ; 8c ;
ds.l 1 ; 90 ;
ds.l 1 ; 94 ;
ds.l 1 ; 98 ;
ds.l 1 ; 9c ;
ds.l 1 ; a0 ;
ds.l 1 ; a4 ;
ds.l 1 ; a8 ;
ds.l 1 ; ac ;
ds.l 1 ; b0 ;
ds.l 1 ; b4 ;
ds.l 1 ; b8 ;
ds.l 1 ; bc ; called by IVT+0 (reserved)
Size equ *
ENDR
########################################################################
KCallTbl RECORD 0, INCR
ReturnFromException ds.l 1 ; 00, trap 0
RunAlternateContext ds.l 1 ; 04, trap 1
ResetSystem ds.l 1 ; 08, trap 2 ; 68k RESET
VMDispatch ds.l 1 ; 0c, trap 3 ; 68k $FE0A
PrioritizeInterrupts ds.l 1 ; 10, trap 4
PowerDispatch ds.l 1 ; 14, trap 5 ; 68k $FEOF
RTASDispatch ds.l 1 ; 18, trap 6
CacheDispatch ds.l 1 ; 1c, trap 7
MPDispatch ds.l 1 ; 20, trap 8
ds.l 1 ; 24, trap 9
ds.l 1 ; 28, trap 10
ds.l 1 ; 2c, trap 11
CallAdapterProcPPC ds.l 1 ; 30, trap 12
ds.l 1 ; 34, trap 13
CallAdapterProc68k ds.l 1 ; 38, trap 14
SystemCrash ds.l 1 ; 3c, trap 15
Size equ *
ENDR
########################################################################
PME RECORD 0, INCR ; PageMap Entry
LBase ds.w 1 ; 0 ; (base - segment) >> 12
PageCount ds.w 1 ; 2 ; page count MINUS ONE
PBaseAndFlags ds.l 1 ; 4 ; PBase page aligned
PBaseBits equ 20
FirstFlagBit equ 20
FirstFlag equ 0x800
DaddyFlag equ 0x800
CountingFlag equ 0x400
PhysicalIsRelativeFlag equ 0x200
; try not to use the equates above; they are dicey
TopFieldMask equ 0xe00
Size equ *
ENDR
########################################################################
KDP RECORD 0x80, INCR
r0 ds.l 1 ; 000 ; used for quick register saves at interrupt time
r1 ds.l 1 ; 004
r2 ds.l 1 ; 008
r3 ds.l 1 ; 00c
r4 ds.l 1 ; 010
r5 ds.l 1 ; 014
r6 ds.l 1 ; 018
r7 ds.l 1 ; 01c
r8 ds.l 1 ; 020
r9 ds.l 1 ; 024
r10 ds.l 1 ; 028
r11 ds.l 1 ; 02c
r12 ds.l 1 ; 030
r13 ds.l 1 ; 034
r14 ds.l 1 ; 038
r15 ds.l 1 ; 03c
r16 ds.l 1 ; 040
r17 ds.l 1 ; 044
r18 ds.l 1 ; 048
r19 ds.l 1 ; 04c
r20 ds.l 1 ; 050
r21 ds.l 1 ; 054
r22 ds.l 1 ; 058
r23 ds.l 1 ; 05c
r24 ds.l 1 ; 060
r25 ds.l 1 ; 064
r26 ds.l 1 ; 068
r27 ds.l 1 ; 06c
r28 ds.l 1 ; 070
r29 ds.l 1 ; 074
r30 ds.l 1 ; 078
r31 ds.l 1 ; 07c
SegMaps
SegMap32SupInit ds.l 32 ; 080:100
SegMap32UsrInit ds.l 32 ; 100:180
SegMap32CPUInit ds.l 32 ; 180:200
SegMap32OvlInit ds.l 32 ; 200:280
BATs ds.l 32 ; 280:300
CurIBAT0 ds BAT ; 300:308
CurIBAT1 ds BAT ; 308:310
CurIBAT2 ds BAT ; 310:318
CurIBAT3 ds BAT ; 318:320
CurDBAT0 ds BAT ; 320:328
CurDBAT1 ds BAT ; 328:330
CurDBAT2 ds BAT ; 330:338
CurDBAT3 ds BAT ; 338:340
NCBPointerCache
NCBCacheLA0 ds.l 1 ; 340
NCBCachePA0 ds.l 1 ; 344
NCBCacheLA1 ds.l 1 ; 348
NCBCachePA1 ds.l 1 ; 34c
NCBCacheLA2 ds.l 1 ; 350
NCBCachePA2 ds.l 1 ; 354
NCBCacheLA3 ds.l 1 ; 358
NCBCachePA3 ds.l 1 ; 35c
NCBPointerCacheEnd
VecTblSystem ds VecTbl ; 360:420 ; when 68k emulator is running, *or* any MTask
VecTblAlternate ds VecTbl ; 420:4e0 ; native PowerPC in blue task
VecTblMemRetry ds VecTbl ; 4e0:5a0 ; "FDP" instruction emulation
FloatEmScratch ds.d 1 ; 5a0:5a8
TopOfFreePages ds.l 1 ; 5a8 ; gotten from the old SPRG0
ds.l 1 ; 5ac
PARPerSegmentPLEPtrs ds.l 4 ; 5b0:5c0 ; for each PAR segment, a ptr into the PAR PageList
FloatingPtTemp1 ds.l 1 ; 5c0
FloatingPtTemp2 ds.l 1 ; 5c4
SupervisorMemLayout ds MemLayout ; 5c8:5d0
UserMemLayout ds MemLayout ; 5d0:5d8
CpuMemLayout ds MemLayout ; 5d8:5e0
OverlayMemLayout ds MemLayout ; 5e0:5e8
CurrentMemLayout ds MemLayout ; 5e8:5f0
KCallTbl ds KCallTbl ; 5f0:630
PA_ConfigInfo ds.l 1 ; 630
PA_EmulatorData ds.l 1 ; 634
KernelMemoryBase ds.l 1 ; 638
KernelMemoryEnd ds.l 1 ; 63c ; Top of HTAB (and entire kernel reserved area). Set by Init.s
PA_RelocatedLowMemInit ds.l 1 ; 640 ; From ConfigInfo. Ptr to Mac LowMem vars, which Init.s sets up
SharedMemoryAddr ds.l 1 ; 644 ; From ConfigInfo. Not sure what latest use is.
LA_EmulatorKernelTrapTable ds.l 1 ; 648 ; Calculated from ConfigInfo.
PA_NanoKernelCode ds.l 1 ; 64c ; Calculated by NanoKernel itself.
PA_FDP ds.l 1 ; 650 ; See notes in NanoKernel. Very interesting.
LA_ECB ds.l 1 ; 654 ; Logical ptr into EDP.
PA_ECB ds.l 1 ; 658 ; gets called "system context"
PA_ContextBlock ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2
Flags ds.l 1 ; 660 ; moved to EWA (per-CPU) in NKv2
Enables ds.l 1 ; 664 ; moved to EWA (per-CPU) in NKv2
OtherContextDEC ds.l 1 ; 668 ; ticks the *inactive* context has left out of 1s
PA_PageMapEnd ds.l 1 ; 66c ; Set at the same time as PA_PageMapStart below...
TestIntMaskInit ds.l 1 ; 670 ; These are all copied from ConfigInfo...
PostIntMaskInit ds.l 1 ; 674
ClearIntMaskInit ds.l 1 ; 678
PA_EmulatorIplValue ds.l 1 ; 67c ; Physical ptr into EDP
DebugIntPtr ds.l 1 ; 680 ; Within (debug?) shared memory
PA_PageMapStart ds.l 1 ; 684 ; Physical ptr to PageMap (= KDP+0x920)
PageAttributeInit ds.l 1 ; 688 ; defaults for page table entries (see ConfigInfo)
HtabTempPage ds.l 1 ; 68c
HtabTempEntryPtr ds.l 1 ; 690
NewestPageInHtab ds.l 1 ; 694
ApproxCurrentPTEG ds.l 1 ; 698
OverflowingPTEG ds.l 1 ; 69c
PTEGMask ds.l 1 ; 6a0
HTABORG ds.l 1 ; 6a4
VMLogicalPages ds.l 1 ; 6a8 ; set at init and changed by VMInit
TotalPhysicalPages ds.l 1 ; 6ac ; does not take into acct maximum MacOS memory
PARPageListPtr ds.l 1 ; 6b0 ; VM puts this in system heap
VMMaxVirtualPages ds.l 1 ; 6b4 ; always 5fffe000, even with VM on
org 0x700
CrashTop
CrashR0 ds.l 1 ; 700
CrashR1 ds.l 1 ; 704
CrashR2 ds.l 1 ; 708
CrashR3 ds.l 1 ; 70c
CrashR4 ds.l 1 ; 710
CrashR5 ds.l 1 ; 714
CrashR6 ds.l 1 ; 718
CrashR7 ds.l 1 ; 71c
CrashR8 ds.l 1 ; 720
CrashR9 ds.l 1 ; 724
CrashR10 ds.l 1 ; 728
CrashR11 ds.l 1 ; 72c
CrashR12 ds.l 1 ; 730
CrashR13 ds.l 1 ; 734
CrashR14 ds.l 1 ; 738
CrashR15 ds.l 1 ; 73c
CrashR16 ds.l 1 ; 740
CrashR17 ds.l 1 ; 744
CrashR18 ds.l 1 ; 748
CrashR19 ds.l 1 ; 74c
CrashR20 ds.l 1 ; 750
CrashR21 ds.l 1 ; 754
CrashR22 ds.l 1 ; 758
CrashR23 ds.l 1 ; 75c
CrashR24 ds.l 1 ; 760
CrashR25 ds.l 1 ; 764
CrashR26 ds.l 1 ; 768
CrashR27 ds.l 1 ; 76c
CrashR28 ds.l 1 ; 770
CrashR29 ds.l 1 ; 774
CrashR30 ds.l 1 ; 778
CrashR31 ds.l 1 ; 77c
CrashCR ds.l 1 ; 780
CrashMQ ds.l 1 ; 784
CrashXER ds.l 1 ; 788
CrashLR ds.l 1 ; 78c
CrashCTR ds.l 1 ; 790
CrashPVR ds.l 1 ; 794
CrashDSISR ds.l 1 ; 798
CrashDAR ds.l 1 ; 79c
CrashRTCU ds.l 1 ; 7a0
CrashRTCL ds.l 1 ; 7a4
CrashDEC ds.l 1 ; 7a8
CrashHID0 ds.l 1 ; 7ac
CrashSDR1 ds.l 1 ; 7b0
CrashSRR0 ds.l 1 ; 7b4
CrashSRR1 ds.l 1 ; 7b8
CrashMSR ds.l 1 ; 7bc
CrashSR0 ds.l 1 ; 7c0
CrashSR1 ds.l 1 ; 7c4
CrashSR2 ds.l 1 ; 7c8
CrashSR3 ds.l 1 ; 7cc
CrashSR4 ds.l 1 ; 7d0
CrashSR5 ds.l 1 ; 7d4
CrashSR6 ds.l 1 ; 7d8
CrashSR7 ds.l 1 ; 7dc
CrashSR8 ds.l 1 ; 7e0
CrashSR9 ds.l 1 ; 7e4
CrashSR10 ds.l 1 ; 7e8
CrashSR11 ds.l 1 ; 7ec
CrashSR12 ds.l 1 ; 7f0
CrashSR13 ds.l 1 ; 7f4
CrashSR14 ds.l 1 ; 7f8
CrashSR15 ds.l 1 ; 7fc
CrashF0 ds.d 1 ; 800
CrashF1 ds.d 1 ; 808
CrashF2 ds.d 1 ; 810
CrashF3 ds.d 1 ; 818
CrashF4 ds.d 1 ; 820
CrashF5 ds.d 1 ; 828
CrashF6 ds.d 1 ; 830
CrashF7 ds.d 1 ; 838
CrashF8 ds.d 1 ; 840
CrashF9 ds.d 1 ; 848
CrashF10 ds.d 1 ; 850
CrashF11 ds.d 1 ; 858
CrashF12 ds.d 1 ; 860
CrashF13 ds.d 1 ; 868
CrashF14 ds.d 1 ; 870
CrashF15 ds.d 1 ; 878
CrashF16 ds.d 1 ; 880
CrashF17 ds.d 1 ; 888
CrashF18 ds.d 1 ; 890
CrashF19 ds.d 1 ; 898
CrashF20 ds.d 1 ; 8a0
CrashF21 ds.d 1 ; 8a8
CrashF22 ds.d 1 ; 8b0
CrashF23 ds.d 1 ; 8b8
CrashF24 ds.d 1 ; 8c0
CrashF25 ds.d 1 ; 8c8
CrashF26 ds.d 1 ; 8d0
CrashF27 ds.d 1 ; 8d8
CrashF28 ds.d 1 ; 8e0
CrashF29 ds.d 1 ; 8e8
CrashF30 ds.d 1 ; 8f0
CrashF31 ds.d 1 ; 8f8
CrashFPSCR ds.l 1 ; 900
CrashKernReturn ds.l 1 ; 904
CrashUnknown ds.l 1 ; 908
CrashBtm
org 0xCC0
SysInfo ds NKSystemInfo ; cc0:d80
DiagInfo ds NKDiagInfo ; d80:e80
NKInfo ds NKNanoKernelInfo ; e80:f80
ProcInfo ds NKProcessorInfo ; f80:fc0
InfoRecBlk ds.b 64 ; fc0:1000 ; Access using ptr equates in InfoRecords
ENDR

3114
NanoKernel/NKSync.s
View File

File diff suppressed because it is too large Load Diff

145
NanoKernel/NKSystemCrash.s
View File

@ -1,132 +1,133 @@
SystemCrash
mfsprg r1, 0
stw r0, KDP.ThudSavedR0(r1)
stw r0, KDP.CrashR0(r1)
mfsprg r0, 1
stw r0, KDP.ThudSavedR1(r1)
stw r0, KDP.CrashR1(r1)
stmw r2, KDP.ThudSavedR2(r1)
stmw r2, KDP.CrashR2(r1)
mfcr r0
stw r0, KDP.ThudSavedCR(r1)
stw r0, KDP.CrashCR(r1)
mfspr r0, mq
stw r0, KDP.ThudSavedMQ(r1)
stw r0, KDP.CrashMQ(r1)
mfxer r0
stw r0, KDP.ThudSavedXER(r1)
stw r0, KDP.CrashXER(r1)
mfsprg r0, 2
stw r0, KDP.ThudSavedSPRG2(r1)
stw r0, KDP.CrashLR(r1)
mfctr r0
stw r0, KDP.ThudSavedCTR(r1)
stw r0, KDP.CrashCTR(r1)
mfspr r0, pvr
stw r0, KDP.ThudSavedPVR(r1)
stw r0, KDP.CrashPVR(r1)
mfspr r0, dsisr
stw r0, KDP.ThudSavedDSISR(r1)
stw r0, KDP.CrashDSISR(r1)
mfspr r0, dar
stw r0, KDP.ThudSavedDAR(r1)
stw r0, KDP.CrashDAR(r1)
mfspr r0, tbu
stw r0, KDP.ThudSavedTBU(r1)
stw r0, KDP.CrashTBU(r1)
mfspr r0, tb
stw r0, KDP.ThudSavedTB(r1)
stw r0, KDP.CrashTB(r1)
mfspr r0, dec
stw r0, KDP.ThudSavedDEC(r1)
stw r0, KDP.CrashDEC(r1)
mfspr r0, hid0
stw r0, KDP.ThudSavedHID0(r1)
stw r0, KDP.CrashHID0(r1)
mfspr r0, sdr1
stw r0, KDP.ThudSavedSDR1(r1)
stw r0, KDP.CrashSDR1(r1)
mfsrr0 r0
stw r0, KDP.ThudSavedSRR0(r1)
stw r0, KDP.CrashSRR0(r1)
mfsrr1 r0
stw r0, KDP.ThudSavedSRR1(r1)
stw r0, KDP.CrashSRR1(r1)
mfmsr r0
stw r0, KDP.ThudSavedMSR(r1)
stw r0, KDP.CrashMSR(r1)
mfsr r0, 0
stw r0, KDP.ThudSavedSR0(r1)
stw r0, KDP.CrashSR0(r1)
mfsr r0, 1
stw r0, KDP.ThudSavedSR1(r1)
stw r0, KDP.CrashSR1(r1)
mfsr r0, 2
stw r0, KDP.ThudSavedSR2(r1)
stw r0, KDP.CrashSR2(r1)
mfsr r0, 3
stw r0, KDP.ThudSavedSR3(r1)
stw r0, KDP.CrashSR3(r1)
mfsr r0, 4
stw r0, KDP.ThudSavedSR4(r1)
stw r0, KDP.CrashSR4(r1)
mfsr r0, 5
stw r0, KDP.ThudSavedSR5(r1)
stw r0, KDP.CrashSR5(r1)
mfsr r0, 6
stw r0, KDP.ThudSavedSR6(r1)
stw r0, KDP.CrashSR6(r1)
mfsr r0, 7
stw r0, KDP.ThudSavedSR7(r1)
stw r0, KDP.CrashSR7(r1)
mfsr r0, 8
stw r0, KDP.ThudSavedSR8(r1)
stw r0, KDP.CrashSR8(r1)
mfsr r0, 9
stw r0, KDP.ThudSavedSR9(r1)
stw r0, KDP.CrashSR9(r1)
mfsr r0, 10
stw r0, KDP.ThudSavedSR10(r1)
stw r0, KDP.CrashSR10(r1)
mfsr r0, 11
stw r0, KDP.ThudSavedSR11(r1)
stw r0, KDP.CrashSR11(r1)
mfsr r0, 12
stw r0, KDP.ThudSavedSR12(r1)
stw r0, KDP.CrashSR12(r1)
mfsr r0, 13
stw r0, KDP.ThudSavedSR13(r1)
stw r0, KDP.CrashSR13(r1)
mfsr r0, 14
stw r0, KDP.ThudSavedSR14(r1)
stw r0, KDP.CrashSR14(r1)
mfsr r0, 15
stw r0, KDP.ThudSavedSR15(r1)
stw r0, KDP.CrashSR15(r1)
mfmsr r0
_bset r0, r0, bitMsrFP
mtmsr r0
stfd f0, KDP.ThudSavedF0(r1)
stfd f1, KDP.ThudSavedF1(r1)
stfd f2, KDP.ThudSavedF2(r1)
stfd f3, KDP.ThudSavedF3(r1)
stfd f4, KDP.ThudSavedF4(r1)
stfd f5, KDP.ThudSavedF5(r1)
stfd f6, KDP.ThudSavedF6(r1)
stfd f7, KDP.ThudSavedF7(r1)
stfd f8, KDP.ThudSavedF8(r1)
stfd f9, KDP.ThudSavedF9(r1)
stfd f10, KDP.ThudSavedF10(r1)
stfd f11, KDP.ThudSavedF11(r1)
stfd f12, KDP.ThudSavedF12(r1)
stfd f13, KDP.ThudSavedF13(r1)
stfd f14, KDP.ThudSavedF14(r1)
stfd f15, KDP.ThudSavedF15(r1)
stfd f16, KDP.ThudSavedF16(r1)
stfd f17, KDP.ThudSavedF17(r1)
stfd f18, KDP.ThudSavedF18(r1)
stfd f19, KDP.ThudSavedF19(r1)
stfd f20, KDP.ThudSavedF20(r1)
stfd f21, KDP.ThudSavedF21(r1)
stfd f22, KDP.ThudSavedF22(r1)
stfd f23, KDP.ThudSavedF23(r1)
stfd f24, KDP.ThudSavedF24(r1)
stfd f25, KDP.ThudSavedF25(r1)
stfd f26, KDP.ThudSavedF26(r1)
stfd f27, KDP.ThudSavedF27(r1)
stfd f28, KDP.ThudSavedF28(r1)
stfd f29, KDP.ThudSavedF29(r1)
stfd f30, KDP.ThudSavedF30(r1)
stfd f31, KDP.ThudSavedF31(r1)
stfd f0, KDP.CrashF0(r1)
stfd f1, KDP.CrashF1(r1)
stfd f2, KDP.CrashF2(r1)
stfd f3, KDP.CrashF3(r1)
stfd f4, KDP.CrashF4(r1)
stfd f5, KDP.CrashF5(r1)
stfd f6, KDP.CrashF6(r1)
stfd f7, KDP.CrashF7(r1)
stfd f8, KDP.CrashF8(r1)
stfd f9, KDP.CrashF9(r1)
stfd f10, KDP.CrashF10(r1)
stfd f11, KDP.CrashF11(r1)
stfd f12, KDP.CrashF12(r1)
stfd f13, KDP.CrashF13(r1)
stfd f14, KDP.CrashF14(r1)
stfd f15, KDP.CrashF15(r1)
stfd f16, KDP.CrashF16(r1)
stfd f17, KDP.CrashF17(r1)
stfd f18, KDP.CrashF18(r1)
stfd f19, KDP.CrashF19(r1)
stfd f20, KDP.CrashF20(r1)
stfd f21, KDP.CrashF21(r1)
stfd f22, KDP.CrashF22(r1)
stfd f23, KDP.CrashF23(r1)
stfd f24, KDP.CrashF24(r1)
stfd f25, KDP.CrashF25(r1)
stfd f26, KDP.CrashF26(r1)
stfd f27, KDP.CrashF27(r1)
stfd f28, KDP.CrashF28(r1)
stfd f29, KDP.CrashF29(r1)
stfd f30, KDP.CrashF30(r1)
stfd f31, KDP.CrashF31(r1)
mffs f31
lwz r0, KDP.ThudSavedF31+4(r1)
stfd f31, KDP.ThudSavedF31+4(r1)
stw r0, KDP.ThudSavedF31+4(r1)
lwz r0, KDP.CrashF31+4(r1)
stfd f31, KDP.CrashF31+4(r1)
stw r0, KDP.CrashF31+4(r1)
mfspr r0, lr
stw r0, KDP.ThudSavedLR(r1)
mflr r0
stw r0, KDP.CrashKernReturn(r1)
########################################################################

1564
NanoKernel/NKTasks.s
View File

File diff suppressed because it is too large Load Diff

1256
NanoKernel/NKThud.s
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File diff suppressed because it is too large Load Diff

962
NanoKernel/NKTimers.s
View File

@ -1,962 +0,0 @@
; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKConsoleLog
; getchar
; printb
; printd
; printh
; printw
; NKIndex
; DeleteID
; LookupID
; NKPoolAllocator
; PoolAllocClear
; PoolFree
; NKScheduler
; CalculateTimeslice
; FlagSchEvaluationIfTaskRequires
; SchRdyTaskNow
; SchTaskUnrdy
; clear_cr0_lt
; major_0x149d4
; NKSync
; EnqueueMessage
; SetEvent
; SignalSemaphore
; NKThud
; panic
; panic_non_interactive
; EXPORTS:
; DequeueTimer (=> NKMPCalls, NKPrimaryIntHandlers, NKSync, NKTasks)
; EnqueueTimer (=> NKMPCalls, NKSync)
; GetTime (=> NKMPCalls, NKScheduler, NKSync, NKTasks)
; InitTMRQs (=> NKInit)
; SetTimesliceFromCurTime (=> NKScheduler)
; StartTimeslicing (=> NKInit)
; TimebaseTicksPerPeriod (=> NKScheduler, NKSync)
; TimerDispatch (=> NKIntHandlers)
Local_Panic set *
b panic
InitTMRQs ; OUTSIDE REFERER
addi r9, r1, PSA.TimerQueue
lis r8, 0x544d
ori r8, r8, 0x5251
stw r8, 0x0004(r9)
stw r9, 0x0008(r9)
stw r9, 0x000c(r9)
li r8, 0x00
stb r8, 0x0014(r9)
li r8, 0x01
stb r8, 0x0016(r9)
stb r8, 0x0017(r9)
lis r8, 0x7fff
ori r8, r8, 0xffff
mtspr dec, r8
stw r8, 0x0038(r9)
oris r8, r8, 0xffff
stw r8, 0x003c(r9)
mfspr r8, pvr
rlwinm. r8, r8, 0, 0, 14
beq InitTMRQs_0x7c
mflr r30
li r8, 0x40
; r1 = kdp
; r8 = size
bl PoolAllocClear
; r8 = ptr
mr. r31, r8
beq Local_Panic
stw r31, PSA.OtherTimerQueuePtr(r1)
li r9, 0x07
stb r9, 0x0014(r31)
li r9, 0x01
stb r9, 0x0016(r31)
mtlr r30
InitTMRQs_0x7c
mfspr r8, pvr
rlwinm. r8, r8, 0, 0, 14
beq InitTMRQs_0xb4
mflr r30
li r8, 0x40
; r1 = kdp
; r8 = size
bl PoolAllocClear
; r8 = ptr
mr. r31, r8
beq Local_Panic
stw r31, PSA._364(r1)
li r9, 0x08
stb r9, 0x0014(r31)
li r9, 0x01
stb r9, 0x0016(r31)
mtlr r30
InitTMRQs_0xb4
; Activate the NanoDebugger (whatever that is...)
lwz r30, KDP.PA_ConfigInfo(r1)
lhz r31, NKConfigurationInfo.Debug(r30)
cmplwi r31, NKConfigurationInfo.DebugThreshold
blt @nodebug
lwz r31, NKConfigurationInfo.DebugFlags(r30)
rlwinm. r8, r31, 0, NKConfigurationInfo.NanodbgrFlagBit, NKConfigurationInfo.NanodbgrFlagBit
beq @nodebug
lwz r8, KDP.NKInfo.ConfigFlags(r1)
_bset r8, r8, NKNanoKernelInfo.NanodbgrFlagBit
stw r8, KDP.NKInfo.ConfigFlags(r1)
mflr r30
li r8, Timer.Size
bl PoolAllocClear ; one of those weird queue structures
mr. r31, r8
beq Local_Panic
li r9, Timer.kKind6
stb r9, Timer.Kind(r31)
li r9, 1
stb r9, Timer.KeepAfterFiring(r31)
bl GetTime
stw r8, Timer.Time(r31)
stw r9, Timer.Time+4(r31)
mr r8, r31
bl EnqueueTimer
_log 'Nanodebugger activated.^n'
mtlr r30
@nodebug
blr
TimerTable
dc.l TimerFireUnknownKind - NKTop ; Timer.kKind0
dc.l TimerFire1 - NKTop ; Timer.kKind1
dc.l TimerFire2 - NKTop ; Timer.kKind2
dc.l TimerFire3 - NKTop ; Timer.kKind3
dc.l TimerFire4 - NKTop ; Timer.kKind4
dc.l TimerFire5 - NKTop ; Timer.kKind5
dc.l TimerFire6 - NKTop ; Timer.kKind6
dc.l TimerFire7 - NKTop ; Timer.kKind7
dc.l TimerFire8 - NKTop ; Timer.kKind8
TimerDispatch ; OUTSIDE REFERER
mflr r19
mfsprg r18, 0
stw r19, EWA.TimerDispatchLR(r18)
TimerDispatch_0x30 ; OUTSIDE REFERER
mfspr r8, pvr
rlwinm. r8, r8, 0, 0, 14
beq @is_601
;not 601
@gettime_loop_non_601
mftbu r8
mftb r9
mftbu r16
cmpw r8, r16
bne- @gettime_loop_non_601
b @common
@is_601
@gettime_loop_601
mfspr r8, rtcu
mfspr r9, rtcl
mfspr r16, rtcu
cmpw r8, r16
bne- @gettime_loop_601
dialect POWER
liu r16, 1000000000 >> 16
oril r16, r16, 1000000000 & 0xffff
mfmq r17
mul r8, r16, r8
mfmq r16
mtmq r17
mfxer r17
a r9, r16, r9
aze r8, r8
mtxer r17
dialect PowerPC
@common
lbz r19, EWA.GlobalTimeIsValid(r18)
addi r30, r18, EWA.Base
cmpwi r19, 1
lwz r16, EWA.GlobalTime - EWA.Base(r30)
bne timer_earlier_than_sometime
lwz r17, EWA.GlobalTime + 4 - EWA.Base(r30)
_b_if_time_gt r16, r8, timer_earlier_than_sometime
@skipbranch
li r19, 0x00
stw r30, -0x0254(r18)
stb r19, 0x0017(r30)
b TimerFire4_0x10
timer_earlier_than_sometime
lwz r30, PSA.TimerQueue + LLL.Next(r1)
lwz r16, 0x0038(r30)
lwz r17, 0x003c(r30)
_b_if_time_gt r16, r8, TimerDispatch_0x188
RemoveFromList r30, scratch1=r19, scratch2=r20
lwz r19, 0x064c(r1)
lbz r20, Timer.Kind(r30)
rlwimi r19, r20, 2, 23, 29
cmplwi r20, 0x09
llabel r20, TimerTable
li r21, 0x00
add r20, r20, r19
bgel Local_Panic
stb r21, 0x0017(r30)
lwz r20, 0x0000(r20)
add r20, r20, r19
mtlr r20
stw r30, -0x0254(r18)
blr
TimerDispatch_0x144
mfsprg r18, 0
lwz r30, -0x0254(r18)
lbz r19, 0x0016(r30)
cmpwi r19, 0x01
lwz r8, 0x0000(r30)
beq TimerDispatch_0x30
bl DeleteID
mr r8, r30
bl PoolFree
lwz r8, 0x001c(r30)
cmpwi r8, 0x00
beq TimerDispatch_0x180
bl PoolFree
li r8, 0x00
stw r8, 0x001c(r30)
TimerDispatch_0x180:
mfsprg r18, 0
b TimerDispatch_0x30
TimerDispatch_0x188
lwz r19, EWA.TimerDispatchLR(r18)
mtlr r19
b SetTimesliceFromCurTimeAndTripTime
StartTimeslicing ; OUTSIDE REFERER
mfsprg r19, 0
li r8, 1
stb r8, EWA.GlobalTimeIsValid(r19)
li r8, 0
stw r8, EWA.GlobalTime(r19)
stw r8, EWA.GlobalTime + 4(r19)
mflr r19
_log 'Starting timeslicing^n'
mtlr r19
; CLOB r8/r9, r16-r21
SetTimeslice
mflr r19
bl GetTime
mtlr r19
; ARG TimeBase r8/r9 curTime
; CLOB r16-r21
SetTimesliceFromCurTime
; This should get the most distant time???
lwz r18, PSA.TimerQueue + LLL.Next(r1)
lwz r16, Timer.Time(r18)
lwz r17, Timer.Time+4(r18)
; ARG TimeBase r8/r9 curTime, TimeBase r16/r17 TripTime
; CLOB r18-r21
SetTimesliceFromCurTimeAndTripTime
mfxer r20
mfsprg r19, 0
lis r21, 0x7fff
lbz r18, EWA.GlobalTimeIsValid(r19)
ori r21, r21, 0xffff
cmpwi r18, 1
; r16/r17 = soonest(last timer, global PSA time if available)
bne global_time_invalid
lwz r18, EWA.GlobalTime(r19)
lwz r19, EWA.GlobalTime+4(r19)
_b_if_time_le r16, r18, last_timer_fires_sooner
mr r17, r19
mr r16, r18
last_timer_fires_sooner
global_time_invalid
; Subtract the current time (or what we were passed in r8/r9) from that time
subfc r17, r9, r17
subfe. r16, r8, r16
mtxer r20
blt @that_time_has_passed ; hi bit of r16 = 1
bne @that_time_is_in_future ;
cmplw r16, r21 ; typo? should be r17???
bgt @that_time_is_in_future ; will never be taken...
; When the times are roughly equal?
mtspr dec, r17
blr
@that_time_is_in_future
mtspr dec, r21
blr
@that_time_has_passed
mtspr dec, r21
mtspr dec, r16 ; this makes nearly no sense!
blr
; TimerFire0
TimerFireUnknownKind
_log 'TimerInformation.kind is zero??^n'
; TimerFire1
TimerFire1 ; OUTSIDE REFERER
bl Local_Panic
lwz r18, 0x0018(r30)
stw r16, 0x0080(r18)
stw r17, 0x0084(r18)
lwz r8, 0x0018(r30)
li r16, 0x00
lbz r17, 0x0018(r8)
lwz r19, 0x0088(r8)
cmpwi r17, 0x00
stw r16, 0x011c(r19)
bne TimerFire1_0x64
addi r16, r8, 0x08
RemoveFromList r16, scratch1=r17, scratch2=r19
li r17, 0x01
stb r17, 0x0019(r8)
bl SchRdyTaskNow
bl CalculateTimeslice
bl FlagSchEvaluationIfTaskRequires
b TimerDispatch_0x144
TimerFire1_0x64
lwz r16, 0x0064(r8)
rlwinm. r16, r16, 0, 30, 30
; TimerFire2
TimerFire2 ; OUTSIDE REFERER
bne TimerDispatch_0x144
bl Local_Panic
lwz r18, 0x0018(r30)
stw r16, 0x0080(r18)
stw r17, 0x0084(r18)
lwz r8, 0x0018(r30)
li r16, -0x7270
lbz r17, 0x0018(r8)
lwz r18, 0x0088(r8)
cmpwi r17, 0x00
bne TimerFire3_0x8
stw r16, 0x011c(r18)
lwz r8, 0x0008(r8)
lwz r8, 0x0000(r8)
; r8 = id
bl LookupID
cmpwi r9, Queue.kIDClass
cmpwi cr1, r9, 0x05
beq TimerFire2_0x8c
beq cr1, TimerFire2_0x7c
cmpwi r9, 0x09
cmpwi cr1, r9, 0x06
beq TimerFire2_0x6c
bne cr1, Local_Panic
lwz r16, 0x0020(r8)
addi r16, r16, -0x01
stw r16, 0x0020(r8)
b TimerFire2_0x98
TimerFire2_0x6c
lwz r16, 0x001c(r8)
addi r16, r16, -0x01
stw r16, 0x001c(r8)
b TimerFire2_0x98
TimerFire2_0x7c
lwz r16, 0x001c(r8)
addi r16, r16, -0x01
stw r16, 0x001c(r8)
b TimerFire2_0x98
TimerFire2_0x8c
lwz r16, 0x002c(r8)
addi r16, r16, -0x01
stw r16, 0x002c(r8)
TimerFire2_0x98
lwz r8, 0x0018(r30)
addi r16, r8, 0x08
RemoveFromList r16, scratch1=r17, scratch2=r18
bl SchRdyTaskNow
; TimerFire3
TimerFire3 ; OUTSIDE REFERER
bl FlagSchEvaluationIfTaskRequires
b TimerDispatch_0x144
TimerFire3_0x8 ; OUTSIDE REFERER
b Local_Panic
; major_0x13258
; Dead code -- probably removed from TimerTable
lwz r8, 0x0018(r30)
; r8 = id
bl LookupID
cmpwi r9, Queue.kIDClass
mr r31, r8
bne major_0x13258_0x68
lwz r16, 0x0024(r31)
lwz r8, 0x001c(r30)
cmpwi r16, 0x00
cmpwi cr1, r8, 0x00
beq major_0x13258_0x40
lwz r17, 0x0028(r31)
mr. r8, r17
lwz r17, 0x0008(r17)
beq major_0x13258_0x68
stw r17, 0x0028(r31)
b major_0x13258_0x4c
major_0x13258_0x40
beq cr1, major_0x13258_0x68
li r16, 0x00
stw r16, 0x001c(r30)
major_0x13258_0x4c
lwz r16, 0x0020(r30)
lwz r17, 0x0024(r30)
lwz r18, 0x0028(r30)
stw r16, 0x0010(r8)
stw r17, 0x0014(r8)
stw r18, 0x0018(r8)
bl EnqueueMessage ; Message *r8, Queue *r31
major_0x13258_0x68
lwz r8, 0x0034(r30)
; r8 = id
bl LookupID
cmpwi r9, Semaphore.kIDClass
mr r31, r8
bne major_0x13258_0x80
bl SignalSemaphore
major_0x13258_0x80
lwz r8, 0x002c(r30)
; r8 = id
bl LookupID
cmpwi r9, EventGroup.kIDClass
mr r31, r8
; TimerFire4
TimerFire4 ; OUTSIDE REFERER
bne TimerFire4_0xc
lwz r8, 0x0030(r30)
bl SetEvent
TimerFire4_0xc
b TimerDispatch_0x144
TimerFire4_0x10 ; OUTSIDE REFERER
mfsprg r28, 0
lwz r29, -0x0008(r28)
mr r8, r29
bl SchTaskUnrdy
lbz r17, 0x0019(r29)
cmpwi r17, 0x02
bge TimerFire4_0x64
mr r8, r29
lwz r16, 0x0038(r30)
lwz r17, 0x003c(r30)
bl clear_cr0_lt
bge TimerFire4_0x50
mr r8, r29
bl SchRdyTaskNow
bl CalculateTimeslice
b TimerFire5_0x8
TimerFire4_0x50
li r18, 0x02
stb r18, 0x0019(r29)
mr r8, r29
bl SchRdyTaskNow
b TimerFire5_0x8
TimerFire4_0x64
mr r8, r29
; TimerFire5
TimerFire5 ; OUTSIDE REFERER
bl SchRdyTaskNow
bl major_0x149d4
TimerFire5_0x8 ; OUTSIDE REFERER
bl FlagSchEvaluationIfTaskRequires
mfsprg r18, 0
b TimerDispatch_0x30
; major_0x13364
; Dead code -- probably removed from TimerTable
_log 'Heartbeat: Ext '
lwz r16, KDP.NKInfo.ExternalIntCount(r1)
mr r8, r16
bl printd
_log 'Alerts '
lwz r16, KDP.NKInfo.AlertCount(r1)
mr r8, r16
bl printd
_log 'Blue cpu-'
lwz r17, PSA.PA_BlueTask(r1)
lhz r16, Task.CPUIndex(r17)
mr r8, r16
bl printb
_log 'state-'
lbz r16, Task.State(r17)
mr r8, r16
bl printb
_log 'scr-'
lwz r16, KDP.PA_ECB(r1)
lwz r18, KDP.PostIntMaskInit(r1)
lwz r16, ContextBlock.CR(r16)
and r16, r16, r18
mr r8, r16
bl printw
_log 'mcr-'
lwz r16, PSA.MCR(r1)
mr r8, r16
bl printw
_log 'IPL-'
lwz r16, KDP.PA_EmulatorIplValue(r1)
lhz r16, 0(r16)
mr r8, r16
bl printh
_log 'eSR-'
lwz r16, KDP.PA_ECB(r1)
lwz r16, ContextBlock.r25(r16)
andi. r16, r16, 7
mr r8, r16
bl printb
_log '^n'
mfxer r19
lwz r16, 0x0038(r30)
lwz r17, 0x003c(r30)
lwz r18, 0x0f2c(r1)
slwi r18, r18, 3
addc r17, r17, r18
; TimerFire7
TimerFire7 ; OUTSIDE REFERER
addze r16, r16
stw r16, 0x0038(r30)
stw r17, 0x003c(r30)
mtxer r19
mr r8, r30
bl EnqueueTimer
b TimerDispatch_0x144
; major_0x134d8
; Dead code -- probably removed from TimerTable
lwz r18, PSA.DecClockRateHzCopy(r1)
lwz r19, 0x0f88(r1)
subf. r19, r18, r19
ble TimerFire8_0x1c
srwi r19, r19, 11
mfxer r20
major_0x134d8_0x18
mftbu r16
mftb r17, 0x10c
mftbu r18
cmpw r16, r18
li r18, 0x00
bne- major_0x134d8_0x18
mttb r18
addc r17, r17, r19
addze r16, r16
mttbu r16
mttb r17
lwz r18, PSA.DecClockRateHzCopy(r1)
srwi r18, r18, 11
; TimerFire8
TimerFire8 ; OUTSIDE REFERER
addc r17, r17, r18
addze r16, r16
stw r16, 0x0038(r30)
stw r17, 0x003c(r30)
mtxer r20
mr r8, r30
bl EnqueueTimer
TimerFire8_0x1c ; OUTSIDE REFERER
b TimerDispatch_0x144
; major_0x13544
; Dead code -- probably removed from TimerTable
lwz r19, PSA._36c(r1)
mfxer r20
cmpwi cr1, r19, 0x00
srawi r8, r19, 31
beq cr1, TimerFire6_0x4
major_0x13544_0x14
mftbu r16
mftb r17, 0x10c
mftbu r18
cmpw r16, r18
li r18, 0x00
bne- major_0x13544_0x14
mttb r18
addc r19, r17, r19
adde r18, r16, r8
mttbu r18
mttb r19
bgt cr1, major_0x13544_0x64
major_0x13544_0x44
mftbu r18
mftb r19, 0x10c
mftbu r8
cmpw r18, r8
bne- major_0x13544_0x44
subfc r19, r17, r19
subfe. r18, r16, r18
blt major_0x13544_0x44
major_0x13544_0x64
lwz r18, PSA._368(r1)
addc r17, r17, r18
addze r16, r16
stw r16, 0x0038(r30)
; TimerFire6
TimerFire6 ; OUTSIDE REFERER
stw r17, 0x003c(r30)
TimerFire6_0x4 ; OUTSIDE REFERER
mtxer r20
beq cr1, TimerDispatch_0x144
mr r8, r30
bl EnqueueTimer
b TimerDispatch_0x144
; major_0x135d0
; Dead code -- probably removed from TimerTable
mfxer r19
lwz r16, 0x0038(r30)
lwz r17, 0x003c(r30)
lwz r18, 0x0f2c(r1)
srwi r18, r18, 1
addc r17, r17, r18
addze r16, r16
stw r16, 0x0038(r30)
stw r17, 0x003c(r30)
mtxer r19
mr r8, r30
bl EnqueueTimer
bl getchar
cmpwi r8, -0x01
beq TimerDispatch_0x144
bl panic_non_interactive
b TimerDispatch_0x144
; ARG Timer *r8
; CLOB r16-r20
EnqueueTimer ; OUTSIDE REFERER
; Keep the trip-time of this timer in r16/r17
lwz r16, Timer.Time(r8)
lwz r17, Timer.Time+4(r8)
; r20 = timer being considered
; r18/r19 = trip-time of timer being condidered
lwz r20, PSA.TimerQueue + TimerQueueStruct.LLL + LLL.Next(r1)
lwz r18, Timer.Time(r20)
lwz r19, Timer.Time+4(r20)
; First try to insert at head of global TMRQ
cmpw r16, r18
cmplw cr1, r17, r19
bgt @insert_further_ahead
blt @insert_at_tail
bge cr1, @insert_further_ahead
@insert_at_tail
addi r20, r1, PSA.TimerQueue + TimerQueueStruct.LLL
li r18, 1
stb r18, Timer.Byte3(r8)
; Insert at the very back of the queue
lwz r19, LLL.Freeform(r8)
lwz r9, LLL.Freeform(r20)
stw r9, LLL.Freeform(r8) ; my freeform = considered freeform
lwz r9, LLL.Next(r20)
stw r9, LLL.Next(r8) ; my next = next of considered
stw r20, LLL.Prev(r8) ; my prev = considered
stw r8, LLL.Prev(r9) ; prev of next of considered = me
stw r8, LLL.Next(r20) ; next of considered = me
stw r19, LLL.Freeform(r8) ; my freeform = my original freeform
b SetTimeslice
@insert_further_ahead
lwz r20, PSA.TimerQueue + TimerQueueStruct.LLL + LLL.Prev(r1)
@searchloop
lwz r18, Timer.Time(r20)
lwz r19, Timer.Time+4(r20)
cmpw r16, r18
cmplw cr1, r17, r19
bgt @insert_after_this_one
blt @next
bge cr1, @insert_after_this_one
@next
lwz r20, LLL.Prev(r20)
b @searchloop
@insert_after_this_one
li r18, 1
stb r18, Timer.Byte3(r8)
lwz r19, LLL.Freeform(r8)
lwz r9, LLL.Freeform(r20)
stw r9, LLL.Freeform(r8) ; my freeform = considered freeform
lwz r9, LLL.Next(r20)
stw r9, LLL.Next(r8) ; my next = next of considered
stw r20, LLL.Prev(r8) ; my prev = considered
stw r8, LLL.Prev(r9) ; prev of next of considered = me
stw r8, LLL.Next(r20) ; next of considered = me
stw r19, LLL.Freeform(r8) ; my freeform = my original freeform
blr
; Remove a Timer from the global timer firing queue (TMRQ).
; If the Timer was to be the next to fire, then perform the
; standard decrementer rollover adjustment.
; ARG Timer *r8
DequeueTimer
lwz r16, Timer.QueueLLL + LLL.FreeForm(r8)
cmpwi r16, 0
lwz r18, PSA.TimerQueue + TimerQueueStruct.LLL + LLL.Next(r1)
beq Local_Panic
RemoveFromList r8, scratch1=r16, scratch2=r17
li r16, 0
cmpw r18, r8
stb r16, Timer.Byte3(r8)
beq SetTimeslice
blr
; Get the number of timebase ticks in a specified period
; ARG long r8 period (positive for ms, negative for us)
TimebaseTicksPerPeriod
mr. r17, r8
li r19, 250
lwz r9, KDP.ProcInfo.DecClockRateHz(r1)
bgt+ @period_positive
blt+ @period_negative
li r8, 0
li r9, 0
blr ; fail
@period_negative
neg r17, r17
lisori r19, 250000
@period_positive
divw r19, r9, r19
mullw r9, r19, r17
mulhw r8, r19, r17
srwi r9, r9, 2
rlwimi r9, r8, 30, 0, 1
srwi r8, r8, 2
blr
; RET long r8 tbu, long r9 tbl
; CLOB r16, r17
GetTime
mfpvr r8
rlwinm. r8, r8, 0, 0, 14
beq @is_601
@retry_timebase:
mftbu r8
mftb r9
mftbu r16
cmpw r8, r16
bne- @retry_timebase
b @return
@is_601
dialect POWER ; disassembled this in POWER mode!
@retry_rtc
mfrtcu r8
mfrtcl r9
mfrtcu r16
cmp 0, r8, r16
dialect PowerPC
bne- @retry_rtc ; POWER chokes on hints?
dialect POWER
liu r16, 1000000000 >> 16
oril r16, r16, 1000000000 & 0xffff
mfmq r17
mul r8, r16, r8
mfmq r16
mtmq r17
mfxer r17
a r9, r16, r9
aze r8, r8
mtxer r17
dialect POWERPC
@return
blr

6
NanoKernel/NKTranslation.s
View File

@ -2147,10 +2147,10 @@ ProbePerfMonitor ; OUTSIDE REFERER
; Temporarily disable program interrupts (leave old handler in r20)
lwz r21, KDP.PA_NanoKernelCode(r1)
lwz r20, KDP.VecBaseSystem + VecTable.ProgramIntVector(r1)
lwz r20, KDP.VecTblSystem.ProgramIntVector(r1)
llabel r18, IgnoreSoftwareInt
add r21, r18, r21
stw r21, KDP.VecBaseSystem + VecTable.ProgramIntVector(r1)
stw r21, KDP.VecTblSystem.ProgramIntVector(r1)
@ -2214,7 +2214,7 @@ ProbePerfMonitor ; OUTSIDE REFERER
; Restore program interrupts
stw r20, KDP.VecBaseSystem + VecTable.ProgramIntVector(r1)
stw r20, KDP.VecTblSystem.ProgramIntVector(r1)
; Test r23 and save

22
NanoKernel/NanoKernel.s
View File

@ -9,19 +9,9 @@
include 'NKEquates.s'
include 'NKMacros.s'
csect NanoKernel[PR]
org 0
; I want these to be visibly wrong for the time being
FDP_TableBase
FDP_003C
loc_A38
FDP_011C
loc_D50
FDP_0DA0
MemRetryDSI
MemRetryMachineCheck
NKTop
b SystemCrash
org 0
include 'NKInit.s'
include 'NKSystemCrash.s'
include 'NKIntHandlers.s'
@ -31,3 +21,11 @@ NKTop
include 'NKSoftInt.s'
include 'NKLegacyVM.s'
NKBtm
FDP_TableBase
FDP_003C
loc_A38
FDP_011C
loc_D50
FDP_0DA0
MemRetryDSI
MemRetryMachineCheck