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Elliot Nunn 2018-08-09 09:28:18 +08:00
parent 47619e6a6f
commit f43b5b3a78
4 changed files with 113 additions and 96 deletions
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93
NanoKernel/NKEquates.s
View File

@ -92,33 +92,33 @@ mrFlagDidLoad equ cr3_so
; Entries and Entry Groups are called "PTEs" and "PTEGs".)
; Upper word of a Page Table Entry (PTE):
_bitequate 0, UpteValid ; if valid then a signed compare will raise the LT bit
_bitequate 0, UpteValid ; [V] if valid then a signed compare will raise the LT bit
; bits 1-24 hold the Virtual Segment ID (VSID, allows one HTAB to hold many addr spaces)
_bitequate 25, UpteHash ; set if this PTE is placed according to secondary hash
_bitequate 25, UpteHash ; [H] set if this PTE is placed according to secondary hash
; bits 26-31 hold the Abbreviated Page Index (API, the EA bits that aren't implicit in the hash)
; Lower word of a Page Table Entry (PTE):
; bits 0-19 hold the Real Page Number (RPN, the address of the physical page)
; bits 20-22 are reserved
_bitequate 23, LpteReference ; set by arch when page is read
_bitequate 24, LpteChange ; set by arch when page is written
_bitequate 25, LpteWritethru ; these are the "WIMG" memory access policy bits
_bitequate 26, LpteInhibcache
_bitequate 27, LpteMemcoher
_bitequate 28, LpteGuardwrite
_bitequate 23, LpteReference ; [R] set by arch when page is read
_bitequate 24, LpteChange ; [C] set by arch when page is written
_bitequate 25, LpteWritethru ; [W] these are the "WIMG" memory access policy bits
_bitequate 26, LpteInhibcache ; [I]
_bitequate 27, LpteMemcoher ; [M]
_bitequate 28, LpteGuardwrite ; [G]
; bit 29 is reserved
_bitequate 30, LpteP1 ; supervisor and user access policy bits (check these)
_bitequate 31, LpteP2
_bitequate 30, LpteP0 ; [P0] supervisor and user access policy bits (check these)
_bitequate 31, LpteP1 ; [P1]
; Some combinations from the v1 Trampoline:
ATTR_RW_Locked equ LpteMemcoher
ATTR_RW equ LpteMemcoher | LpteP1
ATTR_RO equ LpteMemcoher | LpteP1 | LpteP2
ATTR_RW equ LpteMemcoher | LpteP0
ATTR_RO equ LpteMemcoher | LpteP0 | LpteP1
ATTR_IO_Locked equ LpteInhibcache | LpteGuardwrite
ATTR_IO equ LpteInhibcache | LpteGuardwrite | LpteP1
ATTR_RO_Quiet equ LpteWritethru | LpteMemcoher | LpteP1 | LpteP2
ATTR_RO_Locked equ LpteChange | LpteMemcoher | LpteP1 | LpteP2
ATTR_RO_LockedQuiet equ LpteWritethru | LpteChange | LpteMemcoher | LpteP1 | LpteP2
ATTR_IO equ LpteInhibcache | LpteGuardwrite | LpteP0
ATTR_RO_Quiet equ LpteWritethru | LpteMemcoher | LpteP0 | LpteP1
ATTR_RO_Locked equ LpteChange | LpteMemcoher | LpteP0 | LpteP1
ATTR_RO_LockedQuiet equ LpteWritethru | LpteChange | LpteMemcoher | LpteP0 | LpteP1
; "PMDTs" (described below) imitate the lower word of a PTE.
@ -172,30 +172,45 @@ PMDT_PTE_Single_Rel equ 0x600
########################################################################
; 68k Page Table Entries
; A handful of special PMDTs describe the MacOS "Primary Address Range"
; (the contiguous RAM starting at address 0 and containing the sys and app
; heaps etc). Instead of referring directly to physical pages, each of
; these PMDTs has in its RPN field a pointer to an array of 68k Page Table
; Entries! Besides being friendly to old Virtual Memory Manger code, this
; provides a convenient way to store state for individual logical pages
; and to allow them to use discontiguous physical backing.
; 68k Page Descriptors
A handful of special PMDTs describe the MacOS "Primary Address Range"
(the contiguous RAM starting at address 0 and containing the sys and app
heaps etc). Instead of referring directly to physical pages, each of
these PMDTs has in its RPN field a pointer to an array of 68k Page
Descriptors! These are in the 68k 4k-page format, and could also be
called 68k Page Table Entries. Besides being friendly to old 68k code
using the VMDispatch trap (FE0A), this provides a convenient way to
store state for individual logical pages and to allow them to use
discontiguous physical backing.
; Bits 0-9:
; if M68pteInHTAB: PTE offset (in 8b increments from HTABORG)
; else: Real Page Number (RPN)
_bitequate 20, M68pteInHTAB ; (unlike 68k)
_bitequate 21, M68pte21
_bitequate 22, M68pteSavedUpdate
_bitequate 23, M68pte23
_bitequate 24, M68pte24
_bitequate 25, M68pteInhibcache ; (unlike 68k) like PPC Inhibcache
_bitequate 26, M68pteNonwritethru ; (unlike 68k) like inverse of PPC Writethru
_bitequate 27, M68pteModified ; like PPC Change
_bitequate 28, M68pteUpdate ; like PPC Reference
_bitequate 29, M68pteWriteProtect
_bitequate 30, M68pte30
_bitequate 31, M68pteResident ; (unlike 68k) there is a physical page
; Bits 0-19:
; if M68pdInHTAB: native PTE index relative to HTABORG
; else: physical page address
_bitequate 20, M68pdInHTAB ; [UR] user-reserved
_bitequate 21, M68pdGlobal ; [G] page immune to PFLUSH (unused?)
_bitequate 22, M68pdFrozenUsed ; [U1] copied from Used by VMLRU
_bitequate 23, M68pdU0 ; [U0] in 68k arch
_bitequate 24, M68pdSupProtect ; [S] supervisor access only
_bitequate 25, M68pdCacheMode1 ; [CM1] like PPC Inhibcache
_bitequate 26, M68pdCacheMode0 ; [CM0] like inverse of PPC Writethru
_bitequate 27, M68pdModified ; [M] like PPC Change
_bitequate 28, M68pdUsed ; [U] like PPC Reference
_bitequate 29, M68pdWriteProtect ; [WP] ?unused
_bitequate 30, M68pdIndirect ; [PDT1]
_bitequate 31, M68pdResident ; [PDT0]
; Cache Mode (CM) bits:
; CM1/CM0 Meaning
; 00 Cachable,Write-through
; 01 Cachable,Copyback
; 10 Noncachable,Serialized
; 11 Noncachable
; Therefore CM1 should match PPC Inhibcache,
; and CM0 should be inverse of PPC Writethru
; User Page Attribute (U) bits:
; In the 68k arch these are user-defined, but they are exposed on
; the external bus when the logical page is accessed.
########################################################################

90
NanoKernel/NKLegacyVM.s
View File

@ -307,10 +307,10 @@ VMExchangePages
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1 ; must be in pageable area
bc BO_IF, 21, vmRetNeg1
bc BO_IF_NOT, bM68pteResident, vmRetNeg1 ; must be resident
bc BO_IF, bM68pteInhibcache, vmRetNeg1 ; must not have special properties
bc BO_IF_NOT, bM68pteNonwritethru, vmRetNeg1
bcl BO_IF, M68pteInHTAB, RemovePTEFromHTAB ; if in HTAB, must be removed
bc BO_IF_NOT, bM68pdResident, vmRetNeg1 ; must be resident
bc BO_IF, bM68pdCacheMode1, vmRetNeg1 ; must not have special properties
bc BO_IF_NOT, bM68pdCacheMode0, vmRetNeg1
bcl BO_IF, M68pdInHTAB, RemovePTEFromHTAB ; if in HTAB, must be removed
mr r6, r15 ; r6 = src 68k PTE ptr
mr r4, r5
@ -319,10 +319,10 @@ VMExchangePages
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1
bc BO_IF, 21, vmRetNeg1
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
bc BO_IF, bM68pteInhibcache, vmRetNeg1
bc BO_IF_NOT, bM68pteNonwritethru, vmRetNeg1
bcl BO_IF, M68pteInHTAB, RemovePTEFromHTAB
bc BO_IF_NOT, bM68pdResident, vmRetNeg1
bc BO_IF, bM68pdCacheMode1, vmRetNeg1
bc BO_IF_NOT, bM68pdCacheMode0, vmRetNeg1
bcl BO_IF, M68pdInHTAB, RemovePTEFromHTAB
stw r5, 0(r15) ; swap 68k PTEs (in that big flat list)
stw r16, 0(r6)
@ -346,7 +346,7 @@ VMExchangePages
VMGetPhysicalPage
bl PageInfo
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
bc BO_IF_NOT, bM68pdResident, vmRetNeg1
srwi r3, r9, 12
b vmRet
@ -355,7 +355,7 @@ VMGetPhysicalPage
getPTEntryGivenPage
bl PageInfo
mr r3, r16
bc BO_IF_NOT, bM68pteResident, vmRet
bc BO_IF_NOT, bM68pdResident, vmRet
rlwimi r3, r9, 0, 0xFFFFF000
b vmRet
@ -363,7 +363,7 @@ getPTEntryGivenPage
VMIsInited
bl PageInfo
bc BO_IF, bM68pteResident, vmRet1
bc BO_IF, bM68pdResident, vmRet1
rlwinm r3, r16, 16, 31, 31
b vmRet
@ -371,14 +371,14 @@ VMIsInited
VMIsResident
bl PageInfo
rlwinm r3, r16, 0, 1 ; M68pteResident
rlwinm r3, r16, 0, 1 ; M68pdResident
b vmRet
########################################################################
VMIsUnmodified
bl PageInfo
rlwinm r3, r16, bM68pteModified + 1, 1
rlwinm r3, r16, bM68pdModified + 1, 1
xori r3, r3, 1
b vmRet
@ -392,7 +392,7 @@ VMLRU ; For each resident page: save Update bit and clear original
srwi r4, r9, 2 ; r4 = loop counter
li r5, LpteReference ; for clearing bits with andc
li r6, M68pteUpdate
li r6, M68pdUsed
@loop ; over every logical page
lwzu r16, -4(r15)
@ -400,19 +400,19 @@ VMLRU ; For each resident page: save Update bit and clear original
mtcr r16
cmpwi r4, 0
rlwinm r7, r16, 23, 7FFFFFF8 ; r7 = offset of PPC PTE (if any)
bc BO_IF_NOT, bM68pteResident, @nonresident
rlwinm r7, r16, 23, 7FFFFFFC ; r7 = offset of PPC PTE (if any)
bc BO_IF_NOT, bM68pdResident, @nonresident
bc BO_IF_NOT, bM68pteInHTAB, @not_in_htab
bc BO_IF_NOT, bM68pdInHTAB, @not_in_htab
add r14, r14, r7 ; If PPC PTE in HTAB, copy its Ref
lwz r9, 4(r14) ; bit back to 68k PTE and clear
_mvbit r16, bM68pteUpdate, r9, bLpteReference
_mvbit r16, bM68pdUsed, r9, bLpteReference
andc r9, r9, r5
bl ChangeNativeLowerPTE
subf r14, r7, r14
@not_in_htab
_mvbit r16, bM68pteSavedUpdate, r16, bM68pteUpdate
_mvbit r16, bM68pdFrozenUsed, r16, bM68pdUsed
andc r16, r16, r6 ; save Update and clear original
stw r16, 0(r15) ; save changed 68k PTE
@nonresident
@ -426,17 +426,17 @@ VMMakePageCacheable
; PPC: W=0, I=0
; 68k: Nonwritethru=0, Inhibcache=0
bl PageInfo
rlwinm r7, r16, 0, M68pteInhibcache | M68pteNonwritethru
cmpwi r7, M68pteNonwritethru
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
rlwinm r7, r16, 0, M68pdCacheMode1 | M68pdCacheMode0
cmpwi r7, M68pdCacheMode0
bc BO_IF_NOT, bM68pdResident, vmRetNeg1
beq vmRet
bc BO_IF_NOT, ispaged, vmRetNeg1
bcl BO_IF_NOT, M68pteInHTAB, VMSecondLastExportedFunc
bcl BO_IF_NOT, M68pdInHTAB, VMSecondLastExportedFunc
rlwinm r16, r16, 0, ~(M68pteInhibcache | M68pteNonwritethru)
rlwinm r16, r16, 0, ~(M68pdCacheMode1 | M68pdCacheMode0)
rlwinm r9, r9, 0, ~(LpteWritethru | LpteInhibcache)
ori r16, r16, M68pteNonwritethru
ori r16, r16, M68pdCacheMode0
bl ChangeNativeAnd68kPTEs
b vmRet
@ -446,10 +446,10 @@ VMMakePageCacheable
VMMakePageWriteThrough
bl PageInfo
rlwinm. r7, r16, 0, 25, 26
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
bc BO_IF_NOT, bM68pdResident, vmRetNeg1
beq vmRet
bc BO_IF_NOT, ispaged, VMMakePageWriteThrough_0x3c
bcl BO_IF_NOT, M68pteInHTAB, VMSecondLastExportedFunc
bcl BO_IF_NOT, M68pdInHTAB, VMSecondLastExportedFunc
rlwinm r16, r16, 0, 27, 24
rlwinm r9, r9, 0, 27, 24
ori r9, r9, 0x40
@ -460,7 +460,7 @@ VMMakePageWriteThrough_0x3c
rlwinm r7, r4, 16, 28, 31
cmpwi r7, 0x09
blt vmRetNeg1
bc BO_IF_NOT, M68pteInhibcache, vmRetNeg1
bc BO_IF_NOT, M68pdCacheMode1, vmRetNeg1
lwz r5, 0x000c(r15)
andi. r6, r5, 0xe01
cmpwi r6, 0xa01
@ -565,7 +565,7 @@ VMMakePageNonCacheable
bl PageInfo
rlwinm r7, r16, 0, 25, 26
cmpwi r7, 0x60
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
bc BO_IF_NOT, bM68pdResident, vmRetNeg1
beq vmRet
bc BO_IF_NOT, ispaged, vmRetNeg1
bl BO_IF_NOT, 20, VMSecondLastExportedFunc
@ -593,7 +593,7 @@ VMMarkBacking
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1
bc BO_IF, 21, vmRetNeg1
bcl BO_IF, M68pteInHTAB, RemovePTEFromHTAB
bcl BO_IF, M68pdInHTAB, RemovePTEFromHTAB
rlwimi r16, r5, 16, 15, 15
li r7, 0x01
andc r16, r16, r7
@ -605,7 +605,7 @@ VMMarkBacking
VMMarkCleanUnused
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1
bc BO_IF_NOT, bM68pteResident, vmRetNeg1
bc BO_IF_NOT, bM68pdResident, vmRetNeg1
bl BO_IF_NOT, 20, VMSecondLastExportedFunc
li r7, 0x180
andc r9, r9, r7
@ -641,8 +641,8 @@ VMMarkUndefined_0x28
VMMarkResident
bl PageInfo
bc BO_IF_NOT, ispaged, vmRetNeg1
bc BO_IF, bM68pteResident, vmRetNeg1
bcl BO_IF, M68pteInHTAB, SystemCrash
bc BO_IF, bM68pdResident, vmRetNeg1
bcl BO_IF, M68pdInHTAB, SystemCrash
rlwimi r16, r5, 12, 0, 19
ori r16, r16, 0x01
stw r16, 0x0000(r15)
@ -659,10 +659,10 @@ VMPTest
bge vmRet
bl PageInfo
li r3, 0x400
bc BO_IF_NOT, bM68pteResident, vmRet
bc BO_IF_NOT, bM68pdResident, vmRet
li r3, 0x00
ori r3, r3, 0x8000
bc BO_IF_NOT, bM68pteWriteProtect, vmRet
bc BO_IF_NOT, bM68pdWriteProtect, vmRet
cmpwi r6, 0x00
beq vmRet
li r3, 0x800
@ -683,7 +683,7 @@ setPTEntryGivenPage
andi. r7, r7, 0x11c
xor r16, r16, r7
stw r16, 0x0000(r15)
bc BO_IF_NOT, bM68pteInHTAB, vmRet
bc BO_IF_NOT, bM68pdInHTAB, vmRet
rlwimi r9, r16, 5, 23, 23
rlwimi r9, r16, 3, 24, 24
rlwimi r9, r16, 30, 31, 31
@ -694,14 +694,14 @@ setPTEntryGivenPage
VMShouldClean
bl PageInfo
bc BO_IF_NOT, bM68pteResident, vmRet0
bc BO_IF, bM68pteUpdate, vmRet0
bc BO_IF_NOT, bM68pteModified, vmRet0
bc BO_IF_NOT, bM68pdResident, vmRet0
bc BO_IF, bM68pdUsed, vmRet0
bc BO_IF_NOT, bM68pdModified, vmRet0
bc BO_IF_NOT, ispaged, vmRetNeg1
xori r16, r16, 0x10
ori r16, r16, 0x100
stw r16, 0x0000(r15)
bc BO_IF_NOT, bM68pteInHTAB, vmRet1
bc BO_IF_NOT, bM68pdInHTAB, vmRet1
xori r9, r9, 0x80
bl ChangeNativeLowerPTE
b vmRet1
@ -715,7 +715,7 @@ VMAllocateMemory
cmpw cr7, r7, r8
or r7, r4, r6
rlwinm. r7, r7, 0, 0, 11
bc BO_IF_NOT, M68pteInhibcache, vmRetNeg1
bc BO_IF_NOT, M68pdCacheMode1, vmRetNeg1
lwz r9, KDP.VMLogicalPages(r1)
bne cr7, vmRetNeg1
mr r7, r4
@ -727,7 +727,7 @@ VMAllocateMemory
VMAllocateMemory_0x74
addi r4, r4, -0x01
bl PageInfo
bcl BO_IF, M68pteInHTAB, RemovePTEFromHTAB
bcl BO_IF, M68pdInHTAB, RemovePTEFromHTAB
lwz r9, KDP.VMLogicalPages(r1)
subf r8, r4, r9
cmplw cr7, r5, r8
@ -844,6 +844,8 @@ VMAllocateMemory_0x324
; residence is determined by bit 20 (value 0x800) of the PTE. This is
; often checked by a bltl cr5
; Individual VM calls usually BL straight to this function.
PageInfo ; r4=pg, r9=areapgcnt // cr[16]=ispaged, r16/r15/cr[20-31]=68kPTE/ptr/attrs, r8/r9/r14=PTE-hi/lo/ptr
cmplw cr4, r4, r9
lwz r15, KDP.VMPageArray(r1) ; r15 = Page List base
@ -856,8 +858,8 @@ PageInfo ; r4=pg, r9=areapgcnt // cr[16]=ispaged, r16/r15/cr[20-31]=68kPTE/ptr/a
mtcrf %00000111, r16 ; Set all flags in CR (but not RealPgNum)
rlwinm r8, r16, 23, 9, 28 ; r8 = Page Table Entry offset
rlwinm r9, r16, 0, 0, 19
bclr BO_IF_NOT, bM68pteInHTAB ; Page not in Page Table, so return the Page List Entry.
bc BO_IF_NOT, bM68pteResident, SystemCrash ; panic if the PTE is in the HTAB but isn't mapped to a real page??
bclr BO_IF_NOT, bM68pdInHTAB ; Page not in Page Table, so return the Page List Entry.
bc BO_IF_NOT, bM68pdResident, SystemCrash ; panic if the PTE is in the HTAB but isn't mapped to a real page??
lwzux r8, r14, r8 ; r8/r9 = PTE
lwz r9, 4(r14)

14
NanoKernel/NKMemory.s
View File

@ -152,17 +152,17 @@ PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
lwzux r28, r26, r28 ; r26 = PLE ptr, r28 = PLE
lwz r31, KDP.PageAttributeInit(r1)
andi. r30, r28, M68pteInHTAB | M68pte24 | M68pteResident
andi. r30, r28, M68pdInHTAB | M68pdSupProtect | M68pdResident
rlwimi r31, r28, 0, 0xFFFFF000
cmplwi r30, M68pteResident
cmplwi cr7, r30, M68pte24 | M68pteResident
cmplwi r30, M68pdResident
cmplwi cr7, r30, M68pdSupProtect | M68pdResident
ori r31, r31, LpteReference
_mvbit r31, bLpteChange, r28, bM68pteModified
_mvbit r31, bLpteInhibcache, r28, bM68pteInhibcache
_mvbit r31, bLpteWritethru, r28, bM68pteNonwritethru
_mvbit r31, bLpteChange, r28, bM68pdModified
_mvbit r31, bLpteInhibcache, r28, bM68pdCacheMode1
_mvbit r31, bLpteWritethru, r28, bM68pdCacheMode0
xori r31, r31, LpteWritethru
_mvbit r31, bLpteP2, r28, bM68pteWriteProtect
_mvbit r31, bLpteP1, r28, bM68pdWriteProtect
beq @parsed_pmdt ; if resident but outside HTAB, put in HTAB
bltlr cr7 ; if no flags, return invalid (GT)

12
NanoKernel/NKReset.s
View File

@ -326,12 +326,12 @@ Create68kPTEs
lwz r23, KDP.PageAttributeInit(r1) ; "default WIMG/PP settings for PTE creation"
li r30, M68pteResident
_mvbit r30, bM68pteInhibcache, r23, bLpteInhibcache
_mvbit r30, bM68pteNonwritethru, r23, bLpteWritethru
xori r30, r30, bM68pteNonwritethru
_mvbit r30, bM68pteModified, r23, bLpteChange
_mvbit r30, bM68pteUpdate, r23, bLpteReference
li r30, M68pdResident
_mvbit r30, bM68pdCacheMode1, r23, bLpteInhibcache
_mvbit r30, bM68pdCacheMode0, r23, bLpteWritethru
xori r30, r30, bM68pdCacheMode0
_mvbit r30, bM68pdModified, r23, bLpteChange
_mvbit r30, bM68pdUsed, r23, bLpteReference
li r23, NKSystemInfo.MaxBanks
@next_bank