mirror of
https://github.com/elliotnunn/powermac-rom.git
synced 2024-06-02 07:41:28 +00:00
c7d4cdd367
This is part of the work to get the mini running well. The kcPowerDispatch and kcCacheDispatch entry points were explored. The dead code implementing a Timer "Heartbeat" was also used to label some structures better.
530 lines
12 KiB
ArmAsm
530 lines
12 KiB
ArmAsm
###### ### ###### ## ## ######## ###### ### ## ##
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## ## ## ## ## ## ## ## ## ## ## ##
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## ## ## ## ######### ###### ## ## ## ## ##
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## ######### ## ## ## ## ## ######### ## ##
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## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
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###### ## ## ###### ## ## ######## ###### ## ## ######## ########
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; Enable/disable/probe the L1/2 data/inst cache
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; Probably called using an unknown 68k F-trap. Not usually called on my
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; G4, but can be tested by hacking the MPCall table. Uses fancy new CPU
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; features (MSSCR0), so probably not legacy code. For CPU accelerator
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; cards? `FlushCache` needs to be nopped out to prevent a crash.
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; ARGUMENT (r3)
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; r3.hi = action flags
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; enable specified caches $8000
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; disable specified caches $4000
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; report pre-change state $2000
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; also enable (???) $1000
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; enable/disable I-cache $0800
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; enable/disable D-cache $0400
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;
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; r3.lo = which cache (L1/2)
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; level 1 1
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; level 2 2
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;
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; RETURN VALUE (r3)
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; r3.hi = pre-change state flags (resemble action flags)
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; both caches disabled $4000
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; either cache enabled $8000
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; I-cache enabled $0800
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; D-cache enabled $0400
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;
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; r3.lo = return status
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; success 0
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; failure < 0
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; checked L1 but did not set 1
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; checked L2 but did not set 2
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; DeclareMPCall 199, kcCacheDispatch ; DEBUG
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kcCacheDispatch
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_RegRangeToContextBlock r21, r23 ; get some breathing room
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; _log 'kcCacheDispatch ' ; DEBUG
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; mr r8, r3 ; DEBUG
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; bl printw ; DEBUG
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; _log '^n' ; DEBUG
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clrlwi r8, r3, 16 ; bad selector
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cmplwi r8, 2
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bgt- @fail_bad_selector
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
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andi. r8, r8, 1 << NKProcessorInfo.hasL2CR
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beq- CacheCallFailNoL2 ; no L2CR => fail (what about 601?)
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rlwinm. r9, r3, 0, 2, 2 ; if flagged, get cache state in r23
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bnel- CacheCallGetInfoForReturnValue ; (otherwise, r23 is undefined)
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srwi r8, r3, 30 ; cannot enable *and* disable
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cmpwi r8, 3
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beq- CacheCallFailBadFlags
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clrlwi r8, r3, 16 ; go to main code for level 1/2 cache
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cmplwi r8, 1
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beq- CacheCallDispatchL1
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cmplwi r8, 2
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beq- CacheCallDispatchL2
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@fail_bad_selector ; fall through => bad selector
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lisori r3, -2
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b CacheCallReturn
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### ## ## ###
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## ## #### ##
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## ## ## ##
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## ## ## ##
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## ## ## ##
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## ## ## ##
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### ######## ###### ###
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CacheCallDispatchL1
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rlwinm. r9, r3, 0, 1, 1
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bne- CacheCallL1DisableSelected
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rlwinm. r9, r3, 0, 0, 0
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bne- CacheCallL1EnableSelected
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rlwinm. r9, r3, 0, 3, 3 ; ???
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bl FlushCaches
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b CacheCallReturn
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CacheCallL1DisableSelected
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bl FlushCaches
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rlwinm r22, r3, 0, 4, 5 ; shift arg bits to align with HID0[DCE/ICE]
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srwi r22, r22, 12
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mfspr r21, hid0
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andc r21, r21, r22 ; HID0 &= ~mybits
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sync
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mtspr hid0, r21
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li r3, 0
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b CacheCallReturn
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CacheCallL1EnableSelected
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rlwinm r22, r3, 0, 4, 5 ; shift arg bits to align with HID0[DCE/ICE]
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srwi r22, r22, 12
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mfspr r21, hid0
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or r21, r21, r22 ; HID0 |= mybits
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sync
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mtspr hid0, r21
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li r3, 0
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b CacheCallReturn
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### ## ####### ###
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## ## ## ## ##
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## ## ## ##
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## ## ####### ##
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## ## ## ##
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## ## ## ##
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### ######## ######### ###
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CacheCallDispatchL2
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rlwinm. r9, r3, 0, 1, 1
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bne- CacheCallL2DisableSelected
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rlwinm. r9, r3, 0, 0, 0
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bne- CacheCallL2EnableSelected
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rlwinm. r9, r3, 0, 3, 3
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bne- CacheCallL2Flag3 ; goes to DisableSelected
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rlwinm. r9, r3, 0, 2, 2
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;bne removed?
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bne- CacheCallReturn
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CacheCallFailBadFlags
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lisori r3, -4
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b CacheCallReturn
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CacheCallL2Flag3
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bl CacheCallL2DisableSelected ; typo? should be `b`
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CacheCallL2EnableSelected
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mfspr r21, l2cr ; fail if L2CR[L2E] already set
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sync
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andis. r21, r21, 0x8000
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bne- CacheCallReturn
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1)
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and. r8, r8, r8
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beq- CacheCallFailNoL2 ; fail if zero-sized cache reported
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mfspr r21, hid0 ; save HID0
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rlwinm r8, r21, 0, 12, 10 ; clear HID0[DPM] (dynamic power management)
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mtspr hid0, r8 ; presumably to keep L2 working while we wait?
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sync
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addi r8, r1, PSA.ProcessorState
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lwz r8, NKProcessorState.saveL2CR(r8)
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and. r8, r8, r8
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beq- CacheCallReturn ; fail if zero L2CR was saved?
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sync
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lis r9, 0x0020 ; set L2CR[GI] (global invalidate)
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or r8, r8, r9
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mtspr l2cr, r8
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sync
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@inval_loop
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mfspr r8, l2cr ; check L2CR[IP] (invalidate progress)
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sync
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andi. r9, r8, 1
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bne+ @inval_loop
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lis r9, 0x0020 ; clear L2CR[GI]
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andc r8, r8, r9
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mtspr l2cr, r8
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sync
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lis r9, 0x8000 ; set L2CR[L2E] (L2 enable)
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or r8, r8, r9
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mtspr l2cr, r8
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sync
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mtspr hid0, r21 ; restore HID0
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sync
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li r3, 0 ; return successfully
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b CacheCallReturn
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CacheCallFailNoL2
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li r3, -2
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b CacheCallReturn
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CacheCallL2DisableSelected
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mfspr r22, l2cr ; return if already disabled per L2CR[L2E]
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sync
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andis. r22, r22, 0x8000
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beq- CacheCallReturn
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bl FlushCaches
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mfspr r22, l2cr ; clear L2CR[L2E]
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sync
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clrlwi r22, r22, 1
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mtspr l2cr, r22
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sync
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addi r8, r1, PSA.ProcessorState
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stw r22, NKProcessorState.saveL2CR(r8) ; update saveL2CR
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sync
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rlwinm r22, r22, 0, 7, 3 ; clear L2CR[3/5/6] (all reserved)
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oris r22, r22, 0x0010 ; set L2CR[13] (also reserved)
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mtspr l2cr, r22
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sync
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;b CacheCallReturn ; fall through
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### ######## ######## ######## ## ## ######## ## ## ###
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## ## ## ## ## ## ## ## ## ### ## ##
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## ## ## ## ## ## ## ## ## #### ## ##
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## ######## ###### ## ## ## ######## ## ## ## ##
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## ## ## ## ## ## ## ## ## ## #### ##
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## ## ## ## ## ## ## ## ## ## ### ##
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### ## ## ######## ## ####### ## ## ## ## ###
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CacheCallReturn
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ori r23, r23, 0xffff ; put the r23.hi from CacheCallGetInfoForReturnValue into r3.hi
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oris r3, r3, 0xffff
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and r3, r3, r23
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CacheCallReturnWithoutFlags
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_RegRangeFromContextBlock r21, r23
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sync
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; _log 'Return ' ; DEBUG
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; mr r8, r3 ; DEBUG
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; bl printw ; DEBUG
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; _log '^n' ; DEBUG
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b IntReturn
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### ######## ######## ####### ######## ######## ###
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## ## ## ## ## ## ## ## ## ## ##
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## ## ## ## ## ## ## ## ## ## ##
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## ######## ######## ## ## ######## ###### ##
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## ## ## ## ## ## ## ## ## ##
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## ## ## ## ## ## ## ## ## ##
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### ## ## ## ####### ######## ######## ###
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; RET r23.hi = flags describing state of specified cache (see top of file)
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CacheCallGetInfoForReturnValue
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clrlwi r8, r3, 16
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cmplwi r8, 1
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beq- @level1
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cmplwi r8, 2
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beq- @level2
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lisori r3, -5
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b CacheCallReturnWithoutFlags
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@level1
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mfspr r21, hid0
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rlwinm. r21, r21, 12, 4, 5
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beq- @all_off
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oris r23, r21, 0x8000
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blr
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@level2
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1)
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and. r8, r8, r8
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beq+ CacheCallFailNoL2
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mfspr r21, hid0 ; same bits as above
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rlwinm r21, r21, 12, 4, 5
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mfspr r22, l2cr ; L2-D is on if L1-D is on and L2CR[DO] is cleared
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rlwinm r22, r22, 5, 4, 4
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andc r21, r21, r22
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mfspr r22, l2cr ; then again, both L2s are off if L2CR[L2E] is cleared
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andis. r22, r22, 0x8000
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beq- @all_off
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or r23, r21, r22
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blr
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@all_off
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lisori r23, 0x40000000
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blr
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######## ## ## ## ###### ## ## ######## ## ## ## ## ###### ######
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## ## ## ## ## ## ## ## ## ## ## ### ## ## ## ## ##
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## ## ## ## ## ## ## ## ## ## #### ## ## ##
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###### ## ## ## ###### ######### ###### ## ## ## ## ## ## ######
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## ## ## ## ## ## ## ## ## ## ## #### ## ##
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## ## ## ## ## ## ## ## ## ## ## ## ### ## ## ## ##
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## ######## ####### ###### ## ## ## ####### ## ## ###### ######
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; Flush L1 and L2 caches
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; Also used by NKPowerCalls.s
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; ARG KDP *r1, ContextBlock *r6
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; CLOB r8, r9, cr
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FlushCaches
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; blr ; DEBUG
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; Be cautious
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mfctr r8
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stw r25, ContextBlock.r25(r6)
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stw r24, ContextBlock.r24(r6)
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stw r8, ContextBlock.KernelCTR(r6)
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; Flush level 1
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lhz r25, KDP.ProcessorInfo + NKProcessorInfo.DataCacheLineSize(r1)
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and. r25, r25, r25 ; r25 = L1-D line size
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cntlzw r8, r25
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beq- @return
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subfic r9, r8, 31 ; r9 = logb(L1-D line size)
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DataCacheTotalSize(r1)
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and. r8, r8, r8 ; r8 = L1-D size
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beq- @return
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lwz r24, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
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mtcr r24
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bc BO_IF, 31 - NKProcessorInfo.hasMSSregs, @use_SPRs_to_invalidate
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; => go away to handle weird CPUs
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bc BO_IF_NOT, 31 - NKProcessorInfo.hasPLRUL1, @no_pseudo_lru
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slwi r24, r8, 1
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add r8, r8, r24
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srwi r8, r8, 1 ; be generous with pseudo-LRU caches
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@no_pseudo_lru
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srw r8, r8, r9
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mtctr r8 ; loop counter = cache/line
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lwz r8, KDP.PA_ConfigInfo(r1) ; fill the cache with Mac ROM
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lwz r9, NKConfigurationInfo.ROMImageBaseOffset(r8)
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add r8, r8, r9
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@loop_L1
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lwzux r9, r8, r25
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bdnz+ @loop_L1
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; Flush level 2 (very similar to above)
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lwz r24, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
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andi. r24, r24, 1 << NKProcessorInfo.hasL2CR
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beq- @return ; return if L2CR unavailable
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mfspr r24, l2cr
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andis. r24, r24, 0x8000
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beq- @return ; return if L2 off (per L2CR[L2E])
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lhz r25, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DBlockSize(r1)
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and. r25, r25, r25 ; r25 = L2-D line size
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cntlzw r8, r25
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beq- @return
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subfic r9, r8, 31 ; r9 = logb(L2-D line size)
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorL2DSize(r1)
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and. r8, r8, r8 ; r8 = L2-D size
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beq- @return
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srw r8, r8, r9
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mtctr r8 ; loop counter = cache/line
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mfspr r24, l2cr ; set L2CR[DO] (disables L2-I)
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oris r24, r24, 0x0040
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mtspr l2cr, r24
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isync
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lwz r8, KDP.PA_ConfigInfo(r1) ; fill the cache with Mac ROM
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lwz r9, NKConfigurationInfo.ROMImageBaseOffset(r8)
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add r8, r8, r9
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addis r8, r8, 0x19 ; start high in ROM and count backwards
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neg r25, r25
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@loop_L2
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lwzux r9, r8, r25
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bdnz+ @loop_L2
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rlwinm r24, r24, 0, 10, 8
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mtspr l2cr, r24 ; clear L2CR[DO] (reenables L2-I)
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isync
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; Done (this return path is also called from the sneaky code below)
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@return
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lwz r8, ContextBlock.KernelCTR(r6)
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lwz r25, ContextBlock.r25(r6)
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lwz r24, ContextBlock.r24(r6)
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sync
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mtctr r8
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blr
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; If "hasMSSregs" flag (my name) is set in ProcessorFlags, L1 and L2 can
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; instead be flushed by clobbering reserved bits in MSSCR0 and L2CR
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; respectively.
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@use_SPRs_to_invalidate
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; Flush level 1: set MSSCR0[8] and spin until it clears
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dssall ; AltiVec needs to know
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sync
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mfspr r8, msscr0
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oris r8, r8, 0x0080
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mtspr msscr0, r8
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sync
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@loop_msscr0
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mfspr r8, msscr0
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sync
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andis. r8, r8, 0x0080
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bne+ @loop_msscr0
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; Flush level 2: set L2CR[4] and spin until it clears
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mfspr r8, l2cr
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ori r8, r8, 0x0800
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mtspr l2cr, r8
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sync
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@loop_l2cr
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mfspr r8, l2cr
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sync
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andi. r8, r8, 0x0800
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bne+ @loop_l2cr
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; Jump back up to main code path to return
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b @return
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; Called when we cop a machine check with the "L1 data cache error"
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; flag set in SRR1, followed by an interrupt return. Same trick as
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; above.
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; CLOB r8, cr
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FlushL1CacheUsingMSSCR0
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; Return if MSSCR0 unavailable
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lwz r8, KDP.ProcessorInfo + NKProcessorInfo.ProcessorFlags(r1)
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mtcr r8
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bclr BO_IF_NOT, 31-NKProcessorInfo.hasMSSregs
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; Flush level 1: set MSSCR0[8] and spin until it clears
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dssall ; AltiVec needs to know
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sync
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mfspr r8, msscr0
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oris r8, r8, 0x0080
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mtspr msscr0, r8
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sync
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@loop_msscr0
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mfspr r8, msscr0
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sync
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andis. r8, r8, 0x0080
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bne+ @loop_msscr0
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blr
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