mirror of
https://github.com/elliotnunn/supermario.git
synced 2024-11-22 04:31:30 +00:00
128 lines
3.7 KiB
Plaintext
128 lines
3.7 KiB
Plaintext
|
;
|
||
|
|
; File: MC680x0.a
|
||
|
|
;
|
||
|
|
; Contains: Equates for dealing with the 680x0 chips
|
||
|
|
;
|
||
|
|
; Written by: Paul Wolf
|
||
|
|
;
|
||
|
|
; Copyright: © 1991 by Apple Computer, Inc., all rights reserved.
|
||
|
|
;
|
||
|
|
; Change History (most recent first):
|
||
|
|
;
|
||
|
|
; <1> 10/24/91 SAM Rolled in Regatta file.
|
||
|
|
; <0> 8/3/91 SAM (pdw) Created needed for BusErrHandler in SCSIMgrHW96.a.
|
||
|
|
;
|
||
|
|
;__________________________________________________________________________
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
;****** 68040 *******
|
||
|
|
|
||
|
|
; Transfer Type
|
||
|
|
TT_Normal EQU $0 ; normal access
|
||
|
|
TT_MOVE16 EQU $1 ; MOVE16 Access
|
||
|
|
TT_Alternate EQU $2 ; Alternate access
|
||
|
|
TT_Acknowledge EQU $3 ; Acknowledge access
|
||
|
|
|
||
|
|
|
||
|
|
; Transfer Modifier
|
||
|
|
TM_Data_Cache_Push EQU $0 ; Data cache push
|
||
|
|
TM_User_Data EQU $1 ; User Data Access
|
||
|
|
TM_User_Code EQU $2 ; User Code Access
|
||
|
|
TM_MMU_DataTable EQU $3
|
||
|
|
TM_MMU_CodeTable EQU $4
|
||
|
|
TM_Sup_Data EQU $5 ; Supervisor Data Access
|
||
|
|
TM_Sup_Code EQU $6 ; Supervisor Code Access
|
||
|
|
|
||
|
|
|
||
|
|
; Transfer Type and Transfer Modifier combination
|
||
|
|
NORMAL_USER_DATA EQU ((TT_Normal<<3) | TM_User_Data)
|
||
|
|
NORMAL_USER_CODE EQU ((TT_Normal<<3) | TM_User_Code)
|
||
|
|
MOVE16_USER_DATA EQU ((TT_MOVE16<<3) | TM_User_Data)
|
||
|
|
MOVE16_SUPV_DATA EQU ((TT_MOVE16<<3) | TM_Sup_Data)
|
||
|
|
NORMAL_SUPV_DATA EQU ((TT_Normal<<3) | TM_Sup_Data)
|
||
|
|
NORMAL_SUPV_CODE EQU ((TT_Normal<<3) | TM_Sup_Code)
|
||
|
|
|
||
|
|
; Transfer Size
|
||
|
|
;WB_CHAR EQU $1 ; byte access
|
||
|
|
;WB_SHORT EQU $2 ; word access
|
||
|
|
;WB_LONG EQU $0 ; long word access
|
||
|
|
;WB_LINE EQU $3 ; line access
|
||
|
|
|
||
|
|
; MMUSR Bit Mask Definitions
|
||
|
|
MMUSR_R EQU $00000001 ; page resident
|
||
|
|
MMUSR_T EQU $00000002 ; TT hit
|
||
|
|
MMUSR_W EQU $00000004 ; Write-Protect page
|
||
|
|
MMUSR_M EQU $00000010 ; Modified Page
|
||
|
|
MMUSR_CM EQU $00000060 ; Page Cache Mode
|
||
|
|
MMUSR_S EQU $00000080 ; Supervisor Protection Page
|
||
|
|
MMUSR_UPA EQU $00000300 ; User Page Attribute
|
||
|
|
MMUSR_G EQU $00000400 ; Global Page
|
||
|
|
MMUSR_B EQU $00000800 ; Physical Bus error Page
|
||
|
|
MMUSR_PG EQU $fffff000 ; Page Base Address
|
||
|
|
|
||
|
|
|
||
|
|
;
|
||
|
|
; MC68040 Special Status Word (SSW)
|
||
|
|
;
|
||
|
|
|
||
|
|
bCP EQU 15 ; FP Post Exception Pending
|
||
|
|
bCU EQU 14 ; Unimplemented FP Inst. Exception pending
|
||
|
|
bCT EQU 13 ; Trace Exception pending
|
||
|
|
bCM EQU 12 ; MOVEM Instruction Execution pending
|
||
|
|
bMA EQU 11 ; Misaligned Access
|
||
|
|
bATC EQU 10 ; ATC Fault
|
||
|
|
bLK EQU 9 ; Locked Transfer
|
||
|
|
bRW EQU 8 ; Read/Write
|
||
|
|
|
||
|
|
SIZE_MSK EQU $60 ; transfer size
|
||
|
|
TT_MSK EQU $18 ; transfer type
|
||
|
|
TM_MSK EQU $07 ; transfer modifier
|
||
|
|
TTTM_MSK EQU TT_MSK+TM_MSK ; transfer type/modifier
|
||
|
|
|
||
|
|
; Transfer Size
|
||
|
|
WB_BYTE EQU $1<<5 ; byte access
|
||
|
|
WB_WORD EQU $2<<5 ; word access
|
||
|
|
WB_LONG EQU $0<<5 ; long word access
|
||
|
|
WB_LINE EQU $3<<5 ; line access
|
||
|
|
|
||
|
|
|
||
|
|
;
|
||
|
|
; MC68040 WriteBack Status Word (WBSW)
|
||
|
|
;
|
||
|
|
bVALID EQU 7 ; Valid
|
||
|
|
;SIZE_MSK, TT_MSK, TM_MSK, TTTM_MSK same as SSW definitions
|
||
|
|
|
||
|
|
|
||
|
|
AEXFrameType EQU $07 ; Access Error Exception Stack Frame type value
|
||
|
|
shortBEXFrameType EQU $0A ; Short bus cycle fault stack frame (020/030)
|
||
|
|
shortBEXFrameSize EQU 16*2 ; size
|
||
|
|
|
||
|
|
;
|
||
|
|
; Access Error Exception Stack Frame (7) Definition
|
||
|
|
;
|
||
|
|
AEXFrame RECORD 0, INCREMENT
|
||
|
|
xSR ds.w 1 ; Status Register
|
||
|
|
xPC ds.l 1 ; Program Counter
|
||
|
|
FrameType ; =7 for Access Error Exception
|
||
|
|
VectorOffset ds.w 1 ; Vector Offset
|
||
|
|
EffAddr ds.l 1 ; Effective Address
|
||
|
|
SSW ds.w 1 ; Special Status Word
|
||
|
|
WB3S ds.w 1 ; Writeback 3 Status
|
||
|
|
WB2S ds.w 1 ; Writeback 2 Status
|
||
|
|
WB1S ds.w 1 ; Writeback 1 Status
|
||
|
|
FaultAddr ds.l 1 ; Fault Address
|
||
|
|
WB3A ds.l 1 ; Writeback 3 Address
|
||
|
|
WB3D ds.l 1 ; Writeback 3 Data
|
||
|
|
WB2A ds.l 1 ; Writeback 2 Address
|
||
|
|
WB2D ds.l 1 ; Writeback 2 Data
|
||
|
|
WB1A ds.l 1 ; Writeback 1 Address
|
||
|
|
WB1D ; Writeback 1 Data
|
||
|
|
PD0 ds.l 1 ; Push Data 0
|
||
|
|
PD1 ds.l 1 ; Push Data 1
|
||
|
|
PD2 ds.l 1 ; Push Data 2
|
||
|
|
PD3 ds.l 1 ; Push Data 3
|
||
|
|
AEXFrameSize EQU * ; size of 040 AE Exception Frame
|
||
|
|
ENDR
|