mirror of
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734 lines
36 KiB
Plaintext
734 lines
36 KiB
Plaintext
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;---------------------------------------------------------------------------
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; File: USTSubtests.a
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;
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; Contains: This file contains tables for all CTE subtests in the ROM.
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; Following that are tables which are specific to each CPU. The
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; CPU specific tables reference tests in the main test table.
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; In order to add a test to the ROM you must make an entry for it
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; in the main test table, the add it to the appropriate CPU specific
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; tables along with flags which enable the test to run under the
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; following conditions:
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;
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; System power on startup
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; System reset
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; Serial test manager
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; Test manager A trap
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; ROM burnin
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;
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; All of the tests in these tables require RAM in order to run.
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;
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; There is another class of test in the ROMs which does not depend on
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; RAM. These tests run to completion even if RAM is not installed
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; because they operate completely out of CPU registers. These tests
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; do not use the CTE environment.
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;
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; Written by: Scott Smyers
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;
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; Copyright: © 1990-1993 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM15> 12/13/93 PN Roll in KAOs and Horror changes to support Malcom and AJ
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; machines.
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; <SM14> 11/23/93 rab Removed boxCarnation33, boxCarnation25, and boxCarnation16 from
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; the USTCPUList since we'll never ship Carnations.
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; <SM13> 11/8/93 JRH boxDBLite16 is now boxPowerBookDuo250. boxDBLite20 is now
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; boxPenLite.
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; <SM12> 8/17/93 SAM Placed forSmuf condo around smurf stuff.
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; <SM11> 8/12/93 BG Removed reference to boxWLCDc1 as such a thing will never exist.
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; Updated other boxflags to use "official" names.
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; <SM10> 8/11/93 KW changed boxRiscWombat to boxRiscCentris650
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; <SM9> 01-11-93 jmp Updated various BoxFlag names.
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; <SM8> 12/23/92 RC Added Support for Smurf on Wombat
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; <SM7> 12/17/92 RB Removed some of the LC930 conditionals. Added back other hasXXXX
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; conditionals to make it easier to build 1 off 1 Meg ROMs.
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; <SM6> 11/3/92 rab Roll in Horror changes. Comments follow:
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; <H22> 8/25/92 BG Modified WombatTests list to start testing some more parts on
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; the board now that we have real (non-ChipExpress) parts.
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; <H21> 8/2/92 AL Physically removed the SWIM test entry from the DBLite table.
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; <H20> 7/27/92 SWC Removed the SWIM test from the DBLite table since we don't know
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; how to turn on power to the SWIM chip for an arbitrary docking
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; bar.
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; <H19> 7/15/92 AL Removed the TestRBV entry from the DBLite table.
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; <H18> 6/26/92 BG Added further test table references for various new Wombats and
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; WLCDs. Also, ignore the last part of <H14> since there is a
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; Wombat20.
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; <H17> 6/17/92 AL Enabled all tests in the DBLite test table.
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; <H16> 6/9/92 djw Remove RBV test and commented out GSC test from DartTests.
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; <H15> 6/7/92 AL Added DartTests table and other support info, which will take
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; care of Dartanian and DartanianLC.
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; <H14> 6/3/92 BG Changed boxWombat20 to boxWombat33F. We will not (in the near
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; future) release a 20MHz Wombat in Lego plastics, so I'm
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; converting this boxFlag to be a 33MHz Wombat in Frigidaire
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; plastics.
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; <H13> 5/28/92 BG Added USTCPUList entries for various Wombats and WLCDs.
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; <SM5> 10/25/92 HY Changed boxMacLC to boxMacLCII in USTCPUList.
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; <SM4> 10/21/92 HY Added back TestRBV for LC/LC II/930a.
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; Removed If LC930 conditional for TestRBV_Name and TestRBV_ID.
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; <SM3> 10/19/92 RB Exclude non LC II related test code from the 930LC 1 Meg ROM.
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; <SM2> 5/2/92 kc Roll in Horror. Comments follow:
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; <H12> 3/17/92 SWC Renamed boxDBLite->boxDBLite25 and boxDBLiteLC->boxDBLite33, and
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; added boxDBLite16 and boxDBLite20 to the CPU test list.
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; <H11> 3/10/92 AL Cleaned up the machine test tables (aesthetics).
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; <H10> 3/6/92 AL Added the Vail and Carnation test tables, and the necessary
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; support for the different versions of each. Also, modified the
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; subtest lists to add support for the two new DBLite noncritical
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; tests (PG&E Selftest and GSC registers test). Finally, added
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; support for Standard Test Params, a CTE v2.1 feature.
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; <H9> 01/27/92 jmp Conditionalized the PROC parts of this file for use in lining up
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; the UST part of HORROR with that of TERROR/Zydeco.
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; <H8> 1/14/92 SWC Updated boxFlag labels to use shipping product names.
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; <H7> 1/13/92 SWC Added DB-Lite LC to the subtests list.
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; <H6> 12/20/91 JC Turning off all but SCC and VIA tests for unknown machines.
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; <H5> 12/16/91 SWC Temporarily patch out the sound tests in DB-Lite's table since
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; we're taking a bus error when we access the channel B FIFO.
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; <H4> 10/23/91 jmp Updating from the Zydeco-TERROR project.
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; <H3> 8/22/91 SWC Filled out DB-Lite's test list.
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; <H2> 8/5/91 SWC Added in an empty table entry for DB-Lite. We'll fill in the
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; list of tests later.
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; <7> 6/23/91 CCH Disabled IIfx-specific tests for unknown boxes, since they
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; currently cause the IIfx to hang.
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; <6> 6/13/91 djw (for SS) Prevent running 53C80 register test on Tim at startup.
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; This test fails if a powered down external drive is connected,
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; due to an unpowered terminator.
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; <5> 4/13/91 BG Rolled in Scott Smyers' changes: Clarified some of the
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; noncritical test names.
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; <4> 4/2/91 CCH Rolled in Scott Smyers' changes: Changed subtest ID from a long
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; to a word and added a word long test ID to the machine dependant
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; test tables. Added SONIC test and subtests and the 53C96
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; register test to the test tables.
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; <3> 2/18/91 djw Rolled in Scott Smyers' changes
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; <2> 1/14/91 CCH Rolled in Scott Smyers' changes.
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; <1> 12/14/90 SS first checked in
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;
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;
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;---------------------------------------------------------------------------
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TITLE 'USTSubtests.a'
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CASE OFF
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STRING PASCAL ; This is just to make sure that all the strings defined in this
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; file are created in Pascal format by the assembler. This is done
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; so that it will be easy for a controlling program to call the
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; Serial Test Manager, get the address of a name string, dereference
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; it to get the length, and download that many bytes through the
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; serial port. However, to appease the C people of the world (of which
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; I'm one), I'm going to leave the null terminators at the end of the
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; strings (I guess this would make them pcStrings). That way, other
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; shells such as the ATrap could work with C strings by ignoring the
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; leading length byte. 11/5/91
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PROC
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;
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; Import all of the subtests and the test
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;
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IMPORT USTMainTest ;THE ROM test
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IMPORT MapRamDataTest ;Mapper RAM data test
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IMPORT MapRamUniqTest ;Mapper RAM uniqueness test
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IMPORT VramDataTest ;Portable style VRAM data test
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IMPORT VramAddrTest ;Portable style VRAM address test
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IMPORT SCCRegTest ;SCC register test
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IMPORT SCCLoopTest ;SCC internal loopback test
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IMPORT SCCTimerTest ;SCC timer test
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IMPORT VIATest ;VIA test
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IMPORT TestSCSI ;SCSI test
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IMPORT TestASC ;ASC test
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IMPORT PramTest ;Parameter RAM test
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IMPORT TestRBV ;RAM Based Video controller test
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IMPORT TestSWIM ;SWIM chip test
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IMPORT Float_Test ;Floating point test
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IMPORT TestPGC ;PGC style parity test
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IMPORT FMCRegTest ;Fast Memory Controller register test
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IMPORT FMCCacheTest ;Fast Memory Controller Cache test
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IMPORT OSSRegTest ;Operating System Support chip register test
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IMPORT OSSIntTest ;Operating System Support interrupt test
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IMPORT RPUTest ;RPU style parity test
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IMPORT EgretTest ;Egret test
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IMPORT TestSndInts ;sound interrupts test
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IMPORT TestCLUT ;Color lookup table chip test
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IMPORT TestVRAM ;V8 style VRAM test
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IMPORT TestC96 ;53C96 Turbo SCSI chip test <T4>
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IMPORT TestGSCRegs ; GSC (Gray Scale Chip) register test
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IMPORT PGESelfTest ; PG&E (Power Manager ASIC for DBLite & others) self test
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IMPORT TestCSCRegs ; CSC (Color Support Chip) register test
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CASE ON
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IMPORT SONIC_Test ;SONIC Ethernet chip test <T4>
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IMPORT SONIC_BitMarch ;SONIC Ethernet register bitmarch subtest <T4>
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IMPORT SONIC_CAMDMA ;SONIC Ethernet on chip DMA subtest <T4>
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IMPORT SONIC_Loopback ;SONIC Ethernet loopback subtest <T4>
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CASE OFF
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;
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; Following is the one test which knows how to run all original non-critical tests (subtests)
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; in the ROM, and the only other real CTE-style test that is in the ROM, the SONIC test:
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;
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; NOTE: See the description of the subtest table (immediately following this test table)
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; for a running commentary on what the various fields mean, and what you can do to help.
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;
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EXPORT USTTests
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USTTests
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; test ID test entry point pointer to name of test code param result
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; size size size
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; (TTest_ID) (TEntryPtr) (TNamePtr) (TCodeSize) (TParamSize) (TResultSize)
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; ---------- ------------------- ----------------------- ---- ----- ------
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WITH USTTest, USTTestIDs
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USTTestItem (USTMainTest_ID, USTMainTest-USTTests, USTMainTest_Name-USTTests, 0, 0, 0)
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IF hasOrwell THEN ; <SM3> rb <SM7> rb
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CASE ON
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USTTestItem (SONIC_TEST_ID, SONIC_Test-USTTESTS, SONIC_TEST_NAME-USTTESTS, 0, 0, 0)
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CASE OFF
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ENDIF ; <SM3> rb
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USTTestItem ($FFFFFFFF, 0, 0, 0, 0, 0)
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ENDWITH
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USTMainTest_Name dc.b 'ROM based test (type 2)',0
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IF hasOrwell THEN ; <SM3> rb <SM7> rb
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SONIC_Test_Name dc.b 'SONIC Ethernet controller CTE Test',0 ;<T4>
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ENDIF ; <SM3> rb
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ALIGN 2 ;make sure we're still lined up after all that text ;<T4>
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;
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; Following is the table of RAM based test in the ROMs.
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; One or more subtest(s) can be installed and executed using the information in
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; this table. The need for the code size, param size and result size parameters
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; is this:
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;
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; code size - Not really useful for anything right now. There is no need to know
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; this as far as CTE is concerned. One possible use might be if the capability
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; to upload a test/subtest from the ROM to some other location (board tester,
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; through the Serial Test Manager to a host machine, etc.). However, since that
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; feature is not currently available, all of the code size params are 0.
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;
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; param size and result size - These are not necessary for the original ROM based
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; non-critical tests, because their results are returned in d6 (and that's all
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; there is to it). However, the SONIC and other real CTE DTMs have their own
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; result structures, and CTE will allocate the necessary memory for them when
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; the DTM is executed. These values should be plugged into the appropriate fields
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; of the testInfo and subtestInfo structures before calling GI_ExecuteDTM.
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;
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; You may be asking yourself, "How do I know what value to put in for these size
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; fields?". Well, it's like this: for the code size, you have to compile the
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; ROM, look at the ROM map, and calculate the length of the various routines.
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; You will then need to enter that value and re-compile so it will be in the ROM.
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; For the param size and result size, you just need to look at the structures
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; in the code, and calculate the number of bytes needed. You can do this before
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; you compile for the first time, if you wish.
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;
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; NOTE: The names in parentheses under the field descriptions are the actual
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; offsets that should be used to gain access to that field. For example, if
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; a3 was pointing to the first entry in the USTSubtests table, then
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; STSubtest_ID(a3) would give you the MapRamDataTest_ID.
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;
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EXPORT USTSubtests
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USTSubtests
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; subtest ID subtest entry point pointer to name of subtest code param result
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; size size size
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; (STSubtest_ID) (STEntryPtr) (STNamePtr) (STCodeSize) (STParamSize) (STResultSize)
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; ---------- ------------------- -------------------------- ---- ----- ------
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WITH USTSubtest, USTSubtestIDs
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USTSubtestItem (MapRamDataTest_ID, MapRamDataTest-USTSubtests, MapRamDataTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (MapRamUniqTest_ID, MapRamUniqTest-USTSubtests, MapRamUniqTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (VramDataTest_ID, VramDataTest-USTSubtests, VramDataTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (VramAddrTest_ID, VramAddrTest-USTSubtests, VramAddrTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (SCCRegTest_ID, SCCRegTest-USTSubtests, SCCRegTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (SCCLoopTest_ID, SCCLoopTest-USTSubtests, SCCLoopTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (SCCTimerTest_ID, SCCTimerTest-USTSubtests, SCCTimerTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (VIATest_ID, VIATest-USTSubtests, VIATest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (TestSCSI_ID, TestSCSI-USTSubtests, TestSCSI_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (TestASC_ID, TestASC-USTSubtests, TestASC_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (PramTest_ID, PramTest-USTSubtests, PramTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (TestRBV_ID, TestRBV-USTSubtests, TestRBV_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (TestSWIM_ID, TestSWIM-USTSubtests, TestSWIM_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (Float_Test_ID, Float_Test-USTSubtests, Float_Test_Name-USTSubtests, 0, 0, 0)
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IF hasFMC THEN ; <SM3> rb <SM7> rb
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USTSubtestItem (TestPGC_ID, TestPGC-USTSubtests, TestPGC_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (FMCRegTest_ID, FMCRegTest-USTSubtests, FMCRegTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (FMCCacheTest_ID, FMCCacheTest-USTSubtests, FMCCacheTest_Name-USTSubtests, 0, 0, 0)
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ENDIF
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IF hasOss THEN
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USTSubtestItem (OSSRegTest_ID, OSSRegTest-USTSubtests, OSSRegTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (OSSIntTest_ID, OSSIntTest-USTSubtests, OSSIntTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (RPUTest_ID, RPUTest-USTSubtests, RPUTest_Name-USTSubtests, 0, 0, 0)
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ENDIF ; <SM3> rb
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USTSubtestItem (EgretTest_ID, EgretTest-USTSubtests, EgretTest_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (TestSndInts_ID, TestSndInts-USTSubtests, TestSndInts_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (TestCLUT_ID, TestCLUT-USTSubtests, TestCLUT_Name-USTSubtests, 0, 0, 0)
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USTSubtestItem (TestVRAM_ID, TestVRAM-USTSubtests, TestVRAM_Name-USTSubtests, 0, 0, 0)
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IF hasSCSI96 THEN ; <SM3> rb
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|
|
USTSubtestItem (TestC96_ID, TestC96-USTSubtests, TestC96_Name-USTSubtests, 0, 0, 0) ;<T4>
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasPwrControls THEN
|
||
|
|
|
||
|
|
USTSubtestItem (TestGSCRegs_ID, TestGSCRegs-USTSubtests, TestGSCRegs_Name-USTSubtests, 0, 0, 0) ;<T4>
|
||
|
|
USTSubtestItem (PGESelfTest_ID, PGESelfTest-USTSubtests, PGESelfTest_Name-USTSubtests, 0, 0, 0) ;<T4>
|
||
|
|
USTSubtestItem (TestCSCRegs_ID, TestCSCRegs-USTSubtests, TestCSCRegs_Name-USTSubtests, 0, 0, 0) ;<H27>
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasOrwell THEN
|
||
|
|
|
||
|
|
CASE ON
|
||
|
|
USTSubtestItem (SONIC_BITMARCH_ID, SONIC_BitMarch-USTSUBTESTS, SONIC_BITMARCH_NAME-USTSUBTESTS, 0, $0C, $2C) ;<T4>
|
||
|
|
USTSubtestItem (SONIC_CAMDMA_ID, SONIC_CAMDMA-USTSUBTESTS, SONIC_CAMDMA_NAME-USTSUBTESTS, 0, $1C, $18) ;<T4>
|
||
|
|
USTSubtestItem (SONIC_LOOPBACK_ID, SONIC_Loopback-USTSUBTESTS, SONIC_LOOPBACK_NAME-USTSUBTESTS, 0, $80, $2C) ;<T4>
|
||
|
|
CASE OFF
|
||
|
|
|
||
|
|
ENDIF ; <SM3> rb
|
||
|
|
|
||
|
|
USTSubtestItem ($FFFFFFFF, 0, 0, 0, 0, 0) ; Signifies the end of this table.
|
||
|
|
|
||
|
|
ENDWITH
|
||
|
|
|
||
|
|
;
|
||
|
|
; The following name strings describe each element in the test table above.
|
||
|
|
;
|
||
|
|
|
||
|
|
MapRamDataTest_Name dc.b 'Portable mapper RAM data',0 ;<T5>
|
||
|
|
MapRamUniqTest_Name dc.b 'Portable mapper RAM uniqueness',0 ;<T5>
|
||
|
|
VramDataTest_Name dc.b 'Portable VRAM data',0
|
||
|
|
VramAddrTest_Name dc.b 'Portable VRAM address',0
|
||
|
|
SCCRegTest_Name dc.b 'Serial Communications Controller register',0 ;<T5>
|
||
|
|
SCCLoopTest_Name dc.b 'Serial Communications Controller internal loopback',0 ;<T5>
|
||
|
|
SCCTimerTest_Name dc.b 'Serial Communications Controller timer',0 ;<T5>
|
||
|
|
VIATest_Name dc.b 'Versatile Interface Adapter',0 ;<T5>
|
||
|
|
TestSCSI_Name dc.b 'SCSI chip register',0 ;<T5>
|
||
|
|
TestASC_Name dc.b 'Sound chip register',0 ;<T5>
|
||
|
|
PramTest_Name dc.b 'Parameter RAM',0 ;<T5>
|
||
|
|
TestRBV_Name dc.b 'RAM Based Video controller register',0 ;<T5>
|
||
|
|
TestSWIM_Name dc.b 'Floppy controller chip',0 ;<T5>
|
||
|
|
Float_Test_Name dc.b 'Floating point unit',0 ;<T5>
|
||
|
|
|
||
|
|
IF hasFMC THEN ; <SM3> rb
|
||
|
|
|
||
|
|
TestPGC_Name dc.b 'IIci type parity',0 ;<T5>
|
||
|
|
FMCRegTest_Name dc.b 'Fast Memory Controller register',0 ;<T5>
|
||
|
|
FMCCacheTest_Name dc.b 'Fast Memory Controller cache',0 ;<T5>
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasOss THEN
|
||
|
|
|
||
|
|
OSSRegTest_Name dc.b 'Operating System Support chip register',0 ;<T5>
|
||
|
|
OSSIntTest_Name dc.b 'Operating System Support chip interrupt',0 ;<T5>
|
||
|
|
RPUTest_Name dc.b 'IIfx type parity',0 ;<T5>
|
||
|
|
|
||
|
|
ENDIF ; <SM3> rb
|
||
|
|
|
||
|
|
EgretTest_Name dc.b 'Apple Desktop Bus microcontroller self',0 ;<T5>
|
||
|
|
TestSndInts_Name dc.b 'Sound interrupt',0
|
||
|
|
TestCLUT_Name dc.b 'Color lookup table',0
|
||
|
|
TestVRAM_Name dc.b 'Video RAM',0
|
||
|
|
|
||
|
|
IF hasSCSI96 THEN ; <SM3> rb
|
||
|
|
|
||
|
|
TestC96_Name dc.b '53C96 Turbo SCSI chip',0 ;<T4>
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasPwrControls THEN
|
||
|
|
|
||
|
|
TestGSCRegs_Name dc.b 'GSC registers',0
|
||
|
|
TestCSCRegs_Name dc.b 'CSC registers',0 ;<H27>
|
||
|
|
PGESelfTest_Name dc.b 'PG&E self test'
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasOrwell THEN
|
||
|
|
|
||
|
|
SONIC_BitMarch_NAME dc.b 'SONIC Ethernet register bitmarch',0 ;<T4>
|
||
|
|
SONIC_CAMDMA_NAME dc.b 'SONIC Ethernet on-chip DMA',0 ;<T4>
|
||
|
|
SONIC_Loopback_NAME dc.b 'SONIC Ethernet protocol loopback',0 ;<T4>
|
||
|
|
|
||
|
|
ENDIF ; <SM3> rb
|
||
|
|
|
||
|
|
ALIGN 2
|
||
|
|
|
||
|
|
;
|
||
|
|
; The following table lists all of the available machine specific test tables and
|
||
|
|
; the box flag of the machine for which they apply.
|
||
|
|
;
|
||
|
|
; This table is terminated with a box unknown element. The cpu specific table for
|
||
|
|
; box unknown contains the tests which were present before these tables were implemented
|
||
|
|
; in the ROMs.
|
||
|
|
;
|
||
|
|
|
||
|
|
EXPORT USTCPUList
|
||
|
|
|
||
|
|
USTCPUList
|
||
|
|
|
||
|
|
IF hasMDU THEN ; <SM3> rb
|
||
|
|
|
||
|
|
CPUListItem (BoxMacIIsi, MacIIsiTests-USTCPUList)
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasOrwell THEN
|
||
|
|
|
||
|
|
CPUListItem (boxQuadra900, Quadra900Tests-USTCPUList)
|
||
|
|
CPUListItem (boxQuadra700, Quadra700Tests-USTCPUList)
|
||
|
|
CPUListItem (boxQuadra950, Quadra900Tests-USTCPUList) ;<Z8><H3>
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasJaws THEN
|
||
|
|
|
||
|
|
CPUListItem (boxPowerBook170, PowerBook170Tests-USTCPUList)
|
||
|
|
ENDIF ; <SM3> rb
|
||
|
|
|
||
|
|
IF hasVISADecoder THEN
|
||
|
|
|
||
|
|
CPUListItem (boxMacLCII, MacLCTests-USTCPUList) ;<SM5>
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasMSC THEN ; <SM3> rb
|
||
|
|
|
||
|
|
CPUListItem (boxPowerBookDuo210,DBLiteTests-USTCPUList) ;<H12>
|
||
|
|
CPUListItem (boxPowerBookDuo230,DBLiteTests-USTCPUList) ;<H12>
|
||
|
|
CPUListItem (boxPowerBookDuo250,DBLiteTests-USTCPUList) ;<H12>
|
||
|
|
CPUListItem (boxDBLite20,DBLiteTests-USTCPUList) ;<H12>
|
||
|
|
CPUListItem (boxYeagerC , YeagerTests-USTCPUList) ;
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasSonora THEN
|
||
|
|
|
||
|
|
CPUListItem (boxLCIII, VailTests-USTCPUList) ; <SM11>
|
||
|
|
CPUListItem (boxVail16, VailTests-USTCPUList) ;
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasDJMEMC THEN
|
||
|
|
|
||
|
|
CPUListItem (boxWombat20, WombatTests-USTCPUList) ; <H18><SM6>
|
||
|
|
CPUListItem (boxCentris650, WombatTests-USTCPUList) ; <H13><SM6><SM11>
|
||
|
|
IF forSmurf THEN
|
||
|
|
CPUListItem (boxRiscCentris650, WombatTests-USTCPUList) ; <SM9>
|
||
|
|
ENDIF
|
||
|
|
CPUListItem (boxQuadra650, WombatTests-USTCPUList) ; <H13><SM6><SM11>
|
||
|
|
CPUListItem (boxQuadra800, WombatTests-USTCPUList) ; <H13><H14><SM6>
|
||
|
|
CPUListItem (boxWombat40, WombatTests-USTCPUList) ; <H13><SM6>
|
||
|
|
CPUListItem (boxWombat40F, WombatTests-USTCPUList) ; <H13><H18><SM6>
|
||
|
|
CPUListItem (boxCentris610, WombatTests-USTCPUList) ; <H13><SM6>
|
||
|
|
CPUListItem (boxQuadra610, WombatTests-USTCPUList) ; <H13><SM6>
|
||
|
|
CPUListItem (boxWLCD33, WombatTests-USTCPUList) ; <H13><SM6><SM11>
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasNiagra THEN
|
||
|
|
|
||
|
|
CPUListItem (boxPowerBook180, DartTests-USTCPUList) ; <H15><SM6>
|
||
|
|
CPUListItem (boxPowerBook160, DartTests-USTCPUList) ; <H15><SM6>
|
||
|
|
|
||
|
|
ENDIF ; <SM3> rb
|
||
|
|
|
||
|
|
IF hasPratt THEN
|
||
|
|
|
||
|
|
CPUListItem (boxBlackbird, BlackBirdTests-USTCPUList) ; <H15><SM6>
|
||
|
|
CPUListItem (boxBlackbirdLC, BlackBirdTests-USTCPUList) ; <H15><SM6>
|
||
|
|
|
||
|
|
ENDIF ; <SM3> rb
|
||
|
|
|
||
|
|
CPUListItem (boxUnknown, UnknownTests-USTCPUList)
|
||
|
|
|
||
|
|
;
|
||
|
|
; Following are machine specific test tables. These tables contain a list of the subtest
|
||
|
|
; IDs which apply to each machine.
|
||
|
|
;
|
||
|
|
; Each table is terminated with a long word of all Fs
|
||
|
|
;
|
||
|
|
|
||
|
|
; For revision <T4> - added test ID to each entry in the table below. At the same time
|
||
|
|
; I changed the subtest ID from a long to a word, so there is no net increase in space
|
||
|
|
; for these tables. Also in <T4> - added the C96 and VRAM test to the Quadra 700 and 900
|
||
|
|
; test dependant tables.
|
||
|
|
|
||
|
|
WITH RunBits, USTSubtestIDs, USTTestIDs, CPUTestList
|
||
|
|
|
||
|
|
IF hasMDU THEN ; <SM3> rb
|
||
|
|
|
||
|
|
EXPORT MacIIsiTests
|
||
|
|
|
||
|
|
; TLTest_ID TLSubTest_ID TLrunflags TLModifier
|
||
|
|
; --------- ------------ ---------- ----------
|
||
|
|
|
||
|
|
MacIIsiTests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,PramTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestRBV_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSWIM_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,EgretTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestCLUT_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0)
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasOrwell THEN
|
||
|
|
|
||
|
|
Quadra900Tests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,EgretTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,PramTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestC96_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (SONIC_Test_ID, SONIC_BitMarch_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (SONIC_Test_ID, SONIC_CAMDMA_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (SONIC_Test_ID, SONIC_Loopback_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0)
|
||
|
|
|
||
|
|
Quadra700Tests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSWIM_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,PramTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestC96_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (SONIC_Test_ID, SONIC_BitMarch_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (SONIC_Test_ID, SONIC_CAMDMA_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (SONIC_Test_ID, SONIC_Loopback_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0)
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasJaws THEN
|
||
|
|
|
||
|
|
PowerBook170Tests
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI, 0) ;<T6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSWIM_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,PramTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0)
|
||
|
|
|
||
|
|
ENDIF ; <SM3> rb
|
||
|
|
|
||
|
|
IF hasVISADecoder THEN
|
||
|
|
|
||
|
|
EXPORT MacLCTests
|
||
|
|
|
||
|
|
MacLCTests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,PramTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestRBV_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSWIM_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,EgretTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestCLUT_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI | Startup | Restart, 0)
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0)
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
|
||
|
|
IF hasMSC THEN ; <SM3> rb
|
||
|
|
|
||
|
|
EXPORT DBLiteTests
|
||
|
|
|
||
|
|
DBLiteTests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0) ;<H3>
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CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0) ;<H3>
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CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0) ;<H3>
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CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0) ;<H3>
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CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI , 0) ;<H3>
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CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0) ;<H3><H17><SM6>
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||
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CPUTestListItem (USTMainTest_ID,TestGSCRegs_ID, STM | ATrap | RBI, 0) ;<H3><H17><SM6>
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||
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CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI | Startup, 0) ;<H3><SM6>
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CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI | Startup, 0) ;<H3><SM6>
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CPUTestListItem (USTMainTest_ID,PGESelfTest_ID, STM | ATrap | RBI, 0) ;<H3><H17><SM6>
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||
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CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0) ;<H3><H17><SM6>
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CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0) ;<H2>
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EXPORT YeagerTests
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YeagerTests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI, 0) ;<H25>
|
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CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI, 0) ;
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CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI, 0) ;
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CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI, 0) ;
|
||
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CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI, 0) ;
|
||
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CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI, 0) ;
|
||
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CPUTestListItem (USTMainTest_ID,TestCSCRegs_ID, STM | ATrap | RBI, 0) ;<H27>
|
||
|
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CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI, 0) ;
|
||
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;;; CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI, 0) ;<H26>
|
||
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CPUTestListItem (USTMainTest_ID,PGESelfTest_ID, STM | ATrap | RBI, 0) ;
|
||
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CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0) ;
|
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CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0) ;
|
||
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|
|
||
|
|
ENDIF
|
||
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|
||
|
|
IF hasPratt THEN ;
|
||
|
|
EXPORT BlackBirdTests
|
||
|
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|
||
|
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BlackBirdTests
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI, 0) ;
|
||
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CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI, 0) ;
|
||
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CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI, 0) ;
|
||
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CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI, 0) ;
|
||
|
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CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI, 0) ;
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestCSCRegs_ID, STM | ATrap | RBI, 0) ;
|
||
|
|
CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI, 0) ;
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI, 0) ;
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0) ;
|
||
|
|
EndIf
|
||
|
|
|
||
|
|
IF hasSonora THEN
|
||
|
|
|
||
|
|
EXPORT CarnationTests
|
||
|
|
|
||
|
|
CarnationTests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,PramTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestRBV_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSWIM_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,EgretTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestCLUT_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0)
|
||
|
|
|
||
|
|
EXPORT VailTests
|
||
|
|
|
||
|
|
VailTests
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,PramTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestRBV_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSWIM_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,EgretTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestCLUT_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI | Startup | Restart, 0)
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0)
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasDJMEMC THEN
|
||
|
|
|
||
|
|
EXPORT WombatTests ; <H13> thru next <H13><SM3>
|
||
|
|
|
||
|
|
WombatTests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0) ;<SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0) ;<SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0) ;<SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0) ;<SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0) ;<SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSWIM_ID, STM | ATrap | RBI | Startup, 0) ;<SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI, 0) ;<SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0) ;<SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,PramTest_ID, STM | ATrap | RBI, 0) ;<SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestC96_ID, STM | ATrap | RBI, 0) ;<SM6>
|
||
|
|
CPUTestListItem (SONIC_Test_ID, SONIC_BitMarch_ID, STM | ATrap | RBI, 0) ;<SM6>
|
||
|
|
CPUTestListItem (SONIC_Test_ID, SONIC_CAMDMA_ID, STM | ATrap | RBI, 0) ;<SM6>
|
||
|
|
CPUTestListItem (SONIC_Test_ID, SONIC_Loopback_ID, STM | ATrap | RBI, 0) ;<SM6>
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0) ;<SM6>
|
||
|
|
; <H13><SM3>
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
IF hasNiagra THEN
|
||
|
|
|
||
|
|
EXPORT DartTests ;<H15><SM3>
|
||
|
|
|
||
|
|
DartTests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI , 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0) ;<H15><SM6>
|
||
|
|
;•••• CPUTestListItem (USTMainTest_ID,TestGSCRegs_ID, STM | ATrap | RBI | Startup, 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSWIM_ID, STM | ATrap | RBI | Startup, 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI | Startup, 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI | Startup, 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0) ;<H15><SM6>
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0) ;<H15><SM6>
|
||
|
|
ENDIF ; <SM3> rb
|
||
|
|
|
||
|
|
EXPORT UnknownTests
|
||
|
|
|
||
|
|
UnknownTests CPUTestListItem (USTMainTest_ID,SCCRegTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCTimerTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,SCCLoopTest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
CPUTestListItem (USTMainTest_ID,VIATest_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,TestSCSI_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,TestASC_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,TestRBV_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,TestSWIM_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,Float_Test_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,TestPGC_ID, STM | ATrap | RBI | Startup, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,FMCRegTest_ID, STM | ATrap | RBI | Startup, 0) ; <T7>
|
||
|
|
;CPUTestListItem (USTMainTest_ID,FMCCacheTest_ID, STM | ATrap | RBI | Startup, 0) ; <T7>
|
||
|
|
;CPUTestListItem (USTMainTest_ID,OSSRegTest_ID, STM | ATrap | RBI | Startup, 0) ; <T7>
|
||
|
|
;CPUTestListItem (USTMainTest_ID,OSSIntTest_ID, STM | ATrap | RBI | Startup, 0) ; <T7>
|
||
|
|
;CPUTestListItem (USTMainTest_ID,RPUTest_ID, STM | ATrap | RBI | Startup, 0) ; <T7>
|
||
|
|
|
||
|
|
;CPUTestListItem (USTMainTest_ID,PramTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,EgretTest_ID, STM | ATrap | RBI, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,TestSndInts_ID, STM | ATrap | RBI, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,TestCLUT_ID, STM | ATrap | RBI, 0)
|
||
|
|
;CPUTestListItem (USTMainTest_ID,TestVRAM_ID, STM | ATrap | RBI, 0)
|
||
|
|
|
||
|
|
CPUTestListItem ($FFFFFFFF,$FFFFFFFF, 0, 0)
|
||
|
|
|
||
|
|
|
||
|
|
ENDWITH
|
||
|
|
|
||
|
|
ENDPROC
|
||
|
|
|