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https://github.com/elliotnunn/supermario.git
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221 lines
8.3 KiB
Plaintext
221 lines
8.3 KiB
Plaintext
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; File: MMUPatches.a
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;
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; Contains: patches to the MMU traps (the only one I know is SwapMMUMode)
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;
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; Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <5> 7/15/92 DTY #1036002 <gbm>: The InstallSwapPMMU should only be installed in
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; 24 bit mode. Normally, always installing this on a Mac II is OK,
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; since the Mac II normally only works in 24 bit mode. However,
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; with Scruffy, the Mac II could be in 32 bit mode, and in this
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; case, this InstallProc shouldn’t be executed.
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; <4> 2/12/92 JSM Moved this file to MMU folder, keeping all the old revisions.
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; <3> 10/8/90 JDR change hasPMMUNoVM to hasPMMU and notVM
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; <2> 8/18/90 dba put SwapHMMU and SwapPMMU in here
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; <1> 8/2/90 dba first checked in
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;
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load 'StandardEqu.d'
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include 'HardwarePrivateEqu.a'
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include 'MMUEqu.a'
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include 'LinkedPatchMacros.a'
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;————————————————————————————————————————————————————————————————————————————————————————————————————
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; SwapMMUMode — version for 24-bit only machines
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machine mc68000
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DontDoMuchSwappingOfTheMMUMode PatchProc _SwapMMUMode,(Plus,SE,Portable)
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moveq #0,d0
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rts
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EndProc
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;————————————————————————————————————————————————————————————————————————————————————————————————————
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; SwapMMUMode — version for the II with HMMU
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machine mc68020
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ROMs II,hasHMMU,notAUX
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MakePatch SwapHMMU,jSwapMMU
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MakePatch SwapHMMU,_SwapMMUMode
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; SwapHMMU - switches HMMU between 24 & 32 bit modes.
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;
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; This patch fixes the problems of losing sound interrupts when switching
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; MMU modes. On HMMU Mac IIs, a bit on Via2 portB switches the MMU mode.
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; Unfortunately, hitting this bit clears the CB1 interrupt flag, which is
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; the ASC interrupt.
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;
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; Since the interrupt handlers all call SwapMMUMode to switch into 24 bit mode
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; before processing interrutps, an ASC interrupt that occurs after the
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; original interrupt could be lost.
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;
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; This patch reduces the window for losing ASC interrupts to the minimum
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; possible, which is half an instruction. After switching MMU modes,
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; it checks the ASC’s interrupt register, and if any interrupts are present
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; (but lost because the CB1 flag was cleared), it ORs the interrupt register back
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; to itself. The ASC then generates a new interrupt.
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;
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; Entry
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; d0.b 0 to set 24-bit mode, non-zero to set 32-bit mode.
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;
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; Exit
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; MMU32Bit updated with passed value of d0
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; d0.l has previous value of MMU32Bit
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; MMU is switched into the desired mode
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;
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; Trashes:
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; d1/a0
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SwapHMMU Proc Export
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if &type('vBase2') = 'UNDEFINED' then
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vBase2: equ $50F02000 ; this Proc is for the Macintosh II only
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endif
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if &type('AscInt') = 'UNDEFINED' then
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AscInt: equ $804 ; offset to ASC’s interrupt register
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endif
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move.b d0,d1 ; check what mode desired, save it
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bne.s @to32 ; IF we want 24 bit mode
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moveq #0,d0 ; clear return register
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move.b MMU32bit,d0 ; see what mode we’re in now
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beq.s @done ; IF in 32 bit mode now
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move sr,-(sp) ; save current interrupt status
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ori #HiIntMask,sr ; disable interrupts during switch
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andi.b #-1-(1<<vFC3),vBase2+vBufB;throw us into 24 bit mode
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bra.s @common ; (re-use common code)
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@to32 ; ELSE (we want 32 bit mode)
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moveq #0,d0 ; clear return register
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move.b MMU32bit,d0 ; see (and return) what mode we’re in now
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bne.s @done ; IF in 24 bit mode now
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move sr,-(sp) ; save current interrupt status
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ori #HiIntMask,sr ; disable interrupts during switch
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ori.b #1<<vFC3,VBase2+vBufB; throw us into 32 bit mode
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@common move.b d1,MMU32Bit ; update global w/new mode flag
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movec cacr,d1 ; get cache control register
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ori.w #$0808,d1 ; set icache, dcache (in case) flush bits <1.1>
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movec d1,cacr ; flush da cache, Guido
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move.l ASCBase,a0 ; point to ASC
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adda.w #AscInt,a0 ; point to ASC interrupt register
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move.b (a0),d1 ; get ASC interrupt register
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beq.s @doneASC ; IF ASC thinks interrupt is pending
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tst.b vBase2+vier ; try to synch VIA so it catches the edge
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or.b d1,(a0) ; re-generate interrupt to VIA’s CB1
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@doneASC ; ENDIF
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move (sp)+,sr ; restore interrupt mask
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; ENDIF
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@done ; ENDIF
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rts
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EndProc
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;————————————————————————————————————————————————————————————————————————————————————————————————————
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; SwapMMUMode — version for the II with PMMU
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machine mc68020
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mc68851
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ROMs II,hasPMMU,notVM,notAUX,using24BitHeaps
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; This install code fills the MMUInfo table in from the existing MMU configuration.
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;
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; Possible optimizations of the MMU setup might be to use the tt0 & tt1 registers
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; on 68030 based machines.
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InstallSwapPMMU InstallProc
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Import MMUInfo
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With MMUConfigInfo
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lea MMUInfo,a0 ; point at buffer for config info
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pmove crp,theCRP(a0) ; get current 24 bit mode CRP
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pmove tc,theTC(a0) ; get current 24 bit mode tc
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moveq #true32b,d0 ; where we’re going
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_SwapMMUMode ; switch to 32 bit mode
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pmove crp,MMUInfoSize+theCRP(a0) ; get current 32 bit mode CRP
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pmove tc,MMUInfoSize+theTC(a0) ; get current 32 bit mode tc
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_SwapMMUMode ; go back to old mode
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move sr,-(sp) ; save interrupt mask
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ori #HiIntMask,sr ; no interrupts while changing lowmems
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move.l a0,MMU24Info ; save ptr to 24 bit mode info
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lea MMUInfoSize(a0),a0 ; point at 32 bit mode info
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move.l a0,MMU32Info ; save ptr to 32 bit mode info
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move (sp)+,sr ; restore interrupt mask
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rts
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EndWith
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EndProc
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MakePatch SwapPMMU,jSwapMMU
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MakePatch SwapPMMU,_SwapMMUMode
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; SwapPMMU - switches PMMU between 24 & 32 bit modes.
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;
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; This patch is just a more efficient version of SwapMMUMode that ONLY deals with
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; PMMUs. It eliminates the ROM version’s overhead of checking for the HMMU.
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;
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; Entry
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; d0.b 0 to set 24-bit mode, non-zero to set 32-bit mode.
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;
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; Exit
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; MMU32Bit updated with passed value of d0
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; d0.l has previous value of MMU32Bit
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; MMU is switched into the desired mode
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;
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; Trashes:
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; d1/a0
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SwapPMMU Proc Export
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Entry MMUInfo
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With MMUConfigInfo
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move.b d0,d1 ; check what mode we are going to, set up d1
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bne.s @to32 ; IF we want 24 bit mode
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moveq #0,d0 ; clear return register
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move.b MMU32bit,d0 ; see what mode we’re in now
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beq.s @endif ; IF in 32 bit mode now
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move.l MMU24Info,a0 ; get ptr to 24 bit mode info
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bra.s @swap ; go to common swap code
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; ENDIF
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@to32 ; ELSE (we want 32 bit mode)
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moveq #0,d0 ; clear return register
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move.b MMU32bit,d0 ; see what mode we’re in now
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bne.s @endif ; IF in 24 bit mode
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move.l MMU32Info,a0 ; get ptr to 32 bit mode info
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@swap move sr,-(sp) ; save current interrupt status
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ori #HiIntMask,sr ; disable interrupts during switch
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pmove theCRP+2(a0),tc ; disable translation temporarily
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pmove theCRP(a0),crp ; set crp
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pmove theTC(a0),tc ; fire up the TC
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move.b d1,MMU32Bit ; update global w/new mode flag
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movec cacr,d1 ; get cache control register
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ori.w #$0808,d1 ; set 'flush' bits
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movec d1,cacr ; flush both caches
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move (sp)+,sr ; restore interrupt mask
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; ENDIF
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@endif ; ENDIF
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rts
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MMUInfo dcb.l MMUInfoSize*2,0 ; place for MMU config info
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EndWith
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EndProc
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;————————————————————————————————————————————————————————————————————————————————————————————————————
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End
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