mirror of
https://github.com/elliotnunn/supermario.git
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320 lines
9.9 KiB
Plaintext
320 lines
9.9 KiB
Plaintext
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; File: HALc96GC.a
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; Contains: Grand Central SCSI HBA
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;
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; Written by: Craig Prouse
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;
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; Copyright: © 1993 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM2> 11/19/93 chp Add primitives for clearing, enabling, and disabling SCSI IRQ.
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; Add a primitive for testing SCSI IE.
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; <SMG2> 10/26/93 chp Adjust for changes in DBDMA and Grand Central header files.
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;
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;
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case on
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print push,off
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include 'DBDMA.a'
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include 'ACAM.a'
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include 'HALc96equ.a'
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print pop
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machine mc68020
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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; StartGC:
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;
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; In: A5 pointer to HALc96GlobalRecord
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; (SP) stack-based arguments
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;
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; Initiate DMA.
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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StartGC proc export
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saveRegs reg d1-d3
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maxAtomicCount equ $FFF0 ; maximum atomic DMA transfer count
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StackFrame record {a6Link},decrement
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dirRead ds.w 1 ; direction is read (16-bit Boolean)
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byteCount ds.l 1 ; number of bytes to transfer
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bufferAddr ds.l 1 ; source/destination buffer for transfer
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rtsAddr ds.l 1
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a6Link ds.l 1
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localSize equ *
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endr
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with HALc96GlobalRecord, StackFrame
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link a6,#localSize
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movem.l saveRegs,-(sp)
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; A0 is set initially to the address of the first channel command descriptor.
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movea.l cclLogicalAddr(a5),a0 ; pointer to DBDMA command list buffer
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; D3 will contain the command word for a list of input or output channel commands.
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tst.w dirRead(a6)
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bne.b @input
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@output move.w #OUTPUT_MORE,d3
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bra.b @ioCommon
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@input move.w #INPUT_MORE,d3
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; A single DB-DMA channel command can transfer at most $FFFF bytes since the count
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; field is 16 bits. The 53C9x can only DMA an even number of bytes, producing an
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; effective limit of $FFFE bytes. For the sake of roundness, this CCL shall not
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; contain any commands for more than $FFF0 bytes. The channel command list is
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; generated using as many descriptors as necessary to satisfy the request. The CCL
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; buffer is one physical page (8K) in length, allowing for up to 511 data transfer
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; descriptors, or nearly 32 MB in a single request. There is no range checking.
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@ioCommon
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move.l #maxAtomicCount,d0
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movea.l bufferAddr(a6),a1 ; DMA address in A1
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move.l byteCount(a6),d2 ; remaining DMA count in D2
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bra.b @loopTest
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@partialIOCmd swap d0
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move.w d3,d0 ; command in high word of D0
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swap d0 ; count in low word of D0
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_MakeCCDescriptor
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adda.w #DBDMADescriptor.size,a0
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move.l #maxAtomicCount,d0
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adda.l d0,a1 ; increment transfer address
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sub.l d0,d2 ; decrement remaining transfer count
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@loopTest beq.b @stopCmd ; generate STOP immediately when count = 0
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cmp.l d0,d2
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bhi.b @partialIOCmd
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@lastIOCmd move.w d3,d0
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swap d0 ; command in high word of D0
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move.w d2,d0 ; remaining count in low word of D0
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_MakeCCDescriptor
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adda.w #DBDMADescriptor.size,a0
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@stopCmd move.l #(STOP<<16) | $0000,d0 ; stop command / count field is reserved
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lea 0,a1 ; address field is reserved
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_MakeCCDescriptor
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; Point the DMA hardware at the new CCL.
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movea.l dmaCntrlAddr(a5),a0 ; pointer to SCSIx DBDMAChannelRegisters in A0
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move.l cclPhysicalAddr(a5),d0 ; pointer to channel command list in D0
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_SetCommandPtr
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; Reset anything wrong with the channel status and start it running.
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move.l # kdbdmaSetRun |\
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kdbdmaClrPause |\
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kdbdmaClrHalted |\
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kdbdmaClrDead |\
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kdbdmaSetActive, d0
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_SetChannelControl ; A0 still points to DBDMAChannelRegisters
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movem.l (sp)+,saveRegs
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unlk a6
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rts
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endwith
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endproc
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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; StopGCRead:
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; StopGCWrite:
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; Wt4GCComplete:
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;
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; In: A5 pointer to HALc96GlobalRecord
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; Out: D0.L residual count
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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StopGCDMA func entry
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export StopGCRead, StopGCWrite, Wt4GCComplete
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saveRegs reg d1/d2
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with HALc96GlobalRecord
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StopGCRead
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StopGCWrite
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movea.l dmaCntrlAddr(a5),a0 ; pointer to SCSIx DBDMAChannelRegisters in A0
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move.l #kdbdmaClrRun,d0
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_SetChannelControl ; abort the CCL
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Wt4GCComplete
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movea.l dmaCntrlAddr(a5),a0 ; pointer to SCSIx DBDMAChannelRegisters in A0
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@waitInactive _GetChannelStatus ; wait for last status writeback
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andi.l #kdbdmaActive,d0
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bne.b @waitInactive
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; For better or for worse, channel command execution has stopped. It is now time to
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; calculate the residual count. This is just a little bit complicated because it is
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; not known exactly how many command descriptors in the list completed execution.
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movem.l saveRegs,-(sp)
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moveq #0,d2 ; accumulate residual count in D2
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movea.l cclLogicalAddr(a5),a0 ; this is where CCL execution started
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@nextDescriptor
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_GetCCOperation
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cmpi.l #(STOP<<16) | $0000,d0 ; is this the end-of-list?
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beq.b @done
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move.l d0,d1 ; save the request count
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_GetCCResult
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tst.l d0 ; did a status writeback occur?
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bne.b @addResidual ; yes, use residual count field
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move.l d1,d0 ; no, use request count field
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@addResidual and.l #$0000FFFF,d0 ; mask off xferStatus
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add.l d0,d2 ; accumulate residual count
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adda.w #DBDMADescriptor.size,a0 ; increment to next descriptor
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bra.b @nextDescriptor
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@done
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move.l d2,d0 ; move total residual count to D0 result
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movem.l (sp)+,saveRegs
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rts
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endwith
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endfunc
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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; ClearGCSCSIIRQ:
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;
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; In: A5 pointer to HALc96GlobalRecord
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;
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; This routine may not change any registers.
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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ClearGCSCSIIRQ proc entry
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intClearOffset equ gcInterruptClear - gcInterruptMask
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with HALc96GlobalRecord
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align 8
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export ClearGCSCSI0IRQ
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ClearGCSCSI0IRQ:
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ori.l #1 << gcifDevSCSI0,([intEnableSCSIAddr,a5],intClearOffset)
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rts
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align 8
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export ClearGCSCSI1IRQ
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ClearGCSCSI1IRQ:
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ori.l #1 << gcifDevSCSI1,([intEnableSCSIAddr,a5],intClearOffset)
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rts
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endwith
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endproc
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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; EnableGCSCSIIRQ:
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;
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; In: A5 pointer to HALc96GlobalRecord
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;
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; This routine may not change any registers.
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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EnableGCSCSIIRQ proc entry
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with HALc96GlobalRecord
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align 8
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export EnableGCSCSI0IRQ
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EnableGCSCSI0IRQ:
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ori.l #1 << gcifDevSCSI0,([intEnableSCSIAddr,a5])
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rts
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align 8
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export EnableGCSCSI1IRQ
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EnableGCSCSI1IRQ:
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ori.l #1 << gcifDevSCSI1,([intEnableSCSIAddr,a5])
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rts
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endwith
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endproc
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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; DisableGCSCSIIRQ:
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;
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; In: A5 pointer to HALc96GlobalRecord
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;
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; This routine may not change any registers.
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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DisableGCSCSIIRQ proc entry
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with HALc96GlobalRecord
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align 8
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export DisableGCSCSI0IRQ
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DisableGCSCSI0IRQ:
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andi.l #~(1 << gcifDevSCSI0),([intEnableSCSIAddr,a5])
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rts
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align 8
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export DisableGCSCSI1IRQ
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DisableGCSCSI1IRQ:
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andi.l #~(1 << gcifDevSCSI1),([intEnableSCSIAddr,a5])
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rts
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endwith
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endproc
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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; TestGCSCSIIE:
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;
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; In: A5 pointer to HALc96GlobalRecord
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; Out: CCR Z flag indicates state of the SCSI interrupt enable
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;
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; This routine may use D0.
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; ……………………………………………………………………………………………………………………………………………………………………………………………………………………
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TestGCSCSIIE proc entry
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with HALc96GlobalRecord
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align 8
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export TestGCSCSI0IE
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TestGCSCSI0IE:
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move.l #1 << gcifDevSCSI0,d0
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and.l ([intEnableSCSIAddr,a5]),d0
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rts
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align 8
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export TestGCSCSI1IE
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TestGCSCSI1IE:
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move.l #1 << gcifDevSCSI1,d0
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and.l ([intEnableSCSIAddr,a5]),d0
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rts
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endwith
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endproc
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end
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