supermario/base/SuperMarioProj.1994-02-09/OS/SCSIMgr4pt3/HALc96equ.a

;__________________________________________________________________________________________________
;
;	File:		HALc96equ.a
;
;	Contains:	HALc96 private equates, variables and data structures
;
;	Written by:	Paul Wolf
;
;	Copyright © 1989-1994 by Apple Computer, Inc.  All rights reserved.
;
;   This file is used in these builds: 
;
;	Change History (most recent first):
;
;	  <SM34>	 1/25/94	DCB		Added another deferred task record for use by pseudo DMA
;									machines.
;	  <SM33>	12/19/93	DCB		Added the pendingDTask flag.
;	  <SM32>	11/22/93	pdw		Rolling in from <MCxx>.
;	  <MC10>	11/11/93	pdw		Rearranged globals to accomodate dynamic supported-flags.
;	  <SM31>	11/19/93	chp		Add IRQ primitive vectors to HBADesc_53c9x record. Add constants
;									for intTypeSCSI and intTypeDMA. Modify IRQ macros to use the
;									newly defined primitive vectors.
;	  <SM30>	11/16/93	SAM		Removed eieio macro definition.
;	   <MC6>	10/29/93	pdw		Added dmaAlignmentSize and dmaAlignMask.
;	  <SMG3>	 9/29/93	chp		Add HAL fields to the HAL globals to represent a DB-DMA channel
;									command list buffer, with both logical and physical addresses.
;									Clean up changes in <SMG2>. Fix some potentially case-sensitive
;									stuff.
;	  <SMG2>	 9/22/93	chp		Add TNT support.
;	  <SM28>	10/29/93	DCB		Added a deferred task element to the globals so we can reduce
;									the interrupt level in the pseudo DMA data xfer routines.
;	   <MC5>	10/28/93	pdw		Just the usual - new vectors, new globals etc.
;	  <SM27>	10/14/93	pdw		<MC> roll-in.
;	   <MC4>	10/12/93	pdw		Added support for Synchronous data transfers, rewrote State
;									Machine, message handling etc.
;	   <MC3>	 10/6/93	pdw		Added forPDMProto around bit defines that are only used on
;									prototypes.
;	   <MC2>	 9/26/93	pdw		Changes to G_State usage from bit flags to enumeration.
;	  <SM26>	 9/16/93	DCB		Got rid of YeOldeBusErrVect since it isn't used anymore.
;	  <SM25>	 9/12/93	pdw		Getting rid of jvTransfer.
;	  <SM24>	  9/9/93	pdw		Lots of little changes.  Name changes, temporary cache_bug
;									stuff.
;	  <SM23>	 8/19/93	DCB		Improving the bus error handler so that disconnects at
;									non-polled bytes will work properly.
;	  <SM22>	 8/13/93	pdw		Got rid of some unused bits.  Added eieio macro.
;	  <SM21>	 7/20/93	pdw		Added intIRQbitNum and changed intDREQbitNum to a uchar.
;	  <SM20>	 7/17/93	pdw		A few little things.
;	  <SM19>	 6/29/93	pdw		Massive checkins: Change asynchronicity mechanism to CallMachine
;									stack switching mechanism.  Adding support for Cold Fusion.
;									Rearranging HW/SW Init code. Some code optimizations. Resolving
;									with my Ludwig sources.
;	  <SM18>	 5/26/93	PW		Separating...
;	  <SM18>	 5/26/93	PW		Separating the nonSerializedIO from the PDM debug stuff.
;	  <SM17>	 5/25/93	DCB		Rollin from Ludwig. (The next item below)
;	  <LW12>	 5/21/93	PW		Adding PRAM selectable Initiator ID stuff.
;	  <SM16>	  5/6/93	PW		Adding NOP to keep stop asm warnings.
;	  <SM15>	  5/5/93	PW		Converted names to meanies-friendly names.  Updated with latest
;									from Ludwig stuff.
;	  <SM14>	 3/29/93	PW		Temp: Added 2 flags to selectively enable real DMA on AMIC/Curio
;									(PDM). These are set by PRAM values in HALc96Init.a.
;	  <SM13>	 3/29/93	DCB		Adding pdmaTypeBIOS type to the dma type enum.
;	  <LW11>	  5/1/93	PW		Got rid of RECORD_ON definition (should only be in Debug.a now.
;	  <LW10>	 4/30/93	DCB		Getting rid of Info HalAction vector. It is getting its own
;									entry point into the HAL to prevent deadlocks.
;	   <LW9>	 4/30/93	PW		Added fields needed for 1,511 TIB optimization as well as some
;									extra fields in jump table for future use.
;	   <LW8>	 4/30/93	DCB		Changing default RECORD_ON to 0 for final Candiatate
;	   <LW6>	 4/14/93	DCB		Added jump table vector for SetParity
;	   <LW5>	 3/26/93	PW		Added savedCF2 byte and rearranged vectors for some reason.
;	  <SM12>	 3/20/93	PW		Introducing noSCSIInts.
;	   <LW4>	 2/17/93	PW		Moved otherHALg up into C-accessible area of globals.
;	  <SM11>	 1/31/93	PW		Update from the latest of Ludwig. Also changes required for PDM
;									(will update Ludwig with these as needed myself).
;	   <LW3>	 1/27/93	PW		Added dispatched InitDataStuff and DoData routines.
;	   <LW2>	  1/8/93	PW		Added inISR semaphore to check for a re-entrant ISR.
;	  <SM10>	 12/9/92	PW		Deleted unused field.
;	   <SM9>	 12/5/92	PW		Minor rearrangement to be more logical.
;	   <SM8>	11/20/92	DCB		Removed an include and put a conditional around deferred task
;									manager stuff to save a few bytes of global space.
;	   <SM7>	11/12/92	PN		Get rid of ≥ 020 conditionals
;	   <SM6>	10/30/92	DCB		Added some flags to control direct DMA operations. Also added
;									some macros to improve interrupt handlinbg
;	   <SM5>	 10/8/92	PW		Aligned some fields and rearranged some others.  Eliminated
;									unused third transfer vectors.
;	   <SM4>	 8/30/92	PW		Added kAssertATN to dispatch vectors.
;	   <SM3>	 8/20/92	DCB		Fixed SCSI Bus Reset
;	   <SM2>	 7/28/92	PW		Resolved differences in sources.
;	   <SM1>	 7/27/92	PW		Initial check-in.
;
;__________________________________________________________________________________________________

			BLANKS		ON
			STRING		ASIS


	IF CPU ≥ 020	 THEN					; 
			MACHINE		MC68020				; for '020 instructions	
	ENDIF

		IF (&TYPE('__INCLUDINGDEFERREDTASKEQU__') = 'UNDEFINED') THEN
			INCLUDE 'DeferredTaskEqu.a'
		ENDIF

		IF (&TYPE('__INCLUDINGGRANDCENTRALPRIV__') = 'UNDEFINED') THEN
			INCLUDE	'GrandCentralPriv.a'
		ENDIF


;
;	Version number of the SCSI Mgr
;
mgrVersion2	EQU		2		; brand new SCSI Mgr 2


;	SCSI Manager "G_State" flags
scPending		EQU		7		; bit in G_State -- an old request is spinning in SCSIGet
scBusy			EQU		0		; bit in G_State -- an old request is pending/in progress

MAXSTACK		EQU		256

;	Declaration of HALc96 globals
;
HALc96GlobalRecord	RECORD	0, INCREMENT
;
;====== Accessible from C and Asm ===== UPDATE HALc96.h FILE AS WELL!

; NOTE: hwDesc (and the elements of that structure following) must remain at the top
;		of the globals so that the HW init code can use the same routines as the mainline
;		HAL code (i.e. ClearSCSIIRQ).  See HALc96HWInit.a for more details.
;
hwDesc							; HBADesc_53c9x …

baseRegAddr			ds.l	1	; base addr of c9x registers (offset of $10 between regs
pdmaAddr			ds.l	1	; addr of Pseudo-dma access

pdmaNonSerlzdAddr	ds.l	1	; addr of Pseudo-dma in non-serialized space access
dreqAddr			ds.l	1	; addr of DAFB register with DREQ bit (SCSI DREQ base address)

intEnableSCSIAddr	ds.l	1	; addr of control register for SCSI interrupt
intFlagSCSIAddr		ds.l	1	; addr of status register for SCSI interrupt

dafbAddr			ds.l	1	; addr of DAFB that needs initialization
hbaUnusedL1			ds.l	1	; addr of 

dmaCntrlAddr		ds.l	1	; addr of true DMA control register(s)
dmaBaseAddr			ds.l	1	; addr of true DMA base register(s)

jvClearSCSIIRQ		ds.l	1	; hardware-specific primitive routine
jvEnableSCSIIRQ		ds.l	1	; hardware-specific primitive routine
jvDisableSCSIIRQ	ds.l	1	; hardware-specific primitive routine
jvTestSCSIIE		ds.l	1	; hardware-specific primitive routine

dreqNeedsSwapMMU	ds.b	1	; Boolean: set if dreq status bit is in 32-bit space
HBAisFast			ds.b	1	; Boolean: set if c9x part capable of Fast Synchronous (10MB/S)
HBAisDiff			ds.b	1	; Boolean: set if c9x part capable of differential
usesThreshold8		ds.b	1	; Boolean: set if DMA/interface can use c96's threshold8 mode
needsDAFBinit		ds.b	1	; Boolean: set if there's a DAFB that needs to be inited 
hbaUnusedB1			ds.b	1	; Boolean: set if 
hbaUnusedB2			ds.b	1	; Boolean: set if 
hbaUnusedB3			ds.b	1	; Boolean: set if 

HBAhasDMA			ds.b	1	; Boolean: set if true DMA available
HBAhasPseudoDMA		ds.b	1	; Boolean: set if Pseudo-DMA available
HBAhasHskPseudoDMA	ds.b	1	; Boolean: set if handshaked Pseudo-DMA available
dmaCacheCoherent	ds.b	1	; Boolean: set if DMA is fully cache coherent (no flushing needed)
hbaUnusedB4			ds.b	1	; Boolean: set if 
hbaUnusedB5			ds.b	1	; Boolean: set if 
hbaUnusedB6			ds.b	1	; Boolean: set if 
initiatorID			ds.b	1	; Char: ID of Macintosh (Initiator) on this bus

testIRQenableValue	ds.b	1	; Char: value to mask with to test SCSI IRQ enable 
enableIRQvalue		ds.b	1	; Char: value to write to enable SCSI IRQ
disableIRQvalue		ds.b	1	; Char: value to write to disable SCSI IRQ
clearIRQvalue		ds.b	1	; Char: value to write to clear SCSI IRQ
intIRQbitNum		ds.b	1	; bit to test for IRQ
intDREQbitNum		ds.b	1	; bit to test for DREQ
hbaUnusedC1			ds.b	1	;
hbaUnusedC2			ds.b	1	;

intTypeSCSI			ds.b	1	; type of interrupt control (shared VIA bit, etc.) 
intSensSCSI			ds.b	1	; type of sensitivity (LEVEL, EDGE, STICKYBIT)
intTypeDMA			ds.b	1	; type of interrupt control (shared VIA bit, etc.) 
intSensDMA			ds.b	1	; type of sensitivity (LEVEL, EDGE, STICKYBIT)
dmaType				ds.b	1	; type of programming model for DMA (PSC, AMIC,…)
dmaAlignmentSize	ds.b	1	; alignment requirements (i.e. 8, 16 etc)
hbaUnusedC4			ds.b	1	;
hbaUnusedC5			ds.b	1	;

intOSNumberSCSI		ds.w	1	; OS registration number for the SCSI interrupt
intOSNumberDMA		ds.w	1	; OS registration number for the DMA interrupt 
hbaUnusedS1			ds.w	1	;
hbaUnusedS2			ds.w	1	;
;
; …end of hwDesc

;…0
SIMstaticPtr		ds.l	1	; ptr to SIM's globals (for SSM callbacks)
XPT_ISRptr			ds.l	1	; ptr to XPT's ISR (so HAL can install it)
unusedRPtr			ds.l	1	; ptr to 
ReconnectISRptr		ds.l	1	; ptr to SIM's Reconnect ISR for us to call

busID				ds.w	1	; bus ID of this HAL's bus
rsrvdS2				ds.w	1	;  												<SM5> pdw
cclPhysicalAddr		ds.l	1	; addr of DB-DMA channel command list buffer (physical)
cclLogicalAddr		ds.l	1	; addr of DB-DMA channel command list buffer (logical)
physicalCopyBuffer	ds.l	1	; physical address of locked/noncachable copy buffer
logicalCopyBuffer	ds.l	1	; logical address of copy buffer to DMA into/out of
otherHALg			ds.l	1	; globals ptr to other HAL on dual bus machine

privStackTop			ds.l	1	; 
minDMAsize				ds.l	1	; 
supported_scFlags		ds.l	1
supported_scIOFlags		ds.w	1
supported_scDataTypes	ds.w	1

unusedCA1				ds.l	4
;
;======= Accessible from Asm only ======
;
G_JmpTbl	;—————— Jump Table ————————
;———— entry point jump table vectors
; must correspond to HALaction record shown below
jvInitiate			ds.l	1		; 0
jvBitBucket			ds.l	1
jvDataIn			ds.l	1
jvDataOut			ds.l	1
jvAcceptMsg			ds.l	1		; 4
jvRejectMsg			ds.l	1
jvMsgIn				ds.l	1
jvMsgOut			ds.l	1
jvStatus			ds.l	1		; 8				
jvComplete			ds.l	1			
jvSaveDataPointer	ds.l	1
jvModifyDataPointer	ds.l	1
jvRestorePointers	ds.l	1		; 12
jvGetReconnectInfo	ds.l	1
jvGetSelectInfo		ds.l	1
jvSelect			ds.l	1
jvSelectWAtn		ds.l	1		; $10
jvCommand			ds.l	1
jvSetParity			ds.l	1											;	<LW6> DCB
jvHandleSelected	ds.l	1		; $13

jvSetupIO			ds.l	1		; $14
jvResetBus			ds.l	1
jvAssertATN			ds.l	1
jvTeardownIO		ds.l	1		

jvUnused18			DS.L	1		;$18
jvUnused19			DS.L	1
jvUnused1a			DS.L	1
jvUnused1b			DS.L	1
jvUnused1c			DS.L	1
jvUnused1d			DS.L	1
jvUnused1e			DS.L	1
jvUnused1f			DS.L	1

;———— non-entry point jump table vectors
;—— Data Routines
initDataRoutines	ds.l	4	; jump table for data-transfer routines ; $20
dataRoutines		ds.l	4	; jump table for data-transfer routines ; $24

xferRoutines	equ	*	; jump table for data-transfer routines ; $28

readOffset		equ		(* - xferRoutines)/4

scsiReadFast	equ		(* - xferRoutines)/4
jvReadFast		DS.L	1		; fast reads
scsiReadSlow	equ		(* - xferRoutines)/4
jvReadSlow		DS.L	1		; slow reads

writeOffset		equ		(* - xferRoutines)/4

scsiWriteFast	equ		(* - xferRoutines)/4
jvWriteFast		DS.L	1		; fast writes
scsiWriteSlow	equ		(* - xferRoutines)/4
jvWriteSlow		DS.L	1		; slow writes

numTransferTypes	equ		(*-xferRoutines)/4/2		; 					<SM5> pdw

;———— assorted other non-entry vectors
jvUnused2c			DS.L	1		;$2c: 
jvCyclePhase		DS.L	1		; Bitbuckets or fills bytes to get target to Status phase
jvBusErr			DS.L	1		; 	 
jvUnusedX			DS.L	1		; 	 

jvStartDMA			DS.L	1		;$30: starts either DMA read or write
jvStopReadDMA		DS.L	1		; stops a DMA read
jvStopWriteDMA		DS.L	1		; stops a DMA write
jvWt4DMAComplete	DS.L	1		; waits until a DMA is complete (only used by initate)

jvAutoMsgIn			DS.L	1
jvWt4SelectComplete	DS.L	1
jvHandleBusInt		DS.L	1
jvUnused37			DS.L	1

jvUnused38			DS.L	1
jvUnused39			DS.L	1
jvUnused3a			DS.L	1
jvUnused3b			DS.L	1

jvUnused3c			DS.L	1
jvUnused3d			DS.L	1
jvUnused3e			DS.L	1
jvUnused3f			DS.L	1

;———— end of jump vectors
numSelectors		equ		(*-G_JmpTbl)/4		;$38

transferType	DS.W	1		; Type of data transfer to perform (used in Transfer_96, BusError)
rCF3NormalVal	DS.B	1		; value of rCF3 during normal operation
rCF3DMAVal		DS.B	1		; value of rCF3 during DMA operation

unused1			DS.B	1		; LUDWIG : rCF3DataVal
optimTIB		DS.B	1		; set if we're optimizing the TIB
currentPhase	DS.B	1		; current SCSI bus phase
dataDeferStuff	DS.B	1		; semaphore for the null deferred task

G_State96		DS.B	1		; Bits to follow c96 internal state
gotInt			DS.B	1		; flag = we've got an int
intFlags		DS.B	1		; some flags for things
dmaFlags		DS.B	1		; some more flags for things (DMA and LockMemory Control) <SM6>

chanlControl	DS.L	1		; used by PSC code only - saved between Start and StopPSC
setRegs			DS.L	1		; used by PSC code only

intRegsRead		equ		*
int_rSQS		DS.B	1		; Value of rSQS at last valid interrupt read (required)
int_rSTA		DS.B	1		; Value of rSTA at last valid interrupt read (required)
int_rFIFOflags	DS.B	1		; Value of rFOS at last valid interrupt read (useless)
int_rINT		DS.B	1		; Value of rINT at last valid interrupt read (required)

illCmdRegsRead	DS.B	1		; 
				DS.B	1		; 
				DS.B	1		; 
				DS.B	1		; 

r_selectingID	DS.B	1		; ID of target (re)selecting c96
r_selectingMsg1	DS.B	1		; msg byte received (Identify) after reselected
r_selMsgLen		DS.B	1		; 									
r_selPhase		DS.B	1		; 									

newRegsRead		DS.L	1		; Value of regs at previous interrupt read (useless)
oldRegsRead		DS.L	1		; Value of regs at previous interrupt read (useless)
olderRegsRead	DS.L	1		; Value of regs at previous interrupt read (useless)
oldestRegsRead	DS.L	1		; Value of regs at previous interrupt read (useless)

dbug0			DS.L	1		; 

firstIncCount	DS.L	1		; transfer count from first scInc (before optimization)
secondIncCount	DS.L	1		; same but from second scInc of optimized TIB

logBuffer		DS.L	1		; a place to remember where the real (logical) buffer is while
								; we use the physical one to DMA into
getPhysLen		DS.L	1		; a spot for the count of a logical-physical table

publicSP		DS.L	1		; stack pointer upon arrival into RealHALaction
suspendedSP		DS.L	1		; suspended SCSI thread stack pointer


rcvdIDBits		DS.B	1		; mask of bits on bus during selection
selectedRegSQS	DS.B	1		; rSQS after selection
rcvdMessageLen	DS.B	1		; # of message out bytes received after being selected as target
rcvdMessage		DS.B	13		; message out bytes received after being selected as target
rcvdCommandLen	DS.B	1		; # of command bytes received after being selected as target
rcvdCommand		DS.B	15		; command bytes received after being selected as target

publicStkLowPt	DS.L	1
privStackState	DS.B	1
dataDTFlags		DS.B	1		; Used to keep track of whether we are in our data xfer deferred task
savedSR			DS.W	1		; saved SR for use in BERR handler

intrpStackFrame	DS.L	1

dmaAlignMask	DS.L	1		; mask that corresponds with alignment

dataDT			DS		DeferredTask	; The deferred task record which allows us to 
										; defer pseudoDMA data transfers until after
										; we are out of our interrupt handler.
dataDT_Null		DS		DeferredTask	; A deferred task that just points to null.  Since
										; the real deferred task manager doesn't run when
										; VM is disabled we needed to write our own.  jDisptch
										; only gets called when there is something in the real
										; deferred task queue so we just stuff this in there
										; to trigger interrupthandlers.a to call jDisptch which
										; calls our own deferred task manager
extras			DS.L	8		; unused

;
;---- End Of Globals ----
GlobalSize		EQU		*-HALc96GlobalRecord	; size of HALc96 globals
				ENDR
;————————————————————————————————————————————————————————————————————————————————————

; If we were smart, we'd make this page size independent
PageSize601		EQU		$1000		; 4K (for now)
PageMask601		EQU		$0FFF		; inverse

;—————————————————————————————————————————————————————————
;	Bit definitions for flag bytes in globals 
;		bytes! i.e. no bit higher than 7
;————————————————————————————————————————————————————————
;———— G_State96 Value defs —— keeps track of where old-API is in a c96 Select(w/Atn) cmd
;
;	We need to keep track of what state the c96 is in during it's handling of a DMA Select
;	or Select W/Atn command because we hand control back to the SIM (and then to the client
;	during the processing of an old API transaction right in the middle of the c96's 
;	processing of this command.
;
NeedMsgOut		EQU		3		; expect a msg_out phase next as part of $C1 cmd to c96
NeedCmdSent		EQU		2		; expect a command phase that we need to complete the select
FCIntPend		EQU		1		; Function Complete Intrp pending bit (from $C1 cmd)


;——— Bit Definitions for intFlags byte —————

waiting4int		EQU		3		; Wt4SCSIInt has been called but ISR hasn't happened yet
intRegsValid	EQU		6		; set when we get an int and cleared before issuing a command
r_selRegsValid	EQU		7		; set when we get a sel/resel int and clrd at issue of Enable R_Sel cmd

;——— Bit Definitions for dataDTFlags byte —————

inDataDT		EQU		0		; Set if we are doing DMA straight to the user's buffer
fromRealInt		EQU		1		; Set if we have are executing code from our ISR as a result of
								; a real (as opposed to polled for) interrupt.  This means that it
								; is safe to defer our data transfer
pendingDTask	EQU		2		; Set if we are expecting the deferred task to execute.


;——— Bit Definitions for dmaFlags byte —————

noBlockMove		EQU		0		; Set if we are doing DMA straight to the user's buffer <SM6>

; forPDMProto
doRealDMAWrite	EQU		4
doRealDMARead	EQU		5
; end
;
;————	Register saving convention ————
;
scsiRegs		REG		a0-a5/d1-d7	; standard register saving convention (result in d0)
intrRegs		REG		a0-a5/d0-d7	; interrupt handler register saving convention

;
;	Old SCSI Mgr equates -- temporary, since SCSI.a has the public portion of the PB
;

;maxOpcode		EQU		8		; highest numbered TIB opcode (from rom78fix.a)


;---------------------------------------------------
;  For intTypeSCSI and intTypeDMA HW descriptors
;---------------------------------------------------
SHARED_VIA			EQU		0
INDEPENDENT_VIA		EQU		1
SECOND_SHARED_VIA	EQU		2
GRAND_CENTRAL		EQU		3


;---------------------------------------------------
;  For intSensSCSI and intSensDMA HW descriptors
;---------------------------------------------------
EDGE			EQU		0
LEVEL			EQU		1		; no clear necessary
STICKYBIT		EQU		2


;---------------------------------------------------
;  For dmaType HW descriptor
;---------------------------------------------------
dmaTypeNone		EQU		0
dmaTypePSC		EQU		1
dmaTypeAMIC		EQU		2
pdmaTypeBIOS	EQU		3
dmaTypeGC		EQU		4


;---------------------------------------------------
;  Debug Defs
;---------------------------------------------------

overFlow		EQU		$0				;


;——————————————————————————————————————————————————————————
	MACRO
	ClearSCSIIRQ		;	clear latched VIA SCSI interrupt bit	<SM6> pdw
;—————————————————————————————
			IF 0 AND RECORD_ON THEN
				pea		'It=0'
				move.l	sp, -(sp)
				bsr		RecordEvent
				addq.l	#8, sp
			ENDIF
			if noSCSIInts then		
				nop
				nop
				nop
				nop
			else
				jsr		([HALc96GlobalRecord.jvClearSCSIIRQ,A5])
			endif
			eieio
	ENDM

;——————————————————————————————————————————————————————————
	MACRO
	EnableSCSIIRQ		;	Enable SCSI interrupt <SM6> pdw
;—————————————————————————————
			IF 0 AND RECORD_ON THEN
				pea		'It++'
				move.l	sp, -(sp)
				bsr		RecordEvent
				addq.l	#8, sp
			ENDIF
			if noSCSIInts then		
					nop
					nop
					nop
					nop
			else
				jsr		([HALc96GlobalRecord.jvEnableSCSIIRQ,A5])
			endif
			eieio
	ENDM


;——————————————————————————————————————————————————————————
	MACRO
	DisableSCSIIRQ		;	Disable SCSI interrupt <SM6> pdw
;—————————————————————————————
			IF 0 AND RECORD_ON THEN
				pea		'It--'
				move.l	sp, -(sp)
				bsr		RecordEvent
				addq.l	#8, sp
			ENDIF
			if noSCSIInts then		
				nop
				nop
				nop
				nop
			else
				jsr		([HALc96GlobalRecord.jvDisableSCSIIRQ,A5])
			endif
			eieio
	ENDM


;——————————————————————————————————————————————————————————
	MACRO
	jsrv	&jv, &areg		; jsr to A5-vectored routine
;—————————————————————————————
			IF INDEXED_IS_FASTER THEN
				jsr		([&jv, A5])
			ELSE
				move.l	&jv(A5), &areg
				jsr		(&areg)
			ENDIF
	ENDM