mirror of
https://github.com/elliotnunn/supermario.git
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375 lines
10 KiB
Plaintext
375 lines
10 KiB
Plaintext
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;____________________________________________________________________________________
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;
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; File: HALc96_PSC.a
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;
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; Contains: Stuff for 53c96/PSC machines (Cyclone)
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;
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; Written by: Paul Wolf
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;
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; Copyright: © 1990-1993 by Apple Computer, Inc., all rights reserved.
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;
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;
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; Change History (most recent first):
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;
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; <SM28> 11/22/93 pdw Rolling in from <MCxx>.
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; <SM27> 10/29/93 DCB Getting rid of warnings.
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; <SM26> 10/27/93 DCB Saving ChanlControl in the Halg so Cyclone doesn't choke on
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; itself.
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; <SM25> 10/14/93 pdw <MC> roll-in.
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; <MC2> 10/12/93 pdw Added support for Synchronous data transfers, rewrote State
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; Machine, message handling etc.
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; <SM24> 9/9/93 pdw Lots of little changes. Name changes, temporary cache_bug
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; stuff.
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; <SM23> 7/17/93 pdw Added this minDMAsize thing.
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; <SM22> 6/29/93 pdw Massive checkins: Change asynchronicity mechanism to CallMachine
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; stack switching mechanism. Adding support for Cold Fusion.
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; Rearranging HW/SW Init code. Some code optimizations.
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; <SM21> 5/5/93 PW Converted names to meanies-friendly names. Updated with latest
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; from Ludwig stuff.
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; <LW11> 5/1/93 PW Removed PSC register write retries (old PSC bug workaround).
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; <LW9> 3/26/93 PW Removed generic DMA routines from this file and put them into
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; HALc96DMA.a.
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; <SM19> 3/20/93 PW New (effectively). Split HALc96PSC.a into 2 files - this one
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; and HALc96DMA.a to better handle alternate DMA hardware (i.e.
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; AMIC).
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;
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;____________________________________________________________________________________
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MACHINE MC68020 ; '020-level
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BLANKS ON ; assembler accepts spaces & tabs in operand field
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PRINT OFF ; do not send subsequent lines to the listing file
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; don't print includes
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LOAD 'StandardEqu.d'
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; INCLUDE 'HardwarePrivateEqu.a'
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INCLUDE 'HardwareEqu.a' ;
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INCLUDE 'UniversalEqu.a' ; for TestFor
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INCLUDE 'Debug.a' ; for NAME macro
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INCLUDE 'SCSI.a'
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INCLUDE 'SCSIEqu53c96.a'
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INCLUDE 'ACAM.a'
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INCLUDE 'SIMCoreEqu.a'
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INCLUDE 'HALc96equ.a'
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INCLUDE 'PSCequ.a'
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PRINT ON ; do send subsequent lines to the listing files
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CASE OBJECT
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IMPORT RecordEvent
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IMPORT OneByteRead, OneByteWrite
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;==========================================================================
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IF 0 THEN ; from PSCEqu.a $50F31000 +
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SCSI_CNTL EQU $C00 ; Channel 0 control register
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SCSI EQU $1000 ; Channel 0 base
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SCSI_ADDR0 EQU $1000 ; Register Set 0 address register
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SCSI_CNT0 EQU $1004 ; Register Set 0 count register
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SCSI_CMDSTAT0 EQU $1008 ; Register Set 0 command/status register
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SCSI_ADDR1 EQU $1010 ; Register Set 1 address register
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SCSI_CNT1 EQU $1014 ; Register Set 1 count register
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SCSI_CMDSTAT1 EQU $1018 ; Register Set 1 command/status register
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;
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; PSC DMA Channel Register offsets
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;
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PSC_DMA_CHNL RECORD 0 ; PSC DMA Channel record for use
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Addr DS.L 1 ; with Channel base equ's below,
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Cnt DS.L 1 ; SCSI_CHNL, MACE_RECV_CHNL, etc.
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CmdStat DS.W 1
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ENDR
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ENDIF
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;==========================================================================
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;——— DMA Channel Control Register bit offsets
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PSCChannelBits RECORD 0
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unused0 ds.b 8
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CIRQ ds.b 1 ; 8
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FLUSH ds.b 1 ; 9
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PAUSE ds.b 1 ; 10
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SWRESET ds.b 1 ; 11
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CIE ds.b 1 ; 12
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BERR ds.b 1 ; 13
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FROZEN ds.b 1 ; 14
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ENDR
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;———— DMA Channel Set Command/Status Register bit offsets
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PSCSetBits RECORD 0
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unused0 ds.b 8
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IF ds.b 1 ; 8
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DIR ds.b 1 ; 9
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TERMCNT ds.b 1 ; 10
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ENABLED ds.b 1 ; 11
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IE ds.b 1 ; 12
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unused13 ds.b 2
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SENSE ds.b 1 ; 15
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ENDR
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kmWriteOnes equ 1<<PSCSetBits.SENSE
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kmSET equ $1 ; only 1 bit valid for set indication
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kPSC_SetOffset equ $10 ; distance between set control registers
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knbPSC_SetOffset equ $4 ; number of bits to shift for set offset
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;————————————————————————————————————————————
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StackFrame RECORD {link},DECR
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;---- parameters ----
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direction ds.w 1 ; direction of transfer (kIn or kOut)
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byteCount ds.l 1 ; number of bytes to transfer
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bufferAddr ds.l 1 ; source/dest buffer for DMA transfer
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;---- mechanics
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returnAddr ds.l 1 ; return address
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link ds.l 1 ; location of old A6 (after LINK A6)
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;----
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linkSize EQU *
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ENDR
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;————————————————————————————————————————————
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trashedRegs EQU A2
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; ———————— Internal:———————————————————————————————————————————————
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A2_SetRegs EQU A2 ; ptr to the now active register set
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A1_ChanlControl EQU A1
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;——————————————————————————————————————————————————————————————————————————
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StartPSC PROC EXPORT
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;
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; Register Usage:
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;
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; ———————— On Entry:———————————————————————————————————————————————
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;
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;
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; ———————— On Exit:———————————————————————————————————————————————
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D0_result EQU D0 ;.w :
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;
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;
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;
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WITH StackFrame, HALc96GlobalRecord, PSC_DMA_CHNL
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link a6, #linkSize
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move.l A2, -(sp)
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;
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; Get ptrs to PSC regs in A2 and A1
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;
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movea.l UnivInfoPtr, A1 ; get pointer to ProductInfo
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adda.l ProductInfo.DecoderInfoPtr(A1), A1 ; point to the base address table
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move.l DecoderInfo.PSCAddr(A1), A2
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lea SCSI_CNTL(A2), A1_ChanlControl ; set up A1 (whole channel control reg)
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lea SCSI(A2), A2_SetRegs ; set up A2 (top of active set's registers)
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move.l A1_ChanlControl, HALc96GlobalRecord.chanlControl(A5)
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; PAUSE the channel
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;
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IMPORT PausePSC
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bsr PausePSC
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;
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; Displace A2 to point to the Active set's registers
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;
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move.w (A1_ChanlControl), D0
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and.w #kmSET, D0 ; which is the current set?
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lsl.w #knbPSC_SetOffset, D0
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add.w D0, A2_SetRegs ; active set's register base
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move.w CmdStat(A2_SetRegs), D0
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; btst #ENABLED, D0 ; is the active set ENABLED?
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; beq.s @1
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; _debugger ; trap if it is (pre-alpha) it should be stable
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@1
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;
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; Set up set registers; count, addr and cmdStat (direction, intFlag cleared, ENABLED)
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;
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move.l byteCount(a6), Cnt(A2_SetRegs) ; <removed retry><LW11> pdw Fß
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move.l bufferAddr(a6), Addr(A2_SetRegs) ; <removed retry><LW11> pdw Fß
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move.w #1<<DIR, d0 ; direction : if out, clear (with SENSE=0)
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tst.w direction(a6)
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beq.s @dirOut
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or.w #1<<SENSE, d0 ; if in, set (with SENSE=1)
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@dirOut
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move.w d0, CmdStat(A2_SetRegs) ; write direction to reg
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move.w #1<<PSCSetBits.IF, CmdStat(A2_SetRegs) ; clear InterruptFlag
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move.w #(1<<SENSE) + (1<<PSCSetBits.ENABLED), CmdStat(A2_SetRegs) ; ENABLE this set
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;
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; UnPAUSE and return to caller
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;
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move.w #(1<<PSCChannelBits.PAUSE), (A1_ChanlControl)
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move.l A1_ChanlControl, chanlControl(A5)
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move.l A2_SetRegs, setRegs(A5)
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move.l (sp)+, A2
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unlk a6
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rts
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NAME 'StartPSC'
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ENDWITH
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ENDPROC
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;--------------------------------------------------------------------------
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PausePSC PROC EXPORT
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;
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move.l HALc96GlobalRecord.chanlControl(A5), A1_ChanlControl
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move.w #(1<<SENSE)+(1<<PSCChannelBits.PAUSE), (A1_ChanlControl) ; PAUSE the whole channel
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@frozenWait
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move.w (A1_ChanlControl), D0
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btst #PSCChannelBits.FROZEN, D0
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beq.s @frozenWait
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rts
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NAME 'PausePSC'
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ENDPROC
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;--------------------------------------------------------------------------
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Wt4PSCComplete PROC EXPORT
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WITH HALc96GlobalRecord, PSC_DMA_CHNL
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move.l A2, -(sp)
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move.l chanlControl(A5), A1_ChanlControl
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move.l setRegs(A5), A2_SetRegs
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@loop btst #CIRQ, CmdStat(A2_SetRegs)
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beq.s @loop
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@loop2 btst #ENABLED, CmdStat(A2_SetRegs) ; because somehow we ended up in the
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bne.s @loop2 ; next DMA with a set ENABLED!
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move.l Cnt(A2_SetRegs), D0
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move.l (sp)+, A2
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rts
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NAME 'Wt4PSCComplete'
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ENDWITH
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ENDPROC
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;--------------------------------------------------------------------------
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StopPSCRead PROC EXPORT
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;
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; Pauses and returns D0 = number of bytes left in count register
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;
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WITH HALc96GlobalRecord, PSC_DMA_CHNL
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move.l A2, -(sp)
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move.l chanlControl(A5), A1_ChanlControl
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move.l setRegs(A5), A2_SetRegs
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;
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; Check to see if transfer is complete.
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;
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btst #PSCSetBits.TERMCNT, CmdStat(A2_SetRegs)
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bne.s @finishedDMA
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;
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; FLUSH the PSC FIFO then wait for its completion.
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;
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move.w #(1<<SENSE)+(1<<PSCChannelBits.FLUSH), (A1_ChanlControl) ; FLUSH the channel
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@wt4Flushed
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btst #PSCChannelBits.FLUSH, (A1_ChanlControl) ; flushing?
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bne.s @wt4Flushed ; if still Flushing, repeat
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;
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; Pause the channel then get the Cnt register
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;
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IMPORT PausePSC
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bsr PausePSC
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@getCount
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move.l Cnt(A2_SetRegs), D0 ; get count
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beq.s @exit
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@putZeroCount
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move.l #0, Cnt(A2_SetRegs)
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tst.l Cnt(A2_SetRegs)
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bne.s @putZeroCount
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bra.s @exit
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@finishedDMA
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moveq.l #0, D0
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@exit
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move.l (sp)+, A2
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rts
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NAME 'StopPSCRead'
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ENDWITH
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ENDPROC
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;--------------------------------------------------------------------------
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StopPSCWrite PROC EXPORT
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;
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; Pauses and returns D0 = number of bytes left in count register
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;
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WITH HALc96GlobalRecord, PSC_DMA_CHNL
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IMPORT PausePSC
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move.l A2, -(sp)
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move.l chanlControl(A5), A1_ChanlControl
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move.l setRegs(A5), A2_SetRegs
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;
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; Check to see if transfer is complete. If it is then exit with D0=0
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;
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btst #PSCSetBits.TERMCNT, CmdStat(A2_SetRegs)
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bne.s @finishedDMA
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;
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; Pause the channel then get the Cnt register then reset the channel (flush unwritten data)
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;
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@getCount
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bsr PausePSC
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move.l Cnt(A2_SetRegs), D0 ; get count
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move.w #(1<<SENSE)+(1<<PSCChannelBits.SWRESET), (A1_ChanlControl) ; FLUSH the channel
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bra.s @exit
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@finishedDMA
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moveq.l #0, D0
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@exit
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move.l (sp)+, A2
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rts
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NAME 'StopPSCWrite'
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ENDWITH
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ENDPROC
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END
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