; ; File: RBVDepVideoEqu.a -> DepVideoEqu.a ; ; Contains: These are the configuration ROM equates that are specific only to ; built-in video. This includes mode information, sResource IDs, ; etc., etc…. ; ; Written by: David Fung/Mike Puckett, September 25, 1990. ; ; Copyright: © 1988-1994 by Apple Computer, Inc., all rights reserved. ; ; Change History (most recent first): ; ; 2/6/94 IH Check in DAFB version info. ; 1/24/94 rab Sync this file with DepVideoEqu.r. This fixes the video problems ; on DAFB based CPUs… ; 1/3/94 PN Delete an extra entry in DAFBVidParams record. ; 12/14/93 PN Change sRsrc_SCSI_Transport to $FA ; 12/13/93 PN Roll in KAOs and Horror changes to support Malcom and AJ ; machines ; 12-06-93 jmp Bumped DAFB’s driver version so that the WaterWings extension ; doesn’t reload it. Need to roll the Display Manager support ; directly into the driver in ROM.\ ; 11/10/93 fau Update from SuperMunggio . ; 10/27/93 fau Added the ID for the ATI sRsrc Directory. ; 11/9/93 KW added some srsrc's for stp machines ; 11/8/93 JRH boxDBLite16 is now boxPowerBookDuo250. boxDBLite20 is now ; boxPenLite. ; 10/6/93 RC Took out PDM eVT1 support ; 08-16-93 jmp Sorted the BFBased sRsrc-list into purely ascending order (for ; easier eye-ball comparisons with DeclData). ; 8/13/93 KW adding two more smurf wombats ; 8/12/93 BG Removed things related to WLCDc1 since it will never exist. ; Updated other boxflag references with "official" names. ; 8/11/93 KW adding some new srsrc equates for some new smurf machines ; 08-06-93 jmp Updated the timing constants used by the Display Manager for ; non-intelligent displays. ; 08-03-93 jmp Began cleaning up the support for dynamically allocating RAM in ; PDM for video, as well as added initial support for the three ; new Apple multiscan displays. ; 7/14/93 RC stripped out PDM debug flags ; <47> 7/2/93 IH Fix 1096920: Changed civic driver version so I can know which ; driver to patch. ; 6/14/93 kc Roll in Ludwig. ; 5/14/93 fau Adding PUMA Suport. ; 4/29/93 fau #1082085: Added a bit to the Cyclone slotPRAM flags to indicate ; whether the "Boot on composite" should be NTSC or PAL. ; 6/3/93 SAM Changed sRsrc_BdPDM to boxPDMEvt1. ; 6/1/93 IH Add timing mode constants ; 5/6/93 RC Cleaned up the extended sense line support for EVT2 and better ; PDMs, the code still supports EVT1 PDMs ; 4/29/93 fau Synchronized with Ludwig: ; 4/14/93 fau Changes due to the new way of doing video-in with Civic: New ; private control codes, new offsets, new structures, and ; renumbered/deleted some of the spID's. ; 4/9/93 fau Moved the spOpenComponent bit to 3 so that I can give the sound ; guys bits 4-7 of SP_Flags. ; 04-07-93 jmp Added the multiscan family mode to the Sonora/PDM sResource IDs ; to support the Display Manager. ; 4/6/93 fau More Ludwig Synchronization. ; 4/5/93 fau Added the private codes for Civic's driver, as well as some ; specific record definitions for those calls. Added support for ; Puma's W parameter/size/clock in the Video Parameters for Civic. ; 4/2/93 chp Synchronize fully with Ludwig version. ; 3/22/93 fau Added a sRsrc_BdTempest for the board id for Tempest. ; 2/24/93 fau Added a SCSI_Transport sRsrc equate. ; 2/16/93 fau Renumbered all the spID's for Civic, so that I could add the ; video-out modes for all Apple monitors. ; 1/4/93 fau Added spOpenComponent bit on the SP_Flags byte of PRAM. ; 04-01-93 jmp Added support for the no-VRAM case for Sonora/PDM. ; 3/31/93 chp Add sRsrc_BdTempest from Ludwig. ; 3/9/93 jmp Updated the version number for the Sonora/PDM video driver. ; 3/5/93 CCH Added sRsrc ID for Mace on Sonora/PDM. ; 2/20/93 SAM Second attempt at that last rev. Added SonoraSenseEnable masks ; that are different from the "read" masks. ForPDM only. ; 2/9/93 SAM Added Evt1 changes to invert the bit order of the sense masks. ; 01/12/93 jmp Added MiniGamma record from various PrimaryInits. ; 01/11/93 jmp Updated various BoxFlag names and added the initial CSC equates. ; 12/23/92 RC Added Support for Smurf on Wombat ; 12/09/92 jmp Removed the PDM bring-up conditional. ; 12/4/92 fau Changed sRsrc_BdCyclone to use the new BoxCyclone33, instead of ; BoxCyclone. ; 11/11/92 fau Added support for Clifton (the low-cost clock chip) in Cyclone ; CPU's. ; 11/6/92 jmp Added some conditional support for PDM bring-up. ; 10/29/92 fau Added a bit in the PRAM for Civic to tell us to drive the ; composite video out. ; 10/29/92 jmp (jmp,H48) Fixed a typo in the DAFBSpeed macro where I was using ; A0 instead of A2! ; (jmp,H47) Added support for 33 MHz WLCD. ; 10/27/92 fau Added a new long to the Civic Video Parameters: CliftonW (for ; the new clock chip on Tempest). ; 10/25/92 HY Added support for LCII boxflag. ; 10/17/92 jmp Added support for PDM. ; 09/29/92 jmp (jmp,H46) Changed a naming inconsistency in the DAFBVidParams ; data structure. ; 09/03/92 jmp Added “68020” support for RISC emulators and updated from ; Horror: (jmp,H45) Added initial support for the AT&T CLUT/DAC ; (Antelope) to be used in Wombat/WLCD systems. ; (jmp,H44) Changed the Sonora ReadSenseLine macro so that it ; would work on the latest rev (EVT-2.3) parts. ; (SWC,H43)Updated CurDBLiteDrvrVersion to 1 to differentiate ; between the Dartanian and DBLite versions of the driver (a bug ; got fixed in the DBLite version). ; (jmp,H42) Eliminated some redundant equates. ; 8/31/92 fau Added a couple of equates necessary for the changes made to ; Civic-based CPU's in Decldata.a . ; 8/9/92 CCH Added support for video on Quadras with RISC cards. ; 07/14/92 jmp (jmp,H41) Added in support to make the DAFB part of built-in ; video work correctly among Spike, Eclipse, Zydeco, and all ; Wombat/WLCD CPUs. ; (jmp,H40) Fixed the DAFBBWrite macro to work better when being ; run via the Cub card. ; (jmp,H39) Tightened and eliminated a number of the DAFB macros. ; Also, added a pRAM bit for remembering whether AltSense was ; enabled the last reboot. (At the momment, this bit is only used ; for DAFB because it puts out the sync-on-green signal, and we ; might want to keep the same sync-on-green state even though the ; AltSense code changed. I don’t think Vail or Cyclone need to ; know that AltSense was enabled last reboot, but they could use ; this bit if they ever did.) ; (jmp,H38) Made the DAFBReadSenseLines macro work better with ; Wombat DAFBs (due to the fact that the WombatDAFB is not tied to ; the ’040 reset instruction like other DAFB-based CPUs are). ; (jmp,H37) Added yet another base-address constant for Wombat. ; (jmp,H36) Needed some new base-address constants for Wombat. ; (jmp,H35) Added first-pass support for the Wombat version of ; DAFB. ; (jmp,H34) Cleaned up the DAFB byte and word write macros, and a ; fixed a minor bug in the DAFBIdle macro (the way it was ; originally written, there could have been cases where the AC824A ; would NOT have put back into “compatible” mode). ; 7/13/92 CCH Modified DAFBBWrite macro to perform byte writes. ; 7/7/92 CSS Change references for boxApollo to boxClassisII. ; 7/7/92 fau Moved the equ for sRsrc_BdWombat20 to the correct location as ; the boxWombat20 flag moved from 29 to 52. ; 6/26/92 fau Remove DSP3210 sRsrc in Cyclone, since the DSP is not slot ; manager-based anymore. Added ID's for 12" and 13" monitor ; support for composite out. ; 6/19/92 KW (fau,P23) Moved DSP srsrc from $F0 to $F8. We had reserved $40 ; id's for displays with video-in disabled, but only $30 for ; displays with video-in disabled. Changed it to $35 for each, so ; video-in id's run all the way to $F7. Added id's for Goldfish ; out of composite. ; 6/18/92 KW Rolled back in SM8 ; 6/17/92 KW Roll back to SM7 ; 6/17/92 KW (jmp,H34) Cleaned up the DAFB byte and word write macros, and a ; fixed a minor bug in the DAFBIdle macro (the way it was ; originally written, there could have been cases where the AC824A ; would NOT have put back into “compatible” mode). ; (jmp,H33) Eliminated yet even more of the old DAFBVidParams ; fields, so I adjusted the data structures accordingly. ; (jmp,H31) Updated the SonoraVidParams record to accomdate ; Omega-2 and added some new burn-in constants. ; (fau,P21) Added video-in equates for Vesuvio, Kong, Rubik, 19" ; Display and all VGA families for Civic-based CPU's. ; 6/4/92 KW (jmp,H30) Added some new data structures for describing the ; newly-compacted DAFB vidParams. ; (BG,H29) Changed various Wombat-style BoxFlag references to ; their new, more descriptive names. ; (jmp,H28) Eliminated support for the no-vRAM case in V8-base ; systems. ; (jmp,H27) Changed the “sRsrcZydecoDir” name to the more generic ; “sRsrcBFBasedDir” (BF=BoxFlag) name. ; (jmp,H26) Added some base-address constants for V8 to eliminate ; the VideoInfo arrays in Universal.a. ; (jmp,H25) Added some new CPU board ID constants (based on ; BoxFlag), added some new DAFB constants for Wombat, and added ; some conditionals for nuking the Apollo stuff and killing the ; Slot Manager checksum of Slot $0’s DeclData as it’s somewhat ; redundant. ; KW Removed FirstVidMode,SecondVid etc since already in VideoEqu ; 5/21/92 RB Making changes for Cyclone ; 5/17/92 kc Roll in Horror changes. Comments follow: ; 04/24/92 jmp Added constants to support the “switch-on-the-fly” Rubik-512 to ; Rubik-560 and vice-versa call for Sonora. ; 04/20/92 jmp Added constants to support the 640x400 mode of the HiRes ; displays. ; 3/17/92 SWC Renamed boxDBLite->boxDBLite25 and boxDBLiteLC->boxDBLite33, and ; added equates for boxDBLite16 and boxDBLite20. ; 02/20/92 jmp (jmp,Z27) Changed the DAFB clock-select equates from ; Bset/clr-oriented to Bfins/Bfext-oriented. ; 02/19/92 jmp Changed the Condor references to Wombat. ; 2/18/92 JC Changed boxCarnation to boxCarnation33 and boxVail to boxVail25. ; 2/17/92 SAM Changed boxCondor to boxWombat. ; 01/27/92 jmp Moved some equates from DepVideoEqu.a to ROMEqu.a. ; 01/22/92 jmp (jmp,Z26) Renamed all the “NoConnect” equates to “AltSense.” ; 1/14/92 SWC Updated boxFlag labels to use shipping product names. ; 01/11/92 jmp Added equates for the newly-defined extended sense codes. ; 12/19/91 jmp Added the initial support for Rubik-560 mode for Sonora. ; 12/17/91 jmp Added a new baseAddr offset for Kong & Vesuvio on DAFB. ; 12/16/91 HJR Added Dartanian sRsrc_BdDartanian equate. ; 12/12/91 jmp Added more Sonora-related equates and some new DBLiteLC equates. ; 11/27/91 jmp Added massive amounts of Sonora equates. ; 11/26/91 jmp Added some GSC and DBLite equates. ; 11/12/91 jmp Defined two new DAFBFlag bits to indicate the size of vRam. ;
11/05/91 jmp Added more 19” display equates for DAFB. ;
11/01/91 jmp Added equates for (eventually) supporting 19” displays with ; DAFB. ;

10/29/91 jmp Changed the Spike33 names to Condor. ;

10/24/91 jmp Added in constants to support the gray-scale DB-Lite (up to ; 4bpp) LCD display. ;

10/24/91 jmp Updating to Zydeco-TERROR version. ; 4/7/92 JSM Roll-in changes from Reality: ; <2> 3/24/92 JSM Nuke more code names: boxAuroraCX25 is boxMacIIci, boxF19 is ; boxMacIIfx. ; 3/31/92 JSM Rolled this file into Reality. ; 2/11/92 RB Update to reflect the Zydeco changes (beta). Updated boxFlags ; 12/29/91 RB first checked in ; ---------------------------------------------------------------------- ; Zydeco History: ; <26> 01/20/92 jmp Renamed all the “NoConnect” equates to “AltSense.” ; <25> 01/09/92 jmp Added equates for the newly-defined extended sense codes. ; <24> 12/17/91 jmp Added a new baseAddr offset for Kong & Vesuvio on DAFB. ; <23> 11/08/91 jmp Defined two new DAFBFlag bits to indicate the size of vRam. ; <22> 11/05/91 jmp Added equates for supporting 19” Displays with DAFB. ; <21> 10/16/91 jmp Modified the DAFBIdle & DAFBReset macros to set & reset a flags ; register saying whether DAFB video is active or not. This was ; added to support turning video back on immediately in the event ; that the video driver was closed and needed to be opened again ; during “normal” operation of the CPU. ; <20> 09/17/91 jmp When “grounding out” the ECL clock, we also needed to make sure ; the 100 Mhz clock is shut off. This 100 Mhz clock is controlled ; by bit 9 (PIXSEL0) in the DAFB clock configuration register. I ; just added an equate for this. ; <19> 09/17/91 jmp Added support for “grounding out” the ECL clock signals in ; software using the AMD-ACDC for Zydeco/Spike33 CPUs. ; <18> 09/13/91 jmp Added support for 16pp on Rubik displays when only 512K of vRAM ; is around in preparation for Spike33s. ; <17> 8/26/91 jmp Added support for a Spike33-type box. ; <16> 8/21/91 jmp Changed all the Eclipse33 references to Zydeco. ; <15> 8/9/91 jmp Added equates to fix a problem with NTSC & PAL family modes ; where changing the amount of vRAM didn’t cause DAFB’s part of ; PrimaryInit to re-validate the SP_LastConfig pRAM byte. Also, ; added a boundary equate to distinguish 16bpp-capable DAFB sRsrcs ; from non-16bb-capable sRsrcs. ; <14> 8/7/91 jmp Added 16bpp support for all applicable DAFB displays. ; <13> 7/29/91 jmp Added equates for supporting Eclipse33 (Zydeco) & TIM-LC. ; <12> 7/13/91 jmp Added constants to support extending the factory burn-in ; no-connect code. ; <11> 7/11/91 jmp Added code to more intelligently handle the enabling & disabling ; of page mode. ; ——————————————————————————————————————————————————————————————————————————————————————— ; Pre-Zydeco ROM comments begin here. ; ——————————————————————————————————————————————————————————————————————————————————————— ; <10> 6/29/91 jmp Changed the DAFBDriver version number back to $00 from $01. ; <9> 6/27/91 jmp Added version number constants for the various DAFB revisions. ; <8> 6/26/91 jmp Rewrote the ACDC-whacking code to be more AC842A (AMD) friendly. ; <7> 6/25/91 jmp Fixed the problem where 16bpp was not sticking. ; <6> 6/24/91 jmp Added support for 16bpp Vesuvio & RGB Portrait displays. ; <5> 6/17/91 jmp Updated the base address offsets and rowbytes for NTSC, PAL, ; SuperVGA, GoldFish, Kong, and Vesuvio in order to accomodate ; Mitsubishi vRams. Also, updated the MinorLength values to ; accomodate the new base addresses and rowbytes. ; <4> 5/25/91 jmp The DAFBIdle macro was shutting off DAFB entirely. For the most ; part, this is NOT wrong; however, if we completely shut DAFB off ; at driver close time, and someone reopens the driver before the ; machine is restarted, we can’t get video going again without ; going thru the entire DAFB reset cycle, which causes the screen ; to jump. So, I now just kill sync and video refresh, which does ; exactly what I need. ; <3> 5/24/91 jmp Added support for sync-on-green in DAFB and cleaned up the ; DAFBResetDelay macro. ; <2> 5/22/91 jmp Now enable/disable fast page mode depending on whether DAFB is ; configured for row interleave vRam accesses. I only added this ; to the driver version of the DAFBSpeed macro because we don’t ; need to do this in PrimaryInit. ; <1> 5/22/91 jmp Changed name to DepVideoEqu.a from RBVDepVideoEqu.a to reflect ; the fact that this file is used by all built-in videos, not ; just RBV. ; <25> 5/15/91 jmp Added DB-Lite support. Also, had the wrong constant for ; indexedSenseFP; should have been 1 not 5 (5 is for ; indexedSenseRGBFP). This caused the Portrait Display to not be ; luminance-mapped when “Color” mode was turned on. ; <24> 5/10/91 jmp Added sRsrc constants for SuperVGA. Aliased IsSlow to Is16 (bit ; 11) in GFlags for supporting 25 vs. 33 MHz CPU configs. Added ; new DAFBSpeed macros for PrimaryInit & Driver. Code review ; changes: cleaned up the DAFB macros. ; <23> 4/26/91 jmp Added a new baseAddr offset constant for PAL convolved. ; <22> 4/25/91 jmp Updated dafb33MhzConfig constant to new value for 80ns VRam. ; <21> 4/23/91 jmp Added indexedSense codes for the 2P and FP displays, and fixed ; the Minor/MajorLength values for non-convolved PAL were wrong ; (i.e., they were zero). ; <20> 4/15/91 djw Add spId for functional video sRsrc's video attibutes (a data ; field). ; <19> 4/4/91 jmp My previous “optimization” caused some DAFB 1 machines to hang. ; So, I now read the DAFB test register 4 times, which could take ; as long as 480 ns. We only 320 ns DAFB reset writes (even on ; DAFB 1s), so this should be okay. ; <18> 4/3/91 jmp Reduced the number of Nops in the DAFBResetDelay macro to two ; (from eight). I determined this value empirically; before, I ; was just guessing based on Dale Adam’s spec. ; <17> 4/1/91 jmp SixteenBitGray & ThirtyTwoBitGray were inverted! ; <16> 3/25/91 jmp Added a record for Slot pRam. ; <15> 3/18/91 jmp Updated rowbytes constants for 32bpp PAL. ; <14> 3/8/91 jmp Added a 768 rowbytes constant, and made the defmBaseOffset ; constants for PAL & NTSC more general. ; <13> 3/4/91 jmp Added equates (spIDs) for standard and inverse gamma tables. ; Added equates for factory burn-in stuff. ; <12> 2/25/91 jmp Added DAFBSpeed macro for supporting 33Mhz DAFBs. ; <11> 2/15/91 jmp Added various comments and cleaned up file. Added ; “indexEntries” equate for the -1 modes of Get/SetEntries. Also, ; added macro for checking/setting 33Mhz operation of DAFB. ; <10> 2/10/91 jmp Updated NTSC and PAL data for 4/8bpp convolved. Added ; defmBaseOffset to screen clearing params. Added in “Misc” ; params to video params for ChkMode in driver. The Rubik gamma ; table contained the 4•8/8•24 gType id! And updated GoldFish’s ; clock parameters (to match those of the Portrait Display). ; <9> 2/3/91 jmp Added the new rowbytes values (ST/FF) for PAL. Added ; MinorLength values for NTSCFF/ST a,b and PALFF/ST a. Added new ; defmBaseOffsets for NTSCST and PALST. Added sRsrc ID for 040 ; CPU family. And added base address offset constant for NTSC and ; PAL. ; <8> 1/30/91 jmp Added constants and macros to support the extended sense line ; encodings. Added a macro for doing DAFB resets. Added NTSCFF ; and NTSCST data. ; <7> 1/24/91 jmp Added some constants to support extended-sense-line displays. ; <6> 1/21/91 jmp Incremental change -- added support (spIDs) for monitors that ; have both RGB and Mono-Only types. ; <5> 1/15/91 DAF Added DAFB equates (billions of them), updated SONIC equates, ; moved some slot decl ROM type equates to ROMEqu.a. Also changed ; video spIDs to new ranges. ; <4> 1/9/91 JK Added Sonic Ethernet, Eclipse and Spike support. ; <3> 12/11/90 JJ Mac LC: Change all box flag references for Mac LC to use symbol ; boxMacLC. ; <2> 12/11/90 HJR Integration of V8 and Tim video into Terror Project. ; <5> 6/12/90 JJ Add support for Elsie Apple II emulation video modes. ; <4> 4/30/90 JJ Adding multiple board sRsrc support. ; <3> 4/9/90 JJ Rolling in changes from Reality. Original comments below. ; {4} 4/3/90 DAF Added equates for support of Elsie Video features. ; {3} 4/3/90 DF Relocated driver private storage flag bit name equates here from ; RBVDriver.a. They are shared with the Elsie driver here now ; <2> 2/15/90 CV Rolling in changes from Reality. Original comments below. ; {2} 2/14/90 DAF Updated equates for integration with Elsie video code. ; <2.0> 7/16/89 GMR Rolling in changes from 'Reality'. Original 'Reality' version is ; 2.1. Original comments are below. ; <2.1> 7/11/89 DAF FOR AURORA BUILD - Added equates for 1MB RAM size and flag word ; for non-16MHz machines ; <2.0> 7/11/89 DAF FOR AURORA BUILD - Relocated a lot of equates from here to ; ROMEqu.a ; 7/10/89 DAF Relocated many equates from this file to ROMEqu.a where they ; really belong. Generally cleaned up file. Changed MinorLength ; equates to be true size of frame buffer rather than rounded ; size. ; <1.9> 6/30/89 CSL Updated CPUShift to place CPU sRsrc id's in the proper range ; <1.8> 6/30/89 DAF Added a number of new equates for the declaration ROM, including ; board and CPU IDs ; 6/30/89 DAF Corrected CPUShift to place the sRsrc directory entries in the ; appropriate order. ; 6/28/89 DAF Added equates for the monitor sense ID's. Added official board ; and drHwIDs for RBV machines. Added false board IDs for other ; CPUs. Corrected RAM lengths since MMU.a does 32K wraparounds on ; frame buffer ; <1.7> 5/27/89 DAF Updated equates for minor length in each of the different Aurora ; video modes ; <1.6> 5/16/89 DAF Updated equates to make video mode family names a superuser ; feature ; 5/16/89 DAF Added name dir shift value ; <1.5> 5/15/89 DAF Added some new equates in support of PrimaryInit and declData ; changes ; 5/6/89 DAF Added sNameDirFlags, name ResIDs ; <•1.4> 4/15/89 DAF Added sGammaDirectory equate ; 4/15/89 DAF Added sGammaDir ; <1.3> 2/27/89 DAF Removed A/UX 1.0 driver equates ; 2/27/89 DAF Removed A/UX equates, added scrnInval definition for now. ; <1.2> 2/21/89 djw deleted equates for new slot manager temporarily put in this ; file ; <1.1> 11/14/88 DAF Removed redundant hardware equates (now in HardwareEqu.a) ; <1.0> 11/11/88 DAF Adding to EASE for the first time. ; 10/31/88 DAF Integrated some equates from the old DeclData.a file ; 10/26/88 DAF New today. ; Various build flags… ; ApolloSupported Equ 0 ; Apollo isn’t really supported by Horror, so no use carrying it around. RBVSupported Equ 0 ; We needed more space, and RBV was the logically thing to remove at this point. TIMSupported Equ 0 ; Needed even more space. CheckSumEnabled Equ 0 ; No need to have the SlotManager checksum us since the ROM start code does it, too! ; Driver Version Numbers… ; CurRBVDrvrVersion Equ $0000 ; Word-sized version numbers (like 'vers' resources). CurElsieDrvrVersion Equ $0000 CurV8DrvrVersion Equ $0001 ; LC/LCII are 0.0, LC930 is 0.1. CurTimDrvrVersion Equ $0000 CurDAFBDrvrVersion Equ $0007 ; Spike/Eclipse are 0.0, Zydeco is 0.1/0.2. ; Wombat is 0.3. ; System Enabler 040 (v1.0) is 0.4. ; Primus/Optimus is 0.5. ; WaterWings (Pontoon Disk) is 0.6. ; SuperMario has been bumped to 0.7 even though its ; functionality (currently 12-6-93) is still at 0.3. ; Need to update it ASAP! ; Excelsior (STP/rocinante) is 0.8. CurApolloDrvrVersion Equ $0000 CurDBLiteDrvrVersion Equ $0001 CurGSCDrvrVersion Equ $0000 ; Renamed DBLiteDriver to GSC internally! CurSonoraDrvrVersion Equ $0001 ; LC III is 0.0, PDM is 0.1. CurCSCDrvrVersion Equ $0001 ; 0.0 is Escher, BlackBird is 0.1, Yeager is 0.2. CurCivicDrvrVersion Equ $0001 ; Version 0.1 has fix Display Manager ; Misc Equates… ; kMegRAM EQU $100000 ; constant for 1Mb k1536KvRAM Equ $180000 ; constant for 1.5Mb k256KvRAM EQU (256*1024) ; constant for 256Kb k512KvRAM EQU (512*1024) ; constant for 512Kb k1MvRAM EQU (1024*1024) ; constant for 1MB k2MvRAM EQU 2*k1MvRAM ; constant for 2MB seSuccess EQU 1 ; sucessful sExec ROMRevLevel Equ 5 ; We’re on the 5th (major) revision of the Slot 0 DeclData. CPUShift EQU $B0 ; add this value to board spIDs to ; create CPUspIDs ClrDepthBitsMask EQU $F8 ; bit mask to clear V8 and Ariel control register screen ; depth bits (top 5 bits) indexEntries Equ -1 ; -1 mode for Get/SetEntries. alphaEntries Equ -2 ; -2 mode for Get/SetEntries (uses alpha channel in CLUT) burnInSiz Equ $0004 ; Number of bytes in pRAM for burn-in signature. burnInLoc Equ $00FC ; Where burn-in signature starts in pRAM. burnInSig Equ 'RNIN' ; The burn-in signature. burnInSigAlt Equ 'SRNN' ; The alternate burn-in signature. burnInSig12 Equ 'RN12' ; These are the new burn-in signatures. They burnInSig13 Equ 'RN13' ; define all the Apple-produced displays. burnInSig15 Equ 'RN15' ; We could define similar signatures for burnInSig16 Equ 'RN16' ; things like VGA, NTSC, and PAL, but the burnInSig19 Equ 'RN19' ; factory probably couldn’t use them anyway. burnInSig21 Equ 'RN21' ; Timing mode constants for Display Manager MultiMode support ; Corresponding .h equates are in DisplaysPriv.h ; .a equates are in DepVideoEqu.a ; .r equates are in DepVideoEqu.r timingInvalid Equ 0 ; Unknown timing… force user to confirm. timingApple12 Equ 130 ; 512x384 (60 Hz) Rubik timing. timingApple12x Equ 135 ; 560x384 (60 Hz) Rubik-560 timing. timingApple13 Equ 140 ; 640x480 (67 Hz) HR timing. timingApple13x Equ 145 ; 640x400 (67 Hz) HR-400 timing. timingAppleVGA Equ 150 ; 640x480 (60 Hz) VGA timing. timingApple15 Equ 160 ; 640x870 (75 Hz) FPD timing. timingApple15x Equ 165 ; 640x818 (75 Hz) FPD-818 timing. timingApple16 Equ 170 ; 832x624 (75 Hz) GoldFish timing. timingAppleSVGA Equ 180 ; 800x600 (56 Hz) SVGA timing. timingApple1Ka Equ 190 ; 1024x768 (60 Hz) VESA 1K-60Hz timing. timingApple1Kb Equ 200 ; 1024x768 (70 Hz) VESA 1K-70Hz timing. timingApple19 Equ 210 ; 1024x768 (75 Hz) Apple 19" RGB. timingApple21 Equ 220 ; 1152x870 (75 Hz) Apple 21" RGB. timingAppleNTSC_ST Equ 230 ; 512x384 (60 Hz, interlaced, non-convolved). timingAppleNTSC_FF Equ 232 ; 640x480 (60 Hz, interlaced, non-convolved). timingAppleNTSC_STconv Equ 234 ; 512x384 (60 Hz, interlaced, convolved). timingAppleNTSC_FFconv Equ 236 ; 640x480 (60 Hz, interlaced, convolved). timingApplePAL_ST Equ 238 ; 640x480 (50 Hz, interlaced, non-convolved). timingApplePAL_FF Equ 240 ; 768x576 (50 Hz, interlaced, non-convolved). timingApplePAL_STconv Equ 242 ; 640x480 (50 Hz, interlaced, non-convolved). timingApplePAL_FFconv Equ 244 ; 768x576 (50 Hz, interlaced, non-convolved). ; Various extra Control/Status calls used by built-in video ; cscV8GoodBye Equ 128 ; Used by V8Driver for graying the screen at reset time. cscRubik560 Equ 129 ; Used by the SonoraDriver to toggle the Rubik-560 mode. cscSyncOnGreen Equ 128 ; Used by DAFBDriver for enabling/disabling sync on green. csc16bpp Equ 129 ; Used by DAFBDriver for allowing/blocking 16bpp when AC842A is around. cscPageMode Equ 130 ; Used by DAFBDriver for enabling/disabling page mode. cscAltSense Equ 131 ; Used by for enabling sRsrcs via the alternate sense pRAM byte (Sonora/DAFB). cscPowerSelect Equ 132 ; Turn on/off power to the video circuitry (VSC/Jet/Keystone). cscSleepWake Equ 134 ; Sleep/Wake the video circuitry (in some cases, could be the same as cscPowerSelect). powerSelSig Equ 'powr' ; Signature returned in csData by the cscPowerSelect status call. sleepWakeSig Equ 'slwk' ; Signature returned in csData by the cscSleepWake status call. ; Cyclone specific private calls cscSetCompositeOut Equ 133 ; Used by CivicDriver for setting/clearing the PRAM flag for composite out cscSetRGBBypass Equ 135 ; Used by CivicDriver for bypassing RGB outputs (enabling composite-out) on Civic. cscSetVideoIn Equ 136 ; Used by CivicDriver for enabling/disabling video-in. cscSetVidInMode Equ 137 ; Used by CivicDriver for selecting the video-in mode. cscSetVidInRect Equ 138 ; Used by CivicDriver for specifying the destination Rect for Video-in. cscGetCompositeOut Equ 133 ; Used by CivicDriver for getting the status of the PRAM flag for composite out cscGetRGBBypass Equ 135 ; Used by CivicDriver for getting the status of the RGB outputs. cscGetVideoIn Equ 136 ; Used by CivicDriver for getting the video-in status. cscGetVidInMode Equ 137 ; Used by CivicDriver for getting the video-in mode. cscGetVidInRect Equ 138 ; Used by CivicDriver for getting the destination Rect for Video-in. cscGetCompCapab Equ 139 ; Used by CivicDriver for getting the available composite capabilities for the current monitor ; Slot pRAM ; ; Slot pRam is used in various ways. The first two bytes are used by the Slot Manager to record ; the slot’s boardID. The remaining bytes are left undefined by the Slot Manager. Built-in ; video uses Slot pRam as follows: ; SP_Params Record 0 SP_BoardID Ds.w 1 ; BoardID. SP_Depth Ds.b 1 ; spID of Depth (Mode). (vendorUse1) SP_LastConfig Ds.b 1 ; spID of last boot-up configuration. (vendorUse2) SP_DfltConfig Ds.b 1 ; spID of default configuration… (vendorUse3) SP_MonID Ds.b 1 ; Sense code of last display. (vendorUse4) SP_Flags Ds.b 1 ; Various flags. (vendorUse5) SP_AltSense Ds.b 1 ; Alternate senseID byte. (vendorUse6) SP_Size Equ * EndR ; Slot pRAM flag bits ; spSyncOnGreen Equ 0 ; True if we’re supposed to put sync on green (DAFB). spHas16bppACDC Equ 1 ; True if AC842A is around on DAFB. spAllow16bpp Equ 2 ; True if we’re allowing 16bpp to be used on DAFB. spPageMode Equ 3 ; True if we’re enabling DAFB’s PageMode. spHas16bppSRsrc Equ 4 ; True if we’ve actually using a 16bpp sRsrc on DAFB. spAltSenseEnb Equ 5 ; True if AltSense was used before (for keeping SOG state). spVRAMBit0 Equ 0 ; These two bits are used to encode the amount of spVRAMBit1 Equ 1 ; vRAM available in Sonara-based CPUs. numSPVRamBits Equ 2 ; Width for Bfins/Bfext of spVRAMBits spVRAMBits Equ 31-spVRAMBit1 ; Offset for Bfins/Bfext. spKbdNMI Equ 2 ; True if we’re enabling Keyboard NMI (Sonora). spFamilyChanged Equ 2 ; True if the family mode changed on PDM; always reset in PrimayrInit. spNoVRAM Equ 3 ; True if video RAM is not VRAM-based. spVideoIn Equ 0 ; True if we’re supposed to enable video-in (Civic). spCompOut Equ 1 ; True if we should drive out composite even if no monitor connected (CIVIC) spCompOutPAL Equ 2 ; If spCompOut is set, then this tells us (if true), to drive PAL. (CIVIC) spOpenComponent Equ 3 ; True if Open call to a component is for registering purposes only! (Civic) ; Note: In Cyclone, the Built-in sound sifter will use bits 4-7 of the SP_Flags byte of the Slot 0 PRAM spSampleRate Equ 4 ; The built-in sound sifter's hardware output sample rate ( 0 => SampleRate 24 or 48, 1 => SampleRate 22.05 or 44.1) spClockRate Equ 5 ; The built-in sound sifter's hardware output clock rate ( 0 = Selects the first clock input to the PLL, 1 selects 2nd clock) spPlayThrough Equ 6 ; Specifies whether sound-playthrough for the whole system (0 = noPlayThrough) spMikeOrCDInput Equ 7 ; Specifies the source for the sound input (External Mike = 0, Internal CD = 1) ; Slot pRAM alternate senseID masks ; spAltSenseValidMask Equ $40 ; Upper two bits must be valid in order to use lower six. spAltSenseMask Equ $3F ; Lower six bits are the indexed (mapped) sense code. spAltSenseDisable Equ $80 ; Bits used for temporarily disabling the alternate senseID. ; Definition of each of the entries in the ‘scrn’ resource. ; ScrnRecord Record 0 srDrvrHW Ds.w 1 ; Hardware id of video card. srSlot Ds.w 1 ; Slot number. srDCtlDevBase Ds.l 1 ; DCtlDevBase (baseAddr) from AuxDCE. srMode Ds.w 1 ; Mode (spID) of depth. srFlagMask Ds.w 1 ; ???? srFlags Ds.w 1 ; GDevice flags. srColorTable Ds.w 1 ; RsrcID of desired ‘clut’. srGammaTable Ds.w 1 ; RsrcID of desicred ‘gama’. srRect Ds.w 4 ; GDevice rectangle. srCtlCount Ds.w 1 ; ???? ScrnRecSize Equ * Endr ; Definition for the “mini” gamma table used by many of the various PrimaryInits. ; MiniGamma Record 0 ; Entries for mini gamma table used in DAFBInit. blackRed Ds.b 1 ; Red whiteRed Ds.b 1 ; blackGreen Ds.b 1 ; Green whiteGreen Ds.b 1 ; blackBlue Ds.b 1 ; Blue whiteBlue Ds.b 1 ; Ds.b 2 ; GT_Size Equ * Endr ; Definition for the Cyclone Private Records VDVidInRect RECORD 0 csRect DS.W 4 ; Rect - (long) rectangle containg bounds of video in csPage DS.W 1 ; INTEGER - (word) page to switch in csBaseAddr DS.L 1 ; Ptr - (long) base address of page ENDR VDCompositeOut RECORD 0 csMode DS.b 1 ; BYTE - (byte) enable/disable flag csStandard DS.b 1 ; BYTE - (byte) NTSC/PAL flag csConv Ds.b 1 ; BYTE - (byte) NonConv/Conv flag ENDR VDInternalInfo RECORD 0 csMode DS.b 1 ; BYTE - spID to get info on csNTSCID DS.b 1 ; BYTE - spID of corresponding NTSC-capable parameters csNTSCIDConv DS.b 1 ; BYTE - spID of corresponding NTSC Conv-capable parameters csPALID DS.b 1 ; BYTE - spID of corresponding PAL-capable parameters csPALIDConv DS.b 1 ; BYTE - spID of corresponding PAL Conv-capable parameters ENDR ; Various DAFB Equates… ; ; The screen clearing code for DAFB is pretty straight forward with a couple of minor wrinkles. The ; wrinkles come about because NTSC and PAL support both “safe title” (ST) and “full frame” (FF) display ; areas. Since the ST mode is always smaller in area than a display’s FF area, the “non-viewable” area ; in the ST mode must be “blacked out.” But, in order to keep the code general, we always try to ; draw the border. In order to do this, we must carry around the FF vs. ST information. The following ; SC_Params record is where that information is housed. ; SC_Params Record 0 SC_ActiveWidth Ds.w 1 ; Number of doublelongs-1 (per row) for active part of screen. SC_BorderHeight Ds.w 1 ; Number of rows for Top/Bottom section of border. SC_BorderWidth Ds.w 1 ; Number of longs-1 for Top/Bottom section of border. SC_BorderSide Ds.w 1 ; Number of longs for Left/Right section of border (in Middle). SC_SkipFactor Ds.w 1 ; Difference between rowbytes and cleared part of screen. SC_Size Equ * EndR DAFBBppParams Record 0,Increment ; This structure is used for switching depths. dbpRowWords Ds.w 1 ; Framebuffer params. dbpClkCfg Ds.w 1 ; dbpConfig Ds.w 1 ; dbpHSerr Ds.w 1 ; Horizontal timing params. dbpHlfLn Ds.w 1 ; dbpHEq Ds.w 1 ; dbpHSP Ds.w 1 ; dbpHBWay Ds.w 1 ; dbpHBrst Ds.w 1 ; dbpHBP Ds.w 1 ; dbpHAL Ds.w 1 ; dbpHFP Ds.w 1 ; dbpHPix Ds.w 1 ; dbpTimingAdj Ds.w 1 ; dbpACDCPCBR Ds.w 1 ; ACDC (CLUT/DAC) PCBR. dbpTimingAdjAMD Ds.w 1 ; Alternate AMD parameters dbpHALAMD Ds.w 1 ; dbpHFPAMD Ds.w 1 ; DBPSize Equ * Endr DAFBVidParams Record 0,Increment ; This structure is used for programming DAFB. dvpNSC8531 Ds.b 10 ; The NSC-8531 programmable clock parameters. dvpNSC8534 Ds.w 3 ; The NSC-8534 programmable clock parameters. DVPMaxModeBase Equ * dvpMaxModeA Ds.b 1 ; Maximum mode (depth) for A-sized sRsrc. dvpMaxModeB Ds.b 1 ; Maximum mode (depth) for B-sized sRsrc. dvpBadDepth Ds.b 1 ; Index of depth having “bad” AMD param; 0 if okay. dvpFudge Ds.b 1 ; Fudge factor to add to bad AMD param. dvpNumRows Ds.w 1 ; Number of rows-1 for active (QD) part of screen. dvpVHLine Ds.w 1 ; Vertical timing params. dvpVSync Ds.w 1 ; dvpVBPEq Ds.w 1 ; dvpVBP Ds.w 1 ; dvpVAL Ds.w 1 ; dvpVFP Ds.w 1 ; dvpVFPEq Ds.w 1 ; DVPHdrSize Equ * ; dvpRowWords Ds.w 1 ; Keep up-to-date with DAFBBppParams. dvpClkCfg Ds.w 1 ; (Used for 1bpp in PrimaryInit.) dvpConfig Ds.w 1 ; dvpHSerr Ds.w 1 ; dvpHlfLn Ds.w 1 ; dvpHEq Ds.w 1 ; dvpHSP Ds.w 1 ; dvpHBWay Ds.w 1 ; dvpHBrst Ds.w 1 ; dvpHBP Ds.w 1 ; dvpHAL Ds.w 1 ; dvpHFP Ds.w 1 ; dvpHPix Ds.w 1 ; dvpTimingAdj Ds.w 1 ; dvpACDCPCBR Ds.w 1 ; dvpTimingAdjAMD Ds.w 1 ; dvpHALAMD Ds.w 1 ; dvpHFPAMD Ds.w 1 ; Endr ; Versions of the DAFB chip (accessed on the DAFBTest register). ; DAFB1Vers Equ $00 ; DAFB 1: Original hardware release. DAFB2Vers Equ $01 ; DAFB 2: Fix for NTSC & PAL 1,2 bpp modes. DAFB3Vers Equ $02 ; DAFB 3: Support for AC842A (16bpp ACDC). DAFB4Vers Equ $03 ; DAFB 4: The Wombat DAFB. ; Instead of burning valuable pRAM to communicate between PrimaryInit/SecondaryInit and the video ; driver, we use a conviently unused DAFB 12-bit register. ; DAFBFlags Equ Swatch_Test ; A conveniently unused DAFB 12-bit register. rvBeenHere Equ 0 ; The “beenHere” flag for the Remote Video Switch. rvChanged Equ 1 ; Says whether the remote video switch has changed states. rvRemoteState Equ 2 ; The “beenHere” state of remote video. isWombat Equ 3 ; If this bit is set, we’ve got a WombatDAFB. RadiusTPDBit Equ 4 ; If this bit is set, a Radius TPD is attached. RadiusDevType Equ 5 ; RadiusTPD DevType: 0=monochrome, 1=color. wLin16Bpp Equ 6 ; For Wombat, set if using the linear 16bpp CLUT/DAC. w40MHz Equ 7 ; For Wombat, set if running at 40Hz. vRamBit0 Equ 9 ; These two bits say whether there is 512K, 1Meg, or vRamBit1 Equ 10 ; 2Megs of vRAM associated with DAFB. numVRamBits Equ 2 ; Width for Bfins/Bfext of the vRamBits. vRamBits Equ 31-vRamBit1 ; Offset for Bfins/Bfext. videoEnabled Equ 11 ; Set if video is actually turned on. ; DAFB supports a large number of displays, some of which do NOT share the same base address as ; the others. The reason for this is due to hardware constraints (e.g., in order to clock the ; data out fast enough for some large displays and convolved modes, it is necessary to interleave ; and align vRam). ; DAFBStdOffset EQU $1000 ; Active video offset from base of frame buffer vRAM for most displays. DAFB2POffset Equ $0A00 ; Active video offset for Kong & Vesuvio (1-16bpp). DAFB2POffsetW Equ $0080 ; Acivie video offset for Wombat (1-8bpp). DAFBBSOffset EQU $0E00 ; Active video offset for GoldFish & SuperVGA (1-32bpp). DAFBBSOffsetW Equ $0080 ; Active video offset for Wombat BS, 1-32bpp. DAFBNTSCOffset Equ $1020 ; Active video offset for NTSC Displays. DAFBNTSCConvOff Equ $1400 ; Active video offset for NTSC convolved Displays. DAFBPALOffset Equ $0E20 ; Active video offset for PAL Displays. DAFBPALOffsetW Equ $0700 ; Acitve video offset for PAL on Wombat. DAFBPALConvOff Equ $1420 ; Active video offset for PAL convolved Displays. ; DAFB supports several displays that are in the “extended” sense line range. Since the raw ; values that come back from doing the extended sense-line algorithm do not map into a nice ; tablular form like the “normal” sense line codes do, we map the few extended-sense-line displays ; that we support into the bottom of the normal sense line table. ; ; Notes: The “normal” sense displays fall in the range of 0..7, where 7 means “go try the ; extended sense codes.” So, we map the extended sense codes from 8 (yeah, we have ; blank entry). ; ; Radius exploits the fact that the extended sense algorithm is generally only tried ; when a 7 is read back. That is, for their two TPD displays (one color, the other ; monochrome), they use 3 as the trigger for doing the extended sense algorithm. To ; distinguish the two displays from each other, they just reverse the polarity of the ; the diode on sense lines b & c. (Note: This technique could be used for sense ; codes 5 and 6, too.) ; ; So, it should be noted, that there are four types of extended sense codes. We ; just use types 3, 6, and 7; type 5 is reserved. ; extended2P Equ $35 ; Raw Extended Sense for the Two-Page Display. extended2PRdRGB Equ $31 ; Raw Extended Sense for Radius’ Color TPD. extended2PRdMono Equ $34 ; Raw Extended Sense for Radius’ Mono TPD. extendedRGBFP Equ $1E ; Raw Extended Sense for the RGB Full-Page Display. extendedHR Equ $2B ; Raw Extended Sense for the Hi-Res Display (type-6 extended sense). extendedMSB1 Equ $03 extendedMSB2 Equ $0B extendedMSB3 Equ $23 extendedNoConnect Equ $3F ; Raw Extended Sense for no connect. extendedSensePALBox Equ $00 ; Raw Extended Sense for PAL Encoder. extendedSenseNTSC Equ $14 ; Raw Extended Sense for NTSC Encoder. extendedSenseVGA Equ $17 ; Raw Extended Sense for VGA. extendedSenseLP Equ $2D ; Raw Extended Sense for GoldFish. extendedSenseGF Equ $2D ; Raw Extended Sense for GoldFish. extendedSensePAL Equ $30 ; Raw Extended Sense for PAL. extendedSense19 Equ $3A ; Raw Extended Sense for Third-Party 19” Displays. indexedSenseRGB2P Equ 0 ; For switching to 16bpp. indexedSenseFP Equ 1 ; For Mono-Only configs. indexedSenseRubik Equ 2 ; For factory burn-in testing. indexedSense2P Equ 3 ; For Mono-Only configs. indexedSenseNTSC Equ 4 ; To Map NTSC encoder boxes to NTSC displays. indexedSenseRGBFP Equ 5 ; For switching to 16bpp. indexedSenseHR Equ 6 ; DAF said we should do HR for the factory. indexedNoConnect Equ 7 ; (Here for consistency only.) indexedSenseVGA Equ 8 ; Mapped Sense For VGA. indexedSensePAL Equ 9 ; Mapped Sense For PAL. indexedSenseLP Equ 10 ; Mapped Sense For GoldFish. indexedSenseGF Equ 10 ; Mapped Sense For GoldFish. indexedSense19 Equ 11 ; Mapped Sense For 19" Displays. pIndexRdMono Equ 12 ; Pseudo Index for Radius’ Mono TPD. (DAFB) indexedSenseMSB1 Equ 12 ; Mapped Sense For Band-1 Multiscan Displays. indexedSenseMSB2 Equ 13 ; Mapped Sense For Band-2 Multiscan Displays. indexedSenseMSB3 Equ 14 ; Mapped Sense For Band-3 Multiscan Displays. dafbSenseLineA Equ 2 ; Numbers for bit-I/O on DAFB senselines. dafbSenseLineB Equ 1 ; dafbSenseLineC Equ 0 ; dafbAMask Equ 3 ; Masks for reading/writing DAFB senselines. dafbBMask Equ 5 ; dafbCMask Equ 6 ; tristateDAFBSense Equ 7 ; Value for tri-stating DAFB senselines. ; Resetting the DAFB is a process that requires 5 steps. First, the Swatch is released from ; its reset state. Then the Swatch reset mode is reassertd and re-released. Finally, ; the vRam and video refresh state machines are reset. The following equates are the masks ; for setting the right bits in the DAFB reset register. ; dafbReleaseSwatch Equ 3 ; See comments above. dafbReassertSwatch Equ 7 ; dafbReleaseVRamSM Equ 2 ; dafbReleaseVideoSM Equ 0 ; dafbResetIdle Equ 7 ; Value to idle DAFB reset register. dafbDisableSwatch Equ $FF1 ; Value to disable Swatch. dafbEnableSwatch Equ $FF2 ; Value to enable Swatch. ; In order for the ACDC and for the Clock to be programmed correctly, the DAFB_Config ; register must be set up for the right CPU clock speed (which just means turning ; on the WriteAccess bit in the DAFBConfig register). ; ; DAFB supports the fast page mode operation of the VRams. However, the only place where it ; really makes sense to turn this mode on (all the time) is when the VRams are configured ; for the row-interleave access (which is generally 640x480 @ 32bpp). Bit 1 of the ; DAFBConfig register is RowInterleave enable/disable bit; it is bit 30 for bit-field ; extraction & insertion, and that’s how we use it. ; ; Update to above: It really makes more sense to just turn page mode OFF when the VRams are ; configured for word-interleave. ; ; Wombat info: The WombatDAFB doesn’t support either word or row interleaving of VRam, so ; we just mask out those bits on Wombat in the DAFBSpeed macros. ; dafb33MHzConfig Equ $00000800 ; Mask for 33MHz setup (non-Wombat). dafb33MHzConfigW Equ $00000200 ; Mask for Wombat 33MHz setup. dafb40MHzConfigW Equ $00000A00 ; Mask for Wombat 40MHz setup. dafbWaitConfig Equ $00000F00 ; Mask for turning on ALL wait-states. dafbNoInterleave Equ $00000FFC ; Mask to clear interleave bits. dafbRowIntBit Equ 30 ; Bfins/Bfext-style numbers. dafbWrdIntBit Equ 31 ; On the WombatDAFB, the enable/disable for the sync-on-green signal bit 9 (PIXSEL0) of the Clock ; configuration register. In order to do this without disturbing the other bit-fields in this ; register, we use the bit-field insertion instruction; so, bit 9 is bit 22 for Bfins. ; dafbSyncOnGreen Equ 22 ; Bfins/Bfext-style number. ; Originally, we used the “real” VBL interrupt line for doing VBL interrupts. However, it ; turned out VBL was generated at vSync, and this was way too late in the cycle. So, ; to resolve this problem, we actually use the cursor interrupt line, which we can ; program ourselves. dafbIntStatusBit Equ 2 dafbDisableVInts Equ $0 dafbEnableVInts Equ $4 ; With the AMD-ACDC (AC842A), the ECL clock signals can be enabled and disabled in software. The ; only time we want to disable the ECL clock signals is when the PIXSEL1 (bit 10) of the DAFB clock ; configuration register is zero. In AC842A, bit 4 in PCBR1 selects whether the ECL or LD clock ; signals are used. (Note: When we do set the acdcPCS, we must also ensure that PIXSEL0 (bit 9) ; is set so that the 100Mhz clock is not passed thru DAFB, but instead uses the programmable ; clock generator.) acdcPCS Equ 31-4 ; Bfins/Bfext-style numbers. dafbPixSel0 Equ 31-9 dafbPixSel1 Equ 31-10 ; ; Macros to support various “weird” ways hardware must be accessed on the DAFB. ; Macro DAFBWWrite &dafbParam,&dafbReg ; A1->DAFBVidParams/DAFBBppParams,A2->DAFBBase. Move.w &dafbParam(A1),&dafbReg+2(A2) ; Write out word. EndMacro Macro DAFBBWrite &dafbParam,&dafbReg ; A1->DAFBVidParams/DAFBBppParams,A2->DAFBBase. Clr.w -(Sp) ; Make sure hi-bits are clear. Move.b &dafbParam(A1),1(Sp) ; Get byte from params. Move.w (Sp)+,&dafbReg+2(A2) ; Write it out. EndMacro Macro DAFBSetVidBaseAddr &baseOffset ; A2->DAFBBase, trashes D0. Move.l &baseOffset,D0 ; Get baseOffset into a D0. Andi.l #$001FFFFF,D0 ; VidBaseAddr is only be 21-bits: Lsr.l #5,D0 ; Bits [4:0] are always zero, Move.l D0,DAFB_VidBaseLo(A2) ; VidBaseLo = [8:5], Andi.l #$0000000F,DAFB_VidBaseLo(A2) ; (eliminate the unused bits), Lsr.l #4,D0 ; Shift out VidBaseLo, Move.l D0,DAFB_VidBaseHi(A2) ; VidBaseHi = [20:9]. EndMacro Macro DAFBSpeedPI ; A2->DAFBBase,A6->PrimFrame. Tst.b IsSlowClock(A6) ; If CPU is running “slow,” Bne.s @EndDAFBSpeedPI ; then leave things alone. Tst.b wombatDAFB(A6) ; If we’re on a Wombat, Bne.s @WombatSpeedPI ; then do the Wombat setup. Ori.l #dafb33MHzConfig,DAFB_Config(A2) ; Otherwise, setup for 33MHz operation. Bra.s @EndDAFBSpeedPI ; (Skip Wombat setup.) @WombatSpeedPI Andi.l #dafbNoInterleave,DAFB_Config(A2) ; For Wombat, vRAM interleaving is not possible. Ori.l #dafb33MHzConfigW,DAFB_Config(A2) ; Set up for at least 33MHz operation. Subq #2,Sp ; Make some room on the stack. Move.w DAFBFlags+2(A2),(Sp) ; Get the DAFBFlags. Andi.w #(1<DAFBBase,A3->DAFBVidPrivates,D0 trashed. Tst.b wombatFlag(A3) ; If we’re not on a Wombat, Beq.s @EndDAFBIntDR ; then just go on. Andi.l #dafbNoInterleave,DAFB_Config(A2) ; Otherwise, clear the interleave bits. @EndDAFBIntDR Move.l DAFB_Config(A2),D0 ; Read the DAFBConfig register. Bfextu D0{dafbWrdIntBit:1},D0 ; If word-interleave is on, Bne.s @DisablePageMode ; then ALWAYS disable page mode. Tst.b pageModeSet(A3) ; If we’re not supposed to enable page mode, Beq.s @DisablePageMode ; just go on. Moveq #1,D0 ; Otherwise, set up to enable page mode, Bra.s @HitPageMode ; and do it. @DisablePageMode Moveq #0,D0 ; Set up to disable page mode, and @HitPageMode Move.l D0,DAFB_PgMdEn(A2) ; and do it. Btst #IsSlow,GFlags(A3) ; If CPU is running “slow,” Bne.s @EndDAFBSpeedDR ; then leave alone. Tst.b wombatFlag(A3) ; If we’re on a Wombat, Bne.s @WombatSpeedDR ; then do the Wombat setup. Ori.l #dafb33MHzConfig,DAFB_Config(A2) ; Otherwise, setup for 33MHz operation. Bra.s @EndDAFBSpeedDR ; (Skip Wombat setup.) @WombatSpeedDR Ori.l #dafb33MHzConfigW,DAFB_Config(A2) ; Set up for at least 33MHz operation. Subq #2,Sp ; Make some room on the stack. Move.w DAFBFlags+2(A2),(Sp) ; Get the DAFBFlags. Andi.w #(1<DAFBBase. Andi.l #~(1<DAFBBase. Ori.l #(1<DAFBBase. Move.l #dafbReleaseSwatch,DAFB_Reset(A2) ; Release Swatch from reset. DAFBResetDelay ; Wait. Move.l #dafbReassertSwatch,DAFB_Reset(A2) ; Reset Swatch again. DAFBResetDelay ; Wait. Move.l #dafbReleaseSwatch,DAFB_Reset(A2) ; Release swatch from reset. DAFBResetDelay ; Wait. Move.l #dafbReleaseVRamSM,DAFB_Reset(A2) ; Reset VRam state machine. DAFBResetDelay ; Wait. Move.l #dafbReleaseVideoSM,DAFB_Reset(A2) ; Reset Video refresh state machine. DAFBResetDelay ; Wait. EndMacro Macro DAFBResetSenseLines ; A2->DAFBBase. Move.l #tristateDAFBSense,DAFB_SENSE(A2) ; Tristate DAFB sense lines. DAFBResetDelay ; Wait. EndMacro Macro DAFBReadSenseLines &senseLines ; A2->DAFBBase. Clr.l -(Sp) ; Senseline scratch on stack. Move.l DAFB_Sense(A2),(Sp) ; Read the sense lines. Not.b 3(Sp) ; Invert the lines… Andi.b #7,3(Sp) ; …and extract lo 3-bits. Move.b 3(Sp),&senseLines ; Return them to caller. Tst.l (Sp)+ ; Restore stack. DAFBResetSenseLines ; Reset lines & Wait. EndMacro ; ; Various GSC Equates… ; ; Switching depths on GSC’s is pretty straight forward. The following equates are for the GSCGrayScale register. ; They are Bfins/Bfext-type equates, so the bit-number is reverse of normal. ; GSCLevelWidth Equ 3 ; Number of bits in level field. GSCLevelBit0 Equ 0 ; The GSC-level bits. GSCLevelBit1 Equ 1 GSCLevelBit2 Equ 2 GSCLevelBits Equ 31-GSCLevelBit2 ; For use with Bfins/Bfext. GSCBlankCtl Equ 5 ; For enabling/disabling the blank shade. GSCBlankBit Equ 31-GSCBlankCtl ; For use with Bfins/Bfext. ; ; Various CSC Equates… ; ; The following record describes the video parameters for CSC built-in video. The first ; few parameters are for graying the screen, setting up sRsrcs, etc…. The rest of ; the parameters are the actual values that are programmed into the CSC registers. CSCBppParams Record 0,Increment cscbpFRCControl Ds.b 1 ; cscbpPolyMAdj Ds.b 1 ; cscbpPolyNAdj Ds.b 1 ; cscbpGFRCControl Ds.b 1 ; cscbpGPolyMAdj Ds.b 1 ; cscbpGPolyNAdj Ds.b 1 ; CSCBppSize Equ * Endr CSCVidParams Record 0,Increment cscvpMaxModeBase Equ * cscvp512KMax Ds.b 1 ; Max Depths: 512K, cscvp1MegMax Ds.b 1 ; 1Meg. cscvpNumRows Ds.w 1 ; Number of rows (-1). cscvpPanelType Ds.b 1 ; Panel Setup Control. cscvpPanelSetup Ds.b 1 ; cscvpHSkewHi Ds.b 1 ; H/V Timing Params. cscvpHSkewLo Ds.b 1 ; cscvpVSkewHi Ds.b 1 ; cscvpVSkewLo Ds.b 1 ; cscvpACDClkHi Ds.b 1 ; Clocking Control. cscvpACDClkLo Ds.b 1 ; cscvpLPStart Ds.b 1 ; cscvpLPWidth Ds.b 1 ; cscvpFLMControl Ds.b 1 ; cscvpDataOutForm Ds.b 1 ; Panel type. CSCVPHdrSize Equ * cscvpFRCControl Ds.b 1 ; Keep up to date with CSCBppParams. cscvpPolyMAdj Ds.b 1 ; (Just used for 1bpp PrimaryInit). cscvpPolyNAdj Ds.b 1 ; cscvpGFRCControl Ds.b 1 ; cscvpGPolyMAdj Ds.b 1 ; cscvpGPolyNAdj Ds.b 1 ; CSCVPSize Equ * Endr ; ; The interrupt flags and enable bits are housed within the DisplayStatus register. The ; following equates are setting and clearing CSC VBL interrupts. The DisplayStatus ; register also controls “panel shading.” The CSCUnBlank equate is for taking ; the display from an “off” state (blanked) to an “on” state (unblanked). ; CSCDSIER Equ 0 ; The Interrupt Enable bit. CSCDSIFR Equ 1 ; The Interrupt Flag bit. CSCDSRBlankCtl Equ 2 ; When set, these registers enable CSCDSRBlankSts Equ 3 ; “normal” palette operation. CSCUnblank Equ $0C ; Mask enabling BlankCtl/Sts. ; ; Misc CSC bits/masks for various CSC registers… ; CSCPnlPwr Equ 3 ; PanelSetup: Power on/off panel. CSCPnlDataInv Equ 2 ; PanelSetup: Toggle to invert panel data. CSCPaletteBypass Equ 1 ; PanelType: Power on/off palette. CSCInvertVRAM Equ 3 ; GTweak: Toggle to invert VRAM data. CSCBetterDither Equ 0 ; GTweak: Whether dither is H or V oriented. ; ; Unlike most CLUT/DACs used in the various Macintosh CPUs, the CSC CLUT/DAC is called a ; Palette and is completely contained within the CSC itself. One of the Palette ; registers (called the PaletteMask) is used for logically removing video. We actually ; want all video data to be displayed, so we set the mask register to all 1’s (i.e., ; the PaletteMask is AND’d with the video data). ; CSCNoMask Equ $FF ; Enable all 8-bits of video data. ; ; The CSC is a reasonably programmable LCD controller. And, as a result, it supports several ; sizes and styles of LCDs. The list below is the set of panel IDs that identify the ; various LCDs that could potentially be supported by CPUs using the CSC. ; ; Note: In order to keep things sane (I think), we have allowed each of the products using ; CSC to have it’s own set of panel IDs. ; ; Escher/Yeager List… ; isC_S_TFT_640x480 Equ $00 ; Color, Single-Drive, TFT, 640x480. [Sharp] isG_S_TFT_640x400 Equ $04 ; Gray, Single-Drive, TFT, 640x400. [Hosiden] isG_D_STN_640x400 Equ $06 ; Gray, Dual-Drive, STN, 640x400. [Sharp] ; BlackBird List… ; isC_S_TFT_640x480a Equ $00 ; Color, Single-Drive, TFT, 640x480. [Sharp] isC_D_STN_640x480 Equ $01 ; Color, Dual-Drive, STN, 640x480. [Sharp] isC_S_TFT_640x480b Equ $02 ; Color, Single-Drive, TFT, 640x480. [NEC] isC_S_TFT_640x480c Equ $03 ; Color, Single-Drive, TFT, 640x480. [Hosiden] isC_S_TFT_640x480d Equ $04 ; Color, Single-Drive, TFT, 640x480. [Toshiba] isG_D_STN_640x480 Equ $05 ; Gray, Dual Drive, STN, 640x480. [Sharp] isG_S_TFT_640x480 Equ $06 ; Gray, Single-Drive, TFT, 640x480 [Hosiden] isNoConnect Equ $07 ; Indicates there is no panel connected. tristateCSC Equ $07 ; PanelControl: Make senselines inputs. ; ; Macros to support various “weird” ways hardware must be accessed on CSC. ; Macro _CSCMaxDelay ; Trashes D0. Moveq #0,D0 ; Clear both halves of D0. Move.w #2-1,D0 ; We’re going to do two loops. @OuterLoop Swap D0 ; Move outer counter to hiword. Move.w #25000-1,D0 ; Move inner counter to loword. @InnerLoop Tst.b ([VIA]) ; Wait a µs… Dbra D0,@InnerLoop ; …or 50,000. Swap D0 ; Dbra D0,@OuterLoop ; Endm Macro _CSCMinDelay Tst.b ([VIA]) ; Wait a µs… Tst.b ([VIA]) ; …or two… Tst.b ([VIA]) ; …or three. Endm ; ; Various Sonora Equates… ; ; The following record describes the video parameters for Sonora built-in video. The first ; set of parameters are for the Omega (clock generator) chip. The monitor code value ; tells Sonora the type of sync and h/v “line” values to use. The other parameters are ; for graying the screen, setting up sRsrcs, etc…. ; SonoraOmega Record 0,Increment SOmegaN Ds.b 1 ; Omega N,D,P values. SOmegaD Ds.b 1 SOmegaP Ds.b 1 Ds.b 1 SOmegaSize Equ * Endr SonoraVidParams Record 0,Increment svpOmega1 Ds.b SonoraOmega.SOmegaSize ; Omega1 Values. svpOmega2 Ds.b SonoraOmega.SOmegaSize ; Omega2 Values. SVPOmegaSize Equ * svpMonitorCode Ds.b 1 ; Monitor code value. Ds.b 1 ; svpMaxModeBase Equ * svp256Max Ds.b 1 ; Max depths: 256K, svp512Max Ds.b 1 ; 512K, svp768Max Ds.b 1 ; 768K. Ds.b 1 ; svpNoRAMMaxBase Equ * ; svp600Max Ds.b 1 ; Max depths: 600K, svp300Max Ds.b 1 ; 300K, svp068Max Ds.b 1 ; 68K. Ds.b 1 ; svpNumRows Ds.w 1 ; Number of rows (-1). SVPHdrSize Equ * svp1bppRowLongs Ds.w 1 ; 1bpp rowlongs-1. svp2bppRowLongs Ds.w 1 ; 2bpp rowlongs-1. svp4bppRowLongs Ds.w 1 ; 4bpp rowlongs-1. svp8bppRowLongs Ds.w 1 ; 8bpp rowlongs-1. svp16bppRowLongs Ds.w 1 ; 16bpp rowlongs-1. SVPSize Equ * Endr OmegaNBits Equ 7 ; Number of bits in Omega N field. OmegaDBits Equ 7 ; Number of bits in Omega D field. OmegaPBits Equ 2 ; Number of bits in Omega P field. ndpHR Equ $6EE50000 ; N,D,P value for 30.24 MHz (HR’s dot clock). ; Once we determine how much vRAM is actually installed into a Sonora System, we have to ; tell Sonora how much is there. Currently, Sonora Systems are limited to 768K, but ; 1024K is possible, so we’ll support it anyway. ; Sonora256K Equ 0 ; Bank0=256K,Bank1=0. Sonora512Ka Equ 1 ; Bank0=256K,Bank1=256K. Sonora512Kb Equ 4 ; Bank0=512K,Bank1=0. Sonora768Ka Equ 2 ; Bank0=256K,Bank1=512K. Sonora768Kb Equ 5 ; Bank0=512K,Bank1=256K. Sonora1024K Equ 6 ; Bank0=512K,Bank1=512K. SonoraWrap Equ 512 ; Where Sonora wraps vRAM. Why? ; The senselines for Sonora-based systems are very similar to DAFB. The main difference is that ; the Sonora uses the top nybble of the senseline regiters for input and the bottom nybble for ; output. ; sonoraSenseLineA Equ 2 ; Numbers for bit-I/O on Sonora senselines. sonoraSenseLineB Equ 1 ; sonoraSenseLineC Equ 0 ; sonoraEnableAMask Equ 3 ; Masks for writing Twisted Sonora senselines. sonoraEnableBMask Equ 5 ; sonoraEnableCMask Equ 6 ; sonoraAMask Equ 3 ; Masks for reading/writing Sonora senselines. sonoraBMask Equ 5 ; sonoraCMask Equ 6 ; tristateSonoraSense Equ 7 ; Value for tri-stating Sonora senselines. ; Miscellenous Sonora equates… ; SonoraVidBlnkBit Equ 7 ; Bit 7 of the SonoraVdModeReg. ; ; Macros to support various “weird” ways hardware must be accessed on Sonora. ; Macro SonoraDelay ; (D2 trashed.) Move.w #550,D2 ; It takes approximately 500 µs for @WaitLoop Tst.b ([VIA]) ; for the Omega programming to Dbra D2,@WaitLoop ; propage thru DFAC, Egret, etc…. EndMacro ; Macro SonoraReadSenseLines &senseLines ; A2->SonoraVdCtlBase, D2 trashed. SonoraDelay ; Wait. Moveq #0,D2 ; D2 used as senseline scratch. Move.b SonoraVdSenseRg(A2),D2 ; Read the lines into scratch. Lsr.b #4,D2 ; Get inputs out of upper nybble. Move.b D2,&senseLines ; Return seselines to caller. move.b $0cb3,D2 ; check boxflag to see if... cmp.b #$44, D2 ; is it EVT1 - PDM bne.s @notEVTone ; no, not EVT1 Move.b #0,SonoraVdSenseRg(A2) ; Tristate Sense lines on Evt1 board bra.s @next @notEVTone Move.b #tristateSonoraSense,SonoraVdSenseRg(A2) ; Tristate the sense lines. @next SonoraDelay ; Wait. Endm ; ; Various Civic Equates… ; fCivicVidIn Equ 0 ; cvpFlags bit flag -> true if sRsrc is a video-in sRsrc. mCivicGrBpp Equ 7 ; mask to determine the graphics bpp depth from Sebast PCBR mspVideoIn Equ 1 ; mask to ANDI into SP_Flags to isolate the video in flag. fCivicVidInBpp Equ 3 ; SebastPCBR's video-in bpp bit (0 based) fCivicVidInEnb Equ 4 ; SebastPCBR's convolution enable bit fCivicConvEnb Equ 5 ; SebastPCBR's convolution enable bit fCivicVidinCLUT Equ 6 ; SebastPCBR's CLUT Select Bit: (0 selects graphics CLUT, 1 selects Video-in CLUT) fCivicVidInOvly Equ 7 ; SebastPCBR's overlay enable bit (0-based) vCivicGr16Bpp Equ 4 ; SebastPCBR's value for 16bpp graphics on D2-D0 vCivicVidInBase Equ $50200800 ; The Video-in VRAM's base address LoadCliftonControl Equ $1E05 ; Word to load the Control Register in Clifton LoadCliftonProgram Equ $1E04 ; Word to load the Program Register in Clfton LoadCliftonMuxRef Equ $1E00 ; Word to enable the mux reference in Clfton ControlWordSize Equ 14 ; Size in bits of the Clifton control/program word ReadPUMAID Equ $1E24 ; Word to load set PUMA to read the ID register #PUMA PUMAVer1Id Equ %00101010 ; PUMA ID for Version 1 #PUMA CivicEntry Record 0,Increment ; Defines the entries in the CivicRecord (below). offset Ds.w 1 width Ds.w 1 CESize Equ * Endr CivicRecord Record 0,Increment ; This structure is used to read/write Civic registers. VBLInt Ds.l 1 ; $00 Enable Ds.l 1 ; $04 VDCInt Ds.l 1 ; $08 VDCClr Ds.l 1 ; $0C VDCEnb Ds.l 1 ; $10 VidInSize Ds.l 1 ; $14 VDCClk Ds.l 1 ; $18 ScanCtl Ds.l 1 ; $1C GSCDivide Ds.l 1 ; $20 VSCDivide Ds.l 1 ; $24 VRAMSize Ds.l 1 ; $28 RefreshCtl Ds.l 1 ; $2C BusSize Ds.l 1 ; $30 SpeedCtl Ds.l 1 ; $34 ConvEnb Ds.l 1 ; $38 SenseCtl Ds.l 1 ; $3C Sense0 Ds.l 1 ; $40 Sense1 Ds.l 1 ; $44 Sense2 Ds.l 1 ; $48 Tristate Ds.l 1 ; $4C SyncClr Ds.l 1 ; $50 ReadSense Ds.l 1 ; $54 RowWords Ds.l 1 ; $58 BaseAddr Ds.l 1 ; $5C VLDB Ds.l 1 ; $60 VHLTB Ds.l 1 ; $64 VActHi Ds.l 1 ; $68 Reset Ds.l 1 ; $6C VBLEnb Ds.l 1 ; $70 HLDB Ds.l 1 ; $74 HHLTB Ds.l 1 ; $78 HActHi Ds.l 1 ; $7C VBLClr Ds.l 1 ; $80 AdjF2 Ds.l 1 ; $84 AdjF1 Ds.l 1 ; $88 TestEnb Ds.l 1 ; $8C CntTest Ds.l 1 ; $90 HSerr Ds.l 1 ; $94 VInHAL Ds.l 1 ; $98 VInHFPD Ds.l 1 ; $9C VInHFP Ds.l 1 ; $A0 HlfLn Ds.l 1 ; $A4 HEq Ds.l 1 ; $A8 HSP Ds.l 1 ; $AC HBWay Ds.l 1 ; $B0 HAL Ds.l 1 ; $B4 HFP Ds.l 1 ; $B8 HPix Ds.l 1 ; $BC PipeD Ds.l 1 ; $C0 VHLine Ds.l 1 ; $C4 VSync Ds.l 1 ; $C8 VBPEq Ds.l 1 ; $CC VBP Ds.l 1 ; $D0 VAL Ds.l 1 ; $D4 VInVAL Ds.l 1 ; $D8 VInVFP Ds.l 1 ; $DC VFP Ds.l 1 ; $E0 VFPEq Ds.l 1 ; $E4 CurLine Ds.l 1 ; $E8 VInDoubleLine Ds.l 1 ; $EC (Civic II register) Endr CivicBppParams Record 0,Increment ; This structure is used for switching depths. cbpBusSize Ds.w 1 ; Framebuffer Params. cbpGSCDivide Ds.w 1 ; cbpRowWords Ds.w 1 ; cbpAdjF1 Ds.w 1 ; cbpAdjF2 Ds.w 1 ; cbpPipeD Ds.w 1 ; cbpSebastPCBR Ds.w 1 ; Sebastion (CLUT/DAC) PCBR. cbpHSerr Ds.w 1 ; Horizontal timing params. cbpHlfLn Ds.w 1 ; cbpHEq Ds.w 1 ; cbpHSP Ds.w 1 ; cbpHBWay Ds.w 1 ; cbpHAL Ds.w 1 ; cbpHFP Ds.w 1 ; cbpHPix Ds.w 1 ; CBPSize Equ * Endr CivicVidParams Record 0,Increment ; This structure is used to program Civic. CVPMaxModeBase Equ * cvpMaxGraphMode Ds.b 1 ; Max Graphics mode cvpMaxVidInMode Ds.b 1 ; Max Video-in mode cvpFlags Ds.b 1 ; Misc Flags byte. cvpConvEnb Ds.b 1 ; Only set if cvpScanCtl = interlaced. cvpNTSCid1Meg Ds.b 1 ; spID of NTSC timing for this resolution w/ 1 Meg VRAM cvpNTSCid2Meg Ds.b 1 ; spID of NTSC timing for this resolution w/ 2 Meg VRAM cvpPALid1Meg Ds.b 1 ; spID of PAL timing for this resolution w/ 1 Meg VRAM cvpPALid2Meg Ds.b 1 ; spID of PAL timing for this resolution w/ 2 Meg VRAM cvpConvNTSCid Ds.b 1 ; spID of NTSC Convolution timing for this resolution cvpConvPALid Ds.b 1 ; spID of PAL Convolution timing for this resolution cvpEndeavorM Ds.b 1 ; Endeavor (VidClk) params. cvpEndeavorN Ds.b 1 ; cvpEndeavorClk Ds.b 1 ; cvpScanCtl Ds.b 1 ; Progressive/Interlaced. cvpCliftonW Ds.l 1 ; Clifton's W Parameter cvpCliftonWSize Ds.b 1 ; Size of W Parameter cvpCliftonClk Ds.b 1 ; Clock Source for Clifton cvpPumaW Ds.l 1 ; Puma's W Parameter cvpPumaWSize Ds.b 1 ; Size of W Parameter cvpPumaClk Ds.b 1 ; Clock Source for Puma cvpVHLine Ds.w 1 ; Vertical timing params. cvpVSync Ds.w 1 cvpVBPEq Ds.w 1 cvpVBP Ds.w 1 cvpVAL Ds.w 1 cvpVFP Ds.w 1 cvpVFPEq Ds.w 1 cvpNumRows Ds.w 1 ; Number of rows - 1. CVPHdrSize Equ * cvpBusSize Ds.w 1 ; Keep up-to-date with CivicBppParams. cvpGSCDivide Ds.w 1 ; (Used for 1bpp in PrimaryInit.) cvpRowWords Ds.w 1 cvpAdjF1 Ds.w 1 cvpAdjF2 Ds.w 1 cvpPipeD Ds.w 1 cvpSebastPCBR Ds.w 1 cvpHSerr Ds.w 1 cvpHlfLn Ds.w 1 cvpHEq Ds.w 1 cvpHSP Ds.w 1 cvpHBWay Ds.w 1 cvpHAL Ds.w 1 cvpHFP Ds.w 1 cvpHPix Ds.w 1 Endr ; The senselines for Civic-based systems are completely unlike the DAFB- and Sonora-base systems. ; However, by strategic use of the Civic sense-line macros, Civic-based systems are made to ; look like the DAFB- and Sonora-base systems. Neat, huh? ; civicSenseLineA Equ 2 ; Numbers for bit-I/O on Civic senselines. civicSenseLineB Equ 1 ; civicSenseLineC Equ 0 ; civicAMask Equ 3 ; Masks for reading/writing Sonora senselines. civicBMask Equ 5 ; civicCMask Equ 6 ; ; ; Macros to support various “weird” ways hardware must be accessed on Civic. ; Macro ; Trashes D0-D1/A0, nothing returned. pWrite_Civic &theData,&theReg Move.w &theReg,D0 Bsr pGetCivicReg Move.w &theData,D0 Bsr pWriteCivic Endm Macro ; Trashes D0-D1/A0, nothing returned. dWrite_Civic &theData,&theReg Move.w &theReg,D0 Bsr dGetCivicReg Move.w &theData,D0 Bsr dWriteCivic Endm Macro ; Trashes D0-D1/A0, returns theData. pRead_Civic &theReg,&theData Move.w &theReg,D0 Bsr pGetCivicReg Bsr pReadCivic Move.w D0,&theData Endm Macro ; Trashes D0-D1/A0, returns theData. dRead_Civic &theReg,&theData Move.w &theReg,D0 Bsr dGetCivicReg Bsr dReadCivic Move.w D0,&theData Endm Macro CivicResetDelay ; Let pull-up resistors settle. pRead_Civic #CntTest,D0 pRead_Civic #CntTest,D0 pRead_Civic #CntTest,D0 EndMacro Macro CivicResetSenseLines ; Reset the senselines: pWrite_Civic #0,#SenseCtl ; Turn off output-enables, pWrite_Civic #0,#Sense2 ; Reset 'A', pWrite_Civic #0,#Sense1 ; Reset 'B', pWrite_Civic #1,#Sense0 ; Reset 'C', CivicResetDelay ; Wait. Endm Macro CivicReadSenseLines &senseLines ; Read the senselines: CivicResetDelay ; Wait, pRead_Civic #ReadSense,&senseLines ; Read them, CivicResetSenseLines ; Reset them. Endm Macro CivicDriveA ; Drive senseline 'A'. pWrite_Civic #1,#Sense2 pWrite_Civic #0,#Sense1 pWrite_Civic #1,#Sense0 Endm Macro CivicDriveB ; Drive senseline 'B'. pWrite_Civic #0,#Sense2 pWrite_Civic #1,#Sense1 pWrite_Civic #1,#Sense0 Endm Macro CivicDriveC ; Drive senseline 'C'. pWrite_Civic #0,#Sense2 pWrite_Civic #0,#Sense1 pWrite_Civic #0,#Sense0 Endm ; ; Internal equates shared by all built-in video drivers and PrimaryInits. ; ; Flags within GFlags word GrayFlag EQU 15 ; luminance mapped if GFlags(GrayFlag) = 1 IntDisFlag EQU 14 ; interrupts disabled if GFlags(IntFlag) =1 IsMono EQU 13 ; true if monochrome only display (Portrait/Kong) UseSeq EQU 12 ; true if sequence mode SetEntries UseTrans Equ 12 ; True if we’re supposed to translate 5-bit into 8 (DAFB 16bpp). Is16 EQU 11 ; true if 16Mhz (Slow) CPU IsSlow Equ 11 ; True if Slow CPU (for DAFB, 20/25Mhz is slow, 33/40MHz is not). IsSleeping Equ 11 ; True if CPU is sleeping (PowerBook/LCDs). HasAlpha Equ 11 ; True if writing the alpha bits to the CLUT (Civic). IsDirect EQU 10 ; true if direct video mode, else chunkyIndexed PsuedoIndex EQU 9 ; true if SetEntries request was mapped to indexed from sequential ; (due to screen depth hardware requirements) Has16bppSRsrc Equ 9 ; True if FifthVidMode is 16bpp instead of 32bpp (DAFB). SyncOnGreen Equ 8 ; True if we’re supposed to put sync on green (DAFB). InRubik560Mode Equ 8 ; True if we started up in Rubik-560 mode (Sonora). InBlanking Equ 8 ; True if we’re supposed to be blanking the LCD (GSC/CSC). videoInEnb Equ 8 ; True if video-in is enabled (i.e., 32-bit wide graphics/video bus, Civic). CompositeSyncOn Equ 7 ; True if driving out of Composite port (Civic) NTSCTimingOn Equ 6 ; True if driving out NTSC out of Composite port (Civic) ConvolutionOn Equ 5 ; True if driving out with AppleConvolution out of Composite port (Civic) ;--------------------------------------------------- ; ; Rowbytes, page count, and bounds constants ; ;--------------------------------------------------- ; rowbytes constants for the Mac II Hi-Res monitor/VGA monitor and LCD panels ; OBMHRRB EQU 80 ; rowbytes for one-bit mode TBMHRRB EQU 160 ; rowbytes for two-bit mode FBMHRRB EQU 320 ; rowbytes for four-bit mode EBMHRRB EQU 640 ; rowbytes for eight-bit mode D16BMHRRB Equ 1280 ; rowbytes for sixteen-bit mode ; rowbytes constants for the Mono/RGB Full-Page Display ; OBMFPRB EQU 80 ; rowbytes for one-bit mode TBMFPRB EQU 160 ; rowbytes for two-bit mode FBMFPRB EQU 320 ; rowbytes for four-bit mode EBMFPRB Equ 640 ; rowbytes for eight-bit mode ; rowbytes constants for the noninterlaced Apple // GS (Rubik) Monitor ; OBMGSRB EQU 64 ; rowbytes for one-bit mode TBMGSRB EQU 128 ; rowbytes for two-bit mode FBMGSRB EQU 256 ; rowbytes for four-bit mode EBMGSRB EQU 512 ; rowbytes for eight-bit mode D16BMGSRB Equ 1024 ; rowbytes for sixteen-bit mode ; rowbytes constants for the noninterlaced Apple // GS (Rubik) Monitor in 560 mode ; OBMGS560RB EQU 70 ; rowbytes for one-bit mode TBMGS560RB EQU 140 ; rowbytes for two-bit mode FBMGS560RB EQU 280 ; rowbytes for four-bit mode EBMGS560RB EQU 560 ; rowbytes for eight-bit mode D16BMGS560RB Equ 1120 ; rowbytes for sixteen-bit mode ; rowbytes constants for an SE-sized monitor ; OBMSERB EQU 64 ; rowbytes for one-bit mode TBMSERB EQU 128 ; rowbytes for two-bit mode FBMSERB EQU 256 ; rowbytes for four-bit mode EBMSERB EQU 512 ; rowbytes for eight-bit mode ; rowbytes constants for the GoldFish Display ; OBMGFRB Equ 104 ; rowbytes for one-bit mode TBMGFRB Equ 208 ; rowbytes for two-bit mode FBMGFRB Equ 416 ; rowbytes for four-bit mode EBMGFRB Equ 832 ; rowbytes for eight-bit mode ; rowbytes for Tim/DB-Lite LCD display ; OBMLCDRB EQU 80 ; rowbytes for one-bit mode TBMLCDRB Equ 160 ; rowbytes for two-bit mode FBMLCDRB Equ 320 ; rowbytes for four-bit mode EBMLCDRB Equ 640 ; rowbytes for eight-bit mode D16BMLCDRB Equ 1280 ; rowbytes for sixteen-bit mode ; rowbytes for Apollo display ; OBMApolloRB Equ 64 ; rowbytes for one-bit mode ; rowbytes for V8 hardware ; V8_512_RB EQU 512 V8_1024_RB EQU 1024 ; rowbytes for DAFB hardware ; DAFB_512_RB EQU 512 DAFB_576_RB EQU 576 DAFB_832_RB EQU 832 DAFB_1024_RB EQU 1024 DAFB_1152_RB EQU 1152 DAFB_1664_RB Equ 1664 DAFB_2048_RB EQU 2048 DAFB_2304_RB EQU 2304 DAFB_3328_RB EQU 3328 DAFB_4096_RB EQU 4096 ; rowbytes/base addresses for Civic hardware ; Civic_256_RB Equ 256 Civic_512_RB Equ DAFB_512_RB Civic_576_RB Equ DAFB_576_RB Civic_832_RB Equ DAFB_832_RB Civic_1024_RB Equ DAFB_1024_RB Civic_1152_RB Equ DAFB_1152_RB Civic_1280_RB Equ 1280 Civic_1536_RB Equ 1536 Civic_1664_RB Equ DAFB_1664_RB Civic_2048_RB Equ DAFB_2048_RB Civic_2304_RB Equ DAFB_2304_RB Civic_2560_RB Equ 2560 Civic_3328_RB Equ DAFB_3328_RB Civic_256_Base Equ 256 Civic_1280_Base Equ 1280 Civic_1536_Base Equ 1536 Civic_1792_Base Equ 1792 Civic_2048_Base Equ 2048 Civic_2560_Base Equ 2560 Civic_3584_Base Equ 3584 Civic_4096_Base Equ 4096 ; page counts for all (maybe one of these days we’ll support more than one page?) ; OBMPagesHR EQU 1 TBMPagesHR EQU 1 FBMPagesHR EQU 1 EBMPagesHR EQU 1 D16BMPagesHR Equ 1 OBMPagesFP EQU 1 TBMPagesFP EQU 1 FBMPagesFP EQU 1 EBMPagesFP Equ 1 OBMPagesGS EQU 1 TBMPagesGS EQU 1 FBMPagesGS EQU 1 EBMPagesGS EQU 1 D16BMPagesGS EQU 1 OBMPagesGF EQU 1 TBMPagesGF EQU 1 FBMPagesGF EQU 1 EBMPagesGF EQU 1 OBMPagesSE EQU 1 TBMPagesSE EQU 1 FBMPagesSE EQU 1 EBMPagesSE EQU 1 OBMPagesA2Em EQU 1 TBMPagesA2Em EQU 1 FBMPagesA2Em EQU 1 EBMPagesA2Em EQU 1 OBMPagesLCD EQU 1 TBMPagesLCD Equ 1 FBMPagesLCD Equ 1 defPagesLCD Equ 1 OBMPagesApollo Equ 1 ; since they are all 1 page anyway… defPages_DAFB EQU 1 defPages_Sonora Equ 1 defPages_Civic Equ 1 ; ; Bounds constants ; ; for the Mac II Hi-Res Monitor ; defmBounds_THR EQU 0 ; top defmBounds_LHR EQU 0 ; left defmBounds_BHR EQU 480 ; bottom defmBounds_RHR EQU 640 ; right defmBounds_THR400 EQU 0 ; top defmBounds_LHR400 EQU 0 ; left defmBounds_BHR400 EQU 400 ; bottom defmBounds_RHR400 EQU 640 ; right defmBounds_THRMAZ EQU 0 ; top defmBounds_LHRMAZ EQU 0 ; left defmBounds_BHRMAZ EQU 512 ; bottom defmBounds_RHRMAZ EQU 704 ; right ; for the Full Page Display ; defmBounds_TFP EQU 0 ; top defmBounds_LFP EQU 0 ; left defmBounds_BFP EQU 870 ; bottom defmBounds_RFP EQU 640 ; right defmBounds_TFPb EQU 0 ; top defmBounds_LFPb EQU 0 ; left defmBounds_BFPb EQU 818 ; bottom defmBounds_RFPb EQU 640 ; right ; for the noninterlaced Apple // GS Monitor ; defmBounds_TGS EQU 0 ; top defmBounds_LGS EQU 0 ; left defmBounds_BGS EQU 384 ; bottom defmBounds_RGS EQU 512 ; right ; for the Mac SE-Type monitor ; defmBounds_TSE EQU 0 ; top defmBounds_LSE EQU 0 ; left defmBounds_BSE EQU 342 ; bottom defmBounds_RSE EQU 512 ; right ; for the Apple // emulation mode on the Rubik display ; defmBounds_TA2Em EQU 0 ; top defmBounds_LA2Em EQU 0 ; left defmBounds_BA2Em EQU 384 ; bottom defmBounds_RA2Em EQU 560 ; right defmBounds_TGS560 Equ 0 ; top defmBounds_LGS560 Equ 0 ; left defmBounds_BGS560 Equ 384 ; bottom defmBounds_RGS560 Equ 560 ; right ; for VGA-compatible displays ; defmBounds_TVGA EQU 0 ; top defmBounds_LVGA EQU 0 ; left defmBounds_BVGA EQU 480 ; bottom defmBounds_RVGA EQU 640 ; right ; for SuperVGA-compatible displays ; defmBounds_TSVGA Equ 0 ; top defmBounds_LSVGA Equ 0 ; left defmBounds_BSVGA Equ 600 ; bottom defmBounds_RSVGA Equ 800 ; right ; for Landscape Page (Goldfish) displays ; defmBounds_TLP EQU 0 ; top defmBounds_LLP EQU 0 ; left defmBounds_BLP EQU 624 ; bottom defmBounds_RLP EQU 832 ; right defmBounds_TGF EQU 0 ; top defmBounds_LGF EQU 0 ; left defmBounds_BGF EQU 624 ; bottom defmBounds_RGF EQU 832 ; right ; for 19” displays ; defmBounds_T19 Equ 0 ; top defmBounds_L19 Equ 0 ; left defmBounds_B19 Equ 768 ; bottom defmBounds_R19 Equ 1024 ; right ; for 2-Page displays ; defmBounds_T2P EQU 0 ; top defmBounds_L2P EQU 0 ; left defmBounds_B2P EQU 870 ; bottom defmBounds_R2P EQU 1152 ; right ; For NTSC (Full Frame) displays ; defmBounds_TNTSCFF Equ 0 ; top defmBounds_LNTSCFF Equ 0 ; left defmBounds_BNTSCFF Equ 480 ; bottom defmBounds_RNTSCFF Equ 640 ; right ; For NTSC (Safe Title) displays ; defmBounds_TNTSCST Equ 0 ; top defmBounds_LNTSCST Equ 0 ; left defmBounds_BNTSCST Equ 384 ; bottom defmBounds_RNTSCST Equ 512 ; right ; For PAL (Full Frame) displays ; defmBounds_TPALFF Equ 0 ; top defmBounds_LPALFF Equ 0 ; left defmBounds_BPALFF Equ 576 ; bottom defmBounds_RPALFF Equ 768 ; right ; For PAL (Safe Title) displays ; defmBounds_TPALST Equ 0 ; top defmBounds_LPALST Equ 0 ; left defmBounds_BPALST Equ 480 ; bottom defmBounds_RPALST Equ 640 ; right ; for the TIM/DB-Lite LCD display ; defmBounds_TLCD EQU 0 ; top defmBounds_LLCD EQU 0 ; left defmBounds_BLCD EQU 400 ; bottom defmBounds_RLCD EQU 640 ; right ; for the VGA-sized (“Big”) LCD display ; defmBounds_TBigLCD Equ 0 ; top defmBounds_LBigLCD Equ 0 ; left defmBounds_BBigLCD Equ 480 ; bottom defmBounds_RBigLCD Equ 640 ; right defmBounds_THR399 EQU 0 ; top defmBounds_LHR399 EQU 0 ; left defmBounds_BHR399 EQU 399 ; bottom defmBounds_RHR399 EQU 640 ; right ; for the Apollo display ; defmBounds_TApollo Equ 0 ; top defmBounds_LApollo Equ 0 ; left defmBounds_BApollo Equ 342 ; bottom defmBounds_RApollo Equ 512 ; right ; ; screen resolution in dpi (fixed format) ; HResHR EQU $480000 ; 72 HPixels/inch VResHR EQU $480000 ; 72 VPixels/inch HResFP EQU $500000 ; 80 HPixels/inch VResFP EQU $500000 ; 80 VPixels/inch HResGS EQU $480000 ; 72 HPixels/inch VResGS EQU $480000 ; 72 VPixels/inch HResSE EQU $480000 ; 72 HPixels/inch VResSE EQU $480000 ; 72 VPixels/inch HResA2Em EQU $480000 ; 72 HPixels/inch VResA2Em EQU $480000 ; 72 VPixels/inch HRes2P EQU $4D0000 ; 77 HPixels/inch VRes2P EQU $4D0000 ; 77 VPixels/inch HResLP EQU $480000 ; 72 HPixels/inch VResLP EQU $480000 ; 72 VPixels/inch HResGF EQU $480000 ; 72 HPixels/inch VResGF EQU $480000 ; 72 VPixels/inch HRes19 Equ $480000 ; 72 HPixels/inch VRes19 Equ $480000 ; 72 VPixels/inch HResNTSC Equ $480000 ; 72 HPixels/inch VResNTSC Equ $480000 ; 72 VPixels/ince HResPAL Equ $480000 ; 72 HPixels/inch VResPAL Equ $480000 ; 72 HPixels/inch HResLCD EQU $480000 ; 72 HPixels/inch VResLCD EQU $480000 ; 72 VPixels/inch HResApollo Equ $480000 ; 72 HPixels/inch VResApollo Equ $480000 ; 72 VPixels/inch ;--------------------------------------------------- ; ; Miscellaneous constants ; ;--------------------------------------------------- IndexedBlack Equ -1 ; black for indexed modes DirectBlack Equ 0 ; black for direct modes IndexedWhite Equ 0 ; white for indexed modes DirectWhite Equ -1 ; white for direct modes OneBitGray EQU $AAAAAAAA TwoBitGray EQU $CCCCCCCC FourBitGray EQU $F0F0F0F0 EightBitGray EQU $FF00FF00 SixteenBitGray EQU $0000FFFF ThirtyTwoBitGray EQU $00000000 ; need to do this twice (2nd time NOT’d) GrayPatSize Equ 4 defVersion EQU 0 ; Version = 0 defPixelType EQU 0 ; pixeltype=chunky ChunkyDirect EQU 16 ; pixelType=ChunkyDirect defCmpCount EQU 1 ; Number of components in pixel defmPlaneBytes EQU 0 ; Offset from one plane to the next defmDevType EQU clutType ; clutType = 0 defMinorBase EQU 0 ; Video RAM Offset is 0 ; ; Each different video configuration has a different RAM length field. These are the ; length requirements for each RBV configuration, varying from one-bit only to up to eight ; bit modes. The MMU allocation table's rounding factor is 32K, so these values are ; rounded to that size. The size table that this is based on is included in the ; GetRBVSize routine in StartInit.a. The [a,b,c,d] assignment reflects the way that ; the spIDs were assigned ('a' is the normal default, 'b' was the 1MB main RAM default, ; 'c' and 'd' were assigned if those modes were possible). ; MinorLengthHRa EQU (defmBounds_RHR*defmBounds_BHR*8)/8 ; RAM for up to 8-bit mode MinorLengthHRb EQU (defmBounds_RHR*defmBounds_BHR*1)/8 ; RAM for up to 1-bit mode MinorLengthHRc EQU (defmBounds_RHR*defmBounds_BHR*4)/8 ; RAM for up to 4-bit mode MinorLengthHRd EQU (defmBounds_RHR*defmBounds_BHR*2)/8 ; RAM for up to 2-bit mode MinorLengthGSa EQU (defmBounds_RGS*defmBounds_BGS*8)/8 ; RAM for up to 8-bit mode MinorLengthGSb EQU (defmBounds_RGS*defmBounds_BGS*1)/8 ; RAM for up to 1-bit mode MinorLengthGSc EQU (defmBounds_RGS*defmBounds_BGS*4)/8 ; RAM for up to 4-bit mode MinorLengthGSd EQU (defmBounds_RGS*defmBounds_BGS*2)/8 ; RAM for up to 2-bit mode MinorLengthSEa EQU (defmBounds_RSE*defmBounds_BSE*8)/8 ; RAM for up to 8-bit mode MinorLengthSEb EQU (defmBounds_RSE*defmBounds_BSE*1)/8 ; RAM for up to 1-bit mode MinorLengthSEc EQU (defmBounds_RSE*defmBounds_BSE*4)/8 ; RAM for up to 4-bit mode MinorLengthSEd EQU (defmBounds_RSE*defmBounds_BSE*2)/8 ; RAM for up to 2-bit mode MinorLengthFPa EQU (defmBounds_RFP*defmBounds_BFP*4)/8 ; RAM for up to 4-bit mode MinorLengthFPb EQU (defmBounds_RFP*defmBounds_BFP*1)/8 ; RAM for up to 1-bit mode MinorLengthFPc EQU (defmBounds_RFP*defmBounds_BFP*2)/8 ; RAM for up to 2-bit mode ; ; Here are the minor lengths for V8 configurations. Each depth has the same rowbytes for ; a particular vRAM configuration, so there aren't as many permutations as for the RBV. ; As in the declaration structures, 'a' configuration is the 512K flavor, and 'b' is the 256K ; vRAM configuration. ; MinorLength_V8_HRa EQU (1024*defmBounds_BHR) MinorLength_V8_HRb EQU ( 512*defmBounds_BHR) MinorLength_V8_GSa EQU (1024*defmBounds_BGS) MinorLength_V8_GSb EQU ( 512*defmBounds_BGS) MinorLength_V8_VGAa EQU (1024*defmBounds_BVGA) MinorLength_V8_VGAb EQU ( 512*defmBounds_BVGA) MinorLength_V8_A2Ema EQU (1024*defmBounds_BA2Em) ; RAM for any depth on V8 w/512K vRAM MinorLength_V8_A2Emb EQU ( 512*defmBounds_BA2Em) ; RAM for any depth on V8 w/256K vRAM ; ; Here are the minor lengths for the DAFB configurations. These reflect the frame ; buffer size at the greatest screen depth for a given memory configuration. Note ; that rowbytes is constant for a given depth and display (i.e., you may change ; rowbytes on a depth-to-depth change, but 4-bit Hi-Res mode ALWAYS has the same ; rowbytes regardless if you have 0.5M,1.0M, or 2.0M of vRAM). ; MinorLength_DAFB_FPa EQU (DAFB_512_RB*defmBounds_BFP) MinorLength_DAFB_FPb EQU (DAFB_1024_RB*defmBounds_BFP) MinorLength_DAFB_2Pa EQU (DAFB_576_RB*defmBounds_B2P) MinorLength_DAFB_2Pb EQU (DAFB_1152_RB*defmBounds_B2P) MinorLength_DAFB_LPa EQU (DAFB_832_RB*defmBounds_BLP) MinorLength_DAFB_LPax EQU (DAFB_1664_RB*defmBounds_BLP) MinorLength_DAFB_LPb EQU (DAFB_3328_RB*defmBounds_BLP) MinorLength_DAFB_GSa EQU (DAFB_1024_RB*defmBounds_BGS) MinorLength_DAFB_GSb EQU (DAFB_2048_RB*defmBounds_BGS) MinorLength_DAFB_HRa EQU (DAFB_1024_RB*defmBounds_BHR) MinorLength_DAFB_HRax EQU (DAFB_2048_RB*defmBounds_BHR) MinorLength_DAFB_HRb EQU (DAFB_4096_RB*defmBounds_BHR) MinorLength_DAFB_VGAa EQU (DAFB_1024_RB*defmBounds_BVGA) MinorLength_DAFB_VGAax EQU (DAFB_2048_RB*defmBounds_BVGA) MinorLength_DAFB_VGAb EQU (DAFB_4096_RB*defmBounds_BVGA) MinorLength_DAFB_NTSCFFa EQU (DAFB_1024_RB*defmBounds_BNTSCFF) MinorLength_DAFB_NTSCFFax EQU (DAFB_2048_RB*defmBounds_BNTSCFF) MinorLength_DAFB_NTSCFFb EQU (DAFB_4096_RB*defmBounds_BNTSCFF) MinorLength_DAFB_NTSCconvFF EQU (DAFB_1024_RB*defmBounds_BNTSCFF) MinorLength_DAFB_NTSCSTa EQU (DAFB_1024_RB*defmBounds_BNTSCST) MinorLength_DAFB_NTSCSTax EQU (DAFB_2048_RB*defmBounds_BNTSCST) MinorLength_DAFB_NTSCSTb EQU (DAFB_4096_RB*defmBounds_BNTSCST) MinorLength_DAFB_NTSCconvST EQU (DAFB_1024_RB*defmBounds_BNTSCST) MinorLength_DAFB_PALFFa EQU (DAFB_832_RB*defmBounds_BPALFF) MinorLength_DAFB_PALFFax EQU (DAFB_1664_RB*defmBounds_BPALFF) MinorLength_DAFB_PALFFb EQU (DAFB_3328_RB*defmBounds_BPALFF) MinorLength_DAFB_PALconvFF EQU (DAFB_1024_RB*defmBounds_BPALFF) MinorLength_DAFB_PALSTa EQU (DAFB_832_RB*defmBounds_BPALST) MinorLength_DAFB_PALSTax EQU (DAFB_1664_RB*defmBounds_BPALST) MinorLength_DAFB_PALSTb EQU (DAFB_3328_RB*defmBounds_BPALST) MinorLength_DAFB_PALconvST EQU (DAFB_1024_RB*defmBounds_BPALST) MinorLength_DAFB_SVGAa Equ (DAFB_832_RB*defmBounds_BSVGA) MinorLength_DAFB_SVGAax Equ (DAFB_1664_RB*defmBounds_BSVGA) MinorLength_DAFB_SVGAb Equ (DAFB_3328_RB*defmBounds_BSVGA) MinorLength_DAFB_FPbx Equ (DAFB_2048_RB*defmBounds_BFP) MinorLength_DAFB_2Pbx Equ (DAFB_2304_RB*defmBounds_B2P) MinorLength_DAFB_19a Equ (DAFB_512_RB*defmBounds_B19) MinorLength_DAFB_19b Equ (DAFB_1024_RB*defmBounds_B19) MinorLength_DAFB_19bx Equ (DAFB_2048_RB*defmBounds_B19) ; Here is the minor lengths for LCD-based CPUs. ; MinorLengthLCD EQU (defmBounds_RLCD*defmBounds_BLCD*1)/8 ; RAM for 1-bit mode . MinorLengthGSCLCD Equ (defmBounds_RLCD*defmBounds_BLCD*4)/8 ; RAM for 4-bit mode. MinorLengthGSC480 Equ (defmBounds_RBigLCD*defmBounds_BBigLCD*4)/8 ; RAM for 4-bit mode. MinorLength_640x400 Equ (defmBounds_RLCD*defmBounds_BLCD*16)/8 ; RAM for 16-bit mode. MinorLength_640x480 Equ (defmBounds_RBigLCD*defmBounds_BBigLCD*8)/8 ; RAM for 8-bit mode. ; VSC ; MinorLength_VSC_FPa Equ (FBMHRRB*defmBounds_BFP) MinorLength_VSC_FPb Equ (EBMHRRB*defmBounds_BFP) MinorLength_VSC_GS Equ (EBMHRRB*defmBounds_BGS) MinorLength_VSC_HR Equ (EBMHRRB*defmBounds_BHR) ; Here is the minor length for Apollo. ; MinorLengthApollo Equ (defmBounds_RApollo*defmBounds_BApollo*1)/8 ; RAM for 1-bit mode. ; Here are the minor lengths for Sonora CPUs. ; MinorLength_Sonora_FP Equ (OBMFPRB*defmBounds_BFP) ; Also used by RGBFP. MinorLength_Sonora_FPa Equ (TBMFPRB*defmBounds_BFP) MinorLength_Sonora_FPb Equ (FBMFPRB*defmBounds_BFP) MinorLength_Sonora_FPc Equ (EBMFPRB*defmBounds_BFP) MinorLength_Sonora_GS Equ (OBMGSRB*defmBounds_BGS) MinorLength_Sonora_GSa Equ (EBMGSRB*defmBounds_BGS) MinorLength_Sonora_GSb Equ (D16BMGSRB*defmBounds_BGS) MinorLength_Sonora_GS560a Equ (EBMGS560RB*defmBounds_BGS560) MinorLength_Sonora_GS560b Equ (D16BMGS560RB*defmBounds_BGS560) MinorLength_Sonora_HR Equ (OBMHRRB*defmBounds_BHR) ; Also used by VGA. MinorLength_Sonora_HRa Equ (FBMHRRB*defmBounds_BHR) MinorLength_Sonora_HRb Equ (EBMHRRB*defmBounds_BHR) MinorLength_Sonora_HRc Equ (D16BMHRRB*defmBounds_BHR) MinorLength_Sonora_HR400a Equ (EBMHRRB*defmBounds_BHR400) MinorLength_Sonora_HR400b Equ (D16BMHRRB*defmBounds_BHR400) MinorLength_Sonora_GF Equ (OBMGFRB*defmBounds_BGF) MinorLength_Sonora_GFa Equ (TBMGFRB*defmBounds_BGF) MinorLength_Sonora_GFb Equ (EBMGFRB*defmBounds_BGF) ; Here are the minor lengths for Civic CPUs. ; MinorLength_Civic_FPa Equ (Civic_1024_RB*defmBounds_BFP) MinorLength_Civic_FPb Equ (Civic_2048_RB*defmBounds_BFP) MinorLength_Civic_viFPa Equ (Civic_512_RB*defmBounds_BFP) MinorLength_Civic_viFPb Equ (Civic_1024_RB*defmBounds_BFP) MinorLength_Civic_GS Equ (Civic_2048_RB*defmBounds_BGS) MinorLength_Civic_GS560 Equ (Civic_2560_RB*defmBounds_BGS560) MinorLength_Civic_2Pa Equ (Civic_1152_RB*defmBounds_B2P) MinorLength_Civic_vi2Pa Equ (Civic_576_RB*defmBounds_B2P) MinorLength_Civic_2Pb Equ (Civic_2304_RB*defmBounds_B2P) MinorLength_Civic_NTSCFFa Equ (Civic_2048_RB*defmBounds_BNTSCFF) MinorLength_Civic_NTSCFFb Equ (Civic_2560_RB*defmBounds_BNTSCFF) MinorLength_Civic_NTSCST Equ (Civic_2048_RB*defmBounds_BNTSCST) MinorLength_Civic_NTSCFFConv Equ (Civic_1024_RB*defmBounds_BNTSCFF) MinorLength_Civic_NTSCSTConv Equ (Civic_1024_RB*defmBounds_BNTSCST) MinorLength_Civic_HRa Equ (Civic_2048_RB*defmBounds_BHR) MinorLength_Civic_HRb Equ (Civic_2560_RB*defmBounds_BHR) MinorLength_Civic_HR400 Equ (Civic_2560_RB*defmBounds_BHR400) MinorLength_Civic_HRMAZa Equ (Civic_1664_RB*defmBounds_BHRMAZ) MinorLength_Civic_HRMAZb Equ (Civic_3328_RB*defmBounds_BHRMAZ) MinorLength_Civic_viHRa Equ (Civic_1024_RB*defmBounds_BHR) MinorLength_Civic_viHRb Equ (Civic_2048_RB*defmBounds_BHR) MinorLength_Civic_viHR400 Equ (Civic_1280_RB*defmBounds_BHR400) MinorLength_Civic_viHRMAZa Equ (Civic_832_RB*defmBounds_BHRMAZ) MinorLength_Civic_viHRMAZb Equ (Civic_1664_RB*defmBounds_BHRMAZ) MinorLength_Civic_PALFFa Equ (Civic_1664_RB*defmBounds_BPALFF) MinorLength_Civic_PALFFb Equ (Civic_3328_RB*defmBounds_BPALFF) MinorLength_Civic_PALSTa Equ (Civic_1024_RB*defmBounds_BPALST) MinorLength_Civic_PALSTb Equ (Civic_2048_RB*defmBounds_BPALST) MinorLength_Civic_PALFFConv Equ (Civic_1024_RB*defmBounds_BPALFF) MinorLength_Civic_PALSTConv Equ (Civic_1024_RB*defmBounds_BPALST) MinorLength_Civic_viPALFF Equ (Civic_1664_RB*defmBounds_BPALFF) MinorLength_Civic_VGAa Equ (Civic_2048_RB*defmBounds_BVGA) MinorLength_Civic_VGAb Equ (Civic_2560_RB*defmBounds_BVGA) MinorLength_Civic_SVGAa Equ (Civic_1664_RB*defmBounds_BSVGA) MinorLength_Civic_SVGAb Equ (Civic_3328_RB*defmBounds_BSVGA) MinorLength_Civic_GFa Equ (Civic_1664_RB*defmBounds_BGF) MinorLength_Civic_GFb Equ (Civic_3328_RB*defmBounds_BGF) MinorLength_Civic_19a Equ (Civic_1024_RB*defmBounds_B19) MinorLength_Civic_19b Equ (Civic_2048_RB*defmBounds_B19) ; Misc… ; defmBaseOffset EQU 0 ; Offset to base of video RAM Civic_M512_Offset EQU -512 ; Offset to base of video RAM for some Civic modes Civic_1280_Offset EQU 1280 ; Offset to base of video RAM for some Civic modes Civic_1792_Offset EQU 1792 ; Offset to base of video RAM for some Civic modes Civic_2048_Offset EQU 2948 ; Offset to base of video RAM for some Civic modes ; For NTSC, we have two sizes: “Safe Title” (ST) and “Full Frame” (FF), where ST is the ; smaller size. Because QuickDraw doesn’t support a changing base address, we have to ; “lie” to it about where the base address really is. So, we do this with an offset. ; To calculate the offset, we do the following. First, we calculate the horizontal offset. ; We know that there are 1024 “real” pixels and 640 viewable pixels for NTSCFF. So, we ; have (with 512 viewable pixels for NTSCST): ; ; 640 - 512 = 128 (difference between FF and ST). ; 128/2 = 64 (calculate the center). ; ; To calculate the vertical offset, we know there are 480 viewable rows for NTSCFF and ; 384 for NTSCST: ; ; 480 - 384 = 96 (difference between FF and ST). ; 96/2 = 48 (calculate the center). ; ; In order to calculate the base offset, we now just multiply the vertical dimension ; by rowbytes (1024 in 1-8bb, and 4096 in 32bpp), and add in the number of pixels ; we want per depth (for 1-8bb 64/bpp and 64*4 for 32bpp for rowbytes). ; ; Similar logic was used to derive the PAL base address offsets. ; ; NTSC_RB Equ DAFB_1024_RB ; Rowbytes for the indexed modes for NTSC PAL_RB Equ DAFB_832_RB ; and PAL. PAL_RB_Conv Equ DAFB_1024_RB ; NTSC_Mid_RB Equ DAFB_2048_RB ; Rowbytes for the direct modes for NTSC NTSC_Big_RB Equ DAFB_4096_RB ; and PAL. PAL_Mid_RB Equ DAFB_1664_RB ; PAL_Big_RB Equ DAFB_3328_RB ; defmNTSCSTBase Equ (NTSC_RB*48) ; Offset to NTSCST base, 1-8bpp. defmNTSCSTB1 Equ defmNTSCSTBase+(64/8) ; defmNTSCSTBase + 64 pixels (by depth). defmNTSCSTB2 Equ defmNTSCSTBase+(64/4) ; defmNTSCSTB4 Equ defmNTSCSTBase+(64/2) ; defmNTSCSTB8 Equ defmNTSCSTBase+(64/1) ; defmNTSCSTB16 Equ (NTSC_Mid_RB*48)+(64*2) ; 16bpp defmNTSCSTBase + 64 pixels. defmNTSCSTB32 Equ (NTSC_Big_RB*48)+(64*4) ; 32bpp defmNTSCSTBase + 64 pixels. defmPALSTBase Equ (PAL_RB*48) ; Offset to PALST base, 1-8bb. defmPALSTB1 Equ defmPALSTBase+(64/8) ; defmPALSTBase + 64 pixels (by depth). defmPALSTB2 Equ defmPALSTBase+(64/4) ; defmPALSTB4 Equ defmPALSTBase+(64/2) ; defmPALSTB8 Equ defmPALSTBase+(64/1) ; defmPALSTB16 Equ (PAL_Mid_RB*48)+(64*2) ; 16bpp defmPALSTBase + 64 pixels. defmPALSTB32 Equ (PAL_Big_RB*48)+(64*4) ; 32bpp defmPALSTBase + 64 pixels. defmPALSTBConv Equ (PAL_RB_Conv*48) ; Offset to PALST base convolved, 1-8bb. defmPALSTB1Conv Equ defmPALSTBConv+(64/8) ; defmPALSTBConv + 64 pixels (by depth). defmPALSTB2Conv Equ defmPALSTBConv+(64/4) ; defmPALSTB4Conv Equ defmPALSTBConv+(64/2) ; defmPALSTB8Conv Equ defmPALSTBConv+(64/1) ; bSlot0rbv EQU 6 ; bit # of slot zero interrupt enable ; in RBV slot interrupt enable register bEnable EQU 7 ; bit # that writes ones when ; talking to interrupts register ; ; These are the monitor ID's as seen by the RBV sense register ; FPIdMono EQU 1 ; full page monitor, monochrome GSId EQU 2 ; 512*384 FPIdColor EQU 5 ; full page monitor, color HRId EQU 6 ; 640*480 SEId EQU 7 ; 512*342 ; ; Because we ran out of contiguous functional sRsrc IDs in the Zydeco time-frame, ; we came up with a method of having sRsrc directory directories, or super ; sRsrc directories. The method of choosing which super sRsrc directory ; is applicable is the responsibility of a new piece of code called a ; SuperInit. For CPUs done in the Zydeco (or Zydeco-near) time frame, ; the sRsrcBFBasedDir is used. For unknown CPUs, a minimal sRsrc directory ; is selected. All other CPUs can have their own sRsrc directories. ; sRsrcUnknownDir Equ 1 ; sRsrc Directory for unknown CPUs. sRsrcUnknownBd Equ 1 ; Unknown board sRsrc. sRsrcBFBasedDir Equ $7F ; CPUs supported in the BoxFlag-based sRsrc directory. sRsrcSonoraDir Equ $7E ; CPUs supported in the Sonora sRsrc directory. sRsrcCivicDir Equ $7D ; CPUs supported in the Civic sRsrc directory. sRsrcCSCDir Equ $7C ; CPUs supported in the CSC sRsrc directory. sRsrcATIDir Equ $7B ; CPUs supported in the ATI sRsrc directory. ;--------------------------------------------------------------------- ; General and sRsrc IDs in the sRsrcZydecoDir Directory ;--------------------------------------------------------------------- ; ; These are the local definitions for the sRsrcIDs in the slot zero (RBV) video config ; ROM. The naming convention is pretty simple: ; ; sRsrcID = sRsrc_VidXxxYYz, where ; ; Xxx = built-in video CPU name, Rbv for Mac IIci and Erickson ; Els for Elsie ; Ecl for Eclipse ; Por for Waimea ; YY = display type, HR for High-Resolution Display (640*480) ; FP for Portrait Display (640*870) ; GS for Rubik Display (512*384) ; SE for SE-link 9" monitor (512*342) ; z = memory allocation configuration - each sRsrc list supports ; a different set of screen depths. This part of the name ; just makes each configuration unique. There's no 16 vs. 25 ; MHz identifier now, since all screen depth combinations are ; enumerated. ; ; PrimaryInit handles these configurations differently depending on the amount of ; RAM available in the CPU. By default, if more than 1MB of RAM is available in ; the system, then the full capacity sRsrc for this monitor is selected. If only ; 1MB is available, then the 1-bit only sRsrc is selected. This default can be over- ; ridden by the user in Monitors. ; ; Here's how the sRsrc IDs are assigned: ; ; Bit 7 = always set for video sRsrc IDs (by convention) ; Bit 6 = with bit 5, identifies the type of CPU. 00=ci/Erickson ; Bit 5 = 01=Elsie ; Bit 4 = option bit 2, set for 16Mhz default configurations ; Bit 3 = option bit 1, set for 1MB default configurations ; Bit 2 = RBV monitor ID bit ; Bit 1 = RBV monitor ID bit ; Bit 0 = RBV monitor ID bit ; ; The low-order bits are shifted over from what's read in the RBV monitor ID register. ; They are shifted down to make it easier to make decisions about screen size, etc ; later. The high bit is always set to distinguish function sRsrc lists from ; system-defined lists. The two option bits describe alternate sRsrc lists which ; differ in the different available screen depths. There are up to four combinations ; of the bits - 1-bit only, 1- and 2-bit only, 1-,2-, and 4-bit, and (for some ; monitors) 1-,2-,4-, and 8-bit modes. The actual combinations are arbitrary, but ; are contrived so that the defaults for different CPU configurations (clock speed ; and memory) can be generated by setting a single bit. The other combinations are ; valid, but must be selected via the video family selector in Monitors. For ; example, a 5MB Aurora 25 w/HR monitor sets is spID $86. This same combo with ; 1MB of RAM is $8E, and so on. ; ; The IDs for the multiple board sRsrcs are based directly on the boxFlag identifier. ; These sRsrcs are tagged as inactive at startup. Only the Aurora25 board resource ; is active at start, so it determines the system configuration and installs the ; appropriate board sRsrc list. ; ; ; The PrimaryInit code DEPENDS on never allowing $80 to be a valid video sRsrc spID. ; ; ; The sRsrcID for each board resource is equal to it's boxflag+shift value. The shift is required ; since the Mac II box flag is 0, but 0 is an illegal spID value to the Slot Manager ; BoardspIDShift EQU 1 ; board spID shift value sRsrc_BdMacII EQU boxMacII+BoardspIDShift ; (0+BoardspIDShift) sRsrc_BdMacIIx EQU boxMacIIx+BoardspIDShift ; (1+BoardspIDShift) sRsrc_BdMacIIcx EQU boxMacIIcx+BoardspIDShift ; (2+BoardspIDShift) sRsrc_BdMacSE30 EQU boxSE30+BoardspIDShift ; (3+BoardspIDShift) sRsrc_BdMacIIci EQU boxMacIIci+BoardspIDShift ; (5+BoardspIDShift) sRsrc_BdMacIIfx EQU boxMacIIfx+BoardspIDShift ; (7+BoardspIDShift) sRsrc_BdErickson EQU boxMacIIsi+BoardspIDShift ; (12+BoardspIDShift) sRsrc_BdElsie EQU boxMacLC+BoardspIDShift ; (13+BoardspIDShift) sRsrc_BdEclipse EQU boxQuadra900+BoardspIDShift ; (14+BoardspIDShift) sRsrc_BdTIM EQU boxPowerBook170+BoardspIDShift ; (15+BoardspIDShift) sRsrc_BdSpike EQU boxQuadra700+BoardspIDShift ; (16+BoardspIDShift) sRsrc_BdApollo Equ boxClassicII+BoardspIDShift ; (17+BoardspIDShift) sRsrc_BdTIMLC Equ boxPowerBook140+BoardspIDShift ; (19+BoardspIDshift) sRsrc_BdZydeco Equ boxQuadra950+BoardspIDShift ; (20+BoardspIDShift) sRsrc_BdDBLite25 Equ boxPowerBookDuo210+BoardspIDShift; (23+BoardspIDShift) sRsrc_BdWombat25 Equ boxCentris650+BoardspIDShift ; (24+BoardspIDShift) sRsrc_BdDBLite33 Equ boxPowerBookDuo230+BoardspIDShift; (26+BoardspIDshift) sRsrc_BdDartanian Equ boxPowerBook180+BoardspIDShift ; (27+BoardsplDshift) sRsrc_BdDartanianLC Equ boxPowerBook160+BoardspIDShift ; (28+BoardspIDShift) sRsrc_BdWombat33F Equ boxQuadra800+BoardspIDShift ; (29+BoardspIDShift) sRsrc_BdWombat33 Equ boxQuadra650+BoardspIDShift ; (30+BoardspIDShift) sRsrc_BdLCII Equ boxMacLCII+BoardspIDShift ; (31+BoardspIDshift) sRsrc_BdDBLite16 Equ boxPowerBookDuo250+BoardspIDShift ; (32+BoardspIDshift) sRsrc_BdDBLite20 Equ boxDBLite20+BoardspIDShift ; (33+BoardspIDshift) sRsrc_BdWombat40 Equ boxWombat40+BoardspIDShift ; (45+BoardspIDShift) sRsrc_BdWLCD20 Equ boxCentris610+BoardspIDShift ; (46+BoardspIDShift) sRsrc_BdWLCD25 Equ boxQuadra610+BoardspIDShift ; (47+BoardspIDShift) sRsrc_BdWombat20 Equ boxWombat20+BoardspIDShift ; (52+BoardspIDshift) sRsrc_BdWombat40F Equ boxWombat40F+BoardspIDShift ; (53+BoardspIDshift) sRsrc_BdRiscQuadra700 Equ boxRiscQuadra700+BoardspIDShift ; (55+BoardspIDShift) sRsrc_BdWLCD33 Equ boxWLCD33+BoardspIDShift ; (57+BoardspIDshift) sRsrc_BdRiscCentris650 Equ boxRiscCentris650+BoardspIDShift; (76+BoardspIDshift) sRsrc_BdRiscQuadra900 Equ boxRiscQuadra900+BoardspIDShift ; (98+BoardspIDShift) sRsrc_BdRiscQuadra950 Equ boxRiscQuadra950+BoardspIDShift ; (99+BoardspIDShift) sRsrc_BdRiscCentris610 Equ boxRiscCentris610+BoardspIDShift; (100+BoardspIDshift) sRsrc_BdRiscQuadra800 Equ boxRiscQuadra800+BoardspIDShift ; (101+BoardspIDshift) sRsrc_BdRiscQuadra610 Equ boxRiscQuadra610+BoardspIDShift ; (102+BoardspIDshift) sRsrc_BdRiscQuadra650 Equ boxRiscQuadra650+BoardspIDShift ; (103+BoardspIDshift) sRsrc_BdSTPQ700 Equ boxSTPQ700+BoardspIDShift ; (110+BoardspIDshift) sRsrc_BdSTPQ900 Equ boxSTPQ900+BoardspIDShift ; (111+BoardspIDshift) sRsrc_BdSTPQ950 Equ boxSTPQ950+BoardspIDShift ; (112+BoardspIDshift) sRsrc_BdSTPC610 Equ boxSTPC610+BoardspIDShift ; (113+BoardspIDshift) sRsrc_BdSTPC650 Equ boxSTPC650+BoardspIDShift ; (114+BoardspIDshift) sRsrc_BdSTPQ610 Equ boxSTPQ610+BoardspIDShift ; (115+BoardspIDshift) sRsrc_BdSTPQ650 Equ boxSTPQ650+BoardspIDShift ; (116+BoardspIDshift) sRsrc_BdSTPQ800 Equ boxSTPQ800+BoardspIDShift ; (117+BoardspIDshift) ; -------- RBV System sRsrc IDs -------- sRsrc_VidRbvHRa EQU $86 ; Mac II High-Res Display (1,2,4,8) sRsrc_VidRbvHRb EQU $96 ; Mac II High-Res Display (1,2,4) sRsrc_VidRbvHRc EQU $9E ; Mac II High-Res Display (1,2) sRsrc_VidRbvHRd EQU $8E ; Mac II High-Res Display (1 only) sRsrc_VidRbvFPa EQU $81 ; Page Display (1,2,4) sRsrc_VidRbvFPb EQU $91 ; Page Display (1,2) sRsrc_VidRbvFPc EQU $89 ; Page Display (1 only) sRsrc_VidRbvGSa EQU $82 ; nonInterlaced GS Display (1,2,4,8) sRsrc_VidRbvGSb EQU $92 ; nonInterlaced GS Display (1,2,4) sRsrc_VidRbvGSc EQU $9A ; nonInterlaced GS Display (1,2) sRsrc_VidRbvGSd EQU $8A ; nonInterlaced GS Display (1 only) sRsrc_VidRbvSEa EQU $87 ; Mac SE display (1,2,4,8) sRsrc_VidRbvSEb EQU $97 ; Mac SE display (1,2,4) sRsrc_VidRbvSEc EQU $9F ; Mac SE display (1,2) sRsrc_VidRbvSEd EQU $8F ; Mac SE display (1 only) ; -------- Elsie V8 sRsrc IDs -------- ; in this set of IDs, the bits are assigned by feature: ; ; Bit 7 = always on for functional sRsrcIDs ; Bit 6-5 = 01 for Elsie/V8 ; Bit 4 = 0 if vRAM video, 1 if no vRAM with Jersey, 1 if A2 mode with Rubik ; Bit 3 = 0 if 512K vRAM, 1 if 256K vRAM ; Bit 2-0 = monitor ID bits (010 = Rubik, 110 = Hi-Res RGB, 011 = VGA). These ; sense combinations are similar to the RBV, but the V8 doesn't support ; the portrait display. The VGA has an extended sense combination that ; looks like the portrait code if the lines aren't driven. So we effectively ; share that code. ; sRsrc_NeverMatch EQU $A0 ; This sRsrc is NEVER implemented! It's ; used to allow sRsrc pruning to work ; with no connected display. ; It is used by all slot zero configurations. sRsrc_Vid_V8_GSa EQU $A2 ; 512K VRAM V8 + Rubik (1,2,4,8,16) sRsrc_Vid_V8_GSb EQU $AA ; 256K VRAM V8 + Rubik (1,2,4,8) sRsrc_Vid_V8_A2Ema EQU $B2 ; 512K VRAM V8 + A// (1,2,4,8) sRsrc_Vid_V8_A2Emb EQU $BA ; 256K VRAM V8 + A// (1,2,4) sRsrc_Vid_V8_HRa EQU $A6 ; 512K VRAM V8 + Hi-Res (1,2,4,8) sRsrc_Vid_V8_HRb EQU $AE ; 256K VRAM V8 + Hi-Res (1,2,4) sRsrc_Vid_V8_VGAa EQU $A3 ; 512K VRAM V8 + VGA (1,2,4,8) sRsrc_Vid_V8_VGAb EQU $AB ; 256K VRAM V8 + VGA (1,2,4) ; -------- DB-Lite LCD sRsrc IDs ------ ; sRsrc_Vid_GSC_LCD Equ $BB ; GSC (640x400) built-in LCD display. ; -------- DAFB sRsrc IDs -------- sRsrc_Vid_DAFB_19a Equ $BE ; 19” 1,2,4 (Ugh: There’s no where sRsrc_Vid_DAFB_19b Equ $BF ; 19” 1,2,4,8 else to put these!) ; -------- DAFB sRsrc IDs -------- ; In this group of spIDs, the assignment is much more arbitrary than the others ; where properties are associated with bits. Generally, there are two sets of ; modes - a full capability with more memory and a reduced capability with less RAM. ; The mapping of these two flavors on top of the three vRAM sizes is dependent on the ; type of display and isn't obvious. ; ; Progressive scan ID's - $C0-$CF, where even IDs are the lower functionality ; and full function = lower function+1 ; Interlaced scan ID's - $D0-$DF, with the same relationship between evens ; and odds as the progressive scan displays. ; Also, convolved modes (which only work with ; 2MB RAM) are the higher functionality ; ID+8 (even if the higher func. mode is a ; 1MB mode) ; ; Zydeco update: Because the Zydeco (Eclipse 33) has the AC842A (16bpp-capable ACDC), we ; needed a few more sResources. Note that the even sRsrcs are still the lesser capable ; sRsrc IDs. sRsrc_Vid_DAFB_FPa EQU $C0 ; Full-Page 1,2,4 sRsrc_Vid_DAFB_FPb EQU $C1 ; Full-Page 1,2,4,8 sRsrc_Vid_DAFB_GSa EQU $C2 ; Rubik 1,2,4,8 sRsrc_Vid_DAFB_GSb EQU $C3 ; Rubik 1,2,4,8,32 sRsrc_Vid_DAFB_2Pa EQU $C4 ; Two-Page 1,2,4 sRsrc_Vid_DAFB_2Pb EQU $C5 ; Two-Page 1,2,4,8 sRsrc_Vid_DAFB_LPa EQU $C6 ; GoldFish 1,2,4,8 sRsrc_Vid_DAFB_LPb EQU $C7 ; GoldFish 1,2,4,8,32 sRsrc_Vid_DAFB_HRa EQU $C8 ; HiRes 1,2,4,8 sRsrc_Vid_DAFB_HRb EQU $C9 ; HiRes 1,2,4,8,32 sRsrc_Vid_DAFB_VGAa EQU $CA ; VGA 1,2,4,8 sRsrc_Vid_DAFB_VGAb EQU $CB ; VGA 1,2,4,8,32 sRsrc_Vid_DAFB_RGBFPa EQU $CC ; RGBPort 1,2,4 sRsrc_Vid_DAFB_RGBFPb EQU $CD ; RGBPort 1,2,4,8 sRsrc_Vid_DAFB_RGB2Pa EQU $CE ; Vesuvio 1,2,4 sRsrc_Vid_DAFB_RGB2Pb EQU $CF ; Vesuvio 1,2,4,8 sRsrc_Vid_DAFB_NTSCSTa EQU $D0 ; NTSC ST 1,2,4,8 sRsrc_Vid_DAFB_NTSCSTb EQU $D1 ; NTSC ST 1,2,4,8,32 sRsrc_Vid_DAFB_NTSCFFa EQU $D2 ; NTSC FF 1,2,4,8 sRsrc_Vid_DAFB_NTSCFFb EQU $D3 ; NTSC FF 1,2,4,8,32 sRsrc_Vid_DAFB_PALSTa EQU $D4 ; PAL ST 1,2,4,8 sRsrc_Vid_DAFB_PALSTb EQU $D5 ; PAL ST 1,2,4,8,32 sRsrc_Vid_DAFB_PALFFa EQU $D6 ; PAL FF 1,2,4,8 sRsrc_Vid_DAFB_PALFFb EQU $D7 ; PAL FF 1,2,4,8,32 sRsrc_Vid_DAFB_NTSCconvSTx EQU $D8 ; NTSC ST conv 1,2,4,8 (dif ID only for 16bpp) sRsrc_Vid_DAFB_NTSCconvST EQU $D9 ; NTSC ST conv 1,2,4,8 sRsrc_Vid_DAFB_NTSCconvFFx EQU $DA ; NTSC FF conv 1,2,4,8 (dif ID only for 16bpp) sRsrc_Vid_DAFB_NTSCconvFF EQU $DB ; NTSC FF conv 1,2,4,8 sRsrc_Vid_DAFB_PALconvSTx EQU $DC ; PAL ST conv 1,2,4,8 (dif ID only for 16bpp) sRsrc_Vid_DAFB_PALconvST EQU $DD ; PAL ST conv 1,2,4,8 sRsrc_Vid_DAFB_PALconvFFx EQU $DE ; PAL FF conv 1,2,4,8 (dif ID only for 16bpp) sRsrc_Vid_DAFB_PALconvFF EQU $DF ; PAL FF conv 1,2,4,8 ; -------- TIM LCD sRsrc IDs ---------- ; sRsrc_Vid_Tim_LCD EQU $E0 ; TIM built-in LCD display ; -------- Apollo sRsrc IDs ----------- ; sRsrc_Vid_Apollo Equ $E1 ; Apollo built-in video ; ------- Extra DAFB sRsrc IDs ------- ; MinDAFB16bppSRsrc Equ $E2 ; DAFB 16bpp-capable sRsrc boundry. sRsrc_Vid_DAFB_HRax Equ $E2 ; HiRes 1,2,4,8,16 sRsrc_Vid_DAFB_HRbx Equ $E3 ; HiRes 1,2,4,8,16,32 sRsrc_Vid_DAFB_VGAax Equ $E4 ; VGA 1,2,4,8,16 sRsrc_Vid_DAFB_VGAbx Equ $E5 ; VGA 1,2,4,8,16,32 sRsrc_Vid_DAFB_LPax Equ $E6 ; GoldFish 1,2,4,8,16 sRsrc_Vid_DAFB_LPbx Equ $E7 ; GoldFish 1,2,4,8,16,32 sRsrc_Vid_DAFB_SVGAax Equ $E8 ; SuperVGA 1,2,4,8,16 sRsrc_Vid_DAFB_SVGAbx Equ $E9 ; SuperVGA 1,2,4,8,16,32 sRsrc_Vid_DAFB_SVGAa Equ $EA ; SuperVGA 1,2,4,8 sRsrc_Vid_DAFB_SVGAb Equ $EB ; SuperVGA 1,2,4,8,32 sRsrc_Vid_DAFB_GSx Equ $EC ; Rubik 1,2,4,8,16,32 sRsrc_Vid_DAFB_GSz Equ $EE ; Rubik 1,2,4,8,16 (note that it’s out of order here) sRsrc_Vid_DAFB_RGBFPbx Equ $ED ; RGBPort 1,2,4,8,16 sRsrc_Vid_DAFB_RGB2Pbx Equ $EF ; Vesuvio 1,2,4,8,16 sRsrc_Vid_DAFB_NTSCSTax Equ $F0 ; NTSC ST 1,2,4,8,16 sRsrc_Vid_DAFB_NTSCSTbx Equ $F1 ; NTSC ST 1,2,4,8,16,32 sRsrc_Vid_DAFB_NTSCFFax Equ $F2 ; NTSC FF 1,2,4,8,16 sRsrc_Vid_DAFB_NTSCFFbx Equ $F3 ; NTSC FF 1,2,4,8,16,32 sRsrc_Vid_DAFB_PALSTax Equ $F4 ; PAL ST 1,2,4,8,16 sRsrc_Vid_DAFB_PALSTbx Equ $F5 ; PAL ST 1,2,4,8,16,32 sRsrc_Vid_DAFB_PALFFax Equ $F6 ; PAL FF 1,2,4,8,16 sRsrc_Vid_DAFB_PALFFbx Equ $F7 ; PAL FF 1,2,4,8,16 sRsrc_Vid_DAFB_Reserved Equ $F8 ; Reserved for future use. sRsrc_Vid_DAFB_19bx Equ $F9 ; 19” 1,2,4,8,16 pSRsrc_Vid_DAFB_2PRdRGB Equ $FD ; Psuedo-sRsrcID for Radius ColorTPD (1,2,4,8[,16]). pSRsrc_Vid_DAFB_2PRdMono Equ $FE ; Psuedo-sRsrcID for Radius MonoTPD (1,2,4,8). ; ; The following sRsrcs are non-video sRsrcs. As much as it makes sense, we should attempt to use ; the same sRsrc IDs in directories other than the Zydeco sRsrc directory. ; ; -------- CPU Resource IDs ----------- ; sRsrc_CPUMacIIci EQU $FA ; Used for ’030 (and Mac LC) CPU sRsrcs. sRsrc_CPUMac030 Equ $FA ; Just an alias for the “IIci” CPU sRsrc. sRsrc_CPUMac040 Equ $FB ; CPU sRsrc for ’040 machines. sRsrc_Reserved1 Equ $FC ; Reserved for future use. ; -------- Onboard Ethernet ID -------- ; sRsrc_Sonic EQU $FD ; Sonic onboard Ethernet chip. sRsrc_Ethernet Equ $FD ; Just an alias for future non-Sonic Ethernet chips. sRsrc_Reserved2 Equ $FE ; Reserved for future use except in the Zydeco sRsrc dir. ; -------- SCSI Transport ID -------- ; sRsrc_SCSI_Transport Equ $FA ; SCSI Transport sRsrc for 4.3SCSI Mgr ; ; Double Exposure related stuff. This card should have a config ROM on it, but doesn't so ; we have a double exposure functional sRsrc that could potentially be plumbed in. This ; spID is set to be higher than all video functional sRsrcs. ; sRsrc_DoubleExposure EQU $FE ; special functional resource for Double ; Exposure functional sRsrc CPU_FlagsID EQU $80 hasPixelClock EQU 0 ; bit indicating that card provides a pixel clock hasIWM EQU 1 ; card has an IWM hasJoystick EQU 2 ; card has a joystick port hasDERegs EQU 15 ; card uses the initial DE register set CPU_Flags EQU 0|\ ; has pixel clock, IWM, joystick, and DE register set (1< sRsrc_BdPDM Equ boxPDM80F ; Board sResrouce ID for PDM. ; -------- Vail/PDM sRsrc IDs ---------- ; sRsrc_Vid_Sonora_FP Equ $80 ; Full-Page 1 (PDM) sRsrc_Vid_Sonora_FPa Equ $81 ; Full-Page 1,2 sRsrc_Vid_Sonora_FPb Equ $82 ; Full-Page 1,2,4 sRsrc_Vid_Sonora_FPc Equ $83 ; Full-Page 1,2,4,8 sRsrc_Vid_Sonora_GS Equ $84 ; Rubik 1 (PDM) sRsrc_Vid_Sonora_GSa Equ $85 ; Rubik 1,2,4,8 sRsrc_Vid_Sonora_GSb Equ $86 ; Rubik 1,2,4,8,16 sRsrc_Vid_Sonora_GSM Equ $87 ; GSM=GSb sRsrc_Vid_Sonora_GS560a Equ $88 ; Rubik-560 1,2,4,8 (Vail) sRsrc_Vid_Sonora_GS560b Equ $89 ; Rubik-560 1,2,4,8,16 (Vail) sRsrc_Vid_Sonora_RGBFP Equ $8A ; RGB Full-Page 1 (PDM) sRsrc_Vid_Sonora_RGBFPa Equ $8B ; RGB Full-Page 1,2 sRsrc_Vid_Sonora_RGBFPb Equ $8C ; RGB Full-Page 1,2,4 sRsrc_Vid_Sonora_RGBFPc Equ $8D ; RGB Full-Page 1,2,4,8 sRsrc_Vid_Sonora_HR Equ $8E ; HiRes 1 (PDM) sRsrc_Vid_Sonora_HRa Equ $8F ; HiRes 1,2,4 sRsrc_Vid_Sonora_HRb Equ $90 ; HiRes 1,2,4,8 sRsrc_Vid_Sonora_HRc Equ $91 ; HiRes 1,2,4,8,16 sRsrc_Vid_Sonora_MSB1 Equ $92 ; MSB1 -> HRc sRsrc_Vid_Sonora_HR400a Equ $93 ; HiRes-400 1,2,4,8 (Vail) sRsrc_Vid_Sonora_HR400b Equ $94 ; HiRes-400 1,2,4,8,16 (Vail) sRsrc_Vid_Sonora_VGA Equ $95 ; VGA 1 (PDM) sRsrc_Vid_Sonora_VGAa Equ $96 ; VGA 1,2,4 sRsrc_Vid_Sonora_VGAb Equ $97 ; VGA 1,2,4,8 sRsrc_Vid_Sonora_VGAc Equ $98 ; VGA 1,2,4,8,16 sRsrc_Vid_Sonora_GF Equ $99 ; GoldFish 1 (PDM) sRsrc_Vid_Sonora_GFa Equ $9A ; GoldFish 1,2 sRsrc_Vid_Sonora_GFb Equ $9B ; GoldFish 1,2,4,8 sRsrc_Vid_Sonora_MSB2 Equ $9C ; MSB2 -> MSB3 -> GFb sRsrc_Sonora_Mace Equ $EF ; Mace Ethernet on Sonora sRsrc_Sonora_NeverMatch Equ $FE ; The “null” Sonora sRsrc. ;--------------------------------------------------------------------- ; sRsrc IDs in the sRsrcCSCDir Directory ;--------------------------------------------------------------------- ; Define the board sRsrc strategy for the sRsrcCSCDir. ; sRsrc_BdEscher Equ $01 ; Board sResource ID for Eschers. sRsrc_BdBlackBird Equ $02 ; Board sResource ID for BlackBirds. sRsrc_BdYeager Equ $03 ; Board sResource ID for Yeagers. ; -------- CSC sRsrc IDs ---------- ; sRsrc_Vid_CSC_640x400a Equ $80 ; 1,2,4,8,16 [Color, TFT, Single-Drive, 640x480, Sharp] sRsrc_Vid_CSC_640x400b Equ $81 ; 1,2,4,8 sRsrc_Vid_CSC_640x480a Equ $82 ; 1,2,4,8,16 [Color, TFT, Single-Drive, 640x480, Sharp] sRsrc_Vid_CSC_C_S_TFT_399 Equ $80 ; 1,2,4,8,16 [Color, TFT, Single-Drive, 640x480, Sharp] sRsrc_Vid_CSC_C_S_TFT_480 Equ $81 ; 1,2,4,8 sRsrc_Vid_CSC_C_S_TFT_399a Equ $82 ; 1,2,4,8,16 [Color, TFT, Single-Drive, 640x480, Sharp] sRsrc_Vid_CSC_C_S_TFT_480a Equ $83 ; 1,2,4,8 sRsrc_Vid_CSC_C_D_STN_480 Equ $85 ; 1,2,4,8 [Color, STN, Dual-Drive, 640x480, Sharp] sRsrc_Vid_CSC_C_S_TFT_399b Equ $86 ; 1,2,4,8,16 [Color, TFT, Single-Drive, 640x480, NEC] sRsrc_Vid_CSC_C_S_TFT_480b Equ $87 ; 1,2,4,8 sRsrc_Vid_CSC_C_S_TFT_399c Equ $88 ; 1,2,4,8,16 [Color, TFT, Single-Drive, 640x480, Hosiden] sRsrc_Vid_CSC_C_S_TFT_480c Equ $89 ; 1,2,4,8 sRsrc_Vid_CSC_C_S_TFT_399d Equ $8A ; 1,2,4,8,16 [Color, TFT, Single-Drive, 640x480, Toshiba] sRsrc_Vid_CSC_C_S_TFT_480d Equ $8B ; 1,2,4,8 sRsrc_Vid_CSC_G_D_STN_400 Equ $8D ; 1,2,4 [Gray, STN, Dual-Drive, 640x400, Sharp-Escher] sRsrc_Vid_CSC_G_S_TFT_400 Equ $8F ; 1,2,4 [Gray, TFT, Single-Drive, 640x400, Hosiden-Escher] sRsrc_Vid_CSC_G_D_STN_480 Equ $90 ; 1,2,4 [Gray, STN, Dual-Drive, 640x480, Sharp] sRsrc_Vid_CSC_G_S_TFT_480 Equ $91 ; 1,2,4 [Gray, TFT, Single-Drive, 640x400, Hosiden] sRsrc_Vid_CSC_C_S_TFT_399y Equ $92 ; 1,2,4,8,16 [Color, TFT, Single-Drive, 640x480, Sharp-Yeager] sRsrc_Vid_CSC_C_S_TFT_480y Equ $93 ; 1,2,4,8 sRsrc_Vid_CSC_G_D_STN_400y Equ $94 ; 1,2,4 [Gray, STN, Dual-Drive, 640x400, Sharp-Yeager] sRsrc_Vid_CSC_G_S_TFT_400y Equ $95 ; 1,2,4 [Gray, TFT, Single-Drive, 640x400, Hosiden-Yeager] sRsrc_CSC_NeverMatch Equ $FE ; The “null” CSC sRsrc. ; -------- VSC sRsrc IDs ---------- ; sRsrc_Vid_VSC_FPb Equ $80 sRsrc_Vid_VSC_FPa Equ $81 sRsrc_Vid_VSC_GS Equ $82 sRsrc_Vid_VSC_RGBFPb Equ $80 sRsrc_Vid_VSC_RGBFPa Equ $81 sRsrc_Vid_VSC_HR Equ $82 ;--------------------------------------------------------------------- ; sRsrc IDs in the sRsrcCivicDir Directory ;--------------------------------------------------------------------- ; Define the board sRsrc strategy for the sRsrcCivicDir. We just use the boxFlag for ; covenience. Unlike the Zydeco directory, we don’t need to add 1 because none ; of the Cyclone-based CPUs can have a boxFlag of zero. ; sRsrc_BdCyclone Equ boxQuadra840AV ; Board sRsrc ID for the Cyclone family of CPUs. sRsrc_BdTempest Equ boxCentris660AV ; Board sRsrc ID for the Tempest family of CPUs. ; -------- Cyclone sRsrc IDs ---------- ; ; The functional sRsrcs in Cyclone are distributed as follows: ; ; $80 - $EF are the video sRsrcs IDs ; ; $F0 - $FD are for misc. sRsrc IDs (e.g, Mace, DSP, etc…). ; ; $FE is reserved as the “null” sRsrc ID. sRsrc_Vid_Civic_NTSCFFConva Equ $80 ; NTSC FF Conv 1,2,4,8 sRsrc_Vid_Civic_NTSCSTConv Equ $81 ; NTSC ST Conv 1,2,4,8 sRsrc_Vid_Civic_PALFFConva Equ $84 ; PAL FF Conv 1,2,4,8 sRsrc_Vid_Civic_PALSTConva Equ $85 ; PAL ST Conv 1,2,4,8 ; ------ Video-in ID's sRsrc_Vid_Civic_vi2PRGBa Equ $88 ; Vesuvio 1,2,4 sRsrc_Vid_Civic_vi2PRGBb Equ $89 ; Vesuvio 1,2,4,8 sRsrc_Vid_Civic_vi2PRGB512 Equ $8A ; Vesuvio (512x384) 1,2,4,8,16 sRsrc_Vid_Civic_vi2PRGB640a Equ $8B ; Vesuvio (640x480) 1,2,4,8 sRsrc_Vid_Civic_vi2PRGB640b Equ $8C ; Vesuvio (640x480) 1,2,4,8,16 sRsrc_Vid_Civic_vi2PRGB768a Equ $8D ; Vesuvio (768x576) 1,2,4,8 sRsrc_Vid_Civic_vi2PRGB768b Equ $8E ; Vesuvio (768x576) 1,2,4,8,16 sRsrc_Vid_Civic_viFPa Equ $91 ; Full-Page 1,2,4 sRsrc_Vid_Civic_viFPb Equ $92 ; Full-Page 1,2,4,8 sRsrc_Vid_Civic_viFP512 Equ $93 ; Full-Page (512x384) 1,2,4,8 sRsrc_Vid_Civic_viFP640 Equ $94 ; Full-Page (640x480) 1,2,4,8 sRsrc_Vid_Civic_viGS Equ $97 ; Rubik 1,2,4,8,16 sRsrc_Vid_Civic_viGS560 Equ $98 ; Rubik-560 1,2,4,8,16 sRsrc_Vid_Civic_vi2Pa Equ $9B ; Two-Page 1,2,4 sRsrc_Vid_Civic_vi2Pb Equ $9C ; Two-Page 1,2,4,8 sRsrc_Vid_Civic_vi2P512 Equ $9D ; Two-Page (512x384) 1,2,4,8 sRsrc_Vid_Civic_vi2P640 Equ $9E ; Two-Page (640x480) 1,2,4,8 sRsrc_Vid_Civic_vi2P768 Equ $9F ; Two-Page (768x576) 1,2,4,8 sRsrc_Vid_Civic_viNTSCFFa Equ $A2 ; NTSC FF 1,2,4,8 sRsrc_Vid_Civic_viNTSCFFb Equ $A3 ; NTSC FF 1,2,4,8,16 sRsrc_Vid_Civic_viNTSCST Equ $A4 ; NTSC ST 1,2,4,8,16 sRsrc_Vid_Civic_viNTSCFFConva Equ $A5 ; NTSC FF Conv 1,2,4,8 (Actually Non-Conv) sRsrc_Vid_Civic_viNTSCFFConvb Equ $A6 ; NTSC FF Conv 1,2,4,8,16 (Actually Non-Conv) sRsrc_Vid_Civic_viNTSCSTConv Equ $A7 ; NTSC ST Conv 1,2,4,8,16 (Actually Non-Conv) sRsrc_Vid_Civic_viFPRGBa Equ $AA ; Full-Page RGB 1,2,4 sRsrc_Vid_Civic_viFPRGBb Equ $AB ; Full-Page RGB 1,2,4,8 sRsrc_Vid_Civic_viHRa Equ $B0 ; HiRes 1,2,4,8 sRsrc_Vid_Civic_viHRb Equ $B1 ; HiRes 1,2,4,8,16 sRsrc_Vid_Civic_viHRNTSCST Equ $B2 ; HiRes (512x384) 1,2,4,8,16 sRsrc_Vid_Civic_viHR400 Equ $B3 ; HiRes (640x400) 1,2,4,8,16 sRsrc_Vid_Civic_viHRMAZa Equ $B4 ; HiRes (704x512) 1,2,4,8 sRsrc_Vid_Civic_viHRMAZb Equ $B5 ; HiRes (704x512) 1,2,4,8,16 sRsrc_Vid_Civic_viPALFFa Equ $B8 ; PAL FF 1,2,4,8 sRsrc_Vid_Civic_viPALFFb Equ $B9 ; PAL FF 1,2,4,8,16 sRsrc_Vid_Civic_viPALSTa Equ $BA ; PAL ST 1,2,4,8 sRsrc_Vid_Civic_viPALSTb Equ $BB ; PAL ST 1,2,4,8,16 sRsrc_Vid_Civic_viPALFFConva Equ $BC ; PAL FF Conv 1,2,4,8 (Actually, non-Conv) sRsrc_Vid_Civic_viPALFFConvb Equ $BD ; PAL FF Conv 1,2,4,8,16 (Actually, non-Conv) sRsrc_Vid_Civic_viPALSTConva Equ $BE ; PAL ST Conv 1,2,4,8 (Actually, non-Conv) sRsrc_Vid_Civic_viPALSTConvb Equ $BF ; PAL ST Conv 1,2,4,8,16 (Actually, non-Conv) sRsrc_Vid_Civic_viVGAa Equ $C2 ; VGA 1,2,4,8 sRsrc_Vid_Civic_viVGAb Equ $C3 ; VGA 1,2,4,8,16 sRsrc_Vid_Civic_viSVGA56a Equ $C7 ; SVGA (56Hz) 1,2,4,8 sRsrc_Vid_Civic_viSVGA56b Equ $C8 ; SVGA (56Hz) 1,2,4,8,16 sRsrc_Vid_Civic_viSVGA72a Equ $CC ; SVGA (72Hz) 1,2,4,8 sRsrc_Vid_Civic_viSVGA72b Equ $CD ; SVGA (72Hz) 1,2,4,8,16 sRsrc_Vid_Civic_viSxVGA60a Equ $D1 ; SxVGA (60Hz) 1,2,4 sRsrc_Vid_Civic_viSxVGA60b Equ $D2 ; SxVGA (60Hz) 1,2,4,8 sRsrc_Vid_Civic_viSxVGA70a Equ $D6 ; SxVGA (70Hz) 1,2,4 sRsrc_Vid_Civic_viSxVGA70b Equ $D7 ; SxVGA (70Hz) 1,2,4,8 sRsrc_Vid_Civic_viGFa Equ $DB ; GoldFish 1,2,4,8 sRsrc_Vid_Civic_viGFb Equ $DC ; GoldFish 1,2,4,8,16 sRsrc_Vid_Civic_viGFNTSCST Equ $DD ; Goldfish (512x384) 1,2,4,8,16 sRsrc_Vid_Civic_viGFNTSCFFa Equ $DE ; Goldfish (640x480) 1,2,4,8 sRsrc_Vid_Civic_viGFNTSCFFb Equ $DF ; Goldfish (640x480) 1,2,4,8,16 sRsrc_Vid_Civic_viGFPALFFa Equ $E0 ; Goldfish (768x576) 1,2,4,8 sRsrc_Vid_Civic_viGFPALFFb Equ $E1 ; Goldfish (768x576) 1,2,4,8,16 sRsrc_Vid_Civic_vi19a Equ $E4 ; 19" 1,2,4 sRsrc_Vid_Civic_vi19b Equ $E5 ; 19" 1,2,4,8 ; ------ sRsrc_Civic_NeverMatch Equ $FE ; The “null” sRsrc ID