2019-06-29 23:17:50 +08:00

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;
; File: QMgrEqu.a
;
; Contains: Equates for the Queue Manager
;
; Written by: Dave Feldman
;
; Copyright: © 1989-1991 by Apple Computer, Inc., all rights reserved.
;
; Change History (most recent first):
;
; <4> 9/13/91 JSM Cleanup header.
; <3> 3/17/91 dnf dba, dty, #84977: Change interruptRegs to be the right
; registers. Add pascalRegs, and other register-related equates.
; <2> 9/22/90 dnf Add compatibility layer queue refnum
; <1.0> 9/18/89 dnf Adding to ease for the first time
;
; Queue Manager Globals
QMGlobals record 0, increment
DTQueuePtr ds.l 1 ; pointer to desktop mgr queue record
CLQueuePtr ds.l 1 ; pointer to the compatibility layer queue record
size equ *-QMGlobals
endr
; Queue Manager record
; Note that the first three fields are a standard OS queue, and they need to stay that way.
QMRec record 0, increment
qFlags ds.w 1 ; miscellaneous flags [word]
qHead ds.l 1 ; first element in queue [pointer]
qTail ds.l 1 ; last element in queue [pointer]
qType ds.w 1 ; queue refnum/queue type
qmFlags ds.b 1 ; QM flags
resrv1 ds.b 1 ; alignment byte
enQHook ds.l 1 ; hook called before enqueuing
deQHook ds.l 1 ; hook called just before dequeuing
stackBase ds.l 1 ; base of A6 stack
curStack ds.l 1 ; current A6 stack ptr (for i/o)
highWater ds.l 1 ; checked at each i/o
dsErr ds.w 1 ; where dsErr
perf1 ds.l 1 ; for performance measurement
perf2 ds.l 1
size equ *-QMRec
endr
; Queue Manager record flag bits
qIsBusy equ 0 ; 1 if queue is busy, 0 if queue is free
asyncCall equ 1 ; 1 if call is async, 0 if call is sync
; For now, use static Queue refNum assignment.
desktopQType equ 22
fsCompatQType equ 23
clStackSize equ 1500 ; compatibility layer gets 1500 bytes of stack
; Definitions for register saving: sets of registers, and register saving opcode
interruptRegs reg a4-a6/d4-d7 ; the ones that the interrupt dispatchers do not save
pascalRegs reg a2-a6/d3-d7 ; registers that Pascal needs protected
MOVEMSPPostIncOpcode equ $4CDF ; movem.l (sp)+, opcode
VolatileInterruptRegisterMask equ $70F0 ; a4-a6/d4-d7 register mask