mirror of
https://github.com/elliotnunn/supermario.git
synced 2024-11-22 04:31:30 +00:00
261 lines
10 KiB
Plaintext
261 lines
10 KiB
Plaintext
;
|
|
; File: SCSIMgrInitPSC.a
|
|
;
|
|
; Contains: SCSI Manager 53c96 initialization routines
|
|
;
|
|
; Written by: Jonathan Abilay/Paul Wolf
|
|
;
|
|
; Copyright: © 1990-1992 by Apple Computer, Inc. All rights reserved.
|
|
;
|
|
; Change History (most recent first):
|
|
;
|
|
; <SM2> 11/3/92 SWC Changed SCSIEqu.a->SCSI.a.
|
|
; <1> 6/2/92 kc first checked in
|
|
; <SM0> 6/01/92 kc Rolled in from Pandora.
|
|
; <1> 1/17/92 PDW first checked in
|
|
; ———————————————————————————————————————————————————————————————————————————————————————
|
|
; Pre-Pandora ROM comments begin here.
|
|
; ———————————————————————————————————————————————————————————————————————————————————————
|
|
; <2> 8/19/91 SAM (PDW) Reverted to old in/out buserr handler support. Added 'IF
|
|
; forROM' around initialization that is not needed in a linked
|
|
; patch.
|
|
; <1> 8/8/91 SAM (PDW) Checked into Regatta for the first time with lots of
|
|
; changes over the TERROR sources.
|
|
; <0> 8/8/91 SAM Split off from 7.0 GM sources.
|
|
;
|
|
; Pre Regatta split-off change history:
|
|
;
|
|
; <T7> 6/27/91 djw (pdw) Removed all traces of SCSIBusy and FreeHook stuff Added
|
|
; BusErr and CyclePhase jump vector initialization.
|
|
; <T6> 6/14/91 djw (actually PDW) Added jvTransfer initialization (overriding
|
|
; Transfer with Transfer_96).
|
|
; <T5> 6/9/91 BG (actually PDW) Rearranged headers to work more consistently
|
|
; between test INIT and ROM builds. Also added IF around
|
|
; _SetTrapAddress so that the INIT does not patch the trap
|
|
; address.
|
|
; <T4> 3/30/91 BG (actually JMA) Added PostFreeHook_96.
|
|
; <T3> 2/17/91 BG (actually JMA) added SlowComp_96, FastComp_96, DoSCSIBusy_96 &
|
|
; SCSIErr_96
|
|
; <T2> 1/5/91 BG (actually JMA) Added more functionalities.
|
|
; <T1> 12/7/90 JMA Checked into TERROR for the first time.
|
|
;
|
|
;========================================================================== <T3>
|
|
|
|
BLANKS ON ; assembler accepts spaces & tabs in operand field
|
|
STRING ASIS ; generate string as specified
|
|
PRINT OFF ; do not send subsequent lines to the listing file
|
|
; don't print includes
|
|
|
|
IF (&TYPE('forTestInit') = 'UNDEFINED') THEN
|
|
forTestInit: EQU 0
|
|
ENDIF
|
|
|
|
LOAD 'StandardEqu.d' ; from StandardEqu.a and for building ROMs
|
|
INCLUDE 'HardwarePrivateEqu.a' ; <T2>
|
|
INCLUDE 'SCSI.a'
|
|
INCLUDE 'SCSIPriv.a'
|
|
INCLUDE 'UniversalEqu.a' ; for TestFor <T2>
|
|
INCLUDE 'SCSIEqu96.a'
|
|
|
|
PRINT ON ; do send subsequent lines to the listing files
|
|
|
|
SCSIMgrInitPSC PROC EXPORT ;
|
|
|
|
EXPORT InitMgr_SCSI_PSC
|
|
|
|
; From SCSIMgr96.a ---
|
|
IMPORT SCSIMgr_PSC
|
|
IMPORT DoSCSICmd_PSC, DoSCSIComplete_PSC
|
|
IMPORT DoSCSISelect_sPSC, DoSCSISelect_dPSC ; <T2>
|
|
IMPORT DoSCSISelAtn_sPSC, DoSCSISelAtn_dPSC, CyclePhase_PSC ; <T9>
|
|
IMPORT DoSCSIStat_PSC, DoSCSIMsgOut_PSC
|
|
IMPORT Unimplemented_PSC
|
|
IMPORT DoSCSIReset_PSC, DoSCSIGet_PSC
|
|
IMPORT DoSCSIMsgIn_PSC
|
|
IMPORT NewSCSIRead_PSC, NewSCSIWrite_PSC
|
|
IMPORT NewSCSIWBlind_PSC, NewSCSIRBlind_PSC
|
|
IMPORT SCSIErr_PSC
|
|
; From SCSIMgrHW96.a ---
|
|
IMPORT BusErrHandler_PSC
|
|
IMPORT ResetBus_PSC, SlowRead_PSC, Transfer_PSC
|
|
IMPORT SlowWrite_PSC, SlowComp_PSC
|
|
IMPORT FastRead_PSC, FastWrite_PSC, FastComp_PSC
|
|
|
|
|
|
WITH scsiGlobalRecord
|
|
|
|
|
|
;-------------------------------------------------------------
|
|
;
|
|
; Initialization code for the SCSI Manager 5394/5396
|
|
|
|
InitMgr_SCSI_PSC
|
|
|
|
movem.l intrRegs, -(sp) ; save all registers, for convenience
|
|
moveq.l #0, zeroReg ; initialize "zeroReg"
|
|
movea.l SCSIGlobals, a4 ; get ptr to structure
|
|
|
|
moveq.l #numSelectors-1, d1 ; loop count
|
|
IF forTestInit OR forROM THEN ; if not a linked patch, make addrs relative
|
|
lea.l SCSIMgr_PSC, a1 ; get start of SCSI Mgr code
|
|
move.l a1, d0 ; remember base address
|
|
ELSE
|
|
moveq.l #0, D0 ; if linked patch, make addrs absolute
|
|
ENDIF
|
|
lea OffsetTbl96, a1 ; address of offset table
|
|
movea.l a4, a0 ; point to base of old SCSI Mgr jump table
|
|
@MakeJmpTbl
|
|
move.l (a1)+, d2 ; get the next offset
|
|
beq.s @skipEntry ; if zero, skip this entry
|
|
add.l d0, d2 ; compute the address
|
|
move.l d2, (a0) ; install it in the jump table
|
|
@skipEntry
|
|
adda.l #4, a0
|
|
dbra d1, @MakeJmpTbl ; loop for all vectors
|
|
|
|
lea.l Transfer_PSC, a1 ; <T6> <T2>
|
|
move.l a1, jvTransfer(a4) ; use this Transfer routine <T6> <T2>
|
|
|
|
lea.l CyclePhase_PSC, a1 ; <T7> pdw
|
|
move.l a1, jvCyclePhase(a4) ; use this CyclePhase routine <T7> pdw
|
|
|
|
lea.l ResetBus_PSC, a1
|
|
move.l a1, jvResetBus(a4) ; use this Bus Reset routine
|
|
|
|
lea.l BusErrHandler_PSC, a1 ; <T7> pdw
|
|
move.l a1, jvBusErr(a4) ; use this SCSI Bus Error handler <T7> pdw
|
|
|
|
move.l #1,blindBusTO(a4) ; initlz blind rd/wr timeout to ≈1mS
|
|
|
|
lea.l SlowRead_PSC, a1
|
|
move.l a1, jvVSRO(a4) ; use this Slow Read routine
|
|
|
|
lea.l SlowWrite_PSC, a1
|
|
move.l a1, jvVSWO(a4) ; use this Slow Write routine
|
|
|
|
lea.l SlowRead_PSC, a1
|
|
; lea.l FastRead_PSC, a1
|
|
move.l a1, jvVFRO(a4) ; use this Fast Read routine
|
|
|
|
lea.l SlowWrite_PSC, a1
|
|
; lea.l FastWrite_PSC, a1
|
|
move.l a1, jvVFWO(a4) ; use this Fast Write routine
|
|
|
|
lea.l SlowComp_PSC, a1 ; <T3> thru next <T3>
|
|
move.l a1, jvCSO(a4) ; use this Slow Compare routine
|
|
|
|
lea.l FastComp_PSC, a1
|
|
move.l a1, jvCFO(a4) ; use this Fast Compare routine
|
|
|
|
lea.l SCSIErr_PSC, a1
|
|
move.l a1, jvErr(a4) ; use this Error routine
|
|
|
|
lea.l Unimplemented_PSC, a1
|
|
move.l a1, jvClearIRQ(a4) ; use this clear IRQ routine
|
|
move.l a1, jvSel15(a4) ; Selector 15 routine
|
|
move.l a1, jvSel16(a4) ; Selector 16 routine
|
|
move.l a1, jvSel17(a4) ; Selector 17 routine <T3>
|
|
|
|
move.l zeroReg, d0 ; disable SCSI interrupts <T2> thru next <T2>
|
|
movea.l jvDisEnable(a4), a0 ; addr of interrupt enable/disable routine
|
|
jsr (a0) ; disable interrupts
|
|
|
|
IF forROM AND NOT forTestInit THEN ; <2>
|
|
clr.l G_IntrpStat(a4) ; clear our Intrp Status
|
|
clr.l G_FakeStat(a4) ; clear fake stat
|
|
clr.l G_State96(a4) ; clear our indicators of 53c96 state <T7> pdw
|
|
clr.l G_SCSIDevMap0(a4) ; initialize SCSI Device Map 0
|
|
clr.l G_SCSIDevMap1(a4) ; initialize SCSI Device Map 1
|
|
clr.l base539x1(a4) ; init second SCSI base address
|
|
clr.l G_SCSIDREQ(a4) ; initialize SCSI DREQ regr
|
|
|
|
; All this time we've been using a default host ID = 7. Just in case that ever changes <2>
|
|
; load whatever SCSIMgrInit got from PRAM as our host ID.
|
|
|
|
move.b G_ID(a4), d1 ; get SCSI host ID mask
|
|
move.b #7, d0 ; load shift count
|
|
@1
|
|
lsl.b #1, d1 ; shift out mask bit until all 0's
|
|
dbeq d0, @1 ; remaining count in d0 will be SCSI ID
|
|
ori.b #initCF1, d0 ; use this our designated SCSI host ID
|
|
move.b d0, rCF1(a3) ; use this new config regr. value, hopefully
|
|
; nobody has changed the setting since HW init time
|
|
|
|
move.l SCSIBase, base539x0(a4) ; load addr of first SCSI chip
|
|
move.l #SCSI0_DAFB, pdma5380(a4) ; load addr of DAFB regr containing DREQ bit
|
|
ENDIF ; <2>
|
|
|
|
; IF isUniversal THEN
|
|
TestFor SCSI96_2Exists ; do we have a second SCSICyc96 chip?
|
|
beq.s @noSCSICyc96 ;
|
|
@s2Exists
|
|
move.l SCSI2Base, base539x1(a4) ; addr of second SCSI chip
|
|
move.l #SCSI1_DAFB, hhsk5380(a4) ; load addr of DAFB regr containing DREQ bit
|
|
|
|
lea.l DoSCSISelect_dPSC, a1 ; point to Dual SCSICyc96 Select proc
|
|
move.l a1, jvSelect(a4) ; use this Select routine
|
|
|
|
lea.l DoSCSISelAtn_dPSC, a1 ; point to Dual SCSICyc96 Select/WAtn proc
|
|
move.l a1, jvSelAtn(a4) ; use this Select routine
|
|
@noSCSICyc96 ;
|
|
; ENDIF
|
|
move.b #mgrVersion2, state2(a4) ; save the version number
|
|
@InitDone
|
|
|
|
movem.l (sp)+, intrRegs ; restore registers
|
|
rts
|
|
|
|
|
|
|
|
;-------------------------------------------------------------
|
|
;
|
|
Macro
|
|
DispatchVector &ROMAddress
|
|
IF forTestInit OR forROM THEN ;
|
|
dc.l &ROMAddress-SCSIMgr_PSC
|
|
ELSE
|
|
dcImportResident &ROMAddress
|
|
ENDIF
|
|
EndM
|
|
|
|
OffsetTbl96
|
|
IF 1 THEN ;\/----\/----\/----\/
|
|
DispatchVector DoSCSIReset_PSC ; 0: SCSIReset
|
|
DispatchVector DoSCSIGet_PSC ; 1: SCSIGet
|
|
DispatchVector DoSCSISelect_sPSC ; 2: SCSISelect <T2>
|
|
DispatchVector DoSCSICmd_PSC ; 3: SCSICmd
|
|
DispatchVector DoSCSIComplete_PSC ; 4: SCSIComplete
|
|
DispatchVector NewSCSIRead_PSC ; 5: SCSIRead
|
|
DispatchVector NewSCSIWrite_PSC ; 6: SCSIWrite
|
|
DispatchVector Unimplemented_PSC ; 7: Was SCSIInstall
|
|
DispatchVector NewSCSIRBlind_PSC ; 8: SCSIRBlind
|
|
DispatchVector NewSCSIWBlind_PSC ; 9: SCSIWBlind
|
|
DispatchVector DoSCSIStat_PSC ; 10: SCSIStat
|
|
DispatchVector DoSCSISelAtn_sPSC ; 11: SCSISelAtn <T2>
|
|
DispatchVector DoSCSIMsgIn_PSC ; 12: SCSIMsgIn
|
|
DispatchVector DoSCSIMsgOut_PSC ; 13: SCSIMsgOut
|
|
ELSE ;/\----/\----/\----/\
|
|
DispatchVector 0 ; 0: SCSIReset
|
|
DispatchVector 0 ; 1: SCSIGet
|
|
DispatchVector DoSCSISelect_sPSC ; 2: SCSISelect <T2>
|
|
DispatchVector DoSCSICmd_PSC ; 3: SCSICmd
|
|
DispatchVector DoSCSIComplete_PSC ; 4: SCSIComplete
|
|
DispatchVector 0 ; 5: SCSIRead
|
|
DispatchVector 0 ; 6: SCSIWrite
|
|
DispatchVector 0 ; 7: Was SCSIInstall
|
|
DispatchVector 0 ; 8: SCSIRBlind
|
|
DispatchVector 0 ; 9: SCSIWBlind
|
|
DispatchVector DoSCSIStat_PSC ; 10: SCSIStat
|
|
DispatchVector DoSCSISelAtn_sPSC ; 11: SCSISelAtn <T2>
|
|
DispatchVector 0 ; 12: SCSIMsgIn
|
|
DispatchVector DoSCSIMsgOut_PSC ; 13: SCSIMsgOut
|
|
ENDIF
|
|
|
|
|
|
;==========================================================================
|
|
|
|
ENDWITH
|
|
|
|
END
|
|
|