;__________________________________________________________________________________________________
;
;	File:		SCCIOPSysEqu.aii
;
;	Contains:	IOP System Equates include file
;
;	Written by:	Bill O'Connor
;
;	Copyright:	© 1988-1991 by Apple Computer, Inc., all rights reserved.
;
;	Change History (most recent first):
;
;		 <4>	 8/26/91	JSM		Remove equates of TRUE and FALSE, now done in build script.
;		 <3>	 1/14/90	SWC		Fixed a comment in the header that wasn't a comment because the
;									semicolon was missing.
;		 <2>	 1/12/90	WTO		Change the value of IO_Cntl_Int to improve SCC access times.
;	   <1.2>	 11/2/89	WTO		Updated to handle DMA Lap
;	   <1.1>	  7/8/89	CCH		Added EASE comments to file.
;	   <1.0>	  2/8/89	SGS		Initial release
;__________________________________________________________________________________________________


DriverA		Equ		2
DriverB		Equ		3

Clock		Equ		$02						; 2 MHZ CPU clock

*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
*
* Hardware equates
*
*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

IOBase			Equ		$f000				; IOP I/O base address

TmCnt_Lo		Equ		IOBase+$10			; Timer low count address
TmCnt_Hi		Equ		IOBase+$11			; Timer high count address
TmLatch_Lo		Equ		IOBase+$12			; Timer latch low address
TmLatch_Hi		Equ		IOBase+$13			; Timer latch high address
DMA1_Cntl		Equ		IOBase+$20			; DMA channel 1 control
DMA1_AddrLo		Equ		IOBase+$21			; DMA channel 1 low address
DMA1_AddrHi		Equ		IOBase+$22			; DMA channel 1 high address
DMA1_CntLo		Equ		IOBase+$23			; DMA channel 1 transfer count low
DMA1_CntHi		Equ		IOBase+$24			; DMA channel 1 transfer count high

DMA2_Cntl		Equ		IOBase+$28			; DMA channel 2 control
DMA2_AddrLo		Equ		IOBase+$29			; DMA channel 2 low address
DMA2_AddrHi		Equ		IOBase+$2a			; DMA channel 2 high address
DMA2_CntLo		Equ		IOBase+$2b			; DMA channel 2 transfer count low
DMA2_CntHi		Equ		IOBase+$2c			; DMA channel 2 transfer count high

SCC_Cntl		Equ		IOBase+$30			; SCC control register
IO_Cntl			Equ		IOBase+$31			; I/O control register
TD_Cntl			Equ		IOBase+$32			; Timer/DPLL control register
Int_Mask		Equ		IOBase+$33			; Interrupt Mask register
Int_Reg			Equ		IOBase+$34			; IOP interrupt register address
Int_Host		Equ		IOBase+$35			; Interrupt host register


SCC_BCntl		Equ		IOBase+$40			; IOP SCC control register channel B
SCC_BStat		Equ		IOBase+$40			; IOP SCC status register channel B
SCC_ACntl		Equ		IOBase+$41			; IOP SCC control register channel A
SCC_AStat		Equ		IOBase+$41			; IOP SCC status register channel A
SCC_BData		Equ		IOBase+$42			; IOP SCC data register channel B
SCC_AData		Equ		IOBase+$43			; IOP SCC data register channel A

*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
*
* Software equates
*
*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

SCC_Cntl_Init	Equ		$00				; Initial value for SCC control register
IO_Cntl_Init	Equ		$23				; Initial value for I/O control register
Int0			Equ		%00000100		; Host interrupt 0
Int1			Equ		%00001000		; Host interrupt 1

*
* SCC control register equates
*

ByPass_Bit		Equ		%00000001		; ByPass mode bit mask
SCC_Port		Equ		%00000000		; Make IOP SCC
ISM_Port        Equ     %00000010       ; Make IOP ISM
PClk39			Equ		%00000000       ; P Clock is 3.9 MHZ
PClk78			Equ		%00000100       ; P Clock is 7.8 MHZ
RTXCA_36		Equ		%00000000       ; RTXCA source is 3.6864 MHZ
RTXCA_DPClk		Equ		%00001000       ; RTXCA source is DPCLK/16
RTXCA_DPLL		Equ		%00010000       ; RTXCA source is DPLL
RTXCA_GPIA		Equ		%00011000       ; RTXCA source is GPIA
RTXCB_36		Equ		%00000000       ; RTXCB source is 3.6864 MHZ
RTXCB_DPClk		Equ		%00100000       ; RTXCB source is DPCLK/16
RTXCB_DPLL		Equ		%01000000       ; RTXCB source is DPLL 
RTXCB_GPIA		Equ		%01100000       ; RTXCA source is GPIA
DeBugg			Equ		%10000000

*
* Interrupt Mask register equates
*

DMA1_Msk		Equ		%00000010
DMA2_Msk		Equ		%00000100
SCC_Msk			Equ		%00001000
Host_Msk		Equ		%00010000		;
Timer_Msk		Equ		%00100000

*
* Timer DPLL control register equates
*

One_Shot        Equ     %00000001       ;       
Continuous      Equ     %00000001
DPLLA_En        Equ     %00010000       ; Enable DPLL for channel A
RxCDA_Msk       Equ     %00100000       ; Receive carrier detected mask
DPLLB_En        Equ     %01000000       ; Enable DPLL for channel B
RxCDB_Msk       Equ     %10000000       ; Receive carrier detected mask

StackPage		Equ		$0100			; Stack page

pswB			Equ		%00010000		; Processor status word decode for BRK


*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
*
*	Interrupt priority type equates.  
*
*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

UnKnwn			Equ		$00
SCC				Equ		$02					; SCC interrupt 
DMA2			Equ		$04					; DMA2 interrupt 
DMA1			Equ		$06					; DMA1 interrupt 
TIMER			Equ		$08					; Timer interrupt 
HOST			Equ		$0a					; Host interrupt 

B_BufEmp		Equ		$00					; Channel B transmit buffer empty
B_EXT			Equ		$02					; Channel B external status change
B_RX			Equ		$04					; Channel B receive character available
B_SpecRx		Equ		$06					; Channel B special receive condition

A_BufEmp		Equ		$08					; Channle A transmit buffer empty 
A_EXT			Equ		$0a					; Channel A external status change
A_RX			Equ		$0c					; Channel A receive character available
A_SpecRx		Equ		$0e					; Channel A special receive condition

*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
*
* SCC register constants
*
*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Wr_reg0			Equ		$00
Wr_reg1			Equ		$01
Wr_reg2			Equ		$02
Wr_reg3			Equ		$03
Wr_reg4			Equ		$04
Wr_reg5			Equ		$05
Wr_reg6			Equ		$06
Wr_reg7			Equ		$07
Wr_reg8			Equ		$08
Wr_reg9			Equ		$09
Wr_reg10		Equ		$0a
Wr_reg11		Equ		$0b
Wr_reg12		Equ		$0c
Wr_reg13		Equ		$0d
Wr_reg14		Equ		$0e
Wr_reg15		Equ		$0f

Rd_reg0			Equ		$00
Rd_reg1			Equ		$01
Rd_reg2			Equ		$02
Rd_reg3			Equ		$03
Rd_reg8			Equ		$08
Rd_reg10		Equ		$0a
Rd_reg12		Equ		$0c
Rd_reg13		Equ		$0d
Rd_reg15		Equ		$0f

*
* Software Equates
*
* Register bit masks
*
*
* Write register 0
*

Reset_ExtInt	Equ		%00010000		; $10 Reset external status interrupts
RxInt_Enable	Equ		%00100000		; $20 Enable interrupt on next recieved char
Reset_TxPend	Equ		%00101000		; $28 Reset Tx interrupt pending
Err_Reset		Equ		%00110000		; $30 Error reset
Reset_IUS		Equ		%00111000		; $38 Reset highest IUS
Reset_TxCRC		Equ		%10000000		; $80 Reset Tx CRC latch
Reset_TxUnRun	Equ		%11000000		; $C0 Reset Tx underrun/EOM

*
* Write register 1
*

Ext_IntEnable	Equ		%00000001		; $01 External interrupt enable
Tx_IntEnable	Equ		%00000010		; $02 Tx interrupt enable
Par_SpcCnd		Equ		%00000100		; $04 Parity is special condition
Rx_IntDisable	Equ		%00000000		; $00 Rx interrupt disable
Int_1RxChar		Equ		%00001000		; $08 Interrupt on first received character
Int_RxChar		Equ		%00010000		; $10 Interrupt on all received characters
Int_SpcCnd		Equ		%00011000		; $18 Interrupt special condition only
DMA_Rx			Equ		%00100000		; $20 DMA active for Rx
DMA_Tx			Equ		%00000000		; $00 DMA active for Tx
DMA_Req			Equ		%01000000		; DMA request funtion = request
DMA_Enable		Equ		%10000000		; DMA enable

*
* Write register 3
*

Rx_Enable		Equ		%00000001		; $01 Receive enable
Sync_Inhibit	Equ		%00000010		; $02 Sync char load inhibit
Addr_Srch		Equ		%00000100		; $04 Address search enable
Rx_CRC			Equ		%00001000		; $08 Receive CRC enable
Hunt_Enable		Equ		%00010000		; $10 Enable Hunt/Sync
Auto_Eanable	Equ		%00100000		; $20 Programs func of DCD and CTS pins
Rx_5Bits		Equ		%00000000		; $00 Set Rx to 5 bits per char
Rx_7Bits		Equ		%01000000		; $40 Set Rx to 7 bits per char
Rx_6Bits		Equ		%10000000		; $80 Set Rx to 6 bits per char
Rx_8Bits		Equ		%11000000		; $c0 Set Rx to 8 bits per char

*
* Write register 4
*

Par_Enable		Equ		%00000001			; $01 Parity Enable
Par_Even		Equ		%00000010			; $02 Parity Even
Par_Odd			Equ		%00000000			; $00 Parity Odd
Sync_Enable		Equ		%00000000			; $00 Sync modes enable
StopBit1		Equ		%00000100			; $04 1 stop bits/char
StopBit15		Equ		%00001000			; $80 1.5 stop bits/char
StopBit2		Equ		%00001100			; $C0 2 stop bits/char
Sync8			Equ		%00000000			; $00 8 bit sync char
Sync16			Equ		%00010000			; $10 16 bit sync char
SDLC_Mode		Equ		%00100000			; $20 Set SDLC mode
Ext_Sync		Equ		%00110000			; $30 External sync mode
X1Clk			Equ		%00000000			; $00 X 1 clock
X16Clk			Equ		%01000000			; $40 X 16 clock
X32Clk			Equ		%10000000			; $80 X 32 clock
X64Clk			Equ		%11000000			; $C0 X 64 clock

*
* Write register 5
*

Tx_CRC			Equ		%00000001			; $01 Enable Tx CRCs
Dvr_Enable		Equ		%00000010			; $02 Enable output driver
CRC16Poly		Equ		%00000100			; $04 CRC 16 polynomial
SDLCPoly		Equ		%00000000			; $00 SDLC CRC polynomial
Tx_Enable		Equ		%00001000			; $08 Enable Tx
SndBreak		Equ		%00010000			; $10 Send break
Tx_5Bits		Equ		%00000000			; $00 Set Tx to 5 bits per char
Tx_7Bits		Equ		%00100000			; $20 Set Tx to 7 bits per char
Tx_6Bits		Equ		%01000000			; $40 Set Tx to 6 bits per char
Tx_8Bits		Equ		%01100000			; $60 Set Tx to 8 bits per char
DTRSet			Equ		%10000000			; $80 trun DTR on

*
* Write register 7
*

SDLC_Flag		Equ		$7e					; SDLC flag

*
* Write register 9
*

No_Vec			Equ		%00000010			; $02 No vector
MIE				Equ		%00001000			; $08 Master Interrupt enable
NoReset			Equ		%00000000			; $00 NoReset
ChanB_Reset		Equ		%01000000			; $40 Reset channel B
ChanA_Reset		Equ		%10000000			; $80 Reset channel A
SCC_Reset		Equ		%11000000			; $C0 Force SCC Reset	

*
* Write register 10
*

Bit8Sync		Equ		%00000000			; $00 8 bit sync
Bit6Sync		Equ		%00000001			; $01 6 bit sync
Loop			Equ		%00000010			; $02 loop 
CRC_UnRun		Equ		%00000000			; $00 send CRC on transmit underrun
Abort_UnRun		Equ		%00000100			; $04 send Abort on transmit underrun
Flg_Idle		Equ		%00000000			; $00 send flag on idle
Mark_Idle		Equ		%00001000			; $08 send mark on idle
ActivePoll		Equ		%00010000			; $10 go active on poll
NRZ				Equ		%00000000			; $00 Set NRZ mode
NRZI			Equ		%00100000			; $20 Set NRZI mode
FM1				Equ		%01000000			; $40 Set FM1 mode
FM0				Equ		%01100000			; $60 Set FM0 mode
CRC_Preset		Equ		%10000000			; $80 CRC Preset

*
* Write register 11
*

TRxC_XTAL		Equ		%00000000			; $00 TRxC = XTAL
TRxC_TxClk		Equ		%00000001			; $01 TRxC = Transmit clock
TRxC_BR			Equ		%00000010			; $02 TRxC = Baud Rate generator
TRxC_DPLL		Equ		%00000011			; $03 TRxC = DPLL 
TxClk_RTxC		Equ		%00000000			; $00 Transmit clock = ~RTxC pin
TxClk_TRXC		Equ		%00001000			; $08 Transmit clock = ~TRxC
TxClk_BR		Equ		%00010000			; $10 Transmit clock = Baud rate generator output
TxClk_DPLL		Equ		%00011000			; $18 Transmit clock = DPLL
RxClk_RTxC		Equ		%00000000			; $00 Receive clock = ~RTxC pin
RxClk_TRxC		Equ		%00100000			; $20 Receive clock = ~TRxC pin
RxClk_BR		Equ		%01000000			; $40 Receive clock = Br generator
RxClk_DPLL		Equ		%01100000			; $60 Receive clock = DPLL output

*
* Write register 12
*

Baud_Lo			Equ		$06					; Low value for baud rate generator

*
* Write register 13
*

Baud_Hi			Equ		$00					; High value for buad rate generator

*
* Write register 14
*

BR_Enable		Equ		%00000001			; $01 Enable baud rate generator
BR_SrcRTxC		Equ		%00000010			; $02 BR source is RTxC pin
ReqFunc			Equ		%00000100			; $04 Request Function
AutoEcho		Equ		%00001000			; $08 Auto enable mode of operation
LoopBck			Equ		%00010000			; $10 Local loop back mode
Srch_Mode		Equ		%00100000			; $20 Enter search mode 
Reset_MCLock	Equ		%01000000			; $40 Reset missing clock latch
Disable_DPLL	Equ		%01100000			; $60 Disable DPLL
DPLL_BR			Equ		%10000000			; $80 DPLL source is Baud Rate generator
DPLL_RTxC		Equ		%10100000			; $A0 DPLL source is RTxC pin
DPLL_FM			Equ		%11000000			; $C0 Set DPLL to FM mode
DPLL_NRZI		Equ		%11100000			; $E0 Set DPLL to NRZI mode

*
* Write register 15
*

ZeroCount_IE	Equ		%00000010			; $01 Zero count IE
DCD_IE			Equ		%00001000			; $08 DCD IE
SyncHunt_IE		Equ		%00010000			; $10 Sync/Hunt IE
CTS_IE			Equ		%00100000			; $20 CTS IE
TxUnRun_IE		Equ		%01000000			; $40 Tx UnderRun IE
BrkAbort_IE		Equ		%10000000			; $80 Break Abort IE

*
* Read register 0
*

Rx_CharAvail	Equ		%00000001			; $01 Rx character available
ZeroCount		Equ		%00000010			; $02 BR zero count
Tx_BufEmpty		Equ		%00000100			; $04 Transmit buffer empty mask
DCD_Msk			Equ		%00001000			; $08 DCD
SyncHunt		Equ		%00010000			; $10 Sync Hunt
CTS_Msk			Equ		%00100000			; $20 CTS
Tx_UnRun		Equ		%01000000			; $40 Tx underrun/EOM
BreakAbort		Equ		%10000000			; $80 Break abort

*
* Read register 1
*

AllSent			Equ		%00000001			; $01 All sent
Par_Err			Equ		%00010000			; $10 Parity Error
Rx_OvRun		Equ		%00100000			; $20 Receive buffer overrun
CRC_Err			Equ		%01000000			; $40 CRC error
End_Frame		Equ		%10000000			; $80 End of frame

*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
*
* Diagnostic and Error Equates
*
*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

NonMask			Equ		$00

*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
*
* Message Passing Equates
*
*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

TxMsgCnt		Equ		$0300			; Address of Transmit max message count
RxMsgCnt		Equ		$0200			; Address of Receive max message count
TxMsgPage		Equ		$0300			; Transmit message page
RxMsgPage		Equ		$0200			; Receive message page
TxMsgState		Equ		TxMsgPage		; Beginning address of state variables - 1
RxMsgState		Equ		RXMsgPage		; Beginning address of state variables -1
MaxTxMsg		Equ		$07				; Maximum number of Transmit messages
MaxRxMsg		Equ		$07				; Maximum number of receive messages

Idle			Equ		$00				; Message Idle
NewMsgSent		Equ		$01				; New message sent
MsgRcv			Equ		$02				; Message received
MsgCmplt		Equ		$03				; Message complete

*
* Kernel Error Messages
*

NoErr			Equ		0
Error			Equ		-1				; Didn' like sumthin (Unable to write packet etc.)
UnKnwnMsg		Equ		-2				; Received an unsupported message
DvrInUse		Equ		-3				; Driver is already in use
InByPass		Equ		-4				; IOP is in bypass mode
NotAlloc		Equ		-5				; Driver has not been allocated
BadID			Equ		-6				; The wrong ID was used to turn off ByPass

*
* ALap Error Messages
*

ENQFailed		Equ		-1				; ACK was received during ENQ attempt

DvrA			Equ		$00
DvrB			Equ		$01
Kern			Equ		$02
MaxDvr			Equ		DvrB

*
* Kernel Equates
*

Krn_CmdBase		Equ		$0000			; Base address of kernel command table
KCmd_Table_size	Equ		$28				; Size of Kernel command table in bytes

InstRxMsg		Equ		$00				; Install receive message signaller
RemvRxMsg		Equ		$00				; Remove receive message signaller
InstTxCmpl		Equ		$01 			; Install transmit completion routine
RemvTxCmpl		Equ		$01				; Remove transmit completion routine
InstISR			Equ		$02				; Install an interrupt service routine handler
RemvISR			Equ		$02				; Remove an interrupt service routine
SCCISR			Equ		$03				; Install SCC interrupt handler
RemvSCCISR		Equ		$03				; Remove an interrupt service routine
InstTask		Equ		$04				; Install a task into event loop
KillTask		Equ		$04				; Deinstall a task from the loop
RelTask			Equ		$05				; Release a task for one cycle
WaitEvent		Equ		$06				; Wait for an event
SignalTask		Equ		$07				; Signal a task that an event has occurred
ResetEvent		Equ		$08				; Reset the event flag after the event is handled
ResetChan		Equ		$09				; Reset SCC channel
GetTMPB			Equ		$0a				; Get a timer parameter block index
InstTmTask		Equ		$0b				; Install a timer task
RegVer			Equ		$0c				; Register version info

*
* Kernel Signals
*

InitFin			Equ		$02				; Signal to Kernel that driver has initialized

*
* Task ID's
*

TCBSize			Equ		$05
Kern_ID			Equ		$00
DvrA_ID			Equ		TCBSize
DvrB_ID			Equ		(2*TCBSize)

*
* TMPB Time constants (1 tick = 256 clocks @1.9584MHz = 130.71895 uSec)
*

TMPB1second		Equ		7650				; 1 second
TMPB100ms		Equ		TMPB1second/10		; 100 milliseconds
TMPB10ms		Equ		TMPB1second/100		;  10 milliseconds
TMPB1ms			Equ		TMPB1second/1000 	;   1 millisecond

*
* Task Stack Pointers
*

Kern_Sp			Equ		$1FF
DvrA_Sp			Equ		$1A9				; Driver A stack bottom
DvrB_Sp			Equ		$154				; Driver B stack bottom

*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
*
*	IOP Zero Page Memory Map
*
*  The IOP has three things going on: 
*	i.   kernel/operating system/host interface
*  	ii.  driver for channel A
*	iii. driver for channel B
*
*  The Zero page will be divided equally among the three.
*  This gives 85 bytes per process.
*
*				____________________
*			   | Driver B Zp		| $AA-$FF
*				___________________
*			   | Driver A Zp		| $55-$A9
*				___________________
*			   | Kernel Zp			| $00-$54
*				___________________
*
* Zero Page Variables
*
*
* Memory Map
*
*				____________________
*			   | Driver B 			| $56AA-$7fef
*				___________________
*			   | Driver A 			| $2d55-$56a9
*				___________________
*			   | Kernel 			| $400-$2d54
*				___________________
*
*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Kernel_ZP		Equ		KCmd_Table_size+1
DvrA_Zp			Equ		$55
DvrB_Zp			Equ		$aa

Kern_Base		Equ		$400

DvrA_Base		Equ		$2d55
DvrB_Base		Equ		$56aa
DvrA_Top		Equ		DvrB_Base-1
DvrB_Top		Equ		$7fef-1
DvrA_Close		Equ		DvrA_Base+3
DvrB_Close		Equ		DvrB_Base+3

*
* Kernel Macros
*
* The 65C02 does not has a JSR (Address) instruction.
* To emulate this instruction your code should contain a table
* like this. Each procedure using these macros must then import
* this table address.
*
* Cmd_JmpTable	Jmp		(Krn_CmdBase+(RemvRxMsg*2))
*				Jmp		(Krn_CmdBase+(RemvTxCmpl*2))
*				Jmp		(Krn_CmdBase+(RemvISR*2))
*				Jmp		(Krn_CmdBase+(RemvSCCISR*2))
*				Jmp		(Krn_CmdBase+(InstTask*2))
*				Jmp		(Krn_CmdBase+(RelTask*2))
*				Jmp		(Krn_CmdBase+(WaitEvent*2))
*				Jmp		(Krn_CmdBase+(SignalTask*2))
*				Jmp		(Krn_CmdBase+(ResetEvent*2))
*				Jmp		(Krn_CmdBase+(ResetChan*2))
*				Jmp		(Krn_CmdBase+(GetTMPB*2))
*				Jmp		(Krn_CmdBase+(InstTmTask*2))
*				Jmp		(Krn_CmdBase+(RegVer*2))
*

*
* Install Receive message signaller macro
*
* Arguments
*
*	&MsgNum 	- number of the message box that uses this handler
*	&HndleAddr 	- the handler address
*


				MACRO
				_Inst_RxMsgSgn		&MsgNum, &SgnAddr
				
				Ldy		#>&SgnAddr				; Push the handler address
				Lda		#<&SgnAddr
				Ldx		#&MsgNum*2				; Put the message number in register A
				Sec								; Set carry to message install signaller
				Jsr		Cmd_JmpTable+(InstRxMsg*3)
				
				ENDM

*
* Remove Receive message signaller macro
*
* Arguments
*
*	&MsgNum 	- number of the message box that uses this handler
*


				MACRO
				_Remv_RxMsgSgn		&MsgNum
				
				Ldx		#&MsgNum*2				; Put the message number in register A
				Clc								; Clear carry to do remove message signaller
				Jsr		Cmd_JmpTable+(InstRxMsg*3)
				
				ENDM

*
* Install Transmit completion signaller macro
*
* Arguments
*
*	&MsgNum 	- number of the message box that uses this handler
*	&HndleAddr 	- the handler address
*
				
				MACRO
				_Inst_TxCmplSgn	&MsgNum, &SgnAddr
				
				Ldy		#>&SgnAddr				; Push the handler address
				Lda		#<&SgnAddr
				Ldx		#&MsgNum*2				; Load the msg number in register A
				Sec								; Set carry to install message signaller
				Jsr		Cmd_JmpTable+(InstTxCmpl*3)		; Do the indirect jump
				
				ENDM

*
* Remove Transmit completion signaller macro
*
* Arguments
*
*	&MsgNum 	- number of the message box that uses this handler
*
				
				MACRO
				_Remv_TxCmplSgn	&MsgNum
				
				Ldx		#&MsgNum*2				; Load the msg number in register A
				Clc								; Clear carry to do remove signaller
				Jsr		Cmd_JmpTable+(InstTxCmpl*3)		; Do the indirect jump
				
				ENDM
				
				
*
* Assign  an interrupt routine
*
* Arguments
*
*	&Type 		- The  type of interrupt
*	&HndlAddr	- The interrupt handler address
*
				
				MACRO
				_Inst_ISR	&Type, &HndlAddr
				
				Ldy		#>&HndlAddr				; Push the handler address
				Lda		#<&HndlAddr
				Ldx		#&Type
				Sec								; Set carry for install ISR
				Jsr		Cmd_JmpTable+(InstISR*3)	; Do the indirect jump
				
				ENDM

*
* Remove an interrupt service routine routine
*
* Arguments
*
*	&Type 		- The  type of interrupt
*
				
				MACRO
				_Remv_ISR	&Type
				
				Ldx		#&Type
				Clc									; Clear carry for remove ISR
				Jsr		Cmd_JmpTable+(RemvISR*3)	; Do the indirect jump
				
				ENDM
				
*
* Assign an SCC interrupt routine
*
* Arguments
*
*	&Type 		- The type of interrupt
*	&HndlAddr	- The interrupt handler address
*
				
				MACRO
				_Inst_SCC_ISR	&Type, &HndlAddr
				
				Ldy		#>&HndlAddr					; Push the handler address
				Lda		#<&HndlAddr
				Ldx		#&Type
				Sec									; Set carry for install SCC ISR
				Jsr		Cmd_JmpTable+(SCCISR*3)	; Do the indirect jump
				
				ENDM
				
*
* Remove an SCC interrupt routine
*
* Arguments
*
*	&Type 		- The type of interrupt
*
				
				MACRO
				_Remv_SCC_ISR	&Type
				
				Ldx		#&Type
				Clc									; Clear carry for remove SCC ISR
				Jsr		Cmd_JmpTable+(RemvSCCISR*3)	; Do the indirect jump
				
				ENDM

*
* Install a Task
*
* Arguments
*
*	&ID 		- the task ID
*	&TaskAddr	- the task address
*
				
				MACRO
				_Inst_Task	&ID, &TaskAddr
				
				Ldy		#>&TaskAddr				; Push the handler address
				Lda		#<&TaskAddr
				Ldx		#&ID
				Sec								; Set the Carry install task
				Jsr		Cmd_JmpTable+(InstTask*3)	; Do the indirect jump
				
				ENDM

*
* Kill a task
*
* Argument
*
*	&ID - the task ID
*
				
				MACRO
				_Kill_Task	&ID
				
				Ldx		#&ID
				Clc									; Clear Carry for kill task
				Jsr		Cmd_JmpTable+(KillTask*3)	; Do the indirect jump
				
				ENDM


*
* Wait for an event to occur
*
* Arguments
*
*	&Type 	- the event type or types we are waiting for
*
				
				MACRO
				_Wait_Event	&Type
				
				Lda		#&Type
				Jsr		Cmd_JmpTable+(WaitEvent*3)	; Do the indirect jump
				
				ENDM
				
*
* Signal Task that an event has occurred
*
* Arguments
*
* &ID	- ID of task you wish to signal
* &Sgn  - mask you wish placed in tasks tEvent
*

				MACRO
				_Signal_Task	&ID, &Sgn
				
				Ldx		#&ID
				Lda		#&Sgn
				Jsr		Cmd_JmpTable+(SignalTask*3)
				
				ENDM

*
* Reset the event after it has occurred.
*
* Arguments
*
*	&Type 	- the event type or types we are reseting.
*			  (Actually the complement of the Flags we use for _Wait_Event)
*
				
				MACRO
				_Reset_Event	&Type
				
				Lda		#≈&Type
				Jsr		Cmd_JmpTable+(ResetEvent*3)	; Do the indirect jump
				
				ENDM

*
* Relase this task for one Tasking cycle
*
* Arguments
*
*
				
				MACRO
				_Release_Task	
				
				Jsr		Cmd_JmpTable+(RelTask*3)	; Do the indirect jump
				
				ENDM

*
* Reset Channel
*
* Arguments
*
* &Chan - channel A or channel B
*

				MACRO
				_Reset_Chan		&Chan
				
				If	&Chan='A' then
				Sec
				ElseIf &Chan='B' then
				Clc
				Else
				AERROR 'Must specify A or B channel
				EndIf
				
				Jsr		Cmd_JmpTable+(ResetChan*3)
				
				ENDM
				
*
* _Get_TMPB - get a timer parameter block.
*
* Arguments
*
* none
*
* Returns parameter block index in register Y
*

				MACRO
				_Get_TMPB
				
				Clc
				Jsr		Cmd_JmpTable+(GetTMPB*3)
				
				ENDM
				
*
* _Free_TMPB - free a timer parameter block.
*
* Arguments
*
* If &Param is equal to the null string then it is assumed
* the index is already in register Y.  Else register Y is
* loaded with &Param.
*

				MACRO
				_Free_TMPB	&Param
				
				Sec
				IF	&PARAM='' THEN
				Jsr		Cmd_JmpTable+(GetTMPB*3)
				ELSE
				Ldy		&Param
				Jsr		Cmd_JmpTable+(GetTMPB*3)
				ENDIF
				
				ENDM
				
*
* _Inst_TmTask - install a timer task.
*
* Arguments
*
* If &Param is equal to the null string then it is assumed
* the index is already in register Y.  Else register Y is
* loaded with &Param.
*
* &Addr - address of the time and completion routine paramaters
*

				MACRO
				_Inst_TmTask	&Addr
				
				Clc
				Lda		#<&Addr
				Ldx		#>&Addr
				Jsr		Cmd_JmpTable+(InstTmTask*3)
				
				ENDM
				
*
* _Cancel_TmTask - cancel a timer task.
*
* Arguments
*
* If &Param is equal to the null string then it is assumed
* the index is already in register Y.  Else register Y is
* loaded with &Param.
*

				MACRO
				_Cancel_TmTask	&Param
				
				Sec
				IF	&PARAM='' THEN
				Jsr		Cmd_JmpTable+(InstTmTask*3)
				ELSE
				Ldy		&Param
				Jsr		Cmd_JmpTable+(InstTmTask*3)
				ENDIF
				
				ENDM
				
*
* Register Version info
*
* Arguments
*
*	&ID 		- the Driver ID
*	&InfoAddr	- the task address
*
				
				MACRO
				_Reg_Ver	&ID, &InfoAddr
				
				Ldy		#>&InfoAddr				; Push the handler address
				Ldx		#<&InfoAddr
				Lda		#&ID
				Jsr		Cmd_JmpTable+(RegVer*3)	; Do the indirect jump
				
				ENDM

