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212 lines
7.9 KiB
Plaintext
212 lines
7.9 KiB
Plaintext
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; File: AMICEqu.a
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; Contains: Equates for accessing the Apple Macintosh I/O Controller (AMIC) on PDM
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;
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; Written by: Dave Calvert
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;
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; Copyright: © 1992-1993 by Apple Computer, Inc. All rights reserved.
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;
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; This file is used in these builds: ROM RISC (PDM ENET)
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;
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; Change History (most recent first):
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;
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; <SM21> 11/10/93 fau From SuperMunggio: Changed the check to see if the file has
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; already been included.
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; <SM20> 10/14/93 pdw <MC2>
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; <SM19> 9/13/93 SAM Backed out the last rev. The multipier that was changed in
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; <SM17> indicates the number of bytes in each entry. Two longs =
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; 8 bytes.
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; <SM18> 9/13/93 RC Fixed a bug with the number of Vectors which were being
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; allocated for the AMIC DMA handlers
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; <MC2> 9/13/93 SAM Changed the ddVectCount to be a byte quantity instead of a long.
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; <SM17> 9/10/93 pdw Pulled the SCC Lvl 4 Port A and B interrupt vectors/refcons out
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; of the DMA Dispatch portion of DMADispatchGlobals.
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; <SM16> 9/9/93 pdw Another rearrangement of the DMADispatchGlobals structure.
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; <SMG3> 9/1/93 chp Added a slightly less verbose version DMADispGlobals (formerly
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; in InternalOnlyEqu.a). Added symbolic constants previously
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; defined in SonySWIM3.a.
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; <SMG2> 8/30/93 chp Add an interrupt handler selector for level 3 MACE interrupts,
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; which are now dispatched through InterruptHandlers.a as well.
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; <SM14> 8/1/93 pdw Adding SCSI equates.
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; <SM13> 6/14/93 kc Moved some AMIC vectors from obsolete DMAMgrEqu.a.
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; <SM12> 6/2/93 GMR Changed name of DMA reset bit, so it won't conflict with same
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; definition in other include file.
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; <SM11> 6/1/93 dwc Support for work-around to wait for MACE transmit status valid.
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; <SM10> 5/27/93 dwc Added _GetMicroSeconds trap definition to use in AMIC
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; work-around code.
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; <SM9> 5/4/93 dwc Added debug code to work around AMIC's returning FF's on the
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; first read.
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; <SM8> 4/16/93 dwc Add equates for SonoraPrimaryInit.a to mask and clear MACE
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; interrupts.
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; <SM7> 4/6/93 dwc Updated for level 4 DMA interrupts.
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; <SM6> 3/24/93 dwc Added code to try to recover when interrupt level is lowered
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; during packet handling.
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; <SM5> 3/9/93 jmp Moved an equate that was originally placed in
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; SonoraPrimaryInit.a to this file.
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; <SM4> 3/5/93 dwc Removed some more debugging code.
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; <SM3> 2/25/93 dwc Enable receive, remove some debug equates.
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; <SM2> 2/24/93 dwc Cleaned up some debug equates, added some more debug equates,
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; disabled receive for the PDM D5 ROM build.
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;
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;
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IF &TYPE('__INCLUDINGAMICEQU__') = 'UNDEFINED' THEN
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__INCLUDINGAMICEQU__ SET 1
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; Ethernet MACE equate for SonoraPrimaryInit.a
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MACE_INT EQU $80 ; MACE interrupt status register offset <SM8>
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MACE_INT_MSK EQU $90 ; MACE interrupt mask register offset <SM8>
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MACE_BIU_CNFG EQU $B0 ; BIU config register offset to reset MACE
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;
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; AMIC DMA Register offsets
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;
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; AMIC Interrupt Register offsets
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AMIC_INT_CTL EQU -$7000 ; AMIC Interrupt Control register
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AMIC_DMA_ISR0 EQU -$6FF8 ; AMIC Interrupt Status register 0
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AMIC_DMA_ISR1 EQU -$6FF6 ; AMIC Interrupt Status register 1
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; AMIC interrupt control register bits
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MACEIE EQU 3 ; Enable ENET interrupt from MACE to AMIC
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ENETIRQ EQU 3 ; Ethernet interrupt asserted
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DMAIRQ EQU 4 ; DMA interrupt asserted
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INTMODE EQU 6 ; AMIC interrupt mode bit
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CPUINT EQU 7 ; AMIC CPU interrupt bit
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; AMIC DMA status register bits
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ERXIRQ EQU 4 ; Ethernet receive DMA interrupt pending
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ETXIRQ EQU 5 ; Ethernet transmit DMA interrupt pending
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;
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; AMIC DMA recv packet status record
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;
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AMIC_DMA_STAT_REC RECORD 0 ; AMIC DMA status record
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RFS0 DS.B 1 ; RCVCNT [7-0] Recv'd message byte count
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RFS1 DS.W 1 ; RCVCNT [11-8] Receive status, recv message byte count
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CmdStat DS.W 1
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ENDR
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; Absolutes
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bufferLogicalBase EQU $61000000 ; DMA buffer logical address
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emulatorOffset EQU $60F40000 ; Emulator's offset D5 ROM
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AMIC_DMA_BASE_REG EQU $50F31000 ; DMA base address register 3 [31:24]
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; •• Temps for the PDM ENET driver ••
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XMIT_BUFF0 EQU $14000 ; Offset from recv buffer start to xmit buff 0
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XMIT_BUFF1 EQU $14800 ; Offset from recv buffer start to xmit buff 1
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XMITSET0 EQU $00 ; Offset for xmit byte count reg 0 HIGH BYTE
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XMITSET1 EQU $10 ; Offset for xmit byte count reg 1 HIGH BYTE
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; Receive register offsets
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AMIC_DMA_RECV_HEAD EQU $1030 ; Receive head pointer [AMIC] √
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AMIC_DMA_RECV_TAIL EQU $1034 ; Receive tail pointer √
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AMIC_DMA_RECV_CNTL EQU $1028 ; Receive DMA Control/Status register
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; Transmit register offsets, 8 bits
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AMIC_DMA_XMIT_CNTL EQU $0C20 ; Transmit DMA channel control/status register offset
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; AMIC XMIT Register offsets - Set 0
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AMIC_DMA_XMIT_BUFF0 EQU $14000 ; Register Set 0 address register
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AMIC_DMA_XMIT_CNT0L EQU $1045 ; Register Set 0 count register LOW
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AMIC_DMA_XMIT_CNT0H EQU $1044 ; Register Set 0 count register HIGH
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; AMIC XMIT Register offsets - Set 1
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AMIC_DMA_XMIT_BUFF1 EQU $14800 ; Register Set 1 address register
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AMIC_DMA_XMIT_CNT1L EQU $1055 ; Register Set 1 count register LOW
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AMIC_DMA_XMIT_CNT1H EQU $1054 ; Register Set 1 count register HIGH
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; AMIC FDC Register offsets
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DMAFloppyBase equ $1060 ; address offset for floppy DMA
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DMAFloppyCount equ $1064 ; count for floppy DMA
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DMAFloppyCS equ $1068 ; DMA control/status for the floppy
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; Test these to see if the xmit reg set is available
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; If = 1, reg buffer is 'empty', set is available
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SET0 EQU 5
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SET1 EQU 6
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AMIC_DMA_BASE_ADDR0 EQU $0003 ; DMA base address register 0 [7:0]
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AMIC_DMA_BASE_ADDR1 EQU $0002 ; DMA base address register 1 [15:8]
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AMIC_DMA_BASE_ADDR2 EQU $0001 ; DMA base address register 2 [23:16]
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AMIC_DMA_BASE_ADDR3 EQU $0000 ; DMA base address register 3 [31:24]
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;
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; DMA interrupt handler selectors bit #s: $50f2a00a ($F…8) | $50f2a008 (7…0)
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;
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hwAmicRXB EQU 0 ; SCC Port B Receive
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hwAmicTXB EQU 1 ; Transmit
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hwAmicRXA EQU 2 ; SCC Port A Receive
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hwAmicTXA EQU 3 ; Transmit
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hwAmicERX EQU 4 ; Ethernet Receive
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hwAmicETX EQU 5 ; Transmit
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hwAmicFDC EQU 6 ; Floppy
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hwAmicUnused EQU 7 ; Unused
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hwAmicSIN EQU 8 ; Sound In
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hwAmicSOUT EQU 9 ; Out
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ddVectCount EQU $A ; # of implemented vectors
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;
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; AMIC Interrupt Dispatcher vector table
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;
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DMADispGlobals RECORD 0, INCREMENT ; (Generic DMA dispatch table)
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ddDMAbase DS.L 1 ; DMA controller's base address
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ddVector0 DS.L 1 ; Source 0 IRQ vector
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ddRefCon0 DS.L 1 ; Source 0 Handler RefCon
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DS.B (ddVectCount-1)*8 ; one for each remaining vector
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SCCLvl4Avector DS.L 1 ; Level 4 SCC port A vector
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SCCLvl4Arefcon DS.L 1 ; Level 4 SCC port A refCon
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SCCLvl4Bvector DS.L 1 ; Level 4 SCC port B vector
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SCCLvl4Brefcon DS.L 1 ; Level 4 SCC port B refCon
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maceVector DS.L 1 ; MACE enet interrupt vector
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maceRefcon DS.L 1 ; MACE enet interrupt refCon
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ddSize EQU * ; size of this record
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ENDR
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;
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; AMIC DMA Channel Register Bit defines
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;
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; DMA Control/Status Register bit offsets
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DMARST EQU 0 ; Soft reset (xmit & rcv)
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DMARUN EQU 1 ; DMA enable (xmit & rcv)
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DMAIE EQU 3 ; DMA Interrupt Enable (xmit & rcv)
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DMADIR EQU 6 ; DMA Direction (SCSI, FDC)
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OVRRUN EQU 6 ; Rcv Head ptr has tried to pass Tail Ptr (ENET)
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DMAIF EQU 7 ; DMA Interrupt Flag (xmit & rcv)
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XMTMSK EQU (1<<DMAIF) ; Transmit AMIC idle mask
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XMTDMA EQU (1<<DMAIF)+(1<<DMAIE)+(1<<DMARUN) ; Transmit AMIC DMA mask
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RCVMSK EQU (1<<DMAIF)+(1<<DMAIE)+(1<<DMARUN) ; Receive AMIC mask
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pageSize EQU $0100 ; Buffer page - garbage bytes - pkt size & status
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wrapTime EQU $BB ; Max buffer limit - 192 x 256 = 49152
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;***** SCSI ******
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kbAMICDirection equ DMADIR
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kbAMICFlush equ 4
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kbAMICRun equ 1
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kbAMICReset equ 0
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kmAMICDirection equ 1<<kbAMICDirection
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kmAMICFlush equ 1<<kbAMICFlush
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kmAMICRun equ 1<<kbAMICRun
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kmAMICReset equ 1<<kbAMICReset
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ENDIF ; __INCLUDINGAMICEQU__
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