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323 lines
13 KiB
Plaintext
323 lines
13 KiB
Plaintext
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; File: SCSIEqu96.a
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;
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; Contains: Equates for dealing with the SCSI 53c96 chip
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;
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; Written by: Jonathan Abilay
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;
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; Copyright: © 1990-1993 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM6> 2/5/93 CSS Rollin from Horror:
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; <H4> 10/17/92 jab Added some definitions required for supporting Messaging
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; correctly in Wombat.
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; <H3> 9/6/92 jab Updated from CubeE and SkyNet for BIOS SCSI.
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; <H2> 6/10/92 BG (Actually JAB) Modification of DREQ equates for SCSI access
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; through BIOS and renamed SCSIx_DAFB to SCSIx_DREQ to reflect
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; that it references the location of the DREQ bit.
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; <SM5> 10/18/92 CCH Added equates for location of SCSI DREQ bit on PDM.
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; <SM2> 7/7/92 CSS Update from Reality:
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; <2> 5/22/92 DTY #1029009 <jab>: Modification of DREQ equates for SCSI access
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; through BIOS and renamed SCSIx_DAFB to SCSIx_DREQ to reflect
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; that it references the location of the DREQ bit.
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; <SM1> 5/22/92 CSS Cyclone roll in.
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; <1> 10/24/91 SAM Rolled in Regatta file.
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;
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; Terror Change History:
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;
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; <7> 6/27/91 BG (actually PDW) Changed various clock conversion factor and
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; Selection Timeout constants to reflect real world values.
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; <6> 6/27/91 djw (actually PDW) Removed non-96 specific stuff and some
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; SCSIBusy/FreeHook stuff. Corrected values for Select timeout.
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; Added Select sequence bits in G_State96 (was G_53c80bits).
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; <5> 6/8/91 BG (actually PDW) Added tsc_cf_stg_XX equates for DAFB state
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; machine initialization.
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; <4> 3/30/91 BG (actually JMA) Added FreeHookPend bit & new values to support
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; various SCSI clks.
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; <3> 2/17/91 BG (actually JMA) Settled on final clkCnvVal & slctTimeout values,
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; also added new selector values and new max value.
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; <2> 1/5/91 BG (actually JMA) More EQUs.
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; <1> 12/7/90 JMA Added to TERROR for the first time.
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;==========================================================================
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mgrVersion2 EQU 2 ; SCSI96 based Manager
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;---------------------------------------------------
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; SCSI 53C96 (ASC) Register Defs, Offsets
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;---------------------------------------------------
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;EVT2/Final
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;SCSI539x1 EQU $50F0F000 ; channel 1--internal
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;SCSI539x2 EQU $50F0F402 ; channel 2--external
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nonSerlzdDisp EQU $040000 ; disp. between serlzd and non-serlzd I/O images <T6> pdw
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; EVT1
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;SCSI539x1 EQU $F9900000 ; channel 1--internal
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;SCSI539x2 EQU $F9900000 ; channel 2--external
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; Turbo SCSI IIci card
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;SCSI539x0 EQU $50F30000 ; channel 1--internal
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;SCSI539x1 EQU $50F31000 ; channel 2--external
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rXCL EQU $00 ; Transfer counter LSB (r/w)
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rXCM EQU $10 ; Transfer counter MSB (r/w)
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rFFO EQU $20 ; FIFO (r/w)
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rCMD EQU $30 ; Command (r/w)
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rCF1 EQU $80 ; Configuration 1 (r/w)
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rCF2 EQU $B0 ; Configuration 2 (r/w)
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rCF3 EQU $C0 ; Configuration 3 (r/w)
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rSTA EQU $40 ; Status (r)
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rINT EQU $50 ; Interrupt (r)
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rSQS EQU $60 ; Sequence Step (r)
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rFOS EQU $70 ; FIFO Flags/Sequence Step (r)
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rDID EQU $40 ; Destination Bus ID (w)
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rSTO EQU $50 ; Select/Reselect Timeout (w)
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rSYP EQU $60 ; Synchronous Period (w)
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rSYO EQU $70 ; Synchronous Offset (w)
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rCKF EQU $90 ; Clock Conversion Factor (w)
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rTST EQU $A0 ; Test (w)
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rRFO EQU $F0 ; Reserve FIFO Byte (w)
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rDMA EQU $100 ; Pseudo-DMA regr (r/w)
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;---------------------------------------------------
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; SCSI 53C96 (ASC) Command Set
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;---------------------------------------------------
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;Note:
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; for NON-DMA mode, bit7=0. DMA mode command bytes have bit7=1.
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cNOP EQU $00 ; NOP command
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cFlshFFO EQU $01 ; flush FIFO command
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cRstSChp EQU $02 ; reset SCSI chip
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cRstSBus EQU $03 ; reset SCSI bus
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cIOXfer EQU $10 ; non-DMA Transfer command
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cCmdComp EQU $11 ; Initiator Command Complete Sequence
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cMsgAcep EQU $12 ; Message Accepted
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cSlctNoAtn EQU $41 ; Select Without ATN Sequence
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cSlctAtn EQU $42 ; Select With ATN Sequence
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cSlctAtnStp EQU $43 ; Select With ATN and Stop Sequence
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cSetAtn EQU $1A ; Set ATN command
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cRstAtn EQU $1B ; Reset ATN command
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cDMAXfer EQU $90 ; DMA Transfer command
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cDMASlctNoAtn EQU $C1 ; Select Without ATN Sequence, use DMA
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cDMASelWOAtn EQU $C1 ; Select Without ATN Sequence, use DMA <H3>
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cDMASelWAtn EQU $C2 ; Select With ATN Sequence, use DMA <H3>
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cDMASelWAtnStp EQU $C3 ; Select With ATN and Stop Sequence, use DMA <H4>
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;---------------------------------------------------
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; SCSI 53C96 (ASC) Bit Defs
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;---------------------------------------------------
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; rINT bits
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bFNC EQU 3 ; function complete bit (intrp regr)
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bBSS EQU 4 ; bus service bit (intrp regr)
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bDSC EQU 5 ; disconnected bit (intrp regr)
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dbFNC EQU bFNC+16 ; shifted 16 bits
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dbBSS EQU bBSS+16 ; shifted 16 bits
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dbDSC EQU bDSC+16 ; shifted 16 bits
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; rSTA bits
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bTRC EQU 4 ; terminal count bit (status regr)
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bINT EQU 7 ; interrupt bit (status regr)
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dbTRC EQU bTRC+16 ; shifted 16 bits
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dbINT EQU bINT+16 ; shifted 16 bits
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; rINT bits
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bINTMode EQU 4 ; SCSI c9x is in initiator mode (rCMD)
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bTRGMode EQU 5 ; SCSI c9x is in target mode (rCMD)
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bDSCMode EQU 6 ; SCSI c9x is in disconnected mode (rCMD)
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bIDENT EQU 7 ; Identify <H4>
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;---------------------------------------------------
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; SCSI 53C96 (ASC) Constants
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;---------------------------------------------------
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iSQSMsk EQU $07 ; sequence bits mask value (rSQS) <T3>
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iSQSMsk2 EQU $E0 ; sequence bits mask value (rFOS) <T3>
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iFOFMsk EQU $1F ; FIFO count mask value (rFOS)
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iCOM EQU $80 ; completion sequence (rFOS)
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iDcBsMsk EQU $30 ; Disconnect & Bus Service mask bits(rINT)
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iDcBsFcMsk EQU iDcBsMsk+$08 ; Disconnect, Bus Service
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; & Function complete mask bits (rINT)
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iDcBsOK EQU $10 ; not discnct + bs
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iBsFcOK EQU iDcBsOk+$08 ; not discnct + bs + fc bits (rINT)
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iFifoSize EQU $10 ; FIFO size in bytes
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iPhaseMsk EQU $07 ; MASK value for phase bits
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iDataOut EQU $00 ; Data-Out SCSI Phase value
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iDataIn EQU $01 ; Data-In SCSI Phase value
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iCommand EQU $02 ; Command Phase value
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iStatus EQU $03 ; Status Phase value
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iMsgOut EQU $06 ; Msg-Out SCSI Phase value
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iMsgIn EQU $07 ; Msg-In SCSI Phase value
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cBDR EQU $0C ; Bus Device Reset Message <H4>
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cABRT EQU $06 ; Abort Command Message <H4>
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cTERM EQU $11 ; Terminate I/O Process Message <H4>
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;---------------------------------------------------
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; For SCSIStat result word
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;---------------------------------------------------
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aPM EQU iPM<<8 ; assert Phase Match
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aATN EQU iATN<<8 ; assert ATN
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;---------------------------------------------------
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; G_State96 Bit defs (bits 0-7 available)
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;---------------------------------------------------
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HandleBusErrs EQU $7 ; Supposed to handle bus errors flag
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SelMsgOut EQU $6 ; We did the Select with ATN thing <H4>
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PendBusFree EQU $5 ; Bus Free should be expected <H4>
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FldFakeSel EQU $6 ; <SM1> CSS we failed select in cmd <P1> pdw
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OurBus EQU $5 ; <SM1> CSS we are initiator on bus <P1> pdw
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FCIntPend EQU $4 ; Functional Complete Intrp pending bit <T6> pdw
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SelInProg EQU $3 ; Select (or Select w/ATN) cmd is executing bit <T6> pdw
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NeedMsgOut EQU $2 ; we expect a msg_out phase that we need to complete the select <T6> pdw
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NeedCmdSent EQU $1 ; we expect a command phase that we need to complete the select <T6> pdw
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FreeHookPend EQU $0 ; Free Hook pending bit %%% old vm stuff %%% <T4>
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;---------------------------------------------------
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; SCSICfg96 defs (bits 31-0 available)
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;---------------------------------------------------
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bQuadraSCSI EQU 0 ; Quadra 700/900/950 SCSI DAFB setup <H3>
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bHasBIOS EQU 1 ; Wombat 20/25/33/40 BIOS SCSI setup <H3>
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;---------------------------------------------------
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; Miscellaneous Constants
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;---------------------------------------------------
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SCSI0_DREQ_BIOS EQU $50F03A00 ; address to access SCSI1 DREQ bit for BIOS access <H1>
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bDREQ_BIOS EQU 0 ; SCSI DREQ status bit for BIOS access <H1>
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SCSI0_DREQ_PDM EQU $50F26003 ; address to access SCSI1 DREQ bit for PDM <SM3>
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bDREQ_PDM EQU 0 ; SCSI DREQ status bit for PDM access <SM3>
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SCSI0_DAFB EQU $F9800024 ; DAFB address to access SCSI1 DREQ bit <T2>
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SCSI1_DAFB EQU $F9800028 ; DAFB address to access SCSI2 DREQ bit <T2>
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bDREQ EQU 9 ; SCSI DREQ status bit <T2>
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;---------------------------------------------------
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; SCSI DAFB Regr Values <T5>
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;---------------------------------------------------
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tsc_cf_stg_25 EQU $1EC ; DAFB state maching config value for 25 MHz CPU <T5>
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tsc_cf_stg_33 EQU $041 ; DAFB state maching config value for 33 MHz CPU <T5>
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;---------------------------------------------------
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; Debug Defs
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;---------------------------------------------------
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overFlow EQU $0 ;
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;---------------------------------------------------
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; 53C96 Regr Values
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;---------------------------------------------------
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;Clock Conversion Values (based on SCSI chip clock - not CPU clock)
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ccf10MHz EQU $02 ; CLK conv factor 10.0Mhz
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ccf10to15MHz EQU $03 ; CLK conv factor 10.01 to 15.0Mhz
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ccf15to20MHz EQU $04 ; CLK conv factor 15.01 to 20.0Mhz
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ccf20to25MHz EQU $05 ; CLK conv factor 20.01 to 25.0Mhz
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ccf25to30MHz EQU $06 ; CLK conv factor 25.01 to 30.0Mhz
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ccf30to35MHz EQU $07 ; CLK conv factor 30.01 to 35.0Mhz <T4>
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ccf35to40MHz EQU $00 ; CLK conv factor 35.01 to 40.0Mhz (0 <- 8) <T4>
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SelTO16Mhz EQU 126 ; ($7e) using the formula: RV (regr value) <T7>
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; 126 = (16MHz * 250mS)/ (7682 * 4) <T7>
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; 250mS is ANSI standard.
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SelTO25Mhz EQU 167 ; ($a7) using the formula: RV (regr value)
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; 163 = (25MHz * 250mS)/ (7682 * 5)
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; 250mS is ANSI standard.
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SelTO33Mhz EQU 167 ; ($a7) using the formula: RV (regr value) <T4> thru next <T4>
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; 153 = (33MHz * 250mS)/ (7682 * 7)
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; 250mS is ANSI standard.
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SelTO40Mhz EQU 167 ; ($a7) using the formula: RV (regr value)
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; 163 = (40MHz * 250mS)/ (7682 * 8)
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; 250mS is ANSI standard. <T4>
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;Configuration 1 Regr bit defs
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SlowCableMode EQU $80 ; Slow Cable Mode enabled bit
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SCSIRstRptIntDis EQU $40 ; SCSI Reset Reporting Intrp Disabled bit
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ParityTestMode EQU $20 ; Parity Test Mode bit
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EnableParity EQU $10 ; Enable Parity Checking bit
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EnableChpTstMd EQU $08 ; Enable Chip Test Mode bit
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myBusID EQU $07 ; My SCSI Bus ID Mask
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;myBusID EQU scDefaultID ; My SCSI Bus ID Mask
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;Configuration 2 Regr bit defs
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RsrvFIFOByte EQU $80 ; Reserve FIFO Byte
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EnablePhsLtch EQU $40 ; Enable Phase Latch
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EnableByteCntl EQU $20 ; Enable Byte Control
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DREQHiZ EQU $10 ; DREQ High Impedance
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SCSI2 EQU $08 ; SCSI-2 Mode
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TrgtBadPrtyAbrt EQU $04 ; Target Bad Parity Abort
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RegrPrtyEn EQU $02 ; Regr Parity Enable
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DMAPrtyEn EQU $01 ; DMA Parity Enable
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;Configuration 3 Regr bit defs
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; bit8-3 are reserved
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SaveRsdlByte EQU $04 ; Save Residual Byte
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AltDMAMode EQU $02 ; Alternate DMA Mode
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Threshold8 EQU $01 ; Threshold 8
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initCF1 EQU SCSIRstRptIntDis + myBusID ; Initial CF1 value: <T6> pdw
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; 1 - slow cable mode enabled
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; 1 - disable intrp to host on bus reset
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; 0 - parity test mode disabled
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; 0 - parity checking disable
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; (ie. do not check parity on incoming data)
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; 0 - chip mode test disabled
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; 0 - use 0 as default myBusID
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initCF2 EQU $00 ; Initial CF2 value:
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; 0 - do not reserve FIFO byte during sync xfer
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; 0 - disable phase latch
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; (Ie. status regr is a live state indicator
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; of SCSI phase lines)
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; 0 - ignore byte control inputs
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; 0 - DACK* is enabled decr the xfer counter
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; 0 - do not use SCSI-2 features
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; 0 - do not abort is parity error is detected
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; 0 - do not flag outgoing parity errs (IO-xfer)
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; 0 - do not flag outgoing parity errs (DMA-xfer)
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initCF3 EQU SaveRsdlByte ; Initial CF3 value: <T6> pdw
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; 1 - do not assert DREQ on residual byte at end of xfer
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; 0 - disable alterante DMA mode
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; 0 - disable threshold 8 mode
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asyncXfer EQU $0 ; Asynchronous Data Transfer = 0 Synch Offset value
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; a non-zero value indicates Synch data xfer
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initOp EQU asyncXfer ; use this operation
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clkCnvVal EQU ccf20to25MHz ; use this clock conversion factor <T3>
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slctTimeout EQU SelTO25Mhz ; use this Select timeout value <T3>
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