mirror of
https://github.com/elliotnunn/sys7.1-doc-wip.git
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275 lines
11 KiB
Plaintext
275 lines
11 KiB
Plaintext
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;==========================================================================
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;
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; File: SCSIEqu53c96.a
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;
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; Contains: Equates for dealing with the SCSI 53c96 chip
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;
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; Written by: Jonathan Abilay/Paul Wolf
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;
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; Copyright: © 1990-1993 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM16> 10/14/93 pdw <MC> roll-in.
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; <MC3> 10/12/93 pdw Added support for Synchronous data transfers, rewrote State
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; Machine, message handling etc.
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; <MC2> 9/16/93 pdw Tailoring the Select timeout values for 20 and 40MHz clock
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; speeds to about 200mS instead of 250mS to see if anybody
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; complains.
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; <SM15> 9/9/93 pdw Lots of little changes. Name changes, temporary cache_bug
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; stuff.
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; <SM14> 7/17/93 pdw Changed tc bit to bTermCnt (I think).
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; <SM13> 6/29/93 pdw Massive checkins: Change asynchronicity mechanism to CallMachine
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; stack switching mechanism. Adding support for Cold Fusion.
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; Rearranging HW/SW Init code. Some code optimizations.
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; <SM12> 5/25/93 DCB Rollin from Ludwig. (The next item below)
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; <LW5> 5/21/93 PW Adding target mode commands so that we can respond to a select
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; without toasting the bus.
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; <SM11> 5/5/93 PW Converted names to meanies-friendly names. Updated with latest
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; from Ludwig stuff.
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; <LW3> 3/26/93 PW Removed initCFx values.
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; <SM9> 1/31/93 PW Update from the latest of Ludwig. Also changes required for PDM
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; (will update Ludwig with these as needed myself).
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; <LW2> 1/27/93 PW Once again, added mSCSIRstRptIntDis to CF1.
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; <SM8> 12/5/92 PW Got rid of confusing and worthless iDcBsxx stuff.
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; <SM7> 11/17/92 DCB Changed initCF1: added mSCSIRstRptIntDis to disable interrupt on
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; reset until we figure out what's going on.
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; <SM6> 11/12/92 PW Rearranged a bit more logically and put 'm's in front of masks
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; and added some more stuff. Removed parityEnable.
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; <SM5> 10/30/92 DCB Changed some flags for to support changes to the interrupt
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; handling routines
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; <SM4> 10/8/92 PW Added bit definitions for status register.
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; <SM3> 8/31/92 PW Added vowels. Changed FFO to FIFO, Flsh to Flush, Rst to Reset,
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; S to SCSI, Chp to Chip, Acep to Accept, rFOS to rFIFOflags.
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; <SM2> 8/30/92 PW Added cDMASelWAtn3 and cSelWAtn3 commands to equates.
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; <SM1> - PW Initial check-in.
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;
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;==========================================================================
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IF &TYPE('__INCLUDING_SCSIEqu53c96__') = 'UNDEFINED' THEN
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__INCLUDING_SCSIEqu53c96__ SET 1
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;---------------------------------------------------
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; SCSI 53C96 Command Set
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;---------------------------------------------------
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;Note:
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; for NON-DMA mode, bit7=0. DMA mode command bytes have bit7=1.
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cNOP EQU $00 ; NOP command
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cFlushFIFO EQU $01 ; flush FIFO command <SM3> pdw
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cResetChip EQU $02 ; reset SCSI chip <SM3> pdw
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cResetSCSIBus EQU $03 ; reset SCSI bus <SM3> pdw
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cIOXfer EQU $10 ; non-DMA Transfer command
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cCmdComplete EQU $11 ; Initiator Command Complete Sequence <SM3> pdw
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cMsgAccept EQU $12 ; Message Accepted <SM3> pdw
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cSendMsg EQU $20 ; Send Message byte(s)
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cSendStatus EQU $21 ; Send status byte
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cSendData EQU $22 ; Send data byte(s)
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cDisconnectSeq EQU $23 ; Send 2 msg bytes and disconnect
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cTerminateSeq EQU $24 ; Send status byte, message byte then disconnect
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cTgtCmdComplete EQU $25 ; Send status byte, message byte DON'T disconnect
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cDisconnect EQU $27 ; Disconnect (drop busy)
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cRcvMsgSeq EQU $28 ; Receive Message byte(s)
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cRcvCmd EQU $29 ; Receive command byte(s) (specified count)
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cRcvData EQU $2a ; Receive data byte(s)
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cRcvCmdSeq EQU $29 ; Receive command byte(s) (decoded count)
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cStopDMA EQU $04 ; stop DMA
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cSelWOAtn EQU $41 ; Select Without ATN Sequence
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cSelWAtn EQU $42 ; Select With ATN Sequence
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cSelWAtnStop EQU $43 ; Select With ATN and Stop Sequence <SM3> pdw
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cSelWAtn3 EQU $46 ; Select With ATN 3 (msg_out bytes) Sequence <SM2> pdw
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cEnableR_sel EQU $44 ; Enable (re)selection
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cSetAtn EQU $1A ; Set ATN command
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cRstAtn EQU $1B ; Reset ATN command
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cDMAXfer EQU $90 ; DMA Transfer command
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cDMASelWOAtn EQU $C1 ; Select Without ATN Sequence, use DMA
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cDMASelWAtn EQU $C2 ; Select With ATN Sequence, use DMA
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cDMASelWAtnStop EQU $C3 ; Select With ATN and Stop Sequence <SM3> pdw
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cDMASelWAtn3 EQU $C6 ; Select With ATN 3 (msg_out bytes) Sequence <SM2> pdw
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;---------------------------------------------------
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; SCSI 53C96 Register Defs, Offsets
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;---------------------------------------------------
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nonSerlzdDisp EQU $040000 ; disp. between serlzd and non-serlzd I/O images
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rXCL EQU $00 ; Transfer count bits 0-7 (r/w)
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rXCM EQU $10 ; Transfer count bits 8-15 (r/w)
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rFIFO EQU $20 ; FIFO (r/w)
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rCMD EQU $30 ; Command (r/w)
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rCF1 EQU $80 ; Configuration 1 (w)
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rCF2 EQU $B0 ; Configuration 2 (w)
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rCF3 EQU $C0 ; Configuration 3 (w)
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rSTA EQU $40 ; Status (r)
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rINT EQU $50 ; Interrupt (r)
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rSQS EQU $60 ; Sequence Step (r)
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rFIFOflags EQU $70 ; FIFO Flags/Sequence Step (r)
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rDID EQU $40 ; Destination Bus ID (w)
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rSTO EQU $50 ; Select/Reselect Timeout (w)
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rSyncPeriod EQU $60 ; Synchronous Period (w)
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rSyncOffset EQU $70 ; Synchronous Offset (w)
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rCKF EQU $90 ; Clock Conversion Factor (w)
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rTST EQU $A0 ; Test (w)
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rXCH EQU $E0 ; Transfer count bits 16-24 (r/w)
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rChipID EQU rXCH ; Chip ID register (r)
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rFIFObtm EQU $F0 ; Reserve FIFO Byte (w)
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rDMA EQU $100 ; Pseudo-DMA regr (r/w)
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;————————————————————————————————————————————————————
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; SCSI 53C96 Bit Defs
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;————————————————————————————————————————————————————
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;———— Interrupt Register (rINT) bits ————
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bSelected EQU 0 ; selected interrupt
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bSelectedWAtn EQU 1 ; selected w/atn interrupt
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bReselected EQU 2 ; reselected interrupt
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bFuncComplete EQU 3 ; function complete bit
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bBusService EQU 4 ; bus service bit
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bDisconnected EQU 5 ; disconnected bit
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bIllegalCmd EQU 6 ; illegal command interrupt
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bResetDetected EQU 7 ; SCSI reset detected interrupt
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;……… masks ………
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mSelected EQU 1<<bSelected
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mSelectedWAtn EQU 1<<bSelectedWAtn
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mReselected EQU 1<<bReselected
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mFuncComplete EQU 1<<bFuncComplete
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mBusService EQU 1<<bBusService
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mDisconnected EQU 1<<bDisconnected
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mIllegalCmd EQU 1<<bIllegalCmd
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mResetDetected EQU 1<<bResetDetected
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mNonNormalInt EQU mIllegalCmd + mReselected + mSelected + mSelectedWAtn + mResetDetected
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;———— Status Register (rSTA) bits ————
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bCmdXferComp EQU 3 ; Gross Error
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bTermCount EQU 4 ; terminal count
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bParityError EQU 5 ; Parity Error
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bGrossError EQU 6 ; Gross Error
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bINT EQU 7 ; interrupt
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iPhaseMsk EQU $07 ; MASK value for phase bits
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;———— Command Register (rCMD) bits ————
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bINTMode EQU 4 ; initiator mode command
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bTRGMode EQU 5 ; target mode command
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bDSCMode EQU 6 ; disconnected mode command
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;———— Configuration 1 Register (rCF1) bits ————
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mCF1_SlowCableMode EQU $80 ; Slow Cable Mode enabled bit
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mCF1_ResetIntrpDisable EQU $40 ; SCSI Reset Reporting Intrp Disabled bit <SM7>
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mCF1_ParityTestMode EQU $20 ; Parity Test Mode bit
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mCF1_EnableParity EQU $10 ; Enable Parity Checking bit
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mCF1_ChipTestMode EQU $08 ; Enable Chip Test Mode bit
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mCF1_MyBusID EQU $07 ; My SCSI Bus ID Mask
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;———— Configuration 2 Register (rCF2) bits ————
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mCF2_ReserveFIFOByte EQU $80 ; Reserve FIFO Byte
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mCF2_FeaturesEnable EQU $40 ; Enable Phase Latch
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; 53F96: turns on 24bit xfer count also
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mCF2_EnableByteControl EQU $20 ; Enable Byte Control
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mCF2_DREQHiZ EQU $10 ; DREQ High Impedance
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mCF2_SCSI2 EQU $08 ; SCSI-2 Mode
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mCF2_TgtBadParityAbort EQU $04 ; Target Bad Parity Abort
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mCF2_RegisterParity EQU $02 ; Regr Parity Enable
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mCF2_DMAParity EQU $01 ; DMA Parity Enable
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;———— Configuration 3 Register (rCF3) bits ————
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mCF3_FastSCSI EQU $10 ; set if rate>5MB/s
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mCF3_FastClock EQU $08 ; set if clock = 40MHz
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mCF3_SaveResidual EQU $04 ; Save Residual Byte
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mCF3_AltDMAMode EQU $02 ; Alternate DMA Mode
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mCF3_Threshold8 EQU $01 ; Threshold 8
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;———— Other Register bits ————
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mSQSMsk EQU $07 ; sequence bits mask value (rSQS)
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mFIFOCount EQU $1F ; FIFO count mask value (rFOS)
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mSyncOffset EQU $0F ; synchronous offset bits (rSYO)
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mSyncPeriod EQU $1F ; synchronous period bits (rSYP)
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;---------------------------------------------------
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; Miscellaneous Constants
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;---------------------------------------------------
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iFifoSize EQU $10 ; FIFO size in bytes
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;---------------------------------------------------
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; 53c96 Register Values
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;---------------------------------------------------
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;————— Phase values (for iPhaseMsk bits in rSTA) —————
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iDataOut EQU $00 ; Data-Out SCSI Phase value
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iDataIn EQU $01 ; Data-In SCSI Phase value
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iCommand EQU $02 ; Command Phase value
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iStatus EQU $03 ; Status Phase value
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iMsgOut EQU $06 ; Msg-Out SCSI Phase value
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iMsgIn EQU $07 ; Msg-In SCSI Phase value
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;————— Clock Conversion Values (based on SCSI chip clock - not CPU clock) —————
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ccf10MHz EQU $02 ; CLK conv factor 10.0Mhz
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ccf11to15MHz EQU $03 ; CLK conv factor 10.01 to 15.0Mhz
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ccf16to20MHz EQU $04 ; CLK conv factor 15.01 to 20.0Mhz
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ccf21to25MHz EQU $05 ; CLK conv factor 20.01 to 25.0Mhz
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ccf26to30MHz EQU $06 ; CLK conv factor 25.01 to 30.0Mhz
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ccf31to35MHz EQU $07 ; CLK conv factor 30.01 to 35.0Mhz
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ccf36to40MHz EQU $00 ; CLK conv factor 35.01 to 40.0Mhz (0 := 8)
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SelTO16Mhz EQU 126 ; ($7e) using the formula: RV (regr value)
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; 126 = (16MHz * 250mS)/ (7682 * 4)
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; 250mS is ANSI standard.
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SelTO20Mhz EQU 132;160 ; ($) using the formula: RV (regr value)
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; 162 = (20MHz * 250mS)/ (7682 * 4)
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; 250mS is ANSI standard.
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SelTO25Mhz EQU 167 ; ($a7) using the formula: RV (regr value)
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; 163 = (25MHz * 250mS)/ (7682 * 5)
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; 250mS is ANSI standard.
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SelTO33Mhz EQU 167 ; ($a7) using the formula: RV (regr value)
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; 153 = (33MHz * 250mS)/ (7682 * 7)
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; 250mS is ANSI standard.
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SelTO40Mhz EQU 132;160 ; ($a7) using the formula: RV (regr value)
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; 163 = (40MHz * 250mS)/ (7682 * 8)
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; 250mS is ANSI standard.
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; <SM5>
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;————— Values to use —————
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asyncXfer EQU $0 ; Asynchronous Data Transfer = 0 Synch Offset value
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; a non-zero value indicates Synch data xfer
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initOp EQU asyncXfer ; use this operation
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;---------------------------------------------------
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; SCSI DAFB Register Information
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;---------------------------------------------------
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SCSI0_DAFB EQU $F9800024 ; DAFB address to access SCSI1 DREQ bit
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SCSI1_DAFB EQU $F9800028 ; DAFB address to access SCSI2 DREQ bit
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bDREQ EQU 9 ; SCSI DREQ status bit
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tsc_cf_stg_25 EQU $1EC ; DAFB state maching config value for 25 MHz CPU
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tsc_cf_stg_33 EQU $041 ; DAFB state maching config value for 33 MHz CPU
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ENDIF ; already included...
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