diff --git a/DeclData/DeclData.make b/DeclData/DeclData.make new file mode 100644 index 0000000..027f487 --- /dev/null +++ b/DeclData/DeclData.make @@ -0,0 +1,138 @@ +# +# File DeclData.make +# +# Contains: Makefile for Declaration ROM. +# +# Written by: Kurt Clark, Chas Spillar, and Tim Nichols +# +# Copyright: © 1992-1993 by Apple Computer, Inc., all rights reserved. +# +# Change History (most recent first): +# +# 12/13/93 PN Roll in Kaos and Horrors code to support AJ and Malcom machines. +# 9/9/93 pdw Added slots.a to dependencies. +# 08-03-93 jmp Added various necessary dependencies that weren’t previously +# spelled out. +# 3/4/93 dwc Added DeclDataPDMMace definition for PDM ENET. +# <1> 2/21/93 kc first checked in +# 12-04-92 jmp Added the rules for building VSC (Keystone) DeclData. + +EthernetDir = {DeclDir}DeclNet: +SonicDir = {EthernetDir}Sonic: +MaceDir = {EthernetDir}Mace: +VideoDir = {DeclDir}DeclVideo: +GammaDir = {VideoDir}Gamma: +PDMMaceDir = {MaceDir}PDMMaceEnet: + +#include {MaceDir}Mace.Make +#include {SonicDir}Sonic.Make +#include {VideoDir}VideoDrivers.Make +#include {PDMMaceDir}PDMEnet.Make + +DeclResources = "{RsrcDir}DeclData.rsrc" ∂ + "{RsrcDir}PrimaryInit.rsrc" ∂ + "{RsrcDir}SecondaryInit.rsrc" ∂ + "{RsrcDir}SuperInit.rsrc" ∂ + "{RsrcDir}DeclDataMace.rsrc" ∂ + "{RsrcDir}DeclDataPDMMace.rsrc" ∂ + "{RsrcDir}DeclDataSonic.rsrc" ∂ + "{RsrcDir}DeclDataVideo.rsrc" ∂ + "{RsrcDir}Gamma.rsrc" + +DeclHeaders = "{ObjDir}StandardEqu.d" ∂ + "{AIncludes}GestaltEqu.a" ∂ + "{AIncludes}ShutDown.a" ∂ + "{AIncludes}ROMEqu.a" ∂ + "{AIncludes}Video.a" ∂ + "{IntAIncludes}DockingEqu.a" ∂ + "{IntAIncludes}EgretEqu.a" ∂ + "{IntAIncludes}GestaltPrivateEqu.a" ∂ + "{IntAIncludes}HardwarePrivateEqu.a" ∂ + "{IntAIncludes}IOPrimitiveEqu.a" ∂ + "{IntAIncludes}PowerPrivEqu.a" ∂ + "{AIncludes}Slots.a" ∂ + "{IntAIncludes}SlotMgrEqu.a" ∂ + "{IntAIncludes}UniversalEqu.a" ∂ + "{IntAIncludes}DepVideoEqu.a" ∂ + "{SonicDir}SonicEqu.a" + +# +# DeclData +# +"{RsrcDir}DeclData" ƒ {DeclResources} "{RsrcDir}RomLink" + "{RsrcDir}RomLink" {DeclResources} -o "{Targ}" + + +"{RsrcDir}DeclData.rsrc" ƒ "{RIncludes}Types.r" ∂ + "{IntRIncludes}DepVideoEqu.r" ∂ + "{IntRIncludes}HardwarePrivateEqu.r" ∂ + "{IntRIncludes}InternalOnlyEqu.r" ∂ + "{IntRIncludes}QuickDraw.r" ∂ + "{IntRIncludes}ROMLink.r" ∂ + "{DeclDir}DeclData.r" + Rez {StdROpts} "{DeclDir}DeclData.r" -o "{Targ}" + + +# The ROMLinkHeaderBuilder tool is not used. +#"{IntRIncludes}ROMLink.r" ƒ "{RsrcDir}ROMLinkHeaderBuilder" +# "{RsrcDir}ROMLinkHeaderBuilder" > {Targ} #This is kinky + + +# +# PrimaryInit +# +"{RsrcDir}PrimaryInit.rsrc" ƒ "{ObjDir}PrimaryInit.a.o" + Link {StdLOpts} {StdAlign} -rt decl=200 "{ObjDir}PrimaryInit.a.o" -o "{Targ}" + + +"{ObjDir}PrimaryInit.a.o" ƒ "{DeclDir}PrimaryInit.a" ∂ + {DeclHeaders} + Asm {StdAOpts} -d ForEclipseROM=0,sonic32=1,ctlpad=0,mmu=1 -i "{SonicDir}" "{DeclDir}PrimaryInit.a" -o "{Targ}" + + +# +# SecondaryInit +# +"{RsrcDir}SecondaryInit.rsrc" ƒ "{ObjDir}SecondaryInit.a.o" + Link {StdLOpts} {StdAlign} -rt decl=210 "{ObjDir}SecondaryInit.a.o" -o "{Targ}" + + +"{ObjDir}SecondaryInit.a.o" ƒ "{DeclDir}SecondaryInit.a" ∂ + {DeclHeaders} + Asm {StdAOpts} -d ForEclipseROM=0,sonic32=1,ctlpad=0,mmu=1 -i "{SonicDir}" "{DeclDir}SecondaryInit.a" -o "{Targ}" + +# +# SuperInit +# + +"{RsrcDir}SuperInit.rsrc" ƒ "{ObjDir}SuperInit.a.o" + Link {StdLOpts} {StdAlign} -rt decl=220 "{ObjDir}SuperInit.a.o" -o "{Targ}" + + +"{ObjDir}SuperInit.a.o" ƒ "{DeclDir}SuperInit.a" ∂ + {DeclHeaders} + Asm {StdAOpts} -d ForEclipseROM=0,sonic32=1,ctlpad=0,mmu=1 -i "{SonicDir}" "{DeclDir}SuperInit.a" -o "{Targ}" + +# +# Ethernet +# + +"{ObjDir}Loopback.c.o" ƒ "{EthernetDir}Loopback.c" ∂ + "{CIncludes}TextUtils.h" ∂ + "{CIncludes}Memory.h" ∂ + "{CIncludes}Devices.h" ∂ + "{CIncludes}Files.h" ∂ + "{CIncludes}AppleTalk.h" ∂ + "{CIncludes}OSUtils.h" + C {StdCOpts} -b -o "{Targ}" "{EthernetDir}Loopback.c" + +# +# Gamma Resource +# + +"{RsrcDir}Gamma.rsrc" ƒ "{RIncludes}Types.r" ∂ + "{IntRIncludes}ROMLink.r" ∂ + "{GammaDir}Gamma.r" + Rez {StdROpts} "{GammaDir}Gamma.r" -o "{Targ}" + + diff --git a/DeclData/DeclData.make.idump b/DeclData/DeclData.make.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclData.make.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclData.make.rdump b/DeclData/DeclData.make.rdump new file mode 100644 index 0000000..aedf93d --- /dev/null +++ b/DeclData/DeclData.make.rdump @@ -0,0 +1,27 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0009 4765 6F72 6765" /* ..Monaco..George */ + $"2044 2E20 5769 6C73 6F6E 204A 722E 0D23" /* D. Wilson Jr..# */ + $"0D23 0006 0004 0029 0007 035A 023E 0029" /* .#.....)...Z.>.) */ + $"0007 035A 023E A931 9AE4 0000 00F1 0000" /* ...Z.>.1........ */ + $"014A 0000 0000 0100" /* .J...... */ +}; + +data 'MPSR' (1008) { + $"0029 0007 035A 023E 0029 0007 035A 023E" /* .)...Z.>.)...Z.> */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"5AB1 8B8D 3FE5 3230 0004 0000 0000 0000" /* Z...?.20........ */ + $"0000 A933 7389 A933 7389 A6F7 9FDC 0074" /* ...3s..3s......t */ + $"C2F0 0000 0006 0007 1853 7570 6572 4D61" /* .........SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA00 0E43 6872 6973 2050 6574 6572 7365" /* ...Chris Peterse */ + $"6E00 0135 000D 4465 636C 4461 7461 2E6D" /* n..5..DeclData.m */ + $"616B 6500 0000 0040 526F 6C6C 2069 6E20" /* ake....@Roll in */ + $"4B61 6F73 2061 6E64 2048 6F72 726F 7273" /* Kaos and Horrors */ + $"2063 6F64 6520 746F 2073 7570 706F 7274" /* code to support */ + $"2041 4A20 616E 6420 4D61 6C63 6F6D 206D" /* AJ and Malcom m */ + $"6163 6869 6E65 732E 00" /* achines.. */ +}; + diff --git a/DeclData/DeclData.r b/DeclData/DeclData.r new file mode 100644 index 0000000..6cef9ad --- /dev/null +++ b/DeclData/DeclData.r @@ -0,0 +1,9518 @@ +/* + File: DeclData.r + + Contains: Shared resource declarations for DeclData components. + + Copyright: © 1989-1994 by Apple Computer, Inc., all rights reserved. + + Change History (most recent first): + + 1/20/94 PN Remove the remaining slot resource types "_CPUMac20" to fix DAFB + video display. + 1/4/94 PN Add the rest of support for more CSC panels from KAOS. + 12/14/93 PN Obsolete the CPUMac020 resources. + 11/10/93 fau Update from SuperMunggio . + 10/27/93 fau Added the ATIDir to the SuperDirectory. + 11/9/93 KW added some srsrc's for stp machines + 08-16-93 jmp Eliminated an extraneous Wombat/WLCD board sRsrc entry. + 8/12/93 KW adding two more smurf wombats + 8/11/93 KW adding some srsrc for a few more smurf machines + 08-06-93 jmp Added to the list of timinginfo constants, which is not complete + yet, but is good enough for the Sonora/PDM support. + 08-03-93 jmp Updated the copyright notice and changed the various display + name strings to the new resolution/vertical refresh rate format + (i.e., the original Apple display names no longer make sense -- + too many share the same sense codes). + <18> 6/1/93 IH Add timing info for video modes + 4/5/93 chp Synchronize with Ludwig. + 04-01-93 jmp Removed the reference to SuperMario (SM) in the VendorInfo. + 3/9/93 jmp Updated the rev-level to reflect the fact that SuperMario is + different from Ludwig. + 3/8/93 fau Changed the SCSITransport DrHw field to be the board resource + for Cyclone, for lack of a better number. + 3/1/93 DCB Changed typSIM to typeXPT for the transport sRsrc. + 2/24/93 fau Added a sRsrc for the SCSI Transport, as well as typ and cstr + entries for it. + 2/16/93 fau Changed the name of the HRNTSC names to 512x384/640x480/768x576. + 01-12-93 jmp Added initial support for CSC. + 01-11-93 jmp Compacted the DBLite/Dart video data to now match what’s in + HORROR. + 01-07-93 jmp Added a VideoNames directory for V8-based built-in video. + 12/23/92 RC Added support for running Smurf on Wombat (boxRiscWombat) + 12-10-92 jmp Fixed the DAFB Two-Page and 21" Color Display 8bpp entries for + Brooktree CLUT/DAC CPUs (i.e., production Quadra 700/900). The + TimingAdj value was off by one. + 11/2/92 kc Change ObjDir to RsrcDir + 10-29-92 jmp Added support for 33 MHz WLCD. + 10/26/92 HY Added support for LC II boxflag. Defined sRsrc_BdLCII. + 10/19/92 RB Removed more video resources from the LC II (1 Meg) ROM build + for the LC930 + 10-17-92 jmp Needed to the change the 'decl' IDs of various externally + referenced components. + 10/14/92 RB When building for a 1 Meg LC930 ROM, exclude unused components. + 10/8/92 fau Added separate 2bpp/8bpp parameter structures for Civic-based + CPU's. + 10/6/92 GDW Fixed missing text. + 10/6/92 GDW New location for ROMLink tool. + +*/ +// 8/20/92 AK Removed last part of format block (starting with Rom Length Size.) +// SMRomImage.r now supplies this. This is a test for ROMLink. +// 8/9/92 CCH Added video support for Quadras with RISC cards. +// 7/29/92 fau Fixed bug in the Civic vidParams for the full-page displays, +// where I forgot to take the base address out of the data +// structure. Update the Endeavor M,N and clock select on the +// Goldfish and Full page displays to use lower M,N. This got rid +// of the jitter on EVT3 on those displays. Also updated the 2pg +// monitors to lower M,N values. +// 7/28/92 fau Updated PAL Convolution parameters to be exactly 4x the +// non-convolved and moved the base to 4096 (from 2048) -- even +// though 'cause of a bug in Civic, PALConv won't work at 25MHz. +// Because of that, changed the equivalent PAL spID's for switching +// between RGB Syncs and PAL Composite syncs to the non-convolved +// parameters. Added equivalent spID's for NTSC/PAL composite +// syncs to all vidparams that needed them. Adjusted the serration +// timing on PAL and some of the vertical timings on NTSC and PAL +// per the hardware guy (L. Thompson), so that they meet the CCIR +// spec. Change the name of the equivalent modes from +// Under/Overscan to 512x384 et.al. +// 07-14-92 jmp (SWC,H47) Changed the ctSeed for the 1-, 2-, and 4-bit fixed +// CLUTs used for the grayscale LCDs to help fix a QuickDraw bug. +// InitGDevice calls GetDevPixMap to fill in the device's PixMap, +// including its CLUT. For fixed devices, it then generates a new +// ctSeed, which causes problems in IconUtilities because the LCD's +// CLUT doesn't match the current display mode/depth. +// (djw,H46) Add sVidAttribute flag to indicate a "built-in" +// display (fBuiltInDisplay) on all applicable video sRsrc's. +// (jmp,H45) Added in support to make the DAFB-related DeclData +// work correctly among Spike, Eclipse, Zydeco, and all Wombat/WLCD +// CPUs. +// (jmp,H44) Added support for PAL and NTSC on Wombat. +// (jmp,H43) Adjusted a number of the DAFBVidParams to be more +// compatible with Wombat. (In doing this, I have temporarily +// caused some aesthetically unpleasing artifacts to occur on +// Spike/Eclipse/Zydeco, but I will fix these problems shortly.) +// (jmp,H42) Added first-pass support for the Wombat version of +// DAFB (i.e., add the NSC-8534 clock chip params to the supported +// progressive scan displays; interlaced displays to follow soon). +// 7/7/92 fau Moved sRsrc_BdWombat20 to the correct location in the resource +// directory, since the boxflagWombat20 moved from 29 to 52. +// Corrected some problems in the DAFB video parameters entries +// that happenned at the roll-in. +// 6/26/92 fau Changed HSERR parameter on Civic Interlaced displays (to 1/2 of +// original value). Change clock timing for PAL displays in Civic +// to a 14.78MHz dot clock per Eric Baden and Larry Thompson +// request (that is the correct timing, not 14.75). Added +// composite out support for 12" and 13" displays. +// 6/22/92 mal changed label decldataethernet to decldatasonic +// 6/20/92 ejb Removed all trace of BOMII DSP3210 Driver from DeclData. Its +// now going to be just a regular ROM resource like the RTMgr. +// 6/19/92 KW (fau,P28) Added support for GoldFish displays switching to +// composite out. Kludgy, but will go away when we implement a +// dynamic desktop. RSN... +// 6/18/92 KW (jmp,H41) Eliminated yet even more of the old DAFBVidParams +// fields. +// (jmp,H39) Tweaked the 15.6672 MHz Omega-2’s P value from +// previous check-in. +// (jmp,H38) Updated the SonoraVidParams for the Omega-2. +// (fau,P26) Added video-in configurations for Vesuvio, Kong, +// Rubik, 19" Display and all VGA families for Civic-based CPU's. +// 6/18/92 RB Changed the entry of the DSP driver (ATT3210) so it won't get +// opened automatically at PrimaryInit time. The current DSP driver +// breaks on Cyclone EVT2. +// 6/4/92 KW (jmp,H37) Fixed a few minor typos that prevented some displays +// form working correctly on REAL Quadra 900/700s (i.e., ones that +// have Brooktree DACs). (jmp,H36) Compacted the DAFB vidParam +// tables. (djw,H35) Added secondaryInit to board sRsrc for DBLite +// and Dartanian. (BG,H34) Changed various Wombat-style BoxFlag +// references to their new, more descriptive names. (jmp,H33) +// Eliminated support for the no-vRAM case in V8-based systems. +// (jmp,H32) Changed the “sRsrcZydecoDir” name to the more generic +// “sRsrcBFBasedDir” (BF=BoxFlag) name. (jmp,H31) Changed the +// hard-coded values in my last check-in into equates. (jmp,H30) +// Added real MinorBaseOffsets for the V8-based sResources. +// (jmp,H29) Just added the SecondaryInit entry to Wombat board +// sRsrc. (jmp,H28) Took a lot of “air” out of this file by +// combining lots of tables that are exactly the same except for +// their names. Also, conditionally dropped support for Apollo, +// since this ROM can’t do it anyway. Conditionally removed the +// checksumming. (jmp,H26) Did a couple of things for the +// Sonora-based CPUs: 1) Added a 640x400 mode for the HiRes +// display, and 2) fixed a problem in the GoldFish 256K of vRAM +// configuration where only 2bpp is possible but I supporting upto +// 4bpp. +// 5/21/92 RB Making changes for Cyclone. Moved some changes from Pandora. It +// seems like Mike should look at this file because Pandora is out +// of Zync with Horror in Sonora (today). Changed 'The SuperMario +// ROM' to 'The SM ROM' NEVER have someone else's copyright in ROM +// !!! +// 5/16/92 kc Roll in Horror and Zydeco Changes. Comments follow: +// 4/21/92 SWC Added INCLUDE of PowerPrivEqu.a for PrimaryInit.a. +// 04/20/92 jmp Did a couple of things for the Sonora-based CPUs: 1) Added a +// 640x400 mode for the HiRes display, and 2) fixed a problem in +// the GoldFish 256K of vRAM configuration where only 2bpp is +// possible but I supporting upto 4bpp. +// 3/17/92 SWC Renamed boxDBLite->boxDBLite25 and boxDBLiteLC->boxDBLite33, and +// added boxDBLite16 and boxDBLite20 to the lists. +// 3/6/92 SWC Added DockingEqu.a to the INCLUDEs list. +// 02/19/92 jmp Changed all the Condor references to Wombat. +// 01/30/92 jmp Fixed a couple of typo’s I introduced in . +// 01/29/92 jmp (jmp,Z27) Added two new INCLUDES for GestaltEqu.a and +// GestaltPrivateEqu.a for the SecondaryInit System fixes. +// 01/27/92 jmp (BG,Z26) Added an INCLUDE for IOPrimitiveEqu.a for +// SecondaryInit.a. Also, cleaned up the vidAttributes fields on +// the LCD-based sRsrcs. +// 01/22/92 jmp (jmp,Z25) Added SecondaryInit entries for Spike & Eclipse as +// well as for Zydeco. +// (jmp,Z24) Added an include for ShutDownEqu.a. +// 01/14/92 jmp Fixed a problem I introduced during my last check-in (I inserted +// the RdTPD DAFB vidParams in front of the 19x vidParams, and it +// should have been the other way around). +// 01/11/92 jmp Added rudimentary support for the newly-defined extended sense +// codes. +// 01/07/92 jmp Updated the Brooktree-DAC Timing Adjust value in the Kong and +// Vesuvio DAFB vidParams due to change below. +// 12/19/91 jmp Added the initial support for Rubik-560 mode for Sonora. +// 12/17/91 jmp Updated the Kong/Vesuvio, GoldFish, SuperVGA, and PAL +// non-convolved tables so that all depths within each +// configuration share a common base address. Also, tweaked the +// 19" Display parameters to generate a 60.2 KHz clock rather than +// a 59.9 KHz clock. +// 12/16/91 HJR Added support for Dartanian. +// 12/12/91 jmp Added in the rest of the Sonora initial support. +// 11/27/91 jmp Started adding support for Sonora. +// 11/26/91 jmp Added support for a 640x480 LCD screen as well as 640x400 LCD +// screen. +// 11/25/91 jmp Moved the DAFB vidParams from the functional sRrsrcs to the +// board sRsrcs -- this significantly reduced the size of this +// file! +// 11/12/91 jmp Added the “Mac Std Gamma” table to the VGA and SVGA sRsrcs as +// requested by MacDTS. +// 11/05/91 jmp Added preliminary support for 19" Displays for DAFB-based CPUs. +//
11/01/91 jmp We now have two DBLite functional sRsrcs. One is for the +// developmental black/white-only LCD displays (controller), while +// the other is for the grayscale LCD controller. Currently, only +// the black/white sRsrc is used. +//
10/31/91 jmp Marketing (Ross Ely) finally admitted that defaulting to the +// 6500°K gamma table for Vesuvio & GoldFish was a bad idea, so I +// am now defaulting to the 9300°K gamma table on those displays. +// Yeah! +// <4> 10/29/91 jmp Added the initial support for super sRsrc directories. +// <3> 10/24/91 jmp Added the gray-scale (thru 4bpp) mVidParams for DB-Lite and +// updated the Horror ROM VendorInfo sRsrc. +// <2> 10/24/91 jmp Updating to Zydeco-TERROR version. +// ——————————————————————————————————————————————————————————————————————————————————————— +// Pre-Horror ROM comments begin here. +// ——————————————————————————————————————————————————————————————————————————————————————— +// <3> 3/31/92 JSM Rolled this file into Reality. +// <2> 2/11/92 RB Need to include ROMPrivateEqu.a and align a few labels to avoid +// warnings. +// <26> 1/22/92 BG Added an INCLUDE for IOPrimitiveEqu.a for SecondaryInit.a. +// <25> 01/21/92 jmp Added SecondaryInit entries for Spike & Eclipse as well as for +// Zydeco. +// <24> 01/20/92 jmp Added an include for ShutDownEqu.a. +// <23> 01/09/92 jmp Added rudimentary support for the newly-defined extended sense +// codes. +// <22> 01/07/92 jmp Updated the Brooktree-DAC Timing Adjust value in the Kong and +// Vesuvio DAFB vidParams due to change <21> below. +// <21> 12/17/91 jmp Updated the Kong/Vesuvio, GoldFish, SuperVGA, and PAL +// non-convolved tables so that all depths within each +// configuration share a common base address. Also, tweaked the +// 19” Display parameters to generate a 60.2 KHz clock rather than +// a 59.9 KHz clock. +// <20> 11/11/91 jmp Added the “Mac Std Gamma” table to the VGA and SVGA sRsrcs as +// requested by MacDTS. +// <19> 11/05/91 jmp Added preliminary support for 19” Displays for DAFB-based CPUs. +// <18> 10/31/91 jmp Marketing (Ross Ely) finally admitted that defaulting to the +// 6500°K gamma table for Vesuvio & GoldFish was a bad idea, so I +// am now defaulting to the 9300°K gamma table on those displays. +// Yeah! +// <17> 10/03/91 jmp Added a SecondaryInit off the Zydeco board sRsrc. We’re doing +// this to fix any Zydeco-specific System Disk Regatta-related +// problems. +// <16> 09/13/91 jmp Added support for 16pp on Rubik displays when only 512K of vRAM +// is around in preparation for Spike33s. +// <15> 8/26/91 jmp Added the Zydeco ROM part numbers. +// <14> 8/26/91 jmp Added support for a Spike33-type box. +// <13> 8/21/91 jmp Changed all the Eclipse33 references to Zydeco. +// <12> 8/20/91 jmp Just updated the supported CPU code name list. +// <11> 8/9/91 jmp Added support to fix a problem with NTSC & PAL family modes +// where changing the amount of vRAM didn’t cause DAFB’s part of +// PrimaryInit to re-validate the SP_LastConfig pRAM byte. +// <10> 8/7/91 jmp Added 16bpp support for all applicable DAFB displays. +// <9> 7/29/91 jmp Added the Eclipse33 (Zydeco) & TIM-LC board sRsrcs. +// ——————————————————————————————————————————————————————————————————————————————————————— +// Pre-Zydeco ROM comments begin here. +// ——————————————————————————————————————————————————————————————————————————————————————— +// <8> 6/29/91 jmp Added the alternate AC842A-compatible timing adjust, horizontal +// active line, and horizontal front porch DAFB paramters. +// <7> 6/28/91 jmp Fixed the HFP value in the DAFB VGA parameters, and fixed the +// TA, HAL, and HFP values in the DAFB SuperVGA parameters. +// <6> 6/24/91 jmp Added support for 16bpp Vesuvio & RGB Portrait displays. +// <5> 6/17/91 jmp Reset the base address of NTSC, PAL, SuperVGA, Kong, and +// Vesuvio. Also, changed the rowbytes of PAL and SuperVGA to be +// the same as GoldFish. +// <4> 6/10/91 jmp Had to change the clock parameters for HR & GoldFish on Spike & +// Eclipse PVT units to eliminate possible jitter. +// <3> 6/4/91 jmp Made the RGB Portrait name more generic, sinc Apple doesn’t +// manufacture one, and pointed the RGB Portrait gamma directory to +// the HR gamma directory instead of the one used by Vesuvio & +// GoldFish. +// <2> 5/22/91 jmp Corrected the flags in the DB-Lite functional sRsrc to reflect +// the fact that DB-Lite’s frame buffer is 32-bit addressed. +// Updated the Apollo, Tim, and DB-Lite functional sRsrcs to +// contain the fOpenAtStart flag. Added the ROM (surface mount) +// part numbers for Spike & Eclipse. Eliminated the hardware IDs +// on the gamma tables so that the strategy for built-in video is +// again universal (this works because all the current built-in +// videos that have DACs have similar response curves). Removed +// the blanking pedestal on all PAL modes because the PAL standard +// specifies that the black & blanking levels are the same. +// <1> 5/22/91 jmp Changed name to DeclData.a from DeclDataRBV.a to reflect +// the fact that this file is used by all built-in videos, not +// just RBV. +// <29> 5/15/91 jmp Added DB-Lite support. Also, removed the multi-bit icons and +// added a new icon for TIM (also used by DB-Lite for now). +// <28> 5/10/91 jmp Added the 4•8/8•24’s Vesuvio & GoldFish (calibrated) gamma +// tables. Added all the appropriate data to support SuperVGA. +// <27> 4/26/91 jmp Updated the PAL convolved baseAddr. +// <26> 4/25/91 jmp Added a preliminary (i.e., un-calibrated) alternate gamma table +// for Vesuvio & GoldFish. This gamma table is for the the +// “natural” 9300°K heat point of those displays. +// <25> 4/23/91 jmp Eliminated duplicate NTSC parameters. +// <24> 4/19/91 jmp Cleaned up the NTSC & PAL parameters; several modes were +// “fuzzy.” Put a 1bpp icon in the board sResource for Eclipse, +// Spike, TIM, and Apollo. Put in an icon suite for Eclipse & +// Spike, but am not currently pointing at it. Eliminated gamma +// tables for NTSC, PAL, and VGA because we don’t know what kind of +// displays users’ will be hooking up. Pointed Vesuvio & GoldFish +// at the same (yet uncalibrated) gamma table being used by version +// 1.2d1 of the 8•24 card. Finally, moved PrimaryInit to the end +// of the file so that code-common data (i.e., data shared among +// the Drivers & PrimaryInit) can be declared in the DeclData file +// itself. +// <23> 4/16/91 jmp Updated fixed tables for TIM & Apollo. +// <22> 4/15/91 djw Add spId for functional video sRsrc's video attibutes (a data +// field) for Tim. +// <20> 4/4/91 jmp Updated various string names to be consistent across all uses +// (e.g., made all references to “HiRes” look like “Hi-Res”). +// <19> 4/1/91 jmp Forgot to mention two other things in previous check-in: 1) +// Removed support for DAFB 1, and 2) Added R-G-B 6500 & 9300 gamma +// tables for Vesuvio and GoldFish. +// <18> 4/1/91 jmp Changed the Monitors cdev name of VGA from “VGA Display” to “VGA +// 640x480” for consistency with NTSC & PAL. That is, we only use +// the term “Display” for monitors we know about; the NTSC, PAL and +// VGA modes specify industry standards rather than particular +// display types. Also, added an R-G-B 2.2 (D65) gamma table for +// interlaced displays; 2.2 is the common value used for NTSC gamma +// correction, and D65 (6500° K) is the heat temperature of the +// phosphors commonly used in TV (broadcast & reception). +// <17> 3/18/91 jmp Added in DAFB 2 support. The DAFB 2 data is still +// conditionalized for now, so we can take it out very easily if we +// need to. Also, removed some old data from earlier attempts to +// fix the 1bpp Rubik screen clearing stuff. +// <16> 3/8/91 jmp Needed to set rowbytes to 512 for FP @ 1, 2, and 4bb so that FPa +// would actually finti into 512K of vRam. Needed to set rowbytes +// for PAL @ 1, 2, 4, and 8bpp so that PALa would actuall fit into +// 512K of vRam. Had to add new mVidParams for PAL convolved modes +// due to the change in rowbytes for the non-convolved modes. +// Added a vidName directory for TIM and Apollo. +// <15> 3/4/91 jmp Fixed problems (bad entries) in Rubik’s inverse gamma table. +// Fixed problems (bad entries) in HR’s inverse gamma table. +// Reduced video refresh counts by -1 across the board. Needed to +// make real entries for RGB2P and RGBFP (for gamma correction). +// Used same gamma table for VGA as Rubik (due to similarity in +// clock rates). Added new gamma table for NTSC & PAL (uncorrect, +// actually, need to add real one later). +// <14> 2/25/91 jmp Moved driver directory to its proper place (i.e., according to +// its sRsrc-ID number). Moved all drivers to the very end of the +// file. Added support for CPU and Video icons. The gamma tables +// for RubikRBV & RubikACDC were identical, so I eliminated one of +// them. Updated the GS video params to reflect the fact that +// Rubik 1bpp has a 1pixel wide “border” at the top (bottom doesn’t +// matter since it will be drawn offscreen). Added inverse gamma +// tables. The 32bpp screen clearing params for GoldFish were +// incorrect. The 8bpp screen clearing params for the two-page +// display were incorrect. +// <13> 2/15/91 jmp Updated NTSC & PAL data to fix “darkening” problem in the +// full-frame convolved modes. Added support for doing only 4/8bpp +// in NTSC & PAL convolved modes. This has been conditionalized +// with CurDAFBDrvrVersion. Needed to INCLUDE +// 'HardwarePrivateEqu.a' for checking for 33 vs. 25 Mhz CPU +// operation. +// <12> 2/12/91 jmp Updated NTSC & PAL data for 4/8bpp convolved (for both FF & ST +// modes). Added defmBaseOffset to screen clear params. Added in +// “Misc” params to video params for ChkMode (in DAFBDriver.a). +// Fixed the gType id for the Rubik Gamma Table. And updated the +// GoldFish’s clock parameters to match the Portrait’s as per Larry +// Forsblad’s latest spec. +// <11> 2/3/91 jmp Added PAL video and Slot Manager data; commented out 32bpp +// params. Added in NTSC and PAL ST defmBaseOffsets. Added family +// names NTSC and PAL video families, as well as video names for +// each kind of supported display. Added ’040 CPU family sRsrc. And +// fixed the ordering of the DoubleExposure sRsrc. +// <10> 1/31/91 JK Added INCLUDE of SonicEqu.a for Sonic initialization. +// <9> 1/30/91 jmp Several fixes: Fixed rowbytes (in mVidParams) in 32bpp mode for +// GoldFish. Added NTSCFF & NTSCST video and Slot Manager data. +// For now, though, only NTSCST is up, and it is in the upper +// lefthand corner of the display. Eventually, it will be +// centered. Also, fixed a problem in the VGA video data (HFP was +// 10 pixels off in all modes). Finally, doubled rowbytes for +// 1-8bpp for Rubik displays to fix 1bpp problem: The baseAddr is +// set 512 bytes back from where QuickDraw thinks it so that none +// of the 1bpp jitter can be seen. +// <8> 1/24/91 jmp Added support for extended-sense-line displays, but this a long +// way from finished. +// <7> 1/22/91 jmp The RGB versions of the Two-Page and Portrait DAFB vidParam +// OSLstEntries were out of order. +// <6> 1/21/91 jmp Incremental change -- added support for monitors that have both +// RGB and Mono-Only types (for now that means the Portrait and +// Kong). +// <5> 1/15/91 jmp Corrected several parameters in the DAFB sVidParams data. Still +// having problems with 1 bpp mode on Rubik displays. +// <4> 1/15/91 DAF Added DAFB structures (tons of them - way too many to tag). +// Many, many, many new structures, and data. +// <3> 1/9/91 JK Added Sonic Ethernet, Eclipse, and Spike support. +// <2> 12/11/90 HJR Integration of Rex and Tim video into Terror Project. +// + +// +// The Sixth Generation of the Slot 0 Config ROM image. +// +// 0.0 = Simple config ROM ID for Mac II motherboard ROM, no functional sRsrcs. +// 1.0 = Built-in video for RBV (Mac IIci) hardware. +// 2.0 = Support for multiple built-in video devices RBV & VISA (Mac LC). +// 3.0 = Support for even more video (DAFB2, TIM, Apollo, DB-Lite) and SONIC Ethernet. +// 3.1 = Support for Zydeco (Eclipse33) video (DAFB3). +// 4.0 = The Horror DeclData. +// 5.0 = The Ludwig (Cyclone/Tempest/LC930) DeclData. +// 5.1 = The SuperMario DeclData. +// +// This file (which includes a number of other files) is the source of +// the slot 0 configuration ROM which describes a subset of the motherboard +// features. Specifically, this version of the config ROM contains the +// functional slot Resources (sRsrcs) for devices which were previously +// defined as NuBus additions, and have migrated to the motherboard. This +// class of devices include video and Ethernet communications, both of +// which had fully defined Slot Manager interfaces. In this way, these +// motherboard devices can be accessed in an implementation-independent +// manner by software that already knows how to use the Slot Manager. +// Other motherboard devices (serial ports, SCSI, etc.) could be +// represented as part of slot 0 as well, but these functions are +// identified to the system in other ways. +// +//------------------------------------------------------------------- +// Supported CPU code name list (to make sense of stray comments): +//------------------------------------------------------------------- +// Mac II, IIx, IIcx, SE/30 +// Cobra II -> Aurora -> Aurora25/16 -> Pacific/Atlantic -> IIci +// F19 -> Zone5 -> IIfx +// Erickson -> Rafiki -> Hobie Cat -> IIsi +// Elsie -> Rex -> LC +// +// TIM -> PowerBook 170 +// Eclipse -> Quadra 900 +// Spike -> Quadra 700 +// Apollo -> Classic II +// TIM-LC -> PowerBook 140 +// Eclipse33 -> Zydeco -> Quadra 950 +// DB-Lite -> PowerBook Duo 210/230 +// Spike33 -> Condor -> Wombat/WLCD -> Centris/Quadra 800 +// +// Vail -> Lego -> LC III +// Carnation/Carnation3 -> Died +// TimII -> Dartanian/Monet -> PowerBook 160/180 +// +// Cyclone -> +// Tempest -> +// +//------------------------------------------------------------------- +// Hardware code names that pop up in the config ROM code: +//------------------------------------------------------------------- +// RBV - non-programmable video hardware in the IIci and IIsi +// supports the Hi-Res, Portrait, Rubik, and an SE-sized grayscale display +// VISA - a simple non-programmable video controller in the early Elsie. Never produced. +// V8 - the replacement for the VISA in the production Elsie with much greater functionality. +// supports the Hi-Res, Rubik, and VGA displays. +// JAWS - the single mode flat-panel display controller in the 030-family portables. +// DAFB - highly-programmable video controller in the Eclipse25/33 and Spike machines, +// supports all Apple displays including interlaced video. +// Ariel - the (Brooktree-like) CLUT/DAC in the Elsie/Sonora machines. +// ACDC - the CLUT/DAC in the DAFB machines (also in the 8•24/8*24 GC cards). +// Eagle - the one-bit only controller that is in Apollo machines. It is virtually +// identical to V8. +// MSC - the LCD display control for DB-Lite machines. +// GSC - the LCD grayscale controller for DB-Lites and Dartanians. +// Sonora - kitchen-sink ASIC that is RBV-like in it’s programability (or lack there of), but video +// is just one of it’s subfunctions. +// Civic - highly-programmable video controller in the Cyclone CPU(s), similar functionality +// to that of DAFB, except that it also supports video-in. +// Sebastian +// - the CLUT/DAC used by Civic, includes an alpha channel to support video-in. +//------------------------------------------------------------------- +// Displays supported by this code (ST=safe title interlaced modes, FF=full frame): +//------------------------------------------------------------------- +// Hi-Res (HR) - 640*480, 67Hz refresh, 30.2400MHz dot clock, RGB and Monochrome +// Hi-Res 400 - 640*400, 67Hz refresh, 30.2400MHz dot clock, RGB and Monochrome +// Hi-Res MAZ - 704*512, 67Hz refresh, 33.0400MHz dot clock, RGB and Monochrome +// Rubik (GS) - 512*384, 60Hz refresh, 15.6672MHz dot clock, RGB +// Rubik-560 - 560*384, 60Hz refresh, 17.2340MHz dot clock, RGB +// Portrait (FP & RGBFP) - 640*870, 75Hz refresh, 57.2832MHz dot clock, RGB and Monochrome +// Two-Page (2P & RGB2P) - 1152*870, 75Hz refresh,100.0000MHz dot clock, RGB and Monochrome +// Goldfish (LP,GF) - 832*624, 75Hz refresh, 57.2832MHz dot clock, RGB +// VGA - 640*480, 59Hz refresh, 25.1750MHz dot clock, RGB +// SuperVGA (SVGA) - 800*600, 56Hz refresh, 36.0000MHz dot clock, RGB (VESA) +// - 800*600, 72Hz refresh, 50.0000MHz dot clock, RGB (VESA) +// SuperVGA (SxVGA) - 1024x768, 60Hz refresh, 65.0000MHz dot clock, RGB (VESA) +// - 1024x768, 70Hz refresh, 75.0000MHz dot clock, RGB (VESA) +// 19" - 1024*768, 75Hz refresh, 60.2400MHz dot clock RGB +// SE-like - 512*342, 60Hz refresh, ??.????MHz dot clock, Monochrome +// NTSC_ST - 512*384, 60Hz interlaced refresh, 12.2727MHz dot clock, RGB +// NTSC_FF - 640*480, 60Hz interlaced refresh, 12.2727MHz dot clock, RGB +// PAL_ST - 614*460, 50Hz interlaced refresh, 14.7500MHz dot clock, RGB +// PAL_FF - 768*576, 50Hz interlaced refresh, 14.7500MHz dot clock, RGB +// GSC_LCD - 640*400, 60Hz psuedo-refresh, active matrix or supertwish, Monochrome to 4bpp. +// 640x400 LCD - 640x400, 60Hz psuedo-refresh, active matrix or supertwish, RGB. +// 640x480 LCD - 640x480, 60Hz psuedo-refresh, active matrix or supertwish, RGB. +// + +#include "Types.r" +#include "ROMLink.r" + +#include "DepVideoEqu.r" +#include "HardwarePrivateEqu.r" +#include "InternalOnlyEqu.r" +#include "Quickdraw.r" + +//------------------------------------------------------------- +// +// Super sRsrc Directory +// +// This is the sRsrc directory directory, or super sRsrc +// directory. It contains entries to all supported +// sRsrc directories. +// +//------------------------------------------------------------- + +resource 'spdr' (130, "_sRsrcSuperDir") {{ + sRsrcUnknownDir, l{"_sRsrcUnknownDir"}; // Minimal sRsrc dir. + +#if !LC930 + sRsrcATIDir, a{"_sRsrcATIDir"}; // The ATI-based CPUs directory. + sRsrcCSCDir, a{"_sRsrcCSCDir"}; // The CSC-based CPUs directory. + sRsrcCivicDir, a{"_sRsrcCivicDir"}; // The Civic-based CPUs directory. + sRsrcSonoraDir, a{"_sRsrcSonoraDir"}; // The Sonora-based CPUs directory. +#endif + + sRsrcBFBasedDir, l{"_sRsrcBFBasedDir"}; // The BoxFlag-based CPUs directory. +}}; + + +//------------------------------------------------------------- +// Unknown sRsrc Directory +// +// This is a minimal sRsrc Directory. This sRsrc +// directory will only be chosen when the +// SuperInit is run on an unknown CPU. +//------------------------------------------------------------- + +resource 'sdir' (135, "_sRsrcUnknownDir") {{ + sRsrcUnknownBD, l{"_sRsrcUnknownBd"}; // Minimal board sRsrc directory. +}}; + + +resource 'boar' (140, "_sRsrcUnknownBd") {{ + sRsrcType, l{"_BoardType"}; // Minimal board sRsrc. + sRsrcName, c{"Unknown Macintosh"}; + BoardId, d{0}; + VendorInfo, l{"_VendorInfo"}; +}}; + +//------------------------------------------------------------- +// +// BoxFlag-based sRsrc Directory +// +// This sRsrc Directory supports all Slot-Manager- +// capable CPUs whose board sRsrcs and functional +// sRsrcs are/were based on BoxFlag. +// +//------------------------------------------------------------- + +resource 'sdir' (160, "_sRsrcBFBasedDir") {{ + + sRsrc_BdMacII, l{"_sRsrc_BdMacII"}; // Board sResources + sRsrc_BdMacIIx, l{"_sRsrc_BdMacIIx"}; + sRsrc_BdMacIIcx, l{"_sRsrc_BdMacIIcx"}; + sRsrc_BdMacSE30, l{"_sRsrc_BdMacSE30"}; + sRsrc_BdMacIIci, l{"_sRsrc_BdMacIIci"}; + sRsrc_BdMacIIfx, l{"_sRsrc_BdMacIIfx"}; + sRsrc_BdErickson, l{"_sRsrc_BdErickson"}; + sRsrc_BdElsie, l{"_sRsrc_BdElsie"}; + +#if !LC930 + sRsrc_BdEclipse, l{"_sRsrc_BdEclipse"}; + sRsrc_BdTIM, l{"_sRsrc_BdTIM"}; + sRsrc_BdSpike, l{"_sRsrc_BdSpike"}; + sRsrc_BdApollo, l{"_sRsrc_BdApollo"}; + sRsrc_BdTIMLC, l{"_sRsrc_BdTIM"}; + sRsrc_BdZydeco, l{"_sRsrc_BdZydeco"}; + sRsrc_BdDBLite25, l{"_sRsrc_BdDBLite"}; + sRsrc_BdWombat25, l{"_sRsrc_BdWombat"}; // + sRsrc_BdDBLite33, l{"_sRsrc_BdDBLite"}; + sRsrc_BdDartanian, l{"_sRsrc_BdDartanian"}; + sRsrc_BdDartanianLC, l{"_sRsrc_BdDartanian"}; + sRsrc_BdWombat33F, l{"_sRsrc_BdWombat"}; // + sRsrc_BdWombat33, l{"_sRsrc_BdWombat"}; +#endif + + sRsrc_BdLCII, l{"_sRsrc_BdElsie"}; // + +#if !LC930 + sRsrc_BdDBLite16, l{"_sRsrc_BdDBLite"}; + sRsrc_BdDBLite20, l{"_sRsrc_BdDBLite"}; + sRsrc_BdWombat40, l{"_sRsrc_BdWombat"}; // + sRsrc_BdWLCD20, l{"_sRsrc_BdWombat"}; // + sRsrc_BdWLCD25, l{"_sRsrc_BdWombat"}; // + sRsrc_BdWombat20, l{"_sRsrc_BdWombat"}; + sRsrc_BdWombat40F,l{"_sRsrc_BdWombat"}; + + sRsrc_BdRiscQuadra700, l{"_sRsrc_BdSpike"}; // + sRsrc_BdWLCD33, l{"_sRsrc_BdWombat"}; + + sRsrc_BdRiscCentris650, l{"_sRsrc_BdWombat"}; // + + sRsrc_BdRiscQuadra900, l{"_sRsrc_BdEclipse"}; // + sRsrc_BdRiscQuadra950, l{"_sRsrc_BdZydeco"}; // + sRsrc_BdRiscCentris610, l{"_sRsrc_BdWombat"}; // + sRsrc_BdRiscQuadra800, l{"_sRsrc_BdWombat"}; // + sRsrc_BdRiscQuadra610, l{"_sRsrc_BdWombat"}; // + sRsrc_BdRiscQuadra650, l{"_sRsrc_BdWombat"}; // + + + sRsrc_BdSTPQ700, l{"_sRsrc_BdSpike"}; // + sRsrc_BdSTPQ900, l{"_sRsrc_BdEclipse"}; // + sRsrc_BdSTPQ950, l{"_sRsrc_BdZydeco"}; // + sRsrc_BdSTPC610, l{"_sRsrc_BdWombat"}; // + sRsrc_BdSTPC650, l{"_sRsrc_BdWombat"}; // + sRsrc_BdSTPQ610, l{"_sRsrc_BdWombat"}; // + sRsrc_BdSTPQ650, l{"_sRsrc_BdWombat"}; // + sRsrc_BdSTPQ800, l{"_sRsrc_BdWombat"}; // + +#endif + +// +// These are the directory entries for RBV-based machines. +// + +#if !LC930 + + sRsrc_VidRbvFPa, l{"_sRsrc_VidRbvFPa"}; // Portrait (1,2,4) + sRsrc_VidRbvGSa, l{"_sRsrc_VidRbvGSa"}; // Rubik (1,2,4,8) + sRsrc_VidRbvHRa, l{"_sRsrc_VidRbvHRa"}; // High-Res (1,2,4,8) + sRsrc_VidRbvSEa, l{"_sRsrc_VidRbvSEa"}; // SE (1,2,4,8) + + sRsrc_VidRbvFPc, l{"_sRsrc_VidRbvFPc"}; // Portrait (1 only) + sRsrc_VidRbvGSd, l{"_sRsrc_VidRbvGSd"}; // Rubik (1 only) + sRsrc_VidRbvHRd, l{"_sRsrc_VidRbvHRd"}; // High-Res (1 only) + sRsrc_VidRbvSEd, l{"_sRsrc_VidRbvSEd"}; // SE (1 only) + + sRsrc_VidRbvFPb, l{"_sRsrc_VidRbvFPb"}; // Portrait (1,2) + sRsrc_VidRbvGSb, l{"_sRsrc_VidRbvGSb"}; // Rubik (1,2,4) + sRsrc_VidRbvHRb, l{"_sRsrc_VidRbvHRb"}; // High-Res (1,2,4) + sRsrc_VidRbvSEb, l{"_sRsrc_VidRbvSEb"}; // SE (1,2,4) + + sRsrc_VidRbvGSc, l{"_sRsrc_VidRbvGSc"}; // Rubik (1,2) + sRsrc_VidRbvHRc, l{"_sRsrc_VidRbvHRc"}; // High-Res (1,2) + sRsrc_VidRbvSEc, l{"_sRsrc_VidRbvSEc"}; // SE (1,2) +#endif + +// +// These are the directory entries for V8-based machines. +// + sRsrc_Vid_V8_GSa, l{"_sRsrc_Vid_V8_GSa"}; // Rubik, 512K VRAM configuration + sRsrc_Vid_V8_VGAa, l{"_sRsrc_Vid_V8_VGAa"}; // VGA, 512K VRAM configuration + sRsrc_Vid_V8_HRa, l{"_sRsrc_Vid_V8_HRa"}; // Hi-Res, 512K VRAM configuration + + sRsrc_Vid_V8_GSb, l{"_sRsrc_Vid_V8_GSb"}; // Rubik, 256K VRAM configuration + sRsrc_Vid_V8_VGAb, l{"_sRsrc_Vid_V8_VGAb"}; // VGA, 256K VRAM configuration + sRsrc_Vid_V8_HRb, l{"_sRsrc_Vid_V8_HRb"}; // Hi-Res, 256K VRAM configuration + + sRsrc_Vid_V8_A2Ema, l{"_sRsrc_Vid_V8_A2Ema"}; // A2 emulation, 512K VRAM configuration + sRsrc_Vid_V8_A2Emb, l{"_sRsrc_Vid_V8_A2Emb"}; // A2 emulation, 256K VRAM configuration +// ; all Rubik configs require VRAM +// +// DBLite has very simple video capabilites (for now). +// + +#if !LC930 + + sRsrc_Vid_GSC_LCD, l{"_sRsrc_Vid_GSC_LCD"}; // 1,2,4 (640x400) + +// +// This range is used for the DAFB-based directory entries. Lots of modes, so this is complicated. +// + + sRsrc_Vid_DAFB_19a, l{"_sRsrc_Vid_DAFB_19a"}; // 19" (1,2,4) + sRsrc_Vid_DAFB_19b, l{"_sRsrc_Vid_DAFB_19b"}; // 19" (1,2,4,8) + + sRsrc_Vid_DAFB_FPa, l{"_sRsrc_Vid_DAFB_FPa"}; // Portrait (1,2,4) + sRsrc_Vid_DAFB_FPb, l{"_sRsrc_Vid_DAFB_FPb"}; // Portrait (1,2,4,8) + + sRsrc_Vid_DAFB_GSa, l{"_sRsrc_Vid_DAFB_GSa"}; // Rubik (1,2,4,8) + sRsrc_Vid_DAFB_GSb, l{"_sRsrc_Vid_DAFB_GSb"}; // Rubik (1,2,4,8,32) + + sRsrc_Vid_DAFB_2Pa, l{"_sRsrc_Vid_DAFB_2Pa"}; // 2-Page (1,2,4) + sRsrc_Vid_DAFB_2Pb, l{"_sRsrc_Vid_DAFB_2Pb"}; // 2-Page (1,2,4,8) + + sRsrc_Vid_DAFB_LPa, l{"_sRsrc_Vid_DAFB_LPa"}; // Goldfish (1,2,4,8) + sRsrc_Vid_DAFB_LPb, l{"_sRsrc_Vid_DAFB_LPb"}; // Goldfish (1,2,4,8,32) + + sRsrc_Vid_DAFB_HRa, l{"_sRsrc_Vid_DAFB_HRa"}; // High-Res (1,2,4,8) + sRsrc_Vid_DAFB_HRb, l{"_sRsrc_Vid_DAFB_HRb"}; // High-Res (1,2,4,8,32) + + sRsrc_Vid_DAFB_VGAa, l{"_sRsrc_Vid_DAFB_VGAa"}; // VGA (1,2,4,8) + sRsrc_Vid_DAFB_VGAb, l{"_sRsrc_Vid_DAFB_VGAb"}; // VGA (1,2,4,8,32) + + sRsrc_Vid_DAFB_RGBFPa, l{"_sRsrc_Vid_DAFB_RGBFPa"}; // RGB Portrait (1,2,4) + sRsrc_Vid_DAFB_RGBFPb, l{"_sRsrc_Vid_DAFB_RGBFPb"}; // RGB Portrait (1,2,4,8) + + sRsrc_Vid_DAFB_RGB2Pa, l{"_sRsrc_Vid_DAFB_RGB2Pa"}; // RGB 2-Page (1,2,4) + sRsrc_Vid_DAFB_RGB2Pb, l{"_sRsrc_Vid_DAFB_RGB2Pb"}; // RGB 2-Page (1,2,4,8) + + sRsrc_Vid_DAFB_NTSCSTa, l{"_sRsrc_Vid_DAFB_NTSCSTa"}; // NTSC safe title (1,2,4,8) + sRsrc_Vid_DAFB_NTSCSTb, l{"_sRsrc_Vid_DAFB_NTSCSTb"}; // NTSC safe title (1,2,4,8,32) + sRsrc_Vid_DAFB_NTSCFFa, l{"_sRsrc_Vid_DAFB_NTSCFFa"}; // NTSC full frame (1,2,4,8) + sRsrc_Vid_DAFB_NTSCFFb, l{"_sRsrc_Vid_DAFB_NTSCFFb"}; // NTSC full frame (1,2,4,8,32) + + sRsrc_Vid_DAFB_PALSTa, l{"_sRsrc_Vid_DAFB_PALSTa"}; // PAL safe title (1,2,4,8) + sRsrc_Vid_DAFB_PALSTb, l{"_sRsrc_Vid_DAFB_PALSTb"}; // PAL safe title (1,2,4,8,32) + sRsrc_Vid_DAFB_PALFFa, l{"_sRsrc_Vid_DAFB_PALFFa"}; // PAL full frame (1,2,4,8) + sRsrc_Vid_DAFB_PALFFb, l{"_sRsrc_Vid_DAFB_PALFFb"}; // PAL full frame (1,2,4,8,32) + + sRsrc_Vid_DAFB_NTSCconvSTx, l{"_sRsrc_Vid_DAFB_NTSCconvST"}; // NTSC ST, convolved (1,2,4,8) + sRsrc_Vid_DAFB_NTSCconvST, l{"_sRsrc_Vid_DAFB_NTSCconvST"}; // NTSC ST, convolved (1,2,4,8) + sRsrc_Vid_DAFB_NTSCconvFFx, l{"_sRsrc_Vid_DAFB_NTSCconvFF"}; // NTSC FF, convolved (1,2,4,8) + sRsrc_Vid_DAFB_NTSCconvFF, l{"_sRsrc_Vid_DAFB_NTSCconvFF"}; // NTSC FF, convolved (1,2,4,8) + + sRsrc_Vid_DAFB_PALconvSTx, l{"_sRsrc_Vid_DAFB_PALconvST"}; // PAL ST, convolved (1,2,4,8) + sRsrc_Vid_DAFB_PALconvST, l{"_sRsrc_Vid_DAFB_PALconvST"}; // PAL ST, convolved (1,2,4,8) + sRsrc_Vid_DAFB_PALconvFFx, l{"_sRsrc_Vid_DAFB_PALconvFF"}; // PAL FF, convolved (1,2,4,8) + sRsrc_Vid_DAFB_PALconvFF, l{"_sRsrc_Vid_DAFB_PALconvFF"}; // PAL FF, convolved (1,2,4,8) + +// +// The portables have very simple video capabilities - a single sRsrc. +// + sRsrc_Vid_Tim_LCD, l{"_sRsrc_Vid_Tim_LCD"}; // 1bpp only + +// +// Apollo also has very simple video capabilites. +// + sRsrc_Vid_Apollo, l{"_sRsrc_Vid_Apollo"}; // 1bpp only + +// +// Ugh. I needed more entries for DAFB, so I had to put them here. +// + + sRsrc_Vid_DAFB_HRax, l{"_sRsrc_Vid_DAFB_HRax"}; // HiRes (1,2,4,8,16) + sRsrc_Vid_DAFB_HRbx, l{"_sRsrc_Vid_DAFB_HRbx"}; // HiRes (1,2,4,8,16,32) + + sRsrc_Vid_DAFB_VGAax, l{"_sRsrc_Vid_DAFB_VGAax"}; // VGA (1,2,4,8,16) + sRsrc_Vid_DAFB_VGAbx, l{"_sRsrc_Vid_DAFB_VGAbx"}; // VGA (1,2,4,8,16,32) + + sRsrc_Vid_DAFB_LPax, l{"_sRsrc_Vid_DAFB_LPax"}; // GoldFish (1,2,4,8,16) + sRsrc_Vid_DAFB_LPbx, l{"_sRsrc_Vid_DAFB_LPbx"}; // GoldFish (1,2,4,8,16,32) + + sRsrc_Vid_DAFB_SVGAax, l{"_sRsrc_Vid_DAFB_SVGAax"}; // SuperVGA (1,2,4,8,16) + sRsrc_Vid_DAFB_SVGAbx, l{"_sRsrc_Vid_DAFB_SVGAbx"}; // SuperVGA (1,2,4,8,16,32) + + sRsrc_Vid_DAFB_SVGAa, l{"_sRsrc_Vid_DAFB_SVGAa"}; // SuperVGA (1,2,4,8) + sRsrc_Vid_DAFB_SVGAb, l{"_sRsrc_Vid_DAFB_SVGAb"}; // SuperVGA (1,2,4,8,32) + + sRsrc_Vid_DAFB_GSx, l{"_sRsrc_Vid_DAFB_GSx"}; // Rubik (1,2,4,8,16,32) + sRsrc_Vid_DAFB_RGBFPbx, l{"_sRsrc_Vid_DAFB_RGBFPbx"}; // RGBPort (1,2,4,8,16) + sRsrc_Vid_DAFB_GSz, l{"_sRsrc_Vid_DAFB_GSz"}; // Rubik (1,2,4,8,16) + sRsrc_Vid_DAFB_RGB2Pbx, l{"_sRsrc_Vid_DAFB_RGB2Pbx"}; // Vesuvio (1,2,4,8,16) + + sRsrc_Vid_DAFB_NTSCSTax, l{"_sRsrc_Vid_DAFB_NTSCSTax"}; // NTSC ST (1,2,4,8,16) + sRsrc_Vid_DAFB_NTSCSTbx, l{"_sRsrc_Vid_DAFB_NTSCSTbx"}; // NTSC ST (1,2,4,8,16,32) + sRsrc_Vid_DAFB_NTSCFFax, l{"_sRsrc_Vid_DAFB_NTSCFFax"}; // NTSC FF (1,2,4,8,16) + sRsrc_Vid_DAFB_NTSCFFbx, l{"_sRsrc_Vid_DAFB_NTSCFFbx"}; // NTSC FF (1,2,4,8,16,32) + + sRsrc_Vid_DAFB_PALSTax, l{"_sRsrc_Vid_DAFB_PALSTax"}; // PAL ST (1,2,4,8,16) + sRsrc_Vid_DAFB_PALSTbx, l{"_sRsrc_Vid_DAFB_PALSTbx"}; // PAL ST extended (1,2,4,8,16,32) + sRsrc_Vid_DAFB_PALFFax, l{"_sRsrc_Vid_DAFB_PALFFax"}; // PAL FF (1,2,4,8,16) + sRsrc_Vid_DAFB_PALFFbx, l{"_sRsrc_Vid_DAFB_PALFFbx"}; // PAL FF extended (1,2,4,8,16,32) + + sRsrc_Vid_DAFB_19bx, l{"_sRsrc_Vid_DAFB_19bx"}; // 19" (1,2,4,8,16) + +#endif + +// +// The final range is reserved for miscellaneous stuff - Ethernet and Double Exposure. There's also some +// CPU sResources to identify ROM families. +// + + sRsrc_CPUMacIIci, l{"_sRsrc_CPUMacIIci"}; + sRsrc_CPUMac040, l{"_sRsrc_CPUMacO40"}; + +#if !LC930 + sRsrc_Sonic, l{"_sRsrc_Sonic"}; // Onboard Sonic Ethernet chip +#endif + + sRsrc_DoubleExposure, l{"_sRsrc_DoubleExposure"}; // special sRsrc for no-config +// ; ROM Double Exposure + +}}; + + +//------------------------------------------------------------- +// +// sRsrc_Board Lists +// +// These board sResources contain the “card” name seen by the +// Monitors cdev. +// Another important part of the board sRsrc is the PrimaryInit code. +// This universal section of code performs all necessary sRsrc +// pruning which entails a full identification of the CPU type +// and configuration. On entry to the routine, the full contents +// of the sRsrc directory are presented. On exit, only one board +// sRsrc, one video sRsrc, and any other miscellaneous sRsrcs +// remain. +// In theory, each board sRsrc should contain a PrimaryInit entry. +// The Slot Manager expects only one board sRsrc and one PrimaryInit +// per card. Since the Slot Manager scans in ascending spID order, +// only the first entry in the directory (the Mac II resource) has +// a PrimaryInit. After this universal PrimaryInit runs everything +// that needs to happen has happened, so there's no need for +// the ultimate board sRsrc list to run another PrimaryInit. +// +//------------------------------------------------------------- + +resource 'boar' (165, "_sRsrc_BdMacII") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh II"}; + BoardId, d{MIIBoardId}; + PrimaryInit, l{"_sPrimaryInitRec"}; // This PrimaryInit is universal for all machines + VendorInfo, l{"_VendorInfo"}; // supported by this sRsrc directory. +}}; + +resource 'boar' (175, "_sRsrc_BdMacIIx") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh IIx"}; + BoardId, d{MIIxBoardId}; + VendorInfo, l{"_VendorInfo"}; +}}; + +resource 'boar' (185, "_sRsrc_BdMacIIcx") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh IIcx"}; + BoardId, d{MIIcxBoardId}; + VendorInfo, l{"_VendorInfo"}; +}}; + +resource 'boar' (195, "_sRsrc_BdMacSE30") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh SE/30"}; + BoardId, d{SE30BoardID}; + VendorInfo, l{"_VendorInfo"}; +}}; + +resource 'boar' (205, "_sRsrc_BdMacIIci") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh IIci Built-In Video"}; + BoardId, d{ciVidBoardID}; + VendorInfo, l{"_VendorInfo"}; +}}; + +resource 'boar' (215, "_sRsrc_BdMacIIfx") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh IIfx"}; + BoardId, d{MIIfxBoardId}; + VendorInfo, l{"_VendorInfo"}; +}}; + +resource 'boar' (225, "_sRsrc_BdErickson") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh A Built-In Video"}; + BoardId, d{EricksonBoardID}; + VendorInfo, l{"_VendorInfo"}; +}}; + +resource 'boar' (235, "_sRsrc_BdElsie") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh B Built-In Video"}; + BoardId, d{ElsieBoardID}; + VendorInfo, l{"_VendorInfo"}; + sRsrcVidNames, l{"_V8VidNameDir"}; +}}; + +#if !LC930 + +resource 'boar' (245, "_sRsrc_BdEclipse") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh C Built-In Video"}; + sRsrcIcon, l{"_VidICONEclipse"}; + BoardId, d{EclipseBoardID}; + VendorInfo, l{"_VendorInfo"}; + SecondaryInit, l{"_sSecondaryInit"}; + sRsrcVidNames, l{"_DAFBVidNameDir"}; + sVidParmDir, l{"_VidParmDir_DAFB"}; +}}; + +resource 'boar' (255, "_sRsrc_BdTIM") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh D Built-In Video"}; + sRsrcIcon, l{"_VidICONTIM"}; + BoardId, d{TIMBoardID}; + VendorInfo, l{"_VendorInfo"}; + sRsrcVidNames, l{"_TIMVidNameDir"}; +}}; + +resource 'boar' (265, "_sRsrc_BdSpike") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh E Built-In Video"}; + sRsrcIcon, l{"_VidICONSpike"}; + BoardId, d{SpikeBoardID}; + VendorInfo, l{"_VendorInfo"}; + SecondaryInit, l{"_sSecondaryInit"}; + sRsrcVidNames, l{"_DAFBVidNameDir"}; + sVidParmDir, l{"_VidParmDir_DAFB"}; +}}; + +resource 'boar' (275, "_sRsrc_BdApollo") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh F Built-In Video"}; + sRsrcIcon, l{"_VidICONApollo"}; + BoardId, d{ApolloBoardID}; + VendorInfo, l{"_VendorInfo"}; + sRsrcVidNames, l{"_ApolloVidNameDir"}; +}}; + +resource 'boar' (285, "_sRsrc_BdZydeco") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh G Built-In Video"}; + sRsrcIcon, l{"_VidICONZydeco"}; + BoardId, d{ZydecoBrdID}; + VendorInfo, l{"_VendorInfo"}; + SecondaryInit, l{"_sSecondaryInit"}; + sRsrcVidNames, l{"_DAFBVidNameDir"}; + sVidParmDir, l{"_VidParmDir_DAFB"}; +}}; + +resource 'boar' (295, "_sRsrc_BdDBLite") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh H Built-In Video"}; + BoardId, d{DBLiteBoardID}; + VendorInfo, l{"_VendorInfo"}; + SecondaryInit, l{"_sSecondaryInit"}; + sRsrcVidNames, l{"_DBLiteVidNameDir"}; // +}}; + +resource 'boar' (305, "_sRsrc_BdWombat") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh I Built-In Video"}; + sRsrcIcon, l{"_VidICONWombat"}; + BoardId, d{WombatBrdID}; + VendorInfo, l{"_VendorInfo"}; + SecondaryInit, l{"_sSecondaryInit"}; + sRsrcVidNames, l{"_DAFBVidNameDir"}; // + sVidParmDir, l{"_VidParmDir_DAFB"}; +}}; + +resource 'boar' (315, "_sRsrc_BdDartanian") {{ + sRsrcType, l{"_BoardType"}; + sRsrcName, c{"Macintosh J Built-In Video"}; + BoardId, d{DartanianBoardID}; + VendorInfo, l{"_VendorInfo"}; + SecondaryInit, l{"_sSecondaryInit"}; + sRsrcVidNames, l{"_DartanianVidNameDir"}; +}}; + +#endif + +//===================================================================== +// Primary/Secondary/Super Init records +//===================================================================== + +resource 'node' (418, "_sPrimaryInitRec") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"PrimaryInit.rsrc"}; + type{'decl'}; + id{200};}}}; +}}; + +resource 'node' (419, "_sSecondaryInit") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"SecondaryInit.rsrc"}; + type{'decl'}; + id{210};}}}; +}}; + +resource 'node' (420, "_sSuperInitRec") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"SuperInit.rsrc"}; + type{'decl'}; + id{220};}}}; +}}; + +//------------------------------------------------------------- +// Video Name Directory +//------------------------------------------------------------- +// +// A name directory is structured identically to that of a gamma directory. +// For each possible video sRsrc spID, there is a corresponding OSLstEntry +// pointing to the name data. Also, each name data block contains a word-sized +// localization id. +// + +resource 'vdir' (345, "_DAFBVidNameDir") {{ + + sRsrc_Vid_DAFB_19a, l{"_sName_19"}; + sRsrc_Vid_DAFB_19b, l{"_sName_19"}; + + sRsrc_Vid_DAFB_FPa, l{"_sName_FP"}; + sRsrc_Vid_DAFB_FPb, l{"_sName_FP"}; + + sRsrc_Vid_DAFB_GSa, l{"_sName_GS"}; + sRsrc_Vid_DAFB_GSb, l{"_sName_GS"}; + + sRsrc_Vid_DAFB_2Pa, l{"_sName_2P"}; + sRsrc_Vid_DAFB_2Pb, l{"_sName_2P"}; + + sRsrc_Vid_DAFB_LPa, l{"_sName_LP"}; + sRsrc_Vid_DAFB_LPb, l{"_sName_LP"}; + + sRsrc_Vid_DAFB_HRa, l{"_sName_HR"}; + sRsrc_Vid_DAFB_HRb, l{"_sName_HR"}; + + sRsrc_Vid_DAFB_VGAa, l{"_sName_VGA"}; + sRsrc_Vid_DAFB_VGAb, l{"_sName_VGA"}; + + sRsrc_Vid_DAFB_RGBFPa, l{"_sName_RGBFP"}; + sRsrc_Vid_DAFB_RGBFPb, l{"_sName_RGBFP"}; + + sRsrc_Vid_DAFB_RGB2Pa, l{"_sName_RGB2P"}; + sRsrc_Vid_DAFB_RGB2Pb, l{"_sName_RGB2P"}; + + sRsrc_Vid_DAFB_NTSCSTa, l{"_sName_NTSCST"}; + sRsrc_Vid_DAFB_NTSCSTb, l{"_sName_NTSCST"}; + sRsrc_Vid_DAFB_NTSCFFa, l{"_sName_NTSCFF"}; + sRsrc_Vid_DAFB_NTSCFFb, l{"_sName_NTSCFF"}; + + sRsrc_Vid_DAFB_PALSTa, l{"_sName_PALST"}; + sRsrc_Vid_DAFB_PALSTb, l{"_sName_PALST"}; + sRsrc_Vid_DAFB_PALFFa, l{"_sName_PALFF"}; + sRsrc_Vid_DAFB_PALFFb, l{"_sName_PALFF"}; + + sRsrc_Vid_DAFB_NTSCconvSTx, l{"_sName_NTSCconvST"}; + sRsrc_Vid_DAFB_NTSCconvST, l{"_sName_NTSCconvST"}; + sRsrc_Vid_DAFB_NTSCconvFFx, l{"_sName_NTSCconvFF"}; + sRsrc_Vid_DAFB_NTSCconvFF, l{"_sName_NTSCconvFF"}; + + sRsrc_Vid_DAFB_PALconvSTx, l{"_sName_PALconvST"}; + sRsrc_Vid_DAFB_PALconvST, l{"_sName_PALconvST"}; + sRsrc_Vid_DAFB_PALconvFFx, l{"_sName_PALconvFF"}; + sRsrc_Vid_DAFB_PALconvFF, l{"_sName_PALconvFF"}; + + sRsrc_Vid_DAFB_HRax, l{"_sName_HR"}; + sRsrc_Vid_DAFB_HRbx, l{"_sName_HR"}; + + sRsrc_Vid_DAFB_VGAax, l{"_sName_VGA"}; + sRsrc_Vid_DAFB_VGAbx, l{"_sName_VGA"}; + + sRsrc_Vid_DAFB_LPax, l{"_sName_LP"}; + sRsrc_Vid_DAFB_LPbx, l{"_sName_LP"}; + + sRsrc_Vid_DAFB_SVGAax, l{"_sName_SVGA56"}; + sRsrc_Vid_DAFB_SVGAbx, l{"_sName_SVGA56"}; + + sRsrc_Vid_DAFB_SVGAa, l{"_sName_SVGA56"}; + sRsrc_Vid_DAFB_SVGAb, l{"_sName_SVGA56"}; + + sRsrc_Vid_DAFB_GSx, l{"_sName_GS"}; + sRsrc_Vid_DAFB_RGBFPbx, l{"_sName_RGBFP"}; + sRsrc_Vid_DAFB_GSz, l{"_sName_GS"}; + sRsrc_Vid_DAFB_RGB2Pbx, l{"_sName_RGB2P"}; + + sRsrc_Vid_DAFB_NTSCSTax, l{"_sName_NTSCST"}; + sRsrc_Vid_DAFB_NTSCSTbx, l{"_sName_NTSCST"}; + sRsrc_Vid_DAFB_NTSCFFax, l{"_sName_NTSCFF"}; + sRsrc_Vid_DAFB_NTSCFFbx, l{"_sName_NTSCFF"}; + + sRsrc_Vid_DAFB_PALSTax, l{"_sName_PALST"}; + sRsrc_Vid_DAFB_PALSTbx, l{"_sName_PALST"}; + sRsrc_Vid_DAFB_PALFFax, l{"_sName_PALFF"}; + sRsrc_Vid_DAFB_PALFFbx, l{"_sName_PALFF"}; + + sRsrc_Vid_DAFB_19bx, l{"_sName_19"}; + +}}; + +resource 'vdir' (350, "_V8VidNameDir") {{ + + sRsrc_Vid_V8_GSa, l{"_sName_GS"}; + sRsrc_Vid_V8_VGAa, l{"_sName_VGA"}; + sRsrc_Vid_V8_HRa, l{"_sName_HR"}; + + sRsrc_Vid_V8_GSb, l{"_sName_GS"}; + sRsrc_Vid_V8_VGAb, l{"_sName_VGA"}; + sRsrc_Vid_V8_HRb, l{"_sName_HR"}; +}}; + +resource 'vmna' (360, "_sName_FP") {128, " 640 x 870, 75 Hz (Grayscale Only)"}; +resource 'vmna' (365, "_sName_GS") {129, " 512 x 384, 60 Hz"}; +resource 'vmna' (370, "_sName_2P") {130, "1152 x 870, 75 Hz (Grayscale Only)"}; +resource 'node' (375, "_sName_GF") {{include{l{"_sName_LP"}};}}; +resource 'vmna' (380, "_sName_LP") {131, " 832 x 624, 75 Hz"}; +resource 'vmna' (385, "_sName_HR") {133, " 640 x 480, 67 Hz"}; +resource 'vmna' (390, "_sName_VGA") {134, " 640 x 480, 60 Hz (VGA)"}; +resource 'vmna' (395, "_sName_SVGA56") {135, " 800 x 600, 56 Hz (SVGA)"}; +resource 'vmna' (400, "_sName_RGBFP") {136, " 640 x 870, 75 Hz"}; +resource 'vmna' (405, "_sName_RGB2P") {137, "1152 x 870, 75 Hz"}; +resource 'vmna' (410, "_sName_NTSCST") {138, " 512 x 384, NTSC"}; +resource 'vmna' (415, "_sName_NTSCFF") {139, " 640 x 480, NTSC"}; +resource 'vmna' (420, "_sName_PALST") {140, " 640 x 480, PAL"}; +resource 'vmna' (425, "_sName_PALFF") {141, " 768 x 576, PAL"}; +resource 'vmna' (430, "_sName_NTSCconvST") {142, " 512 x 384, NTSC Convolved"}; +resource 'vmna' (435, "_sName_NTSCconvFF") {143, " 640 x 480, NTSC Convolved"}; +resource 'vmna' (440, "_sName_PALconvST") {144, " 640 x 480, PAL Convolved"}; +resource 'vmna' (445, "_sName_PALconvFF") {145, " 768 x 576, PAL Convolved"}; +resource 'vmna' (450, "_sName_19") {146, "1024 x 768, 75 Hz"}; +resource 'vmna' (455, "_sName_GS560") {147, " 560 x 384, 60 Hz"}; +resource 'vmna' (460, "_sName_SVGA72") {148, " 800 x 600, 72 Hz (VESA)"}; +resource 'vmna' (465, "_sName_SxVGA60") {149, "1024 x 768, 60 Hz (VESA)"}; +resource 'vmna' (470, "_sName_SxVGA70") {150, "1024 x 768, 70 Hz (VESA)"}; +resource 'vmna' (475, "_sName_HR400") {151, " 640 x 400, 67 Hz"}; +resource 'vmna' (480, "_sName_HRMAZ") {151, " 704 x 512, 67 Hz"}; +resource 'vmna' (485, "_sName_512x384") {152, " 512 x 384"}; +resource 'vmna' (495, "_sName_640x480") {154, " 640 x 480"}; +resource 'vmna' (500, "_sName_768x576") {155, " 768 x 576"}; + +// We’ve got the room, so what the heck: Let’s put video name directories in for TIMs, Apollos, DB-Lites! +// +resource 'vdir' (505, "_TIMVidNameDir") {{ + sRsrc_Vid_Tim_LCD, l{"_sName_LCD"}; +}}; + +resource 'node' (510, "_DartanianVidNameDir") {{ + include{l{"_DBLiteVidNameDir"}}; +}}; + +resource 'vdir' (515, "_DBLiteVidNameDir") {{ + sRsrc_Vid_GSC_LCD, l{"_sName_LCD"}; +}}; + +resource 'vdir' (520, "_ApolloVidNameDir") {{ + sRsrc_Vid_Apollo, l{"_sName_Apollo"}; +}}; + +resource 'vmna' (525, "_sName_LCD") {128, " 640 x 400 (Black & White)"}; +resource 'vmna' (530, "_sName_Apollo") {128, " 512 x 342 (Black & White)"}; + + +//------------------------------------------------------------- +// Board Type +//------------------------------------------------------------- + +resource 'styp' (535, "_BoardType") {CatBoard, TypBoard, 0, 0}; + +//------------------------------------------------------------- +// Vendor Info +//------------------------------------------------------------- + +resource 'vend' (540, "_VendorInfo") {{ + VendorId, c{"Copyright © 1986-1993 by Apple Computer, Inc. All Rights Reserved."}; + RevLevel, c{"Macintosh CPU Family 5.1"}; // offset to revision + PartNum, c{"Universal DeclROM"}; // offset to part number descriptor + Date, c{$$Date}; // offset to ROM build date descriptor +}}; + +//------------------------------------------------------------- +// CPU sResource List +//------------------------------------------------------------- + + +resource 'node' (575, "_sRsrc_CPUMacIIci") {{ + include{l{"_sRsrc_CPUMac030"}}; +}}; + +resource 'srsc' (575, "_sRsrc_CPUMac030") {{ + sRsrcType, l{"_CPUMacIIci"}; // ’030 Class Machines (plus MacII & LC). + sRsrcName, l{"_CPUMacIIciName"}; + MajRAMSp, l{"_MajRAMSp"}; + MinROMSp, l{"_MinROMSp"}; +}}; + + +resource 'srsc' (578, "_sRsrc_CPUMacO40") {{ + sRsrcType, l{"_CPUMacO40"}; // ’040 Class Machines. + sRsrcName, l{"_CPUMac040Name"}; + MajRAMSp, l{"_MajRAMSp"}; + MinROMSp, l{"_MinROMSp"}; +}}; + + +resource 'styp' (583, "_CPUMacIIci") {CatCPU, Typ68030, DrSwMacCPU, drHWRBV}; +resource 'styp' (585, "_CPUMacO40") {CatCPU, Type68040, DrSwMacCPU, drHwRBV}; + +resource 'node' (590, "_CPUMacIIciName") {{ + cstring{"CPU_68030_\_MacIIFamily"}; // Name of sResource +}}; + +resource 'node' (595, "_CPUMac040Name") {{ + cstring{"CPU_68040"}; // Name of sResource +}}; + +resource 'node' (600, "_MajRAMSp") {{ + longs{{$00000000;$3FFFFFFF;}}; // RAM space +}}; + +resource 'node' (605, "_MinROMSp") {{ + longs{{$F0800000;$F0FFFFFF;}}; // ROM space +}}; + +//------------------------------------------------------------- +// Functional sResources +//------------------------------------------------------------- + +resource 'srsc' (610, "_sRsrc_VidRbvHRa") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthHRa"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvHR"}; + + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMHR"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMHR"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBMHR"}; // offset to FourBitMode parameters + FourthVidMode, l{"_EBMHR"}; + +}}; + + +//---------------------------------- + +resource 'srsc' (615, "_sRsrc_VidRbvHRb") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthHRb"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvHR"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMHR"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMHR"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBMHR"}; // offset to FourBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (620, "_sRsrc_VidRbvHRc") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthHRc"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvHR"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMHR"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMHR"}; // offset to TwoBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (625, "_sRsrc_VidRbvHRd") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthHRd"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvHR"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMHR"}; // offset to OneBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (630, "_sRsrc_VidRbvFPa") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthFPa"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDir_FP"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMFP"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMFP"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBMFP"}; // offset to FourBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (635, "_sRsrc_VidRbvFPb") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthFPb"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDir_FP"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMFP"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMFP"}; // offset to TwoBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (640, "_sRsrc_VidRbvFPc") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthFPc"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDir_FP"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMFP"}; // offset to OneBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (645, "_sRsrc_VidRbvGSa") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthGSa"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvGS"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMGS"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMGS"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBMGS"}; // offset to TwoBitMode parameters + FourthVidMode, l{"_EBMGS"}; // offset to TwoBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (650, "_sRsrc_VidRbvGSb") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthGSb"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvGS"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMGS"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMGS"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBMGS"}; // offset to TwoBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (655, "_sRsrc_VidRbvGSc") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthGSc"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvGS"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMGS"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMGS"}; // offset to TwoBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (660, "_sRsrc_VidRbvGSd") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthGSd"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvGS"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMGS"}; // offset to OneBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (665, "_sRsrc_VidRbvSEa") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthSEa"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvSE"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMSE"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMSE"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBMSE"}; // offset to FourBitMode parameters + FourthVidMode, l{"_EBMSE"}; // offset to EightBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (670, "_sRsrc_VidRbvSEb") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthSEb"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvSE"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMSE"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMSE"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBMSE"}; // offset to FourBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (675, "_sRsrc_VidRbvSEc") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthSEc"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvSE"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMSE"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMSE"}; // offset to TwoBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (680, "_sRsrc_VidRbvSEd") {{ + sRsrcType, l{"_VideoTypeRBV"}; // Video Type descriptor + sRsrcName, l{"_VideoNameRBV"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirRBV"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseRBV"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLengthSEd"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirRbvSE"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMSE"}; // offset to OneBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (685, "_sRsrc_Vid_V8_GSa") {{ + sRsrcType, l{"_VideoTypeElsie"}; // Video Type descriptor + sRsrcName, l{"_VideoNameV8"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirElsie"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseElsie"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLength_V8_GSa"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirElsGS"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBM_V8_GSa"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBM_V8_GSa"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBM_V8_GSa"}; // offset to FourBitMode parameters + FourthVidMode, l{"_EBM_V8_GSa"}; // offset to EightBitMode parameters + FifthVidMode, l{"_D16BM_V8_GS"}; // offset to SixteenBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (690, "_sRsrc_Vid_V8_GSb") {{ + sRsrcType, l{"_VideoTypeElsie"}; // Video Type descriptor + sRsrcName, l{"_VideoNameV8"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirElsie"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseElsie"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLength_V8_GSb"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirElsGS"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBM_V8_GSb"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBM_V8_GSb"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBM_V8_GSb"}; // offset to FourBitMode parameters + FourthVidMode, l{"_EBM_V8_GSb"}; // offset to EightBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (695, "_sRsrc_Vid_V8_A2Ema") {{ + sRsrcType, l{"_VideoTypeElsie"}; // Video Type descriptor + sRsrcName, l{"_VideoNameV8"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirElsie"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseElsie"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLength_V8_A2Ema"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirElsGS"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBM_V8_A2Ema"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBM_V8_A2Ema"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBM_V8_A2Ema"}; // offset to FourBitMode parameters + FourthVidMode, l{"_EBM_V8_A2Ema"}; // offset to EightBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (700, "_sRsrc_Vid_V8_A2Emb") {{ + sRsrcType, l{"_VideoTypeElsie"}; // Video Type descriptor + sRsrcName, l{"_VideoNameV8"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirElsie"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseElsie"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLength_V8_A2Emb"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirElsGS"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBM_V8_A2Emb"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBM_V8_A2Emb"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBM_V8_A2Emb"}; // offset to FourBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (705, "_sRsrc_Vid_V8_HRa") {{ + sRsrcType, l{"_VideoTypeElsie"}; // Video Type descriptor + sRsrcName, l{"_VideoNameV8"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirElsie"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseElsie"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLength_V8_HRa"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirElsHR"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBM_V8_HRa"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBM_V8_HRa"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBM_V8_HRa"}; // offset to FourBitMode parameters + FourthVidMode, l{"_EBM_V8_HR"}; // offset to EightBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (710, "_sRsrc_Vid_V8_HRb") {{ + sRsrcType, l{"_VideoTypeElsie"}; // Video Type descriptor + sRsrcName, l{"_VideoNameV8"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirElsie"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseElsie"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLength_V8_HRb"}; // offset to frame buffer length + + sGammaDir, a{"_GammaDirElsHR"}; + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBM_V8_HRb"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBM_V8_HRb"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBM_V8_HRb"}; // offset to FourBitMode parameters + +}}; + + +//---------------------------------- +// +// The two VGA modes have the same configurations and capabilities as the Mac II High-Res, so, to +// save a little ROM space, we have a distinct sRsrc list, but the elements of this list all +// point to High-Res data structures. +// + +resource 'srsc' (715, "_sRsrc_Vid_V8_VGAa") {{ + sRsrcType, l{"_VideoTypeElsie"}; // Video Type descriptor + sRsrcName, l{"_VideoNameV8"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirElsie"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseElsie"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLength_V8_VGAa"}; // offset to frame buffer length + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBM_V8_HRa"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBM_V8_HRa"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBM_V8_HRa"}; // offset to FourBitMode parameters + FourthVidMode, l{"_EBM_V8_HR"}; // offset to EightBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (720, "_sRsrc_Vid_V8_VGAb") {{ + sRsrcType, l{"_VideoTypeElsie"}; // Video Type descriptor + sRsrcName, l{"_VideoNameV8"}; // offset to Video Name string + sRsrcDrvrDir, l{"_VidDrvrDirElsie"}; // offset to driver directory + sRsrcHWDevID, d{1}; // hardware device id + + MinorBaseOS, l{"_MinorBaseElsie"}; // offset to frame buffer array offset + MinorLength, l{"_MinorLength_V8_VGAb"}; // offset to frame buffer length + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBM_V8_HRb"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBM_V8_HRb"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBM_V8_HRb"}; // offset to FourBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (725, "_sRsrc_Vid_DAFB_19a") {{ + sRsrcType, l{"_VideoTypeDAFB"}; + sRsrcName, l{"_VideoNameDAFB"}; + sRsrcDrvrDir, l{"_VidDrvrDirDAFB"}; + sRsrcFlags, d{(0|(1< + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMLCD"}; // offset to OneBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (995, "_sRsrc_Vid_Apollo") {{ + sRsrcType, l{"_VideoTypeApollo"}; // Video type descriptor. + sRsrcName, l{"_VideoNameApollo"}; // Offset to video name string. + sRsrcDrvrDir, l{"_VidDrvrDirApollo"}; // Offset to driver directory. + sRsrcFlags, d{(0|(1< + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMApollo"}; // offset to OneBitMode parameters + +}}; + + +//---------------------------------- + +resource 'srsc' (1005, "_sRsrc_Vid_GSC_LCD") {{ + sRsrcType, l{"_VideoTypeGSC"}; // Video type descriptor. + sRsrcName, l{"_VideoNameGSC"}; // Offset to video name string. + sRsrcDrvrDir, l{"_VidDrvrDirGSC"}; // Offset to driver directory. + sRsrcFlags, d{(0|(1< + +//Parameters - this consists of a list of the different modes supported by this hardware configuration + + FirstVidMode, l{"_OBMLCD"}; // offset to OneBitMode parameters + SecondVidMode, l{"_TBMLCD"}; // offset to TwoBitMode parameters + ThirdVidMode, l{"_FBMLCD"}; // offset to FourBitMode paramters + +}}; + +//---------------------------------- + +resource 'srsc' (1570, "_sRsrc_Sonic") {{ + sRsrcType, l{"_NetSonic"}; // Network type descriptor + sRsrcName, l{"_NetSonicName"}; // offset to name string + sRsrcDrvrDir, l{"_NetSonicDrvrDir"}; // offset to driver directory + sRsrcFlags, d{0}; // don't open this device at start + sRsrcHWDevId, d{1}; // the first of many onboard Ethernet chips +}}; + + +resource 'srsc' (1575, "_sRsrc_Mace") {{ + sRsrcType, l{"_NetMace"}; // Network type descriptor + sRsrcName, l{"_NetMaceName"}; // offset to name string + sRsrcDrvrDir, l{"_NetMaceDrvrDir"}; // offset to driver directory + sRsrcFlags, d{0}; // don't open this device at start + sRsrcHWDevId, d{2}; // the second of many onboard Ethernet chips +}}; + + +//---------------------------------- + +resource 'srsc' (1580, "_sRsrc_DoubleExposure") {{ + sRsrcType, l{"_CPUDblExp"}; + sRsrcName, l{"_CPUDblExpName"}; + CPU_FlagsID, d{CPU_Flags}; // tells that we have a pixel clock +}}; + +//---------------------------------- + +resource 'srsc' (1581, "_sRsrc_SCSI_Transport") {{ + sRsrcType, l{"_SCSITransport"}; + sRsrcName, l{"_SCSITransName"}; +}}; + + +//------------------------------------------------------------- +// Resource Types +//------------------------------------------------------------- + +resource 'styp' (1585, "_VideoTypeRBV") {CatDisplay, TypVideo, DrSwApple, DrHwRBV}; +resource 'styp' (1590, "_VideoTypeElsie") {CatDisplay, TypVideo, DrSwApple, DrHwElsie}; +resource 'styp' (1595, "_VideoTypeTim") {CatDisplay, TypVideo, DrSwApple, DrHwTim}; +resource 'styp' (1600, "_VideoTypeDAFB") {CatDisplay, TypVideo, DrSwApple, DrHwDAFB}; +resource 'styp' (1605, "_VideoTypeApollo") {CatDisplay, TypVideo, DrSwApple, DrHwApollo}; +resource 'styp' (1610, "_VideoTypeGSC") {CatDisplay, TypVideo, DrSwApple, DrHwGSC}; +resource 'styp' (1625, "_NetSonic") {CatNetwork, TypEthernet, DrSwApple, DrHwSonic}; +resource 'styp' (1630, "_NetMace") {CatNetwork, TypEthernet, DrSwApple, DrHwMace}; +resource 'styp' (1635, "_CPUDblExp") {CatCPU, TypAppleII, DrSwAppleIIe, DrHwDblExp}; +resource 'styp' (1636, "_SCSITransport") {CatIntBus, TypXPT, DrSwApple, sRsrc_BdCyclone}; + +//------------------------------------------------------------- +// Resource Names +//------------------------------------------------------------- + +resource 'cstr' (1640, "_VideoNameRBV") {"Display_Video_Apple_RBV1"}; +resource 'cstr' (1645, "_VideoNameV8") {"Display_Video_Apple_V8"}; + +#if !LC930 + +resource 'cstr' (1650, "_VideoNameTim") {"Display_Video_Apple_TIM"}; +resource 'cstr' (1655, "_VideoNameDAFB") {"Display_Video_Apple_DAFB"}; +resource 'cstr' (1660, "_VideoNameApollo") {"Display_Video_Apple_Apollo"}; +resource 'cstr' (1665, "_VideoNameGSC") {"Display_Video_Apple_DBLite"}; +resource 'cstr' (1680, "_NetSonicName") {"Network_Ethernet_Apple_Sonic"}; +resource 'cstr' (1685, "_NetMaceName") {"Network_Ethernet_Apple_Mace"}; + +#endif + +resource 'cstr' (1690, "_CPUDblExpName") {"CPU_AppleII_AppleIIe_FeatureCard"}; +resource 'cstr' (1691, "_SCSITransName") {"IntelligentBus_Transport_Apple"}; + +//------------------------------------------------------------- +// Resource Icons +//------------------------------------------------------------- + +// The current implementation of the Monitors cdev (i.e., versions 4.x - 7.0) lamely looks at the board +// sRsrc for its icon. And, for 7.0, Monitors’ current icon-plotting mechanism isn’t very studly. So, +// I have come up with in interrim solution: For now I’ll only include 1-bit icons at the CPU (board sResource) +// level. +// + +#if !LC930 + +resource 'node' (1695, "_VidICONCyclone") {{ + include{l{"_VidICONVail"}}; +}}; + +resource 'node' (1700, "_VidICONVail") {{ + include{l{"_VidICONCarnation"}}; +}}; + +resource 'node' (1705, "_VidICONCarnation") {{ + include{l{"_VidICONZydeco"}}; +}}; + +resource 'node' (1710, "_VidICONZydeco") {{ + include{l{"_VidICONEclipse"}}; +}}; + +resource 'node' (1715, "_VidICONEclipse") {{ + include{l{"_VidICONSpike"}}; +}}; + +resource 'node' (1720, "_VidICONSpike") {{ + include{l{"_VidICONWombat"}}; +}}; + +resource 'ICON' (1725, "_VidICONWombat") { + $"3FFFE000400010004FFF900050005000" + $"55505000500050005500500050007FFC" + $"5400400250004FF25000500A5000554A" + $"4FFFD00A4000550A3FFFD00A0800540A" + $"3BFF500A2000540A3FFFD00A0000500A" + $"3FFE500A40014FF24FF9400250053FFC" + $"5505081050057BDE5405400250057FFE" + $"500500004FF90000400100003FFE0000" +}; + + +resource 'ICON' (1730, "_VidICONTIM") { + $"00000000000000000000000000000000" + $"00000000000000000000000000000000" + $"00000000000000000000000000000000" + $"00000000000000020000000500000009" + $"00000012000000240000004800000090" + $"00000120000002400000048000000900" + $"00000E0000001C0000DB7E0001FFC200" + $"7F004200803F420080004200FFFFFC00" +}; + + +resource 'ICON' (1735, "_VidICONApollo") { + $"0000000007FFFFE00800001008000010" + $"08FFFF10090000900955509009000090" + $"09550090090000900950009009000090" + $"09500090090000900954009009000090" + $"0900009008FFFF100800001008000010" + $"08000010080000100800FF1008000010" + $"08000010080000100800001007FFFFE0" + $"04000020040000200400002007FFFFE0" +}; + + +//------------------------------------------------------------- +// Driver Directory +//------------------------------------------------------------- + +resource 'ddir' (1740, "_VidDrvrDirRBV") {{ + sMacOS68020, l{"_sRBVDrvrDir"}; +}}; + +resource 'ddir' (1750, "_VidDrvrDirDAFB") {{ + sMacOS68020, l{"_sDAFBDrvrDir"}; +}}; + +resource 'ddir' (1755, "_VidDrvrDirTim") {{ + sMacOS68020, l{"_sTimDrvrDir"}; +}}; + +resource 'ddir' (1760, "_VidDrvrDirApollo") {{ + sMacOS68020, l{"_sApolloDrvrDir"}; +}}; + +resource 'ddir' (1765, "_VidDrvrDirGSC") {{ + sMacOS68020, l{"_sGSCDrvrDir"}; +}}; + +resource 'ddir' (1780, "_NetSonicDrvrDir") {{ + sMacOS68020, l{"_sSonicDrvrDir"}; +}}; + +resource 'ddir' (1785, "_NetMaceDrvrDir") {{ + sMacOS68020, l{"_sMaceDrvrDir"}; +}}; + +#endif + +resource 'ddir' (1745, "_VidDrvrDirElsie") {{ + sMacOS68020, l{"_sV8DrvrDir"}; +}}; + +//================================================================== +// Bring in the driver images +//================================================================== + +#if !LC930 +resource 'node' (570, "_sRBVDrvrDir") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataVideo.rsrc"}; + type{'decl'}; + id{60};}}}; +}}; + + +resource 'node' (571, "_sDAFBDrvrDir") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataVideo.rsrc"}; + type{'decl'}; + id{40};}}}; +}}; + +resource 'node' (572, "_sTimDrvrDir") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataVideo.rsrc"}; + type{'decl'}; + id{90};}}}; +}}; + +resource 'node' (573, "_sApolloDrvrDir") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataVideo.rsrc"}; + type{'decl'}; + id{10};}}}; +}}; + +resource 'node' (574, "_sGSCDrvrDir") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataVideo.rsrc"}; + type{'decl'}; + id{50};}}}; +}}; + +resource 'node' (578, "_sSonicDrvrDir") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataSonic.rsrc"}; + type{'decl'}; + id{1};}}}; +}}; + +resource 'node' (579, "_sMaceDrvrDir") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataMace.rsrc"}; + type{'decl'}; + id{1};}}}; +}}; + +#endif + +resource 'node' (560, "_sV8DrvrDir") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataVideo.rsrc"}; + type{'decl'}; + id{100};}}}; +}}; + +//------------------------------------------------------------- +// Minor/Major Bases/Lengths +//------------------------------------------------------------- + +resource 'node' (1790, "_MinorBaseRBV") {{ + include{l{"_MinorBaseElsie"}}; +}}; + +resource 'node' (1795, "_MinorBaseElsie") {{ + include{l{"_MinorBaseTim"}}; +}}; + +resource 'node' (1800, "_MinorBaseTim") {{ + include{l{"_MinorBaseApollo"}}; +}}; + +resource 'node' (1805, "_MinorBaseApollo") {{ + include{l{"_MinorBaseGSC"}}; +}}; + +resource 'node' (1810, "_MinorBaseGSC") {{ + include{l{"_MinorBaseSonora"}}; +}}; + +resource 'long' (1815, "_MinorBaseSonora") {defMinorBase}; +resource 'long' (1820, "_MinorBaseDAFBStd") {DAFBStdOffset}; +resource 'long' (1825, "_MinorBaseDAFB2P") {DAFB2POffset}; +resource 'long' (1830, "_MinorBaseDAFB2PW") {DAFB2POffsetW}; +resource 'long' (1835, "_MinorBaseDAFBBS") {DAFBBSOffset}; +resource 'long' (1840, "_MinorBaseDAFBBSW") {DAFBBSOffsetW}; +resource 'long' (1845, "_MinorBaseDAFBNTSC") {DAFBNTSCOffset}; +resource 'long' (1850, "_MinorBaseDAFBNTSCConv") {DAFBNTSCConvOff}; +resource 'long' (1855, "_MinorBaseDAFBPAL") {DAFBPALOffset}; +resource 'long' (1860, "_MinorBaseDAFBPALW") {DAFBPALOffsetW}; +resource 'long' (1865, "_MinorBAseDAFBPALConv") {DAFBPALConvOff}; + + +resource 'long' (1990, "_MinorLengthHRa") {MinorLengthHRa}; +resource 'long' (1995, "_MinorLengthHRb") {MinorLengthHRb}; +resource 'long' (2000, "_MinorLengthHRc") {MinorLengthHRc}; +resource 'long' (2005, "_MinorLengthHRd") {MinorLengthHRd}; +resource 'long' (2010, "_MinorLengthFPa") {MinorLengthFPa}; +resource 'long' (2015, "_MinorLengthFPb") {MinorLengthFPb}; +resource 'long' (2020, "_MinorLengthFPc") {MinorLengthFPc}; +resource 'long' (2025, "_MinorLengthSEa") {MinorLengthSEa}; +resource 'long' (2030, "_MinorLengthSEb") {MinorLengthSEb}; +resource 'long' (2035, "_MinorLengthSEc") {MinorLengthSEc}; +resource 'long' (2040, "_MinorLengthSEd") {MinorLengthSEd}; +resource 'long' (2045, "_MinorLengthGSa") {MinorLengthGSa}; +resource 'long' (2050, "_MinorLengthGSb") {MinorLengthGSb}; +resource 'long' (2055, "_MinorLengthGSc") {MinorLengthGSc}; +resource 'long' (2060, "_MinorLengthGSd") {MinorLengthGSd}; +resource 'long' (2065, "_MinorLength_V8_HRa") {MinorLength_V8_HRa}; +resource 'long' (2070, "_MinorLength_V8_HRb") {MinorLength_V8_HRb}; +resource 'long' (2075, "_MinorLength_V8_GSa") {MinorLength_V8_GSa}; +resource 'long' (2080, "_MinorLength_V8_GSb") {MinorLength_V8_GSb}; +resource 'long' (2085, "_MinorLength_V8_VGAa") {MinorLength_V8_VGAa}; +resource 'long' (2090, "_MinorLength_V8_VGAb") {MinorLength_V8_VGAb}; +resource 'long' (2095, "_MinorLength_V8_A2Ema") {MinorLength_V8_A2Ema}; +resource 'long' (2100, "_MinorLength_V8_A2Emb") {MinorLength_V8_A2Emb}; +resource 'long' (2105, "_MinorLength_DAFB_FPa") {MinorLength_DAFB_FPa}; +resource 'long' (2110, "_MinorLength_DAFB_FPb") {MinorLength_DAFB_FPb}; +resource 'long' (2115, "_MinorLength_DAFB_FPbx") {MinorLength_DAFB_FPbx}; +resource 'long' (2120, "_MinorLength_DAFB_2Pa") {MinorLength_DAFB_2Pa}; +resource 'long' (2125, "_MinorLength_DAFB_2Pb") {MinorLength_DAFB_2Pb}; +resource 'long' (2130, "_MinorLength_DAFB_2Pbx") {MinorLength_DAFB_2Pbx}; +resource 'long' (2135, "_MinorLength_DAFB_LPa") {MinorLength_DAFB_LPa}; +resource 'long' (2140, "_MinorLength_DAFB_LPax") {MinorLength_DAFB_LPax}; +resource 'long' (2145, "_MinorLength_DAFB_LPb") {MinorLength_DAFB_LPb;}; + +resource 'node' (2150, "_MinorLength_DAFB_NTSCconvST") {{ + include{l{"_MinorLength_DAFB_NTSCSTa"}}; +}}; + +resource 'node' (2155, "_MinorLength_DAFB_NTSCSTa") {{ + include{l{"_MinorLength_DAFB_GSa"}}; +}}; + +resource 'long' (2160, "_MinorLength_DAFB_GSa") {MinorLength_DAFB_GSa}; +resource 'node' (2165, "_MinorLength_DAFB_NTSCSTax") {{ + include{l{"_MinorLength_DAFB_GSb"}}; +}}; + +resource 'long' (2170, "_MinorLength_DAFB_GSb") {MinorLength_DAFB_GSb}; +resource 'long' (2175, "_MinorLength_DAFB_NTSCSTb") {MinorLength_DAFB_NTSCSTb}; + +resource 'node' (2180, "_MinorLength_DAFB_NTSCconvFF") {{ + include{l{"_MinorLength_DAFB_NTSCFFa"}}; +}}; + +resource 'node' (2185, "_MinorLength_DAFB_NTSCFFa") {{ + include{l{"_MinorLength_DAFB_VGAa"}}; +}}; + +resource 'node' (2190, "_MinorLength_DAFB_VGAa") {{ + include{l{"_MinorLength_DAFB_HRa"}}; +}}; + +resource 'long' (2195, "_MinorLength_DAFB_HRa") {MinorLength_DAFB_HRa}; + +resource 'node' (2200, "_MinorLength_DAFB_NTSCFFax") {{ + include{l{"_MinorLength_DAFB_VGAax"}}; +}}; + +resource 'node' (2205, "_MinorLength_DAFB_VGAax") {{ + include{l{"_MinorLength_DAFB_HRax"}}; +}}; + +resource 'long' (2210, "_MinorLength_DAFB_HRax") {MinorLength_DAFB_HRax}; + +resource 'node' (2215, "_MinorLength_DAFB_NTSCFFb") {{ + include{l{"_MinorLength_DAFB_VGAb"}}; +}}; + +resource 'node' (2220, "_MinorLength_DAFB_VGAb") {{ + include{l{"_MinorLength_DAFB_HRb"}}; +}}; + +resource 'long' (2225, "_MinorLength_DAFB_HRb") {MinorLength_DAFB_HRb}; +resource 'long' (2230, "_MinorLength_DAFB_PALFFa") {MinorLength_DAFB_PALFFa}; +resource 'long' (2235, "_MinorLength_DAFB_PALFFax") {MinorLength_DAFB_PALFFax}; +resource 'long' (2240, "_MinorLength_DAFB_PALFFb") {MinorLength_DAFB_PALFFb}; +resource 'long' (2245, "_MinorLength_DAFB_PALconvFF") {MinorLength_DAFB_PALconvFF}; +resource 'long' (2250, "_MinorLength_DAFB_PALSTa") {MinorLength_DAFB_PALSTa}; +resource 'long' (2255, "_MinorLength_DAFB_PALSTax") {MinorLength_DAFB_PALSTax}; +resource 'long' (2260, "_MinorLength_DAFB_PALSTb") {MinorLength_DAFB_PALSTb}; +resource 'long' (2265, "_MinorLength_DAFB_PALconvST") {MinorLength_DAFB_PALconvST}; +resource 'long' (2270, "_MinorLength_DAFB_SVGAa") {MinorLength_DAFB_SVGAa}; +resource 'long' (2275, "_MinorLength_DAFB_SVGAax") {MinorLength_DAFB_SVGAax}; +resource 'long' (2280, "_MinorLength_DAFB_SVGAb") {MinorLength_DAFB_SVGAb}; +resource 'long' (2285, "_MinorLength_DAFB_19a") {MinorLength_DAFB_19a}; +resource 'long' (2290, "_MinorLength_DAFB_19b") {MinorLength_DAFB_19b}; +resource 'long' (2295, "_MinorLength_DAFB_19bx") {MinorLength_DAFB_19bx}; +resource 'long' (2305, "_MinorLengthGSCLCD") {MinorLengthGSCLCD}; +resource 'long' (2310, "_MinorLengthLCD") {MinorLengthLCD}; +resource 'long' (2315, "_MinorLengthApollo") {MinorLengthApollo}; + +//------------------------------------------------------------- +// Video Parameters Directory +//------------------------------------------------------------- +// +// This directory holds references to data blocks containing the hardware +// setup parameters for the various modes and configurations of the +// hardware. +// +// DAFB +// ---- +// Here's the organization of the data - there's a block for each type of +// display. The 'a' (reduced functionality) and 'b' (full functionality) +// entries may point at the same block of parameters, since the 'b' set +// is a superset of the 'a' group for these current configurations. Each +// block has a bunch of parameters which are device specific, the format +// of which is known only to the consumers. For DAFB, this includes +// DAFB setup info, Swatch info, ACDC info, National clock chip info, and +// screen clearing information (skip factor, longs/row, number of rows). +// There is one set of this information for each of the supported screen depths. +// +// For more detailed information about what all the data in this section +// actually means, the following ERS should be consulted: +// +// 1) AC842, 9/12/88 -- the ACDC ERS, Apple Computer, Inc. +// 2) AC842A, Risc Products Gropu, Apple Computer, Inc. +// 3) DP8531/32/33 Programmable Clock Generator, 4/27/89 -- National ERS, +// National Semiconductor. +// 4) DAFB, Eclipse Direct Access Frame Buffer Controller Specification -- DAFB ERS, +// Apple Computer, Inc. +// 5) Wombat/djMEMC ERS? +// +// Sonora +// ------ +// Sonora is much more simple than DAFB. The first set of parameteres are for the +// Omega; they are used to generate the correct dot-clock per display. The next +// parameter is the value used to tell Sonora which display is attached. Following +// that is a set of parameters that says which bit-depths are valid in the various +// vRAM configurations. Finally, there is a set of parameters that describes the +// number of rows and the rowbytes per bit-depth per display. +// +// Civic +// ----- +// +//------------------------------------------------------------- + +resource 'list' (2740, "_VidParmDir_DAFB") {{ + + sRsrc_Vid_DAFB_19a, l{"_sVidParms_DAFB_19"}; // 19" Display + sRsrc_Vid_DAFB_19b, l{"_sVidParms_DAFB_19"}; + + sRsrc_Vid_DAFB_FPa, l{"_sVidParms_DAFB_FP"}; // Portrait + sRsrc_Vid_DAFB_FPb, l{"_sVidParms_DAFB_FP"}; + + sRsrc_Vid_DAFB_GSa, l{"_sVidParms_DAFB_GS"}; // Rubik + sRsrc_Vid_DAFB_GSb, l{"_sVidParms_DAFB_GS"}; + + sRsrc_Vid_DAFB_2Pa, l{"_sVidParms_DAFB_2P"}; // 2-Page (Kong) + sRsrc_Vid_DAFB_2Pb, l{"_sVidParms_DAFB_2P"}; + + sRsrc_Vid_DAFB_LPa, l{"_sVidParms_DAFB_LP"}; // Goldfish + sRsrc_Vid_DAFB_LPb, l{"_sVidParms_DAFB_LP"}; + + sRsrc_Vid_DAFB_HRa, l{"_sVidParms_DAFB_HR"}; // High-Res (Mono & RGB) + sRsrc_Vid_DAFB_HRb, l{"_sVidParms_DAFB_HR"}; + + sRsrc_Vid_DAFB_VGAa, l{"_sVidParms_DAFB_VGA"}; // VGA + sRsrc_Vid_DAFB_VGAb, l{"_sVidParms_DAFB_VGA"}; + + sRsrc_Vid_DAFB_RGBFPa, l{"_sVidParms_DAFB_FP"}; // RGB Portrait + sRsrc_Vid_DAFB_RGBFPb, l{"_sVidParms_DAFB_FP"}; + + sRsrc_Vid_DAFB_RGB2Pa, l{"_sVidParms_DAFB_2P"}; // RGB 2-Page (Vesuvio) + sRsrc_Vid_DAFB_RGB2Pb, l{"_sVidParms_DAFB_2P"}; + + sRsrc_Vid_DAFB_NTSCSTa, l{"_sVidParms_DAFB_NTSCST"}; // NTSC ST + sRsrc_Vid_DAFB_NTSCSTb, l{"_sVidParms_DAFB_NTSCST"}; + + sRsrc_Vid_DAFB_NTSCFFa, l{"_sVidParms_DAFB_NTSCFF"}; // NTSC FF + sRsrc_Vid_DAFB_NTSCFFb, l{"_sVidParms_DAFB_NTSCFF"}; + + sRsrc_Vid_DAFB_PALSTa, l{"_sVidParms_DAFB_PALST"}; // PAL ST + sRsrc_Vid_DAFB_PALSTb, l{"_sVidParms_DAFB_PALST"}; + + sRsrc_Vid_DAFB_PALFFa, l{"_sVidParms_DAFB_PALFF"}; // PAL FF + sRsrc_Vid_DAFB_PALFFb, l{"_sVidParms_DAFB_PALFF"}; + + sRsrc_Vid_DAFB_NTSCconvSTx, l{"_sVidParms_DAFB_NTSCconvST"}; // NTSC ST convolved + sRsrc_Vid_DAFB_NTSCconvST, l{"_sVidParms_DAFB_NTSCconvST"}; // NTSC ST convolved + sRsrc_Vid_DAFB_NTSCconvFFx, l{"_sVidParms_DAFB_NTSCconvFF"}; // NTSC FF convolved + sRsrc_Vid_DAFB_NTSCconvFF, l{"_sVidParms_DAFB_NTSCconvFF"}; // NTSC FF convolved + + sRsrc_Vid_DAFB_PALconvSTx, l{"_sVidParms_DAFB_PALconvST"}; // PAL ST convolved + sRsrc_Vid_DAFB_PALconvST, l{"_sVidParms_DAFB_PALconvST"}; // PAL ST convolved + sRsrc_Vid_DAFB_PALconvFFx, l{"_sVidParms_DAFB_PALconvFF"}; // PAL FF convolved + sRsrc_Vid_DAFB_PALconvFF, l{"_sVidParms_DAFB_PALconvFF"}; // PAL FF convolved + + sRsrc_Vid_DAFB_HRax, l{"_sVidParms_DAFB_HR"}; // HiRes 16bpp + sRsrc_Vid_DAFB_HRbx, l{"_sVidParms_DAFB_HR"}; // HiRes 16/32bpp + + sRsrc_Vid_DAFB_VGAax, l{"_sVidParms_DAFB_VGA"}; // VGA 16bpp + sRsrc_Vid_DAFB_VGAbx, l{"_sVidParms_DAFB_VGA"}; // VGA 16/32bpp + + sRsrc_Vid_DAFB_LPax, l{"_sVidParms_DAFB_LP"}; // GoldFish 16bpp + sRsrc_Vid_DAFB_LPbx, l{"_sVidParms_DAFB_LP"}; // GoldFish 16/32bpp + + sRsrc_Vid_DAFB_SVGAax, l{"_sVidParms_DAFB_SVGA"}; // SuperVGA + sRsrc_Vid_DAFB_SVGAbx, l{"_sVidParms_DAFB_SVGA"}; + sRsrc_Vid_DAFB_SVGAa, l{"_sVidParms_DAFB_SVGA"}; // + sRsrc_Vid_DAFB_SVGAb, l{"_sVidParms_DAFB_SVGA"}; // + + sRsrc_Vid_DAFB_GSx, l{"_sVidParms_DAFB_GS"}; // Rubik 16/32bpp + sRsrc_Vid_DAFB_RGBFPbx, l{"_sVidParms_DAFB_FP"}; // RGBPort 16bpp + sRsrc_Vid_DAFB_GSz, l{"_sVidParms_DAFB_GS"}; // Rubik 16bpp + sRsrc_Vid_DAFB_RGB2Pbx, l{"_sVidParms_DAFB_2P"}; // Vesuvio 16bpp + + sRsrc_Vid_DAFB_NTSCSTax, l{"_sVidParms_DAFB_NTSCST"}; // NTSC ST 16bpp + sRsrc_Vid_DAFB_NTSCSTbx, l{"_sVidParms_DAFB_NTSCST"}; // NTSC ST 16/32bpp + sRsrc_Vid_DAFB_NTSCFFax, l{"_sVidParms_DAFB_NTSCFF"}; // NTSC FF 16bpp + sRsrc_Vid_DAFB_NTSCFFbx, l{"_sVidParms_DAFB_NTSCFF"}; // NTSC FF 16/32bpp + + sRsrc_Vid_DAFB_PALSTax, l{"_sVidParms_DAFB_PALST"}; // PAL ST 16bpp + sRsrc_Vid_DAFB_PALSTbx, l{"_sVidParms_DAFB_PALST"}; // PAL ST 16/32bpp + sRsrc_Vid_DAFB_PALFFax, l{"_sVidParms_DAFB_PALFF"}; // PAL FF 16bpp + sRsrc_Vid_DAFB_PALFFbx, l{"_sVidParms_DAFB_PALFF"}; // PAL FF 16/32bpp + + sRsrc_Vid_DAFB_19bx, l{"_sVidParms_DAFB_19"}; // 19" 16bpp + + pSRsrc_Vid_DAFB_2PRdRGB, l{"_sVidParms_DAFB_2PRdRGB"}; // Radius ColorTPD + pSRsrc_Vid_DAFB_2PRdMono, l{"_sVidParms_DAFB_2PRdMono"}; // Radius MonoTPD + +}}; + + + +// This #define's are a stopgap measure for now. +#define firstVidMode 0x80 +#define secondVidMode 0x81 +#define thirdVidMode 0x82 +#define fourthVidMode 0x83 +#define fifthVidMode 0x84 +#define sixthVidMode 0x85 + + + +// +// Full Page Display parameters +// +resource 'node' (2755, "_sVidParms_DAFB_FP") {{ + blocksize{}; // block size + +// Clock chip parms +// + bytes{{$0E;$07;$00;$00;$0B;$00;$00;$00;$00;$02;}}; // 8531 chip parms. + words{{$2C05;$01A0;$7E00;}}; // 8534 chip parms. + +// Misc params +// + bytes{{FourthVidMode;FifthVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BFP-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$072C;$072A;$0004;$0009;$0058;$0724;$072A;}}; // Static Swatch Params. + +// One bit mode parameters +// + words{{$0080;$060E;$0010;}}; // DAFB parms + words{{$0176;$00D0;$0014;$019F;$0027;$002D;}}; // Dynamic Swatch parms + words{{$003F;$004B;$018B;$019E;$001D;}}; + words{{$00A0;}}; // ACDC parms + words{{$001A;$0048;$0188;}}; // AMD params + + words{{((defmBounds_RFP*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_512_RB-((defmBounds_RFP*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$0080;$0606;$0010;}}; // DAFB parms + words{{$0176;$00D0;$0014;$019F;$0027;$002D;}}; // Dynamic Swatch parms + words{{$003F;$004B;$018B;$019E;$0035;}}; + words{{$00A8;}}; // ACDC parms + words{{$0032;$0048;$0188;}}; // AMD params + + words{{((defmBounds_RFP*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_512_RB-((defmBounds_RFP*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$0080;$0602;$0010;}}; // DAFB parms + words{{$0176;$00D0;$0014;$019F;$0027;$002D;}}; // Dynamic Swatch parms + words{{$003F;$004B;$018B;$019E;$0041;}}; + words{{$00B0;}}; // ACDC parms + words{{$003E;$0048;$0188;}}; // AMD params + + words{{((defmBounds_RFP*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_512_RB-((defmBounds_RFP*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$0100;$0600;$0010;}}; // DAFB parms + words{{$0176;$00D0;$0014;$019F;$0027;$002D;}}; // Dynamic Swatch parms + words{{$003F;$004B;$018B;$019E;$0047;}}; + words{{$00B8;}}; // ACDC parms + words{{$0044;$0048;$0188;}}; // AMD params + + words{{((defmBounds_RFP*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RFP*8)/8));}}; // SkipFactor + +// Sixteen bit mode parameters + + words{{$0200;$06FF;$0011;}}; // DAFB parms + words{{$0176;$00D0;$0014;$019F;$0027;$002D;}}; // Dynamic Swatch parms + words{{$003F;$004B;$018B;$019E;$004A;}}; + words{{$00BE;}}; // ACDC parms + words{{$0047;$0048;$0188;}}; // AMD params + + words{{((defmBounds_RFP*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_2048_RB-((defmBounds_RFP*16)/8));}}; // SkipFactor +}}; + + + +// +// 19" DAFB parameters +// +resource 'node' (2760, "_sVidParms_DAFB_19") {{ + blocksize{}; // block size + +// Clock chip parms + bytes{{$08;$0F;$00;$00;$0F;$01;$00;$00;$00;$01;}}; // 8531 chip parms + words{{$3C04;$0040;$0400;}}; // 8534 chip parms. + +// Misc params +// + bytes{{FourthVidMode;FifthVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_B19-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$0648;$0646;$0004;$0009;$0040;$0640;$0644;}}; // Static Swatch params. + +// One bit mode parameters +// + words{{$0080;$0606;$0030;}}; // DAFB parms + words{{$012A;$00A5;$000C;$014B;$0017;$001A;}}; // Dynamic Swatch parms + words{{$0023;$003F;$013F;$014A;$0029;}}; + words{{$00C0;}}; // ACDC parms + words{{$0029;$003F;$013F;}}; // AMD params + + words{{((defmBounds_R19*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_512_RB-((defmBounds_R19*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$0080;$0602;$0030;}}; // DAFB parms + words{{$012A;$00A5;$000C;$014B;$0017;$001A;}}; // Dynamic Swatch parms + words{{$0023;$003F;$013F;$014A;$0035;}}; + words{{$00C8;}}; // ACDC parms + words{{$0035;$003F;$013F;}}; // AMD params + + words{{((defmBounds_R19*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_512_RB-((defmBounds_R19*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$0080;$0600;$0030;}}; // DAFB parms + words{{$012A;$00A5;$000C;$014B;$0017;$001A;}}; // Dynamic Swatch parms + words{{$0023;$003F;$013F;$014A;$003B;}}; + words{{$00D0;}}; // ACDC parms + words{{$003B;$003F;$013F;}}; // AMD params + + words{{((defmBounds_R19*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_512_RB-((defmBounds_R19*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$0100;$06FF;$0030;}}; // DAFB parms + words{{$012A;$00A5;$000C;$014B;$0017;$001A;}}; // Dynamic Swatch parms + words{{$0023;$003F;$013F;$014A;$003F;}}; + words{{$00D8;}}; // ACDC parms + words{{$003F;$003F;$013F;}}; // AMD params + + words{{((defmBounds_R19*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_R19*8)/8));}}; // SkipFactor + +// Sixteen bit mode parameters +// + words{{$0200;$06FF;$0031;}}; // DAFB parms + words{{$0254;$014A;$0018;$0297;$002F;$0035;}}; // Dynamic Swatch parms + words{{$0047;$0081;$0281;$0296;$0080;}}; + words{{$00BE;}}; // ACDC parms + words{{$0080;$0081;$0281;}}; // AMD params + + words{{((defmBounds_R19*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_2048_RB-((defmBounds_R19*16)/8));}}; // SkipFactor +}}; + + + +// +// Rubik parameters +// +resource 'node' (2765, "_sVidParms_DAFB_GS") {{ + blocksize{}; // block size + +// Clock chip parms + bytes{{$0E;$05;$00;$00;$0F;$00;$00;$00;$00;$03;}}; // 8531 chip parms + words{{$1C05;$40A0;$7A00;}}; // 8534 chip parms + +// Misc params +// + bytes{{SixthVidMode;SixthVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BGS-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$032E;$032C;$0004;$0009;$002A;$032A;$032B;}}; // Static Swatch Params. + +// One bit mode parameters +// + words{{$0100;$061E;$0050;}}; // DAFB parms + words{{$025E;$0140;$0010;$027F;$001F;$002B;}}; // Dynamic Swatch parms + words{{$004F;$0068;$0268;$027E;$000A;}}; + words{{$0080;}}; // ACDC parms + words{{$0005;$0063;$0263;}}; // AMD params + + words{{((defmBounds_RGS*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RGS*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$0100;$060E;$0050;}}; // DAFB parms + words{{$025E;$0140;$0010;$027F;$001F;$002B;}}; // Dynamic Swatch parms + words{{$004F;$0068;$0268;$027E;$003A;}}; + words{{$0088;}}; // ACDC parms + words{{$0035;$0063;$0263;}}; // AMD params + + words{{((defmBounds_RGS*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RGS*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$0100;$0606;$0050;}}; // DAFB parms + words{{$025E;$0140;$0010;$027F;$001F;$002B;}}; // Dynamic Swatch parms + words{{$004F;$0068;$0268;$027E;$0052;}}; + words{{$0090;}}; // ACDC parms + words{{$004D;$0063;$0263;}}; // AMD params + + words{{((defmBounds_RGS*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RGS*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$0100;$0602;$0050;}}; // DAFB parms + words{{$025E;$0140;$0010;$027F;$001F;$002B;}}; // Dynamic Swatch parms + words{{$004F;$0068;$0268;$027E;$005E;}}; + words{{$0098;}}; // ACDC parms + words{{$0059;$0063;$0263;}}; // AMD params + + words{{((defmBounds_RGS*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RGS*8)/8));}}; // SkipFactor + +// Sixteen bit mode parameters +// + words{{$0100;$0600;$0050;}}; // DAFB parms + words{{$025E;$0140;$0010;$027F;$001F;$002B;}}; // Swatch parms + words{{$004F;$0063;$0263;$027E;$005F;}}; + words{{$009E;}}; // ACDC parms + words{{$005F;$0063;$0263;}}; // AMD params + + words{{((defmBounds_RGS*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RGS*16)/8));}}; // SkipFactor + +// Thirty-Two bit mode parameters +// + words{{$0200;$06FF;$0050;}}; // DAFB parms + words{{$025E;$0140;$0010;$027F;$001F;$002B;}}; // Dynamic Swatch parms + words{{$004F;$0069;$0269;$027E;$0069;}}; + words{{$009C;}}; // ACDC parms + words{{$0063;$0063;$0263;}}; // AMD params + + words{{((defmBounds_RGS*32)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_2048_RB-((defmBounds_RGS*32)/8));}}; // SkipFactor +}}; + + + +// +// Two-Page Display parameters +// +resource 'node' (2770, "_sVidParms_DAFB_2P") {{ + blocksize{}; // block size + +// Clock chip parms +// + bytes{{$0E;$0B;$00;$00;$06;$02;$00;$00;$00;$00;}}; // 8531 chip parms + words{{$1C04;$0040;$1400;}}; // 8534 chip parms + +// Misc params +// + bytes{{FourthVidMode;FifthVidMode;}}; // MaxMode a,b + bytes{{FourthVidMode-FirstVidMode;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_B2P-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$0726;$0724;$0004;$0009;$0052;$071E;$0722;}}; // Static Swatch Params. + +// One bit mode parameters +// + words{{$0090;$0406;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$016B;$001F;$0022;}}; // Dynamic Swatch parms + words{{$002B;$0040;$0160;$016A;$002A;}}; + words{{$00C0;}}; // ACDC parms + words{{$0029;$003F;$015F;}}; // AMD params + + words{{((defmBounds_R2P*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_576_RB-((defmBounds_R2P*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$0090;$0402;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$016B;$001F;$0022;}}; // Dynamic Swatch parms + words{{$002B;$0040;$0160;$016A;$0036;}}; + words{{$00C8;}}; // ACDC parms + words{{$0035;$003F;$015F;}}; // AMD params + + words{{((defmBounds_R2P*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_576_RB-((defmBounds_R2P*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$0090;$0400;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$016B;$001F;$0022;}}; // Dynamic Swatch parms + words{{$002B;$0040;$0160;$016A;$003C;}}; + words{{$00D0;}}; // ACDC parms + words{{$003B;$003F;$015F;}}; // AMD params + + words{{((defmBounds_R2P*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_576_RB-((defmBounds_R2P*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$0120;$4FF;$0011;}}; // DAFB parms + words{{$014A;$00B6;$0010;$016B;$001F;$0022;}}; // Dynamic Swatch parms + words{{$002B;$0040;$0160;$016A;$003F;}}; + words{{$00D8;}}; // ACDC parms + words{{$003F;$003F;$015F;}}; // AMD params + + words{{((defmBounds_R2P*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1152_RB-((defmBounds_R2P*8)/8));}}; // SkipFactor + +// Sixteen bit mode parameters +// + words{{$0240;$4FF;$0011;}}; // DAFB parms + words{{$0294;$016C;$0020;$02D7;$003F;$0045;}}; // Dynamic Swatch parms + words{{$0057;$0087;$02C7;$02D6;$0086;}}; + words{{$00BE;}}; // ACDC parms + words{{$0080;$0081;$02C1;}}; // AMD params + + words{{((defmBounds_R2P*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_2304_RB-((defmBounds_R2P*16)/8));}}; // SkipFactor +}}; + + + +// +// Radius ColorTPD parameters +// +resource 'node' (2775, "_sVidParms_DAFB_2PRdRGB") {{ + blocksize{}; // block size + +// Clock chip parms +// + bytes{{$0E;$0B;$00;$00;$06;$02;$00;$00;$00;$00;}}; // 8531 chip parms + words{{$1C04;$0040;$1400;}}; // 8534 chip parms + +// Misc params +// + bytes{{FourthVidMode;FifthVidMode;}}; // MaxMode a,b + bytes{{FourthVidMode-FirstVidMode;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_B2P-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$0720;$071E;$0004;$0009;$0046;$0712;$071C;}}; // Static Swatch parms. + +// One bit mode parameters +// + words{{$0090;$0406;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$017F;$002B;$002E;}}; // Dynamic Swatch parms + words{{$0037;$005B;$017B;$017E;$0045;}}; + words{{$00C0;}}; // ACDC parms + words{{$0045;$005B;$017B;}}; // AMD params + + words{{((defmBounds_R2P*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_576_RB-((defmBounds_R2P*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$0090;$0402;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$017F;$002B;$002E;}}; // Dyamic Swatch parms + words{{$0037;$005B;$017B;$017E;$0051;}}; + words{{$00C8;}}; // ACDC parms + words{{$0051;$005B;$017B;}}; // AMD params + + words{{((defmBounds_R2P*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_576_RB-((defmBounds_R2P*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$0090;$0400;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$017F;$002B;$002E;}}; // Dynamic Swatch parms + words{{$0037;$005B;$017B;$017E;$0057;}}; + words{{$00D0;}}; // ACDC parms + words{{$0057;$005B;$017B;}}; // AMD params + + words{{((defmBounds_R2P*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_576_RB-((defmBounds_R2P*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$0120;$04FF;$0011;}}; // DAFB parms + words{{$014A;$00B6;$0010;$017F;$002B;$002E;}}; // Dynamic Swatch parms + words{{$0037;$005B;$017B;$017E;$005A;}}; + words{{$00D8;}}; // ACDC parms + words{{$005B;$005B;$017B;}}; // AMD params + + words{{((defmBounds_R2P*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1152_RB-((defmBounds_R2P*8)/8));}}; // SkipFactor + +// Sixteen bit mode parameters +// + words{{$0240;$04FF;$0011;}}; // DAFB parms + words{{$0294;$016C;$0020;$02FF;$0057;$005D;}}; // Dynamic Swatch parms + words{{$006F;$00B9;$02F9;$02FE;$00B8;}}; + words{{$00BE;}}; // ACDC parms + words{{$00B8;$00B9;$02F9;}}; // AMD params + + words{{((defmBounds_R2P*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_2304_RB-((defmBounds_R2P*16)/8));}}; // SkipFactor +}}; + + + +// +// Radius MonoTPD parameters +// +resource 'node' (2780, "_sVidParms_DAFB_2PRdMono") {{ + blocksize{}; // block size + +// Clock chip parms +// + bytes{{$0E;$0B;$00;$00;$06;$02;$00;$00;$00;$00;}}; // 8531 chip parms + words{{$1C04;$0040;$1400;}}; // 8534 chip parms + +// Misc params +// + bytes{{ThirdVidMode-FirstVidMode;FourthVidMode-FirstVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_B2P-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$0730;$072E;$001C;$0021;$0056;$0722;$072C;}}; // Static Swatch parms + +// One bit mode parameters +// + words{{$0090;$0406;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$017F;$002B;$002E;}}; // Dynamic Swatch parms + words{{$0037;$005B;$017B;$017E;$0045;}}; + words{{$00C0;}}; // ACDC parms + words{{$0045;$005B;$017B;}}; // AMD params + + words{{((defmBounds_R2P*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_576_RB-((defmBounds_R2P*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$0090;$0402;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$017F;$002B;$002E;}}; // Dynamic Swatch parms + words{{$0037;$005B;$017B;$017E;$0051;}}; + words{{$00C8;}}; // ACDC parms + words{{$0051;$005B;$017B;}}; // AMD params + + words{{((defmBounds_R2P*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_576_RB-((defmBounds_R2P*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$0090;$0400;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$017F;$002B;$002E;}}; // Dynamic Swatch parms + words{{$0037;$005B;$017B;$017E;$0057;}}; + words{{$00D0;}}; // ACDC parms + words{{$0057;$005B;$017B;}}; // AMD params + + words{{((defmBounds_R2P*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_576_RB-((defmBounds_R2P*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$0120;$04FF;$0010;}}; // DAFB parms + words{{$014A;$00B6;$0010;$017F;$002B;$002E;}}; // Dynamic Swatch parms + words{{$0037;$005B;$017B;$017E;$005B;}}; + words{{$00D8;}}; // ACDC parms + words{{$005B;$005B;$017B;}}; // AMD params + + words{{((defmBounds_R2P*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1152_RB-((defmBounds_R2P*8)/8));}}; // SkipFactor +}}; + + + +// +// Goldfish Display parameters +// +resource 'node' (2785, "_sVidParms_DAFB_LP") {{ + blocksize{}; // block size + +// Clock chip parms +// + bytes{{$0E;$07;$00;$00;$0B;$00;$00;$00;$00;$02;}}; // 8531 chip parms. + words{{$2C05;$01A0;$7E00;}}; // 8534 chip parms. + +// Misc params +// + bytes{{FifthVidMode;SixthVidMode;}}; // MaxMode a,b + bytes{{FifthVidMode-FirstVidMode;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BLP-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$0536;$0534;$0004;$0009;$0052;$0532;$0533;}}; // Static Swatch Parms. + +// One bit mode parameters +// + words{{$00D0;$060E;$0010;}}; // DAFB parms + words{{$021E;$0120;$0010;$023F;$001F;$0025;}}; // Dynamic Swatch parms + words{{$0037;$008B;$022B;$023E;$005D;}}; + words{{$00A0;}}; // ACDC parms + words{{$005B;$0089;$0229;}}; // AMD params + + words{{((defmBounds_RLP*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RLP*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$00D0;$0606;$0010;}}; // DAFB parms + words{{$021E;$0120;$0010;$023F;$001F;$0025;}}; // Dynamic Swatch parms + words{{$0037;$008B;$022B;$023E;$0075;}}; + words{{$00A8;}}; // ACDC parms + words{{$0073;$0089;$0229;}}; // AMD params + + words{{((defmBounds_RLP*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RLP*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$00D0;$0602;$0010;}}; // DAFB parms + words{{$021E;$0120;$0010;$023F;$001F;$0025;}}; // Dynamic Swatch parms + words{{$0037;$008B;$022B;$023E;$0081;}}; + words{{$00B0;}}; // ACDC parms + words{{$007F;$0089;$0229;}}; // AMD params + + words{{((defmBounds_RLP*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RLP*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$00D0;$0600;$0010;}}; // DAFB parms + words{{$021E;$0120;$0010;$023F;$001F;$0025;}}; // Dynamic Swatch parms + words{{$0037;$008B;$022B;$023E;$0087;}}; + words{{$00B8;}}; // ACDC parms + words{{$0085;$0089;$0229;}}; // AMD params + + words{{((defmBounds_RLP*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RLP*8)/8));}}; // SkipFactor + +// Sixteen bit mode parameters +// + words{{$01A0;$06FF;$0011;}}; // DAFB parms + words{{$021E;$0120;$0010;$023F;$001F;$0025;}}; // Dynamic Swatch parms + words{{$0037;$0089;$0229;$023E;$0088;}}; + words{{$00BE;}}; // ACDC parms + words{{$0089;$0089;$0229;}}; // AMD params + + words{{((defmBounds_RLP*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1664_RB-((defmBounds_RLP*16)/8));}}; // SkipFactor + +// Thirty-Two bit mode parameters +// + words{{$0340;$0000;$0011;}}; // DAFB parms + words{{$043E;$0240;$0020;$047F;$003F;$004B;}}; // Dynamic Swatch parms + words{{$006F;$0119;$0459;$047E;$0118;}}; + words{{$003C;}}; // ACDC parms + words{{$0113;$0113;$0453;}}; // AMD params + + words{{((defmBounds_RLP*32)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_3328_RB-((defmBounds_RLP*32)/8));}}; // SkipFactor +}}; + + + +// +// Hi-Res Display parameters +// +resource 'node' (2790, "_sVidParms_DAFB_HR") {{ + blocksize{}; // block size + +// Clock chip parms +// + bytes{{$0E;$0F;$00;$00;$05;$01;$00;$00;$00;$03;}}; // 8531 parms + words{{$1C05;$8190;$6700;}}; // 8534 parms + +// Misc params +// + bytes{{FifthVidMode;SixthVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BHR-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$041A;$0418;$0004;$0009;$0052;$0412;$0416;}}; // Static Swatch parms + +// One bit mode parameters +// + words{{$0100;$061E;$0030;}}; // DAFB parms + words{{$031E;$01B0;$0020;$035F;$003F;$004B;}}; // Dynamic Swatch parms + words{{$006F;$0098;$0318;$035E;$003A;}}; + words{{$0080;}}; // ACDC parms + words{{$0035;$0093;$0313;}}; // AMD params + + words{{((defmBounds_RHR*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RHR*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$0100;$060E;$0030;}}; // DAFB parms + words{{$031E;$01B0;$0020;$035F;$003F;$004B;}}; // Dynamic Swatch parms + words{{$006F;$0098;$0318;$035E;$006A;}}; + words{{$0088;}}; // ACDC parms + words{{$0065;$0093;$0313;}}; // AMD params + + words{{((defmBounds_RHR*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RHR*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$0100;$0606;$0030;}}; // DAFB parms + words{{$031E;$01B0;$0020;$035F;$003F;$004B;}}; // Dynamic Swatch parms + words{{$006F;$0098;$0318;$035E;$0082;}}; + words{{$0090;}}; // ACDC parms + words{{$007D;$0093;$0313;}}; // AMD params + + words{{((defmBounds_RHR*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RHR*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$0100;$0602;$0030;}}; // DAFB parms + words{{$031E;$01B0;$0020;$035F;$003F;$004B;}}; // Dynamic Swatch parms + words{{$006F;$0098;$0318;$035E;$008E;}}; + words{{$0098;}}; // ACDC parms + words{{$0089;$0093;$0313;}}; // AMD params + + words{{((defmBounds_RHR*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RHR*8)/8));}}; // SkipFactor + +// Sixteen bit mode parameters +// + words{{$0200;$0600;$0030;}}; // DAFB parms + words{{$031E;$01B0;$0020;$035F;$003F;$004B;}}; // Dynamic Swatch parms + words{{$006F;$0093;$0313;$035E;$008F;}}; + words{{$009E;}}; // ACDC parms + words{{$008F;$0093;$0313;}}; // AMD params + + words{{((defmBounds_RHR*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_2048_RB-((defmBounds_RHR*16)/8));}}; // SkipFactor + +// Thirty-Two bit mode parameters +// + words{{$0400;$06FF;$0032;}}; // DAFB parms + words{{$031E;$01B0;$0020;$035F;$003F;$004B;}}; // Dynamic Swatch parms + words{{$006F;$0099;$0319;$035E;$0099;}}; + words{{$009C;}}; // ACDC parms + words{{$0093;$0093;$0313;}}; // AMD params + + words{{((defmBounds_RHR*32)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_4096_RB-((defmBounds_RHR*32)/8));}}; // SkipFactor +}}; + + + +// +// VGA Display parameters +// +resource 'node' (2795, "_sVidParms_DAFB_VGA") {{ + blocksize{}; // block size + +// Clock chip parms +// + bytes{{$0F;$01;$01;$00;$09;$03;$00;$00;$00;$02;}}; // 8531 chip parms + words{{$2C05;$8130;$3F00;}}; // 8534 chip parms + +// Misc params +// + bytes{{FifthVidMode;SixthVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BVGA-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$041A;$0418;$0002;$0007;$0044;$0404;$0408;}}; // Static Swatch parms. + +// One bit mode parameters +// + words{{$0100;$061E;$0030;}}; // DAFB parms + words{{$026E;$0190;$0030;$031F;$005F;$006B;}}; // Dynamic Swatch parms + words{{$007E;$0088;$0308;$031E;$002A;}}; + words{{$0080;}}; // ACDC parms + words{{$0025;$0083;$0303;}}; // AMD params + + words{{((defmBounds_RVGA*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RVGA*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$0100;$060E;$0030;}}; // DAFB parms + words{{$026E;$0190;$0030;$031F;$005F;$006B;}}; // Dynamic Swatch parms + words{{$007E;$0088;$0308;$031E;$005A;}}; + words{{$0088;}}; // ACDC parms + words{{$0055;$0083;$0303;}}; // AMD params + + words{{((defmBounds_RVGA*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RVGA*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$0100;$0606;$0030;}}; // DAFB parms + words{{$026E;$0190;$0030;$031F;$005F;$006B;}}; // Dynamic Swatch parms + words{{$007E;$0088;$0308;$031E;$0072;}}; + words{{$0090;}}; // ACDC parms + words{{$006D;$0083;$0303;}}; // AMD params + + words{{((defmBounds_RVGA*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RVGA*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$0100;$0602;$0030;}}; // DAFB parms + words{{$026E;$0190;$0030;$031F;$005F;$006B;}}; // Dynamic Swatch parms + words{{$007E;$0088;$0308;$031E;$007E;}}; + words{{$0098;}}; // ACDC parms + words{{$0079;$0083;$0303;}}; // AMD params + + words{{((defmBounds_RVGA*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RVGA*8)/8));}}; // SkipFactor + +// Sixteen bit mode parameters +// + words{{$0200;$0600;$0030;}}; // DAFB parms + words{{$026E;$0190;$0030;$031F;$005F;$006B;}}; // Dynamic Swatch parms + words{{$007E;$0083;$0303;$031E;$007F;}}; + words{{$009E;}}; // ACDC parms + words{{$007F;$0083;$0303;}}; // AMD params + + words{{((defmBounds_RVGA*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_2048_RB-((defmBounds_RVGA*16)/8));}}; // SkipFactor + +// Thirty-Two bit mode parameters +// + words{{$0400;$06FF;$0032;}}; // DAFB parms + words{{$026E;$0190;$0030;$031F;$005F;$006B;}}; // Dynamic Swatch parms + words{{$007E;$0089;$0309;$031E;$0089;}}; + words{{$009C;}}; // ACDC parms + words{{$0083;$0083;$0303;}}; // AMD params + + words{{((defmBounds_RVGA*32)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_4096_RB-((defmBounds_RVGA*32)/8));}}; // SkipFactor +}}; + + + +// +// SuperVGA Display parameters +// +resource 'node' (2800, "_sVidParms_DAFB_SVGA") {{ + blocksize{}; // block size + +// Clock chip parms +// + bytes{{$0C;$0F;$00;$00;$03;$02;$00;$00;$00;$02;}}; // 8531 chip parms + words{{$1C04;$80A0;$3600;}}; // 8534 chip parms + +// Misc params +// + bytes{{FifthVidMode;SixthVidMode;}}; // MaxMode a,b + bytes{{FifthVidMode-FirstVidMode;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BSVGA-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$04E8;$04E6;$001A;$001F;$0028;$04D8;$04DC;}}; // Static Swatch parms + +// One bit mode parameters +// + words{{$00D0;$060E;$0030;}}; // DAFB parms + words{{$01C6;$0100;$001C;$01FF;$0037;$003D;}}; // Dynamic Swatch parms + words{{$004F;$0063;$01F3;$01FE;$0035;}}; + words{{$00A0;}}; // ACDC parms + words{{$0032;$0060;$01F0;}}; // AMD params + + words{{((defmBounds_RSVGA*1)/32)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RSVGA*1)/8));}}; // SkipFactor + +// Two bit mode parameters +// + words{{$00D0;$0606;$0030;}}; // DAFB parms + words{{$01C6;$0100;$001C;$01FF;$0037;$003D;}}; // Dynamic Swatch parms + words{{$004F;$0063;$01F3;$01FE;$004D;}}; + words{{$00A8;}}; // ACDC parms + words{{$004A;$0060;$01F0;}}; // AMD params + + words{{((defmBounds_RSVGA*2)/32)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RSVGA*2)/8));}}; // SkipFactor + +// Four bit mode parameters +// + words{{$00D0;$0602;$0030;}}; // DAFB parms + words{{$01C6;$0100;$001C;$01FF;$0037;$003D;}}; // Dynamic Swatch parms + words{{$004F;$0063;$01F3;$01FE;$0059;}}; + words{{$00B0;}}; // ACDC parms + words{{$0056;$0060;$001F0;}}; // AMD params + + words{{((defmBounds_RSVGA*4)/32)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RSVGA*4)/8));}}; // SkipFactor + +// Eight bit mode parameters +// + words{{$00D0;$0600;$0030;}}; // DAFB parms + words{{$01C6;$0100;$001C;$01FF;$0037;$003D;}}; // Dynamic Swatch parms + words{{$004F;$0063;$01F3;$01FE;$005F;}}; + words{{$00B8;}}; // ACDC parms + words{{$005C;$0060;$01F0;}}; // AMD params + + words{{((defmBounds_RSVGA*8)/32)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RSVGA*8)/8));}}; // SkipFactor + +// Sixteen bit mode parameters +// + words{{$01A0;$06FF;$0031;}}; // DAFB parms + words{{$01C6;$0100;$001C;$01FF;$0037;$003D;}}; // Dynamic Swatch parms + words{{$004F;$0060;$01F0;$01FE;$005F;}}; + words{{$00BE;}}; // ACDC parms + words{{$0060;$0060;$01F0;}}; // AMD params + + words{{((defmBounds_RSVGA*16)/32)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1664_RB-((defmBounds_RSVGA*16)/8));}}; // SkipFactor + +// Thirty-two bit mode parameters +// + words{{$0340;$0000;$0031;}}; // DAFB parms + words{{$038C;$0200;$0038;$03FF;$006F;$007B;}}; // Dynamic Swatch parms + words{{$009F;$00C9;$03E9;$03FE;$00C8;}}; + words{{$003C;}}; // ACDC parms + words{{$00C3;$00C3;$03E3;}}; // AMD params + + words{{((defmBounds_RSVGA*32)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_3328_RB-((defmBounds_RSVGA*32)/8));}}; // SkipFactor +}}; + + + +// +// NTSC (Safe Title) Display parameters +// +resource 'node' (2805, "_sVidParms_DAFB_NTSCST") {{ + blocksize{}; // block size + +// Clock chip params +// + bytes{{$0C;$01;$02;$00;$07;$03;$00;$00;$00;$04;}}; // 8531 chip parms + words{{$1C05;$C1A0;$3600;}}; // 8534 chip parms + +// Misc params +// + bytes{{FifthVidMode;SixthVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BNTSCST-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$020D;$020C;$0005;$000B;$0023;$0203;$0206;}}; // Static Swatch params + +// One bit mode params +// + words{{$0200;$061E;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0072;$02F2;$030A;$0814;}}; + words{{$0080;}}; // ACDC params + words{{$080F;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCST*1)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*1)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*1)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*1)/8));}}; // SkipFactor + +// Two bit mode params +// + words{{$0200;$060E;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0072;$02F2;$030A;$0844;}}; + words{{$0088;}}; // ACDC params + words{{$083F;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCST*2)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*2)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*2)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*2)/8));}}; // SkipFactor + +// Four bit mode params +// + words{{$0200;$0606;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0072;$02F2;$030A;$085C;}}; + words{{$0090;}}; // ACDC params + words{{$0857;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCST*4)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*4)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*4)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*4)/8));}}; // SkipFactor + +// Eight bit mode params +// + words{{$0200;$0602;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0072;$02F2;$030A;$0868;}}; + words{{$0098;}}; // ACDC params + words{{$0863;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCST*8)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*8)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*8)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*8)/8));}}; // SkipFactor + +// Sixteen bit mode params +// + words{{$0400;$0600;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$006D;$02ED;$030A;$0869;}}; + words{{$009E;}}; // ACDC params + words{{$0869;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCST*16)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*16)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*16)/32;}}; // BorderSide + words{{(DAFB_2048_RB-((defmBounds_RNTSCFF*16)/8));}}; // SkipFactor + +// Thirty-two bit mode params +// + words{{$0800;$06FF;$0076;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0073;$02F3;$030A;$0873;}}; + words{{$009C;}}; // ACDC params + words{{$086D;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCST*32)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*32)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*32)/32;}}; // BorderSide + words{{(DAFB_4096_RB-((defmBounds_RNTSCFF*32)/8));}}; // SkipFactor +}}; + + + +// +// NTSC (Full Frame) Display parameters +// +resource 'node' (2810, "_sVidParms_DAFB_NTSCFF") {{ + blocksize{}; // block size + +// Clock chip params +// + bytes{{$0C;$01;$02;$00;$07;$03;$00;$00;$00;$04;}}; // 8531 chip parms + words{{$1C05;$C1A0;$3600;}}; // 8534 chip parms + +// Misc params +// + bytes{{FifthVidMode;SixthVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BNTSCFF-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$020D;$020C;$0005;$000B;$0023;$0203;$0206;}}; // Static Swatch params + +// One bit mode params +// + words{{$0200;$061E;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0072;$02F2;$030A;$0814;}}; + words{{$0080;}}; // ACDC params + words{{$080F;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCFF*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*1)/8));}}; // SkipFactor + +// Two bit mode params +// + words{{$0200;$060E;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0072;$02F2;$030A;$0844;}}; + words{{$0088;}}; // ACDC params + words{{$083F;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCFF*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*2)/8));}}; // SkipFactor + +// Four bit mode params +// + words{{$0200;$0606;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0072;$02F2;$030A;$085C;}}; + words{{$0090;}}; // ACDC params + words{{$0857;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCFF*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*4)/8));}}; // SkipFactor + +// Eight bit mode params +// + words{{$0200;$0602;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0072;$02F2;$030A;$0868;}}; + words{{$0098;}}; // ACDC params + words{{$0863;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCFF*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*8)/8));}}; // SkipFactor + +// Sixteen bit mode params +// + words{{$0400;$0600;$0074;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$006D;$02ED;$030A;$0869;}}; + words{{$009E;}}; // ACDC params + words{{$0869;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCFF*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_2048_RB-((defmBounds_RNTSCFF*16)/8));}}; // SkipFactor + +// Thirty-two bit mode params +// + words{{$0800;$06FF;$0076;}}; // DAFB params + words{{$014C;$0186;$001D;$030B;$0039;$003F;}}; // Dynamic Swatch params + words{{$0062;$0073;$02F3;$030A;$0873;}}; + words{{$009C;}}; // ACDC params + words{{$086D;$006D;$02ED;}}; // AMD params + + words{{((defmBounds_RNTSCFF*32)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_4096_RB-((defmBounds_RNTSCFF*32)/8));}}; // SkipFactor +}}; + + + +// +// NTSC (Safe Title Convolved) Display parameters +// +resource 'node' (2815, "_sVidParms_DAFB_NTSCconvST") {{ + blocksize{}; // block size + +// Clock chip params +// + bytes{{$0C;$01;$02;$00;$07;$03;$00;$00;}}; // Clock chip parms + bytes{{$00;$02;$05;$06;$04;$01;$00;$00;}}; + +// Misc params +// + bytes{{FourthVidMode-FirstVidMode;FourthVidMode-FirstVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BNTSCST-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$020D;$020C;$0005;$000B;$0023;$0203;$0206;}}; // Static Swatch params + +// One bit mode params +// + words{{$0200;$060E;$007C;}}; // DAFB params + words{{$0298;$030C;$003A;$0617;$0073;$007F;}}; // Dynamic Swatch params + words{{$00B1;$00BE;$05EC;$0616;$08A0;}}; + words{{$00A1;}}; // ACDC params + words{{$089C;$00BA;$05BA;}}; // AMD params + + words{{((defmBounds_RNTSCST*1)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*1)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*1)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*1)/8));}}; // SkipFactor + +// Two bit mode params +// + words{{$0200;$0606;$007C;}}; // DAFB params + words{{$0298;$030C;$003A;$0617;$0073;$007F;}}; // Dynamic Swatch params + words{{$00B1;$00D6;$05EC;$0616;$08C8;}}; + words{{$00A9;}}; // ACDC params + words{{$08C4;$00D2;$05D2;}}; // AMD params + + words{{((defmBounds_RNTSCST*2)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*2)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*2)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*2)/8));}}; // SkipFactor + +// Four bit mode params +// + words{{$0200;$0602;$007C;}}; // DAFB params + words{{$0298;$030C;$003A;$0617;$0073;$007F;}}; // Dynamic Swatch params + words{{$00B1;$00E2;$05EC;$0616;$08DC;}}; + words{{$00B1;}}; // ACDC params + words{{$08D8;$00DE;$05DE;}}; // AMD params + + words{{((defmBounds_RNTSCST*4)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*4)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*4)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*4)/8));}}; // SkipFactor + +// Eight bit mode params +// + words{{$0200;$0600;$007C;}}; // DAFB params + words{{$0298;$030C;$003A;$0617;$0073;$007F;}}; // Dynamic Swatch params + words{{$00B1;$00E8;$05EC;$0616;$08E6;}}; + words{{$00B9;}}; // ACDC params + words{{$08E2;$00E4;$05E4;}}; // AMD params + + words{{((defmBounds_RNTSCST*8)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BNTSCFF-defmBounds_BNTSCST)/2;}}; // BorderHeight + words{{((defmBounds_RNTSCFF*8)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RNTSCFF-defmBounds_RNTSCST)/2)*8)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*8)/8));}}; // SkipFactor +}}; + + + +// +// NTSC (Full Frame Convolved) Display parameters +// +resource 'node' (2820, "_sVidParms_DAFB_NTSCconvFF") {{ + blocksize{}; // block size + +// Clock chip params +// + bytes{{$0C;$01;$02;$00;$07;$03;$00;$00;}}; // Clock chip parms + bytes{{$00;$02;$05;$06;$04;$01;$00;$00;}}; + +// Misc params +// + bytes{{FourthVidMode-FirstVidMode;FourthVidMode-FirstVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BNTSCFF-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$020D;$020C;$0005;$000B;$0023;$0203;$0206;}}; // Static Swatch params + +// One bit mode params +// + words{{$0200;$060E;$007C;}}; // DAFB params + words{{$0298;$030C;$003A;$0617;$0073;$007F;}}; // Dynamic Swatch params + words{{$00B1;$00BE;$05EC;$0616;$08A0;}}; + words{{$00A1;}}; // ACDC params + words{{$089C;$00BA;$05BA;}}; // AMD params + + words{{((defmBounds_RNTSCFF*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*1)/8));}}; // SkipFactor + +// Two bit mode params +// + words{{$0200;$0606;$007C;}}; // DAFB params + words{{$0298;$030C;$003A;$0617;$0073;$007F;}}; // Dynamic Swatch params + words{{$00B1;$00D6;$05EC;$0616;$08C8;}}; + words{{$00A9;}}; // ACDC params + words{{$08C4;$00D2;$05D2;}}; // AMD params + + words{{((defmBounds_RNTSCFF*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*2)/8));}}; // SkipFactor + +// Four bit mode params +// + words{{$0200;$0602;$007C;}}; // DAFB params + words{{$0298;$030C;$003A;$0617;$0073;$007F;}}; // Dynamic Swatch params + words{{$00B1;$00E2;$05EC;$0616;$08DC;}}; + words{{$00B1;}}; // ACDC params + words{{$08D8;$00DE;$05DE;}}; // AMD params + + words{{((defmBounds_RNTSCFF*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*4)/8));}}; // SkipFactor + +// Eight bit mode params +// + words{{$0200;$0600;$007C;}}; // DAFB params + words{{$0298;$030C;$003A;$0617;$0073;$007F;}}; // Dynamic Swatch params + words{{$00B1;$00E8;$05EC;$0616;$08E6;}}; + words{{$00B9;}}; // ACDC params + words{{$08E2;$00E4;$05E4;}}; // AMD params + + words{{((defmBounds_RNTSCFF*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RNTSCFF*8)/8));}}; // SkipFactor +}}; + + + +// +// PAL (Safe Title) Display parameters +// +resource 'node' (2825, "_sVidParms_DAFB_PALST") {{ + blocksize{}; // block size + +// Clock chip params +// + bytes{{$0D;$09;$01;$00;$06;$04;$00;$01;$01;$03;}}; // 8531 chip params + words{{$1C05;$C0A0;$6E00;}}; + +// Misc params +// + bytes{{FifthVidMode;SixthVidMode;}}; // MaxMode a,b + bytes{{FifthVidMode-FirstVidMode;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BPALST-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$0271;$0270;$0004;$0009;$0027;$0267;$026B;}}; // Static Swatch params + +// One bit mode params +// + words{{$01A0;$061E;$0074;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0092;$0392;$03AE;$0834;}}; + words{{$0000;}}; // ACDC params + words{{$082F;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALST*1)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*1)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*1)/32;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RPALFF*1)/8));}}; // SkipFactor + +// Two bit mode params +// + words{{$01A0;$060E;$0074;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0092;$0392;$03AE;$0864;}}; + words{{$0008;}}; // ACDC params + words{{$085F;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALST*2)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*2)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*2)/32;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RPALFF*2)/8));}}; // SkipFactor + +// Four bit mode params +// + words{{$01A0;$0606;$0074;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0092;$0392;$03AE;$087C;}}; + words{{$0010;}}; // ACDC params + words{{$0877;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALST*4)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*4)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*4)/32;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RPALFF*4)/8));}}; // SkipFactor + +// Eight bit mode params +// + words{{$01A0;$0602;$0074;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0092;$0392;$03AE;$0888;}}; + words{{$0018;}}; // ACDC params + words{{$0883;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALST*8)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*8)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*8)/32;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RPALFF*8)/8));}}; // SkipFactor + +// Sixteen bit mode params +// + words{{$0340;$0600;$0075;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$008D;$038D;$03AE;$0887;}}; + words{{$001E;}}; // ACDC params + words{{$0888;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALST*16)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*16)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*16)/32;}}; // BorderSide + words{{(DAFB_1664_RB-((defmBounds_RPALFF*16)/8));}}; // SkipFactor + +// Thirty-Two bit mode params +// + words{{$0680;$06FF;$0075;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0093;$0393;$03AE;$0892;}}; + words{{$001C;}}; // ACDC params + words{{$088C;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALST*32)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*32)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*32)/32;}}; // BorderSide + words{{(DAFB_3328_RB-((defmBounds_RPALFF*32)/8));}}; // SkipFactor +}}; + + + +// +// PAL (Full Frame) Display parameters +// +resource 'node' (2830, "_sVidParms_DAFB_PALFF") {{ + blocksize{}; // block size + +// Clock chip params +// + bytes{{$0D;$09;$01;$00;$06;$04;$00;$01;$01;$03;}}; // 8531 chip params + words{{$1C05;$C0A0;$6E00;}}; + +// Misc params +// + bytes{{FifthVidMode;SixthVidMode;}}; // MaxMode a,b + bytes{{FifthVidMode-FirstVidMode;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BPALFF-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$0271;$0270;$0004;$0009;$0027;$0267;$026B;}}; // Static Swatch params + +// One bit mode params +// + words{{$01A0;$061E;$0074;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0092;$0392;$03AE;$0834;}}; + words{{$0000;}}; // ACDC params + words{{$082F;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALFF*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RPALFF*1)/8));}}; // SkipFactor + +// Two bit mode params +// + words{{$01A0;$060E;$0074;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0092;$0392;$03AE;$0864;}}; + words{{$0008;}}; // ACDC params + words{{$085F;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALFF*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RPALFF*2)/8));}}; // SkipFactor + +// Four bit mode params +// + words{{$01A0;$0606;$0074;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0092;$0392;$03AE;$087C;}}; + words{{$0010;}}; // ACDC params + words{{$0877;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALFF*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RPALFF*4)/8));}}; // SkipFactor + +// Eight bit mode params +// + words{{$01A0;$0602;$0074;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0092;$0392;$03AE;$0888;}}; + words{{$0018;}}; // ACDC params + words{{$0883;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALFF*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_832_RB-((defmBounds_RPALFF*8)/8));}}; // SkipFactor + +// Sixteen bit mode params +// + words{{$0340;$0600;$0075;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$008D;$038D;$03AE;$0887;}}; + words{{$001E;}}; // ACDC params + words{{$0888;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALFF*16)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1664_RB-((defmBounds_RPALFF*16)/8));}}; // SkipFactor + +// Thirty-Two bit mode params +// + words{{$0680;$06FF;$0075;}}; // DAFB params + words{{$0192;$01D8;$0023;$03AF;$0045;$0049;}}; // Dynamic Swatch params + words{{$006D;$0093;$0393;$03AE;$0892;}}; + words{{$001C;}}; // ACDC params + words{{$088C;$008D;$038D;}}; // AMD params + + words{{((defmBounds_RPALFF*32)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_3328_RB-((defmBounds_RPALFF*32)/8));}}; // SkipFactor +}}; + + + +// +// PAL (Safe Title Convolved) Display parameters +// +resource 'node' (2835, "_sVidParms_DAFB_PALconvST") {{ + blocksize{}; // block size + +// Clock chip params +// + bytes{{$0D;$09;$01;$00;$06;$04;$00;$01;}}; // Clock chip params + bytes{{$01;$01;$05;$06;$00;$01;$00;$00;}}; + +// Misc params +// + bytes{{FourthVidMode-FirstVidMode;FourthVidMode-FirstVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BPALST-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$0271;$0270;$0004;$0009;$0027;$0267;$026B;}}; // Static Swatch params + +// One bit mode params +// + words{{$0200;$060E;$007C;}}; // DAFB params + words{{$0324;$03B0;$0046;$075F;$008B;$0093;}}; // Dynamic Swatch params + words{{$00DB;$00FE;$072C;$075E;$08E0;}}; + words{{$0021;}}; // ACDC params + words{{$08DC;$00FA;$06FA;}}; // AMD params + + words{{((defmBounds_RPALST*1)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*1)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*1)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RPALFF*1)/8));}}; // SkipFactor + +// Two bit mode params +// + words{{$0200;$0606;$007C;}}; // DAFB params + words{{$0324;$03B0;$0046;$075F;$008B;$0093;}}; // Dynamic Swatch params + words{{$00DB;$0116;$072C;$075E;$0908;}}; + words{{$0029;}}; // ACDC params + words{{$0904;$0112;$0712;}}; // AMD params + + words{{((defmBounds_RPALST*2)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*2)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*2)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RPALFF*2)/8));}}; // SkipFactor + +// Four bit mode params +// + words{{$0200;$0602;$007C;}}; // DAFB params + words{{$0324;$03B0;$0046;$075F;$008B;$0093;}}; // Dynamic Swatch params + words{{$00DB;$0122;$072C;$075E;$091C;}}; + words{{$0031;}}; // ACDC params + words{{$0918;$011E;$071E;}}; // AMD params + + words{{((defmBounds_RPALST*4)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*4)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*4)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RPALFF*4)/8));}}; // SkipFactor + +// Eight bit mode params +// + words{{$0200;$0600;$007C;}}; // DAFB params + words{{$0324;$03B0;$0046;$075F;$008B;$0093;}}; // Dynamic Swatch params + words{{$00DB;$0128;$072C;$075E;$0926;}}; + words{{$0039;}}; // ACDC params + words{{$0922;$0124;$0724;}}; // AMD params + + words{{((defmBounds_RPALST*8)/64)-1;}}; // ActiveWidth + words{{(defmBounds_BPALFF-defmBounds_BPALST)/2;}}; // BorderHeight + words{{((defmBounds_RPALFF*8)/32)-1;}}; // BorderWidth + words{{(((defmBounds_RPALFF-defmBounds_RPALST)/2)*8)/32;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RPALFF*8)/8));}}; // SkipFactor +}}; + + + +// +// PAL (Full Frame Convolved) Display parameters +// +resource 'node' (2840, "_sVidParms_DAFB_PALconvFF") {{ + blocksize{}; // block size + +// Clock chip params +// + bytes{{$0D;$09;$01;$00;$06;$04;$00;$01;}}; // Clock chip params + bytes{{$01;$01;$05;$06;$00;$01;$00;$00;}}; + +// Misc params +// + bytes{{FourthVidMode-FirstVidMode;FourthVidMode-FirstVidMode;}}; // MaxMode a,b + bytes{{-1;-1;}}; // Non-Wombat AMD TimingAdj Fudge + words{{defmBounds_BPALFF-1;}}; // ActiveHeight + +// Static DAFB params +// + words{{$0271;$0270;$0004;$0009;$0027;$0267;$026B;}}; // Static Swatch params. + +// One bit mode params +// + words{{$0200;$060E;$007C;}}; // DAFB params + words{{$0324;$03B0;$0046;$075F;$008B;$0093;}}; // Dynamic Swatch params + words{{$00DB;$00FE;$072C;$075E;$08E0;}}; + words{{$0021;}}; // ACDC params + words{{$08DC;$00FA;$06FA;}}; // AMD params + + words{{((defmBounds_RPALFF*1)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RPALFF*1)/8));}}; // SkipFactor + +// Two bit mode params +// + words{{$0200;$0606;$007C;}}; // DAFB params + words{{$0324;$03B0;$0046;$075F;$008B;$0093;}}; // Dynamic Swatch params + words{{$00DB;$0116;$072C;$075E;$0908;}}; + words{{$0029;}}; // ACDC params + words{{$0904;$0112;$0712;}}; // AMD params + + words{{((defmBounds_RPALFF*2)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RPALFF*2)/8));}}; // SkipFactor + +// Four bit mode params +// + words{{$0200;$0602;$007C;}}; // DAFB params + words{{$0324;$03B0;$0046;$075F;$008B;$0093;}}; // Dynamic Swatch params + words{{$00DB;$0122;$072C;$075E;$091C;}}; + words{{$0031;}}; // ACDC params + words{{$0918;$011E;$071E;}}; // AMD params + + words{{((defmBounds_RPALFF*4)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RPALFF*4)/8));}}; // SkipFactor + +// Eight bit mode params +// + words{{$0200;$0600;$007C;}}; // DAFB params + words{{$0324;$03B0;$0046;$075F;$008B;$0093;}}; // Dynamic Swatch params + words{{$00DB;$0128;$072C;$075E;$0926;}}; + words{{$0039;}}; // ACDC params + words{{$0922;$0124;$0724;}}; // AMD params + + words{{((defmBounds_RPALFF*8)/64)-1;}}; // ActiveWidth + words{{0;}}; // BorderHeight + words{{0-1;}}; // BorderWidth + words{{0;}}; // BorderSide + words{{(DAFB_1024_RB-((defmBounds_RPALFF*8)/8));}}; // SkipFactor +}}; + + +//------------------------------------------------------------- +// One-Bit per pixel parameters +//------------------------------------------------------------- + +resource 'vmod' (3180, "_OBMHR") {{ + mVidParams, l{"_OBVParmsHR"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3185, "_OBMHR400") {{ + mVidParams, l{"_OBVParmsHR400"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + +resource 'vmod' (3187, "_OBMHR399") {{ + mVidParams, l{"_OBVParmsHR399"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3190, "_OBMFP") {{ + mVidParams, l{"_OBVParmsFP"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesFP}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3195, "_OBMGS") {{ + mVidParams, l{"_OBVParmsGS"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3200, "_OBMGS560") {{ + mVidParams, l{"_OBVParmsGS560"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3205, "_OBMGF") {{ + mVidParams, l{"_OBVParmsGF"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesGF}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3210, "_OBMSE") {{ + mVidParams, l{"_OBVParmsSE"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesSE}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3215, "_OBM_V8_HRa") {{ + mVidParams, l{"_OBVParms_V8_HRa"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3220, "_OBM_V8_HRb") {{ + mVidParams, l{"_OBVParms_V8_HRb"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3225, "_OBM_V8_GSa") {{ + mVidParams, l{"_OBVParms_V8_GSa"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3230, "_OBM_V8_GSb") {{ + mVidParams, l{"_OBVParms_V8_GSb"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3235, "_OBM_V8_A2Ema") {{ + mVidParams, l{"_OBVParms_V8_A2Em"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesA2Em}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3240, "_OBM_V8_A2Emb") {{ + mVidParams, l{"_OBVParms_V8_A2Em"}; // offset to vid parameters for this configuration + mPageCnt, d{OBMPagesA2Em}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'node' (3245, "_OBM_Civic_19") {{ + include{l{"_OBM_DAFB_19"}}; +}}; + +resource 'vmod' (3250, "_OBM_DAFB_19") {{ + mVidParams, l{"_OBVParms_DAFB_19"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3255, "_OBM_Civic_FP") {{ + include{l{"_OBM_DAFB_FP"}}; +}}; + +resource 'vmod' (3260, "_OBM_DAFB_FP") {{ + mVidParams, l{"_OBVParms_DAFB_FP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3265, "_OBM_Civic_2P") {{ + mVidParams, l{"_OBVParms_Civic_2P"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3270, "_OBM_Civic_vi2P") {{ + include{l{"_OBM_DAFB_2P"}}; +}}; + +resource 'vmod' (3275, "_OBM_DAFB_2P") {{ + mVidParams, l{"_OBVParms_DAFB_2P"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3280, "_OBM_Civic_GF") {{ + include{l{"_OBM_DAFB_LP"}}; +}}; + +resource 'vmod' (3285, "_OBM_DAFB_LP") {{ + mVidParams, l{"_OBVParms_DAFB_LP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3290, "_OBM_Civic_NTSCSTConv") {{ + include{l{"_OBM_Civic_NTSCST"}}; +}}; + +resource 'node' (3295, "_OBM_Civic_NTSCST") {{ + include{l{"_OBM_Civic_GS"}}; +}}; + +resource 'node' (3300, "_OBM_Civic_GS") {{ + include{l{"_OBM_DAFB_GS"}}; +}}; + +resource 'vmod' (3305, "_OBM_DAFB_GS") {{ + mVidParams, l{"_OBVParms_DAFB_GS"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3310, "_OBM_Civic_GS560") {{ + mVidParams, l{"_OBVParms_Civic_GS560"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3315, "_OBM_Civic_PALSTConv") {{ + include{l{"_OBM_Civic_PALST"}}; +}}; + +resource 'node' (3320, "_OBM_Civic_PALST") {{ + include{l{"_OBM_Civic_NTSCFFconv"}}; +}}; + +resource 'node' (3325, "_OBM_Civic_NTSCFFconv") {{ + include{l{"_OBM_Civic_NTSCFF"}}; +}}; + +resource 'node' (3330, "_OBM_Civic_NTSCFF") {{ + include{l{"_OBM_Civic_VGA"}}; +}}; + +resource 'node' (3335, "_OBM_Civic_VGA") {{ + include{l{"_OBM_Civic_HR"}}; +}}; + +resource 'node' (3340, "_OBM_Civic_HR") {{ + include{l{"_OBM_DAFB_NTSCFF"}}; +}}; + +resource 'node' (3345, "_OBM_DAFB_NTSCFF") {{ + include{l{"_OBM_DAFB_NTSCFFconv"}}; +}}; + +resource 'node' (3350, "_OBM_DAFB_NTSCFFconv") {{ + include{l{"_OBM_DAFB_VGA"}}; +}}; + +resource 'node' (3355, "_OBM_DAFB_VGA") {{ + include{l{"_OBM_DAFB_HR"}}; +}}; + +resource 'vmod' (3360, "_OBM_DAFB_HR") {{ + mVidParams, l{"_OBVParms_DAFB_640by480"}; // a number of different modes share this mVidParams block + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3365, "_OBM_Civic_HR400") {{ + mVidParams, l{"_OBVParms_Civic_HR400"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3370, "_OBM_Civic_HRMAZ") {{ + mVidParams, l{"_OBVParms_Civic_HRMAZ"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3375, "_OBM_Civic_SVGA") {{ + include{l{"_OBM_DAFB_SVGA"}}; +}}; + +resource 'vmod' (3380, "_OBM_DAFB_SVGA") {{ + mVidParams, l{"_OBVParms_DAFB_SVGA"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3385, "_OBM_DAFB_NTSCST") {{ + include{l{"_OBM_DAFB_NTSCSTconv"}}; +}}; + +resource 'vmod' (3390, "_OBM_DAFB_NTSCSTconv") {{ + mVidParams, l{"_OBVParms_DAFB_NTSCST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3395, "_OBM_DAFB_PALST") {{ + mVidParams, l{"_OBVParms_DAFB_PALST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3400, "_OBM_DAFB_PALSTconv") {{ + mVidParams, l{"_OBVParms_DAFB_PALSTconv"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3405, "_OBM_Civic_PALFF") {{ + include{l{"_OBM_DAFB_PALFF"}}; +}}; + +resource 'vmod' (3410, "_OBM_DAFB_PALFF") {{ + mVidParams, l{"_OBVParms_DAFB_PALFF"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3415, "_OBM_Civic_PALFFConv") {{ + include{l{"_OBM_DAFB_PALFFconv"}}; +}}; + +resource 'vmod' (3420, "_OBM_DAFB_PALFFconv") {{ + mVidParams, l{"_OBVParms_DAFB_PALFFconv"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3425, "_OBMLCD") {{ + mVidParams, l{"_OBVParmsLCD"}; // offset to vid parameters for this configuration + mTable, l{"_OBVFixedCLUTLCD"}; // offset to device color table (fixed device) + mPageCnt, d{OBMPagesLCD}; // number of video pages in this configuration + mDevType, d{fixedType}; // device type +}}; + +resource 'vmod' (3430, "_OBMLCD480") {{ + mVidParams, l{"_OBVParmsHR"}; // offset to vid parameters for this configuration + mTable, l{"_OBVFixedCLUTLCD"}; // offset to device color table (fixed device) + mPageCnt, d{OBMPagesLCD}; // number of video pages in this configuration + mDevType, d{fixedType}; // device type +}}; + + +resource 'vmod' (3435, "_OBMApollo") {{ + mVidParams, l{"_OBVParmsApollo"}; // offset to vid parameters for this configuration + mTable, l{"_OBVFixedCLUTApollo"}; // offset to device color table (fixed device) + mPageCnt, d{OBMPagesApollo}; // number of video pages in this configuration + mDevType, d{fixedType}; // device type +}}; + + +// Fixed CLUTs… +// +resource 'node' (3440, "_OBVFixedCLUTApollo") {{ + include{l{"_OBVFixedCLUTLCD"}}; +}}; + +resource 'node' (3445, "_OBVFixedCLUTLCD") {{ + include{l{"_OBVFixedCLUT"}}; +}}; + +resource 'node' (3450, "_OBVFixedCLUT") {{ + blocksize{}; // Physical Block Size. + + longs{{32+1;}}; // ctSeed + words{{$0000;}}; // ctFlags + words{{$0001;}}; // ctSize (n - 1) + + words{{$0000;$FFFF;$FFFF;$FFFF;}}; // value, r,g,b (white entry). + words{{$0001;$0000;$0000;$0000;}}; // value, r,g,b (black entry). +}}; + + + +// VidParams… +// +resource 'node' (3455, "_OBVParmsHR") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{OBMHRRB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3460, "_OBVParmsHR400") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{OBMHRRB;}}; // physRowBytes + words{{defmBounds_THR400;defmBounds_LHR400;defmBounds_BHR400;defmBounds_RHR400;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + +resource 'node' (3462, "_OBVParmsHR399") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{OBMHRRB;}}; // physRowBytes + words{{defmBounds_THR399;defmBounds_LHR399;defmBounds_BHR399;defmBounds_RHR399;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3465, "_OBVParmsFP") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{OBMFPRB;}}; // physRowBytes + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; // bmHRes + longs{{VResFP;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3470, "_OBVParmsGS") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{OBMGSRB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3475, "_OBVParmsGS560") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{OBMGS560RB;}}; // physRowBytes + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3480, "_OBVParmsGF") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{OBMGFRB;}}; // physRowBytes + words{{defmBounds_TGF;defmBounds_LGF;defmBounds_BGF;defmBounds_RGF;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGF;}}; // bmHRes + longs{{VResGF;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3485, "_OBVParmsSE") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{OBMSERB;}}; // physRowBytes + words{{defmBounds_TSE;defmBounds_LSE;defmBounds_BSE;defmBounds_RSE;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResSE;}}; // bmHRes + longs{{VResSE;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3490, "_OBVParms_DAFB_640by480") {{ + include{l{"_OBVParms_V8_HRa"}}; +}}; + +resource 'node' (3495, "_OBVParms_V8_HRa") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3500, "_OBVParms_V8_HRb") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3505, "_OBVParms_DAFB_GS") {{ + include{l{"_OBVParms_V8_GSa"}}; +}}; + +resource 'node' (3510, "_OBVParms_V8_GSa") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3515, "_OBVParms_V8_GSb") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3520, "_OBVParms_V8_A2Em") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_TA2Em;defmBounds_LA2Em;defmBounds_BA2Em;defmBounds_RA2Em;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3525, "_OBVParms_DAFB_19") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_512_RB;}}; + words{{defmBounds_T19;defmBounds_L19;defmBounds_B19;defmBounds_R19;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes19;}}; + longs{{VRes19;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3530, "_OBVParms_DAFB_FP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_512_RB;}}; + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; + longs{{VResFP;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3535, "_OBVParms_Civic_2P") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1152_RB;}}; + words{{defmBounds_T2P;defmBounds_L2P;defmBounds_B2P;defmBounds_R2P;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes2P;}}; + longs{{VRes2P;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3540, "_OBVParms_DAFB_2P") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_576_RB;}}; + words{{defmBounds_T2P;defmBounds_L2P;defmBounds_B2P;defmBounds_R2P;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes2P;}}; + longs{{VRes2P;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3545, "_OBVParms_DAFB_LP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TLP;defmBounds_LLP;defmBounds_BLP;defmBounds_RLP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResLP;}}; + longs{{VResLP;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3550, "_OBVParms_Civic_GS560") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1024_RB;}}; + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; + longs{{VResGS;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3555, "_OBVParms_Civic_HR400") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1024_RB;}}; + words{{0;0;400;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3560, "_OBVParms_Civic_HRMAZ") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_832_RB;}}; + words{{0;0;512;704;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3565, "_OBVParms_DAFB_SVGA") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TSVGA;defmBounds_LSVGA;defmBounds_BSVGA;defmBounds_RSVGA;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3570, "_OBVParms_DAFB_NTSCST") {{ + blocksize{}; + longs{{defmNTSCSTB1;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TNTSCST;defmBounds_LNTSCST;defmBounds_BNTSCST;defmBounds_RNTSCST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResNTSC;}}; + longs{{VResNTSC;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3575, "_OBVParms_DAFB_PALST") {{ + blocksize{}; + longs{{defmPALSTB1;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3580, "_OBVParms_DAFB_PALFF") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3585, "_OBVParms_DAFB_PALSTconv") {{ + blocksize{}; + longs{{defmPALSTB1Conv;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3590, "_OBVParms_DAFB_PALFFconv") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{1;}}; + words{{defCmpCount;}}; + words{{1;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3595, "_OBVParmsLCD") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{OBMLCDRB;}}; // physRowBytes + words{{defmBounds_TLCD;defmBounds_LLCD;defmBounds_BLCD;defmBounds_RLCD;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResLCD;}}; // bmHRes + longs{{VResLCD;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3605, "_OBVParmsApollo") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{OBMApolloRB;}}; // physRowBytes + words{{defmBounds_TApollo;defmBounds_LApollo;defmBounds_BApollo;defmBounds_RApollo;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResApollo;}}; // bmHRes + longs{{VResApollo;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{1;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{1;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +//------------------------------------------------------------- +// Two-Bit per pixel parameters +//------------------------------------------------------------- + +resource 'vmod' (3610, "_TBMHR") {{ + mVidParams, l{"_TBVParmsHR"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3615, "_TBMHR400") {{ + mVidParams, l{"_TBVParmsHR400"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + +resource 'vmod' (3617, "_TBMHR399") {{ + mVidParams, l{"_TBVParmsHR399"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3620, "_TBMFP") {{ + mVidParams, l{"_TBVParmsFP"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesFP}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3625, "_TBMGS") {{ + mVidParams, l{"_TBVParmsGS"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3630, "_TBMGS560") {{ + mVidParams, l{"_TBVParmsGS560"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3635, "_TBMGF") {{ + mVidParams, l{"_TBVParmsGF"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesGF}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3640, "_TBMSE") {{ + mVidParams, l{"_TBVParmsSE"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesSE}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3645, "_TBM_V8_HRa") {{ + mVidParams, l{"_TBVParms_V8_HRa"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3650, "_TBM_V8_HRb") {{ + mVidParams, l{"_TBVParms_V8_HRb"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3655, "_TBM_V8_GSa") {{ + mVidParams, l{"_TBVParms_V8_GSa"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3660, "_TBM_V8_GSb") {{ + mVidParams, l{"_TBVParms_V8_GSb"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3665, "_TBM_V8_A2Ema") {{ + mVidParams, l{"_TBVParms_V8_A2Ema"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesA2Em}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3670, "_TBM_V8_A2Emb") {{ + mVidParams, l{"_TBVParms_V8_A2Emb"}; // offset to vid parameters for this configuration + mPageCnt, d{TBMPagesA2Em}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (3675, "_TBM_Civic_19") {{ + mVidParams, l{"_TBVParms_Civic_19"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + +resource 'vmod' (3680, "_TBM_DAFB_19") {{ + mVidParams, l{"_TBVParms_DAFB_19"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3685, "_TBM_Civic_FP") {{ + include{l{"_TBM_DAFB_FP"}}; +}}; + +resource 'vmod' (3690, "_TBM_DAFB_FP") {{ + mVidParams, l{"_TBVParms_DAFB_FP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3695, "_TBM_Civic_2P") {{ + mVidParams, l{"_TBVParms_Civic_2P"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3700, "_TBM_Civic_vi2P") {{ + include{l{"_TBM_DAFB_2P"}}; +}}; + +resource 'vmod' (3705, "_TBM_DAFB_2P") {{ + mVidParams, l{"_TBVParms_DAFB_2P"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3710, "_TBM_Civic_GF") {{ + include{l{"_TBM_DAFB_LP"}}; +}}; + +resource 'vmod' (3715, "_TBM_DAFB_LP") {{ + mVidParams, l{"_TBVParms_DAFB_LP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3720, "_TBM_Civic_NTSCSTconv") {{ + include{l{"_TBM_Civic_NTSCST"}}; +}}; + +resource 'node' (3725, "_TBM_Civic_NTSCST") {{ + include{l{"_TBM_Civic_GS"}}; +}}; + +resource 'node' (3730, "_TBM_Civic_GS") {{ + include{l{"_TBM_DAFB_GS"}}; +}}; + +resource 'vmod' (3735, "_TBM_DAFB_GS") {{ + mVidParams, l{"_TBVParms_DAFB_GS"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3740, "_TBM_Civic_GS560") {{ + mVidParams, l{"_TBVParms_Civic_GS560"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3745, "_TBM_Civic_PALSTConv") {{ + include{l{"_TBM_Civic_PALST"}}; +}}; + +resource 'node' (3750, "_TBM_Civic_PALST") {{ + include{l{"_TBM_Civic_NTSCFFConv"}}; +}}; + +resource 'node' (3755, "_TBM_Civic_NTSCFFConv") {{ + include{l{"_TBM_Civic_NTSCFF"}}; +}}; + +resource 'node' (3760, "_TBM_Civic_NTSCFF") {{ + include{l{"_TBM_Civic_VGA"}}; +}}; + +resource 'node' (3765, "_TBM_Civic_VGA") {{ + include{l{"_TBM_Civic_HR"}}; +}}; + +resource 'node' (3770, "_TBM_Civic_HR") {{ + include{l{"_TBM_DAFB_NTSCFF"}}; +}}; + +resource 'node' (3775, "_TBM_DAFB_NTSCFF") {{ + include{l{"_TBM_DAFB_NTSCFFconv"}}; +}}; + +resource 'node' (3780, "_TBM_DAFB_NTSCFFconv") {{ + include{l{"_TBM_DAFB_VGA"}}; +}}; + +resource 'node' (3785, "_TBM_DAFB_VGA") {{ + include{l{"_TBM_DAFB_HR"}}; +}}; + +resource 'vmod' (3790, "_TBM_DAFB_HR") {{ + mVidParams, l{"_TBVParms_DAFB_640by480"}; // a number of different modes share this mVidParams block + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3795, "_TBM_Civic_HR400") {{ + mVidParams, l{"_TBVParms_Civic_HR400"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3800, "_TBM_Civic_HRMAZ") {{ + mVidParams, l{"_TBVParms_Civic_HRMAZ"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3805, "_TBM_Civic_SVGA") {{ + include{l{"_TBM_DAFB_SVGA"}}; +}}; + +resource 'vmod' (3810, "_TBM_DAFB_SVGA") {{ + mVidParams, l{"_TBVParms_DAFB_SVGA"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3815, "_TBM_DAFB_NTSCST") {{ + include{l{"_TBM_DAFB_NTSCSTconv"}}; +}}; + +resource 'vmod' (3820, "_TBM_DAFB_NTSCSTconv") {{ + mVidParams, l{"_TBVParms_DAFB_NTSCST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3825, "_TBM_DAFB_PALST") {{ + mVidParams, l{"_TBVParms_DAFB_PALST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3830, "_TBM_DAFB_PALSTconv") {{ + mVidParams, l{"_TBVParms_DAFB_PALSTconv"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3835, "_TBM_Civic_PALFF") {{ + include{l{"_TBM_DAFB_PALFF"}}; +}}; + +resource 'vmod' (3840, "_TBM_DAFB_PALFF") {{ + mVidParams, l{"_TBVParms_DAFB_PALFF"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (3845, "_TBM_Civic_PALFFConv") {{ + include{l{"_TBM_DAFB_PALFFconv"}}; +}}; + +resource 'vmod' (3850, "_TBM_DAFB_PALFFconv") {{ + mVidParams, l{"_TBVParms_DAFB_PALFFconv"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (3855, "_TBMLCD") {{ + mVidParams, l{"_TBVParmsLCD"}; // offset to vid parameters for this configuration + mTable, l{"_TBVFixedCLUTLCD"}; // offset to device color table (fixed device) + mPageCnt, d{TBMPagesLCD}; // number of video pages in this configuration + mDevType, d{fixedType}; // device type +}}; + +resource 'vmod' (3860, "_TBMLCD480") {{ + mVidParams, l{"_TBVParmsHR"}; // offset to vid parameters for this configuration + mTable, l{"_TBVFixedCLUTLCD"}; // offset to device color table (fixed device) + mPageCnt, d{TBMPagesLCD}; // number of video pages in this configuration + mDevType, d{fixedType}; // device type +}}; + + +// Fixed CLUTs… +// +resource 'node' (3865, "_TBVFixedCLUTLCD") {{ + blocksize{}; // Physical Block Size. + + longs{{32+2;}}; // ctSeed + words{{$0000;}}; // ctFlags + words{{$0003;}}; // ctSize (n - 1) + + words{{$0000;$FFFF;$FFFF;$FFFF;}}; // value, r,g,b (white entry). + words{{$0001;$AAAA;$AAAA;$AAAA;}}; // value, r,g,b (ltGray entry). + words{{$0002;$5555;$5555;$5555;}}; // value, r,g,b (dkGray entry). + words{{$0003;$0000;$0000;$0000;}}; // value, r,g,b (black entry). +}}; + + + +resource 'node' (3870, "_TBVParmsHR") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{TBMHRRB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3875, "_TBVParmsHR400") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{TBMHRRB;}}; // physRowBytes + words{{defmBounds_THR400;defmBounds_LHR400;defmBounds_BHR400;defmBounds_RHR400;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + +resource 'node' (3877, "_TBVParmsHR399") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{TBMHRRB;}}; // physRowBytes + words{{defmBounds_THR399;defmBounds_LHR399;defmBounds_BHR399;defmBounds_RHR399;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3880, "_TBVParmsFP") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{TBMFPRB;}}; // physRowBytes + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; // bmHRes + longs{{VResFP;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3885, "_TBVParmsGS") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{TBMGSRB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3890, "_TBVParmsGS560") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{TBMGS560RB;}}; // physRowBytes + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3895, "_TBVParmsGF") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{TBMGFRB;}}; // physRowBytes + words{{defmBounds_TGF;defmBounds_LGF;defmBounds_BGF;defmBounds_RGF;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGF;}}; // bmHRes + longs{{VResGF;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3900, "_TBVParmsSE") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{TBMSERB;}}; // physRowBytes + words{{defmBounds_TSE;defmBounds_LSE;defmBounds_BSE;defmBounds_RSE;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResSE;}}; // bmHRes + longs{{VResSE;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3905, "_TBVParms_DAFB_640by480") {{ + include{l{"_TBVParms_V8_HRa"}}; +}}; + +resource 'node' (3910, "_TBVParms_V8_HRa") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3915, "_TBVParms_V8_HRb") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3920, "_TBVParms_DAFB_GS") {{ + include{l{"_TBVParms_V8_GSa"}}; +}}; + +resource 'node' (3925, "_TBVParms_V8_GSa") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3930, "_TBVParms_V8_GSb") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3935, "_TBVParms_V8_A2Ema") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_TA2Em;defmBounds_LA2Em;defmBounds_BA2Em;defmBounds_RA2Em;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3940, "_TBVParms_V8_A2Emb") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_TA2Em;defmBounds_LA2Em;defmBounds_BA2Em;defmBounds_RA2Em;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (3943, "_TBVParms_Civic_19") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_256_RB;}}; + words{{defmBounds_T19;defmBounds_L19;defmBounds_B19;defmBounds_R19;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes19;}}; + longs{{VRes19;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + +resource 'node' (3945, "_TBVParms_DAFB_19") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_512_RB;}}; + words{{defmBounds_T19;defmBounds_L19;defmBounds_B19;defmBounds_R19;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes19;}}; + longs{{VRes19;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + +resource 'node' (3950, "_TBVParms_DAFB_FP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_512_RB;}}; + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; + longs{{VResFP;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3955, "_TBVParms_Civic_2P") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1152_RB;}}; + words{{defmBounds_T2P;defmBounds_L2P;defmBounds_B2P;defmBounds_R2P;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes2P;}}; + longs{{VRes2P;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3960, "_TBVParms_DAFB_2P") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_576_RB;}}; + words{{defmBounds_T2P;defmBounds_L2P;defmBounds_B2P;defmBounds_R2P;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes2P;}}; + longs{{VRes2P;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3965, "_TBVParms_DAFB_LP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TLP;defmBounds_LLP;defmBounds_BLP;defmBounds_RLP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResLP;}}; + longs{{VResLP;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3970, "_TBVParms_Civic_GS560") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1024_RB;}}; + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; + longs{{VResGS;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3975, "_TBVParms_Civic_HR400") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1024_RB;}}; + words{{0;0;400;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3980, "_TBVParms_Civic_HRMAZ") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_832_RB;}}; + words{{0;0;512;704;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3985, "_TBVParms_DAFB_SVGA") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TSVGA;defmBounds_LSVGA;defmBounds_BSVGA;defmBounds_RSVGA;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3990, "_TBVParms_DAFB_NTSCST") {{ + blocksize{}; + longs{{defmNTSCSTB2;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TNTSCST;defmBounds_LNTSCST;defmBounds_BNTSCST;defmBounds_RNTSCST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResNTSC;}}; + longs{{VResNTSC;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (3995, "_TBVParms_DAFB_PALST") {{ + blocksize{}; + longs{{defmPALSTB2;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4000, "_TBVParms_DAFB_PALFF") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4005, "_TBVParms_DAFB_PALSTconv") {{ + blocksize{}; + longs{{defmPALSTB2Conv;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4010, "_TBVParms_DAFB_PALFFconv") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{2;}}; + words{{defCmpCount;}}; + words{{2;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4015, "_TBVParmsLCD") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{TBMLCDRB;}}; // physRowBytes + words{{defmBounds_TLCD;defmBounds_LLCD;defmBounds_BLCD;defmBounds_RLCD;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResLCD;}}; // bmHRes + longs{{VResLCD;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{2;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{2;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +//------------------------------------------------------------- +// Four-Bit per pixel parameters +//------------------------------------------------------------- + +resource 'vmod' (4025, "_FBMHR") {{ + mVidParams, l{"_FBVParmsHR"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4030, "_FBMHR400") {{ + mVidParams, l{"_FBVParmsHR400"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + +resource 'vmod' (4033, "_FBMHR399") {{ + mVidParams, l{"_FBVParmsHR399"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4035, "_FBMFP") {{ + mVidParams, l{"_FBVParmsFP"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesFP}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4040, "_FBMGS") {{ + mVidParams, l{"_FBVParmsGS"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4045, "_FBMGS560") {{ + mVidParams, l{"_FBVParmsGS560"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4050, "_FBMGF") {{ + mVidParams, l{"_FBVParmsGF"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesGF}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4055, "_FBMSE") {{ + mVidParams, l{"_FBVParmsSE"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesSE}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4060, "_FBM_V8_HRa") {{ + mVidParams, l{"_FBVParms_V8_HRa"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4065, "_FBM_V8_HRb") {{ + mVidParams, l{"_FBVParms_V8_HRb"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4070, "_FBM_V8_GSa") {{ + mVidParams, l{"_FBVParms_V8_GSa"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4075, "_FBM_V8_GSb") {{ + mVidParams, l{"_FBVParms_V8_GSb"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4080, "_FBM_V8_A2Ema") {{ + mVidParams, l{"_FBVParms_V8_A2Ema"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesA2Em}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4085, "_FBM_V8_A2Emb") {{ + mVidParams, l{"_FBVParms_V8_A2Emb"}; // offset to vid parameters for this configuration + mPageCnt, d{FBMPagesA2Em}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'node' (4090, "_FBM_Civic_19") {{ + include{l{"_FBM_DAFB_19"}}; +}}; + +resource 'vmod' (4095, "_FBM_DAFB_19") {{ + mVidParams, l{"_FBVParms_DAFB_19"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4100, "_FBM_Civic_FP") {{ + include{l{"_FBM_DAFB_FP"}}; +}}; + +resource 'vmod' (4105, "_FBM_DAFB_FP") {{ + mVidParams, l{"_FBVParms_DAFB_FP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4110, "_FBM_Civic_2P") {{ + mVidParams, l{"_FBVParms_Civic_2P"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4115, "_FBM_Civic_vi2P") {{ + include{l{"_FBM_DAFB_2P"}}; +}}; + +resource 'vmod' (4120, "_FBM_DAFB_2P") {{ + mVidParams, l{"_FBVParms_DAFB_2P"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4125, "_FBM_Civic_GF") {{ + include{l{"_FBM_DAFB_LP"}}; +}}; + +resource 'vmod' (4130, "_FBM_DAFB_LP") {{ + mVidParams, l{"_FBVParms_DAFB_LP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4135, "_FBM_Civic_NTSCSTconv") {{ + include{l{"_FBM_Civic_NTSCST"}}; +}}; + +resource 'node' (4140, "_FBM_Civic_NTSCST") {{ + include{l{"_FBM_Civic_GS"}}; +}}; + +resource 'node' (4145, "_FBM_Civic_GS") {{ + include{l{"_FBM_DAFB_GS"}}; +}}; + +resource 'vmod' (4150, "_FBM_DAFB_GS") {{ + mVidParams, l{"_FBVParms_DAFB_GS"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4155, "_FBM_Civic_GS560") {{ + mVidParams, l{"_FBVParms_Civic_GS560"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4160, "_FBM_Civic_PALSTConv") {{ + include{l{"_FBM_Civic_PALST"}}; +}}; + +resource 'node' (4165, "_FBM_Civic_PALST") {{ + include{l{"_FBM_Civic_NTSCFFConv"}}; +}}; + +resource 'node' (4170, "_FBM_Civic_NTSCFFConv") {{ + include{l{"_FBM_Civic_NTSCFF"}}; +}}; + +resource 'node' (4175, "_FBM_Civic_NTSCFF") {{ + include{l{"_FBM_Civic_VGA"}}; +}}; + +resource 'node' (4180, "_FBM_Civic_VGA") {{ + include{l{"_FBM_Civic_HR"}}; +}}; + +resource 'node' (4185, "_FBM_Civic_HR") {{ + include{l{"_FBM_DAFB_NTSCFF"}}; +}}; + +resource 'node' (4190, "_FBM_DAFB_NTSCFF") {{ + include{l{"_FBM_DAFB_NTSCFFconv"}}; +}}; + +resource 'node' (4195, "_FBM_DAFB_NTSCFFconv") {{ + include{l{"_FBM_DAFB_VGA"}}; +}}; + +resource 'node' (4200, "_FBM_DAFB_VGA") {{ + include{l{"_FBM_DAFB_HR"}}; +}}; + +resource 'vmod' (4205, "_FBM_DAFB_HR") {{ + mVidParams, l{"_FBVParms_DAFB_640by480"}; // a number of different modes share this mVidParams block + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4210, "_FBM_Civic_HR400") {{ + mVidParams, l{"_FBVParms_Civic_HR400"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4215, "_FBM_Civic_HRMAZ") {{ + mVidParams, l{"_FBVParms_Civic_HRMAZ"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4220, "_FBM_Civic_SVGA") {{ + include{l{"_FBM_DAFB_SVGA"}}; +}}; + +resource 'vmod' (4225, "_FBM_DAFB_SVGA") {{ + mVidParams, l{"_FBVParms_DAFB_SVGA"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4230, "_FBM_DAFB_NTSCST") {{ + include{l{"_FBM_DAFB_NTSCSTconv"}}; +}}; + +resource 'vmod' (4235, "_FBM_DAFB_NTSCSTconv") {{ + mVidParams, l{"_FBVParms_DAFB_NTSCST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4240, "_FBM_DAFB_PALST") {{ + mVidParams, l{"_FBVParms_DAFB_PALST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4245, "_FBM_DAFB_PALSTconv") {{ + mVidParams, l{"_FBVParms_DAFB_PALSTconv"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4250, "_FBM_Civic_PALFF") {{ + include{l{"_FBM_DAFB_PALFF"}}; +}}; + +resource 'vmod' (4255, "_FBM_DAFB_PALFF") {{ + mVidParams, l{"_FBVParms_DAFB_PALFF"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4260, "_FBM_Civic_PALFFconv") {{ + include{l{"_FBM_DAFB_PALFFconv"}}; +}}; + +resource 'vmod' (4265, "_FBM_DAFB_PALFFconv") {{ + mVidParams, l{"_FBVParms_DAFB_PALFFconv"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4270, "_FBMLCD") {{ + mVidParams, l{"_FBVParmsLCD"}; // offset to vid parameters for this configuration + mTable, l{"_FBVFixedCLUTLCD"}; // offset to device color table (fixed device) + mPageCnt, d{FBMPagesLCD}; // number of video pages in this configuration + mDevType, d{fixedType}; // device type +}}; + +resource 'vmod' (4275, "_FBMLCD480") {{ + mVidParams, l{"_FBVParmsHR"}; // offset to vid parameters for this configuration + mTable, l{"_FBVFixedCLUTLCD"}; // offset to device color table (fixed device) + mPageCnt, d{FBMPagesLCD}; // number of video pages in this configuration + mDevType, d{fixedType}; // device type +}}; + + +// Fixed CLUTs… +// +resource 'node' (4280, "_FBVFixedCLUTLCD") {{ + blocksize{}; // Physical Block Size. + + longs{{32+4;}}; // ctSeed + words{{$0000;}}; // ctFlags + words{{$000F;}}; // ctSize (n - 1) + + words{{$0000;$FFFF;$FFFF;$FFFF;}}; // value, r,g,b (white entry). + words{{$0001;$EEEE;$EEEE;$EEEE;}}; // value, r,g,b (gray1 entry). + words{{$0002;$DDDD;$DDDD;$DDDD;}}; // value, r,g,b (gray2 entry). + words{{$0003;$CCCC;$CCCC;$CCCC;}}; // value, r,g,b (gray3 entry). + words{{$0004;$BBBB;$BBBB;$BBBB;}}; // value, r,g,b (gray4 entry). + words{{$0005;$AAAA;$AAAA;$AAAA;}}; // value, r,g,b (gray5 entry). + words{{$0006;$9999;$9999;$9999;}}; // value, r,g,b (gray6 entry). + words{{$0007;$8888;$8888;$8888;}}; // value, r,g,b (gray7 entry). + words{{$0008;$7777;$7777;$7777;}}; // value, r,g,b (gray8 entry). + words{{$0009;$6666;$6666;$6666;}}; // value, r,g,b (gray9 entry). + words{{$000A;$5555;$5555;$5555;}}; // value, r,g,b (grayA entry). + words{{$000B;$4444;$4444;$4444;}}; // value, r,g,b (grayB entry). + words{{$000C;$3333;$3333;$3333;}}; // value, r,g,b (grayC entry). + words{{$000D;$2222;$2222;$2222;}}; // value, r,g,b (grayD entry). + words{{$000E;$1111;$1111;$1111;}}; // value, r,g,b (grayE entry). + words{{$000F;$0000;$0000;$0000;}}; // value, r,g,b (black entry). +}}; + + + +resource 'node' (4285, "_FBVParmsHR") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{FBMHRRB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4290, "_FBVParmsHR400") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{FBMHRRB;}}; // physRowBytes + words{{defmBounds_THR400;defmBounds_LHR400;defmBounds_BHR400;defmBounds_RHR400;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + +resource 'node' (4293, "_FBVParmsHR399") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{FBMHRRB;}}; // physRowBytes + words{{defmBounds_THR399;defmBounds_LHR399;defmBounds_BHR399;defmBounds_RHR399;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4295, "_FBVParmsFP") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{FBMFPRB;}}; // physRowBytes + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; // bmHRes + longs{{VResFP;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4300, "_FBVParmsGS") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{FBMGSRB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4305, "_FBVParmsGS560") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{FBMGS560RB;}}; // physRowBytes + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4310, "_FBVParmsGF") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{FBMGFRB;}}; // physRowBytes + words{{defmBounds_TGF;defmBounds_LGF;defmBounds_BGF;defmBounds_RGF;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGF;}}; // bmHRes + longs{{VResGF;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4315, "_FBVParmsSE") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{FBMSERB;}}; // physRowBytes + words{{defmBounds_TSE;defmBounds_LSE;defmBounds_BSE;defmBounds_RSE;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResSE;}}; // bmHRes + longs{{VResSE;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4320, "_FBVParms_DAFB_640by480") {{ + include{l{"_FBVParms_V8_HRa"}}; +}}; + +resource 'node' (4325, "_FBVParms_V8_HRa") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4330, "_FBVParms_V8_HRb") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4335, "_FBVParms_DAFB_GS") {{ + include{l{"_FBVParms_V8_GSa"}}; +}}; + +resource 'node' (4340, "_FBVParms_V8_GSa") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4345, "_FBVParms_V8_GSb") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4350, "_FBVParms_V8_A2Ema") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_TA2Em;defmBounds_LA2Em;defmBounds_BA2Em;defmBounds_RA2Em;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4355, "_FBVParms_V8_A2Emb") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_TA2Em;defmBounds_LA2Em;defmBounds_BA2Em;defmBounds_RA2Em;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4360, "_FBVParms_DAFB_19") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_512_RB;}}; + words{{defmBounds_T19;defmBounds_L19;defmBounds_B19;defmBounds_R19;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes19;}}; + longs{{VRes19;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4365, "_FBVParms_DAFB_FP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_512_RB;}}; + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; + longs{{VResFP;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4370, "_FBVParms_Civic_2P") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1152_RB;}}; + words{{defmBounds_T2P;defmBounds_L2P;defmBounds_B2P;defmBounds_R2P;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes2P;}}; + longs{{VRes2P;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4375, "_FBVParms_DAFB_2P") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_576_RB;}}; + words{{defmBounds_T2P;defmBounds_L2P;defmBounds_B2P;defmBounds_R2P;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes2P;}}; + longs{{VRes2P;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4380, "_FBVParms_DAFB_LP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TLP;defmBounds_LLP;defmBounds_BLP;defmBounds_RLP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResLP;}}; + longs{{VResLP;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4385, "_FBVParms_Civic_GS560") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1024_RB;}}; + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; + longs{{VResGS;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4390, "_FBVParms_Civic_HR400") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1024_RB;}}; + words{{0;0;400;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4395, "_FBVParms_Civic_HRMAZ") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_832_RB;}}; + words{{0;0;512;704;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4400, "_FBVParms_DAFB_SVGA") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TSVGA;defmBounds_LSVGA;defmBounds_BSVGA;defmBounds_RSVGA;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4405, "_FBVParms_DAFB_NTSCST") {{ + blocksize{}; + longs{{defmNTSCSTB4;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TNTSCST;defmBounds_LNTSCST;defmBounds_BNTSCST;defmBounds_RNTSCST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResNTSC;}}; + longs{{VResNTSC;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4410, "_FBVParms_DAFB_PALST") {{ + blocksize{}; + longs{{defmPALSTB4;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4415, "_FBVParms_DAFB_PALFF") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4420, "_FBVParms_DAFB_PALSTconv") {{ + blocksize{}; + longs{{defmPALSTB4Conv;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4425, "_FBVParms_DAFB_PALFFconv") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{4;}}; + words{{defCmpCount;}}; + words{{4;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4430, "_FBVParmsLCD") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{FBMLCDRB;}}; // physRowBytes + words{{defmBounds_TLCD;defmBounds_LLCD;defmBounds_BLCD;defmBounds_RLCD;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResLCD;}}; // bmHRes + longs{{VResLCD;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{4;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{4;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +//------------------------------------------------------------- +// Eight-Bit per pixel parameters +//------------------------------------------------------------- + +resource 'vmod' (4440, "_EBMHR") {{ + mVidParams, l{"_EBVParmsHR"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4445, "_EBMHR400") {{ + mVidParams, l{"_EBVParmsHR400"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + +resource 'vmod' (4447, "_EBMHR399") {{ + mVidParams, l{"_EBVParmsHR399"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4450, "_EBMFP") {{ + mVidParams, l{"_EBVParmsFP"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesFP}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4455, "_EBMGS") {{ + mVidParams, l{"_EBVParmsGS"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4460, "_EBMGS560") {{ + mVidParams, l{"_EBVParmsGS560"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4465, "_EBMGF") {{ + mVidParams, l{"_EBVParmsGF"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesGF}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4470, "_EBMSE") {{ + mVidParams, l{"_EBVParmsSE"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesSE}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4475, "_EBM_V8_HR") {{ + mVidParams, l{"_EBVParms_V8_HR"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesHR}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4480, "_EBM_V8_GSa") {{ + mVidParams, l{"_EBVParms_V8_GSa"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4485, "_EBM_V8_GSb") {{ + mVidParams, l{"_EBVParms_V8_GSb"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesGS}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4490, "_EBM_V8_A2Ema") {{ + mVidParams, l{"_EBVParms_V8_A2Ema"}; // offset to vid parameters for this configuration + mPageCnt, d{EBMPagesA2Em}; // number of video pages in this configuration + mDevType, d{defmDevType}; // device type +}}; + + +resource 'vmod' (4495, "_EBM_Civic_19") {{ + mVidParams, l{"_EBVParms_Civic_19"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4500, "_EBM_DAFB_19") {{ + mVidParams, l{"_EBVParms_DAFB_19"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4505, "_EBM_Civic_FP") {{ + include{l{"_EBM_DAFB_FP"}}; +}}; + +resource 'vmod' (4510, "_EBM_DAFB_FP") {{ + mVidParams, l{"_EBVParms_DAFB_FP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4515, "_EBM_Civic_2P") {{ + include{l{"_EBM_DAFB_2P"}}; +}}; + +resource 'vmod' (4520, "_EBM_DAFB_2P") {{ + mVidParams, l{"_EBVParms_DAFB_2P"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4525, "_EBM_Civic_GF") {{ + include{l{"_EBM_DAFB_LP"}}; +}}; + +resource 'vmod' (4530, "_EBM_DAFB_LP") {{ + mVidParams, l{"_EBVParms_DAFB_LP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4535, "_EBM_Civic_NTSCSTconv") {{ + include{l{"_EBM_Civic_NTSCST"}}; +}}; + +resource 'node' (4540, "_EBM_Civic_NTSCST") {{ + include{l{"_EBM_Civic_GS"}}; +}}; + +resource 'node' (4545, "_EBM_Civic_GS") {{ + include{l{"_EBM_DAFB_GS"}}; +}}; + +resource 'vmod' (4550, "_EBM_DAFB_GS") {{ + mVidParams, l{"_EBVParms_DAFB_GS"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4555, "_EBM_Civic_GS560") {{ + mVidParams, l{"_EBVParms_Civic_GS560"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4560, "_EBM_Civic_PALSTConv") {{ + include{l{"_EBM_Civic_PALST"}}; +}}; + +resource 'node' (4565, "_EBM_Civic_PALST") {{ + include{l{"_EBM_Civic_NTSCFFConv"}}; +}}; + +resource 'node' (4570, "_EBM_Civic_NTSCFFConv") {{ + include{l{"_EBM_Civic_NTSCFF"}}; +}}; + +resource 'node' (4575, "_EBM_Civic_NTSCFF") {{ + include{l{"_EBM_Civic_VGA"}}; +}}; + +resource 'node' (4580, "_EBM_Civic_VGA") {{ + include{l{"_EBM_Civic_HR"}}; +}}; + +resource 'node' (4585, "_EBM_Civic_HR") {{ + include{l{"_EBM_DAFB_NTSCFF"}}; +}}; + +resource 'node' (4590, "_EBM_DAFB_NTSCFF") {{ + include{l{"_EBM_DAFB_NTSCFFconv"}}; +}}; + +resource 'node' (4595, "_EBM_DAFB_NTSCFFconv") {{ + include{l{"_EBM_DAFB_VGA"}}; +}}; + +resource 'node' (4600, "_EBM_DAFB_VGA") {{ + include{l{"_EBM_DAFB_HR"}}; +}}; + +resource 'vmod' (4605, "_EBM_DAFB_HR") {{ + mVidParams, l{"_EBVParms_DAFB_640by480"}; // a number of different modes share this mVidParams block + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4610, "_EBM_Civic_HR400") {{ + mVidParams, l{"_EBVParms_Civic_HR400"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4615, "_EBM_Civic_HRMAZ") {{ + mVidParams, l{"_EBVParms_Civic_HRMAZ"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4620, "_EBM_Civic_SVGA") {{ + include{l{"_EBM_DAFB_SVGA"}}; +}}; + +resource 'vmod' (4625, "_EBM_DAFB_SVGA") {{ + mVidParams, l{"_EBVParms_DAFB_SVGA"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4630, "_EBM_DAFB_NTSCST") {{ + include{l{"_EBM_DAFB_NTSCSTconv"}}; +}}; + +resource 'vmod' (4635, "_EBM_DAFB_NTSCSTconv") {{ + mVidParams, l{"_EBVParms_DAFB_NTSCST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4640, "_EBM_DAFB_PALST") {{ + mVidParams, l{"_EBVParms_DAFB_PALST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'vmod' (4645, "_EBM_DAFB_PALSTconv") {{ + mVidParams, l{"_EBVParms_DAFB_PALSTconv"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4650, "_EBM_Civic_PALFF") {{ + include{l{"_EBM_DAFB_PALFF"}}; +}}; + +resource 'vmod' (4655, "_EBM_DAFB_PALFF") {{ + mVidParams, l{"_EBVParms_DAFB_PALFF"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4660, "_EBM_Civic_PALFFconv") {{ + include{l{"_EBM_DAFB_PALFFconv"}}; +}}; + +resource 'vmod' (4665, "_EBM_DAFB_PALFFconv") {{ + mVidParams, l{"_EBVParms_DAFB_PALFFconv"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{defmDevType}; +}}; + + +resource 'node' (4670, "_EBVParmsHR") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{EBMHRRB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4675, "_EBVParmsHR400") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{EBMHRRB;}}; // physRowBytes + words{{defmBounds_THR400;defmBounds_LHR400;defmBounds_BHR400;defmBounds_RHR400;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + +resource 'node' (4678, "_EBVParmsHR399") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{EBMHRRB;}}; // physRowBytes + words{{defmBounds_THR399;defmBounds_LHR399;defmBounds_BHR399;defmBounds_RHR399;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4680, "_EBVParmsFP") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{EBMFPRB;}}; // physRowBytes + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; // bmHRes + longs{{VResFP;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4685, "_EBVParmsGS") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{EBMGSRB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4690, "_EBVParmsGS560") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{EBMGS560RB;}}; // physRowBytes + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4695, "_EBVParmsGF") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{EBMGFRB;}}; // physRowBytes + words{{defmBounds_TGF;defmBounds_LGF;defmBounds_BGF;defmBounds_RGF;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGF;}}; // bmHRes + longs{{VResGF;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4700, "_EBVParmsSE") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{EBMSERB;}}; // physRowBytes + words{{defmBounds_TSE;defmBounds_LSE;defmBounds_BSE;defmBounds_RSE;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResSE;}}; // bmHRes + longs{{VResSE;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4705, "_EBVParms_DAFB_640by480") {{ + include{l{"_EBVParms_V8_HR"}}; +}}; + +resource 'node' (4710, "_EBVParms_V8_HR") {{ + blocksize{}; // physical Block Size + + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4715, "_EBVParms_DAFB_GS") {{ + include{l{"_EBVParms_V8_GSa"}}; +}}; + +resource 'node' (4720, "_EBVParms_V8_GSa") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4725, "_EBVParms_V8_GSb") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_512_RB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4730, "_EBVParms_V8_A2Ema") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_TA2Em;defmBounds_LA2Em;defmBounds_BA2Em;defmBounds_RA2Em;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{defPixelType;}}; // bmPixelType + words{{8;}}; // bmPixelSize + words{{defCmpCount;}}; // bmCmpCount + words{{8;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4733, "_EBVParms_Civic_19") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1152_RB;}}; + words{{defmBounds_T19;defmBounds_L19;defmBounds_B19;defmBounds_R19;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes19;}}; + longs{{VRes19;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + +resource 'node' (4735, "_EBVParms_DAFB_19") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_T19;defmBounds_L19;defmBounds_B19;defmBounds_R19;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes19;}}; + longs{{VRes19;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4740, "_EBVParms_DAFB_FP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; + longs{{VResFP;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4745, "_EBVParms_DAFB_2P") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_1152_RB;}}; + words{{defmBounds_T2P;defmBounds_L2P;defmBounds_B2P;defmBounds_R2P;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes2P;}}; + longs{{VRes2P;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4750, "_EBVParms_DAFB_LP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TLP;defmBounds_LLP;defmBounds_BLP;defmBounds_RLP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResLP;}}; + longs{{VResLP;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4755, "_EBVParms_Civic_GS560") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1024_RB;}}; + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; + longs{{VResGS;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4760, "_EBVParms_Civic_HR400") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1024_RB;}}; + words{{0;0;400;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4765, "_EBVParms_Civic_HRMAZ") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_832_RB;}}; + words{{0;0;512;704;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4770, "_EBVParms_DAFB_SVGA") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TSVGA;defmBounds_LSVGA;defmBounds_BSVGA;defmBounds_RSVGA;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4775, "_EBVParms_DAFB_NTSCST") {{ + blocksize{}; + longs{{defmNTSCSTB8;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TNTSCST;defmBounds_LNTSCST;defmBounds_BNTSCST;defmBounds_RNTSCST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResNTSC;}}; + longs{{VResNTSC;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4780, "_EBVParms_DAFB_PALST") {{ + blocksize{}; + longs{{defmPALSTB8;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4785, "_EBVParms_DAFB_PALFF") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_832_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4790, "_EBVParms_DAFB_PALSTconv") {{ + blocksize{}; + longs{{defmPALSTB8Conv;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (4795, "_EBVParms_DAFB_PALFFconv") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_1024_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{defPixelType;}}; + words{{8;}}; + words{{defCmpCount;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +//------------------------------------------------------------- +// Sixteen-Bit per pixel parameters +//------------------------------------------------------------- + +//** WARNING: Added an 0xff000000 entry at end. +resource 'vmod' (4800, "_D16BMHR") {{ + mVidParams, l{"_D16BVParmsHR"}; // offset to vid parameters for this configuration + mPageCnt, d{D16BMPagesHR}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'vmod' (4805, "_D16BMHR400") {{ + mVidParams, l{"_D16BVParmsHR400"}; // offset to vid parameters for this configuration + mPageCnt, d{D16BMPagesHR}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + +resource 'vmod' (4807, "_D16BMHR399") {{ + mVidParams, l{"_D16BVParmsHR399"}; // offset to vid parameters for this configuration + mPageCnt, d{D16BMPagesHR}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'node' (4810, "_D16BMGS") {{ + include{l{"_D16BM_V8_GS"}}; +}}; + +resource 'vmod' (4815, "_D16BM_V8_GS") {{ + mVidParams, l{"_D16BVParms_V8_GS"}; // offset to vid parameters for this configuration + mPageCnt, d{D16BMPagesGS}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'vmod' (4820, "_D16BMGS560") {{ + mVidParams, l{"_D16BVParms_GS560"}; // offset to vid parameters for this configuration + mPageCnt, d{D16BMPagesGS}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'vmod' (4825, "_D16BM_Civic_19") {{ + mVidParams, l{"_D16BVParms_Civic_19"}; // offset to vid parameters for this configuration + mPageCnt, d{defPages_Civic}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'vmod' (4830, "_D16BM_DAFB_19") {{ + mVidParams, l{"_D16BVParms_DAFB_19"}; // offset to vid parameters for this configuration + mPageCnt, d{defPages_DAFB}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'vmod' (4835, "_D16BM_DAFB_FP") {{ + mVidParams, l{"_D16BVParms_DAFB_FP"}; // offset to vid parameters for this configuration + mPageCnt, d{defPages_DAFB}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'vmod' (4840, "_D16BM_Civic_FP") {{ + mVidParams, l{"_D16BVParms_Civic_FP"}; // offset to vid parameters for this configuration + mPageCnt, d{defPages_Civic}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'node' (4845, "_D16BM_Civic_2P") {{ + include{l{"_D16BM_DAFB_2P"}}; +}}; + +resource 'vmod' (4850, "_D16BM_DAFB_2P") {{ + mVidParams, l{"_D16BVParms_DAFB_2P"}; // offset to vid parameters for this configuration + mPageCnt, d{defPages_DAFB}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'node' (4855, "_D16BM_Civic_GF") {{ + include{l{"_D16BM_DAFB_LP"}}; +}}; + +resource 'vmod' (4860, "_D16BM_DAFB_LP") {{ + mVidParams, l{"_D16BVParms_DAFB_LP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'node' (4865, "_D16BM_Civic_NTSCST") {{ + include{l{"_D16BM_Civic_GS"}}; +}}; + +resource 'node' (4870, "_D16BM_Civic_GS") {{ + include{l{"_D16BM_DAFB_GS"}}; +}}; + +resource 'vmod' (4875, "_D16BM_DAFB_GS") {{ + mVidParams, l{"_D16BVParms_DAFB_GS"}; // offset to vid parameters for this configuration + mPageCnt, d{defPages_DAFB}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'vmod' (4880, "_D16BM_Civic_GS560") {{ + mVidParams, l{"_D16BVParms_Civic_GS560"}; // offset to vid parameters for this configuration + mPageCnt, d{defPages_Civic}; // number of video pages in this configuration + mDevType, d{directType}; // device type +}}; + + +resource 'node' (4885, "_D16BM_Civic_PALST") {{ + include{l{"_D16BM_Civic_NTSCFF"}}; +}}; + +resource 'vmod' (4890, "_D16BM_Civic_NTSCFF") {{ + mVidParams, l{"_D16BVParms_Civic_NTSCFF"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{directType}; +}}; + + +resource 'node' (4895, "_D16BM_Civic_VGA") {{ + include{l{"_D16BM_Civic_HR"}}; +}}; + +resource 'node' (4900, "_D16BM_Civic_HR") {{ + include{l{"_D16BM_DAFB_NTSCFF"}}; +}}; + +resource 'node' (4905, "_D16BM_DAFB_NTSCFF") {{ + include{l{"_D16BM_DAFB_VGA"}}; +}}; + +resource 'node' (4910, "_D16BM_DAFB_VGA") {{ + include{l{"_D16BM_DAFB_HR"}}; +}}; + +resource 'vmod' (4915, "_D16BM_DAFB_HR") {{ + mVidParams, l{"_D16BVParms_DAFB_640by480"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'vmod' (4920, "_D16BM_Civic_HR400") {{ + mVidParams, l{"_D16BVParms_Civic_HR400"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{directType}; +}}; + + +resource 'vmod' (4925, "_D16BM_Civic_HRMAZ") {{ + mVidParams, l{"_D16BVParms_Civic_HRMAZ"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{directType}; +}}; + + +resource 'node' (4930, "_D16BM_Civic_SVGA") {{ + include{l{"_D16BM_DAFB_SVGA"}}; +}}; + +resource 'vmod' (4935, "_D16BM_DAFB_SVGA") {{ + mVidParams, l{"_D16BVParms_DAFB_SVGA"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'vmod' (4940, "_D16BM_DAFB_NTSCST") {{ + mVidParams, l{"_D16BVParms_DAFB_NTSCST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'vmod' (4945, "_D16BM_DAFB_PALST") {{ + mVidParams, l{"_D16BVParms_DAFB_PALST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'node' (4950, "_D16BM_Civic_PALFF") {{ + include{l{"_D16BM_DAFB_PALFF"}}; +}}; + +resource 'vmod' (4955, "_D16BM_DAFB_PALFF") {{ + mVidParams, l{"_D16BVParms_DAFB_PALFF"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'node' (4960, "_D16BVParmsHR") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{D16BMHRRB;}}; // physRowBytes + words{{defmBounds_THR;defmBounds_LHR;defmBounds_BHR;defmBounds_RHR;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4965, "_D16BVParmsHR400") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{D16BMHRRB;}}; // physRowBytes + words{{defmBounds_THR400;defmBounds_LHR400;defmBounds_BHR400;defmBounds_RHR400;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + +resource 'node' (4967, "_D16BVParmsHR399") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{D16BMHRRB;}}; // physRowBytes + words{{defmBounds_THR399;defmBounds_LHR399;defmBounds_BHR399;defmBounds_RHR399;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResHR;}}; // bmHRes + longs{{VResHR;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4970, "_D16BVParms_DAFB_GS") {{ + include{l{"_D16BVParms_V8_GS"}}; +}}; + +resource 'node' (4975, "_D16BVParms_V8_GS") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{V8_1024_RB;}}; // physRowBytes + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4980, "_D16BVParms_GS560") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{D16BMGS560RB;}}; // physRowBytes + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4985, "_D16BVParms_Civic_19") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{Civic_2560_RB;}}; // physRowBytes + words{{defmBounds_T19;defmBounds_L19;defmBounds_B19;defmBounds_R19;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes19;}}; // bmHRes + longs{{VRes19;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4990, "_D16BVParms_DAFB_19") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{DAFB_2048_RB;}}; // physRowBytes + words{{defmBounds_T19;defmBounds_L19;defmBounds_B19;defmBounds_R19;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes19;}}; // bmHRes + longs{{VRes19;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (4995, "_D16BVParms_DAFB_FP") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{DAFB_2048_RB;}}; // physRowBytes + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; // bmHRes + longs{{VResFP;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (5000, "_D16BVParms_Civic_FP") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{Civic_1280_RB;}}; // physRowBytes + words{{defmBounds_TFP;defmBounds_LFP;defmBounds_BFP;defmBounds_RFP;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResFP;}}; // bmHRes + longs{{VResFP;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (5005, "_D16BVParms_DAFB_2P") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{DAFB_2304_RB;}}; // physRowBytes + words{{defmBounds_T2P;defmBounds_L2P;defmBounds_B2P;defmBounds_R2P;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HRes2P;}}; // bmHRes + longs{{VRes2P;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (5010, "_D16BVParms_DAFB_LP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_1664_RB;}}; + words{{defmBounds_TLP;defmBounds_LLP;defmBounds_BLP;defmBounds_RLP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResLP;}}; + longs{{VResLP;}}; + words{{ChunkyDirect;}}; + words{{16;}}; + words{{3;}}; + words{{5;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5015, "_D16BVParms_Civic_GS560") {{ + blocksize{}; // physical Block Size + longs{{defmBaseOffset;}}; + words{{Civic_1280_RB;}}; // physRowBytes + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; // bmVersion + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; // bmHRes + longs{{VResGS;}}; // bmVRes + words{{ChunkyDirect;}}; // bmPixelType + words{{16;}}; // bmPixelSize + words{{3;}}; // bmCmpCount + words{{5;}}; // bmCmpSize + longs{{defmPlaneBytes;}}; // bmPlaneBytes +}}; + + +resource 'node' (5020, "_D16BVParms_Civic_NTSCFF") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1280_RB;}}; + words{{0;0;480;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{16;}}; + words{{3;}}; + words{{5;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5025, "_D16BVParms_DAFB_640by480") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_2048_RB;}}; + words{{0;0;480;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{16;}}; + words{{3;}}; + words{{5;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5030, "_D16BVParms_Civic_HR400") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1280_RB;}}; + words{{0;0;400;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{16;}}; + words{{3;}}; + words{{5;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5035, "_D16BVParms_Civic_HRMAZ") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_1664_RB;}}; + words{{0;0;512;704;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{16;}}; + words{{3;}}; + words{{5;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5040, "_D16BVParms_DAFB_SVGA") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_1664_RB;}}; + words{{defmBounds_TSVGA;defmBounds_LSVGA;defmBounds_BSVGA;defmBounds_RSVGA;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{16;}}; + words{{3;}}; + words{{5;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5045, "_D16BVParms_DAFB_NTSCST") {{ + blocksize{}; + longs{{defmNTSCSTB16;}}; + words{{DAFB_2048_RB;}}; + words{{defmBounds_TNTSCST;defmBounds_LNTSCST;defmBounds_BNTSCST;defmBounds_RNTSCST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResNTSC;}}; + longs{{VResNTSC;}}; + words{{ChunkyDirect;}}; + words{{16;}}; + words{{3;}}; + words{{5;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5050, "_D16BVParms_DAFB_PALST") {{ + blocksize{}; + longs{{defmPALSTB16;}}; + words{{DAFB_1664_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{ChunkyDirect;}}; + words{{16;}}; + words{{3;}}; + words{{5;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5055, "_D16BVParms_DAFB_PALFF") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_1664_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{ChunkyDirect;}}; + words{{16;}}; + words{{3;}}; + words{{5;}}; + longs{{defmPlaneBytes;}}; +}}; + + +//------------------------------------------------------------- +// ThirtyTwo-Bit per pixel parameters +//------------------------------------------------------------- + +resource 'node' (5060, "_D32BM_Civic_GF") {{ + include{l{"_D32BM_DAFB_LP"}}; +}}; + +resource 'vmod' (5065, "_D32BM_DAFB_LP") {{ + mVidParams, l{"_D32BVParms_DAFB_LP"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'node' (5070, "_D32BM_Civic_NTSCST") {{ + include{l{"_D32BM_Civic_GS"}}; +}}; + +resource 'node' (5075, "_D32BM_Civic_GS") {{ + include{l{"_D32BM_DAFB_GS"}}; +}}; + +resource 'vmod' (5080, "_D32BM_DAFB_GS") {{ + mVidParams, l{"_D32BVParms_DAFB_GS"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'vmod' (5085, "_D32BM_Civic_GS560") {{ + mVidParams, l{"_D32BVParms_Civic_GS560"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{directType}; +}}; + + +resource 'node' (5090, "_D32BM_Civic_PALST") {{ + include{l{"_D32BM_Civic_NTSCFF"}}; +}}; + +resource 'node' (5095, "_D32BM_Civic_NTSCFF") {{ + include{l{"_D32BM_Civic_VGA"}}; +}}; + +resource 'node' (5100, "_D32BM_Civic_VGA") {{ + include{l{"_D32BM_Civic_HR"}}; +}}; + +resource 'vmod' (5105, "_D32BM_Civic_HR") {{ + mVidParams, l{"_D32BVParms_Civic_640by480"}; // a number of different modes share this mVidParams block + mPageCnt, d{defPages_Civic}; + mDevType, d{directType}; +}}; + + +resource 'vmod' (5110, "_D32BM_Civic_HR400") {{ + mVidParams, l{"_D32BVParms_Civic_HR400"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{directType}; +}}; + + +resource 'vmod' (5115, "_D32BM_Civic_HRMAZ") {{ + mVidParams, l{"_D32BVParms_Civic_HRMAZ"}; + mPageCnt, d{defPages_Civic}; + mDevType, d{directType}; +}}; + + +resource 'node' (5120, "_D32BM_DAFB_NTSCFF") {{ + include{l{"_D32BM_DAFB_VGA"}}; +}}; + +resource 'node' (5125, "_D32BM_DAFB_VGA") {{ + include{l{"_D32BM_DAFB_HR"}}; +}}; + +resource 'vmod' (5130, "_D32BM_DAFB_HR") {{ + mVidParams, l{"_D32BVParms_DAFB_640by480"}; // a number of different modes share this mVidParams block + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'node' (5135, "_D32BM_Civic_SVGA") {{ + include{l{"_D32BM_DAFB_SVGA"}}; +}}; + +resource 'vmod' (5140, "_D32BM_DAFB_SVGA") {{ + mVidParams, l{"_D32BVParms_DAFB_SVGA"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'vmod' (5145, "_D32BM_DAFB_NTSCST") {{ + mVidParams, l{"_D32BVParms_DAFB_NTSCST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'vmod' (5150, "_D32BM_DAFB_PALST") {{ + mVidParams, l{"_D32BVParms_DAFB_PALST"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'node' (5155, "_D32BM_Civic_PALFF") {{ + include{l{"_D32BM_DAFB_PALFF"}}; +}}; + +resource 'vmod' (5160, "_D32BM_DAFB_PALFF") {{ + mVidParams, l{"_D32BVParms_DAFB_PALFF"}; + mPageCnt, d{defPages_DAFB}; + mDevType, d{directType}; +}}; + + +resource 'node' (5165, "_D32BVParms_DAFB_LP") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_3328_RB;}}; + words{{defmBounds_TLP;defmBounds_LLP;defmBounds_BLP;defmBounds_RLP;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResLP;}}; + longs{{VResLP;}}; + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5170, "_D32BVParms_DAFB_GS") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_2048_RB;}}; + words{{defmBounds_TGS;defmBounds_LGS;defmBounds_BGS;defmBounds_RGS;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; + longs{{VResGS;}}; + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5175, "_D32BVParms_Civic_GS560") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_2560_RB;}}; + words{{defmBounds_TGS560;defmBounds_LGS560;defmBounds_BGS560;defmBounds_RGS560;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResGS;}}; + longs{{VResGS;}}; + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + + +resource 'node' (5180, "_D32BVParms_DAFB_640by480") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_4096_RB;}}; + words{{0;0;480;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5185, "_D32BVParms_Civic_640by480") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_2560_RB;}}; + words{{0;0;480;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5190, "_D32BVParms_Civic_HR400") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_2560_RB;}}; + words{{0;0;400;640;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5195, "_D32BVParms_Civic_HRMAZ") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{Civic_3328_RB;}}; + words{{0;0;512;704;}}; // who needs equates in a file of this size? + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5200, "_D32BVParms_DAFB_SVGA") {{ + blocksize{}; + + longs{{defmBaseOffset;}}; + words{{DAFB_3328_RB;}}; + words{{defmBounds_TSVGA;defmBounds_LSVGA;defmBounds_BSVGA;defmBounds_RSVGA;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{$00480000;}}; // 72 hdpi + longs{{$00480000;}}; // 72 vdpi + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5205, "_D32BVParms_DAFB_NTSCST") {{ + blocksize{}; + longs{{defmNTSCSTB32;}}; + words{{DAFB_4096_RB;}}; + words{{defmBounds_TNTSCST;defmBounds_LNTSCST;defmBounds_BNTSCST;defmBounds_RNTSCST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResNTSC;}}; + longs{{VResNTSC;}}; + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5210, "_D32BVParms_DAFB_PALST") {{ + blocksize{}; + longs{{defmPALSTB32;}}; + words{{DAFB_3328_RB;}}; + words{{defmBounds_TPALST;defmBounds_LPALST;defmBounds_BPALST;defmBounds_RPALST;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + + +resource 'node' (5215, "_D32BVParms_DAFB_PALFF") {{ + blocksize{}; + longs{{defmBaseOffset;}}; + words{{DAFB_3328_RB;}}; + words{{defmBounds_TPALFF;defmBounds_LPALFF;defmBounds_BPALFF;defmBounds_RPALFF;}}; + words{{defVersion;}}; + words{{0;}}; // packType not used + longs{{0;}}; // packSize not used + longs{{HResPAL;}}; + longs{{VResPAL;}}; + words{{ChunkyDirect;}}; + words{{32;}}; + words{{3;}}; + words{{8;}}; + longs{{defmPlaneBytes;}}; +}}; + +resource 'long' (2650, "_timingInvalid") {timingInvalid}; +resource 'long' (2651, "_timingApple12") {timingApple12}; +resource 'long' (2652, "_timingApple12x") {timingApple12x}; +resource 'long' (2653, "_timingApple13") {timingApple13}; +resource 'long' (2654, "_timingApple13x") {timingApple13x}; +resource 'long' (2655, "_timingAppleVGA") {timingAppleVGA}; +resource 'long' (2656, "_timingApple15") {timingApple15}; +resource 'long' (2657, "_timingApple16") {timingApple16}; + +//------------------------------------------------------------- +// Extended Format/Header Block +//------------------------------------------------------------- + +resource 'xfrm' (6000, "Root") { + l{"_sSuperInitRec"}, + l{"_sRsrcSuperDir"}, + l{"_sRsrcUnknownDir"}, + 1, // RomRevision + appleFormat, + 0, + 0x0F // Byte lanes +}; + +#if 0 +resource 'node' (6000, "Root") {{ + include{l{"_RootDirectory"}}; + long{testPattern}; + byte{0}; + // Stuff below is part of regular format block. + offset{l{"_sRsrcUnknownDir"}}; + romlength{}; /* ROM Length */ + romcrc{}; /* CRC */ + byte{1}; + byte{1}; + long{testPattern}; + byte{0}; + byte{0x0F}; +}}; + +resource 'list' (6001, "_RootDirectory") {{ + appleFormat, include{a{"OffsetTo_sSuperInitRec"}}; + sSuperDir, l{"_sRsrcSuperDir"}; +}}; + + +#endif diff --git a/DeclData/DeclData.r.idump b/DeclData/DeclData.r.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclData.r.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclData.r.rdump b/DeclData/DeclData.r.rdump new file mode 100644 index 0000000..ea43002 --- /dev/null +++ b/DeclData/DeclData.r.rdump @@ -0,0 +1,33 @@ +data 'MPSR' (1005) { + $"0009 436F 7572 6965 7200 2020 2020 2020" /* ..Courier. */ + $"2020 2020 2020 2020 2020 2020 2020 2020" /* */ + $"2020 0005 0004 0029 0007 035A 023E 0029" /* .....)...Z.>.) */ + $"0007 035A 023E A964 1348 0000 00C6 0000" /* ...Z.>.d.H...... */ + $"0136 0000 0000 0100" /* .6...... */ +}; + +data 'MPSR' (1007) { + $"0001 0003 D821 0003 D82A 0956 6964 5061" /* .....!...*.VidPa */ + $"7261 6D73" /* rams */ +}; + +data 'MPSR' (1008) { + $"0029 0007 035A 023E 0029 0007 035A 023E" /* .)...Z.>.)...Z.> */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"79E4 A53B 3FE5 3230 0004 0000 0000 0000" /* y..;?.20........ */ + $"0000 A972 83C9 A972 83C9 A6F7 9FDC 0074" /* ...r...r.......t */ + $"C2F0 0000 0005 0029 1853 7570 6572 4D61" /* .......).SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA00 0E43 6872 6973 2050 6574 6572 7365" /* ...Chris Peterse */ + $"6E00 0232 3800 0A44 6563 6C44 6174 612E" /* n..28..DeclData. */ + $"7200 0000 004F 5265 6D6F 7665 2074 6865" /* r....ORemove the */ + $"2072 656D 6169 6E69 6E67 2073 6C6F 7420" /* remaining slot */ + $"7265 736F 7572 6365 2074 7970 6573 2022" /* resource types " */ + $"5F43 5055 4D61 6332 3022 2074 6F20 6669" /* _CPUMac20" to fi */ + $"7820 4441 4642 2076 6964 656F 2064 6973" /* x DAFB video dis */ + $"706C 6179 2E00" /* play.. */ +}; + diff --git a/DeclData/DeclNet/802Equ.a b/DeclData/DeclNet/802Equ.a new file mode 100644 index 0000000..4ebee32 --- /dev/null +++ b/DeclData/DeclNet/802Equ.a @@ -0,0 +1,97 @@ +; +; File: 802Equ.a +; +; Contains: Equates for IEEE network standards +; +; Written by: Kerry E. Lynn, Sean Findley +; +; Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved. +; +; Change History (most recent first): +; +; <1> 10/6/92 GDW New location for ROMLink tool. +; <1> 3/26/92 FM first checked in +; <1> 12/14/90 JK Added to build +; +; To Do: +; + +;-----------=-----------=-------------------------------=--------------------------------------- +; 802Equ.a - Equates for IEEE network standards +; +; Kerry E. Lynn +; Feb 1989 +; +; Copyright (C) 1989 by: +; +; Apple Computer, Inc. +; 20525 Mariani Ave. +; Cupertino, CA 95014 +; +; All Rights Reserved. +;-----------=-----------=-------------------------------=--------------------------------------- + +; 24-bit quantities, left justified + +AppleCode EQU $08000700 ; Apple's vendor code for 802.2 Individual addr +MultiCode EQU $09000700 ; Apple's vendor code for 802.2 Group addr + + +; Size of a MAC addr + +MACAddrSz EQU 6 ; max size (in bytes) for data link addr +MaxMCastSz EQU MACAddrSz ; max size (in bytes) for multicast addr + +;--------------------------------------- +; 802.3 MAC packet header +;--------------------------------------- + +MDstAddr EQU 0 ; Offset to destination address +MSrcAddr EQU MDstAddr+MACAddrSz ; Offset to source address +MLength EQU MSrcAddr+MACAddrSz ; Offset to LLC length +MHdrSize EQU MLength+2 ; 802.3 MAC header size + +;--------------------------------------- +; 802.2 LLC (Type 1) packet header +;--------------------------------------- + +LDSAP EQU 0 ; Offset to destination Service Access Point (SAP) +IGBIT EQU 0 ; I/G = 0 if Individual DSAP, = 1 if Group DSAP + +LSSAP EQU LDSAP+1 ; Offset to source SAP +CRBIT EQU 0 ; C/R = 0 if Command, = 1 if Response + +LCtrl EQU LSSAP+1 ; Offset to LLC CONTROL field (see below) +LHdrSize EQU LCtrl+1 + +LInfo EQU LHdrSize ; Offset to LLC Information + +GlobalSAP EQU $FF +NullSAP EQU 0 + +;--------------------------------------- +; CONTROL field bits for 802.2 Type 1 LLC Protocol Data Units (PDUs) +;--------------------------------------- + +UI EQU %00000011 ; value for "Unnumbered Information" (P/F bit must be 0) +XID EQU %10101111 ; mask for "Exchange Identification" (P/F bit may be 0 or 1) +TEST EQU %11100011 ; mask for "Test" (P/F bit may be 0 or 1) + +PFBIT EQU 4 ; P/F = 0 if Poll (command), = 1 if Final (response) + +;--------------------------------------- +; XID information field +;--------------------------------------- + +XIDformat EQU %10000001 ; indicates IEEE basic format +XIDinfo1 EQU %00000001 ; indicates Type 1 AND Class I LLC +XIDinfo2 EQU %00000000 ; receive window size = N/A + +XIDinfoSz EQU 3 ; number of bytes in an XID response + +;--------------------------------------- +; Sub-Network Access Protocol (SNAP) packet header +;--------------------------------------- + +SType EQU 0 ; 5-byte protocol discriminator +SHdrSize EQU SType+5 diff --git a/DeclData/DeclNet/802Equ.a.idump b/DeclData/DeclNet/802Equ.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/802Equ.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/802Equ.a.rdump b/DeclData/DeclNet/802Equ.a.rdump new file mode 100644 index 0000000..966a24a --- /dev/null +++ b/DeclData/DeclNet/802Equ.a.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 008F 0090 7FFF 005F" /* ..Monaco......._ */ + $"0090 0091 7FFF 0250 0090 0091 7FFF 0262" /* .......P.......b */ + $"0000 0006 0004 00B5 0137 03E6 036E 0029" /* .........7...n.) */ + $"0007 035A 023E A6A7 F930 0000 03C7 0000" /* ...Z.>...0...... */ + $"03C7 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"00B5 0137 03E6 036E 0029 0007 035A 023E" /* ...7...n.)...Z.> */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"6658 1030 3FE5 3230 0004 0000 0000 0000" /* fX.0?.20........ */ + $"0000 A933 7396 A933 7396 A6F7 AE5C 0078" /* ...3s..3s....\.x */ + $"2B21 0000 0001 0001 2053 7570 6572 4D61" /* +!...... SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA00 0E43 6872 6973" /* .DeclNet...Chris */ + $"2050 6574 6572 7365 6E00 0131 0008 3830" /* Petersen..1..80 */ + $"3245 7175 2E61 0000 0000 1F4E 6577 206C" /* 2Equ.a.....New l */ + $"6F63 6174 696F 6E20 666F 7220 524F 4D4C" /* ocation for ROML */ + $"696E 6B20 746F 6F6C 2E0D 00" /* ink tool... */ +}; + diff --git a/DeclData/DeclNet/AtalkMacros.a b/DeclData/DeclNet/AtalkMacros.a new file mode 100644 index 0000000..ce1cecc --- /dev/null +++ b/DeclData/DeclNet/AtalkMacros.a @@ -0,0 +1,397 @@ +; +; File: ATMacros.a +; +; Contains: Assembly macros used by AppleTalk +; +; Written by: Mike Shoemaker +; +; Copyright: © 1990-1993 by Apple Computer, Inc., all rights reserved. +; +; Change History (most recent first): +; +; 12/13/93 PN Roll in KAOS and Horror to add support for Malcom and AJ +; <1> 10/6/92 GDW New location for ROMLink tool. +; 6/22/92 mal Added some labels to VERSION macro and added VMImmumebit equate. +; 5/4/92 CSS moved to ethernet folder to get build to work +; <2> 3/19/92 kc Roll in Terror/Horror Changes. +; 2/??/92 kc first checked in +; ——————————————————————————————————————————————————————————————————————————————————————— +; Pre-SuperMario ROM comments begin here. +; ——————————————————————————————————————————————————————————————————————————————————————— +;

01/22/92 jmp (BG,Z2) Added some additional macros for new ethernet changes. +; ——————————————————————————————————————————————————————————————————————————————————————— +; Pre-Horror ROM comments begin here. +; ——————————————————————————————————————————————————————————————————————————————————————— +; 3/27/91 jmp first checked in +; ——————————————————————————————————————————————————————————————————————————————————————— +; Pre-TERROR ROM comments begin here. +; ——————————————————————————————————————————————————————————————————————————————————————— +; <8> 1/30/91 mbs cj,#82011: Move years after company name in copyright message. +; <7> 12/17/90 mbs The ALIGN directive does not work for the IIGS assembler. Use +; IF ENDIF to generate an extra dc.b 0 if necessary. Yes except +; for the ALIGN, the entire macro worked under the IIGS +; assembler!. +; <6> 11/28/90 mbs In the VERSION macro, when the release stage is 'released', pad +; the version with two trailing spaces so that the length remains +; the same when changing from an f1 to a Golden Master build. +; <5> 11/26/90 mbs Did not handle 3-digit major version number +; <4> 11/12/90 mbs Steven pointed out that verUs is zero, not 1. +; <3> 11/10/90 mbs Add optional parameter to set the label at the front of the +; version structure. +; <2> 11/09/90 mbs Add 'v' in front of version number in long string +; 11/9/90 mbs First written +; +; To Do: +; + +; WARNING -- CAN'T USE IF (__IncludingATalkMacros__ == 'UNDEFINED') because +; 6502 assember barfs and doesn't include the file. + + PRINT PUSH, OFF + +;========================================================================================== +; VERSION +; +; USAGE: +; VERSION , , , +; , , +; [, [, ] ] +; +; The name field should be quoted if more than one word. +; The copyright years field may or may not be quoted. The macro works either way +; It is OK to leave the engineering suffix field empty. +; +; The start of the version information is given the Label 'VersionInfo', unless +; you specify the last parameter; then it will be used. It must not be quoted. +; +; Example for EtherTalk 1.2a3q1 copyrighted 1987-1990 +; +; VERSION 'EtherTalk', 1, 2, 0, alpha, 3, '1987-1990', 'q1' + +;========================================================================================== + +ATM_development EQU $20 ; These are used in the 3rd byte of the 4-byte version # +ATM_alpha EQU $40 ; .. to indicate release stage +ATM_beta EQU $60 +ATM_final EQU $80 +ATM_release EQU $80 + +ATM_verUS EQU 0 + + MACRO + VERSION &sName, &nMajor, &nMinor, &nBug, \ + &sStage, &nRevision, &sCopyright, &sEngr='', &sLabel0=VersionInfo,&sLabel1=End + +&sLabel0 ;Make label for this version information + LCLA &nStage ;Numeric representation of stage + LCLC &cStage ;Character representation of stage + LCLA &nPadBytes ;Add padding at end of record to + ;allow room for expansion if we + ;have to add bug release digits + ;to the version # + + LCLC &StrSetting ;To save current string setting +&StrSetting SETC &SETTING('STRING') ;Save current string setting + + STRING PASCAL ;Set string state to Pascal + +; +; Do some error checking +; + IF &UPCASE(&sStage)='ALPHA' THEN +&nStage SETA ATM_alpha +&cStage SETC 'a' + ELSEIF &UPCASE(&sStage)='BETA' THEN +&nStage SETA ATM_beta +&cStage SETC 'b' + ELSEIF &UPCASE(&sStage)='DEVELOPMENT' THEN +&nStage SETA ATM_development +&cStage SETC 'd' + ELSEIF &UPCASE(&sStage)='FINAL' THEN +&nStage SETA ATM_final +&cStage SETC 'f' + ELSEIF &UPCASE(&sStage)='RELEASE' THEN +&nStage SETA ATM_release +&cStage SETC 'x' + ELSE + AERROR 'The stage parameter to VERSION must be: development, alpha, beta, final or release' + ENDIF + + + + IF (&nMinor > 15) THEN + AERROR 'The Minor version must be less than 16' + ENDIF + + IF (&nBug > 15) THEN + AERROR 'The Bug fix version must be less than 16' + ENDIF + +; +; Generate the 4-byte version numbers +; + dc.b &nMajor ;Major version number + dc.b (&nMinor * 16) + &nBug ;Build 2nd byte of version + dc.b &nStage, &nRevision ;stage and revision level +; +; Generate the integer country code +; + dc.w ATM_verUS ;Country Code + +; +; Build Version string from major/minor version string +; + LCLC &lShortVer + +; +; Make 1st digit of version string +; + IF (&nMajor >= 100) THEN +&lShortVer SETC &CONCAT(&CHR(&nMajor / 100 + $30), \ + &CHR((&nMajor MOD 100) / 10 + $30), \ + &CHR(&nMajor MOD 10 + $30)) + ELSE + IF (&nMajor >= 10) THEN +&lShortVer SETC &CONCAT(&CHR(&nMajor / 10 + $30), &CHR(&nMajor MOD 10 + $30)) + ELSE +&lShortVer SETC &CHR(&nMajor + $30) + ENDIF + ENDIF + +; +; Append 2nd digit of version number (ie: 1.0) +; + IF (&nMinor >= 10) THEN +&lShortVer SETC &CONCAT(&lShortVer,'.',&CONCAT(&CHR(&nMinor / 10 + $30), &CHR(&nMinor MOD 10 + $30))) + ELSE +&lShortVer SETC &CONCAT(&lShortVer,'.',&CHR(&nMinor + $30)) + ENDIF + +; +; Append third digit of version number if non-zero (ie: 1.0.2). If zero, leave +; room for the extra characters at the end of the record +; + IF (&nBug <> 0) THEN +&nPadBytes SETA 0 ; Will not need padding + IF (&nBug >= 10) THEN +&lShortVer SETC &CONCAT(&lShortVer,'.',&CONCAT(&CHR(&nBug / 10 + $30), &CHR(&nBug MOD 10 + $30))) + ELSE +&lShortVer SETC &CONCAT(&lShortVer,'.',&CHR(&nBug + $30)) + ENDIF + ELSE +&nPadBytes SETA 1 ; Leave room for padding + ENDIF + + +; Append stage letter and revision if not a release version. +; For release version, append two spaces. This way the string does not change length +; between an 'f1' build and a GM build. + + IF (&cStage <> 'x') THEN +&lShortVer SETC &CONCAT(&lShortVer,&cStage) + IF (&nRevision >= 10) THEN +&lShortVer SETC &CONCAT(&lShortVer,&CONCAT(&CHR(&nRevision / 10 + $30), &CHR(&nRevision MOD 10 + $30))) + ELSE +&lShortVer SETC &CONCAT(&lShortVer,&CHR(&nRevision + $30)) + ENDIF + ELSE +&lShortVer SETC &CONCAT(&lShortVer, ' ') ; Append two spaces if release + ENDIF + +; +; Emit the short string +; + dc.b '&lShortVer' + +; ALIGN directive doesn't exist on IIGS assembler so do it the hard way... + + IF ((&LEN(&lShortVer) +1) MOD 2) = 1 THEN + dc.b 0 + ENDIF +; +; Trim the beginning and ending quotes from the name, copyright years, and +; engineering suffix if present +; + LCLC &lName + LCLC &lCopyright + LCLC &lEngr + + IF &SUBSTR(&sName, 1, 1) = &CHR($27) THEN +&lName SETC &SUBSTR(&sName, 2, &LEN(&sName) - 2) + ELSE +&lName SETC &sName + ENDIF + IF &SUBSTR(&sCopyright, 1, 1) = &CHR($27) THEN +&lCopyright SETC &SUBSTR(&sCopyright, 2, &LEN(&sCopyright) - 2) + ELSE +&lCopyright SETC &sCopyright + ENDIF + IF &SUBSTR(&sEngr, 1, 1) = &CHR($27) THEN +&lEngr SETC &SUBSTR(&sEngr, 2, &LEN(&sEngr) - 2) + ELSE +&lEngr SETC &sEngr + ENDIF + +; +; Build the long string +; + LCLC &lLongVer ; Define a local variable to hold it +&lLongVer SETC &CONCAT(&lName,' v',&lShortVer,&lEngr,'; © Apple Computer, Inc. ',&lCopyright) + +; +; Emit the long string +; + LCLC &sLongVerLabel ; + LCLC &sLongVerLabelEnd ; +&sLongVerLabel SETC &CONCAT(&sLabel0, 'LongStr') ; +&sLongVerLabel ; + dc.b '&lLongVer' ; + + IF ((&LEN(&lLongVer) +1) MOD 2) = 1 THEN ; Align things + dc.b 0 + ENDIF + +; +; If this is an "xx.x" release rather than an "xx.x.x" release, leave room so that +; if we have to rev the version # to x.x.x, the size of the record will not change. +; + IF (&nPadBytes) THEN + dc.b 0,0,0,0 + ENDIF +&sLongVerLabelEnd SETC &CONCAT(&sLongVerLabel, 'End') +&sLongVerLabelEnd +; +; Clean up and we're done +; + LCLC &sEndLabel ;Make label for end of version information +&sEndLabel SETC &CONCAT(&sLabel0, &sLabel1) +&sEndLabel + STRING &StrSetting ;Restore string setting + ENDM + + + EJECT + +;========================================================================================== +; SCCLOCKOUT +; +; Macro for disabling interrupts. +;========================================================================================== + + +SRIntMaskBits EQU $0700 ; The 3 interrupt level bit in the SR +SRIntMaskBitsCMP EQU $F8FF ; The 3 interrupt level bit in the SR +SRIntLevel6 EQU $0600 ; Level 6 interrupt mask +SRIntLevel6MASK EQU $FEFF ; Level 6 interrupt AND value +SRIntLevel5MASK EQU $FDFF ; Level 5 interrupt AND value + + MACRO + _SCCLOCKOUT + + ORI.W #SRIntMaskBits,SR ; Set all of the INT bits + ANDI.W #SRIntLevel6MASK,SR ; Set to priority 6 + + ENDM + + + +;========================================================================================== +; _SETINTMASK +; +; Macro for setting the interrupt level to an arbitrary level. Pass the level in +; a Data register. +;========================================================================================== + + MACRO + _SETINTMASK &sReg + move.w SR,-(SP) + andi.w #SRIntMaskBitsCMP,(SP) + or.w &sReg,(SP) + move.w (SP)+,SR + ENDM + +;========================================================================================== +; VSCCEnable +; +; Macro for disabling interrupts. +; Pass address register holding MPP vars, and a temporary Data register +;========================================================================================== + MACRO + _VSCCENABLE &sMPPVarsReg, &tmpReg + + MOVE.W SR, &tmpReg + ANDI.W #SRIntMaskBitsCMP,&tmpReg ; Clear all of the INT bits + EORI.W #$2000, &tmpReg ; Toggle the 2000 bit + move.w vSCCEnable(&sMPPVarsReg),-(SP) ; Push vscc enable + EOR.W &tmpReg, (SP) ; Or in the int bits (and toggles 2000) +; Stupid machine won't let memory be the source on an XOR instruction + MOVE.W (SP)+,SR ; Set SR + + ENDM + +;========================================================================================== +; These Macros & Equates are used to call the multipurpose function dispatcher in the +; Lap Manager. None of these functionn have jack to do with the Lap Manager, but they +; provide a way for code to get the functions without having to link with the library +; containing them. Of course, they require that a Lap Manager be present. +;========================================================================================== +; +; Macro used in following macros +; + MACRO + _L21Common &nVal + LCLC &cLabel ; Used to make a semi-unique label +&cLabel SETC &CONCAT('@L21Ret',&nVal) + pea &cLabel ; Want to return to here + move.l LAPMgrPtr,D0 ; Ptr to Lap Manager + add.l #LAPMgrCall,D0 ; Ptr to dispatch entry point + move.l D0,-(SP) ; Put on stack + move.l #((&nVal << 16) + LInt21Dispatch),D0 + rts ; Call Lap Manager +&cLabel + ENDM + +; +; Macros to call Lap Manager Dispatch routines +; + +; Returns non-zero in D0.L if Extensions are disabled at boot time. Always returns zero on +; System 6. Sets condition codes + MACRO + _LExtensionsDisabled + _L21Common L21ExtensionsDisabled + ENDM + +; pascal Handle GetBestResource(OSType theType, short theID) + + MACRO + _LGetBestResource + _L21Common L21GetBestResource + ENDM + +; pascal Boolean TrapAvailable(short theTrap) + MACRO + _LTrapAvailable + _L21Common L21TrapAvailable + ENDM + + + + +;========================================================================================== +; New Macros go here +;========================================================================================== +; +; MACROS for SNMP counters +; + + MACRO + _IncrCount &SNMPCounter + ADDQ.L #1, SNMPVars.&SNMPCounter(A2) ; increment whatever SNMP counter + ENDM + +VMImmuneBit EQU 0 ; bit in driver DCE flags to tell VM to leave paramblocks alone + + PRINT POP + +; END ATMacros.a diff --git a/DeclData/DeclNet/AtalkMacros.a.idump b/DeclData/DeclNet/AtalkMacros.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/AtalkMacros.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/AtalkMacros.a.rdump b/DeclData/DeclNet/AtalkMacros.a.rdump new file mode 100644 index 0000000..5192dff --- /dev/null +++ b/DeclData/DeclNet/AtalkMacros.a.rdump @@ -0,0 +1,27 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0062 7920 4170 706C" /* ..Monaco.by Appl */ + $"6554 616C 6B0D 3B0D 3B09 5772 6974 7465" /* eTalk.;.;.Writte */ + $"6E20 0006 0004 0067 0076 0373 02AB 0067" /* n .....g.v.s...g */ + $"0076 0373 02AB A92E 382C 0000 00D8 0000" /* .v.s....8,...... */ + $"0129 0000 0000 0100" /* .)...... */ +}; + +data 'MPSR' (1008) { + $"0067 0076 0373 02AB 0067 0076 0373 02AB" /* .g.v.s...g.v.s.. */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"3AD9 AFA2 3FE5 3230 0004 0000 0000 0000" /* :...?.20........ */ + $"0000 A933 7396 A933 7396 A6F7 AE5C 0078" /* ...3s..3s....\.x */ + $"2B21 0000 0002 0003 2053 7570 6572 4D61" /* +!...... SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA00 0E43 6872 6973" /* .DeclNet...Chris */ + $"2050 6574 6572 7365 6E00 0132 000D 4174" /* Petersen..2..At */ + $"616C 6B4D 6163 726F 732E 6100 0000 0038" /* alkMacros.a....8 */ + $"526F 6C6C 2069 6E20 4B41 4F53 2061 6E64" /* Roll in KAOS and */ + $"2048 6F72 726F 7220 746F 2061 6464 2073" /* Horror to add s */ + $"7570 706F 7274 2066 6F72 204D 616C 636F" /* upport for Malco */ + $"6D20 616E 6420 414A 00" /* m and AJ. */ +}; + diff --git a/DeclData/DeclNet/ENETEqu.a b/DeclData/DeclNet/ENETEqu.a new file mode 100644 index 0000000..a469b02 --- /dev/null +++ b/DeclData/DeclNet/ENETEqu.a @@ -0,0 +1,94 @@ +; +; File: ENETEqu.a +; +; Contains: Equates for the Ethernet driver +; +; Written by: Sean Findley (Version 1.1a1) +; +; Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved. +; +; This file is used in these builds: Mac32 +; +; Change History (most recent first): +; +; 10/26/92 mal Updated SNMP control codes. +; <1> 10/6/92 GDW New location for ROMLink tool. +; <2> 3/26/92 FM Rolled into reality +; <2> 1/9/91 JK Cleaned up to simplify N&C support. +; <1> 12/14/90 JK Added to build +; +; To Do: +; + + IF (&TYPE('MHdrSize') = 'UNDEFINED') THEN + INCLUDE '802Equ.a' ; IEEE equates + ENDIF + +; Control codes. + +ESetGeneral EQU 253 ; Set "general" mode +EGetInfo EQU 252 ; Get info +ERdCancel EQU 251 ; Cancel read +ERead EQU 250 ; Read +EWrite EQU 249 ; Write +EDetachPH EQU 248 ; Detach protocol handler +EAttachPH EQU 247 ; Attach protocol handler +EAddMulti EQU 246 ; Add a multicast address +EDelMulti EQU 245 ; Delete a multicast address +EOpenSAP EQU 244 ; Open an 802.2 SAP +ECloseSAP EQU 243 ; Close an 802.2 SAP +ELapGetLinkStatus EQU 242 ; Get interface statistics, RFC 1213 +EGetDot3CollStats EQU 241 ; Get 802.3 collision statistics, RFC 1284 +EGetDot3Statistics EQU 240 ; Get 802.3 statistics, RFC 1284 +ESetDot3Entry EQU 239 ; Set 802.3 status & control information +EGetDot3Entry EQU 238 ; Get 802.3 status & control information + + +FirstENET EQU EGetDot3Entry ; First ENET command +LastENET EQU ESetGeneral ; Last ENET command + +; ENET queue element standard structure: arguments passed in the CSParam area + +EProtType EQU CSParam ; Offset to protocol type code +EMultiAddr EQU CSParam ; Multicast address (EAddMulti,EDelMulti) + +EHandler EQU EProtType+2 ; Offset to protocol handler +EWDSPointer EQU EHandler ; WDS pointer (EWrite) +EBuffPtr EQU EHandler ; Buffer pointer (ERead,EGetInfo) +EKillQEl EQU EHandler ; QEl pointer (ERdCancel) + +EBuffSize EQU EBuffPtr+4 ; Buffer size (ERead,EGetInfo) +EDataSize EQU EBuffSize+2 ; Actual data size (Eread) + + +;--------------------------------------- +; Ethernet packet header +;--------------------------------------- + +EDestAddr EQU 0 ; Offset to destination address +ESrcAddr EQU 6 ; Offset to source address +EType EQU 12 ; Offset to data link type +EHdrSize EQU 14 ; Ethernet header size + +EMinDataSz EQU 46 ; Minimum data size +EMaxDataSz EQU 1500 ; Maximum data size +EAddrSz EQU 6 ; Size of an ethernet node address +MAddrSz EQU 8 ; Size of an ethernet multicast address (?) + +; These are defined in 802Equ.a +; +ETHdrSize EQU MHdrSize+LHdrSize+SHdrSize + +; +; Errors and misc. +; + +eLenErr EQU ddpLenErr ; Length error +eMultiErr EQU ddpSktErr ; Multicast address error + +EAddrRType EQU 'eadr' ; Alternate address resource type + +; +; Link specific 'atlk' AGetInfo call +; +ESpeed EQU 10000000 ; Link speed in bits/sec diff --git a/DeclData/DeclNet/ENETEqu.a.idump b/DeclData/DeclNet/ENETEqu.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/ENETEqu.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/ENETEqu.a.rdump b/DeclData/DeclNet/ENETEqu.a.rdump new file mode 100644 index 0000000..3411c58 --- /dev/null +++ b/DeclData/DeclNet/ENETEqu.a.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 002E 00FD 002E 00FE" /* ..Monaco........ */ + $"020E 0000 020E 00FE 0000 0000 0000 0000" /* ................ */ + $"0000 0006 0004 0045 0029 01D2 0246 0083" /* .......E.)...F.. */ + $"001C 0210 0239 A711 6848 0000 0113 0000" /* .....9..hH...... */ + $"0148 0000 0000 0100" /* .H...... */ +}; + +data 'MPSR' (1008) { + $"0045 0029 01D2 0246 0083 001C 0210 0239" /* .E.)...F.......9 */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"2321 3B31 3FE5 3230 0004 0000 0000 0000" /* #!;1?.20........ */ + $"0000 A933 7396 A933 7396 A6F7 AE5C 0078" /* ...3s..3s....\.x */ + $"2B21 0000 0003 0003 2053 7570 6572 4D61" /* +!...... SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA00 0E43 6872 6973" /* .DeclNet...Chris */ + $"2050 6574 6572 7365 6E00 0132 0009 454E" /* Petersen..2..EN */ + $"4554 4571 752E 6100 0000 001B 5570 6461" /* ETEqu.a.....Upda */ + $"7465 6420 534E 4D50 2063 6F6E 7472 6F6C" /* ted SNMP control */ + $"2063 6F64 6573 2E00" /* codes.. */ +}; + diff --git a/DeclData/DeclNet/Loopback.c b/DeclData/DeclNet/Loopback.c new file mode 100644 index 0000000..5854715 --- /dev/null +++ b/DeclData/DeclNet/Loopback.c @@ -0,0 +1,157 @@ +/* + File: Loopback.c + + Contains: Ethernet loopback test code + + Written by: Sean Findley + + Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved. + + Change History (most recent first): + + <1> 10/6/92 GDW New location for ROMLink tool. + 6/22/92 mal Modified so ptr and size to loopback test data is passed from + the driver since shared by Sonic and Mace drivers. + 6/11/92 CS Roll-in changes from Reality: + <2> 6/1/92 DTY Include TextUtils.h for the new home of EqualString. + TextUtils now contains the EqualString prototype, so include it. + <3> 3/26/92 FM Rolled into reality + <2> 2/11/92 RB Use the real EqualString to avoid having to link old C libraries + with this code. + <2> 4/21/91 CCH Rolled in Sean Findley's changes. + <1> 12/14/90 JK Added to build + + To Do: +*/ + +#include + +#include "memory.h" +#include "devices.h" +#include "files.h" +#include "appletalk.h" +#include "OSUtils.h" + +typedef struct +{ + char Addr[6]; +} Enet; + +typedef struct +{ + Enet Destination; /* Ethernet destination */ + Enet Source; /* Ethernet source */ + unsigned short EProtocoltype; /* Ethernet protocol type */ + char testdata[255]; +} LBpacket; + +typedef union /* parameter block for calling .ENET */ +{ + CntrlParam ctl; /* for ctl calls */ + struct + { + char filler[28]; + unsigned short EprotType; + Ptr EBuffPtr; + unsigned short EBuffSize; + unsigned short EDataSize; + } info; + MPPParamBlock ecall; +} Edrvrparms; + +#define Ehandler DDP.DDPptrs.listener +#define EWdsPointer DDP.DDPptrs.wdsPointer +#define EKillQEl EBuffPtr + +#define ERdCancel 251 +#define ERead 250 +#define EWrite 249 +#define EDetachPH 248 +#define EAttachPH 247 + +#define Ethhdrsz 14 + +Boolean cmpdata(char *p1, char *p2, short len) /* true = data equal, false = data not equal */ +{ +short i; + for(i=0;ictl.csCode = ERdCancel; + pbw->info.EKillQEl = (Ptr) pb; + PBControl((ParmBlkPtr) pbw,false); + pbw->ctl.csCode = EDetachPH; + PBControl((ParmBlkPtr) pbw,false); +} + +Boolean LOOPBACKTEST(short refnum,Enet *enetaddr, int AppleData, short AppleDataSz) +{ +LBpacket LBPR,LBPW; +Edrvrparms pb,pbw; +WDSElement wds[2]; +unsigned long secs1,secs2; + + pb.ctl.ioCRefNum = refnum; + pb.ctl.ioCompletion = nil; + + pb.ctl.csCode = EAttachPH; + pb.info.EprotType = 0x809B; + pb.ecall.Ehandler = nil; + + if (PBControl((ParmBlkPtr) &pb,false)) /* attach special protocol using default handler */ + return(false); + + pb.ctl.csCode = ERead; + pb.info.EBuffPtr = (Ptr) &LBPR; + pb.info.EBuffSize = sizeof(LBpacket); + + if (PBControl((ParmBlkPtr) &pb,true)) /* setup a read using default handler */ + { + pb.ctl.csCode = EDetachPH; + PBControl((ParmBlkPtr) &pb,false); + return(false); + } + + pbw = pb; + wds[0].entryLength = Ethhdrsz + AppleDataSz; + wds[0].entryPtr = (Ptr) &LBPW; + wds[1].entryLength = 0; + LBPW.Destination = *enetaddr; + LBPW.Source = *enetaddr; + LBPW.EProtocoltype = 0x809B; + BlockMove((Ptr)AppleData,LBPW.testdata,AppleDataSz); + pbw.ecall.EWdsPointer = (Ptr) wds; + pbw.ctl.csCode = EWrite; + + if (PBControl((ParmBlkPtr) &pbw,false)) /* write a packet to ourself */ + { + killtest(&pbw,&pb); + return(false); + } + + GetDateTime(&secs1); + while (pb.ctl.ioResult == 1) /* wait for default read to complete or timeout */ + { + GetDateTime(&secs2); + if (secs2 - secs1 > 3) + { + killtest(&pbw,&pb); + return(false); + } + } + + pbw.ctl.csCode = EDetachPH; + PBControl((ParmBlkPtr) &pbw,false); + + if (!cmpdata(LBPR.testdata,LBPW.testdata,AppleDataSz)) /* check data looped back */ + return(false); + + return(true); +} diff --git a/DeclData/DeclNet/Loopback.c.idump b/DeclData/DeclNet/Loopback.c.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Loopback.c.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Loopback.c.rdump b/DeclData/DeclNet/Loopback.c.rdump new file mode 100644 index 0000000..4f21f55 --- /dev/null +++ b/DeclData/DeclNet/Loopback.c.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0081 0902 0000 0000" /* ..Monaco........ */ + $"0000 0043 7F10 FFFE 09EC 0003 0000 0000" /* ...C............ */ + $"0000 0006 0004 0082 0072 02A1 02AB 0082" /* .........r...... */ + $"0072 02A1 02AB A678 8BA0 0000 00C7 0000" /* .r.....x........ */ + $"00C7 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"0082 0072 02A1 02AB 0082 0072 02A1 02AB" /* ...r.......r.... */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"ACF4 9D69 3FE5 3230 0004 0000 0000 0000" /* ...i?.20........ */ + $"0000 A933 7396 A933 7396 A6F7 AE5C 0078" /* ...3s..3s....\.x */ + $"2B21 0000 0004 0001 2053 7570 6572 4D61" /* +!...... SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA00 0E43 6872 6973" /* .DeclNet...Chris */ + $"2050 6574 6572 7365 6E00 0131 000A 4C6F" /* Petersen..1..Lo */ + $"6F70 6261 636B 2E63 0000 0000 1F4E 6577" /* opback.c.....New */ + $"206C 6F63 6174 696F 6E20 666F 7220 524F" /* location for RO */ + $"4D4C 696E 6B20 746F 6F6C 2E0D 00" /* MLink tool... */ +}; + diff --git a/DeclData/DeclNet/Mace/MACEecfg.r b/DeclData/DeclNet/Mace/MACEecfg.r new file mode 100644 index 0000000..4fa50b3 --- /dev/null +++ b/DeclData/DeclNet/Mace/MACEecfg.r @@ -0,0 +1,89 @@ +/* + File: MACEecfg.r + + Contains: 'ecfg' resource templates for MACE built-in ethernet systems + + Written by: Mark A. Law + + Copyright: © 1992-1993 by Apple Computer, Inc., all rights reserved. + + Change History (most recent first): + + <1> 6/7/93 kc first checked in + 3/21/93 mal Versioned MACE 'ecfg' rsrc record and removed 24-bit MACEBase + field. + + To Do: +*/ + +Type 'ecfg' +{ + unsigned integer; /* Record version */ + unsigned hex longint; /* 32-bit MACE address */ + unsigned hex longint; /* Ethernet PROM address */ + unsigned hex byte; /* MACE transmit frame control */ + unsigned hex byte; /* MACE receive frame control */ + unsigned hex byte; /* MACE xmit/recv fifo config control */ + unsigned hex byte; /* MACE MAC config control */ + hex string [6]; /* Alternate ethernet address */ + unsigned integer; /* Alternate # transmit buffers */ + unsigned integer; /* Alternate # receive buffers */ + unsigned integer; /* Alternate # receive chains */ +}; + + +Resource 'ecfg' (43, "Cyclone33") { + 1, + 0x50F1C000, + 0x50F08000, + 0x1, + 0, + 0x2C, + 0x3, + $"", + 0, + 0, + 0 +}; + +Resource 'ecfg' (78, "Cyclone40") { + 1, + 0x50F1C000, + 0x50F08000, + 0x1, + 0, + 0x2C, + 0x3, + $"", + 0, + 0, + 0 +}; + +Resource 'ecfg' (60, "Tempest25") { + 1, + 0x50F1C000, + 0x50F08000, + 0x1, + 0, + 0x2C, + 0x3, + $"", + 0, + 0, + 0 +}; + +Resource 'ecfg' (79, "Tempest33") { + 1, + 0x50F1C000, + 0x50F08000, + 0x1, + 0, + 0x2C, + 0x3, + $"", + 0, + 0, + 0 +}; diff --git a/DeclData/DeclNet/Mace/MACEecfg.r.idump b/DeclData/DeclNet/Mace/MACEecfg.r.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Mace/MACEecfg.r.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Mace/MACEecfg.r.rdump b/DeclData/DeclNet/Mace/MACEecfg.r.rdump new file mode 100644 index 0000000..ba0f06a --- /dev/null +++ b/DeclData/DeclNet/Mace/MACEecfg.r.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0000 2120 0000 0000" /* ..Monaco..! .... */ + $"0000 0046 0000 0014 0006 1D98 0001 0045" /* ...F...........E */ + $"0013 0006 0004 002E 023D 0376 0472 0027" /* .........=.v.r.' */ + $"0005 036F 023A A7EF 2570 0000 00E7 0000" /* ...o.:..%p...... */ + $"0172 0000 0000 0100" /* .r...... */ +}; + +data 'MPSR' (1008) { + $"002E 023D 0376 0472 0027 0005 036F 023A" /* ...=.v.r.'...o.: */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"EC7C 5D24 3FE5 3230 0004 0000 0000 0000" /* .|]$?.20........ */ + $"0000 A933 739B A933 739B A6F7 B0C6 0078" /* ...3s..3s......x */ + $"BC36 0000 0008 0001 2553 7570 6572 4D61" /* .6......%SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA4D 6163 65BA 000E" /* .DeclNet.Mace... */ + $"4368 7269 7320 5065 7465 7273 656E 0001" /* Chris Petersen.. */ + $"3100 0A4D 4143 4565 6366 672E 7200 0000" /* 1..MACEecfg.r... */ + $"0010 6669 7273 7420 6368 6563 6B65 6420" /* ..first checked */ + $"696E 00" /* in. */ +}; + diff --git a/DeclData/DeclNet/Mace/Mace.a b/DeclData/DeclNet/Mace/Mace.a new file mode 100644 index 0000000..0e980d3 --- /dev/null +++ b/DeclData/DeclNet/Mace/Mace.a @@ -0,0 +1,2729 @@ +; +; File: Mace.a +; +; Contains: Routines to support MACE when coupled with a PSC-style DMA model. +; +; Written by: Mark A. Law ,3-March-92 +; +; Copyright: © 1992-1993 by Apple Computer, Inc. All rights reserved. +; +; This file is used in these builds: Mac32 +; +; Change History (most recent first): +; +; 7/26/93 mal Fixed bug where drvr can fail to open if VM on and logical to +; physical address mapping of recv buffers are not 1 to 1. See +; GetPkt(). +; 6/14/93 kc Roll in Ludwig. +; 5/14/93 mal #1084946 Fixed race between xmit interrupt and non-interrupt +; rtns. that could result in sending out-of-order packets. +; 5/3/93 mal #1082628 Fixed race between deferred task and int. hndlr. rtns. +; See MaceRecv:@exit for details. +; 5/1/93 mal #1082434 Changed calling sequence to GetMem/FreeMem (see +; MaceEnet.a). Removed PSC debugging code, we support ONLY most +; current PSC, ≥ upgraded EVT5. +; 3/21/93 mal Fix last checkin bug in WriteLAF where MACE_MAC_CONFIG must be +; saved. +; 3/21/93 mal Remove Curio A2 support, ie. evt3 support. Removed use of +; _SetIntMask. Write-once on bug-fixed PSC. +; 3/16/93 chp Replace references to the obsolete PSCIntTbl lomem with +; references to the equivalent field in ExpandMem. +; 2/17/93 mal Moved receive chain/buffer headers out of unused portion of DMA +; buffer and into separate memory block. +; 1/27/93 mal Added MACEecfg rsrc support. Changed promiscuous mode support to +; lower main codepath risk. +; 12/4/92 mal Turned off debug code; promiscuous change to MaceRecv(); no +; longer deliver pkts with overflow error; added RCVCO counter; +; improved error handling if TranslateAddress fails. +; 11/19/92 mal Added PSC-bug recv DMA chnl checks; made ResetMace more robust; +; chg'd alignment method on recv buffers; added rcv collision cnt; +; chg'd MaceHalt to dequeue DT +; 11/10/92 mal Fixed bug in Mace open that could corrupt memory byte off A3; +; Corrected reporting of Recv FIFO overflow to +; InternalMacRecvError. +; 10/30/92 mal Fixed race cond. between deferred task & int. hndlr to give +; better recv perf.; added cmd/stat reg debug cuz of psc hw bug; +; disable all ints at end of ResetMace; call FreeMemory if error +; in MaceInit; misc global cleanup; misc comment cleanup. +; 10/26/92 mal Updated to ESD's latest stats equs. +; 10/26/92 mal Fixed some bugs and modified recv/xmit buffer memory allocation +; loop in open(). +; 10/13/92 mal -perf. improvement: removed all memory indirect preindexed ea's; +; -changed status to lw and always deliver to RecvRtn; -added temp +; code to handle PSC addr/cnt bug on 33 Mhz evt4. +; <1> 10/6/92 GDW New location for ROMLink tool. +; 9/14/92 mal -Updated SNMP counters; -added temp code to handle all Curio +; revs up to B0 +; 7/27/92 mal Added temp code to handle version 1 'ebfr's. +; 7/25/92 mal Added support for HW's maximum receive buffer configuration. +; Fixed xmit path bug where pkts could be sent out of order +; (stress). Fixed recv path bug to ensure correct reg set primed +; when only 1 chain available (heavy stress). Added recv/xmit +; bus error handlers. Improved MACEHALT routine. +; 6/26/92 mal Expanded # of maceinit parms saved in globals. +; 6/22/92 mal New drvr to support PSC2's (EVT2) Ethernet DMA receive model. +; 5/21/92 RB Removed the inclusion of VMCalls.a, got rid of a warning +; branch to next instruction and included InternalOnlyEqu.a +; 5/5/92 mal Removed some unused global vars +; 4/30/92 mal Expanded interface between MaceEnet.a and Mace.a. +; +; To Do: +; +; Notes: Initial version provides support for Cyclone builtin Ethernet. +; +; + + PRINT OFF + INCLUDE 'SysEqu.a' ; System definitions + INCLUDE 'SysErr.a' ; System errors + INCLUDE 'Traps.a' ; Traps definitions + INCLUDE 'GestaltEqu.a' + INCLUDE 'InternalOnlyEqu.a' ; lowmem globals + INCLUDE 'HardwarePrivateEqu.a' + INCLUDE 'UniversalEqu.a' ; lowmem global records + INCLUDE 'ATalkMacros.a' ; Nifty Macros + INCLUDE 'SysPrivateEqu.a' ; ExpandMem defs + +; Conditional compile equates +COUNTERS EQU 0 +BUFDEBUG EQU 0 +DEBUG EQU 0 +SETDEBUG EQU 0 +SETDEBUGFAIL EQU 0 +SETCSDEBUG EQU 0 +SETCSDEBUGFAIL EQU 0 +USEDEFERREDTASK EQU 1 +PROM EQU 1 + + PRINT NOGEN,NOMDIR,ON + INCLUDE 'MaceEqu.a' ; Mace definitions + INCLUDE 'PSCEqu.a' ; PSC definitions + INCLUDE 'ENETEqu.a' ; Driver definitions + INCLUDE 'SNMPLAP.a' ; SNMP definitions + EJECT + +;_______________________________________ +; +; Misc definitions +;_______________________________________ + +OneWdsSz EQU 8 ; single fragment wds size +INTLockOut EQU $0700 ; SR value to disable ALL interrupts +DMALockOut EQU $0400 ; SR value to disable PSC DMA interrupts +NeedDefer EQU 5 ; bit indicates VM is running + ; •••• warning, MaxChns should NOT be set > 64. It could make some calcs in the + ; •••• MaceInit rtn overflow the 16 bit low-order word! +MaxChns EQU 64 ; max number of chains +OneChn EQU 1 ; one chain, minimum too +DefChns EQU 4 ; default number of chains +MaxBufpChn EQU 1023 ; max number of buffers per chain +DefTxBuffs EQU 8 ; default number of xmit buffers +DefRxBuffs EQU 16 ; default number of recv buffers +MinBufpChn EQU 2 ; min number of buffers per chain +;MACERevA2 EQU $0941 +MACERevB0 EQU $0940 + +MaceVars RECORD 0 ; our variables +MACEmem DS.l 1 ; ptr to memory block with recv & xmit buffers +RecvBuffMem DS.l 1 ; aligned recv buffer mem +XmitBuffMem DS.l 1 ; aligned xmit buffer mem +RecvXmitMemSz DS.l 1 ; need size of aligned mem if need to free it +ChnDescrMem DS.l 1 ; recv chain descriptor mem +MACEBase DS.l 1 ; MACE base address +PSCBase DS.l 1 ; PSC base address +DTQE DS.b dtQElSize ; Deferred task queue element +DTInstalled DS.b 1 ; flag, non-zero if DT installed + DS.b 1 ; fill +MACEChipID DS.w 1 ; MACE revision + ALIGN 4 +; ••• parms saved from MaceInit call +RcvRtn DS.l 1 ; users recv rtn +RcvParm DS.l 1 ; users recv rtn parm +XmtDnRtn DS.l 1 ; users xmit completion rtn +XmtDnParm DS.l 1 ; users xmit completion rtn parm +MCfg DS.l 1 ; ptr to MACE config record +Dot3StatPtr DS.l 1 ; ptr to 802.3 statistics counters +LAPMIBStatPtr DS.l 1 ; ptr to LAP MIB statistics counters +OurAddrPtr DS.l 1 ; ptr to ethernet address +MemMove DS.l 1 ; ptr to fast memory move rtn +; ••• end parms +; ActRecvSet is REQUIRED since it enables the Recv processing to ensures that recv +; pkts are processed IN ORDER. +ActRecvSet DS.w 1 ; offset to active recv reg set +; ActXmitSet helps, ie. not necessary, the Xmit DONE processing by pting to the "oldest" reg +; set that has completed a xmit. For cases where both sets have a xmit done int, this +; will make available the next set that can perform a xmit, the "oldest". +; NxtXmitSet is REQUIRED since it enables the Xmit PRIME processing to ensures that xmit +; pkts are sent IN ORDER. +ActXmitSet DS.w 1 ; offset to active xmit reg set +NxtXmitSet DS.w 1 ; offset to xmit reg set for next xmit +; ••••• WARNING: Do NOT add or delete any parms in this range +; The offsets between RxChainSet0,RxChainSet1 & +; TxBuffSet0,TxBuffSet1 MUST be maintained +CntlRegSetByte EQU $0001 ; AND with cntrl reg to get inactive set +RegSet1Offset EQU $10 ; Reg Set1 offset from Channel base + ALIGN 4 +RxChainSet0 DS.l 1 ; Log addr of chain assigned to Set0 +FreeRxChain DS.l 1 ; head of free recv chain list +InUseRxHead DS.l 1 ; head of InUse recv chain list +InUseRxTail DS.l 1 ; tail of InUse recv chain list +RxChainSet1 DS.l 1 ; Log addr of chain assigned to Set1 +TxBuffSet0 DS.l 1 ; Log addr of buffer assigned to Set0 +FreeXmtBuff DS.l 1 ; head of free xmit buffers list +InUseTxHead DS.l 1 ; head of InUse xmit buffers list +InUseTxTail DS.l 1 ; tail of InUse xmit buffers list +TxBuffSet1 DS.l 1 ; Log addr of buffer assigned to Set1 +; ••••• END WARNING +COLLCnt DS.l 1 ; recv frames with collision error + ; Transmit Frame Status Register counters +XmtStatINV DS.l 1 ; xmit ints with xmit status invalid +XmtLCOL DS.l 1 ; late collision +XmtRTRYCnt DS.l 1 ; total number of retries + ; Interrupt Register counter +RCVCOCnt DS.l 1 ; *256 to get # collisions on net +MPCOCnt DS.l 1 ; *256 to get # of missed packets due to + ; RcvOFLO, receiver disabled, or excessive + ; receive frame count (RcvFC) + ; +RecvBerr DS.w 1 ; recv chnl bus error being processed +XmitBerr DS.w 1 ; xmit chnl bus error being processed + IF COUNTERS THEN +RcvInts DS.l 1 ; # of times MACE int rtn called for a recvint +PSCIntCnt DS.l 1 ; # of times PSC Int Rtn called +MaceIntCnt DS.l 1 ; # of times MACE Int Rtn called +MaceRcvCnt DS.l 1 ; # of times Deferred Recv Task called +; ••••• WARNING: Do NOT add or delete any parms in this range +; The offsets between RecvSet0Cnt,RecvSet1Cnt; DTprimeSet0,DTprimeSet1; & +; XmitSet0Cnt,XmitSet1Cnt MUST be maintained +RecvSet0Cnt DS.l 1 ; # of recv frames on set 0 +DTprimeSet0 DS.l 1 ; # of times DT primed reg set 0 +XmitSet0Cnt DS.l 1 ; # of xmit frames on set 0 +NoFreeChains DS.l 1 ; # of times no free chains available +RecvSet1Cnt DS.l 1 ; # of recv frames on set 1 +DTprimeSet1 DS.l 1 ; # of times DT primed reg set 0 +XmitSet1Cnt DS.l 1 ; # of xmit frames on set 1 +; ••••• END WARNING +XmitRSFull DS.l 1 ; Cnt of RegSets full on MaceXmit, -> InUse +InUseXmit DS.l 1 ; Cnt of xmits done from InUse Queue +InUseXmitD DS.l 1 ; Cnt of xmits removed from InUse Queue +XmitPend DS.l 1 ; Cnt of DoWrite calls from MaceXmitDone +noDTInstall DS.l 1 ; # of times didn't install deferred task + ; since it was already installed +ChnFlushed DS.l 1 ; # of times a chn was flushed +RecvBerrCnt DS.l 1 ; # of bus error's on recv chnl +XmitBerrCnt DS.l 1 ; # of bus error's on xmit chnl + ENDIF + IF BUFDEBUG THEN +RecvBerrAddr DS.l 1 ; addr that caused bus error on recv chnl +RecvBerrCntl DS.w 1 ; Cntl reg, look at set byte +XmitBerrAddr DS.l 1 ; addr that caused bus error on xmit chnl +XmitBerrCntl DS.w 1 ; Cntl reg, look at set byte +XmtDnActive DS.l 1 +CurrRecv DS.l 1 + ENDIF + IF SETDEBUG THEN +hasNewPSC DS.b 1 ; non-zero = new psc, 0 = old psc + ALIGN 4 + ENDIF +LogAddrFltr DS.b 8 ; Copy of MACE Logical Address Filter + ; bit order 63-56, 55-48, ... 7-0 +LAFHashTbl DS.b 64 ; Tbl of counts of number multicasts addresses + ; that hash to each bit +MaceVarSz EQU * ; End of variables + ENDR + +; +; Transmit Buffer template +; -ensure 1st one is quad-aligned and all the rest will be +XmitBuff Record 0 +Next DS.l 1 ; Ptr to next buffer +Prev DS.l 1 ; Ptr to previous buffer +LogBufPtr DS.l 1 ; Logical address of packet data area +WDSptr EQU * ; Address of 1 entry WDS +Len DS.w 1 ; Packet length +PhyBufPtr DS.l 1 ; Physical address of packet data area +Status DS.b 1 + ALIGN 16 +LogBufOff EQU LogBufPtr - * ; Offset from packet data area + ; to Logical address of packet data area +HdrBufOff EQU XmitBuff - * ; Offset from buffer header + ; to packet data area +Packet DS.b Max_Pkt_Size ; packet data area + ALIGN 16 +TxBuffSz EQU * + EndR +; +; Receive Buffer template +; -ensure 1st one is quad-aligned and all the rest will be +RecvBuff Record 0 +MaceStat DS.b 8 ; Recv'd pkt status from Mace + DS.b 8 ; fill, PSC DMAs quad-lw chunks +Packet DS.b Max_Pkt_Size ; packet data area + ALIGN 2048 +RxBuffSz EQU * + EndR + +; +; Receive Chain Descriptor template +; +RxChnDescr Record 0 +NextChn DS.l 1 ; ptr to next chain descr +PhyChnPtr DS.l 1 ; Physical address of chain +LogChnPtr DS.l 1 ; Logical address of chain +State DS.b 1 ; state of this chain + DS.b 1 ; fill +OnOffSet EQU 0 ; bit 0: 0-not on, 1-on reg set +Flushed EQU 1 ; bit 1: 0-no flush, 1-flush occurred +Berred EQU 2 ; bit 2: 0-no berr, 1-berr occurred +Limit DS.w 1 ; # of buffers in this chain +Out DS.w 1 ; # of next buffer to drain +In DS.w 1 ; # of next buffer to be filled with pkt + ; only valid when chain OFF reg set +savedLimit DS.w 1 ; only needed after flush done on chain +RxChnDescrSz EQU * + EndR + + EJECT + + STRING PASCAL + MACHINE MC68020 + +MaceData PROC + ENTRY MaceVarPtr +MaceVarPtr Dc.l 1 ; Contains ptr to my variables + ENDP + + +;________________________________________________________________________ +; +; RecoverXmitBuffs - move any xmit buffers from DMA chnl to free queue. +; +; Call: A2 - globals +; Return: none +; +;________________________________________________________________________ + +RecoverXmitBuffs PROC + WITH MACERegs,MaceVars,PSC_DMA_CHNL + + ; Put transmit buffs back on freelist + MoveQ #0, D0 ; reg set 0 offset +@chgsets Move.l TxBuffSet0(A2,D0), D1 + Beq.s @nobuff + Clr.l TxBuffSet0(A2,D0) + MoveA.l D1, A0 + Move.l FreeXmtBuff(A2), XmitBuff.Next(A0) ; Make us pt to head of freelist + Move.l A0, FreeXmtBuff(A2) ; Make us head of freelist +@nobuff BChg #4, D0 + Beq.s @chgsets + + Rts + + ENDP + +;________________________________________________________________________ +; +; ResetXmitChnl - reset PSC's MACE DMA xmit channel, reset MACE xmit FIFO, +; move any xmit buffers from DMA chnl to free queue. +; +; Call: A2 - globals +; Return: none +; +;________________________________________________________________________ + +ResetXmitChnl PROC + WITH MACERegs,MaceVars,PSC_DMA_CHNL + + ; Reset PSC DMA xmit chnl + ; -leaves chnl paused + ; -clears set ENABLE's + MoveA.l PSCBase(A2), A0 + Move #(1< Mace Recv DMA channel + +@initset Move.l FreeRxChain(A2), D0 ; Dequeue next available recv chain + Beq.s @nocando ; none available, leave + MoveA.l D0, A1 + Move.l NextChn(A1), FreeRxChain(A2) + Clr.l NextChn(A1) + + IF SETDEBUG THEN + Bsr InitRecv ; Prime Register Set + ELSE + Bsr.s InitRecv ; Prime Register Set + ENDIF + + BChg #4, D4 ; Toggle reg sets + Beq.s @initset ; if D2 was $0 (set 0), init set 1 +@nocando + MoveM.l (SP)+, A3/D4 + Rts + + ENDP + EJECT + +;________________________________________________________________________ +; +; PrimeRecv - Prime reg set with chain from free queue +; +; Call: +; A2 - our variables +; A3 - Receive DMA Channel Reg Set base address +; D4 - Register set offset +; +; Return: none +; +; Notes: +; -can trash C scratch regs: A0-A1,D0-D2 +;________________________________________________________________________ + +PrimeRecv PROC + WITH MACERegs,MaceVars,PSC_DMA_CHNL,RxChnDescr + MoveA.l RxChainSet0(A2,D4), A0 ; get active chain descriptor ptr + IF BUFDEBUG THEN + Move.l A0, D1 + Bne.s @noprob + _Debugger +@noprob + ENDIF + Clr.l RxChainSet0(A2,D4) ; indicate no chain on reg set + BClr #OnOffSet, State(A0) ; indicate this chain NOT on reg set +; +; Put this recv chain on InUse queue +; + Move.l InUseRxTail(A2), D1 ; Something on the queue? + Bne.s @61 ; Yes + ; Empty queue + Move.l A0, InUseRxTail(A2) ; Point tail at us + Move.l A0, InUseRxHead(A2) ; Point head at us + Bra.s @62 +@61 ; Items on queue + Move.l D1, A1 ; Get tail + Move.l A0, NextChn(A1) ; Put on end of queue + Move.l A0, InUseRxTail(A2) ; Make tail pt to us +@62 + Clr.l NextChn(A0) +; +; Setup offset to active chain for DT. Since all buffers in chain are full or we flushed, +; PSC will have switched to other reg set. +; + BChg #4, D4 ; toggle reg set offset + Move D4, ActRecvSet(A2) ; chg offset to active reg set + BChg #4, D4 ; toggle back reg set offset + + Tst.b RecvBerr(A2) ; are we're processing buserror? + Bne.s @bye ; yes, leave + +; +; Dequeue next available recv chain +; + Move.l FreeRxChain(A2), D1 + IF COUNTERS THEN + Bne.s @getfreechain + AddQ.l #1, NoFreeChains(A2) ; no chains available + Bra.s @bye +@getfreechain + ELSE + Beq.s @bye ; no chains available + ENDIF + MoveA.l D1, A1 ; A1->addr of recv chain descriptor + Move.l NextChn(A1), FreeRxChain(A2) ; Dequeue from free list + Clr.l NextChn(A1) + + Bsr InitRecv ; prime reg set with this chain + +@bye Rts ; leave + + ENDP + EJECT + +;________________________________________________________________________ +; +; ResetMACE - Reset PSC & MACE FIFOs and disable recv & xmit paths and reset MACE +; +; Call: A2 - drvr vars +; +; Return: none +; +; Destroys: A1,D0,D1 +; +;________________________________________________________________________ + +ResetMACE PROC EXPORT + WITH MACERegs,MaceVars,PSC_DMA_CHNL + +; reset & disable MACE -> PSC receive path + MoveA.l MACEBase(A2), A0 ; A0-> base address of MACE regs + MoveA.l PSCBase(A2), A1 ; A1-> base address of PSC regs + + Move.b #0, MACE_MAC_CNFG(A0) ; Disable MACE recv, xmit, et. al. + + Move.b MACE_FIFO_CNFG(A0), D0 ; Get current FIFO config + OrI.b #(1< MACE transmit path + Move #(1< PSC Interrupt table ptr + ENDWITH + MoveQ #0, D0 + Move.l D0, MACE_RECVhndlr(A0) + Move.l D0, MACE_RECVparm(A0) + Move.l D0, MACE_XMIThndlr(A0) + Move.l D0, MACE_XMITparm(A0) + + ; Install Mace Interrupt handler, called at Level 3 + Move.l PSCBase(A2), A1 ; Base address of PSC + Move.b #(1< my variables +; +; Return: +; none +; +; Uses: +; A1, D0 +; +; The LAF can not be updated while MACE recv is enabled. Disable MACE pkt +; reception. If frames in MACE Recv FIFO, reset MACE Recv FIFO (possible pkt +; loss), flush PSC recv FIFO, and reprime affected DMA Reg. Set. Finally, +; update the LAF. +;________________________________________________________________________ + +WriteLAF PROC + WITH MACERegs,MaceVars,PSC_DMA_CHNL + MoveA.l MACEBase(A2), A1 + + Move.b MACE_MAC_CNFG(A1), -(SP) ; Save current config + + Move.b #(1< copy of logical address filter + Move.b #(1< 6 bit hash into LAF + AddQ.b #1, (LAFHashTbl,A2,D0) ; Inc. # of multi's with this hash + CmpI.b #1, (LAFHashTbl,A2,D0) ; Multiaddr hash bit already in LAF? + Bhi @bye ; yes, do nothing + + Lea LogAddrFltr(A2), A0 ; A0-> copy of log. addr. filter + Cmp.b #31, D0 ; Hash > 31? + Bhi.s @b63to32 ; yes + Move.l 4(A0), D1 ; no, get LAF bits 31-0 + BSet.l D0, D1 ; Is this hash bit already set? + Bne @bye ; yes, nothing to do + Move.l D1, 4(A0) ; Save modified LAF bits 31-0 + Bra.s @doit + +@b63to32 Sub.b #32, D0 ; Convert hash for use on LAF bits 63-32 + Move.l (A0), D1 ; Get LAF bits 63-32 + BSet.l D0, D1 ; Is this hash bit already set? + Bne @bye ; yes, nothing to do + Move.l D1, (A0) ; Save modified LAF bits 63-32 + +@doit Bsr WriteLAF ; Write the new LAF + +@bye Move.l (SP)+, A2 ; Restore used C regs + Rts + ENDP + EJECT + +;___________________________________________________________________________ +; +; MaceDelMulti - Delete a multicast address HASH from the LAF +; +; Call: +; D1 = first two bytes of address +; D3 = last four bytes of address +; +; Return: +; none +; +; Computes the hash for this multicast address and decrements the LAF +; Table hash count for the given Multicast address. If new hash count = 0, +; clears appropriate bit in MACE LAF. +; Depends on caller to ensure not called for a multicast's hash that hasn't +; already been inc'd in LAFHashTbl. +;___________________________________________________________________________ + +MaceDelMulti PROC EXPORT + WITH MACERegs,MaceVars + + Move.l A2, -(SP) ; Save used C regs + MoveA.l MaceVarPtr, A2 ; Get ptr to my vars + + Bsr DoCRC ; D0-> 6 bit hash into LAF + SubQ.b #1, (LAFHashTbl,A2,D0) ; Dec. # of multi's with this hash + Bne @bye ; Do nothing if hash table cnt non-zero + + ; Clear this bit in LAF since no other + ; multiaddr's hash to this bit + Lea LogAddrFltr(A2), A0 ; A0-> copy of log. addr. filter + Cmp.b #31, D0 ; Hash > 31? + Bhi.s @b63to32 ; yes + Move.l 4(A0), D1 ; no, get LAF bits 31-0 + BClr.l D0, D1 ; Clear this hash bit + IF DEBUG THEN + Beq @huh ; if LAFHashTbl correct, D1 should + ELSE ; have D0 bit set! + Beq @bye ; do nothing hash bit already clear! + ENDIF + Move.l D1, 4(A0) ; Save modified LAF bits 31-0 + Bra.s @doit + +@b63to32 Sub.b #32, D0 ; Convert hash for use on LAF bits 63-32 + Move.l (A0), D1 ; Get LAF bits 63-32 + BClr.l D0, D1 ; Clear this hash bit + IF DEBUG THEN + Beq @huh ; if LAFHashTbl correct, D1 should + ELSE ; have D0 bit set! + Beq @bye ; do nothing hash bit already clear! + ENDIF + Move.l D1, (A0) ; Save modified LAF bits 63-32 + +@doit Bsr WriteLAF ; Write the new LAF + +@bye Move.l (SP)+, A2 ; Restore used C regs + Rts + + IF DEBUG THEN +@huh _Debugger ; nothing to do 'cause hash bit + Bra.s @bye ; was already clear + ENDIF + + ENDP + EJECT + +;___________________________________________________________________________ +; +; PrimeXmitRS - Prime Reg Set with transmit packet info. +; +; Call: +; 4(SP) - xmit buffer ptr +; A2 - our vars +; +; Return: +; If xmit register sets are full, return CC==NE; else, CC==EQ. +; Notes: +; Called both on normal writes (with level 4 interrupts disabled) +; AND on write completions (interrupt level 4) +;___________________________________________________________________________ + +PrimeXmitRS PROC + +XmitPrm RECORD 4 +XmitPtr DS.l 1 ; Transmit buffer ptr +ParmSz EQU * + ENDR + + WITH MACERegs,MaceVars,PSC_DMA_CHNL,LAPMIBStats + + Move.l XmitPrm.XmitPtr(SP), D1 ; D1 - xmit buffer ptr + +; Move SR,-(SP) ; Save interrupt mask level +; OrI #DMALockOut, SR ; Disable DMA ints. + + Move NxtXmitSet(A2), D2 ; get offset to next reg set to xmit on + Lea TxBuffSet0(A2), A1 + Tst.l (A1,D2) ; Can we use this reg set? + Beq.s @cont2 ; yes + +; Move (SP)+,SR ; Restore int. mask level + MoveQ #-1, D0 ; Set CC's + Rts ; Return + +; +; Initialize Xmit DMA Channel Register Set +; +@cont2 + MoveA.l PSCBase(A2), A0 + Lea PSC_MACE_XMIT(A0), A0 ; A0-> Xmit DMA Channel base addr + + Move.l D1, (A1,D2) ; Indicate (D1) is active buff on reg set + MoveA.l D1, A1 ; A1->xmit buffer + + IF SETDEBUG THEN + IF not SETDEBUGFAIL THEN + Tst.b hasNewPSC(A2) + Beq.s @a01 ; go to old PSC patch + Move.l XmitBuff.PhyBufPtr(A1), Addr(A0,D2) ; Set DMA dest addr + Bra.s @aaa1 +@a01 + ENDIF + Move.l XmitBuff.PhyBufPtr(A1), D0 + And.l #$FFFFFFF0, D0 ; line aligned addr +@a1 Move.l XmitBuff.PhyBufPtr(A1), Addr(A0,D2) ; Set DMA dest addr + Move.l Addr(A0,D2), D1 + And.l #$FFFFFFF0, D1 ; line aligned addr + Cmp.l D0, D1 + IF SETDEBUGFAIL THEN + Beq.s @aa1 + _Debugger + Bra.s @a1 +@aa1 + ELSE + Bne.s @a1 +@aaa1 + ENDIF + ELSE + Move.l XmitBuff.PhyBufPtr(A1), Addr(A0,D2) ; Set DMA dest addr + ENDIF + + MoveQ #0, D0 + Move.w XmitBuff.Len(A1), D0 ; Get DMA byte count (word) + + IF SETDEBUG THEN + IF not SETDEBUGFAIL THEN + Tst.b hasNewPSC(A2) + Beq.s @a02 ; go to old PSC patch + Move.l D0, Cnt(A0,D2) ; Set DMA byte count (long) + Bra.s @aaa2 +@a02 + ENDIF +@a2 Move.l D0, Cnt(A0,D2) ; Set DMA byte count (long) + Move.l Cnt(A0,D2), D1 + Cmp.l D0, D1 + IF SETDEBUGFAIL THEN + Beq.s @aa2 + _Debugger + Bra.s @a2 +@aa2 + ELSE + Bne.s @a2 +@aaa2 + ENDIF + ELSE + Move.l D0, Cnt(A0,D2) ; Set DMA byte count (long) + ENDIF + + BTst #0, XmitBuff.Packet(A1) ; xmiting a multi/bcast? + MoveA.l LAPMIBStatPtr(A2), A1 + Bne.s @30 + AddQ.l #1, ifOutUcastPkts(A1) ; inc. non-multi/bcast cntr + Bra.s @31 +@30 AddQ.l #1, ifOutNUcastPkts(A1) ; inc. multi/bcast cntr +@31 Add.l D0, ifOutOctets(A1) ; inc. sent octet cntr + + IF SETCSDEBUG THEN + IF not SETCSDEBUGFAIL THEN + Tst.b hasNewPSC(A2) + Beq.s @a03 ; go to old PSC patch + Move #(1< + MoveQ #0, D0 ; Set CC's + Rts ; Return + + ENDP + EJECT + +;___________________________________________________________________________ +; +; RecvBusErr - handle bus errors on PSC's MACE DMA receive channel +; +; Call: +; A2 - our variables +; D1 - Receive DMA Channel control register value +; +; Return: +; none +; Notes: +; Should never get called! +;___________________________________________________________________________ + +RecvBusErr PROC + WITH MACERegs,MaceVars,PSC_DMA_CHNL,RxChnDescr + + ST RecvBerr(A2) ; indicate we're processing buserror + IF COUNTERS THEN + AddQ.l #1, RecvBerrCnt(A2) + ENDIF + MoveA.l MACEBase(A2), A0 + Move.b MACE_MAC_CNFG(A0), D0 ; get current config + Move.b D0, -(SP) ; save it + BClr #ENRCV, D0 + Move.b D0, MACE_MAC_CNFG(A0) ; Disable recv + + IF BUFDEBUG THEN + Move D1, RecvBerrCntl(A2) ; save chnl control reg + MoveQ #0, D0 ; assume set 0 + BTst #0, D1 ; which set had bus error? + Beq.s @set0 + BChg #4, D0 ; chng to set 1 +@set0 MoveA.l PSCBase(A2), A0 + Lea PSC_MACE_RECV(A0), A0 ; A0-> base addr of recv DMA chnl + Move.l Addr(A0,D0), RecvBerrAddr(A2) ; save addr of bus error + ENDIF + + ; Reset MACE FIFO + Bsr FlushRecvRegSet ; and put chain in InUse (PrimeRecv). + ; NOTE: PrimeRecv toggles ActRecvSet(A2) + Bsr FlushRecvChn ; put other chain in InUse (PrimeRecv). + + MoveA.l PSCBase(A2), A0 + Move #(1< base addr of xmit DMA chnl + Move.l Addr(A0,D0), XmitBerrAddr(A2) ; save addr of bus error + ENDIF + ; Reset PSC's MACE DMA xmit chnl and reset MACE xmit FIFO + Bsr ResetXmitChnl ; and put any xmit buffs on free queue. + + Clr.b XmitBerr(A2) ; indicate we're DONE processing buserror + + Rts + + ENDP + EJECT + +;___________________________________________________________________________ +; +; MaceXmit - Calls PrimeXmitRS to prime Reg Set with transmit packet info. +; If xmit register sets are full, put xmit buffer ptr on tail +; of xmit InUse queue. +; +; Call: +; 4(SP) - WDS ptr +; +; Return: +; D0 = error code; nobuff - temporarily out of xmit buffers +; eLenErr - sum of data in WDS > max. pkt size +; noErr - primed reg set with xmit pkt or put pkt +; on xmit InUse queue +; Notes: +; Called both on normal writes AND write completion (interrupt level 4) +;___________________________________________________________________________ + +MaceXmit PROC EXPORT + +WDSPrm RECORD 4 ; Return address +WDSPtr DS.l 1 ; Write Data Structure ptr +ParmSz EQU * + ENDR + + WITH MACERegs,MaceVars + + Move.l WDSPrm.WDSPtr(SP), D2 ; Get WDS ptr + Move.l A2, -(SP) ; Save C regs + + MoveA.l MaceVarPtr, A2 ; Get ptr to my vars + + Move SR,-(SP) ; Save interrupt mask level + OrI #DMALockOut, SR ; Disable DMA ints. + + Move.l FreeXmtBuff(A2),D1 ; get a buffer pointer + Bne.s @haveBuff + + Move (SP)+,SR ; Restore int. mask level + MoveA.l (SP)+, A2 ; Restore C regs + MoveQ #nobuff,D0 ; Set no xmit buff available error + Rts ; return to caller +@haveBuff + MoveA.l D1, A1 ; A1->buffer + IF BUFDEBUG THEN + CmpA.l XmitBuff.Next(A1), A1 ; linked to myself? + Bne.s @dok1 + _Debugger ; yes, oooppppsss! +@dok1 + CmpA.l InUseTxHead(A2), A1 ; on Free as well as InUse? + Bne.s @dok2 + _Debugger ; yes, oooppppsss! +@dok2 + ENDIF + Move.l XmitBuff.Next(A1),FreeXmtBuff(A2) ; unlink buffer from free list + Clr.l XmitBuff.Next(A1) + Move (SP)+,SR ; Restore int. mask level +; +; Total the length and make sure it's valid +; + Move.l A1, -(SP) ; save buffer pointer for later + + Move.l A4, -(SP) ; save non-interrupt scratch reg. + + Clr.w XmitBuff.Len(A1) ; init len + Move.l D2, A4 ; A4-> WDS +@1 + MoveQ #0,D0 + Move.w (A4), D0 ; get this wds entry length + Beq.s @2 ; all done + AddQ.w #6, A4 ; inc to next wds entry length + Add.w D0, XmitBuff.Len(A1) ; sum the length + Bra.s @1 ; look for more +@2 + Move.w XmitBuff.Len(A1),D1 ; get single fragment length + Sub.w #EHdrSize,D1 ; Subtract out header bytes + Cmp.w #EMaxDataSz,D1 ; Check the data's length + Bls.s @cont ; Branch if ok +; +; Length error, relink buffer onto free list and return error +; + MoveA.l (SP)+, A4 ; restore non-interrupt scratch reg. + MoveA.l (SP)+, A1 ; Pop buff ptr + + Move SR,-(SP) ; Save interrupt mask level + OrI #DMALockOut, SR ; Disable DMA ints. + + Move.l FreeXmtBuff(A2), XmitBuff.Next(A1) ; link buffer back into free list + Move.l A1, FreeXmtBuff(A2) + + Move (SP)+,SR ; Restore int. mask level + MoveA.l (SP)+, A2 ; Restore C regs + MoveQ #eLenErr,D0 ; Set length error + Rts ; Return it +; +; Copy WDS data to our Xmit buffer +; +@cont + MoveA.l XmitBuff.LogBufPtr(A1), A1 ; A1->packet data + MoveA.l D2, A4 ; A4-> WDS +@3 + Move.w (A4)+, D0 ; last WDS entry? + Beq.s @4 ; yes, all done + MoveA.l (A4)+, A0 ; get pointer to the data + ; A0->source, A1->dest, D0=len + MoveM.l A1/D0,-(SP) ; save buff ptr and len + Jsr ([MemMove,A2]) ; move the data + MoveM.l (SP)+,A1/D0 + AddA.l D0, A1 ; update buff ptr + Bra.s @3 ; look for more +@4 + MoveA.l (SP)+, A4 ; restore non-interrupt scratch reg. + ; (SP) -> Xmit buffer ptr pushed earlier + + MoveA.l (SP)+, A1 ; Pop buff ptr + Move SR,-(SP) ; Save interrupt mask level + OrI #DMALockOut, SR ; Disable DMA ints. + Move.l A1, -(SP) ; Push buff ptr + + Jsr PrimeXmitRS + Bne.s @regsetsfull + AddQ #4, SP ; Strip parms + Move (SP)+, SR ; + MoveA.l (SP)+, A2 ; Restore C regs + MoveQ #0, D0 ; Set return code & CC's + Rts ; Return +; +; We were NOT able to queue this buffer in a reg set +; Put this xmit buffer on xmit InUse queue +; +@regsetsfull + IF COUNTERS THEN + AddQ.l #1, XmitRSFull(A2) + ENDIF + MoveA.l (SP)+, A1 ; Restore xmit buffer ptr + +; Move SR,-(SP) ; Save interrupt mask level +; OrI #DMALockOut, SR ; Disable DMA ints. + + Move.l InUseTxTail(A2), D1 ; Something on the queue? + Bne.s @11 ; Yes, branch + ; Empty queue + Move.l A1, InUseTxTail(A2) ; Point tail at us + Move.l A1, InUseTxHead(A2) ; Point head at us + Bra.s @22 +@11 ; Items on queue + Move.l D1, A0 ; Get tail + Move.l A1, XmitBuff.Next(A0) ; Put on end of queue + Move.l A1, InUseTxTail(A2) ; Make tail pt to us +@22 + Clr.l XmitBuff.Next(A1) + + Move (SP)+,SR ; Restore int. mask level + MoveA.l (SP)+, A2 ; Restore C regs + MoveQ #0, D0 ; Set return code & CC's + Rts ; Return + + ENDP + EJECT + + IF PROM THEN +;___________________________________________________________________________ +; +; MACEXmitProm - xmit packet directly from user's buffer +; +; Call: +; 4(SP) - xmit buffer ptr +; +; Return: +; If xmit register sets are full, return CC==NE; else, CC==EQ. +; Notes: +; Called both on normal writes AND write completion (interrupt level 4) +;___________________________________________________________________________ + +MACEXmitProm PROC EXPORT + +XmitPrm RECORD {A6Link} +LocalSize EQU * +A6Link DS.l 2 +XmitPtr DS.l 1 ; Transmit buffer ptr +XmitLen DS.w 1 ; Transmit buffer len + ENDR + + WITH MACERegs,MaceVars,PSC_DMA_CHNL,LAPMIBStats,XmitPrm + + Link A6,#LocalSize ; Save A6 + MoveM.l A2, -(SP) + MoveA.l MaceVarPtr, A2 ; Get ptr to my vars + + Move SR,-(SP) ; Save interrupt mask level + OrI #DMALockOut, SR ; Disable DMA ints. + + Move NxtXmitSet(A2), D2 ; get offset to next reg set to xmit on + MoveA.l PSCBase(A2), A0 + Lea PSC_MACE_XMIT(A0), A0 ; A0-> Xmit DMA Channel base addr +@chkxmtdn Move CmdStat(A0,D2), D0 ; Get DMA status (word) + Btst #TERMCNT, D0 ; xfer in progress? + Beq.s @chkxmtdn ; yes, wait for it to complete + ; no, we can use this set +; +; Initialize Xmit DMA Channel Register Set +; + Move.l XmitPtr(A6), A1 ; A1 - user xmit buffer ptr + IF SETDEBUG THEN + IF not SETDEBUGFAIL THEN + Tst.b hasNewPSC(A2) + Beq.s @a01 ; go to old PSC patch + Move.l A1, Addr(A0,D2) ; Set DMA dest addr to user buff ptr + Bra.s @aaa1 +@a01 + ENDIF + Move.l A1, D0 + And.l #$FFFFFFF0, D0 ; line aligned addr +@a1 Move.l A1, Addr(A0,D2) ; Set DMA dest addr + Move.l Addr(A0,D2), D1 + And.l #$FFFFFFF0, D1 ; line aligned addr + Cmp.l D0, D1 + IF SETDEBUGFAIL THEN + Beq.s @aa1 + _Debugger + Bra.s @a1 +@aa1 + ELSE + Bne.s @a1 + ENDIF +@aaa1 + ELSE + Move.l A1, Addr(A0,D2) ; Set DMA dest addr to user buff ptr + ENDIF + + MoveQ #0, D0 + Move XmitLen(A6), D0 ; Get pkt len (word) + IF SETDEBUG THEN + IF not SETDEBUGFAIL THEN + Tst.b hasNewPSC(A2) + Beq.s @a02 ; go to old PSC patch + Move.l D0, Cnt(A0,D2) ; Set DMA byte count (long) + Bra.s @aaa2 +@a02 + ENDIF +@a2 Move.l D0, Cnt(A0,D2) ; Set DMA byte count (long) + Move.l Cnt(A0,D2), D1 + Cmp.l D0, D1 + IF SETDEBUGFAIL THEN + Beq.s @aa2 + _Debugger + Bra.s @a2 +@aa2 + ELSE + Bne.s @a2 + ENDIF +@aaa2 + ELSE + Move.l D0, Cnt(A0,D2) ; Set DMA byte count (long) + ENDIF + + BTst #0, (A1) ; xmiting a multi/bcast? + MoveA.l LAPMIBStatPtr(A2), A1 + Bne.s @30 + AddQ.l #1, ifOutUcastPkts(A1) ; inc. non-multi/bcast cntr + Bra.s @31 +@30 AddQ.l #1, ifOutNUcastPkts(A1) ; inc. multi/bcast cntr +@31 Add.l D0, ifOutOctets(A1) ; inc. sent octet cntr + + Move #(1< buffer to xmit (InUseTxHead) + Jsr PrimeXmitRS + MoveA.l (SP)+, A1 ; A1-> buffer just xmitted + MoveA.l (SP)+, A0 ; Restore MaceVarPtr + + IF BUFDEBUG THEN + CmpA.l XmitBuff.Next(A1), A1 ; linked to myself? + Bne.s @dok3 + _Debugger ; oooppppsss! +@dok3 + CmpA.l FreeXmtBuff(A0), A1 ; on free list too? + Bne.s @dok4 + _Debugger ; oooppppsss! +@dok4 + Move.l FreeXmtBuff(A0), D1 + Cmp.l InUseTxHead(A0), D1 ; on both? + Bne.s @dok5 + _Debugger ; oooppppsss! +@dok5 + ENDIF + IF COUNTERS THEN + AddQ.l #1, InUseXmitD(A0) + ENDIF + +@inuseempty + Move.l XmtDnRtn(A0), D0 + Beq.s @skip ; no xmit completion rtn + Move.l A0, -(SP) ; Save A0 + Move.l XmtDnParm(A0), -(SP) ; Push user parm + MoveA.l D0, A0 + Jsr (A0) ; Call user xmit completion rtn + AddQ #4, SP ; Strip parms + MoveA.l (SP)+, A0 ; Restore A0 +@skip + IF BUFDEBUG THEN + SubQ.l #1, XmtDnActive(A0) + ENDIF + Rts + + ENDP + EJECT +;___________________________________________________________________________ +; +; MaceRecv - Deferred Task Packet receive routine +; +; Call: +; A1 - our variables +; Received packet(s) in buffers in chain(s) on InUse Queue and, perhaps, +; in buffers in chain(s) on Register Sets. +; +; Return: +; Empty InUse Queue +; +; Destroys: +; +; Calls: +; Calls user's handler to receive packet. +; +; Notes: +; Since MaceRecv runs under DTMgr, more packets can arrive and +; get queued in chains on InUse queue while we're running. So, +; we'll loop using InUseRxHead to dequeue and process received packets. +; Once we've drained all chains from InUse, we check for packets in the +; chain on the active reg set. +; Installed via PSCInterrupt, called via Deferred Task Mgr. +; When the chain is ON the reg set, we compare Out & In, where +; In = Limit - Cnt. When the chain is on InUse, we compare Out & Limit. +;___________________________________________________________________________ + +MaceRecv PROC + WITH MACERegs,MaceVars,PSC_DMA_CHNL,RecvBuff,RxChnDescr + WITH Dot3StatsEntry,LAPMIBStats + + MoveM.l A2-A4/D3-D4,-(SP) ; save non-scratch regs + + Move.l A1, A2 ; A2 -> Mace vars + + IF COUNTERS THEN + AddQ.l #1, MaceRcvCnt(A2) + ENDIF +; +; Check InUse queue for recv chains +; + Move SR,-(SP) ; Save interrupt mask level + OrI #DMALockOut, SR ; Disable DMA ints. +@recvnext + Move.l InUseRxHead(A2), D0 ; recv chain(s) in InUse? + Beq @chksets ; no + MoveA.l D0, A4 + Move.l NextChn(A4), D0 ; Another chain in queue? + Bne.s @1 ; yes + Move.l D0, InUseRxTail(A2) ; Clear tail +@1 Move.l D0, InUseRxHead(A2) ; Make head pt to next entry + Clr.l NextChn(A4) + + Move (SP)+, SR ; Restore SR + + IF BUFDEBUG THEN + Move.l A4, CurrRecv(A2) + ENDIF +; +; Loop until Out == Limit, delivering packets to .ENET +; +@dochain + Move Limit(A4), D0 + Cmp Out(A4), D0 ; are there packets to process? + Beq.s @chaindone ; no + + Bsr GetPkt ; Get pkt at Out and deliver it + + Bra.s @dochain ; check for more pkts + +@chaindone +; +; Queue the now empty recv chain onto head of Free list. First check if either reg set +; needs to be primed since there may have been NO freechains when the DMA interrupt +; handler wanted to prime the reg set. +; + MoveA.l A4, A1 ; A1-> now empty chain descr + + Move SR,-(SP) ; Save interrupt mask level + OrI #DMALockOut, SR ; Disable DMA ints. + + + Move ActRecvSet(A2), D4 ; get offset to active reg set + Move #1, D3 ; init loop cntr + MoveA.l PSCBase(A2), A3 + Lea PSC_MACE_RECV(A3), A3 ; A3-> Recv Channel base address +@chkset Tst.l RxChainSet0(A2,D4) ; Reg Set0/1 need priming? + Bne.s @chk1 ; no + Bsr InitRecv ; Prime it + IF COUNTERS THEN + AddQ.l #1, (DTprimeSet0,A2,D4) + ENDIF + Bra @recvnext ; Go check InUse list +@chk1 + BChg #4, D4 ; Toggle reg sets ; + DBra D3, @chkset + ; Put chain on free list + Move.l FreeRxChain(A2), NextChn(A1) ; Make us pt to current head of free list + Move.l A1, FreeRxChain(A2) ; Make us new head of free list + Bra @recvnext ; Go check InUse list + +; +; We've drained all packets in chains on InUse queue, now check for packets +; in chains still on reg sets. We know ActRecvSet is valid since we just checked +; InUse queue and DMA ints are still masked. ActRecvSet assures us we'll process +; pkts in the correct order; ie. InUse head to tail, then ActRecvSet. +@chksets + Move ActRecvSet(A2), D4 ; get offset to active reg set + MoveA.l RxChainSet0(A2,D4), A4 ; get active chain descr + + MoveA.l PSCBase(A2), A3 + Lea PSC_MACE_RECV(A3), A3 ; A3-> Recv Channel base address + +@domore +; We want to get Limit while ints are off to ensure we calculate "In" with the "real" +; limit and not with the "flush" value of limit. We want to get Cnt while ints are off to +; ensure Cnt value is Cnt for our chain. If ints we're on, we could take an int, reprime +; the reg set with a new chain, and Cnt would no longer refer to our chain. + Move Limit(A4), D1 ; get Limit + Move.l Cnt(A3,D4), D2 ; get current cnt + +; Here, we don't care any more if chain is on or off reg set. We can recv the pkt at Out. +; However, we'll keep ints masked until after we clear DTInstalled. This prevents a race cond. +; where a recv/xmit int could occur between here and @exit. It could happen when we're here +; and there's 1 buffer left in chain (Out = Limit - 1). The int. hnldlr (ChkRecv) could run +; and would clear ints on the set then NOT install us since we're already installed. We'd +; leave but no more ints will happen on the set. If the other set is not primed, we'll never +; get called again. + Sub D2, D1 ; D1 = In = Limit - Cnt + IF BUFDEBUG THEN + Move D1, In(A4) ; save In + ENDIF + Cmp Out(A4), D1 ; Out == In? + Beq.s @exit ; yes, no more packets to recv + + Move (SP), SR ; Restore int mask level + + Bsr.s GetPkt ; Get pkt at Out and deliver it +; +; Verify chain we're processing is still on reg set. If not, its moved to InUse queue. +; + OrI #DMALockOut, SR ; Disable DMA ints. + + Btst #OnOffSet, State(A4) ; Is chain still on reg set? + Beq @recvnext ; no, go drain it from InUse + Bra.s @domore ; yes, go check for more pkts + +@exit Clr.b DTInstalled(A2) ; Indicate Deferred Task NOT Installed + Move #(1< + MoveA.l D0, A0 ; A0-> segment in chain + Lea MaceStat(A0), A1 ; pt to Mace status + MoveA.l LAPMIBStatPtr(A2), A5 ; pt to LAP stats + MoveA.l Dot3StatPtr(A2), A6 ; pt to DOT3 stats +; +; Retrieve status bytes from beginning of buffer. Each status byte is present in +; the high and low bytes of a word. There are 4 status bytes, so there are 8 bytes +; of status. +; + Move (A1)+, D2 ; Get Byte Cnt(7-0) + MoveQ #0, D1 + Move.b D2, D1 + Add.l D1, ifInOctets(A5) + + Move (A1)+, D1 ; Get Status(in bits 7-4) and + ; Byte Cnt(11-8) in bits 3-0 + Move.b D1, D0 + AndI #(1<0 + Beq.s @mpci ; no + AddQ.l #1, RCVCOCnt(A1) + +@mpci BTst #MPCO, D0 ; Missed packet count interrupt? This int. + ; indicates MPC reg. rolled over from 255->0 + Beq.s @cerr ; no + AddQ.l #1, MPCOCnt(A1) + Add.l #256, ifInErrors(A2) + + +@cerr BTst #CERR, D0 ; Collision error interrupt? + Beq.s @babl ; no + AddQ.l #1, dot3StatsSQETestErrors(A3) + AddQ.l #1, ifOutErrors(A2) + +@babl BTst #BABL, D0 ; Babble error interrupt? + IF COUNTERS THEN + Beq.s @chkrcv ; no + AddQ.l #1, dot3StatsFrameTooLongs(A3) + AddQ.l #1, ifOutErrors(A2) + +@chkrcv BTst #RCVINT, D0 ; Recv int? + Beq.s @done ; no, check ints. + AddQ.l #1, RcvInts(A1) + ELSE + Beq.s @done ; no + AddQ.l #1, dot3StatsFrameTooLongs(A3) + AddQ.l #1, ifOutErrors(A2) + ENDIF + +@done MoveM.l (SP)+, A0/A2/A3/D1 + MoveQ #1, D0 ; Indicate int. was serviced + RtS ; Return from MaceInterrupt + + ENDP + EJECT +;___________________________________________________________________________ +; +; PSCInterrupt - Process DMA Interrupt from PSC +; +; Call: +; A1 - our variables +; +; Return: +; D0=1, Indicate Interrupt was serviced +; +; Destroys: +; A2 - our variables +; A3 - Receive or Transmit DMA Channel base address +; D4.b - Register Set offset, 0 or $10 +; +; Calls: +; PrimeRecv - reprime a Recv DMA reg set +; MaceXmitDone - read Xmit status and reprime Xmit DMA regs if needed +; +; RePrime Receive and Transmit Register Sets. Install Deferred Task to +; process Received Packets and Transmit Completions. +;___________________________________________________________________________ + +PSCInterrupt PROC + WITH MACERegs,MaceVars,PSC_DMA_CHNL + + MoveM.l A0/A2-A3/D1-D4, -(SP) ; Save regs + Move.l A1, A2 ; A2 -> our variables + + IF COUNTERS THEN + AddQ.l #1, PSCIntCnt(A2) + ENDIF +; +; Check for packet in Receive DMA Channel +; +; If bus error, go handle it, make sure DT installed, then check for xmit done int. +; Else +; If set's chain is full, reprime set and install DT. Loop back and check the other +; set, ONLY so we can, if needed, disable ints for this set. Note: DT checks +; "active set" after draining InUse. +; Else set's chain is NOT full, disable ints for set, install DT, and leave. +; +ChkRecv + MoveA.l PSCBase(A2), A0 + Move PSC_MACE_RECV_CNTL(A0), D1 + BTst #BERR, D1 ; Bus Error on recv channel? + Beq.s @noberr ; no + Bsr RecvBusErr ; go handle it + Bra.s @rcvberrcont ; go make sure DT installed + +@noberr BTst #CIRQ, D1 ; Interrupt on recv channel? + Beq.s ChkXmitDone ; no, check xmit channel + + Lea PSC_MACE_RECV(A0), A3 ; A3-> Recv Channel base address + Move ActRecvSet(A2), D4 ; D4-> offset to reg set + + IF COUNTERS THEN + AddQ.l #1, (RecvSet0Cnt,A2,D4) ; inc count for set + ENDIF + IF DEBUG THEN + Move CmdStat(A3,D4), D1 ; Get command/status + BTst #IF, D1 ; Recv packet? + Bne.s @ok1 + _Debugger ; no, actrecvset screwed up? +@ok1 + ENDIF + Move #(1<deferred task queue element + MoveA.l JDTInstall, A1 + Jmp (A1) ; install deferred task + ELSE + Move SR, -(SP) + Move #$0300, D0 ; Disable ≤ l3 ints. + _SETINTMASK D0 + Lea MaceRecv, A0 + MoveA.l A2, A1 + Jsr (A0) + Move (SP)+, SR + ENDIF +@donerecv Rts + +@chnfull Bsr PrimeRecv ; All of chain's buffers are full, + ; reprime reg set with new chain + Bsr.s @installDT ; make sure DT installed + Bra.s ChkRecv ; go check other reg set + +; +; Check for Transmit Completion Interrupt +; +ChkXmitDone + MoveA.l PSCBase(A2), A0 + Move PSC_MACE_XMIT_CNTL(A0), D1 + BTst #BERR, D1 ; Bus Error on xmit channel? + Beq.s @noberr ; no + Bsr XmitBusErr ; yes, go handle it + Bra.s @donePSCInt + +@noberr BTst #CIRQ, D1 ; Interrupt on xmit channel? + Beq.s @donePSCInt ; no, leave + + Lea PSC_MACE_XMIT(A0), A3 ; A3-> Xmit Channel base address + Move ActXmitSet(A2), D4 ; get offset to active reg set + + IF COUNTERS THEN + AddQ.l #1, (XmitSet0Cnt,A2,D4) ; inc count for set + ENDIF + IF DEBUG THEN + Move CmdStat(A3,D4), D1 ; Get command/status + BTst #IF, D1 ; Xmit done packet? + Bne.s @ok1 + _Debugger ; no, ActXmitSet screwed up? +@ok1 + ENDIF + Move #(1<proc to move memory FAST +; IPSize EQU * +; +; Return: +; D0 = openErr (-23) or mFulErr (-41) +;___________________________________________________________________________ + +MaceInit PROC EXPORT + +parms RECORD {A6Link} +LocalSize EQU * +A6Link DS.l 2 ; link and return address +initp DS MACEInitParms ; parameters passed to us + ENDR + + IMPORT TranslateAddress, GetMemory, FreeMemory + WITH parms,initp,MACERegs,MaceVars,PSC_DMA_CHNL,PSC_INT_TBL + + Link A6,#LocalSize ; Save A6 + MoveM.l A2-A4/D3-D5,-(SP) ; Save regs + + WITH GetMem + Sub.l #GetMemSz, SP ; room for results + Move.l #MaceVarSz, memsize(SP) ; requested memory size + Move.l #0, memoptions(SP) ; do NOT want memory locked, + ; contiguous, and non-cacheable + Pea MaceVarPtr + Move.l (SP)+, memhndl(SP) + Lea GetMemory, A0 + Jsr (A0) ; get memory + Add.l #GetMemSz, SP ; pop parms + Blt @InitError ; bra if error + ENDWITH + MoveA.l MaceVarPtr, A2 ; get ptr to my vars + + Move.l UnivInfoPtr, A0 ; get ptr to ProductInfo + Add.l ProductInfo.DecoderInfoPtr(A0), A0 ; point to the base address table + Move.l DecoderInfo.PSCAddr(A0), PSCBase(A2) ; Save the PSC base address + + Move.l RecvRtn(A6), RcvRtn(A2) ; save addr of recv rtn + Move.l RecvPrms(A6), RcvParm(A2) ; save parm for recv rtn + + Move.l XmitRtn(A6), XmtDnRtn(A2) ; save addr of xmit compl rtn + Move.l XmitPrms(A6), XmtDnParm(A2) ; save parm for xmit compl rtn + + Move.l MACECfgPtr(A6), A4 + Move.l MACECfg.MACEBase(A4), MACEBase(A2) + Move.l A4, MCfg(A2) ; save ptr to MACE config record + + Move.l Dot3NetStats(A6), Dot3StatPtr(A2) + Move.l LAPMIBNetStats(A6), LAPMIBStatPtr(A2) + + Move.l EnetAddr(A6), OurAddrPtr(A2) ; save ptr to our Ethernet address + + Move.l FastMoveRtn(A6), MemMove(A2) ; save addr of fast mem move rtn + + MoveQ #0, D0 ; initialize some regs + Move.l D0, D2 + Move.l D0, D3 + Move.l D0, D5 + Move MACECfg.XmitBuffs(A4), D2 + Bne.s @10 + Move #DefTxBuffs, D2 ; 0 passed in, set to default +@10 Move MACECfg.RecvBuffs(A4), D3 + Bne.s @11 + Move #DefRxBuffs, D3 ; 0 passed in, set to default +@11 Move MACECfg.RecvChains(A4), D5 + Bne.s @12 + Move #DefChns, D5 ; 0 passed in, set to default +@12 ; force 1 ≤ recv chains ≤ max + CmpI #OneChn, D5 ; 1 recv chain? + Bne.s @chkmax ; no + CmpI #MaxBufpChn, D3 ; too many buffers in our 1 chain? + Bls.s @GetMem ; no + Move #MaxBufpChn, D3 ; reset # of buffers to max allowed + Bra.s @GetMem + +@chkmax CmpI #MaxChns, D5 ; must be ≤ max allowed + Bls.s @cont1 + Move #MaxChns, D5 +@cont1 Move D5, MACECfg.RecvChains(A4) ; set # of chains + + Move D5, D0 ; D0.w=# of chains + Move D3, D5 ; D5.l=# of recv buffers + DivU D0, D5 ; D5.l=# of buffers per chain in low word + Swap D5 ; get remainder in low word + Tst D5 ; was there a remainder? + Beq.s @noremndr ; no + Sub D5, D3 ; adjust # recv buffers down so + ; same # per chain + Clr D5 ; clear remainder +@noremndr Swap D5 ; get back # of buffers per chain + + CmpI #MaxBufpChn, D5 ; too many buffers per chain? + Bls.s @chkmin ; no + Move #MaxBufpChn, D5 ; reset # of buffers to max allowed + Bra.s @cont2 +@chkmin CmpI #MinBufpChn, D5 ; too few buffers per chain? + Bhs.s @Getmem ; no + Move #MinBufpChn, D5 ; reset # of buffers to min allowed + Move #DefChns, MACECfg.RecvChains(A4) ; reset # of chains +@cont2 Move D5, D3 ; D3=# of buffers per chain + Move MACECfg.RecvChains(A4), D1 ; D1=# of chains + MulU D1, D3 ; D3.l=total # of recv buffers + +@GetMem + Move D2, D4 ; D4=# xmit buffers + Move #XmitBuff.TxBuffSz, D0 + MulU D4, D0 ; D0.l=memory for xmit buffers + + Move D3, D4 ; D4=# recv buffers + Move #RecvBuff.RxBuffSz, D1 ; size of a recv buffer + MulU D1, D4 ; D4.l=memory for recv buffers, used later + + Add.l D4, D0 ; D0=memory for recv & xmit buffers + AddI.l #RecvBuff.RxBuffSz, D0 ; add 1 since we must 2K align recv buffs + + WITH GetMem + Sub.l #GetMemSz, SP ; room for results + Move.l D0, memsize(SP) ; requested memory size + Move.l #(1< next buffer address + Move.l A1, Next(A0) ; set link to next buffer + MoveA.l A1, A0 ; point to next buffer +@x1 + DBra D0,@x2 ; do them all + Clr.l Next(A0) ; clear last buffer's next ptr +; +; Get and save physical address of each transmit buffer's packet data area +; This loop depends on all buffers being contiguous. +; + Move.l FreeXmtBuff(A2), A0 ; Get Xmit header pointer + Move.l D2,D1 + SubQ #1,D1 ; adjust loop count +@x3 + Lea Packet(A0), A1 ; Get Packet logical address + MoveM.l A0/D1/D2, -(SP) ; Save used C regs + Move.l #TxBuffSz, -(SP) ; logical size + Move.l A1, -(SP) ; logical address + Lea TranslateAddress, A0 + Jsr (A0) ; get physical address in D0 + MoveA.l (SP)+, A1 ; get back buffer addr + AddQ #4, SP ; trash length + MoveM.l (SP)+, A0/D1/D2 ; restore used C regs + Blt @InitError + Move.l A1, LogBufPtr(A0) ; save logical address + Move.l D0, PhyBufPtr(A0) ; save physical address + Lea TxBuffSz(A0), A0 ; A0-> next buffer address + DBra D1,@x3 ; do them all + ENDWITH +; +; MACE Chip initialization +; + MoveA.l MACEBase(A2), A0 ; A0-> base address of Mace regs + + Bsr ResetMACE ; Reset MACE chip and PSC DMA chnls + + Move.b #(1< Default: + ; Enable Retry, FCS, Auto Padding + Move.b MACECfg.RecvFrmCtl(A4), MACE_RX_FRM_CNTRL(A0) ; Recv Control -> Default: + ; Disable Auto Pad Stripping + ; Set up FIFOs' configuration + Move.b MACECfg.FIFOCfgCtl(A4), MACE_FIFO_CNFG(A0) + Move.b #0, MACE_PLS_CNFG(A0) ; Set up for normal transmit + + Move.b MACE_CHIP_ID_HIGH(A0), D0 + Lsl #8, D0 + Move.b MACE_CHIP_ID_LOW(A0), D0 + Move D0, MACEChipID(A2) + + Move.b #(1< Mace Phy Address Reg + MoveA.l OurAddrPtr(A2), A1 ; A1-> Our node address + Move.b (A1)+, (A0) ; Move addr byte0 to Mace reg + Move.b (A1)+, (A0) ; Move addr byte1 to Mace reg + Move.b (A1)+, (A0) ; Move addr byte2 to Mace reg + Move.b (A1)+, (A0) ; Move addr byte3 to Mace reg + Move.b (A1)+, (A0) ; Move addr byte4 to Mace reg + Move.b (A1), (A0) ; Move addr byte5 to Mace reg + MoveA.l MACEBase(A2), A0 ; Get back base address of Mace regs + + Move.b #(1< Mace Phy Address Reg + MoveQ #7, D0 +@laf Move.b #0, (A1) ; CLEAR all bits in Log Addr Filter + DBra D0, @laf + + Move #0, NxtXmitSet(A2) ; make set0 next reg set to xmit on + Move #0, ActXmitSet(A2) ; make set0 active xmit reg set + Move #0, ActRecvSet(A2) ; make set0 active recv reg set + + IF SETDEBUG THEN +;???? temp code to see if we have post evt5 PSC that has non-sticking register write fix + MoveA.l VIA, A1 + BTst #vSCCWrReq, vDirA(A1) ; new psc: bit(vSCCWrReq) = 0 + ; old psc: bit(vSCCWrReq) = 1 + Seq.b hasNewPSC(A2) +; end temp code + ENDIF + + Bsr InitRecvChl ; Initialize DMA recv channel + + ; Install MACE Recv DMA channel Deferred Task, called by MACE_RECVhndlr + Move.w #dtQType, DTQE+qType(A2) ; Set Deferred Task queue type + Lea MaceRecv, A1 + Move.l A1, DTQE+dtAddr(A2) ; Set address of DT, called by slot int. hndlr. + Move.l A2, DTQE+dtParm(A2) ; Set variable pointer to MACE vars + + ; Install PSC DMA handlers for Mace Recv & Xmit channels + MoveA.l PSCBase(A2), A3 ; Get the PSC base address + WITH ExpandMemRec + MoveA.l ([ExpandMem],emDMADispatchGlobals), A0; A0-> PSC Interrupt table ptr + ENDWITH + Lea PSCInterrupt, A1 + Move.l A1, MACE_RECVhndlr(A0) ; Install DMA recv handler + Move.l A2, MACE_RECVparm(A0) ; MaceVarPtr passed back in A1 + Move.l A1, MACE_XMIThndlr(A0) ; Install DMA xmit done handler + Move.l A2, MACE_XMITparm(A0) ; MaceVarPtr passed back in A1 + Move.b #(1< 6/14/93 kc Roll in Ludwig. +# 3/16/93 chp Added a dependency on SysPrivateEqu.a for Mace.a.o. +# 1/27/93 mal Add MACE ecfg rsrc. +# 11/30/92 SWC Changed TimeEqu.a->Timer.a. +# + +"{RsrcDir}DeclDataMace.rsrc" ƒ "{ObjDir}MaceEnet.a.o" ∂ + "{ObjDir}Mace.a.o" ∂ + "{ObjDir}Loopback.c.o" ∂ + "{IfObjDir}interface.o" + Link {StdLOpts} {StdAlign} -rt decl=1 -o "{Targ}" ∂ + "{ObjDir}MaceEnet.a.o" ∂ + "{ObjDir}Mace.a.o" ∂ + "{ObjDir}Loopback.c.o" ∂ + "{IfObjDir}interface.o" + +"{RsrcDir}MACEecfg.rsrc" ƒ {MaceDir}MACEecfg.r + Rez {StdROpts} -t rsrc -c RSED "{MaceDir}MACEecfg.r" -o "{Targ}" + + +"{ObjDir}Enet61.rsrc" ƒ "{ObjDir}MaceEnet.a.o" ∂ + "{ObjDir}Mace.a.o" ∂ + "{ObjDir}Loopback.c.o" + Link {StdLOpts} {StdAlign} -rt enet=61 -o "{Targ}" ∂ + -sn Main="Cyclone MACE Ethernet Driver" ∂ + -ra "Cyclone MACE Ethernet Driver"=resSysHeap,resPurgeable,resLocked ∂ + "{ObjDir}MaceEnet.a.o" ∂ + "{ObjDir}Mace.a.o" ∂ + "{ObjDir}Loopback.c.o" ∂ + "{IfObjDir}interface.o" + + +"{ObjDir}MaceEnet.a.o" ƒ "{MaceDir}MaceEnet.a" ∂ + "{MaceDir}MaceEqu.a" ∂ + "{MaceDir}VersionMaceEnet.a" ∂ + "{EthernetDir}AtalkMacros.a" ∂ + "{EthernetDir}ENETEqu.a" ∂ + "{EthernetDir}SNMPLAP.a" ∂ + "{AIncludes}GestaltEqu.a" ∂ + "{AIncludes}Slots.a" ∂ + "{AIncludes}SysEqu.a" ∂ + "{AIncludes}SysErr.a" ∂ + "{AIncludes}Timer.a" ∂ + "{AIncludes}Traps.a" ∂ + "{IntAIncludes}HardwarePrivateEqu.a"∂ + "{IntAIncludes}InternalOnlyEqu.a" ∂ + "{IntAIncludes}PSCEqu.a" ∂ + "{IntAIncludes}UniversalEqu.a" + Asm {StdAOpts} -i "{MaceDir}" -i "{EthernetDir}" -o "{Targ}" "{MaceDir}MaceEnet.a" + + +"{ObjDir}Mace.a.o" ƒ "{MaceDir}Mace.a" ∂ + "{MaceDir}MaceEqu.a" ∂ + "{EthernetDir}AtalkMacros.a" ∂ + "{EthernetDir}ENETEqu.a" ∂ + "{EthernetDir}SNMPLAP.a" ∂ + "{AIncludes}GestaltEqu.a" ∂ + "{AIncludes}SysEqu.a" ∂ + "{AIncludes}SysErr.a" ∂ + "{AIncludes}Traps.a" ∂ + "{IntAIncludes}SysPrivateEqu.a" ∂ + "{IntAIncludes}HardwarePrivateEqu.a"∂ + "{IntAIncludes}InternalOnlyEqu.a" ∂ + "{IntAIncludes}PSCEqu.a" ∂ + "{IntAIncludes}UniversalEqu.a" + Asm {StdAOpts} -i "{MaceDir}" -i "{EthernetDir}" -o "{Targ}" "{MaceDir}Mace.a" diff --git a/DeclData/DeclNet/Mace/Mace.make.idump b/DeclData/DeclNet/Mace/Mace.make.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Mace/Mace.make.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Mace/Mace.make.rdump b/DeclData/DeclNet/Mace/Mace.make.rdump new file mode 100644 index 0000000..863f0d7 --- /dev/null +++ b/DeclData/DeclNet/Mace/Mace.make.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0065 6F72 6765 2044" /* ..Monaco.eorge D */ + $"2E20 5769 6C73 6F6E 204A 722E 0D23 0D23" /* . Wilson Jr..#.# */ + $"0943 0006 0004 0027 0005 01E0 023A 0027" /* .C.....'.....:.' */ + $"0005 01E0 023A A833 AE0C 0000 00E2 0000" /* .....:.3........ */ + $"010A 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"0027 0005 01E0 023A 0027 0005 01E0 023A" /* .'.....:.'.....: */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"776C 9186 3FE5 3230 0004 0000 0000 0000" /* wl..?.20........ */ + $"0000 A933 739B A933 739B A6F7 B0C6 0078" /* ...3s..3s......x */ + $"BC36 0000 0006 0003 2553 7570 6572 4D61" /* .6......%SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA4D 6163 65BA 000E" /* .DeclNet.Mace... */ + $"4368 7269 7320 5065 7465 7273 656E 0001" /* Chris Petersen.. */ + $"3200 094D 6163 652E 6D61 6B65 0000 0000" /* 2..Mace.make.... */ + $"0F52 6F6C 6C20 696E 204C 7564 7769 672E" /* .Roll in Ludwig. */ + $"00" /* . */ +}; + diff --git a/DeclData/DeclNet/Mace/MaceEnet.a b/DeclData/DeclNet/Mace/MaceEnet.a new file mode 100644 index 0000000..f935225 --- /dev/null +++ b/DeclData/DeclNet/Mace/MaceEnet.a @@ -0,0 +1,1983 @@ +; +; File: MaceEnet.a +; +; Contains: Ethernet Data Link level driver for builtin MACE Ethernet on Cyclone. +; +; Written by: Mark A. Law ,3-March-92 +; +; Copyright: © 1991-1993 by Apple Computer, Inc. All rights reserved. +; +; This file is used in these builds: Mac32 +; +; Change History (most recent first): +; +; 6/14/93 kc Roll in Ludwig. +; 5/1/93 mal #1082434 Changed GetMem/FreeMem so extra memory is grabbed, then +; some of it deleted, when locking down pages so we don't lock +; memory that doesn't belong to us. Also changed snmp stat +; 'ifType' to indicate we're and Ethernet, not 802.3, link to +; match current Quadra drvrs. +; 3/21/93 mal Added back 'eadr' support. +; <2> 1/27/93 mal Added MACEecfg rsrc support. Changed promiscuous mode support to +; lower main codepath risk. +; 12/4/92 mal Turned off debug code; stopped using time mgr task for xmit +; deferrals; Promiscuous mode changes to EtherRecv(). +; 11/19/92 mal Added Promiscous mode support; check for VM correctly; install +; VBL and TimeMgr rtns before loopback; correct addr size in SNMP +; stats. +; 10/30/92 mal Translate/Get/Free mem error condition improvement and made +; exported; 32BIT clean conditionally asm out; misc globals +; cleanup; misc comment cleanup. +; 10/28/92 SWC Changed the INCLUDEs to a LOAD of StandardEqu.d. +; 10/26/92 mal Updated to ESD's latest SNMP stats equs. +; 10/26/92 mal Updated 2 and added 1 SNMP statistics control calls. +; 10/13/92 mal -changed status that is recv'd in EtherRecv to lw and ignore +; pkts with bad status; -added debug code to get/free mem rtns. +; 9/14/92 mal -fixed SNMP var storage and retrieval +; 8/24/92 PN Take out CycloneboxEVT1 stuff +; 7/25/92 mal Added support so # of recv chains can be changed via 'ebfr'. +; Removed _Debugger statements from LoopBack tests failure path. +; 6/26/92 mal Fixed GetStats so it returns correct stats. +; 6/23/92 mal Added runtime check so we'll always fail the open on PSC1 (EVT1) +; systems. +; 6/22/92 mal New drvr to support PSC2's (EVT2) Ethernet DMA receive model. +; 5/21/92 RB Removed the inclusion of VMCalls.a +; 5/5/92 mal Removed unused global vars. +; 4/30/92 mal Expanded interface between with Mace.a: now pass ptrs to +; TranslateAddress, GetMemory, and Blockmove rtns via MaceInit. +; Replaced XmitDone with rtn called via TimeMgr task. +; 4/28/92 mal Moved Mace specific tasks to Mace.a +; 3/26/92 mal Changed WriteLAF algorithm, now flush MACE and PSC FIFOs and +; drop packet(s) if packets present in MACE FIFO. +; 3/23/92 mal Added Multicast Add/Delete support; Removed TWISTER conditional +; sections; Cleaned up src. +; 3/5/92 mal Now get Ethernet Address from Prom if no 'eadr' resource in +; system file. +; 3/4/92 mal For no free recv buffs case; clear int. in DoRecv and added code +; in EtherRecv to reprime reg sets. +; 3/3/92 mal Made "DEBUG" conditional false. +; 3/3/92 mal Removed debug statements for non-error conditions. +; +; To Do: +; +; Notes: +; -based on Ethernet driver for Eclipse/Spike by Sean Findley, January 1990 +; +; + + PRINT OFF + LOAD 'StandardEqu.d' + INCLUDE 'Slots.a' ; Slot interrupt equates + INCLUDE 'GestaltEqu.a' + INCLUDE 'HardwarePrivateEqu.a' + INCLUDE 'UniversalEqu.a' ; lowmem global records + INCLUDE 'ATalkMacros.a' ; Nifty Macros + +; Conditional compile equates +COUNTERS EQU 0 +BUFDEBUG EQU 0 +BIT24 EQU 0 ; SuperMario always 32-bit +DEBUG EQU 0 +PROM EQU 1 ; Promiscous mode support +PRIMEDEFER EQU 0 ; Use Time Mgr for xmit defferals + + PRINT NOGEN,NOMDIR,ON + INCLUDE 'MaceEqu.a' ; Mace definitions + INCLUDE 'PSCEqu.a' ; Mace definitions + INCLUDE 'ENETEqu.a' ; Driver definitions + INCLUDE 'SNMPLAP.a' ; SNMP definitions + EJECT + +NumTxBuffers EQU 8 ; "optimal" number of xmit buffers +NumRxBuffers EQU 16 ; "optimal" number of recv buffers +NumRxChains EQU 4 ; "optimal" number of recv buffer chains + +OurV RECORD 0 ; our variables +OurDCE DS.l 1 ; Offset to our DCE pointer in variables + IF PROM THEN +PromiscRHA DS.l 1 ; Contains status lw when in promiscuous mode + ; ••• WARNING: do not separate from RHA! + ENDIF +RHA DS.b EHdrSize ; Read Header Area +;___________________________________________________________________________ +; +; The LAP protocol handler table starts here. Format: +; .BYTE InUseFlag1,..., InUseFlagN ; Entry in use flag +; .wORD ProtCode1, ..., ProtCodeN ; Protocol type codes +; .lONG PHAddr1, ..., PHAddrN ; Protocol handler addresses +; .lONG RdQueueHd1, ..., RdQueueHdN ; Read queue heads +;___________________________________________________________________________ +LAPTblSz EQU 16 ; Size of LAP protocol handler table (even) +InUseFlag DS.b LAPTblSz ; Entry in use flag +Protocols DS.w LAPTblSz ; List of active protocols +Handlers DS.l LAPTblSz ; List of handler addresses +RdQueueHd DS.l LAPTblSz ; Read queue heads +LAPTblEnd EQU * ; End of LAP table + +;___________________________________________________________________________ +; +; Multicast address table. Entry format: +; Ethernet address (6 bytes) +; Use count (1 byte). Zero means entry free. +; Unused (1 byte) +;___________________________________________________________________________ + +MTblSz EQU 16 ; Size (in entries) of multicast address table +MEntrySz EQU 8 ; Size of an entry (power of 2) +MUseCount EQU EAddrSz ; Offset to use count in entry + + ALIGN 4 +MultiCTbl DS.b MTblSz*MEntrySz ; A list of valid addresses + ALIGN 4 +XmitWait DS.b 1 ; non-zero = DoWrite waiting for buffers + IF PROM THEN +Promiscflg DS.b 1 ; non-zero = Promiscuous operation mode + ENDIF +deferCtl DS.b 1 ; non-zero = deferring control call + ALIGN 2 +VBLQEL DS.b 14 ; VBL for control call deferrals + IF PRIMEDEFER THEN + ALIGN 4 +DoWriteQEL DS.b tmQSize ; TimeMgr task for DoWrite deferrals + ENDIF + ALIGN 4 + IF BIT24 THEN +AddrMask DS.l 1 ; 32 bit mask for addresses + ENDIF +MemMove DS.l 1 ; trap address of block move + IF COUNTERS THEN +EtherRcvCnt DS.l 1 ; # of times Deferred Recv Task called +XmitPend DS.l 1 ; Cnt of DoWrite calls from TimeMgr task + ENDIF + IF BUFDEBUG THEN +XmtDnActive DS.l 1 + ENDIF +MCfg DS MACECfg ; MACE config data from config rsrc + ALIGN 4 +InfoStart EQU * ; Old "GetInfo" network statistics start +OurAddr DS.b EAddrSz ; Our Ethernet address + DS.l 3 ; fill for compatibility with old getinfo +EtherStats DS NetStats +InfoEnd EQU * ; End of returned info +MultiRecvd DS.l 1 ; # of multicast pkts received +BcastRecvd DS.l 1 ; # of broadcast pkts received +; SNMP vars +LAPStats DS LAPMIBStats ; SNMP MIB stats for any link access protocol +Dt3Entry DS Dot3Entry ; SNMP status info and control vars +Dt3Stats DS Dot3StatsEntry ; SNMP stats for an 802.3 link +OurVarSz EQU * ; End of variables + ENDR + +;_______________________________________ +; +; Other definitions +;_______________________________________ + +AMaxDataSz EQU 768-EHdrSize ; Maximum data size for AppleTalk mode + +INTLockOut EQU $0700 ; SR value to disable ALL interrupts +DMALockOut EQU $0400 ; SR value to disable PSC DMA interrupts + +BlockMoveTrap EQU $A02E ; trap value for _BlockMove + + IF PROM THEN +Promiscuous EQU 1 ; Bit #1 of Open()'s paramblk->ioFlags + ENDIF + EJECT + + EJECT + +ENETDriver MAIN EXPORT + STRING PASCAL + MACHINE MC68020 + + EXPORT TranslateAddress, GetMemory, FreeMemory + IMPORT MACEInit,MACEXmit,MACEAddMulti,MACEDelMulti,MACEHalt,NormAddr + IMPORT LOOPBACKTEST,MACESetProm,MACEXmitProm + WITH MACERegs,OurV,PSC_DMA_CHNL,PSC_INT_TBL + WITH LAPMIBStats,Dot3StatsEntry,Dot3Entry + +; ***************************************** +; * * +; * Start of ENET driver * +; * * +; ***************************************** +ENET +; +; Driver header +; + DC.w $4400 ; Control, Locked, no Goodbye + DC.w 0,0 ; No time, no events + DC.w 0 ; No menu + +; +; Entry points offset table +; + DC.w Open-ENET + DC.w AnRts-ENET + DC.w Control-ENET + DC.w AnRts-ENET + DC.w Close-ENET + + DC.w '.ENET' ; Driver name + ALIGN 2 + + INCLUDE 'VersionMaceEnet.a' + +;________________________________________________________________________ +; +; Open - initialize the ENET driver +; +; Call: +; D0 = 0 +; A0 -> queue element +; A1 -> DCE +; +; Return: +; D0 = 0, no error +; D0 != 0, if error +;________________________________________________________________________ + +OpenRec RECORD {A6Link} +LinkSz EQU * +pbblkptr DS.l 1 ; copy of parameter block ptr +A6Link DS.l 2 ; link and return addr + ENDR +Open + Link A6,#OpenRec.LinkSz ; mark the stack for easy exit + + Move.l A0,OpenRec.pbblkptr(A6) ; Save paramblock ptr for later access + + Move.l #gestaltVMAttr,D0 ; see if VM is running + _Gestalt + Bne.s @noVM ; it is'nt if call failed + Move.l A0,D0 + Btst #gestaltVMPresent,D0 + Beq.s @noVM ; zero result means no VM running + BSet #VMImmuneBit,dCtlFlags+1(A1) ; tell VM to leave our calls alone +@noVM + Lea OurVarPtr,A3 ; A3 -> variable pointer +; +; Allocate our variables +; + Move.l #OurVarSz,D0 ; variables size + _NewPtr ,SYS,CLEAR ; get memory for our variables + Bne OpenError + + Move.l A0,(A3) ; save variable pointer + MoveA.l A0, A2 ; A2 -> our vars + + Move.b MaceEnet,DCtlQueue+1(A1) ; Version number goes here + IF BIT24 THEN + Move.l A1,D0 + _StripAddress + Move.l D0,OurDCE(A2) ; Save our DCE address + ELSE + Move.l A1,OurDCE(A2) ; Save our DCE address + ENDIF + Move.w #BlockMoveTrap,D0 + _GetTrapAddress + Move.l A0,MemMove(A2) ; save trap address in our vars +; +; Look for a MACE configuration resource for this CPU +; + + Move.l #gestaltMachineType,D0 + _Gestalt ; get our machine type + Tst D0 ; any errors? + Bne OpenError ; yes, return with error + Move A0,D3 ; save our machine ID + + SubQ #4,SP ; Make room for handle + Move.l #Configrsrc,-(SP) ; Push resource type + Move D3,-(SP) ; Set machine ID as resource ID + _GetResource ; Get it from system file + Move.l (SP)+,D0 ; D0 = handle to config resource + Bne.S @21 ; Bra if we found it + + SubQ #4,SP ; Make room for handle + Move.l #Configrsrc,-(SP) ; Push resource type + Move D3,-(SP) ; Set machine ID as resource ID + Move #MapTrue,ROMMapInsert ; Look for resource in sys ROM + _GetResource ; Get it from ROM + Move.l (SP)+,D0 ; D0 = handle to config resource + Bne.S @21 + MoveQ #-23,D0 ; return with generic error (D0=-1) + Bra OpenError ; return, config rsrc not found + +@21 MoveA.l D0, A3 ; Save handle to resource + + MoveA.l (A3), A0 ; A0-> config resource + Lea MCfg(A2), A1 ; A1-> space in our vars + Move.l #MACECFG.CfgSize, D0 + _BlockMove ; Copy data from rsrc to our vars + + Move.l A3, -(SP) ; push handle + _ReleaseResource ; We're thru with config resource + + Lea MCfg.EnetAddr(A2), A0 ; A0-> alternate ethernet address + Tst.l (A0) ; Check address + Bne.s @22 + Tst 4(A0) + Beq.s @23 ; Ignore if all zeros +@22 + BTst #0, (A0) ; Make sure it's not a multicast addr + Bne.s @23 ; Ignore it if it is + Move.l (A0)+, OurAddr(A2) ; Move four bytes to our address + Move (A0)+, OurAddr+4(A2) ; Move the last two bytes +@23 +; +; Look for an alternate address resource for this slot +; + SubQ #4,SP ; Make room for handle + Move.l #EAddrRType, -(SP) ; Push resource type + MoveQ #0,D0 ; Clear out D0 + MoveA.l OurDCE(A2),A1 ; A1 -> our DCE + Move.b dCtlSlot(A1),D0 ; D0 = slot + Move D0,-(SP) ; Set slot number as resource ID + _GetResource ; Get it + Move.l (SP)+,D0 ; D0 = handle to resource + Beq.s @25 ; Branch if not there + Move.l D0,A0 ; A0 = handle to resource + Move.l (A0),A0 ; A0 = pointer to resource + BTst #0,(A0) ; Make sure it's not a multicast addr + Bne.s @24 ; Ignore it if it is + Move.l (A0)+,OurAddr(A2) ; Move four bytes to our address + Move (A0)+,OurAddr+4(A2) ; Move the last two bytes +@24 Move.l D0, -(SP) ; push handle + _ReleaseResource ; We're thru with alternate address resource +@25 +; +; Determine our Ethernet Address from Address Prom, if address not provided +; via 'ecfg' or 'eadr' resource +; + Lea OurAddr(A2), A1 ; A1-> storage for address + Tst.l (A1) ; Do we already have an address? + Bne.s @45 ; yes, ignore address prom + Tst 4(A1) + Bne.s @45 ; yes, ignore address prom + + MoveA.l MCfg.EnetPROM(A2), A0 ; Address of Ethernet Address PROM + MoveQ #0, D1 ; Setup to checksum the PROM address + MoveQ #7, D0 ; Do 8 bytes + MoveQ #1, D3 ; Offset to address byte + ; Checksum the addresss PROM +@Xor Move.b (A0,D3.w), D2 ; get byte to XOR + Eor.b D2, D1 + AddI #$10, D3 ; Inc offset to next byte + DBra D0, @Xor ; do them all + CmpI.b #$FF, D1 ; end result should be $FF + Bne OpenError ; return with generic error (D0=-1) + ; Get our Ethernet addresss from the PROM + AddQ #EAddrSz, A1 ; go from last to first + MoveQ #EAddrSz-1, D2 ; Get 6 addr bytes + MoveQ #$51, D3 ; Offset to last address byte + +@35 Move.b (A0,D3.w), D0 ; D0=inverted address + Bsr NormAddr ; Normalize it + Move.b D0, -(A1) ; Store in our vars + SubI #$10, D3 ; Dec offset to previous byte + DBra D2, @35 +@45 + IF BIT24 THEN + MoveQ #-1,D0 + _StripAddress + Move.l D0,AddrMask(A2) ; save cached 32 bit address mask + ENDIF + WITH MACEInitParms + SubA #IPSize, SP ; make room for parms + Pea EtherRecv ; addr of packet reception rtn + Move.l (SP)+, RecvRtn(SP) + Move.l A2, RecvPrms(SP) + IF PRIMEDEFER THEN + Move.l #0, A0 ; no xmit completion rtn + ELSE + Lea XmitBuffAvail, A0 ; xmit completion rtn + ENDIF + Move.l A0, XmitRtn(SP) + Move.l A2, XmitPrms(SP) + Pea MCfg(A2) + Move.l (SP)+, MACECfgPtr(SP) ; ptr to MACE config record + Pea Dt3Stats(A2) + Move.l (SP)+, Dot3NetStats(SP) ; where to store 802.3 stats + Pea LAPStats(A2) + Move.l (SP)+, LAPMIBNetStats(SP) ; where to store LAP MIB stats + Pea OurAddr(A2) + Move.l (SP)+, EnetAddr(SP) ; ptr to our Ethernet address + Move.l MemMove(A2), FastMoveRtn(SP) ; addr of fast move memory rtn + + Bsr MACEInit + Bne OpenError + + AddA #IPSize, SP ; Strip parms + ENDWITH + + Lea VBLQEL(A2),A0 + Move #vType,vblType(A0) + Pea ControlDefer + Move.l (SP)+,vblAddr(A0) + Move #32767,vblCount(A0) ; setup control call deferral timer + _VInstall + + IF PRIMEDEFER THEN + Lea DoWriteQEL(A2),A0 + Move #0, tmCount(A0) + Pea XmitBuffAvail + Move.l (SP)+, tmAddr(A0) + _InsTime ; setup xmit buffer full deferral + ENDIF +; +; Perform 3 MACE loopback tests, if any fails, return an open error +; + Move.l #MaceEnetLongStrEnd-MaceEnetLongStr-1, -(SP) ; pass size of loopback + ; data, minus 1 since pascal string + Pea MaceEnetLongStr+1 ; pass ptr to loopback data + Pea OurAddr(A2) ; pass ptr to our address + MoveA.l OurDCE(A2),A1 ; get ptr to DCE + Move dCtlRefNum(A1),D0 + Move.l D0,-(SP) ; pass our refnum for ctl calls + + MoveA.l MCfg.MACEBase(A2),A3 ; MACE base address + + ; Perform Internal, no MENDEC, Lpbk + ; Note: network packet reception disabled + Move.b #INTLPB, MACE_USER_TEST_REG(A3) ; set user test reg + Bsr LOOPBACKTEST ; D0 ≠ 0 if passed + Beq LoopError ; failed + + ; Perform Internal, with MENDEC, Lpbk + ; Note: network packet reception disabled + Move.b #MENDECLPB, MACE_USER_TEST_REG(A3) ; set user test reg + Bsr LOOPBACKTEST ; D0 ≠ 0 if passed + Beq LoopError ; failed + + Move.b #EXTLPB, MACE_USER_TEST_REG(A3) ; perform external loopback + Bsr LOOPBACKTEST ; D0 ≠ 0 if passed + Beq LoopError ; failed + + Move.b #NOLPB, MACE_USER_TEST_REG(A3) ; disable loopback + + Bsr.s InitSNMP + IF PROM THEN +; +; Check if we're opened in promiscuous mode +; + Move.l OpenRec.pbblkptr(A6), A0 ; Restore paramblock ptr + BTst.b #Promiscuous, ioFlags+1(A0) ; Are we being opened in Promiscuous mode? + Beq.s @notprm + ST Promiscflg(A2) ; Yes, indicate we're in promiscuous mode + Pea EtherRecvProm + Bsr MACESetProm ; turn on promiscuous in hw drvr + AddQ #4, SP ; clean up parms +@notprm + ENDIF + MoveQ #noErr,D0 ; Indicate no error + Unlk A6 + Rts ; And return + +; +; Loopback test error - 1 of 3 loopback tests failed +; +LoopError + AddQ #8,SP ; strip loopback test parms + Bsr Close ; shut down MACE + MoveQ #-1,D0 + Bra.s OpenErrDone ; return with open error +; +; Open error - clear out variable pointer for next try +; +OpenError + Move.w D0,D3 ; Save error code + + Lea OurVarPtr, A3 + Tst.l (A3) ; Our variable pointer + Beq.s @56 ; Mem not allocated + MoveA.l (A3), A0 + _DisposPtr ; Free it up + Clr.l (A3) ; Clear it out +@56 + Move.w D3,D0 +OpenErrDone + CmpI.w #-1,D0 ; Translate generic error + Bne.s @60 + MoveQ #openErr,D0 +@60 + Tst.w D0 + Unlk A6 + Rts ; Return with error + + Align 2 +; Strings used when building LAPStats.ifdescr string +RevStrStart Equ * +RevStr DC.B '. Hardware Revision: ' +RevStrEnd Equ * +RevStrLen Equ RevStrEnd-(RevStrStart+1) ; str length, minus length byte + Align 2 +;________________________________________________________________________ +; +; Initialize SNMP statistic arrays +; +; Call: A2 - globals +; +; Return: none +; +; Destroys: A0,A1,D0,D3 +;________________________________________________________________________ + +InitSNMP + +; Initialize LAPStats + ; Copy Pascal String MaceEnetLongStr + Lea LAPStats.ifDescr(A2), A1 ; A1 -> ifDescr + Lea MaceEnetLongStr, A0 ; A0 -> where to move from + MoveQ #0, D3 ; Init for BlockMove + Move.b (A0), D3 ; D0.B = strlen of MaceEnetLongStr + Cmp #255, D3 ; is str be greater than 255? + Bls @doit ; no + Move #255, D3 ; yes, move what we can +@doit AddQ #1, D3 ; move len byte too + Move.l D3, D0 + _BlockMove ; Move it + Add.l D3, A1 ; A1 -> new end of ifDescr + + Add.l #RevStrLen, D3 ; ifDescr + RevStr + Cmp #255, D3 ; would new str be greater than 255? + Bgt.s @cont ; yes, done with ifDescr + + ; get MACE Chip ID and convert to ascii + Lea RevStrEnd, A0 + MoveA.l MCfg.MACEBase(A2), A3 ; MACE base address + MoveQ #0, D0 + Move.b MACE_CHIP_ID_HIGH(A3), D0 ; get high byte MACE Chip ID + Ror.l #4, D0 ; get high nibble + Add.b #$30, D0 ; convert to ascii + Move.b D0, -4(A0) ; save it in RevStr + Clr.b D0 + Rol.l #4, D0 ; get low nibble + Add.b #$30, D0 ; convert to ascii + Move.b D0, -3(A0) ; save it in RevStr + Move.b MACE_CHIP_ID_LOW(A3), D0 ; get low byte MACE Chip ID + Ror.l #4, D0 ; get high nibble + Add.b #$30, D0 ; convert to ascii + Move.b D0, -2(A0) ; save it in RevStr + Clr.b D0 + Rol.l #4, D0 ; get low nibble + Add.b #$30, D0 ; convert to ascii + Move.b D0, -1(A0) ; save it in RevStr + + ; Append RevStr, minus len byte, to ifDescr + Lea RevStrStart+1, A0 ; A0 -> where to move from, will skip length byte + ; A1 -> current end of ifDescr + Move.l #RevStrLen, D0 ; D0.l = strlen of RevStr + _BlockMove ; Move it + + Lea LAPStats.ifDescr(A2), A1 ; A1 -> ifDescr + Add.b #RevStrLen, (A1) ; Set final string length +@cont + + Move.l #SNMPVersion, LAPStats.ifVersion(A2) ; Set version to 1.0.0 + Move.l #ethernet_csmacd, LAPStats.ifType(A2) ; indicate we're an Ethernet link + Move.l #EMaxDataSz, LAPStats.ifMaxMTU(A2) + Move.l #ESpeed, LAPStats.ifSpeed(A2) + + Move.b #EAddrSz, LAPStats.ifPhysAddress(A2) ; set len of ifPhyAddr to #6 + Move.l OurAddr(A2), LAPStats.ifPhysAddress+1(A2) ; copy first 4 bytes of address + Move OurAddr+4(A2), LAPStats.ifPhysAddress+5(A2) ; copy last 2 bytes of address + Move.l #ifStatusUp, LAPStats.ifAdminStatus(A2) + Move.l #ifStatusUp, LAPStats.ifOperStatus(A2) + Move.l Ticks, LAPStats.ifLastChange(A2) + +; Initialize Dt3Stats + + Move.l #SNMPVersion, Dt3Stats.dot3StatsVersion(A2) ; Set version to 1.0.0 + Move.l #0, Dt3Stats.dot3StatsIndex(A2) ; Set index to 0 + +; Initialize Dt3Entry + + Move.l #SNMPVersion, Dt3Entry.dot3Version(A2) ; Set version = 1.0.0 + Move.l #$0, Dt3Entry.dot3Index(A2) + Move.l #2, Dt3Entry.dot3InitializeMac(A2) + Move.l #1, Dt3Entry.dot3SubLayerStatus(A2) + Move.l #1, Dt3Entry.dot3MulticastReceiveStatus(A2) + Move.l #1, Dt3Entry.dot3TxEnabled(A2) + Move.l #0, Dt3Entry.dot3TestTdrValue(A2) + + Rts + +;________________________________________________________________________ +; +; Translate Logical to Physical Address Routine +; +; Call: +; 8(A6).l -> logical address +; 12(A6).l -> logical size +; +; Return: +; D0.w < 0 -> ERROR +; D0.l = physical address +; CC's are set +;________________________________________________________________________ + +; Ptr TranslateAddress(laddr,lsize) ; translate logical to physical addrs +MemBlk RECORD 0 +address DS.l 1 +count DS.l 1 + ENDR + +TraAdd RECORD {A6Link} +LinkSz EQU * +logical DS MemBlk +physical DS MemBlk +A6Link DS.l 2 ; link and return addr +laddr DS.l 1 ; logical address +lsize DS.l 1 ; logical size + ENDR + +TranslateAddress + + WITH TraAdd + Link A6,#LinkSz + Move.l laddr(A6),logical.address(A6) + Move.l lsize(A6),logical.count(A6) + Lea logical(A6),A0 ; A0->translation table + Lea 1,A1 ; A1=count to translate + MoveQ #5,D0 ; GetPhysical + + _MemoryDispatch + IF BUFDEBUG THEN + Beq.s @cont ; success + _Debugger ; failure ?!? +@cont + ELSE + Blt.s @exit ; error, exit + ENDIF + + Move.l physical.Address(A6),D0 ; return lowest physical address +@exit Unlk A6 + Rts + + ENDWITH + +;___________________________________________________________________________ +; +; GetMemory - Get mem and then, optionally, make it contiguous & locked & +; non-cacheable +; +; Call: +; 8(A6).l -> mem size requested +; 12(A6).l -> mem options requested +; 16(A6).l -> address of storage for memory mgr block ptr (a handle) +; 20(A6).l -> address of storage for aligned memory region ptr (a handle) +; 24(A6).l -> address of storage for aligned memory region size (a ptr) +; +; Return: +; (16(A6)).l -> memory mgr block ptr +; (20(A6)).l -> aligned block of memory ptr +; (24(A6)).l -> aligned block of memory size +; D0.w < 0 -> ERROR, couldn't get mem or couldn't lockmemcontig it +; CC's are set +;___________________________________________________________________________ + +GetMemPs RECORD {A6Link} +LinkSz EQU * +A6Link DS.l 2 ; link and return addr +GMparms DS GetMem ; passed in parms + ENDR + +kDefaultPageSize EQU $2000 ; default page size = 32k (same as Gestalt's) + +GetMemory + WITH GetMemPs,GMparms + Link A6,#LinkSz + Movem.l A0-A1/D1-D4, -(SP) ; save registers + + Move.l memsize(A6), D2 ; D2 = requested memory size + Move.l memoptions(A6), D1 ; D1 = requested memory options + ; want mem locked, contiguous, or non-cacheable? + AndI.l #(1< new memory block +; A1 = scratch register +; D2 = memory block size +; D3 = Logical Page Size +; D4 = scratch register + + Move.l A0, D1 ; D1 = address of new memory block to be aligned + Move.l D3, D4 ; D4 = Page Size + SubQ.l #1, D4 ; D4 = (Page Size - 1) + Add.l D4, D1 ; D1 = starting address + (Page Size - 1) + EorI.l #$FFFFFFFF, D4 ; Compute mask + And.l D4, D1 ; mask out lower bits to get page boundary + Move.l D1, ([memhndla,A6]) ; save aligned ptr + + MoveA.l D1, A0 ; A0 -> ptr to aligned buffer + Move.l memsize(A6), D1 ; D1 = req. buffer len + Move.l D3, D4 ; D4 = Page Size + SubQ.l #1, D4 ; D4 = Page Size - 1 + Add.l D4, D1 ; add to req buffer len + EorI.l #$FFFFFFFF, D4 ; Compute mask + And.l D4, D1 ; mask out lower bits to get page boundary + Move.l D1, ([memhndlasz,A6]) ; save aligned memory size + + MoveA.l D1, A1 ; A1 -> length of buffer to Lock, A0 -> start address to Lock + MoveQ #4, D0 ; LockMemoryContiguous + _MemoryDispatch + Beq.s @donelock ; if no errors, then branch +; +; LockMemoryContiguous failed, so try to get rid of the memory block and leave with error +; + MoveA.l ([memhndl,A6]), A0 ; A0 -> memory block allocated + Move D0, -(SP) ; save err code + _DisposPtr ; failure, get rid of memory block + Move.l #0, ([memhndl,A6]) ; zero out addr + Move.l #0, ([memhndla,A6]) ; zero out addr + Move.l #0, ([memhndlasz,A6]) ; zero out size + Move (SP)+, D0 ; restore err code + Bra.s @exit ; return err + +@donelock + MoveA.l ([memhndl,A6]), A0 ; A0 -> memory block + Move.l D2, D0 ; D0 = saved memory block size + Add.l A0, D2 ; D2 = addr of top of memory blk + Add.l ([memhndla,A6]), D1 ; D1 = addr of top of aligned mem region + Sub.l D1, D2 ; get unused space at top of mmgr blk + Sub.l D2, D0 ; get new mmgr blk size + _SetPtrSize ; decrease mmgr blk size + +@done MoveQ #0, D0 ; set no error +@exit Movem.L (SP)+, A0-A1/D1-D4 ; restore registers + Unlk A6 + Rts + ENDWITH + + EJECT +;___________________________________________________________________________ +; +; FreeMemory - Free mem and then, optionally, UN-make it contiguous & locked & +; non-cacheable +; +; Call: +; 8(A6).l -> memory options +; 12(A6).l -> memory mgr block ptr to free +; 16(A6).l -> aligned memory region ptr to unlock +; 20(A6).l -> size of aligned memory region +; +; Return: +; D0 = noErr +; CC's are set +;___________________________________________________________________________ + +FreeMemPs RECORD {A6Link} +LinkSz EQU * +A6Link DS.l 2 ; link and return addr +FMparms DS FreeMem ; passed in parms + ENDR + +FreeMemory + WITH FreeMemPs,FMparms + Link A6,#LinkSz + + Move.l memoptions(A6), D1 ; get mem options + ; was mem locked,contiguous,or non-cacheable? + AndI.l #(1< I/O queue element +; A1 -> device control entry +;________________________________________________________________________ + +ControlDefer ; task to complete a deferred control call + Move.w #32767,vblCount(A0) ; next task is a long time maybe + _StackSpace ; D0 = avail. stack space + Tst.l D0 + Bmi.s @defer ; defer if negative space + CmpI.l #512,D0 ; is there a little room? + Bhs.s @doControl ; yes +@defer + Move.w #1,VBLCount(A0) ; restart fast timer +@exit + Rts ; and get out +@doControl + Lea -VBLQEL(A0),A2 ; A2->our vars + BClr #0,deferCtl(A2) + Beq.s @exit ; return to VBL if not really deferring + + MoveA.l OurDCE(A2),A1 ; A1->our DCE + MoveA.l dCtlQHead(A1),A0 ; A0->param block in use + Bra.s doControl +Control + Move.w ioTrap(A0),D0 ; get trap word that called us + + BTst #asyncTrpBit,D0 ; is this a synchronous call? + Beq.s doControl ; yes, bypass stack check + + _StackSpace ; D0 = avail. stack space + Tst.l D0 + Bmi.s @defer ; defer if negative space + CmpI.l #512,D0 ; is there a little room? + Bhs.s doControl ; yes +@defer + MoveA.l OurVarPtr,A2 ; A2->our vars + BSet #0,deferCtl(A2) ; indicate we are deferring + Move.w #1,vblCount+VBLQEL(A2) ; set next vbl to tick fast +CRts + MoveQ #noErr,D0 ; good return for now + Rts ; get out and get stack back +doControl + Move.l OurVarPtr,A2 ; A2 -> our variables + Move.w CSCode(A0),D2 ; Pickup control code + SubQ #KillCode,D2 ; Check for OS kill I/O call + Beq.s CRts ; return if so + + MoveQ #ControlErr,D0 ; Assume a control error + Move.l OurVarPtr,A2 ; A2 -> our variables + Sub #FirstENET-KillCode,D2 ; Subtract off lowest command + Blt ENETDone ; Return error if too low + Cmp #LastENET-FirstENET,D2 ; Make sure not too high + Bgt ENETDone ; Return error if too high + Move CSParam(A0),D1 ; D1 = 1st parameter word + Move.l CSParam+2(A0),D3 ; D3 = 1st parameter longword +; +; Pick up routine address for this command and jump to routine +; + Move.w (ControlTable,D2.w*2),D2 ; get offset of routine + Jmp (ControlTable,D2.w) ; go do the call + +;_________________________________________________________________________ +; +; Control dispatch table - must be in the same order as the ENET commands. +; Specifies offsets to the command-handling routines. +;_________________________________________________________________________ + +ControlTable + DC.w LapGetDot3Entry-ControlTable ; 238 + DC.w ENETDONE-ControlTable ; 239 LapSetDot3Entry + DC.w LapDot3Stats-ControlTable ; 240 + DC.w ENETDONE-ControlTable ; 241 LapDot3CollStats + DC.w LapGetLinkStatus-ControlTable ; 242 + DC.w ENETOK-ControlTable ; 243 CloseSAP + DC.w ENETOK-ControlTable ; 244 OpenSAP + DC.w DoDelMulti-ControlTable ; 245 + DC.w DoAddMulti-ControlTable ; 246 + DC.w DoAttachPH-ControlTable ; 247 + DC.w DoDetachPH-ControlTable ; 248 + DC.w DoWrite-ControlTable ; 249 + DC.w DoRead-ControlTable ; 250 + DC.w DoRdCancel-ControlTable ; 251 + DC.w DoGetInfo-ControlTable ; 252 + DC.w ENETOK-ControlTable ; 253 DoSetGeneral + +;___________________________________________________________________________ +; +; LapGetDot3Entry - Get Dt3Entry +; +; Call: +; A0 -> queue element +; A2 -> our variables +; D3 = Link Stats Pointer +; +; Return: +; D0 = noErr +; EBuffSize(A0) = bytes returned +;___________________________________________________________________________ + +LapGetDot3Entry + Move.l #0, D0 ; Clear out D0 + Move EBuffSize(A0), D0 ; D0 = # of bytes to move + Cmp #Dot3EntrySz, D0 ; Asking for more than we have? + Bls.s @OKsize ; no + Move #Dot3EntrySz, D0 ; yes, just return what we have +@OKsize + Move D0, EDataSize(A0) ; Return eDataSize + Move.l D3, A1 ; A1 -> user's Dot3Entry buffer + LEA Dt3Entry(A2), A0 + _BlockMove + + Bra ENETOK + +;___________________________________________________________________________ +; +; LapGetLinkStatus - Return LAPMIBStats record info +; +; Call: +; A2 -> our variables +; D3 = Link Stats Pointer +; +; Return: +; D0 = noErr +; EBuffSize(A0) = bytes returned +;___________________________________________________________________________ + +LapGetLinkStatus + Move.l MultiRecvd(A2), D0 + Add.l BcastRecvd(A2), D0 + Move.l D0, LAPStats.ifInNUcastPkts(A2) ; update non-unicast cnt + + Move.l #0, D0 ; Clear out D0 + Move EBuffSize(A0), D0 ; D0 = # of bytes to move + Cmp #LAPMIBStatsSz, D0 ; Asking for more than we have? + Bls.s @OKsize ; no + Move #LAPMIBStatsSz, D0 ; yes, just return what we have +@OKsize + Move D0, EDataSize(A0) ; Return eDataSize + MoveA.l D3, A1 ; A1 -> user's LAPMIBStats buffer + Lea LAPStats(A2), A0 + _BlockMove + + Bra ENETOK + +;___________________________________________________________________________ +; +; LapDot3Stats - return Dot3Stats record info +; +; Call: +; A2 -> our variables +; D3 = 802.3 Stats Pointer +; +; Return: +; D0 = noErr +; EBuffSize(A0) = bytes returned +;___________________________________________________________________________ + +LapDot3Stats + Move.l #0, D0 ; Clear out D0 + Move EBuffSize(A0), D0 ; D0 = # of bytes to move + Cmp #Dot3StatsEntrySz, D0 ; Asking for more than we have? + Bls.s @OKsize ; no + Move #Dot3StatsEntrySz, D0 ; yes, just return what we have +@OKsize + Move D0, EDataSize(A0) ; Return eDataSize + MoveA.l D3, A1 ; A1 -> user's Dot3Stats buffer + Lea Dt3Stats(A2), A0 + _BlockMove + + Bra ENETOK + +;___________________________________________________________________________ +; +; DoAddMulti - add a multicast address to the list +; +; Call: +; A2 -> our variables +; D1 = first two bytes of address +; D3 = last four bytes of address +; +; Return: +; D0 = error code +; +; Finds a free entry in the Multicast Table, stores the multicast address, +; and increments the use count. Calls Mace rtn to update Mace Logical +; Address Filter (LAF). +;___________________________________________________________________________ + +DoAddMulti + MoveQ #eMultiErr,D0 ; Assume invalid address or table full + BTst #8,D1 ; Make sure multicast bit is set + Beq ENETDone ; Return error if invalid multicast address + Bsr FindMEntry ; D2 = entry number for this address + Bpl.s @40 ; Branch if found it +; +; Look for the first free one +; + MoveQ #MTblSz-1,D2 ; D2 = no. of entries in multicast table +@30 Tst.b (MultiCTbl+MUseCount,A2,D2*MEntrySz) + ; This one free? + DBeq D2,@30 ; Loop until checked them all or got one +@35 Bne ENETDone ; Error if none free + +; +; Set in table, then compute and set hash bit in Logical Address Filter (LAF) +; +@40 Move.l D3,(MultiCTbl+2,A2,D2*MEntrySz) + ; Set second part of address + Move D1,(MultiCTbl,A2,D2*MEntrySz) + ; Set first part of address + AddQ.b #1,(MultiCTbl+MUseCount,A2,D2*MEntrySz) + + Bsr.l MACEAddMulti ; Let Mace update LAF + + Bra ENETOK + +;___________________________________________________________________________ +; +; DoDelMulti - delete a multicast address from the list +; +; Call: +; A2 -> our variables +; D1 = first two bytes of address +; D3 = last four bytes of address +; +; Return: +; D0 = error code +; +; Finds the multicast address in the Multicast Table and decrements the use +; count. Calls Mace rtn to update Mace Logical Address Filter (LAF). +;___________________________________________________________________________ + +DoDelMulti MoveQ #eMultiErr,D0 ; Assume address not found + Bsr.s FindMEntry ; D2 = entry number in table + Bmi ENETDone ; Return error if not found + SubQ.b #1,(MultiCTbl+MUseCount,A2,D2*MEntrySz) ; Decrement use count + + Bsr.l MACEDelMulti ; Let Mace update LAF + + Bra ENETOK + +; +; FindMEntry - find this address's entry in the multicast table +; +; Call: +; D1 = high two bytes of address +; D3 = low four bytes of address +; A2 -> our variables +; +; Return: +; D2 = entry number within table (minus if not found). CCR set. +; + +FindMEntry MoveQ #MTblSz-1,D2 ; D2 = no. of entries in multicast table +@10 Tst.b (MultiCTbl+MUseCount,A2,D2*MEntrySz) + ; Is this entry in use? + Beq.s @20 ; Branch if not + Cmp (MultiCTbl,A2,D2*MEntrySz),D1 + ; This it? + Bne.s @20 ; Branch if not + Cmp.l (MultiCTbl+2,A2,D2*MEntrySz),D3 + ; Is it? + Beq.s @30 ; Branch if got it +@20 DBra D2,@10 ; Loop until checked them all +@30 Tst D2 ; Set CCR + Rts ; And return + +;___________________________________________________________________________ +; +; DoAttachPH - attach protocol handler control call +; +; Call: +; A2 -> our variables +; D3.l = address of protocol handler's packet-receive code or zero +; D1.w = protocol type code +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoAttachPH + IF BIT24 THEN + And.l AddrMask(A2),D3 ; 32 bit clean + ENDIF + MoveQ #LAPProtErr,D0 ; Assume an invalid protocol error + + IF PROM THEN + Tst.B Promiscflg(A2) ; Are we in Promiscuous mode? + Beq.S @10 ; No, Note: not set until pass lpbk test + Tst.w D1 + Bne.s ENETDone ; Force attach to ONLY prot type 0 +@10 + ENDIF +; +; Read down the active protocol table, searching for a match +; + Bsr.s GetProt ; See if it's there + Bpl.s ENETDone ; Return error if protocol already active +; +; Now scan for the first free one . . . +; + MoveQ #LAPTblSz-1,D2 ; Index into active protocols list +@20 Tst.b InUseFlag(A2,D2) ; Check this entry + DBeq D2,@20 ; Loop until get one or end + Bne.s ENETDone ; Error if none + Move.l D3,(Handlers,A2,D2*4) ; Fill Handlers in first (in case of interrupt) + Clr.l (RdQueueHd,A2,D2*4) ; Clear out read queue head + Move D1,Protocols(A2,D2*2) + ; Fill protocol type in + ST InUseFlag(A2,D2) ; Indicate in use +ENETOK Clr D0 ; Indicate no error +ENETDone + Move.l OurDCE(A2),A1 ; Make sure A1 has DCE address + MoveA.l JIODone,A0 + Jmp (A0) ; all done now + +; +; Lookup D1 in the protocol table. Return D2 = index to protocol (negative = error). +; +GetProt MoveQ #LAPTblSz-1,D2 ; Index into active protocols list +@10 Tst.b InUseFlag(A2,D2) ; In use? + Beq.s @20 ; Branch if not + Cmp Protocols(A2,D2*2),D1 ; Match? + Beq.s @30 ; Branch if so +@20 DBra D2,@10 ; Keep going until got one +@30 Tst D2 ; Set CCR to D2 + Rts ; Return (BPL for match) +;___________________________________________________________________________ +; +; DoDetachPH - detach protocol handler control call +; +; Call: +; A2 -> our variables +; D1.w = protocol type code +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoDetachPH + MoveQ #LAPProtErr,D0 ; Assume no such protocol active + + IF PROM THEN + Tst.B Promiscflg(A2) ; Are we in Promiscuous mode? + Beq.S @5 ; No, Note: not set until pass lpbk test + Tst.w D1 + Bne.s ENETDone ; Force deattach to ONLY prot type 0 +@5 + ENDIF + Bsr.s GetProt ; D2 = index to protocol + Bmi.s ENETDone ; Return error if at end of table + Clr.b InUseFlag(A2,D2) ; Indicate entry free + Tst.l (Handlers,A2,D2*4) ; Default handler? + Bne.s @10 ; All done if not + Bsr.s AbortAll ; Abort all active reads +@10 Bra.s ENETOK ; Complete this call + + +; +; AbortAll - abort all active read requests. +; +; Call: +; A2 -> our variables +; D2 = flag offset into protocol table +; Uses D1,A0 +; +; Assumes InUseFlag(A2,D2) cleared out already so no interrupts +; + +AbortAll Move.l (RdQueueHd,A2,D2*4),D1 ; D1 -> first read, if any + Beq.s @10 ; Branch if none + Move.l D1,A0 ; A0 -> queue element + Move.l (A0),(RdQueueHd,A2,D2*4) ; Remove from queue + Move #reqAborted,D0 ; Set error code + Bsr CompleteReq ; Return error + Bra.s AbortAll ; And loop + +@10 Rts + +;___________________________________________________________________________ +; +; DoWrite - write out a packet on Ethernet +; +; Called: +; A2 -> our variables +; D3 = WDS pointer +; +; Return: +; D0 = error code; nobuff => chip drvr out of xmit buffers +; eLenErr => sum of data in WDS > max. pkt size +; noErr => chip drvr gave pkt to chip or put pkt +; in xmit queue for transmission +; +; Notes: Depends on MACEXmit to check maximum WDS length +; +;___________________________________________________________________________ + +DoWrite + IF PROM THEN + Tst.b Promiscflg(A2) ; Are we in promiscuous mode? + Bne.s WritePromisc ; yes, only do promiscuous writes + ENDIF + MoveQ #eLenErr, D0 ; Assume length error + Clr.b XmitWait(A2) ; Clear waiting flag + Move.l D3,A0 ; A0 -> WDS + Cmp #EHdrSize,(A0) ; First entry must have whole header + Blo ENETDone ; Error if not + + Move.l 2(A0),A0 ; A0 -> first WDS entry + Move.l OurAddr(A2),ESrcAddr(A0) ; Set our address in it + Move OurAddr+4(A2),ESrcAddr+4(A0) + + Move.l D3, -(SP) ; Push WDS ptr + Bsr MACEXmit ; send the packet + AddQ #4, SP ; Strip parms + Tst.l D0 ; Error? + Bne.s @xmitfail ; yes, check it + Bra ENETDone ; no, complete write req. w/no error + +@xmitfail Cmp.l #nobuff, D0 ; temporarily out of xmit buffs? + IF BUFDEBUG THEN + Bne.s @chklenerr ; no, it must be a len err; lets chk + ELSE + Bne ENETDone ; no, its a len err; return err + ENDIF + ST XmitWait(A2) ; yes, set waiting flag + IF PRIMEDEFER THEN + Lea DoWriteQEL(A2), A0 ; A0-> TimeMgr task element + Move.l #-200, D0 ; delay 200 microseconds + _PrimeTime ; install task to try again later + ENDIF + MoveQ #noErr,D0 + Rts ; Return, don't complete write yet + + IF BUFDEBUG THEN +@chklenerr Cmp.l #eLenErr, D0 ; WDS length error? + Beq.s @ok ; yes + _Debugger ; no, what the heck? +@ok Bra ENETDone ; complete write req. w/error + ENDIF + + IF PROM THEN + +;___________________________________________________________________________ +; +; WritePromisc - write out a packet on Ethernet when DIRECTLY from user buffer +; •••• user buffer MUST BE locked, contiguous, non-cached +; •••• user MUST fully specify Ethernet Header +; •••• FCS generation controlled via Xmit Frame Cntrl register +; •••• which is changeable via 'ecfg' rsrc +; +; Called: +; A2 -> our variables +; D3 = SINGLE entry WDS ptr +; +; Return: +; noErr +; +; Notes: +; +;___________________________________________________________________________ + +WritePromisc + Move.l D3, A0 ; user WDS ptr + Move (A0), -(SP) ; Push user buffer len + Move.l 4(A0), -(SP) ; Push user buffer ptr + Bsr MACEXmitProm ; send the packet + AddQ #6, SP ; Strip parms + Bra ENETOK ; complete write req. w/no error + + ENDIF + +;___________________________________________________________________________ +; +; XmitBuffAvail - IF PRIMEDEFER, transmit deferral routine +; ELSE, xmit completion routine +; +; Call: +; IF PRIMEDEFER +; A1 - time manager queue element +; +; Return: +; no return value/status +; +; Notes: called via time manager after DoWrite gets no buff available error +; from MACEXmit call. +;___________________________________________________________________________ +TxPrm RECORD 4 +TxParm DS.l 1 ; my xmitdone parm +TxPrmSz EQU * + ENDR + +XmitBuffAvail + MoveA.l OurVarPtr, A0 ; get ptr to our vars + + IF BUFDEBUG THEN + AddQ.l #1, XmtDnActive(A0) + CmpI.l #1, XmtDnActive(A0) + Beq.s @ok + _Debugger ; oooppppsss! +@ok + ENDIF + + Tst.b XmitWait(A0) ; waiting for xmit buffs? + Beq.s @exit ; no + + IF COUNTERS THEN + AddQ.l #1, XmitPend(A0) + ENDIF + + MoveM.l A0/A2/A3/D3, -(SP) ; save C regs + + MoveA.l A0, A2 ; A2->our vars + MoveA.l OurDCE(A2), A1 ; A1->our DCE + MoveA.l dCtlQHead(A1), A0 ; A0->waiting write param blk + + Move.l CSParam+2(A0), D3 ; D3 = 1st parameter longword (e.g. WDSP) + + Bsr DoWrite ; process the write + + MoveM.l (SP)+, A0/A2/A3/D3 ; restore C regs + + IF BUFDEBUG THEN + SubQ.l #1, XmtDnActive(A0) + ENDIF +@exit Rts + + EJECT +;___________________________________________________________________________ +; +; DoRead - read a packet off the Ethernet +; +; Call: +; A0 -> queue element +; A1 -> our DCE +; A2 -> our variables +; D1 = protocol type code +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoRead MoveQ #LAPProtErr,D0 ; Assume an error + Bsr GetProt ; D2 = index into PH table + Bmi ENETDone ; Error if not there + Tst.l (Handlers,A2,D2*4) ; Is it the default? + Bne ENETDone ; Error if not + Move #buf2SmallErr,D0 ; Assume buffer not big enough + Cmp #EHdrSize,EBuffSize(A0) ; Must hold at least header + Blo ENETDone ; Return error if not +; +; Dequeue the request from the system queue and queue it on ours (in order) +; + Lea (RdQueueHd,A2,D2*4),A3 ; A3 -> queue head + Move SR,-(SP) ; Save interrupt status + Move #DMALockOut, D1 + _SETINTMASK D1 +@10 Tst.l (A3) ; Is there a next element? + Beq.s @20 ; Branch if not + Move.l (A3),A3 ; Point to it if so + Bra.s @10 ; And keep going until end + +@20 + IF BIT24 THEN + Exg D0,A0 + And.l AddrMask(A2),D0 + Exg D0,A0 ; 32 bit clean + ENDIF + Move.l A0,(A3) ; Put queue element on our queue + BClr #DrvrActive,DCtlFlags+1(A1) + ; Clear driver active flag + Move.l IOLink(A0),DCtlQHead(A1) ; Set next element addr in head + Bne.s @30 ; Branch if there is none + Clr.l DCtlQTail(A1) ; Clear tail if not +@30 Clr.l IOLink(A0) ; Indicate it's last one on our queue + Move.l DCtlQHead(A1),D0 ; Any more requests? + Beq.s @40 ; Branch if not + BSet #DrvrActive,DCtlFlags+1(A1) + ; We're active again + Move (SP)+,SR ; Restore interrupt state + Move.l D0,A0 ; A0 -> new queue element + MoveQ #0,D0 ; D0 should be clear + Bsr Control ; Call ourselves + MoveQ #0,D0 ; Return no error for previous call + Rts ; Return + +@40 Move (SP)+,SR ; Restore interrupt state + Rts ; Return +;___________________________________________________________________________ +; +; DoRdCancel - abort a pending read call +; +; Call: +; A2 -> our variables +; D3 = pointer to queue element to abort +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoRdCancel Move #CBNotFound,D0 ; Assume an error + IF BIT24 THEN + And.l AddrMask(A2),D3 ; 32 bit clean + ENDIF + Move.l D3,A1 ; A1 -> queue element + Move EProtType(A1),D1 ; D1 = protocol type + Bsr GetProt ; D2 = index into PH table + Bmi.s @60 ; Error if not there + Tst.l (Handlers,A2,D2*4) ; Is it the default? + Bne.s @60 ; Error if not + Lea (RdQueueHd,A2,D2*4),A3 ; A3 -> queue head + Move SR,-(SP) ; Save interrupt status + Move #DMALockOut, D1 + _SETINTMASK D1 +@30 Move.l (A3),D3 ; D3 -> next element in queue + IF BIT24 THEN + And.l AddrMask(A2),D3 ; 32 bit clean + ENDIF + Beq.s @50 ; Error if no more + Sub.l A1,D3 ; Subtract out desired one + Beq.s @40 ; Branch if it's the one + Move.l (A3),A3 ; A3 -> next in queue + Bra.s @30 ; Keep looking + +@40 Move.l (A1),(A3) ; Point previous to next + Move (SP)+,SR ; Restore interrupts +; +; Complete the ERead with an error, then the ERdCancel +; + Move.l A1,A0 ; A0 -> ERead queue element + Move #ReqAborted,D0 ; D0 = aborted error + Bsr.s CompleteReq ; Complete it with error + Bra ENETOk ; Return no error for RdCancel + +@50 Move (SP)+,SR ; Restore interrupt state +@60 Bra ENETDone ; Return not found error + + +;________________________________________________________________________ +; +; CompleteReq - this code basically executes the parts of IODone necessary to +; complete the user's request (sets result code and executes the user's +; completion routine) +; +; Call: +; D0 = result code +; A0 -> I/O queue element +;________________________________________________________________________ + +CompleteReq Move.w D0,IOResult(A0) ; Set the result code + MoveM.l D1-D3/A0-A3,-(SP) ; Save registers + Move.l IOCompletion(A0),D1 ; Check if there's a completion routine + Beq.s @10 ; Branch if not - just return + Move.l D1,A1 ; Get it if so + Tst.w D0 ; IODone does this + Jsr (A1) ; Call completion routine +@10 MoveM.l (SP)+,D1-D3/A0-A3 ; Restore registers + Rts ; Return +;___________________________________________________________________________ +; +; DoGetInfo - return stats in the following form: +; Our address, 3 lw's of 0's, Netstats record +; +; Call: +; A0 -> queue element +; A2 -> our variables +; D3 -> buffer for response +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoGetInfo + IF BIT24 THEN + And.l AddrMask(A2),D3 ; 32 bit clean + ENDIF + Move #buf2SmallErr,D0 ; Assume buffer not big enough + Cmp #6,EBuffSize(A0) ; Must hold at least address + Blo ENETDone ; Return error if not + + MoveQ #0, D0 + Move EBuffSize(A0),D0 ; D0 = buffer size + Cmp #InfoEnd-InfoStart,D0 ; Asking for more than we have? + Bls.s @10 ; no, branch + MoveQ #InfoEnd-InfoStart,D0 ; yes, just return what we have +@10 Move.l D3,A1 ; A1 -> where to move to + Lea InfoStart(A2),A0 ; A0 -> where to move from + +; +; Copy netstat info from Dot2stat and LAPMIBstat areas to "old" getinfo area +; + Move.l (LAPStats.ifOutUcastPkts,A2), D1 + Add.l (LAPStats.ifOutNUcastPkts,A2), D1 + Move.l D1, (EtherStats.TxOK,A2) + Move.l (Dt3Stats.dot3StatsSingleCollisionFrames,A2), (EtherStats.sCollFrame,A2) + Move.l (Dt3Stats.dot3StatsMultipleCollisionFrames,A2), (EtherStats.mCollFrame,A2) +; EtherStats.CollFrame doesn't make sense and is left 0 + Move.l (Dt3Stats.dot3StatsDeferredTransmissions,A2), (EtherStats.DefTx,A2) + Move.l (Dt3Stats.dot3StatsLateCollisions,A2), (EtherStats.LateColl,A2) + Move.l (Dt3Stats.dot3StatsExcessiveCollisions,A2), (EtherStats.ExcessColl,A2) + Move.l (Dt3Stats.dot3StatsExcessiveDeferrals,A2), (EtherStats.ExcessDef,A2) + Move.l (Dt3Stats.dot3StatsInternalMacTransmitErrors,A2), (EtherStats.InMACTxErr,A2) + Move.l (LAPStats.ifInUcastPkts,A2), (EtherStats.RxOK,A2) + Move.l MultiRecvd(A2), (EtherStats.MultiRxOK,A2) + Move.l BcastRecvd(A2), (EtherStats.BroadRxOK,A2) + Move.l (Dt3Stats.dot3StatsFCSErrors,A2), (EtherStats.FCSerr,A2) + Move.l (Dt3Stats.dot3StatsAlignmentErrors,A2), (EtherStats.FAerr,A2) + Move.l (LAPStats.ifInErrors,A2), (EtherStats.MPerr,A2) + + _BlockMove ; Move it + Bra ENETOK ; Return no error + +;___________________________________________________________________________ +; +; EtherRecv - .ENET packet receive routine +; +; Call: +; Received packet(s) pointed to by buffer(s) on InUse Queue +; +; Return: +; Empty InUse Queue +; +; Destroys: +; Notes: +; EtherRecv is called by the MACE since we passed a ptr to EtherRecv +; as the RecvRtn in the MACEInit call. +; +; Calls: +; Upper layer handler, or Default Handler, to receive packet. +;___________________________________________________________________________ + +EtherRecv + WITH RcvParms + Link A6, #Size + + Move.l Stat(A6), D0 ; get packet status + AndI.w #(1< RHA + MoveA.l Pkt(A6), A0 ; A0 -> packet data + Move.l (A0)+, (A3)+ ; Move header into buffer + Move.l (A0)+, (A3)+ ; Hard code for speed + Move.l (A0)+, (A3)+ + Move (A0)+, (A3)+ ; A3 -> buffer after header +; +; Check if dest. addr. a broadcast or one of our multicasts +; + Move RHA(A2), D3 ; D3 = first 2 bytes of dest address + BTst #8, D3 ; Is it a broadcast or multicast? + Beq.s @45 ; Branch if not, it must be our physical address + MoveQ #-1, D2 ; D2 = $FFFFFFFF + Cmp D2, D3 ; Is packet a broadcast? + Beq.s @last4 ; Maybe, check last 4 bytes of dest address + Move.l RHA+2(A2), D3 ; No, D3 = last 4 bytes of dest address + Bra @120 ; Go check if one of our registered multicasts +@last4 Move.l RHA+2(A2), D3 ; D3 = last 4 bytes of dest address + Cmp.l D2, D3 ; Is packet a broadcast? + Bne @120 ; No, go check if one of our registered multicasts + AddQ.l #1, BcastRecvd(A2) ; Yes, inc. broadcast pkt cntr + Bra.s @50 + +@45 AddQ.l #1, (LAPStats.ifInUcastPkts,A2) ; inc. non-multi/bcast pkt cntr + +; +; Search the protocol handler table for this protocol +; + +@50 Move EType-EHdrSize(A3),D0 ; D0 = protocol type or 802.3 length + Cmp.w #EMaxDataSz,D0 ; is it an 802.3? + Bhi @110 ; if not, try other protocols + + Clr D0 ; Handler will be for type zero + Exg D0,D1 ; D1 = protocol type, D0 = old D1 + Bsr GetProt ; D2 = offset in table + Exg D0,D1 ; Restore D0, D1 + Bmi.s @90 ; Branch if not found +; Move EType-EHdrSize(A3),D0 ; D0 = protocol type + +@70 Lea EReadPacket,A4 ; A4 -> our ReadPacket routine + Lea DefaultPH,A5 ; use default maybe + Move.l (Handlers,A2,D2*4),D3 ; get the protocol handler + Beq.s @80 ; use default + MoveA.l D3,A5 ; use table entry's protocol handler + +@80 + Jsr (A5) ; Call protocol handler + +@85 MoveM.l (SP)+, A2-A5/D3 ; Restore registers +@86 Unlk A6 + Rts ; That's it + +@90 AddQ.l #1, LAPStats.ifInUnknownProtos(A2) + Bra.s @85 +; +; Find Protocol handler for non 802.3 packet +; +@110 + Exg D0,D1 ; D1 = protocol type, D0 = old D1 + Bsr GetProt ; D2 = offset in table + Exg D0,D1 ; Restore D0, D1 + Bmi.s @90 ; Branch if not found + + Bra.s @70 ; Process it + +; +; Packet is a multicast. Check if it matches one of our multicast addresses. +; +; Call: +; A2 -> our variables +; D3 = last 4 bytes of destination address +; +@120 Move D1,D0 ; Save length in case packet's for us + Move RHA(A2),D1 ; D1 = high two bytes of address + Bsr FindMEntry ; D2 = entry within multicast table + Bmi.s @150 ; Ignore it if not found + AddQ.l #1, MultiRecvd(A2) ; Inc count of multicast pkts recv'd + Move D0,D1 ; Restore packet length + Bra @50 ; And process packet + +@150 AddQ.l #1, LAPStats.ifInDiscards(A2) ; Increment count of packets not for us + Bra.s @85 ; Ignore this packet + + IF PROM THEN +;___________________________________________________________________________ +; +; EtherRecvProm - Promiscuous .ENET packet receive routine +; +; Call: +; Received packet(s) pointed to by buffer(s) on InUse Queue +; +; Return: +; Empty InUse Queue +; +; Destroys: +; Notes: +; EtherRecvProm is called by the MACE since we passed a ptr to it +; as the RecvRtn in the MACEInit call. +; +; Calls: +; Upper layer handler, or Default Handler, to receive packet. +;___________________________________________________________________________ + +EtherRecvProm + WITH RcvParms + Link A6, #Size + MoveM.l A2-A5/D3,-(SP) ; save used C regs + + MoveA.l Parm(A6), A2 ; Our variables + IF COUNTERS THEN + AddQ.l #1, EtherRcvCnt(A2) + ENDIF + Move Len(A6), D1 ; D1=size of packet, including FCS + Sub #EHdrSize, D1 ; Subtract header from, leave 4 FCS in total +; +; Copy the Ethernet header from the packet into the RHA +; + Lea PromiscRHA(A2), A3 ; A3 -> PromiscRHA + Move.l Stat(A6), D0 ; get packet status + Move.l D0, (A3)+ ; Put pkt status at -4(RHA(A2)) + MoveA.l Pkt(A6), A0 ; A0 -> packet data + Move.l (A0)+, (A3)+ ; Move header into buffer + Move.l (A0)+, (A3)+ ; Hard code for speed + Move.l (A0)+, (A3)+ + Move (A0)+, (A3)+ ; A3 -> buffer after header + + AndI.w #(1< our ReadPacket routine + Lea DefaultPH,A5 ; use default maybe + Move.l (Handlers,A2,D2*4),D3 ; get the protocol handler + Beq.s @80 ; use default + MoveA.l D3,A5 ; use table entry's protocol handler + +@80 + Jsr (A5) ; Call protocol handler + +@85 MoveM.l (SP)+, A2-A5/D3 ; Restore registers + Unlk A6 + Rts ; That's it + +;@90 AddQ.l #1, LAPStats.ifInUnknownProtos(A2) + + ENDIF ; PROM +;___________________________________________________________________________ +; +; EReadPacket - read in the specified number of bytes into the specified +; buffer. Asking for more than there is is an error. +; +; EReadRest - read in the rest of the packet, putting the specified number +; of bytes into the specified buffer, and ignoring the rest. +; +; Call: +; A0 -> current location in card memory +; A1 -> card registers +; A3 -> buffer to read into +; A4 -> start of ReadPacket +; D1 = number of bytes left to come in (caller may decrease) +; D3 = byte count to read +; +; Return: +; D0 = error byte (Z bit set in CCR) +; D1 updated (ReadPacket) +; D2 saved +; D3 = 0 if exact number of bytes requested were read +; > 0 indicates number of bytes requested but not read +; (packet smaller than requested maximum) +; < 0 indicates number of extra bytes read but not returned +; (packet larger than requested maximum) +; A0,A1 preserved by ReadPacket, modified by ReadRest +; A2 saved +; A3 -> one past where last character went +; A4,A5 saved (until packet's all in or error) +;___________________________________________________________________________ + +EReadPacket Bra.s EDoRP ; Need this for two entry points + +EReadRest Move D3,D0 ; D0 = number of bytes to return + Sub D1,D0 ; D0 = remainder count + Tst D3 ; Check for zero + Beq.s @10 ; If so, don't waste our time + Bsr.s MoveBytes ; Move the bytes in +@10 Move D0,D3 ; D3 = remainder count + MoveQ #0,D0 ; No error no matter what + Rts +EDoRP + Cmp.w D3,D1 + Blo.s @5 ; error in request + Bsr.s MoveBytes ; Move in the bytes + Tst D3 ; Moved them all? + Beq.s @10 ; Branch if moved all ok +@5 MoveQ #eLenErr,D0 ; Set length error +@10 Rts ; Return +;___________________________________________________________________________ +; +; DefaultPH - default protocol handler - complete an ERead call if there +; +; Call: +; A0,A1: preserve until ReadRest +; A2 -> local variables +; A4 -> EReadPacket +; A5 usable until ReadRest +; D0 = protocol type +; D2 = index into protocol table +; +; Notes: Interrupts are off +; +;___________________________________________________________________________ + +DefaultPH + Move.l (RdQueueHd,A2,D2*4),D0 ; D0 -> first ERead on queue + Beq.s @20 ; Skip packet if none + Move.l D0,A5 ; A5 -> ERead queue element + Move.l (A5),(RdQueueHd,A2,D2*4) ; Remove from queue + Move.l D0,D2 ; D2 = queue element pointer + Move.l EBuffPtr(A5),A3 ; A3 -> buffer to read into + Move EBuffSize(A5),D3 ; D3 = maximum size to read + Sub #EHdrSize,D3 ; Adjust for header + IF PROM THEN + Tst.B Promiscflg(A2) ; Are we in Promiscuous mode? + Beq.S @5 ; No, Note: not set until pass lpbk test + Lea PromiscRHA(A2), A5 ; A5 -> header info including pkt status lw + Move.l (A5)+,(A3)+ ; Move pkt status into buffer + Bra.s @6 +@5 Lea RHA(A2),A5 ; A5 -> header info +@6 + ELSE + Lea RHA(A2),A5 ; A5 -> header info + ENDIF + Move.l (A5)+,(A3)+ ; Move header into buffer + Move.l (A5)+,(A3)+ ; Hard code for speed + Move.l (A5)+,(A3)+ ; (AssumeEq?) + Move (A5)+,(A3)+ ; A3 -> buffer after header + Jsr 2(A4) ; Read in the whole thing (D0=0) + Move.l D2,A0 ; A0 -> queue element again + Move EBuffSize(A0),D1 ; D1 = original request size + Sub D3,D1 ; D1 = total packet size + Move D1,EDataSize(A0) ; Set in queue element + Tst D3 ; Check for buffer overflow + Bpl.s @10 ; Branch if no overflow + Move #buf2SmallErr,D0 ; Set error +@10 Bra CompleteReq ; Complete request and return + +@20 MoveQ #0,D3 ; Indicate no buffer + Jmp 2(A4) ; Ignore packet and return + + +;___________________________________________________________________________ +; +; MoveBytes - move bytes from card memory to desired place +; +; Call: +; A0 -> current location in card memory +; A3 -> place to move bytes to +; D1 = number of bytes left in packet +; D3 = number of bytes to move +; +; Return: +; A0 adjusted +; A3 adjusted past bytes moved in +; D1 adjusted +; D3 = zero if all could be moved, remainder otherwise +;___________________________________________________________________________ + +MoveBytes + + MoveM.l D0/D2/A1/A2,-(SP) ; Save registers + Move.l OurVarPtr,A2 ; A2 -> our variables + IF BIT24 THEN + Exg D0,A3 + And.l AddrMask(A2),D0 + Exg D0,A3 ; 32 bit clean + ENDIF + Move.l A3,A1 ; A1 -> where to move to + MoveQ #0,D0 ; D0 = number of bytes to move + Move D3,D0 ; Assume we can move all asked for + Cmp D1,D3 ; Can we move all asked for? + Bls.s @10 ; Branch if so + Move D1,D0 ; Else move all we can +@10 Sub D0,D1 ; Adjust count left to come in + Sub D0,D3 ; D3 = bytes not moved + AddA.w D0,A3 + + Move.l D1,-(SP) ; save this one + Move.l A0,-(SP) + Move.l D0,-(SP) + Jsr ([MemMove,A2]) ; call block move routine + MoveA.l (SP)+,A0 + AddA.l (SP)+,A0 ; adjust pointer + Move.l (SP)+,D1 + +@30 MoveM.l (SP)+,D0/D2/A1/A2 ; Restore registers + Rts ; That's it +;________________________________________________________________________ +; +; Close - close the ENET driver. +; +; Call: +; A1 -> DCE +;________________________________________________________________________ + +Close +; This code is only called if one of the LoopBack tests failed. Closing is +; not a supported function since there is no way for me to know how many +; clients are using the driver; ie. AppleTalk using 802.3 and MacTCP using +; Ethernet. If the Device Manager passed all open calls to the driver a +; use-count could be implemented and I could truely support Close. + MoveA.l OurVarPtr, A2 ; A2 -> our variables + + Bsr MACEHalt ; stop MACE + + MoveQ #LAPTblSz-1,D2 ; D2 = Index into active protocols list +@10 Tst.b InUseFlag(A2,D2) ; Active? + Beq.s @20 ; Branch if not + Tst.l (Handlers,A2,D2*4) ; Default handler + Bne.s @20 ; Branch if not + Bsr AbortAll ; Abort all requests +@20 DBra D2,@10 ; On to next + + Lea VBLQEL(A2),A0 + Tst.l vblAddr(A0) ; did we launch ctl call VBL? + Beq.s @50 + _VRemove ; remove VBL task if so +@50 + IF PRIMEDEFER THEN + Lea DoWriteQEL(A2),A0 + Tst.l tmAddr(A0) ; did we install xmit buff full deferral? + Beq.s @60 ; no, do nothing + Tst.b XmitWait(A2) ; have we prime'd task? + Beq.s @55 ; no, remove task + _Debugger ; rmvtime doesn't really remove an active task ?!? + ; need method to handle this case +@55 + _RmvTime ; remove TimeMgr task if so +@60 + ENDIF + MoveA.L OurVarPtr,A0 + _DisPosPtr ; free our var mem + + Lea OurVarPtr,A2 ; A2 -> variable pointer + Clr.l (A2) ; Clear it out (no variables) + MoveQ #0,D0 ; Indicate no error +AnRts Rts ; And return + +; +; Variable storage +; +OurVarPtr DC.l 0 ; Pointer to our variables + END + + + diff --git a/DeclData/DeclNet/Mace/MaceEnet.a.idump b/DeclData/DeclNet/Mace/MaceEnet.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Mace/MaceEnet.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Mace/MaceEnet.a.rdump b/DeclData/DeclNet/Mace/MaceEnet.a.rdump new file mode 100644 index 0000000..9804eba --- /dev/null +++ b/DeclData/DeclNet/Mace/MaceEnet.a.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0000 F0D2 0001 CD42" /* ..Monaco.......B */ + $"0000 0200 0000 F200 0200 0000 0000 0000" /* ................ */ + $"0000 0006 0004 0029 0242 035A 0479 0029" /* .......).B.Z.y.) */ + $"0242 035A 0479 A839 2AE4 0000 0137 0000" /* .B.Z.y.9*....7.. */ + $"015F 0000 0000 0100" /* ._...... */ +}; + +data 'MPSR' (1008) { + $"0029 0242 035A 0479 0029 0242 035A 0479" /* .).B.Z.y.).B.Z.y */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"0C58 0EBB 3FE5 3230 0004 0000 0000 0000" /* .X..?.20........ */ + $"0000 A933 739B A933 739B A6F7 B0C6 0078" /* ...3s..3s......x */ + $"BC36 0000 0003 0010 2553 7570 6572 4D61" /* .6......%SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA4D 6163 65BA 000E" /* .DeclNet.Mace... */ + $"4368 7269 7320 5065 7465 7273 656E 0001" /* Chris Petersen.. */ + $"3900 0A4D 6163 6545 6E65 742E 6100 0000" /* 9..MaceEnet.a... */ + $"000F 526F 6C6C 2069 6E20 4C75 6477 6967" /* ..Roll in Ludwig */ + $"2E00" /* .. */ +}; + diff --git a/DeclData/DeclNet/Mace/MaceEqu.a b/DeclData/DeclNet/Mace/MaceEqu.a new file mode 100644 index 0000000..883a935 --- /dev/null +++ b/DeclData/DeclNet/Mace/MaceEqu.a @@ -0,0 +1,336 @@ +; +; File: MaceEqu.a +; +; Contains: Equates for accessing the Ethernet Media Access +; Controller (MACE) +; +; Written by: Mark A. Law +; +; Copyright: © 1991-1993 by Apple Computer, Inc. All rights reserved. +; +; This file is used in these builds: Mac32 +; +; Change History (most recent first): +; +; 6/14/93 kc Roll in Ludwig. +; 5/1/93 mal #1082434 Added records for new GetMem & FreeMem rtns. +; 3/21/93 mal Versioned record for MACE 'ecfg' rsrc. +; 1/27/93 mal Added MACEecfg rsrc support. +; 12/4/92 mal Removed OFLO bit from recv pkt status. +; 11/19/92 mal Added equ for yet another bit AMD didn't tell us about. +; 10/30/92 mal MaceInitParms record change. +; 10/13/92 mal -changed status thats passed to RecvRtn to lw +; <1> 10/6/92 GDW New location for ROMLink tool. +; 6/22/92 mal Changes to support PSC2's (EVT2) Ethernet DMA receive model. +; 4/30/92 mal Expanded MaceInitParms record. +; 4/27/92 mal Added MaceInit parameters record. +; 3/23/92 mal Added MACE MAC config reg bit defines +; + + ; --------------------------------------------------------- + ; MACE Registers + ; --------------------------------------------------------- +MACERegBase EQU $50F1C000 ; Mace Reg Base on Cyclone + +MACERegs RECORD 0 +MACE_RX_FIFO DS.W 1 ;RD RXData -Read Status first + ORG *+$e +MACE_XMIT_FIFO DS.W 1 ;TX TXData + ORG *+$e +MACE_TX_FRM_CNTRL DS.B 1 ;RD/WR 01=Retry,XMTFCS,AUTOPAD + ORG *+$f +MACE_TX_FRM_STAT DS.B 1 ;RD + ORG *+$f +MACE_TX_RETRY_CNT DS.B 1 ;RD + ORG *+$f +MACE_RX_FRM_CNTRL DS.B 1 ;RD/WR 00 = Not_AutoStripPad + ORG *+$f +MACE_RX_FRM_STAT DS.B 1 ;RD Read 4x to get RX Status of packet + ORG *+$f +MACE_FIFO_FRM_CNT DS.B 1 ;RD Number of frames in FIFO + ORG *+$f +MACE_INT DS.B 1 ;RD_1 Interupt Source bits + ORG *+$f +MACE_INT_MSK DS.B 1 ;RD/WR Interupt Enables + ORG *+$f +MACE_POLL DS.B 1 ;RD Yet another status location + ORG *+$f +MACE_BIU_CNFG DS.B 1 ;RD/WR 20 = normal mode 01 = Soft Reset + ORG *+$f +MACE_FIFO_CNFG DS.B 1 + ORG *+$f +MACE_MAC_CNFG DS.B 1 ;Enables + ORG *+$f +MACE_PLS_CNFG DS.B 1 ;RD/WR 0=Normal Mode + ORG *+$f +MACE_PHY_CNFG DS.B 1 ;RD/WR Reserved,Dude. + ORG *+$f +MACE_CHIP_ID_LOW DS.B 1 ;RD Just Reads ID + ORG *+$f +MACE_CHIP_ID_HIGH DS.B 1 ;RD Just Reads ID + ORG *+$f +MACE_ADDR_CNFG DS.B 1 ;RD/WR 04=Phy_Addr, 02=Log_Addr + ORG *+$1f +MACE_LOG_ADDR DS.B 1 ;Load with 6 Zeros + ORG *+$f +MACE_PHY_ADDR DS.B 1 ;Load with Address + ORG *+$2f +MACE_MISSED_PKT_CNT DS.B 1 ;RD + ORG *+$4f +MACE_USER_TEST_REG DS.B 1 ; + ENDR +; +; MACE Interrupt Reg. & Int. Reg. Mask Bit defines +; MACE Int. Reg - Read/Clear; MACE Int. Mask Reg. - Read/Write +; +BABL EQU 6 ; Babble, Xmit timeout error +CERR EQU 5 ; Signal Quality Error (SQE), xmit +RCVCO EQU 4 ; Receive Collision Cnt Overflow +MPCO EQU 2 ; Missed Pkt Cnt Overflow +RCVINT EQU 1 ; Rcv int +XMTINT EQU 0 ; Xmit int + ; mask to disable all MACE ints +MaceIntMask EQU (1< max pkt, used for Recv DMA cnt + +CntRegMask EQU $0001ffff ; Ignore upper 15 bits + +nobuff EQU -2 ; no xmit buffer available + +;•••••••••••••••• Network Statistics +NetStats RECORD 0 ; network management stats. +TxOK DS.L 1 ; frames transmitted OK +sCollFrame DS.L 1 ; single collision frames +mCollFrame DS.L 1 ; multiple collision frames +CollFrame DS.L 1 ; collision frames +DefTx DS.L 1 ; deferred transmissions +LateColl DS.L 1 ; late collisions +ExcessColl DS.L 1 ; excessive collisions +ExcessDef DS.L 1 ; excessive defferals +InMACTxErr DS.L 1 ; internal MAC transmit errors +RxOK DS.L 1 ; frames received OK +MultiRxOK DS.L 1 ; multicast frames recd OK +BroadRxOK DS.L 1 ; broadcast frames recd OK +FCSerr DS.L 1 ; frame check sequence errors +FAerr DS.L 1 ; frame alignment errors +MPerr DS.L 1 ; missed packet errors +Size EQU * + ENDR + +;•••••••••••••••• General Equates +TalliesPerSec EQU 5000000 ; number of timer ticks/second +TxMaxRetries EQU 4 ; max attempts to retry aborted xmits +Max_Tx_Packets EQU 16 ; maximum # of chained Tx packets +Min_Pkt_Size EQU 60 ; minimum packet size +Min_Rx_Buffs EQU 2 ; minimum # of recv descriptors/buffers +Max_Pkt_Size EQU 1518 ; maximum packet size (inc. CRC) +EOL_Bit EQU 0 ; end-of-link bit + +;•••••••••••••••• For GetMemory call +GetMem RECORD 0 +memsize DS.l 1 ; requested size +memoptions DS.l 1 ; requested options +memhndl DS.l 1 ; handle to memory mgr block +memhndla DS.l 1 ; handle to 4 or 8k aligned memory +memhndlasz DS.l 1 ; ptr to 4 or 8k aligned memory size +GetMemSz EQU * + ENDR + +Locked EQU 0 ; want locked memory +Contig EQU 1 ; want contiguous memory +CacheOff EQU 2 ; want non-cacheable memory + +;•••••••••••••••• For FreeMemory call +FreeMem RECORD 0 +memoptions DS.l 1 ; requested options +memptr DS.l 1 ; ptr to memory mgr block +memptra DS.l 1 ; ptr to 4 or 8k aligned memory +memptrasz DS.l 1 ; 4 or 8k aligned memory size +FreeMemSz EQU * + ENDR + +;•••••••••••••••• Initialization Parameters +MACEInitParms RECORD 0 +RecvRtn DS.l 1 ; address of Ethernet receive routine +RecvPrms DS.l 1 ; parms to pass @ receive +XmitRtn DS.l 1 ; address of Ethernet xmit complete routine +XmitPrms DS.l 1 ; parms to pass @ xmit complete +MACECfgPtr DS.l 1 ; ptr to MACE config record +Dot3NetStats DS.l 1 ; ptr to 802.3 statistics array +LAPMIBNetStats DS.l 1 ; ptr to LAP MIB statistics array +EnetAddr DS.l 1 ; ptr to ethernet address +FastMoveRtn DS.l 1 ; ->proc to move memory FAST +IPSize EQU * + ENDR + +;•••• Parms passed to .ENET "RecvRtn" +RcvParms RECORD {A6Link} +Size EQU * ; no local vars +A6Link DS.l 2 ; saved A6 and return addr +Parm DS.l 1 ; parm passed to MaceInit +Buff DS.l 1 ; ptr to Mace's buffer containing pkt +Pkt DS.l 1 ; ptr to packet data +Len DS.w 1 ; pkt length +Stat DS.l 1 ; pkt status +; Stat definition: +; Byte 0: Receive Runt Packet Count (Bits 31-24) +; -number of runts recv'd since last successfully recv'd pkt +; -maxs at 255 +; Byte 1: Receive Collision Count (Bits 23-16) +; -number of collisions since last successfully recv'd pkt +; -maxs at 255 +; Byte 2-3: Receive Status (Bits 15-0) +; Bits 15-7,3-0 : reserved, read as 0's +; Bits 6-4 : Recv Message Status bits +; RcvCLSN EQU 6 ; late collision during recv +; RcvFRAM EQU 5 ; frame error, non-integer # of bytes +; RcvFCS EQU 4 ; frame check sequence error +ParmsSz EQU * - Parm ; len of passed parms + ENDR + +Configrsrc EQU 'ecfg' ; rsrc type for MACE config data rsrc + +; Mace Configuration Record +MACECfg RECORD 0 ; Config values from config rsrc +MACECfgVers DS.w 1 ; record version +MACEBase DS.l 1 ; Base address of MACE +EnetPROM DS.l 1 ; base address of Address Prom +XmitFrmCtl DS.b 1 ; MACE transmit frame control register value +RecvFrmCtl DS.b 1 ; MACE receive frame control register value +FIFOCfgCtl DS.b 1 ; MACE xmit/recv fifo config control register value +MACCfgCtl DS.b 1 ; MACE MAC config control register value + ; The following are optional values; ignored if zero +EnetAddr DS.b 6 ; Alternate Ethernet Address, overrides Address PROM +XmitBuffs DS.w 1 ; Alternate number of transmit buffers +RecvBuffs DS.w 1 ; Alternate number of receive buffers +RecvChains DS.w 1 ; Alternate number of receive "chains" +CfgSize EQU * + ENDR diff --git a/DeclData/DeclNet/Mace/MaceEqu.a.idump b/DeclData/DeclNet/Mace/MaceEqu.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Mace/MaceEqu.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Mace/MaceEqu.a.rdump b/DeclData/DeclNet/Mace/MaceEqu.a.rdump new file mode 100644 index 0000000..4daa6c9 --- /dev/null +++ b/DeclData/DeclNet/Mace/MaceEqu.a.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"000C 436F 7572 6965 7200 2A2A 2A2A 2A2A" /* ..Courier.****** */ + $"2A2A 2A2A 2A2A 2A2A 2A2A 2A0D 3B09 4571" /* ***********.;.Eq */ + $"7561 0007 0004 0029 0242 035A 0479 0029" /* ua.....).B.Z.y.) */ + $"0242 035A 0479 A839 2AA8 0000 0129 0000" /* .B.Z.y.9*....).. */ + $"0151 0000 0000 0100" /* .Q...... */ +}; + +data 'MPSR' (1008) { + $"0029 0242 035A 0479 0029 0242 035A 0479" /* .).B.Z.y.).B.Z.y */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"7F7E 54A0 3FE5 3230 0004 0000 0000 0000" /* .~T.?.20........ */ + $"0000 A933 739B A933 739B A6F7 B0C6 0078" /* ...3s..3s......x */ + $"BC36 0000 0004 000A 2553 7570 6572 4D61" /* .6......%SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA4D 6163 65BA 000E" /* .DeclNet.Mace... */ + $"4368 7269 7320 5065 7465 7273 656E 0001" /* Chris Petersen.. */ + $"3600 094D 6163 6545 7175 2E61 0000 0000" /* 6..MaceEqu.a.... */ + $"0F52 6F6C 6C20 696E 204C 7564 7769 672E" /* .Roll in Ludwig. */ + $"00" /* . */ +}; + diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/PDMEnet.make b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMEnet.make new file mode 100644 index 0000000..c6ad270 --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMEnet.make @@ -0,0 +1,83 @@ +# Contains: Makefile for PDM MACE Ethernet driver. +# +# Written by: Dave Calvert +# +# Copyright: © 1993 by Apple Computer, Inc., all rights reserved. +# +# Change History (most recent first): +# +# 3/5/93 dwc Changed DeclDataPDMMace.rsrc ID to be unique from +# DeclDataMace.rsrc. +# 3/4/93 dwc Added DeclDataPDMMace definition for PDM ENET. +# 2/25/93 dwc Re-enable loopbacktests and include Interface.o for them. +# 2/4/93 RC Took out Loopback.c.o link and fixed {make} to {makedir} +# + + +#=============================================================================== +# Create DeclData Resource for PDM Declaration ROM +#=============================================================================== +"{RsrcDir}DeclDataPDMMace.rsrc" ƒ "{ObjDir}PDMMaceEnet.a.o" ∂ + "{ObjDir}PDMMace.a.o" ∂ + "{ObjDir}Loopback.c.o" ∂ + "{IfObjDir}interface.o" + Link {StdLOpts} {StdAlign} -rt decl=1 -o "{Targ}" ∂ + "{ObjDir}PDMMaceEnet.a.o" ∂ + "{ObjDir}PDMMace.a.o" ∂ + "{ObjDir}Loopback.c.o" ∂ + "{IfObjDir}Interface.o" + +"{RsrcDir}PDMENET.rsrc" ƒ "{ObjDir}PDMMaceEnet.a.o" ∂ + "{ObjDir}PDMMace.a.o" ∂ + "{PDMMaceDir}PDMEnet.make" ∂ + "{ObjDir}Loopback.c.o" ∂ + "{IfObjDir}Interface.o" + Link -t rsrc -c RSED -sn Main="PDM MACE Ethernet Driver" ∂ + -ra "PDM MACE Ethernet Driver"=resSysHeap,resPurgeable,resLocked ∂ + -rt enet=57 -o {Targ} ∂ + "{ObjDir}PDMMaceEnet.a.o" ∂ + "{ObjDir}PDMMace.a.o" ∂ + "{ObjDir}Loopback.c.o" ∂ + "{IfObjDir}Interface.o" + +"{RsrcDir}PDMENET57.rsrc" ƒ "{ObjDir}PDMMaceEnet.a.o" ∂ + "{ObjDir}PDMMace.a.o" ∂ +# "{ObjDir}Loopback.c.o" ∂ + "{PDMMaceDir}PDMEnet.make" + Link -t rsrc -c RSED -sn Main="PDM MACE Ethernet Driver" ∂ + -ra "PDMENET"=resSysHeap,resPurgeable,resLocked ∂ + -rt enet=57 -o {Targ} ∂ + "{ObjDir}PDMMaceEnet.a.o" ∂ +# "{ObjDir}Loopback.c.o" ∂ + "{ObjDir}PDMMace.a.o" + +#=============================================================================== +# Assemble Stuff +#=============================================================================== + + +"{ObjDir}PDMMace.a.o" ƒ "{PDMMaceDir}PDMMace.a" ∂ + "{PDMMaceDir}PDMMaceEqu.a" ∂ + "{IntAIncludes}AMICEqu.a" ∂ + "{IntAIncludes}UniversalEqu.a" ∂ + "{EthernetDir}ATalkMacros.a" ∂ + "{PDMMaceDir}PDMEnet.make" + Asm {StdAOpts} {Defs} -i "{PDMMaceDir}" -i "{EthernetDir}" -o "{Targ}" "{PDMMaceDir}PDMMace.a" + +"{ObjDir}PDMMaceEnet.a.o" ƒ "{PDMMaceDir}PDMMaceEnet.a" ∂ + "{PDMMaceDir}PDMMaceEqu.a" ∂ + "{PDMMaceDir}VersionPDMMaceEnet.a" ∂ + "{EthernetDir}802Equ.a" ∂ + "{EthernetDir}ATalkMacros.a" ∂ + "{EthernetDir}ENETEqu.a" ∂ + "{EthernetDir}SNMPLAP.a" ∂ + "{IntAIncludes}UniversalEqu.a" ∂ + "{IntAIncludes}AMICEqu.a" ∂ + "{AIncludes}GestaltEqu.a" ∂ + "{AIncludes}SysEqu.a" ∂ + "{AIncludes}SysErr.a" ∂ + "{AIncludes}Traps.a" ∂ + "{AIncludes}Slots.a" ∂ + "{PDMMaceDir}PDMEnet.make" + Asm {StdAOpts} {Defs} -i "{PDMMaceDir}" -i "{EthernetDir}" -o "{Targ}" "{PDMMaceDir}PDMMaceEnet.a" + diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/PDMEnet.make.idump b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMEnet.make.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMEnet.make.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/PDMEnet.make.rdump b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMEnet.make.rdump new file mode 100644 index 0000000..f07a531 --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMEnet.make.rdump @@ -0,0 +1,29 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0065 6F72 6765 2044" /* ..Monaco.eorge D */ + $"2E20 5769 6C73 6F6E 204A 722E 0D23 0D23" /* . Wilson Jr..#.# */ + $"0943 0006 0004 00B4 000C 0363 043D 00B4" /* .C.........c.=.. */ + $"000C 0363 043D A7BD 0EC8 0000 0000 0000" /* ...c.=.......... */ + $"0000 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"00B4 000C 0363 043D 00B4 000C 0363 043D" /* .....c.=.....c.= */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"ABA3 F3A9 3FE5 3230 0004 0000 0000 0000" /* ....?.20........ */ + $"0000 A933 73A3 A933 73A3 A796 71C8 0006" /* ...3s..3s...q... */ + $"D7AA 0000 0005 0006 3153 7570 6572 4D61" /* ........1SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA4D 6163 65BA 5044" /* .DeclNet.Mace.PD */ + $"4D4D 6163 6545 6E65 74BA 000E 4368 7269" /* MMaceEnet...Chri */ + $"7320 5065 7465 7273 656E 0001 3600 0C50" /* s Petersen..6..P */ + $"444D 456E 6574 2E6D 616B 6500 0000 0044" /* DMEnet.make....D */ + $"4368 616E 6765 6420 4465 636C 4461 7461" /* Changed DeclData */ + $"5044 4D4D 6163 652E 7273 7263 2049 4420" /* PDMMace.rsrc ID */ + $"746F 2062 6520 756E 6971 7565 2066 726F" /* to be unique fro */ + $"6D20 4465 636C 4461 7461 4D61 6365 2E72" /* m DeclDataMace.r */ + $"7372 632E 00" /* src.. */ +}; + diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMace.a b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMace.a new file mode 100644 index 0000000..e56df6d --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMace.a @@ -0,0 +1,1715 @@ +; +; File: PDMMace.a +; +; Contains: routines to support MACE when coupled with a AMIC-style DMA model +; +; Written by: Sean Findley, Mark A. Law, Gary Rensberger +; +; Copyright: © 1990-1993 by Apple Computer, Inc., all rights reserved. +; +; Change History (most recent first): +; +; 10/6/93 RC Took out PDM EVT1 support +; 9/20/93 GMR Fixed a bug where we might count a xmit frame twice, if we got +; an underflow interrupt in the middle of transmission. +; 9/9/93 pdw Changed installation of MACE int to maceVector in +; DMADispatchGlobals instead of ddMACE…. +; 9/2/93 chp Change MaceVarPtr from DC.L 1 to DC.L 0 so that the MACE +; variables are initialized to “none.” +; 8/30/93 chp InterruptHandlers.a now supports MACE interrupts on PDM. +; Modified the MACEInterrupt exception handler to run as a +; subroutine to the system interrupt dispatcher, so deferred tasks +; can now run following a MACE interrupt. Modified MACE and Enet +; DMA interrupt routines to save and restore only those registers +; not saved by the interrupt dispatcher. Modified the install code +; to install interrupt handlers into the AMIC dispatch table +; rather than AutoInt3, and to do so directly rather than calling +; _DMAIntInstall. +; 8/20/93 GMR Added AMIC4 support (don't apply AMIC headPtr hack if on AMIC4). +; 8/4/93 GMR Fixed a bug that caused the xmit routine to count a packet as +; going out, but which didn't go out because of a bad length. +; 7/1/93 GMR Backed out a couple of the changes in which were +; unnecessary; the branch to the wrong label was the only change +; needed to fix the problem. +; 7/1/93 pdw Fixed the "Blowed up after Macsbug" bug which was due to not +; handling MACE Overflow problems correctly which were due to AMIC +; overflows caused by the deferred task processing of packets +; which was not happening because Macsbug turns off the Deferred +; Task Manager which was... It was late one night... Actually we +; just moved the @done label up one line. +; 6/28/93 GMR Made receive handling use deferred tasks now, instead of +; processing at level 4. +; 6/10/93 GMR Fixed a couple bugs (found by test tool) in the level 3 Mace +; handler, and in handling transmit completions. +; 6/8/93 GMR Added support for EVT1. Temporarily fixed privilage violation +; when running VM; the level 3 handler installation really needs +; support from Inthandlers.a. +; 6/3/93 GMR Remove debugger on receive overflow. +; 6/2/93 GMR Now, defer transmits until we get a MACE interrupt indicating +; the previous packet went out. +; 6/2/93 GMR Rewrote the interrupt handlers and cleaned up parts of the code. +; 6/1/93 dwc Fix init code, add code to wait for MACE transmit status valid +; to work around MACE's not returning it in a timely manner. +; 5/27/93 dwc Added work-around code to wait for AMIC to finish writing a +; packet into the receive DMA buffer before handling it. +; 5/25/93 dwc Cleaned uo for Alpha. Removed some more debug code and hardware +; patches. Added simple work around for AMICs' incrementing the +; head pointer before it has finished writing the packet into the +; DMA buffer. This is a kluge, but it is the fastest one I +; tried, and throws away the fewest packets. +; 5/4/93 dwc Added debug code to work around AMIC's returning FF's on the +; first read. Added test for EVT1/EVT2. +; 4/6/93 dwc Updated for level #4 DMA interrupts. +; 3/24/93 dwc Remove obsolete code and added code to try to recover from +; lowered interrupt level during packet handling. +; 3/5/93 dwc Removed some more debugging and obsolete code and comments. +; 2/25/93 dwc Enabled receive, removed some debug code and obsolete routines. +; 2/24/93 dwc Cleaned up transmit, disabled receive for PDM D5 ROM build. +; 11/30/92 dwc Moved INTLockOut, DMALockOut to PDMMaceEqu.a. +; 11/20/92 dwc Convert to PDM. +; +; To Do: Look into AMIC not properly detecting receive overflow (head continues to wrap past +; the tail without error). +; +; Notes: This version supports EVT2 and later machines. +; +; + + + + PRINT OFF + INCLUDE 'SysEqu.a' ; System definitions + INCLUDE 'SysErr.a' ; System errors + INCLUDE 'Traps.a' ; Traps definitions + INCLUDE 'GestaltEqu.a' + INCLUDE 'InternalOnlyEqu.a' ; lowmem globals + INCLUDE 'HardwarePrivateEqu.a' + INCLUDE 'UniversalEqu.a' ; lowmem global records + INCLUDE 'ATalkMacros.a' ; Nifty Macros + INCLUDE 'SysPrivateEqu.a' ; ExpandMem defs + +; Conditional compile equates +BUFDEBUG EQU 0 +DEBUG EQU 0 +PROM EQU 0 +Logging EQU 1 +SUPPORTS_OLD_HW EQU 1 +USEDEFERREDTASK EQU 1 + + + PRINT NOGEN,NOMDIR,ON + INCLUDE 'PDMMaceEqu.a' ; Mace definitions + INCLUDE 'AMICEqu.a' ; AMIC definitions + INCLUDE 'ENETEqu.a' ; Driver definitions + INCLUDE 'SNMPLAP.a' ; SNMP definitions + EJECT + + + + +;_______________________________________ +; +; Misc definitions +;_______________________________________ + +OneWdsSz EQU 8 ; single fragment wds size +INTLockOut EQU $0700 ; SR value to disable ALL interrupts +DMALockOut EQU $0400 ; SR value to disable AMIC DMA interrupts +NeedDefer EQU 5 ; bit indicates VM is running + +MACERevA2 EQU $0941 +MACERevB0 EQU $0940 + +MAX_STAT_PEND EQU 1 + + +MaceVars RECORD 0 ; our variables +MACEmem DS.l 1 ; ptr to memory block with recv & xmit buffers +MACEmemSz DS.l 1 ; need size if need to free it +XmitBuffMem DS.l 1 ; xmit buffer mem +DMAPacketPtr DS.l 1 ; ptr to active receive packet in DMA buffer +MACEBase DS.l 1 ; MACE base address +AMICDMABase DS.l 1 ; AMIC DMA base address +DTQE DS.b dtQElSize ; Deferred task queue element +MACEChipID DS.w 1 ; MACE revision + ALIGN 4 + +; ••• parms saved from MaceInit call +RcvRtn DS.l 1 ; users recv rtn +RcvParm DS.l 1 ; users recv rtn parm +XmtDnRtn DS.l 1 ; users xmit completion rtn +XmtDnParm DS.l 1 ; users xmit completion rtn parm +MCfg DS.l 1 ; ptr to MACE config record +Dot3StatPtr DS.l 1 ; ptr to 802.3 statistics counters +LAPMIBStatPtr DS.l 1 ; ptr to LAP MIB statistics counters +OurAddrPtr DS.l 1 ; ptr to ethernet address +MemMove DS.l 1 ; ptr to fast memory move rtn +; ••• end parms + +DeferFlag ds.b 1 ; bit 0 = deferred task installed. +XmitPend ds.b 1 ; <> 0 = # xmits pending +XmitStat ds.b 1 ; <> 0 = # xmit status's pending from mace + + IF SUPPORTS_OLD_HW THEN +BoardFlag ds.b 1 ; 00 = AMIC1-3 + ; 01 = AMIC4 + ENDIF + + ALIGN 4 +DMABufStart DS.l 1 ; logical addr of start of DMA recv buffer +TxBuffPtr0 DS.l 1 ; logical addr of start of DMA xmit buffer0 +TxBuffPtr1 DS.l 1 ; logical addr of start of DMA xmit buffer1 + +XmitRegSet ds.w 1 ; 0 or 1 +ByteCount ds.w 1 ; bytes in current xmit packet + +COLLCnt DS.l 1 ; recv frames with collision error + + ; Transmit Frame Status Register counters +XmtStatINV DS.l 1 ; xmit ints with xmit status invalid +XmtLCOL DS.l 1 ; late collision +XmtRTRYCnt DS.l 1 ; total number of retries + + ; Interrupt Register counter +RCVCOCnt DS.l 1 ; *256 to get # collisions on net +MPCOCnt DS.l 1 ; *256 to get # of missed packets due to + ; RcvOFLO, receiver disabled, or excessive + ; receive frame count (RcvFC) + +LogAddrFltr DS.b 8 ; Copy of MACE Logical Address Filter + ; bit order 63-56, 55-48, ... 7-0 +LAFHashTbl DS.b 64 ; Tbl of counts of number multicasts addresses + +RcvBuffer ds.b 6*256 ; Receive buffer (transfered to from DMA buffer) + + IF Logging THEN +LogPtr ds.l 1 +LogEndPtr ds.l 1 ; ptr to end of log +LogStart ds.l 512*4 ; room for 512 log entries +LogEnd + ENDIF + +MaceVarSz EQU * ; End of variables + ENDR + + +;----------------------------------------------------------------- +; Receive Buffer template +; -ensure 1st one is quad-aligned and all the rest will be +;----------------------------------------------------------------- +RecvBuff Record 0 +MaceStat DS.b 4 ; Recv'd pkt status from Mace + DS.b 4 ; Garbage bytes +Packet DS.b Max_Pkt_Size ; packet data area + EndR + + + + + EJECT + + STRING PASCAL + MACHINE MC68020 + +MaceData PROC + ENTRY MaceVarPtr +MaceVarPtr DC.L 0 ; Contains ptr to my variables + ENDP + + + + +;________________________________________________________________________ +; +; ResetMACE - Reset AMIC & MACE FIFOs and disable recv & xmit paths and reset MACE +; +; Call: A2 - drvr vars +; +; Return: none +; +; Destroys: A1,D0,D1 +; +;________________________________________________________________________ + +ResetMACE PROC EXPORT + WITH MACERegs,MaceVars + +; reset & disable MACE -> AMIC receive path + MoveA.l MACEBase(A2), A0 ; A0-> base address of MACE regs + MoveA.l AMICDMABase(A2), A1 ; A1-> base address of AMIC regs + + Move.b #0, MACE_MAC_CNFG(A0) ; Disable MACE recv, xmit, et. al. + nop + Move.b MACE_FIFO_CNFG(A0), D0 ; Get current FIFO config + OrI.b #(1< my variables +; +; Return: +; none +; +; Uses: +; A1, D0 +; +; The LAF can not be updated while MACE recv is enabled. Disable MACE pkt +; reception. If frames in MACE Recv FIFO, reset MACE Recv FIFO (possible pkt +; loss), flush AMIC recv FIFO, and reprime affected DMA Reg. Set. Finally, +; update the LAF. +;________________________________________________________________________ + +WriteLAF PROC + WITH MACERegs,MaceVars + MoveA.l MACEBase(A2), A1 + + Move.b MACE_MAC_CNFG(A1), -(SP) ; Save current config + + Move.b #(1< copy of logical address filter + Move.b #(1< 6 bit hash into LAF + AddQ.b #1, (LAFHashTbl,A2,D0) ; Inc. # of multi's with this hash + CmpI.b #1, (LAFHashTbl,A2,D0) ; Multiaddr hash bit already in LAF? + Bhi @bye ; yes, do nothing + + Lea LogAddrFltr(A2), A0 ; A0-> copy of log. addr. filter + Cmp.b #31, D0 ; Hash > 31? + Bhi.s @b63to32 ; yes + Move.l 4(A0), D1 ; no, get LAF bits 31-0 + BSet.l D0, D1 ; Is this hash bit already set? + Bne @bye ; yes, nothing to do + Move.l D1, 4(A0) ; Save modified LAF bits 31-0 + Bra.s @doit + +@b63to32 Sub.b #32, D0 ; Convert hash for use on LAF bits 63-32 + Move.l (A0), D1 ; Get LAF bits 63-32 + BSet.l D0, D1 ; Is this hash bit already set? + Bne @bye ; yes, nothing to do + Move.l D1, (A0) ; Save modified LAF bits 63-32 + +@doit Bsr WriteLAF ; Write the new LAF + +@bye Move.l (SP)+, A2 ; Restore used C regs + Rts + ENDP + EJECT + +;___________________________________________________________________________ +; +; MaceDelMulti - Delete a multicast address HASH from the LAF +; +; Call: +; D1 = first two bytes of address +; D3 = last four bytes of address +; +; Return: +; none +; +; Computes the hash for this multicast address and decrements the LAF +; Table hash count for the given Multicast address. If new hash count = 0, +; clears appropriate bit in MACE LAF. +; Depends on caller to ensure not called for a multicast's hash that hasn't +; already been inc'd in LAFHashTbl. +;___________________________________________________________________________ + +MaceDelMulti PROC EXPORT + WITH MACERegs,MaceVars + + Move.l A2, -(SP) ; Save used C regs + MoveA.l MaceVarPtr, A2 ; Get ptr to my vars + + Bsr DoCRC ; D0-> 6 bit hash into LAF + SubQ.b #1, (LAFHashTbl,A2,D0) ; Dec. # of multi's with this hash + Bne @bye ; Do nothing if hash table cnt non-zero + + ; Clear this bit in LAF since no other + ; multiaddr's hash to this bit + Lea LogAddrFltr(A2), A0 ; A0-> copy of log. addr. filter + Cmp.b #31, D0 ; Hash > 31? + Bhi.s @b63to32 ; yes + Move.l 4(A0), D1 ; no, get LAF bits 31-0 + BClr.l D0, D1 ; Clear this hash bit + IF DEBUG THEN + Beq @huh ; if LAFHashTbl correct, D1 should + ELSE ; have D0 bit set! + Beq @bye ; do nothing hash bit already clear! + ENDIF + Move.l D1, 4(A0) ; Save modified LAF bits 31-0 + Bra.s @doit + +@b63to32 Sub.b #32, D0 ; Convert hash for use on LAF bits 63-32 + Move.l (A0), D1 ; Get LAF bits 63-32 + BClr.l D0, D1 ; Clear this hash bit + IF DEBUG THEN + Beq @huh ; if LAFHashTbl correct, D1 should + ELSE ; have D0 bit set! + Beq @bye ; do nothing hash bit already clear! + ENDIF + Move.l D1, (A0) ; Save modified LAF bits 63-32 + +@doit Bsr WriteLAF ; Write the new LAF + +@bye Move.l (SP)+, A2 ; Restore used C regs + Rts + + IF DEBUG THEN +@huh _Debugger ; nothing to do 'cause hash bit + Bra.s @bye ; was already clear + ENDIF + + ENDP + EJECT + +;___________________________________________________________________________ +; +; PrimeXmitRS - Prime Reg Set with transmit packet info. +; +; Call: +; 4(SP) - xmit buffer ptr +; A2 - our vars +; +; Return: +; If xmit register sets are full, return CC==NE; else, CC==EQ. +; Notes: +; Called both on normal writes AND write completion (interrupt level 4) +;___________________________________________________________________________ + +PrimeXmitRS PROC + IMPORT AddToLog + +XmitPrm RECORD 4 +XmitPtr DS.l 1 ; Transmit buffer ptr +ParmSz EQU * + ENDR + + WITH MACERegs,MaceVars,LAPMIBStats + + addq.b #1,XmitStat(a2) ; count this packet as waiting to go out + + move.l AMICDMABase(A2),A3 ; Get AMIC DMA base addr + + Move.b AMIC_DMA_XMIT_CNTL(A3), D1 ; get xmit status + BTst #DMARUN, D1 ; DMA enabled already? + Beq @noten ; No, don't reset it + + move.b #XMTMSK, AMIC_DMA_XMIT_CNTL(A3) ; Clear IF & DMARUN + nop + + +@noten moveq #0, D0 + Move.w ByteCount(A2), D0 ; Get DMA byte count (word) + move.w XmitRegSet(a2),d1 ; get register set + lsl #4,d1 ; * 16 for proper reg offset + + IF Logging THEN + move.l #'DMA ',-(sp) + move.l #'SEND',-(sp) + move.l d0,-(sp) + move.w XmitPend(a2),(sp) + bsr AddToLog + add.w #12,sp + ENDIF + + Move.b D0, (AMIC_DMA_XMIT_CNT0L,A3,d1.w) ; Set DMA byte count (LOW) + nop ; Allow it to complete + ror.w #8,D0 ; Get HIGH count into lower byte + Move.b D0, (AMIC_DMA_XMIT_CNT0H,A3,d1.w) ; Set DMA byte count (HIGH) + nop ; Allow it to complete + + +@aroundone rol.w #8,D0 ; Get HIGH count back into upper byte + + Move.l XmitPrm.XmitPtr(SP),a1 ; a1 - xmit buffer ptr + BTst #0,(A1) ; xmiting a multi/bcast? + MoveA.l LAPMIBStatPtr(A2), A1 + Bne.s @30 + AddQ.l #1, ifOutUcastPkts(A1) ; inc. non-multi/bcast cntr + Bra.s @31 +@30 AddQ.l #1, ifOutNUcastPkts(A1) ; inc. multi/bcast cntr +@31 Add.l D0, ifOutOctets(A1) ; inc. sent octet cntr + + + Move.b #XMTDMA, AMIC_DMA_XMIT_CNTL(A3) ; Clear IF & enable xmit DMA + nop ; Allow it to complete + + MoveQ #0, D0 ; Set CC's + Rts ; Return + + ENDP + EJECT + + + +;___________________________________________________________________________ +; +; MaceXmit - Calls PrimeXmitRS to prime Reg Set with transmit packet info. +; If xmit register sets are full, put xmit buffer ptr on tail +; of xmit InUse queue. +; +; Call: +; 4(SP) - WDS ptr +; +; Return: +; D0 = error code; nobuff - temporarily out of xmit buffers +; eLenErr - sum of data in WDS > max. pkt size +; noErr - primed reg set with xmit pkt or put pkt +; on xmit InUse queue +; Notes: +; Called both on normal writes AND write completion (interrupt level 4). Due to +; a hardware problem in Curio (it seems), you cannot DMA another packet into +; MACE before a pending Xmit status is read, or the transmitter locks up. Hence +; the code below will return a 'nobuff' error if there is an outstanding status. +; If the part is fixed, then by modifying a constant, the code will allow 2 or more +; packets to go out before returning the error. +;___________________________________________________________________________ + +MaceXmit PROC EXPORT + +WDSPrm RECORD 4 ; Return address +WDSPtr DS.l 1 ; Write Data Structure ptr +ParmSz EQU * + ENDR + + IMPORT AddToLog + WITH MACERegs,MaceVars + + Move.l WDSPrm.WDSPtr(SP), D2 ; Get WDS ptr + movem.l A0-A4/D1-D4,-(SP) ; save non-scratch regs + + MoveA.l MaceVarPtr, A2 ; Get ptr to my vars + + Move SR,-(SP) ; ••`Save interrupt mask level + OrI #DMALockOut, SR ; Disable DMA ints. + + move.l AMICDMABase(A2),a0 ; Get AMIC DMA base addr + Move.b AMIC_DMA_XMIT_CNTL(A0),d0 ; Which reg set is available? + andi.b #(1< WDS +@1 + MoveQ #0,D0 + Move.w (A4), D0 ; get this wds entry length + Beq.s @2 ; all done + AddQ.w #6, A4 ; inc to next wds entry length + Add.w D0,ByteCount(A2) ; sum the length + Bra.s @1 ; look for more +@2 + Move.w ByteCount(A2),D1 ; get single fragment length + Sub.w #EHdrSize,D1 ; Subtract out header bytes + Cmp.w #EMaxDataSz,D1 ; Check the data's length + Bls.s @cont ; Branch if ok + +;------------------------------------------ +; Length error, relink buffer onto free list and return error +;------------------------------------------ + MoveA.l (SP)+,A1 ; ••Pop buff ptr + + Move (SP)+,sr ; ••Restore int. mask level + Movem.l (SP)+,A0-A4/D1-D4 ; Restore C regs + MoveQ #eLenErr,D0 ; Set length error + Rts ; Return it + + +;------------------------------------------ +; Copy WDS data to our Xmit buffer +;------------------------------------------ +@cont MoveA.l (SP),A1 ; + MoveA.l D2,A4 ; A4-> WDS +@3 + Move.w (A4)+,D0 ; last WDS entry? + Beq.s @4 ; yes, all done + MoveA.l (A4)+,A0 ; get pointer to the data + ; A0->source, A1->dest, D0=len + MoveM.l A1/D0,-(SP) ; save buff ptr and len + Jsr ([MemMove,A2]) ; move the data + MoveM.l (SP)+,A1/D0 + AddA.l D0, A1 ; update buff ptr + Bra.s @3 ; look for more +@4 ; (SP) -> Xmit buffer ptr pushed earlier + Jsr PrimeXmitRS + + AddQ #4,sp ; ••Pop buff ptr + Move (SP)+,SR ; ••Restore int. mask level + Movem.l (SP)+,A0-A4/D1-D4 ; Restore C regs + MoveQ #0, D0 ; Set return code & CC's + Rts ; Return + + ENDP + EJECT + + + + + + + +;___________________________________________________________________________ +; +; MaceRecv - Deferred Task Packet receive routine +; +; Call: a1 - our variables +; +; Return: +; +; Destroys: a0-a1,d0-d1 +; +; Calls: +; Calls user's handler to receive packet. +; +; Notes: +; Installed via DMAInterrupt, called via Deferred Task Mgr. +;___________________________________________________________________________ + +MaceRecv PROC + IMPORT AddToLog,CopyRcvBuffer,InitStatBuf + WITH MACERegs,MaceVars,RecvBuff + WITH Dot3StatsEntry,LAPMIBStats + + + movem.l A2-A6/D2-D4,-(SP) ; save non-scratch regs + move.l a1,a2 ; get ptr to our globals + +@ChkRecv movea.l AMICDMABase(a2),a3 ; get ptr to AMIC + + move.w sr,-(sp) ; •• save sr + ori.w #DMALockOut,sr ; • mask out DMA ints + +;-------------------------------------- +; Here we check for a valid packet in the circular buffer... +;-------------------------------------- +@rcvPcktLoop + moveq #0,d0 + move.b AMIC_DMA_RECV_TAIL(A3),D0 ; Are there packets to process? (should be) + cmp.b AMIC_DMA_RECV_HEAD(A3),D0 ; Get the Head Ptr + bne @gotData + + btst.b #6,AMIC_DMA_RECV_CNTL(a3) ; overrun? + beq @exit + IF Logging THEN + move.b AMIC_DMA_RECV_HEAD(A3),d0 + move.l #'McRv',-(sp) ; push string + move.l #'OVER',-(sp) ; push string + move.l #'RUN ',-(sp) ; push string + bsr AddToLog + add.w #12,sp + ENDIF +@gotData + tst.l DMAPacketPtr(a2) ; did we re-enter?? + bne @exit ; yes, exit for now + + + IF Logging THEN + move.l d0,-(sp) + swap d0 + move.b AMIC_DMA_RECV_HEAD(A3),d0 + move.l #'DMAr',-(sp) ; push string + move.l d0,-(sp) ; push tail/head + + move.l DMABufStart(A2),a0 ; Recv buffer ptr + clr.w d0 + swap d0 + lsl.w #8,d0 + adda.l d0,a0 ; point to start of packet + move.l (a0),-(sp) ; push status/length + + bsr AddToLog + add.w #12,sp + move.l (sp)+,d0 + ENDIF + + move.l DMABufStart(A2),a0 ; Recv buffer ptr + lsl.w #8,d0 ; convert to offset + add.l d0,a0 ; a0=addr of packet + IF SUPPORTS_OLD_HW THEN + tst.b BoardFlag(a2) ; AMIC4? + bgt.s @skipStat ; yes, don't bother with the hack + tst.l (a0) ; • has status been updated? + beq @exit ; • no, not full packet, exit +@skipStat + ENDIF + move.l a0,DMAPacketPtr(a2) ; save ptr, flag we're in use + + move.w (sp)+,sr ; •• restore interrupts + +;-------------------------------------- +; we seem to have a complete packet, get it's status, +; copy DMA buffer to our receive buffer (if status valid), +; and call user with data +;-------------------------------------- + + moveq #0,d1 + move.w (a0),d1 ; Get Status(15-12) & Byte Cnt(11-8,7-0) + move.w d1,d2 ; want Status later + lsr.w #8,d2 ; d2.w=00ss + andi.b #$f0,d2 ; d2.w=00s0 + swap d2 ; d2.l=s000 + move.w 2(a0),d2 ; d2.l=s0cr (Get the Collision & Runt cnts) + swap d2 ; d2.l=crs0 (Coll,Runt,Stat,Null) + andi.w #$0fff,d1 ; remove status bits from byte cnt + + bsr CopyRcvBuffer ; copy the DMA buffer into our receive buffer + + btst.b #6,AMIC_DMA_RECV_CNTL(a3) ; are we in an overrun condition? + beq.s @notOverrun + IF Logging THEN + move.b AMIC_DMA_RECV_HEAD(A3),d0 + move.l #'McR2',-(sp) ; push string + move.l #'OVER',-(sp) ; push string + move.l #'RUN ',-(sp) ; push string + bsr AddToLog + add.w #12,sp + ENDIF + move.b #$4a,AMIC_DMA_RECV_CNTL(a3) ; yes, clear the overrun and turn on DMA +@notOverrun + + MoveA.l LAPMIBStatPtr(A2),A5 ; pt to LAP stats + MoveA.l Dot3StatPtr(A2),A6 ; pt to DOT3 stats + +;----------------------------------------------------------------- +; Retrieve status bytes from beginning of buffer. Each status byte is present in +; the high and low bytes of a word. There are 4 status bytes, so there are 8 bytes +; of status. +;----------------------------------------------------------------- + Add.l d1,ifInOctets(a5) + + Btst #RcvOFLO,d2 ; Overflow Error? + Beq.s @s1 + AddQ.l #1,dot3StatsInternalMacReceiveErrors(a6) + Bra.s @s4 ; + +@s1 AndI.b #(1< + beq.s @skipCnt ; no, don't count it + subq.b #1,XmitStat(a1) ; else, count this frame status as read +@skipCnt + IF Logging THEN + move.l #'MACE',-(sp) + move.l d0,-(sp) ; log interrupt reg + move.b d1,1(sp) ; and frame status + move.l XmitPend(a1),-(sp) + move.b MACE_FIFO_FRM_CNT(A0),2(sp) ; and frame counts + bsr AddToLog + add.w #12,sp + ENDIF + BTst #XMTSV, D1 ; Is status valid? + Bne.s @10 ; yes, continue + AddQ.l #1, XmtStatINV(A1) + Bra @xmit + +@10 Move.b D1, -(SP) ; save D1 + AndI.b #(1<0 + Beq.s @mpci ; no + AddQ.l #1, RCVCOCnt(A1) + +@mpci BTst #MPCO, D0 ; Missed packet count interrupt? This int. + ; indicates MPC reg. rolled over from 255->0 + Beq.s @cerr ; no + AddQ.l #1, MPCOCnt(A1) + Add.l #256, ifInErrors(A2) + + +@cerr BTst #CERR, D0 ; Collision error interrupt? + Beq.s @babl ; no + AddQ.l #1, dot3StatsSQETestErrors(A3) + AddQ.l #1, ifOutErrors(A2) + +@babl BTst #BABL, D0 ; Babble error interrupt? + Beq.s @chkAgain ; no + AddQ.l #1, dot3StatsFrameTooLongs(A3) + AddQ.l #1, ifOutErrors(A2) + +@chkAgain bra @more + + ENDP + + + + +;___________________________________________________________________________ +; +; Routine: CopyRcvBuffer +; +; Inputs: d1 - packet length +; d2 - packet status +; a0 - ptr to start of packet in DMA buffer +; a2 - globals +; a2 - AMIC base +; Outputs: RcvBuffer - contains the received packet +; Destroys: a1,d3 +; +; Calls: +; +; Function: Copyies the packet in DMA buffer to our receive buffer, bumping +; the tail pointer as we go. +;___________________________________________________________________________ +CopyRcvBuffer PROC EXPORT + WITH MACERegs,MaceVars + + move.l d1,-(sp) ; save length + tst.b d2 ; check status, is length valid? + bne.s @copyExit + + add.w #$00ff+8,d1 ; compute the rounded up length in pages + andi.w #$ff00,d1 + lsr.w #8,d1 ; # of pages (256 bytes) + subq.w #1,d1 ; adjust for dbra + blt.s @copyExit + + moveq #0,d3 + move.b AMIC_DMA_RECV_TAIL(a3),d3 ; get tail ptr + move.l DMAPacketPtr(a2),a0 ; get buf ptr + lea RcvBuffer(a2),a1 ; get ptr to our receive buffer + +@clrLoop move.l #$0100,d0 + _BlockMove ; copy next page to user buffer + add.w #$0100,a1 ; point to next page + clr.l (a0) ; clear out it's length/status ••hardware fix + add.w #$0100,a0 ; point to next status + addq.b #1,d3 ; bump tail ptr + cmpi.b #$c0,d3 ; at end of buffer? + blo.s @update ; no, continue + moveq #0,d3 ; yes, reset to starting page + move.l DMABufStart(a2),a0 ; wrap length/status ptr to start +@update move.b d3,AMIC_DMA_RECV_TAIL(a3) ; update tail ptr + nop + cmp.b AMIC_DMA_RECV_HEAD(a3),d3 ; have we caught up with head (bad length)? + dbeq d1,@clrLoop ; and repeat for next page + +@copyExit move.l (sp)+,d1 + rts + + ENDP + + + + EJECT +;___________________________________________________________________________ +; +; DMAIntHandler - Process DMA Interrupt from AMIC +; +; Call: A1 - our variables (reference constant from dispatcher) +; +; Regs: A2 - our variables +; A3 - Receive or Transmit DMA Channel base address +; D4.B - Register Set offset, 0 or $10 +; +; Calls: PrimeRecv - reprime a Recv DMA reg set +; MaceXmitDone - read Xmit status and reprime Xmit DMA regs if needed +; +; RePrime Receive and Transmit Register Sets. Install Deferred Task to +; process Received Packets and Transmit Completions. +;___________________________________________________________________________ + +DMAIntHandler PROC + IMPORT AddToLog,InitStatBuf,CopyRcvBuffer + WITH MACERegs,MaceVars + + Move.l D4, -(SP) ; Save non-interrupt regs used + Move.l A1,A2 ; A2 -> our variables + +;-------------------------------------- +; Check for packet in Receive DMA Channel +;-------------------------------------- +ChkRecv MoveA.l AMICDMABase(a2),a3 + Move.b AMIC_DMA_RECV_CNTL(a3),d0 ; Get receive status, int pending? + bpl @ChkXmitDone ; no, check xmit channel + + btst #6,d0 ; is this an overrun? + beq.s @notOVRN ; no, continue + IF Logging THEN + move.b AMIC_DMA_RECV_HEAD(A3),d0 + move.l #'RECV',-(sp) ; push string + move.l #'OVER',-(sp) ; push string + move.l #'RUN ',-(sp) ; push string + bsr AddToLog + add.w #12,sp + ENDIF + + IF DEBUG THEN + _debugger + ENDIF + Move.b #$80, AMIC_DMA_RECV_CNTL(A3) ; Clear the interrupt + bra.s @2 +@notOVRN Move.b #RCVMSK, AMIC_DMA_RECV_CNTL(A3) ; Clear the interrupt and turn on DMA +@2 + nop + + IF Logging THEN + move.b AMIC_DMA_RECV_HEAD(A3),d0 + move.l #'DMAr',-(sp) ; push string + move.l #'Int ',-(sp) ; push string + move.l DeferFlag(a2),-(sp) + bsr AddToLog + add.w #12,sp + ENDIF + + bset #0,DeferFlag(a2) ; we're installing deferred task + bne.s @ChkXmitDone ; skip if already installed + + IF USEDEFERREDTASK THEN + lea DTQE(a2),a0 ; A0->deferred task queue element + movea.l JDTInstall,a1 + jsr (a1) ; install deferred task + ELSE + move.l a2,a1 ; a1 = globals for deferred tasks + bsr MaceRecv + ENDIF + +;--------------------------------------------------------------- +; Check for Transmit Completion Interrupt +;--------------------------------------------------------------- +@ChkXmitDone + move.b AMIC_DMA_XMIT_CNTL(a3),d0 ; AMIC xmit control/status + bpl @doneAMICInt ; exit if no xmit DMA int + + IF Logging THEN + move.l #'DMA ',-(sp) + move.l #'DONE',-(sp) + move.l d0,-(sp) + bsr AddToLog + add.w #12,sp + ENDIF + + Move.b #XMTMSK, AMIC_DMA_XMIT_CNTL(A3) ; clear the interrupt + nop + +@doneAMICInt + Move.l (SP)+, D4 + + rts ; Return from DMAInterrupt + + ENDP + + + + + + EJECT +;___________________________________________________________________________ +; +; MaceInit - Get var and DMA memory, then initialize DMA Register Sets and +; MACE chip +; +; Call: following record on stack: +; +; MACEInitParms RECORD 0 +; RecvRtn DS.l 1 ; address of Ethernet receive routine +; RecvPrms DS.l 1 ; parms to pass @ receive +; XmitRtn DS.l 1 ; address of Ethernet xmit complete routine +; XmitPrms DS.l 1 ; parms to pass @ xmit complete +; MACECfgPtr DS.l 1 ; ptr to MACE config record +; Dot3NetStats DS.l 1 ; ptr to 802.3 statistics array +; LAPMIBNetStats DS.l 1 ; ptr to LAP MIB statistics array +; EnetAddr DS.l 1 ; ptr to ethernet address +; FastMoveRtn DS.l 1 ; ->proc to move memory FAST +; IPSize EQU * +; +; Return: +; D0 = openErr (-23) or mFulErr (-41) +;___________________________________________________________________________ + +MaceInit PROC EXPORT + +parms RECORD {A6Link} +LocalSize EQU * +A6Link DS.l 2 ; link and return address +initp DS MACEInitParms ; parameters passed to us + ENDR + + IMPORT TranslateAddress, GetMemory, FreeMemory, AddToLog, InitStatBuf + WITH parms,initp,MACERegs,MaceVars + + Link A6,#LocalSize ; Save A6 + MoveM.l A2-A4/D3-D5,-(SP) ; Save regs + + Move.l #MaceVarSz, -(SP) ; requested memory size + Move #0, -(SP) ; do NOT want memory locked, + ; contiguous, and non-cacheable + Lea GetMemory, A0 + Jsr (A0) ; get memory in D0 + AddQ #6, SP ; pop parms + Blt @InitError ; bra if CC indicate error + + Lea MaceVarPtr, A3 + Move.l A0, (A3) ; Save ptr to my vars + MoveA.l A0, A2 + + + IF SUPPORTS_OLD_HW THEN + clr.b BoardFlag(a2) ; init to AMIC1-3 + move.w sr,-(sp) ;•• + ori.w #$0700,sr ; mask ints during this + lea $50f14010,a0 + move.b (a0),d1 + move.b d1,-(sp) ;•• read AMIC, save old value + btst.l #3,d1 ; check bit 3 + bne.s @amic4 ; if set, must be amic4 + ori.b #(1<<3),d1 ; clear, get set mask + move.b d1,(a0) ; try setting bit 3 + nop + btst.b #3,(a0) ; did it set? + beq.s @hwChkDone ; no, must be AMIC1-3 +@amic4 addq.b #1,BoardFlag(a2) ; yes, 01=AMIC4 +@hwChkDone move.b (sp)+,(a0) ; •• restore AMIC + move.w (sp)+,sr ; •• restore SR + ENDIF + + IF Logging THEN + lea LogStart(a2),a0 + move.l a0,LogPtr(a2) + lea LogEnd(a2),a0 + move.l a0,LogEndPtr(a2) + + move.l #'STRT',-(sp) + move.l #'ENET',-(sp) + clr.l -(sp) + bsr AddToLog + add.w #12,sp + ENDIF + + Move.l UnivInfoPtr, A0 ; get ptr to ProductInfo + Add.l ProductInfo.DecoderInfoPtr(A0), A0 ; point to the base address table + Move.l DecoderInfo.MACEAddr(A0), MACEBase(A2) ; Save the MACE base address + Move.l DecoderInfo.AMICAddr(A0), AMICDMABase(A2) ; Save the AMIC base address + + Move.l RecvRtn(A6), RcvRtn(A2) ; save addr of recv rtn + Move.l RecvPrms(A6), RcvParm(A2) ; save parm for recv rtn + + Move.l XmitRtn(A6), XmtDnRtn(A2) ; save addr of xmit compl rtn + Move.l XmitPrms(A6), XmtDnParm(A2) ; save parm for xmit compl rtn + + Move.l Dot3NetStats(A6), Dot3StatPtr(A2) + Move.l LAPMIBNetStats(A6), LAPMIBStatPtr(A2) + + Move.l EnetAddr(A6), OurAddrPtr(A2) ; save ptr to our Ethernet address + Move.l FastMoveRtn(A6), MemMove(A2) ; save addr of fast mem move rtn + + +;------------------------------------------------------------------------------------- +; Get the buffer addresses from the AMIC base address register + offsets +;------------------------------------------------------------------------------------- + lea $61000000,a1 ; Get the buffer base address + Move.l a1,DMABufStart(A2) ; Set Recv buffer pointer + + adda.l #XMIT_BUFF0,a1 ; D0 = Recv ptr + xmit buff offset + Move.l a1,TxBuffPtr0(A2) ; Set 1st Xmit buffer pointer + adda.w #2048,a1 + Move.l a1,TxBuffPtr1(A2) ; Set 2nd Xmit buffer pointer + + IF SUPPORTS_OLD_HW THEN + tst.b BoardFlag(a2) ; AMIC4? + bgt.s @skipStat ; yes, don't bother with the hack + bsr InitStatBuf ; •• hack to init status words at each page boundary +@skipStat + ENDIF +;------------------------------------------------------------------------------------- +; Install MACE Recv DMA channel Deferred Task, called by MACE_RECVhndlr +;------------------------------------------------------------------------------------- + Move.w #dtQType, DTQE+qType(A2) ; Set Deferred Task queue type + Lea MaceRecv,A1 + Move.l A1, DTQE+dtAddr(A2) ; Set address of DT, called by slot int. hndlr. + Move.l A2, DTQE+dtParm(A2) ; Set variable pointer to MACE vars + +;------------------------------------------------------------------------------------- +; MACE Chip initialization +;------------------------------------------------------------------------------------- + MoveA.l MACEBase(A2), A0 ; A0-> base address of Mace regs + + Bsr ResetMACE ; Reset MACE chip and AMIC DMA chnls + + Move.b #(1< + ; Enable Retry, FCS, Auto Padding + Move.b #$00, MACE_RX_FRM_CNTRL(A0) ; •••Recv Control -> + ; Disable Auto Pad Stripping + ; Set up FIFOs' configuration + Move.b #TFW16+(1< Mace Phy Address Reg + MoveA.l OurAddrPtr(A2), A1 ; A1-> Our node address + Move.b (A1)+, (A0) ; Move addr byte0 to Mace reg + nop ; Allow it to complete + Move.b (A1)+, (A0) ; Move addr byte1 to Mace reg + nop ; Allow it to complete + Move.b (A1)+, (A0) ; Move addr byte2 to Mace reg + nop ; Allow it to complete + Move.b (A1)+, (A0) ; Move addr byte3 to Mace reg + nop ; Allow it to complete + Move.b (A1)+, (A0) ; Move addr byte4 to Mace reg + nop ; Allow it to complete + Move.b (A1), (A0) ; Move addr byte5 to Mace reg + nop ; Allow it to complete + MoveA.l MACEBase(A2), A0 ; Get back base address of Mace regs + + CmpI #MACERevA2, MACEChipID(A2) ;???? temp code to check MACE chip id + Beq.s @skip2 ; MACE in Rev B0 Curio has new bit in IAC! + Move.b #(1< Mace Phy Address Reg + MoveQ #7, D0 +@laf Move.b #0, (A1) ; CLEAR all bits in Log Addr Filter + nop ; Allow it to complete + DBra D0, @laf + + + MoveA.l AMICDMABase(A2), A3 ; Get the AMIC base address + Move.b #(1<Get the AMIC base address + Move.b #XMTMSK, AMIC_DMA_XMIT_CNTL(A3) ; Clear IF to be safe + nop ; Allow it to complete + Move.b #RCVMSK, AMIC_DMA_RECV_CNTL(A3) ; Clear IF & enable recv DMA + nop ; Allow it to complete + +; Be sure the Tail Pointer starts out a 0 + Move.b #0, AMIC_DMA_RECV_TAIL(A3) ; Start at the beginning + nop ; Allow it to complete + +;------------------------------------------------------------ +; Install Enet interrupt handlers +;------------------------------------------------------------ + + with ExpandMemRec, DMADispGlobals + + movea.l ([ExpandMem],emDMADispatchGlobals), A0 + + ; Install MACE (level 3) interrupt handler + + lea MaceInterrupt, A1 + move.l A1, maceVector(A0) ; register the handler in its designated entry + + ; Install AMIC DMA (level 4) interrupt handlers + + lea DMAIntHandler, A1 + moveq #hwAmicETX, D0 + move.l A1, ddVector0(A0,D0.l*8) ; register transmit DMA handler + move.l A2, ddRefCon0(A0,D0.l*8) ; register globals pointer as reference constant + + moveq #hwAmicERX, D0 + move.l A1, ddVector0(A0,D0.l*8) ; register receive DMA handler + move.l A2, ddRefCon0(A0,D0.l*8) ; register globals pointer as reference constant + + endwith + +;------------------------------------------------------------ +; Enable MACE +;------------------------------------------------------------ + Move.l MACEBase(A2), A0 ; Base address of Mace + Move.b #(1< 7/1/93 GMR Make the receive handler ignore the packet if there was a Mace +; overrun error. +; 6/10/93 GMR Changed the handling transmit deferrals. +; 6/2/93 GMR Minor changes to the receive handler. +; 5/27/93 dwc Added support for AMIC work-around code. +; 5/25/93 dwc Clean up for Alpha. +; 5/4/93 dwc Added debug code to work around AMIC's returning FF's on the +; first read and removed some obsolete code and equates. +; 4/6/93 dwc Updated for level #4 DMA interrupts. +; 3/24/93 dwc Remove obsolete code and added code to try to recover from +; lowered interrupt level during packet handling. +; 3/5/93 dwc Removed some obsolete code and comments. +; 2/25/93 dwc Enabled receive and loopbacktests. +; 2/24/93 dwc Removed some debug code and checked in for the PDM D5 ROM build. +; 2/4/93 dwc first checked in +; +; To Do: +; +; Replace BIT24 with Supports24Bit +; Remove some unused equates +; + + + PRINT OFF + LOAD 'StandardEqu.d' + INCLUDE 'Slots.a' ; Slot interrupt equates + INCLUDE 'GestaltEqu.a' + INCLUDE 'HardwarePrivateEqu.a' + INCLUDE 'UniversalEqu.a' ; lowmem global records + INCLUDE 'ATalkMacros.a' ; Nifty Macros + +; Conditional compile equates +COUNTERS EQU 0 +BUFDEBUG EQU 0 +BIT24 EQU 0 ; SuperMario always 32-bit +DEBUG EQU 0 +PROM EQU 0 ; Promiscous mode support +Logging EQU 1 ; + + PRINT NOGEN,NOMDIR,ON + INCLUDE 'PDMMaceEqu.a' ; Mace definitions + INCLUDE 'AMICEqu.a' ; AMIC definitions + INCLUDE 'ENETEqu.a' ; Driver definitions + INCLUDE 'SNMPLAP.a' ; SNMP definitions + EJECT + +NumTxBuffers EQU 8 ; "optimal" number of xmit buffers +NumRxBuffers EQU 16 ; "optimal" number of recv buffers +NumRxChains EQU 4 ; "optimal" number of recv buffer chains + +OurV RECORD 0 ; our variables +OurDCE DS.l 1 ; Offset to our DCE pointer in variables +MACEBase DS.l 1 ; MACE base address + IF PROM THEN +PromiscRHA DS.l 1 ; Contains status lw when in promiscuous mode + ; ••• WARNING: do not separate from RHA! + ENDIF +RHA DS.b EHdrSize ; Read Header Area +;___________________________________________________________________________ +; +; The LAP protocol handler table starts here. Format: +; .BYTE InUseFlag1,..., InUseFlagN ; Entry in use flag +; .wORD ProtCode1, ..., ProtCodeN ; Protocol type codes +; .lONG PHAddr1, ..., PHAddrN ; Protocol handler addresses +; .lONG RdQueueHd1, ..., RdQueueHdN ; Read queue heads +;___________________________________________________________________________ +LAPTblSz EQU 16 ; Size of LAP protocol handler table (even) +InUseFlag DS.b LAPTblSz ; Entry in use flag +Protocols DS.w LAPTblSz ; List of active protocols +Handlers DS.l LAPTblSz ; List of handler addresses +RdQueueHd DS.l LAPTblSz ; Read queue heads +LAPTblEnd EQU * ; End of LAP table + +;___________________________________________________________________________ +; +; Multicast address table. Entry format: +; Ethernet address (6 bytes) +; Use count (1 byte). Zero means entry free. +; Unused (1 byte) +;___________________________________________________________________________ + +MTblSz EQU 16 ; Size (in entries) of multicast address table +MEntrySz EQU 8 ; Size of an entry (power of 2) +MUseCount EQU EAddrSz ; Offset to use count in entry + + ALIGN 4 +MultiCTbl DS.b MTblSz*MEntrySz ; A list of valid addresses + ALIGN 4 +XmitWait DS.b 1 ; non-zero = DoWrite waiting for buffers + IF PROM THEN +Promiscflg DS.b 1 ; non-zero = Promiscuous operation mode + ENDIF +deferCtl DS.b 1 ; non-zero = deferring control call + ALIGN 2 +VBLQEL DS.b 14 ; VBL for control call deferrals + ALIGN 4 + IF BIT24 THEN +AddrMask DS.l 1 ; 32 bit mask for addresses + ENDIF +MemMove DS.l 1 ; trap address of block move + IF COUNTERS THEN +EtherRcvCnt DS.l 1 ; # of times Deferred Recv Task called +XmitPend DS.l 1 ; Cnt of DoWrite calls from TimeMgr task + ENDIF + IF BUFDEBUG THEN +XmtDnActive DS.l 1 + ENDIF +MCfg DS MACECfg ; MACE config data from config rsrc + ALIGN 4 +InfoStart EQU * ; Old "GetInfo" network statistics start +OurAddr DS.b EAddrSz ; Our Ethernet address + DS.l 3 ; fill for compatibility with old getinfo +EtherStats DS NetStats +InfoEnd EQU * ; End of returned info +MultiRecvd DS.l 1 ; # of multicast pkts received +BcastRecvd DS.l 1 ; # of broadcast pkts received +; SNMP vars +LAPStats DS LAPMIBStats ; SNMP MIB stats for any link access protocol +Dt3Entry DS Dot3Entry ; SNMP status info and control vars +Dt3Stats DS Dot3StatsEntry ; SNMP stats for an 802.3 link +OurVarSz EQU * ; End of variables + ENDR + +;_______________________________________ +; +; Other definitions +;_______________________________________ + +AMaxDataSz EQU 768-EHdrSize ; Maximum data size for AppleTalk mode + +INTLockOut EQU $0700 ; SR value to disable ALL interrupts +DMALockOut EQU $0400 ; SR value to disable PSC DMA interrupts + +BlockMoveTrap EQU $A02E ; trap value for _BlockMove + +ORBuffrsrc EQU 'ebfr' ; res type for buffer count override + + IF PROM THEN +Promiscuous EQU 1 ; Bit #1 of Open()'s paramblk->ioFlags + ENDIF + EJECT + + EJECT + +ENETDriver MAIN EXPORT + STRING PASCAL + MACHINE MC68020 + + EXPORT TranslateAddress, GetMemory, FreeMemory + IMPORT MACEInit,MACEXmit,MACEAddMulti,MACEDelMulti,MACEHalt,NormAddr + IMPORT LOOPBACKTEST,MACESetProm,MACEXmitProm, AddToLog + + WITH MACERegs,OurV + WITH LAPMIBStats,Dot3StatsEntry,Dot3Entry + +; ***************************************** +; * * +; * Start of ENET driver * +; * * +; ***************************************** +ENET +; +; Driver header +; + DC.w $4400 ; Control, Locked, no Goodbye + DC.w 0,0 ; No time, no events + DC.w 0 ; No menu + +; +; Entry points offset table +; + DC.w Open-ENET + DC.w AnRts-ENET + DC.w Control-ENET + DC.w AnRts-ENET + DC.w Close-ENET + + DC.w '.ENET' ; Driver name + ALIGN 2 + + INCLUDE 'VersionPDMMaceEnet.a' + +;________________________________________________________________________ +; +; Open - initialize the ENET driver +; +; Call: +; D0 = 0 +; A0 -> queue element +; A1 -> DCE +; +; Return: +; D0 = 0, no error +; D0 != 0, if error +;________________________________________________________________________ + +OpenRec RECORD {A6Link} +LinkSz EQU * +pbblkptr DS.l 1 ; copy of parameter block ptr +A6Link DS.l 2 ; link and return addr + ENDR +Open + + Link A6,#OpenRec.LinkSz ; mark the stack for easy exit + + Move.l A0,OpenRec.pbblkptr(A6) ; Save paramblock ptr for later access + + Move.l #gestaltVMAttr,D0 ; see if VM is running + _Gestalt + Bne.s @noVM ; it is'nt if call failed + Move.l A0,D0 + Btst #gestaltVMPresent,D0 + Beq.s @noVM ; zero result means no VM running + BSet #VMImmuneBit,dCtlFlags+1(A1) ; tell VM to leave our calls alone +@noVM + Lea OurVarPtr,A3 ; A3 -> variable pointer +; +; Allocate our variables +; + Move.l #OurVarSz,D0 ; variables size + _NewPtr ,SYS,CLEAR ; get memory for our variables + Bne OpenError + + Move.l A0,(A3) ; save variable pointer + MoveA.l A0, A2 ; A2 -> our vars + + Move.b MaceEnet,DCtlQueue+1(A1) ; Version number goes here + Move.l A1,OurDCE(A2) ; Save our DCE address + + Move.w #BlockMoveTrap,D0 + _GetTrapAddress + Move.l A0,MemMove(A2) ; save trap address in our vars + +; +; Look for an alternate address resource for this slot +; + SubQ #4,SP ; Make room for handle + Move.l #EAddrRType,-(SP) ; Push resource type + MoveQ #0,D0 ; Clear out D0 + Move.b dCtlSlot(A1),D0 ; Get the slot number + Move D0,-(SP) ; Set slot number as resource ID + _GetResource ; Get it + MoveQ #-1, D0 ; Assume error + Move.l (SP)+,D1 ; D1 = handle to resource + Beq @30 ; Do nothing, if not there + Move.l D1,A0 ; A0 = handle to resource + Move.l (A0),A0 ; A0 = pointer to resource + BTst #0,(A0) ; Make sure it's not a multicast addr + Bne OpenError ; EXIT, if it is + Move.l (A0)+,OurAddr(A2) ; Move four bytes to our address + Move (A0)+,OurAddr+4(A2) ; Move the last two bytes +@30 + + Clr.l -(SP) ; room for result + Move.l #ORBuffrsrc,-(SP) + MoveQ #0,D0 ; Clear out D0 + Move.b dCtlSlot(A1),D0 + Move D0,-(SP) ; Set slot number as resource ID + _GetResource + Move.l (SP)+,D0 + Beq.s @31 ; no buff override rsrc, branch + MoveA.l D0,A0 + MoveA.l (A0),A0 + +@31 + +; +; Determine our Ethernet Address from Address Prom, if address not provided +; via EAddrRType resource +; + Lea OurAddr(A2),A1 + Tst.l (A1) + Bne.s @45 ; already have an address + Tst.w 4(A1) + Bne.s @45 ; already have an address + + Move.l D3, -(SP) + Lea AddrPROM, A0 ; Address of Ethernet Address PROM + MoveQ #0, D1 ; Setup to checksum the PROM address + MoveQ #7, D0 ; Do 8 bytes + MoveQ #1, D3 ; Offset to address byte + ; Checksum the addresss PROM +@Xor Move.b (A0,D3.w), D2 ; get byte to XOR + Eor.b D2, D1 + AddI #$10, D3 ; Inc offset to next byte + DBra D0, @Xor ; do them all + Move.l (SP)+, D3 + CmpI.b #$FF, D1 ; end result should be $FF + Bne OpenError ; return with generic error (D0=-1) + ; Get our Ethernet addresss from the PROM + AddQ #EAddrSz, A1 ; go from last to first + MoveQ #EAddrSz-1, D2 ; Get 6 addr bytes + Move.l D3, -(SP) + MoveQ #$51, D3 ; Offset to last address byte + +@35 Move.b (A0,D3.w), D0 ; D0=inverted address + Bsr NormAddr ; Normalize it + Move.b D0, -(A1) ; Store in our vars + SubI #$10, D3 ; Dec offset to previous byte + DBra D2, @35 + Move.l (SP)+, D3 +@45 + + WITH MACEInitParms + SubA #IPSize, SP ; make room for parms + + Move.l UnivInfoPtr, A0 ; Get ptr to ProductInfo + Add.l ProductInfo.DecoderInfoPtr(A0), A0 ; Point to the base address table + Move.l DecoderInfo.MACEAddr(A0), MACEBase(A2) ; Save base address of Mace + + Pea EtherRecv ; addr of packet reception rtn + Move.l (SP)+, RecvRtn(SP) + Move.l A2, RecvPrms(SP) + Lea XmitBuffAvail, A0 ; xmit completion rtn + Move.l A0, XmitRtn(SP) + Move.l A2, XmitPrms(SP) + clr.l MACECfgPtr(SP) ; ptr to MACE config record (none) + Pea Dt3Stats(A2) + Move.l (SP)+, Dot3NetStats(SP) ; where to store 802.3 stats + Pea LAPStats(A2) + Move.l (SP)+, LAPMIBNetStats(SP) ; where to store LAP MIB stats + Pea OurAddr(A2) + Move.l (SP)+, EnetAddr(SP) ; ptr to our Ethernet address + Move.l MemMove(A2), FastMoveRtn(SP) ; addr of fast move memory rtn + + Bsr MACEInit + Bne OpenError + + AddA #IPSize, SP ; Strip parms + ENDWITH + + Lea VBLQEL(A2),A0 + Move #vType,vblType(A0) + Pea ControlDefer + Move.l (SP)+,vblAddr(A0) + Move #32767,vblCount(A0) ; setup control call deferral timer + _VInstall + +; +; Perform 3 MACE loopback tests, if any fails, return an open error +; + Move.l #MaceEnetLongStrEnd-MaceEnetLongStr-1, -(SP) ; pass size of loopback + ; data, minus 1 since pascal string + Pea MaceEnetLongStr+1 ; pass ptr to loopback data + Pea OurAddr(A2) ; pass ptr to our address + MoveA.l OurDCE(A2),A1 ; get ptr to DCE + Move dCtlRefNum(A1),D0 + Move.l D0,-(SP) ; pass our refnum for ctl calls + + MoveA.l MACEBase(A2),A3 ; MACE base address + + ; Perform Internal, no MENDEC, Lpbk + ; Note: network packet reception disabled + Move.b #INTLPB, MACE_USER_TEST_REG(A3) ; set user test reg + nop + Bsr LOOPBACKTEST ; D0 ≠ 0 if passed + Beq LoopError ; failed + + ; Perform Internal, with MENDEC, Lpbk + ; Note: network packet reception disabled + Move.b #MENDECLPB, MACE_USER_TEST_REG(A3) ; set user test reg + nop ; Allow write to complete + Bsr LOOPBACKTEST ; D0 ≠ 0 if passed + Beq LoopError ; failed + + Move.b #EXTLPB, MACE_USER_TEST_REG(A3) ; perform external loopback + nop ; Allow write to complete + Bsr LOOPBACKTEST ; D0 ≠ 0 if passed + Beq LoopError ; failed + + Move.b #NOLPB, MACE_USER_TEST_REG(A3) ; disable loopback + + Bsr.s InitSNMP + IF PROM THEN +; +; Check if we're opened in promiscuous mode +; + Move.l OpenRec.pbblkptr(A6), A0 ; Restore paramblock ptr + BTst.b #Promiscuous, ioFlags+1(A0) ; Are we being opened in Promiscuous mode? + Beq.s @notprm + ST Promiscflg(A2) ; Yes, indicate we're in promiscuous mode + Move.b MACE_MAC_CNFG(A3), D0 ; get current config + OrI.b #(1< ifDescr + Lea MaceEnetLongStr, A0 ; A0 -> where to move from + MoveQ #0, D3 ; Init for BlockMove + Move.b (A0), D3 ; D0.B = strlen of MaceEnetLongStr + Cmp #255, D3 ; is str be greater than 255? + Bls @doit ; no + Move #255, D3 ; yes, move what we can +@doit AddQ #1, D3 ; move len byte too + Move.l D3, D0 + _BlockMove ; Move it + Add.l D3, A1 ; A1 -> new end of ifDescr + + Add.l #RevStrLen, D3 ; ifDescr + RevStr + Cmp #255, D3 ; would new str be greater than 255? + Bgt.s @cont ; yes, done with ifDescr + + ; get MACE Chip ID and convert to ascii + Lea RevStrEnd, A0 + MoveA.l MACEBase(A2), A3 ; MACE base address + MoveQ #0, D0 + Move.b MACE_CHIP_ID_HIGH(A3), D0 ; get high byte MACE Chip ID + Ror.l #4, D0 ; get high nibble + Add.b #$30, D0 ; convert to ascii + Move.b D0, -4(A0) ; save it in RevStr + Clr.b D0 + Rol.l #4, D0 ; get low nibble + Add.b #$30, D0 ; convert to ascii + Move.b D0, -3(A0) ; save it in RevStr + Move.b MACE_CHIP_ID_LOW(A3), D0 ; get low byte MACE Chip ID + Ror.l #4, D0 ; get high nibble + Add.b #$30, D0 ; convert to ascii + Move.b D0, -2(A0) ; save it in RevStr + Clr.b D0 + Rol.l #4, D0 ; get low nibble + Add.b #$30, D0 ; convert to ascii + Move.b D0, -1(A0) ; save it in RevStr + + ; Append RevStr, minus len byte, to ifDescr + Lea RevStrStart+1, A0 ; A0 -> where to move from, will skip length byte + ; A1 -> current end of ifDescr + Move.l #RevStrLen, D0 ; D0.l = strlen of RevStr + _BlockMove ; Move it + + Lea LAPStats.ifDescr(A2), A1 ; A1 -> ifDescr + Add.b #RevStrLen, (A1) ; Set final string length +@cont + + Move.l #SNMPVersion, LAPStats.ifVersion(A2) ; Set version to 1.0.0 + Move.l #iso88023_csmacd, LAPStats.ifType(A2) ; indicate we're an 802.3 link + Move.l #EMaxDataSz, LAPStats.ifMaxMTU(A2) + Move.l #ESpeed, LAPStats.ifSpeed(A2) + + Move.b #EAddrSz, LAPStats.ifPhysAddress(A2) ; set len of ifPhyAddr to #6 + Move.l OurAddr(A2), LAPStats.ifPhysAddress+1(A2) ; copy first 4 bytes of address + Move OurAddr+4(A2), LAPStats.ifPhysAddress+5(A2) ; copy last 2 bytes of address + Move.l #ifStatusUp, LAPStats.ifAdminStatus(A2) + Move.l #ifStatusUp, LAPStats.ifOperStatus(A2) + Move.l Ticks, LAPStats.ifLastChange(A2) + +; Initialize Dt3Stats + + Move.l #SNMPVersion, Dt3Stats.dot3StatsVersion(A2) ; Set version to 1.0.0 + Move.l #0, Dt3Stats.dot3StatsIndex(A2) ; Set index to 0 + +; Initialize Dt3Entry + + Move.l #SNMPVersion, Dt3Entry.dot3Version(A2) ; Set version = 1.0.0 + Move.l #$0, Dt3Entry.dot3Index(A2) + Move.l #2, Dt3Entry.dot3InitializeMac(A2) + Move.l #1, Dt3Entry.dot3SubLayerStatus(A2) + Move.l #1, Dt3Entry.dot3MulticastReceiveStatus(A2) + Move.l #1, Dt3Entry.dot3TxEnabled(A2) + Move.l #0, Dt3Entry.dot3TestTdrValue(A2) + + Rts + +;________________________________________________________________________ +; +; Translate Logical to Physical Address Routine +; +; Call: +; 8(A6).l -> logical address +; 12(A6).l -> logical size +; +; Return: +; D0.w < 0 -> ERROR +; D0.l = physical address +; CC's are set +;________________________________________________________________________ + +; Ptr TranslateAddress(laddr,lsize) ; translate logical to physical addrs +MemBlk RECORD 0 +address DS.l 1 +count DS.l 1 + ENDR + +TraAdd RECORD {A6Link} +LinkSz EQU * +logical DS MemBlk +physical DS MemBlk +A6Link DS.l 2 ; link and return addr +laddr DS.l 1 ; logical address +lsize DS.l 1 ; logical size + ENDR + +TranslateAddress + + WITH TraAdd + Link A6,#LinkSz + Move.l laddr(A6),logical.address(A6) + Move.l lsize(A6),logical.count(A6) + Lea logical(A6),A0 ; A0->translation table + Lea 1,A1 ; A1=count to translate + MoveQ #5,D0 ; GetPhysical + + _MemoryDispatch + IF BUFDEBUG THEN + Beq.s @cont ; success + _Debugger ; failure ?!? +@cont + ELSE + Blt.s @exit ; error, exit + ENDIF + + Move.l physical.Address(A6),D0 ; return lowest physical address +@exit Unlk A6 + Rts + + ENDWITH + +;___________________________________________________________________________ +; +; GetMemory - Get mem and then, optionally, make it contiguous & locked & +; non-cacheable +; +; Call: +; 8(A6).w -> mem options requested +; 10(A6).l -> mem size requested +; +; Return: +; D0.w < 0 -> ERROR, couldn't get mem or couldn't lockmemcontig it +; D0.l = Ptr to locked, contig, non-cacheable mem +; CC's are set +;___________________________________________________________________________ + +GetMem RECORD {A6Link} +LinkSz EQU * +A6Link DS.l 2 ; link and return addr +memoptions DS.w 1 ; requested options +memsize DS.l 1 ; requested size + ENDR + +GetMemory + WITH GetMem + Link A6,#LinkSz + Move.l memsize(A6), D0 + _NewPtr ,SYS,CLEAR ; get the memory + Blt.s @exit ; error, exit + + Move.l A0, -(SP) ; save ptr to new mem + Move memoptions(A6), D1 + ; want mem locked, contiguous, or non-cacheable? + AndI #(1< mem options +; 10(A6).l -> mem address to free +; 14(A6).l -> mem size to free +; +; Return: +; D0 = noErr +; CC's are set +;___________________________________________________________________________ + +FreeMem RECORD {A6Link} +LinkSz EQU * +A6Link DS.l 2 ; link and return addr +memoptions DS.w 1 ; requested options +memaddr DS.l 1 ; address of mem to free +memsize DS.l 1 ; size of mem to UN-(lock,contig,noncache) + ENDR + +FreeMemory + WITH FreeMem + Link A6,#LinkSz + + Move memoptions(A6), D1 ; get mem options + ; was mem locked,contiguous,or non-cacheable? + AndI #(1< I/O queue element +; A1 -> device control entry +;________________________________________________________________________ + +ControlDefer ; task to complete a deferred control call + Move.w #32767,vblCount(A0) ; next task is a long time maybe + _StackSpace ; D0 = avail. stack space + Tst.l D0 + Bmi.s @defer ; defer if negative space + CmpI.l #512,D0 ; is there a little room? + Bhs.s @doControl ; yes +@defer + Move.w #1,VBLCount(A0) ; restart fast timer +@exit + Rts ; and get out +@doControl + Lea -VBLQEL(A0),A2 ; A2->our vars + BClr #0,deferCtl(A2) + Beq.s @exit ; return to VBL if not really deferring + + MoveA.l OurDCE(A2),A1 ; A1->our DCE + MoveA.l dCtlQHead(A1),A0 ; A0->param block in use + Bra.s doControl +Control + Move.w ioTrap(A0),D0 ; get trap word that called us + + BTst #asyncTrpBit,D0 ; is this a synchronous call? + Beq.s doControl ; yes, bypass stack check + + _StackSpace ; D0 = avail. stack space + Tst.l D0 + Bmi.s @defer ; defer if negative space + CmpI.l #512,D0 ; is there a little room? + Bhs.s doControl ; yes +@defer + MoveA.l OurVarPtr,A2 ; A2->our vars + BSet #0,deferCtl(A2) ; indicate we are deferring + Move.w #1,vblCount+VBLQEL(A2) ; set next vbl to tick fast +CRts + MoveQ #noErr,D0 ; good return for now + Rts ; get out and get stack back +doControl + Move.l OurVarPtr,A2 ; A2 -> our variables + Move.w CSCode(A0),D2 ; Pickup control code + SubQ #KillCode,D2 ; Check for OS kill I/O call + Beq.s CRts ; return if so + + MoveQ #ControlErr,D0 ; Assume a control error + Move.l OurVarPtr,A2 ; A2 -> our variables + Sub #FirstENET-KillCode,D2 ; Subtract off lowest command + Blt ENETDone ; Return error if too low + Cmp #LastENET-FirstENET,D2 ; Make sure not too high + Bgt ENETDone ; Return error if too high + Move CSParam(A0),D1 ; D1 = 1st parameter word + Move.l CSParam+2(A0),D3 ; D3 = 1st parameter longword +; +; Pick up routine address for this command and jump to routine +; + Move.w (ControlTable,D2.w*2),D2 ; get offset of routine + Jmp (ControlTable,D2.w) ; go do the call + +;_________________________________________________________________________ +; +; Control dispatch table - must be in the same order as the ENET commands. +; Specifies offsets to the command-handling routines. +;_________________________________________________________________________ + +ControlTable + DC.w LapGetDot3Entry-ControlTable ; 238 + DC.w ENETDONE-ControlTable ; 239 LapSetDot3Entry + DC.w LapDot3Stats-ControlTable ; 240 + DC.w ENETDONE-ControlTable ; 241 LapDot3CollStats + DC.w LapGetLinkStatus-ControlTable ; 242 + DC.w ENETOK-ControlTable ; 243 CloseSAP + DC.w ENETOK-ControlTable ; 244 OpenSAP + DC.w DoDelMulti-ControlTable ; 245 + DC.w DoAddMulti-ControlTable ; 246 + DC.w DoAttachPH-ControlTable ; 247 + DC.w DoDetachPH-ControlTable ; 248 + DC.w DoWrite-ControlTable ; 249 + DC.w DoRead-ControlTable ; 250 + DC.w DoRdCancel-ControlTable ; 251 + DC.w DoGetInfo-ControlTable ; 252 + DC.w ENETOK-ControlTable ; 253 DoSetGeneral + +;___________________________________________________________________________ +; +; LapGetDot3Entry - Get Dt3Entry +; +; Call: +; A0 -> queue element +; A2 -> our variables +; D3 = Link Stats Pointer +; +; Return: +; D0 = noErr +; EBuffSize(A0) = bytes returned +;___________________________________________________________________________ + +LapGetDot3Entry + Move.l #0, D0 ; Clear out D0 + Move EBuffSize(A0), D0 ; D0 = # of bytes to move + Cmp #Dot3EntrySz, D0 ; Asking for more than we have? + Bls.s @OKsize ; no + Move #Dot3EntrySz, D0 ; yes, just return what we have +@OKsize + Move D0, EDataSize(A0) ; Return eDataSize + Move.l D3, A1 ; A1 -> user's Dot3Entry buffer + LEA Dt3Entry(A2), A0 + _BlockMove + + Bra ENETOK + +;___________________________________________________________________________ +; +; LapGetLinkStatus - Return LAPMIBStats record info +; +; Call: +; A2 -> our variables +; D3 = Link Stats Pointer +; +; Return: +; D0 = noErr +; EBuffSize(A0) = bytes returned +;___________________________________________________________________________ + +LapGetLinkStatus + Move.l MultiRecvd(A2), D0 + Add.l BcastRecvd(A2), D0 + Move.l D0, LAPStats.ifInNUcastPkts(A2) ; update non-unicast cnt + + Move.l #0, D0 ; Clear out D0 + Move EBuffSize(A0), D0 ; D0 = # of bytes to move + Cmp #LAPMIBStatsSz, D0 ; Asking for more than we have? + Bls.s @OKsize ; no + Move #LAPMIBStatsSz, D0 ; yes, just return what we have +@OKsize + Move D0, EDataSize(A0) ; Return eDataSize + MoveA.l D3, A1 ; A1 -> user's LAPMIBStats buffer + Lea LAPStats(A2), A0 + _BlockMove + + Bra ENETOK + +;___________________________________________________________________________ +; +; LapDot3Stats - return Dot3Stats record info +; +; Call: +; A2 -> our variables +; D3 = 802.3 Stats Pointer +; +; Return: +; D0 = noErr +; EBuffSize(A0) = bytes returned +;___________________________________________________________________________ + +LapDot3Stats + Move.l #0, D0 ; Clear out D0 + Move EBuffSize(A0), D0 ; D0 = # of bytes to move + Cmp #Dot3StatsEntrySz, D0 ; Asking for more than we have? + Bls.s @OKsize ; no + Move #Dot3StatsEntrySz, D0 ; yes, just return what we have +@OKsize + Move D0, EDataSize(A0) ; Return eDataSize + MoveA.l D3, A1 ; A1 -> user's Dot3Stats buffer + Lea Dt3Stats(A2), A0 + _BlockMove + + Bra ENETOK + +;___________________________________________________________________________ +; +; DoAddMulti - add a multicast address to the list +; +; Call: +; A2 -> our variables +; D1 = first two bytes of address +; D3 = last four bytes of address +; +; Return: +; D0 = error code +; +; Finds a free entry in the Multicast Table, stores the multicast address, +; and increments the use count. Calls Mace rtn to update Mace Logical +; Address Filter (LAF). +;___________________________________________________________________________ + +DoAddMulti + MoveQ #eMultiErr,D0 ; Assume invalid address or table full + BTst #8,D1 ; Make sure multicast bit is set + Beq ENETDone ; Return error if invalid multicast address + Bsr FindMEntry ; D2 = entry number for this address + Bpl.s @40 ; Branch if found it +; +; Look for the first free one +; + MoveQ #MTblSz-1,D2 ; D2 = no. of entries in multicast table +@30 Tst.b (MultiCTbl+MUseCount,A2,D2*MEntrySz) + ; This one free? + DBeq D2,@30 ; Loop until checked them all or got one +@35 Bne ENETDone ; Error if none free + +; +; Set in table, then compute and set hash bit in Logical Address Filter (LAF) +; +@40 Move.l D3,(MultiCTbl+2,A2,D2*MEntrySz) + ; Set second part of address + Move D1,(MultiCTbl,A2,D2*MEntrySz) + ; Set first part of address + AddQ.b #1,(MultiCTbl+MUseCount,A2,D2*MEntrySz) + + Bsr.l MACEAddMulti ; Let Mace update LAF + + Bra ENETOK + +;___________________________________________________________________________ +; +; DoDelMulti - delete a multicast address from the list +; +; Call: +; A2 -> our variables +; D1 = first two bytes of address +; D3 = last four bytes of address +; +; Return: +; D0 = error code +; +; Finds the multicast address in the Multicast Table and decrements the use +; count. Calls Mace rtn to update Mace Logical Address Filter (LAF). +;___________________________________________________________________________ + +DoDelMulti MoveQ #eMultiErr,D0 ; Assume address not found + Bsr.s FindMEntry ; D2 = entry number in table + Bmi ENETDone ; Return error if not found + SubQ.b #1,(MultiCTbl+MUseCount,A2,D2*MEntrySz) ; Decrement use count + + Bsr.l MACEDelMulti ; Let Mace update LAF + + Bra ENETOK + +; +; FindMEntry - find this address's entry in the multicast table +; +; Call: +; D1 = high two bytes of address +; D3 = low four bytes of address +; A2 -> our variables +; +; Return: +; D2 = entry number within table (minus if not found). CCR set. +; + +FindMEntry MoveQ #MTblSz-1,D2 ; D2 = no. of entries in multicast table +@10 Tst.b (MultiCTbl+MUseCount,A2,D2*MEntrySz) + ; Is this entry in use? + Beq.s @20 ; Branch if not + Cmp (MultiCTbl,A2,D2*MEntrySz),D1 + ; This it? + Bne.s @20 ; Branch if not + Cmp.l (MultiCTbl+2,A2,D2*MEntrySz),D3 + ; Is it? + Beq.s @30 ; Branch if got it +@20 DBra D2,@10 ; Loop until checked them all +@30 Tst D2 ; Set CCR + Rts ; And return + +;___________________________________________________________________________ +; +; DoAttachPH - attach protocol handler control call +; +; Call: +; A2 -> our variables +; D3.l = address of protocol handler's packet-receive code or zero +; D1.w = protocol type code +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoAttachPH + IF BIT24 THEN + And.l AddrMask(A2),D3 ; 32 bit clean + ENDIF + MoveQ #LAPProtErr,D0 ; Assume an invalid protocol error + + IF PROM THEN + Tst.B Promiscflg(A2) ; Are we in Promiscuous mode? + Beq.S @10 ; No, Note: not set until pass lpbk test + Tst.w D1 + Bne.s ENETDone ; Force attach to ONLY prot type 0 +@10 + ENDIF +; +; Read down the active protocol table, searching for a match +; + Bsr.s GetProt ; See if it's there + Bpl.s ENETDone ; Return error if protocol already active +; +; Now scan for the first free one . . . +; + MoveQ #LAPTblSz-1,D2 ; Index into active protocols list +@20 Tst.b InUseFlag(A2,D2) ; Check this entry + DBeq D2,@20 ; Loop until get one or end + Bne.s ENETDone ; Error if none + Move.l D3,(Handlers,A2,D2*4) ; Fill Handlers in first (in case of interrupt) + Clr.l (RdQueueHd,A2,D2*4) ; Clear out read queue head + Move D1,Protocols(A2,D2*2) + ; Fill protocol type in + ST InUseFlag(A2,D2) ; Indicate in use +ENETOK Clr D0 ; Indicate no error +ENETDone + Move.l OurDCE(A2),A1 ; Make sure A1 has DCE address + MoveA.l JIODone,A0 + Jmp (A0) ; all done now + +; +; Lookup D1 in the protocol table. Return D2 = index to protocol (negative = error). +; +GetProt MoveQ #LAPTblSz-1,D2 ; Index into active protocols list +@10 Tst.b InUseFlag(A2,D2) ; In use? + Beq.s @20 ; Branch if not + Cmp Protocols(A2,D2*2),D1 ; Match? + Beq.s @30 ; Branch if so +@20 DBra D2,@10 ; Keep going until got one +@30 Tst D2 ; Set CCR to D2 + Rts ; Return (BPL for match) +;___________________________________________________________________________ +; +; DoDetachPH - detach protocol handler control call +; +; Call: +; A2 -> our variables +; D1.w = protocol type code +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoDetachPH + MoveQ #LAPProtErr,D0 ; Assume no such protocol active + + IF PROM THEN + Tst.B Promiscflg(A2) ; Are we in Promiscuous mode? + Beq.S @5 ; No, Note: not set until pass lpbk test + Tst.w D1 + Bne.s ENETDone ; Force deattach to ONLY prot type 0 +@5 + ENDIF + Bsr.s GetProt ; D2 = index to protocol + Bmi.s ENETDone ; Return error if at end of table + Clr.b InUseFlag(A2,D2) ; Indicate entry free + Tst.l (Handlers,A2,D2*4) ; Default handler? + Bne.s @10 ; All done if not + Bsr.s AbortAll ; Abort all active reads +@10 Bra.s ENETOK ; Complete this call + + +; +; AbortAll - abort all active read requests. +; +; Call: +; A2 -> our variables +; D2 = flag offset into protocol table +; Uses D1,A0 +; +; Assumes InUseFlag(A2,D2) cleared out already so no interrupts +; + +AbortAll Move.l (RdQueueHd,A2,D2*4),D1 ; D1 -> first read, if any + Beq.s @10 ; Branch if none + Move.l D1,A0 ; A0 -> queue element + Move.l (A0),(RdQueueHd,A2,D2*4) ; Remove from queue + Move #reqAborted,D0 ; Set error code + Bsr CompleteReq ; Return error + Bra.s AbortAll ; And loop + +@10 Rts + +;___________________________________________________________________________ +; +; DoWrite - write out a packet on Ethernet +; +; Called: +; A2 -> our variables +; D3 = WDS pointer +; +; Return: +; D0 = error code; nobuff => chip drvr out of xmit buffers +; eLenErr => sum of data in WDS > max. pkt size +; noErr => chip drvr gave pkt to chip or put pkt +; in xmit queue for transmission +; +; Notes: Depends on MACEXmit to check maximum WDS length +; +;___________________________________________________________________________ + +DoWrite + MoveQ #eLenErr, D0 ; Assume length error + Move.l D3,A0 ; A0 -> WDS + Cmp #EHdrSize,(A0) ; First entry must have whole header + Blo ENETDone ; Error if not + + Move.l 2(A0),A0 ; A0 -> first WDS entry + Move.l OurAddr(A2),ESrcAddr(A0) ; Set our address in it + Move OurAddr+4(A2),ESrcAddr+4(A0) + + IF Logging THEN + move.l #'DoWr',-(sp) + move.l ESrcAddr(A0),-(sp) + move.l ESrcAddr+4(A0),-(sp) + bsr AddToLog + add.w #12,sp + ENDIF + + Move.l D3, -(SP) ; Push WDS ptr + Bsr MACEXmit ; send the packet + AddQ #4, SP ; Strip parms + Tst.l D0 ; Error? + Bne.s @xmitfail ; yes, check it + Bra ENETDone ; no, complete write req. w/no error + +@xmitfail Cmp.l #nobuff, D0 ; temporarily out of xmit buffs? + IF BUFDEBUG THEN + Bne.s @chklenerr ; no, it must be a len err; lets chk + ELSE + Bne ENETDone ; no, its a len err; return err + ENDIF + + MoveQ #noErr,D0 + Rts ; Return, don't complete write yet + + IF BUFDEBUG THEN +@chklenerr Cmp.l #eLenErr, D0 ; WDS length error? + Beq.s @ok ; yes + _Debugger ; no, what the heck? +@ok Bra ENETDone ; complete write req. w/error + ENDIF + + +;___________________________________________________________________________ +; +; XmitBuffAvail - xmit completion routine +; +; Call: +; d0 - transmit waiting flag (!=0 means a write is pending) +; +; Return: +; no return value/status +; +; Notes: called via time manager after DoWrite gets no buff available error +; from MACEXmit call. +;___________________________________________________________________________ +TxPrm RECORD 4 +TxParm DS.l 1 ; my xmitdone parm +TxPrmSz EQU * + ENDR + +XmitBuffAvail + + IF Logging THEN + move.l #'WrDn',-(sp) + clr.l -(sp) + clr.l -(sp) + bsr AddToLog + add.w #12,sp + ENDIF + + MoveA.l OurVarPtr,A0 ; get ptr to our vars + + IF BUFDEBUG THEN + AddQ.l #1, XmtDnActive(A0) + CmpI.l #1, XmtDnActive(A0) + Beq.s @ok + _Debugger ; oooppppsss! +@ok + ENDIF + + Tst.b d0 ; waiting for xmit buffs? + Beq.s @exit ; no + + IF COUNTERS THEN + AddQ.l #1, XmitPend(A0) + ENDIF + + MoveM.l A0/A2/A3/D3, -(SP) ; save C regs + MoveA.l A0, A2 ; A2->our vars + MoveA.l OurDCE(A2), A1 ; A1->our DCE + Move.l dCtlQHead(A1),d0 + beq.s @done + move.l d0,A0 ; A0->waiting write param blk + Move.l CSParam+2(A0), D3 ; D3 = 1st parameter longword (e.g. WDSP) + Bsr DoWrite ; process the write +@done MoveM.l (SP)+, A0/A2/A3/D3 ; restore C regs + + IF BUFDEBUG THEN + SubQ.l #1, XmtDnActive(A0) + ENDIF +@exit Rts + + EJECT +;___________________________________________________________________________ +; +; DoRead - read a packet off the Ethernet +; +; Call: +; A0 -> queue element +; A1 -> our DCE +; A2 -> our variables +; D1 = protocol type code +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoRead MoveQ #LAPProtErr,D0 ; Assume an error + Bsr GetProt ; D2 = index into PH table + Bmi ENETDone ; Error if not there + Tst.l (Handlers,A2,D2*4) ; Is it the default? + Bne ENETDone ; Error if not + Move #buf2SmallErr,D0 ; Assume buffer not big enough + Cmp #EHdrSize,EBuffSize(A0) ; Must hold at least header + Blo ENETDone ; Return error if not +; +; Dequeue the request from the system queue and queue it on ours (in order) +; + Lea (RdQueueHd,A2,D2*4),A3 ; A3 -> queue head + Move SR,-(SP) ; Save interrupt status + Move #DMALockOut, D1 + _SETINTMASK D1 +@10 Tst.l (A3) ; Is there a next element? + Beq.s @20 ; Branch if not + Move.l (A3),A3 ; Point to it if so + Bra.s @10 ; And keep going until end + +@20 + IF BIT24 THEN + Exg D0,A0 + And.l AddrMask(A2),D0 + Exg D0,A0 ; 32 bit clean + ENDIF + Move.l A0,(A3) ; Put queue element on our queue + BClr #DrvrActive,DCtlFlags+1(A1) + ; Clear driver active flag + Move.l IOLink(A0),DCtlQHead(A1) ; Set next element addr in head + Bne.s @30 ; Branch if there is none + Clr.l DCtlQTail(A1) ; Clear tail if not +@30 Clr.l IOLink(A0) ; Indicate it's last one on our queue + Move.l DCtlQHead(A1),D0 ; Any more requests? + Beq.s @40 ; Branch if not + BSet #DrvrActive,DCtlFlags+1(A1) + ; We're active again + Move (SP)+,SR ; Restore interrupt state + Move.l D0,A0 ; A0 -> new queue element + MoveQ #0,D0 ; D0 should be clear + IF Logging THEN + move.l #'DoRd',-(sp) + move.l a0,-(sp) + clr.l -(sp) + bsr AddToLog + add.w #12,sp + ENDIF + Bsr Control ; Call ourselves + MoveQ #0,D0 ; Return no error for previous call + Rts ; Return + +@40 Move (SP)+,SR ; Restore interrupt state + Rts ; Return +;___________________________________________________________________________ +; +; DoRdCancel - abort a pending read call +; +; Call: +; A2 -> our variables +; D3 = pointer to queue element to abort +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoRdCancel Move #CBNotFound,D0 ; Assume an error + IF BIT24 THEN + And.l AddrMask(A2),D3 ; 32 bit clean + ENDIF + Move.l D3,A1 ; A1 -> queue element + Move EProtType(A1),D1 ; D1 = protocol type + Bsr GetProt ; D2 = index into PH table + Bmi.s @60 ; Error if not there + Tst.l (Handlers,A2,D2*4) ; Is it the default? + Bne.s @60 ; Error if not + Lea (RdQueueHd,A2,D2*4),A3 ; A3 -> queue head + Move SR,-(SP) ; Save interrupt status + Move #DMALockOut, D1 + _SETINTMASK D1 +@30 Move.l (A3),D3 ; D3 -> next element in queue + IF BIT24 THEN + And.l AddrMask(A2),D3 ; 32 bit clean + ENDIF + Beq.s @50 ; Error if no more + Sub.l A1,D3 ; Subtract out desired one + Beq.s @40 ; Branch if it's the one + Move.l (A3),A3 ; A3 -> next in queue + Bra.s @30 ; Keep looking + +@40 Move.l (A1),(A3) ; Point previous to next + Move (SP)+,SR ; Restore interrupts +; +; Complete the ERead with an error, then the ERdCancel +; + Move.l A1,A0 ; A0 -> ERead queue element + Move #ReqAborted,D0 ; D0 = aborted error + Bsr.s CompleteReq ; Complete it with error + Bra ENETOk ; Return no error for RdCancel + +@50 Move (SP)+,SR ; Restore interrupt state +@60 Bra ENETDone ; Return not found error + + +;________________________________________________________________________ +; +; CompleteReq - this code basically executes the parts of IODone necessary to +; complete the user's request (sets result code and executes the user's +; completion routine) +; +; Call: +; D0 = result code +; A0 -> I/O queue element +;________________________________________________________________________ + +CompleteReq Move.w D0,IOResult(A0) ; Set the result code + MoveM.l D1-D3/A0-A3,-(SP) ; Save registers + + IF Logging THEN + move.l #'COMP',-(sp) + move.l a0,-(sp) + clr.l -(sp) + bsr AddToLog + add.w #12,sp + ENDIF + Move.l IOCompletion(A0),D1 ; Check if there's a completion routine + Beq.s @10 ; Branch if not - just return + Move.l D1,A1 ; Get it if so + Tst.w D0 ; IODone does this + Jsr (A1) ; Call completion routine +@10 MoveM.l (SP)+,D1-D3/A0-A3 ; Restore registers + Rts ; Return +;___________________________________________________________________________ +; +; DoGetInfo - return stats in the following form: +; Our address, 3 lw's of 0's, Netstats record +; +; Call: +; A0 -> queue element +; A2 -> our variables +; D3 -> buffer for response +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoGetInfo + IF BIT24 THEN + And.l AddrMask(A2),D3 ; 32 bit clean + ENDIF + Move #buf2SmallErr,D0 ; Assume buffer not big enough + Cmp #6,EBuffSize(A0) ; Must hold at least address + Blo ENETDone ; Return error if not + + MoveQ #0, D0 + Move EBuffSize(A0),D0 ; D0 = buffer size + Cmp #InfoEnd-InfoStart,D0 ; Asking for more than we have? + Bls.s @10 ; no, branch + MoveQ #InfoEnd-InfoStart,D0 ; yes, just return what we have +@10 Move.l D3,A1 ; A1 -> where to move to + Lea InfoStart(A2),A0 ; A0 -> where to move from + +; +; Copy netstat info from Dot2stat and LAPMIBstat areas to "old" getinfo area +; + Move.l (LAPStats.ifOutUcastPkts,A2), D1 + Add.l (LAPStats.ifOutNUcastPkts,A2), D1 + Move.l D1, (EtherStats.TxOK,A2) + Move.l (Dt3Stats.dot3StatsSingleCollisionFrames,A2), (EtherStats.sCollFrame,A2) + Move.l (Dt3Stats.dot3StatsMultipleCollisionFrames,A2), (EtherStats.mCollFrame,A2) +; EtherStats.CollFrame doesn't make sense and is left 0 + Move.l (Dt3Stats.dot3StatsDeferredTransmissions,A2), (EtherStats.DefTx,A2) + Move.l (Dt3Stats.dot3StatsLateCollisions,A2), (EtherStats.LateColl,A2) + Move.l (Dt3Stats.dot3StatsExcessiveCollisions,A2), (EtherStats.ExcessColl,A2) + Move.l (Dt3Stats.dot3StatsExcessiveDeferrals,A2), (EtherStats.ExcessDef,A2) + Move.l (Dt3Stats.dot3StatsInternalMacTransmitErrors,A2), (EtherStats.InMACTxErr,A2) + Move.l (LAPStats.ifInUcastPkts,A2), (EtherStats.RxOK,A2) + Move.l MultiRecvd(A2), (EtherStats.MultiRxOK,A2) + Move.l BcastRecvd(A2), (EtherStats.BroadRxOK,A2) + Move.l (Dt3Stats.dot3StatsFCSErrors,A2), (EtherStats.FCSerr,A2) + Move.l (Dt3Stats.dot3StatsAlignmentErrors,A2), (EtherStats.FAerr,A2) + Move.l (LAPStats.ifInErrors,A2), (EtherStats.MPerr,A2) + + _BlockMove ; Move it + Bra ENETOK ; Return no error + +;___________________________________________________________________________ +; +; EtherRecv - .ENET packet receive routine +; +; Call: +; Received packet(s) pointed to by buffer(s) on InUse Queue +; +; Return: +; Empty InUse Queue +; +; Destroys: +; Notes: +; EtherRecv is called by the MACE since we passed a ptr to EtherRecv +; as the RecvRtn in the MACEInit call. +; +; Calls: +; Upper layer handler, or Default Handler, to receive packet. +;___________________________________________________________________________ + +EtherRecv + WITH RcvParms + Link A6, #Size + + IF Logging THEN + move.l #'Ethr',-(sp) + move.l #'Recv',-(sp) + move.l PktStat(A6),-(sp) + bsr AddToLog + add.w #12,sp + ENDIF + Move.l PktStat(A6), D0 ; get packet status + AndI.w #(1< RHA + MoveA.l PktData(A6), A0 ; A0 -> packet data + Move.l (A0)+, (A3)+ ; Move header into buffer + Move.l (A0)+, (A3)+ ; Hard code for speed + Move.l (A0)+, (A3)+ + Move (A0)+, (A3)+ ; A3 -> buffer after header + +; +; Check if dest. addr. a broadcast or one of our multicasts +; + Move RHA(A2), D3 ; D3 = first 2 bytes of dest address + BTst #8, D3 ; Is it a broadcast or multicast? + Beq.s @45 ; Branch if not, it must be our physical address + MoveQ #-1, D2 ; D2 = $FFFFFFFF + Cmp D2, D3 ; Is packet a broadcast? + Beq.s @last4 ; Maybe, check last 4 bytes of dest address + Move.l RHA+2(A2), D3 ; No, D3 = last 4 bytes of dest address + Bra @120 ; Go check if one of our registered multicasts +@last4 Move.l RHA+2(A2), D3 ; D3 = last 4 bytes of dest address + Cmp.l D2, D3 ; Is packet a broadcast? + Bne @120 ; No, go check if one of our registered multicasts + AddQ.l #1, BcastRecvd(A2) ; Yes, inc. broadcast pkt cntr + Bra.s @50 + +@45 AddQ.l #1, (LAPStats.ifInUcastPkts,A2) ; inc. non-multi/bcast pkt cntr + +; +; Search the protocol handler table for this protocol +; + +@50 Move EType-EHdrSize(A3),D0 ; D0 = protocol type or 802.3 length + Cmp.w #EMaxDataSz,D0 ; is it an 802.3? + Bhi @110 ; if not, try other protocols + + Clr D0 ; Handler will be for type zero + Exg D0,D1 ; D1 = protocol type, D0 = old D1 + Bsr GetProt ; D2 = offset in table + Exg D0,D1 ; Restore D0, D1 + Bmi.s @90 ; Branch if not found +; Move EType-EHdrSize(A3),D0 ; D0 = protocol type + +@70 Lea EReadPacket,A4 ; A4 -> our ReadPacket routine + Lea DefaultPH,A5 ; use default maybe + Move.l (Handlers,A2,D2*4),D3 ; get the protocol handler + Beq.s @80 ; use default + MoveA.l D3,A5 ; use table entry's protocol handler + +@80 + Jsr (A5) ; Call protocol handler + +@85 MoveM.l (SP)+, A2-A5/D3 ; Restore registers +@86 Unlk A6 + Rts ; That's it + +@90 AddQ.l #1, LAPStats.ifInUnknownProtos(A2) + Bra.s @85 +; +; Find Protocol handler for non 802.3 packet +; +@110 + Exg D0,D1 ; D1 = protocol type, D0 = old D1 + Bsr GetProt ; D2 = offset in table + Exg D0,D1 ; Restore D0, D1 + Bmi.s @90 ; Branch if not found + + Bra.s @70 ; Process it + +; +; Packet is a multicast. Check if it matches one of our multicast addresses. +; +; Call: +; A2 -> our variables +; D3 = last 4 bytes of destination address +; +@120 Move D1,D0 ; Save length in case packet's for us + Move RHA(A2),D1 ; D1 = high two bytes of address + Bsr FindMEntry ; D2 = entry within multicast table + Bmi.s @150 ; Ignore it if not found + AddQ.l #1, MultiRecvd(A2) ; Inc count of multicast pkts recv'd + Move D0,D1 ; Restore packet length + Bra @50 ; And process packet + +@150 AddQ.l #1, LAPStats.ifInDiscards(A2) ; Increment count of packets not for us + Bra.s @85 ; Ignore this packet + + + +;___________________________________________________________________________ +; +; EReadPacket - read in the specified number of bytes into the specified +; buffer. Asking for more than there is is an error. +; +; EReadRest - read in the rest of the packet, putting the specified number +; of bytes into the specified buffer, and ignoring the rest. +; +; Call: +; A0 -> current location in card memory +; A1 -> card registers +; A3 -> buffer to read into +; A4 -> start of ReadPacket +; D1 = number of bytes left to come in (caller may decrease) +; D3 = byte count to read +; +; Return: +; D0 = error byte (Z bit set in CCR) +; D1 updated (ReadPacket) +; D2 saved +; D3 = 0 if exact number of bytes requested were read +; > 0 indicates number of bytes requested but not read +; (packet smaller than requested maximum) +; < 0 indicates number of extra bytes read but not returned +; (packet larger than requested maximum) +; A0,A1 preserved by ReadPacket, modified by ReadRest +; A2 saved +; A3 -> one past where last character went +; A4,A5 saved (until packet's all in or error) +;___________________________________________________________________________ + +EReadPacket Bra.s EDoRP ; Need this for two entry points + +EReadRest Move D3,D0 ; D0 = number of bytes to return + Sub D1,D0 ; D0 = remainder count + Tst D3 ; Check for zero + Beq.s @10 ; If so, don't waste our time + Bsr.s MoveBytes ; Move the bytes in +@10 Move D0,D3 ; D3 = remainder count + MoveQ #0,D0 ; No error no matter what + Rts +EDoRP + Cmp.w D3,D1 + Blo.s @5 ; error in request + Bsr.s MoveBytes ; Move in the bytes + Tst D3 ; Moved them all? + Beq.s @10 ; Branch if moved all ok +@5 MoveQ #eLenErr,D0 ; Set length error +@10 Rts ; Return +;___________________________________________________________________________ +; +; DefaultPH - default protocol handler - complete an ERead call if there +; +; Call: +; A0,A1: preserve until ReadRest +; A2 -> local variables +; A4 -> EReadPacket +; A5 usable until ReadRest +; D0 = protocol type +; D2 = index into protocol table +; +; Notes: Interrupts are off +; +;___________________________________________________________________________ + +DefaultPH + Move.l (RdQueueHd,A2,D2*4),D0 ; D0 -> first ERead on queue + Beq.s @20 ; Skip packet if none + Move.l D0,A5 ; A5 -> ERead queue element + Move.l (A5),(RdQueueHd,A2,D2*4) ; Remove from queue + Move.l D0,D2 ; D2 = queue element pointer + Move.l EBuffPtr(A5),A3 ; A3 -> buffer to read into + Move EBuffSize(A5),D3 ; D3 = maximum size to read + Sub #EHdrSize,D3 ; Adjust for header + IF PROM THEN + Tst.B Promiscflg(A2) ; Are we in Promiscuous mode? + Beq.S @5 ; No, Note: not set until pass lpbk test + Lea PromiscRHA(A2), A5 ; A5 -> header info including pkt status lw + Move.l (A5)+,(A3)+ ; Move pkt status into buffer + Bra.s @6 +@5 Lea RHA(A2),A5 ; A5 -> header info +@6 + ELSE + Lea RHA(A2),A5 ; A5 -> header info + ENDIF + Move.l (A5)+,(A3)+ ; Move header into buffer + Move.l (A5)+,(A3)+ ; Hard code for speed + Move.l (A5)+,(A3)+ ; (AssumeEq?) + Move (A5)+,(A3)+ ; A3 -> buffer after header + Jsr 2(A4) ; Read in the whole thing (D0=0) + Move.l D2,A0 ; A0 -> queue element again + Move EBuffSize(A0),D1 ; D1 = original request size + Sub D3,D1 ; D1 = total packet size + Move D1,EDataSize(A0) ; Set in queue element + Tst D3 ; Check for buffer overflow + Bpl.s @10 ; Branch if no overflow + Move #buf2SmallErr,D0 ; Set error +@10 Bra CompleteReq ; Complete request and return + +@20 MoveQ #0,D3 ; Indicate no buffer + Jmp 2(A4) ; Ignore packet and return + + +;___________________________________________________________________________ +; +; MoveBytes - move bytes from card memory to desired place +; +; Call: +; A0 -> current location in card memory +; A3 -> place to move bytes to +; D1 = number of bytes left in packet +; D3 = number of bytes to move +; +; Return: +; A0 adjusted +; A3 adjusted past bytes moved in +; D1 adjusted +; D3 = zero if all could be moved, remainder otherwise +;___________________________________________________________________________ + +MoveBytes + + MoveM.l D0/D2/A1/A2,-(SP) ; Save registers + Move.l OurVarPtr,A2 ; A2 -> our variables + IF BIT24 THEN + Exg D0,A3 + And.l AddrMask(A2),D0 + Exg D0,A3 ; 32 bit clean + ENDIF + Move.l A3,A1 ; A1 -> where to move to + MoveQ #0,D0 ; D0 = number of bytes to move + Move D3,D0 ; Assume we can move all asked for + Cmp D1,D3 ; Can we move all asked for? + Bls.s @10 ; Branch if so + Move D1,D0 ; Else move all we can +@10 Sub D0,D1 ; Adjust count left to come in + Sub D0,D3 ; D3 = bytes not moved + AddA.w D0,A3 + + Move.l D1,-(SP) ; save this one + Move.l A0,-(SP) + Move.l D0,-(SP) + Jsr ([MemMove,A2]) ; call block move routine + MoveA.l (SP)+,A0 + AddA.l (SP)+,A0 ; adjust pointer + Move.l (SP)+,D1 + +@30 MoveM.l (SP)+,D0/D2/A1/A2 ; Restore registers + Rts ; That's it +;________________________________________________________________________ +; +; Close - close the ENET driver. +; +; Call: +; A1 -> DCE +;________________________________________________________________________ + +Close +; This code is only called if one of the LoopBack tests failed. Closing is +; not a supported function since there is no way for me to know how many +; clients are using the driver; ie. AppleTalk using 802.3 and MacTCP using +; Ethernet. If the Device Manager passed all open calls to the driver a +; use-count could be implemented and I could truely support Close. + MoveA.l OurVarPtr, A2 ; A2 -> our variables + + Bsr MACEHalt ; stop MACE + + MoveQ #LAPTblSz-1,D2 ; D2 = Index into active protocols list +@10 Tst.b InUseFlag(A2,D2) ; Active? + Beq.s @20 ; Branch if not + Tst.l (Handlers,A2,D2*4) ; Default handler + Bne.s @20 ; Branch if not + Bsr AbortAll ; Abort all requests +@20 DBra D2,@10 ; On to next + + Lea VBLQEL(A2),A0 + Tst.l vblAddr(A0) ; did we launch ctl call VBL? + Beq.s @50 + _VRemove ; remove VBL task if so +@50 + MoveA.L OurVarPtr,A0 + _DisPosPtr ; free our var mem + + Lea OurVarPtr,A2 ; A2 -> variable pointer + Clr.l (A2) ; Clear it out (no variables) + MoveQ #0,D0 ; Indicate no error +AnRts Rts ; And return + +; +; Variable storage +; +OurVarPtr DC.l 0 ; Pointer to our variables + END + + + diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEnet.a.idump b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEnet.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEnet.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEnet.a.rdump b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEnet.a.rdump new file mode 100644 index 0000000..cb6d1a1 --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEnet.a.rdump @@ -0,0 +1,29 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0000 F0D2 0001 CD42" /* ..Monaco.......B */ + $"0000 0200 0000 F200 0200 0000 0000 0000" /* ................ */ + $"0000 0006 0004 005F 0249 027D 0465 003B" /* ......._.I.}.e.; */ + $"0012 0259 022E A858 AB80 0000 0193 0000" /* ...Y...X........ */ + $"0204 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"005F 0249 027D 0465 003B 0012 0259 022E" /* ._.I.}.e.;...Y.. */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"0E95 2FA6 3FE5 3230 0004 0000 0000 0000" /* ../.?.20........ */ + $"0000 A933 73A3 A933 73A3 A796 71C8 0006" /* ...3s..3s...q... */ + $"D7AA 0000 0001 000F 3153 7570 6572 4D61" /* ........1SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA4D 6163 65BA 5044" /* .DeclNet.Mace.PD */ + $"4D4D 6163 6545 6E65 74BA 000E 4368 7269" /* MMaceEnet...Chri */ + $"7320 5065 7465 7273 656E 0002 3132 000D" /* s Petersen..12.. */ + $"5044 4D4D 6163 6545 6E65 742E 6100 0000" /* PDMMaceEnet.a... */ + $"004D 4D61 6B65 2074 6865 2072 6563 6569" /* .MMake the recei */ + $"7665 2068 616E 646C 6572 2069 676E 6F72" /* ve handler ignor */ + $"6520 7468 6520 7061 636B 6574 2069 6620" /* e the packet if */ + $"7468 6572 6520 7761 7320 6120 4D61 6365" /* there was a Mace */ + $"206F 7665 7272 756E 2065 7272 6F72 2E00" /* overrun error.. */ +}; + diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEqu.a b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEqu.a new file mode 100644 index 0000000..f7f5493 --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEqu.a @@ -0,0 +1,335 @@ +; +; File: PDMMaceEqu.a +; +; Contains: Equates for accessing the Ethernet Media Access +; Controller (MACE) for the PDM ENET driver +; +; Written by: Dave Calvert +; +; Copyright: © 1992-1993 by Apple Computer, Inc. All rights reserved. +; +; This file is used in these builds: ROM RISC (PDM ENET) +; +; Change History (most recent first): +; +; 6/2/93 GMR Changed some of the init parameters (back to Mark's equates), +; modified the receive record/status definitions. +; 5/27/93 dwc Added support for AMIC work-around code. +; 5/25/93 dwc Clean up for Alpha. +; 5/4/93 dwc Added debug code to work around AMIC's returning FF's on the +; first read. +; 4/6/93 dwc Added status/packet logging equate. +; 3/24/93 dwc Remove obsolete code and added code to try to recover from +; lowered interrupt level during packet handling. +; 3/5/93 dwc Removed some more debugging code. +; 2/25/93 dwc Enable receive, remove some debug equates. +; 2/24/93 dwc Cleaned up some debug equates, added some more debug equates, +; disabled receive for the PDM D5 ROM build. +; 2/4/93 dwc first checked in +; +; + + ; --------------------------------------------------------- + ; MACE Registers + ; --------------------------------------------------------- +MACERegBase EQU $50F1C000 ; Mace Reg Base on Cyclone + +MACERegs RECORD 0 +MACE_RX_FIFO DS.W 1 ;RD RXData -Read Status first + ORG *+$e +MACE_XMIT_FIFO DS.W 1 ;TX TXData + ORG *+$e +MACE_TX_FRM_CNTRL DS.B 1 ;RD/WR 01=Retry,XMTFCS,AUTOPAD + ORG *+$f +MACE_TX_FRM_STAT DS.B 1 ;RD + ORG *+$f +MACE_TX_RETRY_CNT DS.B 1 ;RD + ORG *+$f +MACE_RX_FRM_CNTRL DS.B 1 ;RD/WR 00 = Not_AutoStripPad + ORG *+$f +MACE_RX_FRM_STAT DS.B 1 ;RD Read 4x to get RX Status of packet + ORG *+$f +MACE_FIFO_FRM_CNT DS.B 1 ;RD Number of frames in FIFO + ORG *+$f +MACE_INT DS.B 1 ;RD_1 Interupt Source bits + ORG *+$f +MACE_INT_MSK DS.B 1 ;RD/WR Interupt Enables + ORG *+$f +MACE_POLL DS.B 1 ;RD Yet another status location + ORG *+$f +MACE_BIU_CNFG DS.B 1 ;RD/WR 20 = normal mode 01 = Soft Reset + ORG *+$f +MACE_FIFO_CNFG DS.B 1 + ORG *+$f +MACE_MAC_CNFG DS.B 1 ;Enables + ORG *+$f +MACE_PLS_CNFG DS.B 1 ;RD/WR 0=Normal Mode + ORG *+$f +MACE_PHY_CNFG DS.B 1 ;RD/WR Reserved,Dude. + ORG *+$f +MACE_CHIP_ID_LOW DS.B 1 ;RD Just Reads ID + ORG *+$f +MACE_CHIP_ID_HIGH DS.B 1 ;RD Just Reads ID + ORG *+$f +MACE_ADDR_CNFG DS.B 1 ;RD/WR 04=Phy_Addr, 02=Log_Addr + ORG *+$1f +MACE_LOG_ADDR DS.B 1 ;Load with 6 Zeros + ORG *+$f +MACE_PHY_ADDR DS.B 1 ;Load with Address + ORG *+$2f +MACE_MISSED_PKT_CNT DS.B 1 ;RD + ORG *+$4f +MACE_USER_TEST_REG DS.B 1 ; + ENDR +; +; MACE Interrupt Reg. & Int. Reg. Mask Bit defines +; MACE Int. Reg - Read/Clear; MACE Int. Mask Reg. - Read/Write +; +BABL EQU 6 ; Babble, Xmit timeout error +CERR EQU 5 ; Signal Quality Error (SQE), xmit +RCVCO EQU 4 ; Receive Collision Cnt Overflow +MPCO EQU 2 ; Missed Pkt Cnt Overflow +RCVINT EQU 1 ; Rcv int +XMTINT EQU 0 ; Xmit int + ; mask to disable all MACE ints +; +; MACE Poll register bits +; + +TDTREQ EQU 6 ; Transmit data request +RTDREQ EQU 5 ; Receive data request +;========================================================================================== +; _SETTHEINTMASK +; +; Macro for setting the interrupt level to an arbitrary level. Pass the level in +; a Data register. +;========================================================================================== + + MACRO + _SETTHEINTMASK &sReg + move.w SR,-(SP) + or.w &sReg,(SP) + move.w (SP)+,SR + ENDM + + +MaceIntMask EQU (1< max pkt, used for Recv DMA cnt + +AddrPROM EQU $50F08000 ; 32 bit address of address PROM + +CntRegMask EQU $0001ffff ; Ignore upper 15 bits + +nobuff EQU -2 ; no xmit buffer available + +;•••••••••••••••• Network Statistics +NetStats RECORD 0 ; network management stats. +TxOK DS.L 1 ; frames transmitted OK +sCollFrame DS.L 1 ; single collision frames +mCollFrame DS.L 1 ; multiple collision frames +CollFrame DS.L 1 ; collision frames +DefTx DS.L 1 ; deferred transmissions +LateColl DS.L 1 ; late collisions +ExcessColl DS.L 1 ; excessive collisions +ExcessDef DS.L 1 ; excessive defferals +InMACTxErr DS.L 1 ; internal MAC transmit errors +RxOK DS.L 1 ; frames received OK +MultiRxOK DS.L 1 ; multicast frames recd OK +BroadRxOK DS.L 1 ; broadcast frames recd OK +FCSerr DS.L 1 ; frame check sequence errors +FAerr DS.L 1 ; frame alignment errors +MPerr DS.L 1 ; missed packet errors +Size EQU * + ENDR + +;•••••••••••••••• General Equates +TalliesPerSec EQU 5000000 ; number of timer ticks/second +TxMaxRetries EQU 4 ; max attempts to retry aborted xmits +Max_Tx_Packets EQU 16 ; maximum # of chained Tx packets +Min_Pkt_Size EQU 60 ; minimum packet size +Min_Rx_Buffs EQU 2 ; minimum # of recv descriptors/buffers +Max_Pkt_Size EQU 1518 ; maximum packet size (inc. CRC) +EOL_Bit EQU 0 ; end-of-link bit + +;•••••••••••••••• For GetMemory call +Locked EQU 0 ; want locked memory +Contig EQU 1 ; want contiguous memory +CacheOff EQU 2 ; want non-cacheable memory + +;•••••••••••••••• Initialization Parameters +MACEInitParms RECORD 0 +RecvRtn DS.l 1 ; address of Ethernet receive routine +RecvPrms DS.l 1 ; parms to pass @ receive +XmitRtn DS.l 1 ; address of Ethernet xmit complete routine +XmitPrms DS.l 1 ; parms to pass @ xmit complete +MACECfgPtr DS.l 1 ; ptr to MACE config record +Dot3NetStats DS.l 1 ; ptr to 802.3 statistics array +LAPMIBNetStats DS.l 1 ; ptr to LAP MIB statistics array +EnetAddr DS.l 1 ; ptr to ethernet address +FastMoveRtn DS.l 1 ; ->proc to move memory FAST +IPSize EQU * + ENDR + +;•••• Parms passed to .ENET "RecvRtn" +RcvParms RECORD {A6Link} +Size EQU * ; no local vars +A6Link DS.L 2 ; saved A6 and return addr +Parm DS.L 1 ; parm passed to MaceInit +PktLen DS.L 1 ; pkt length +PktStat DS.L 1 ; pkt status +PktData DS.L 1 ; ptr to packet data + +; Byte 0-1: Receive Status (Bits 15-0) +; Bits 15-7,3-0 : reserved, read as 0's +; Bits 6-4 : Recv Message Status bits +; RcvCLSN EQU 6 ; late collision during recv +; RcvFRAM EQU 5 ; frame error, non-integer # of bytes +; RcvFCS EQU 4 ; frame check sequence error +ParmsSz EQU * - Parm ; len of passed parms + ENDR + +Configrsrc EQU 'ecfg' ; rsrc type for MACE config data rsrc + +; Mace Configuration Record +MACECfg RECORD 0 ; Config values from config rsrc +MACECfgVers DS.w 1 ; record version +MACEBase DS.l 1 ; Base address of MACE +EnetPROM DS.l 1 ; base address of Address Prom +XmitFrmCtl DS.b 1 ; MACE transmit frame control register value +RecvFrmCtl DS.b 1 ; MACE receive frame control register value +FIFOCfgCtl DS.b 1 ; MACE xmit/recv fifo config control register value +MACCfgCtl DS.b 1 ; MACE MAC config control register value + ; The following are optional values; ignored if zero +EnetAddr DS.b 6 ; Alternate Ethernet Address, overrides Address PROM +XmitBuffs DS.w 1 ; Alternate number of transmit buffers +RecvBuffs DS.w 1 ; Alternate number of receive buffers +RecvChains DS.w 1 ; Alternate number of receive "chains" +CfgSize EQU * + ENDR diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEqu.a.idump b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEqu.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEqu.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEqu.a.rdump b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEqu.a.rdump new file mode 100644 index 0000000..858d9f4 --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/PDMMaceEqu.a.rdump @@ -0,0 +1,31 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0000 2A2A 2A2A 2A2A" /* ..Monaco..****** */ + $"2A2A 2A2A 2A2A 2A2A 2A2A 2A0D 3B09 4571" /* ***********.;.Eq */ + $"7561 0006 0004 0054 003E 018F 0239 0054" /* ua.....T.>...9.T */ + $"003E 018F 0239 A832 523C 0000 0153 0000" /* .>...9.2R<...S.. */ + $"01E4 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"0054 003E 018F 0239 0054 003E 018F 0239" /* .T.>...9.T.>...9 */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"A4F1 0AD6 3FE5 3230 0004 0000 0000 0000" /* ....?.20........ */ + $"0000 A933 73A3 A933 73A3 A796 71C8 0006" /* ...3s..3s...q... */ + $"D7AA 0000 0003 000B 3153 7570 6572 4D61" /* ........1SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA4D 6163 65BA 5044" /* .DeclNet.Mace.PD */ + $"4D4D 6163 6545 6E65 74BA 000E 4368 7269" /* MMaceEnet...Chri */ + $"7320 5065 7465 7273 656E 0002 3130 000C" /* s Petersen..10.. */ + $"5044 4D4D 6163 6545 7175 2E61 0000 0000" /* PDMMaceEqu.a.... */ + $"6D43 6861 6E67 6564 2073 6F6D 6520 6F66" /* mChanged some of */ + $"2074 6865 2069 6E69 7420 7061 7261 6D65" /* the init parame */ + $"7465 7273 2028 6261 636B 2074 6F20 4D61" /* ters (back to Ma */ + $"726B 2773 2065 7175 6174 6573 292C 206D" /* rk's equates), m */ + $"6F64 6966 6965 6420 7468 6520 7265 6365" /* odified the rece */ + $"6976 6520 7265 636F 7264 2F73 7461 7475" /* ive record/statu */ + $"7320 6465 6669 6E69 7469 6F6E 732E 00" /* s definitions.. */ +}; + diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/VersionPDMMaceEnet.a b/DeclData/DeclNet/Mace/PDMMaceEnet/VersionPDMMaceEnet.a new file mode 100644 index 0000000..4e0c7cf --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/VersionPDMMaceEnet.a @@ -0,0 +1,25 @@ +; +; File: VersionMaceEnet.a +; +; Contains: Version information for Mace Ethernet driver for PDM +; +; Written by: Dave Calvert +; +; Copyright: © 1992-1993 by Apple Computer, Inc., all rights reserved. +; +; Change History (most recent first): +; +; 5/27/93 dwc Make Rev D8. +; 2/24/93 dwc Made version zero for the ROM based version. +; 2/4/93 dwc first checked in +; +; To Do: +; + + PRINT PUSH, GEN, NOMDIR +; +; ••• DO NOT CHANGE parm 9, "MaceEnet", driver code depends on that string! +; + VERSION 'PDM MACE DMA Ethernet Driver', 0, 0, 0, development, 8, '1993', 'q4', MaceEnet + + PRINT POP diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/VersionPDMMaceEnet.a.idump b/DeclData/DeclNet/Mace/PDMMaceEnet/VersionPDMMaceEnet.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/VersionPDMMaceEnet.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Mace/PDMMaceEnet/VersionPDMMaceEnet.a.rdump b/DeclData/DeclNet/Mace/PDMMaceEnet/VersionPDMMaceEnet.a.rdump new file mode 100644 index 0000000..f0ff428 --- /dev/null +++ b/DeclData/DeclNet/Mace/PDMMaceEnet/VersionPDMMaceEnet.a.rdump @@ -0,0 +1,26 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0069 6768 7473 2072" /* ..Monaco.ights r */ + $"6573 6572 7665 642E 0D3B 0D3B 0943 6861" /* eserved..;.;.Cha */ + $"6E67 0006 0004 019A 0485 022C 06FA 019A" /* ng.........,.... */ + $"0485 022C 06FA A82A 4B00 0000 0000 0000" /* ...,...*K....... */ + $"0000 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"019A 0485 022C 06FA 019A 0485 022C 06FA" /* .....,.......,.. */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"2FEA 3453 3FE5 3230 0004 0000 0000 0000" /* /.4S?.20........ */ + $"0000 A933 73A3 A933 73A3 A796 71C8 0006" /* ...3s..3s...q... */ + $"D7AA 0000 0004 0003 3153 7570 6572 4D61" /* ........1SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA4D 6163 65BA 5044" /* .DeclNet.Mace.PD */ + $"4D4D 6163 6545 6E65 74BA 000E 4368 7269" /* MMaceEnet...Chri */ + $"7320 5065 7465 7273 656E 0001 3300 1456" /* s Petersen..3..V */ + $"6572 7369 6F6E 5044 4D4D 6163 6545 6E65" /* ersionPDMMaceEne */ + $"742E 6100 0000 000C 4D61 6B65 2052 6576" /* t.a.....Make Rev */ + $"2044 382E 00" /* D8.. */ +}; + diff --git a/DeclData/DeclNet/Mace/VersionMaceEnet.a b/DeclData/DeclNet/Mace/VersionMaceEnet.a new file mode 100644 index 0000000..2b2e8aa --- /dev/null +++ b/DeclData/DeclNet/Mace/VersionMaceEnet.a @@ -0,0 +1,45 @@ +; +; File: VersionMaceEnet.a +; +; Contains: Version information for Mace Ethernet driver for Cyclone +; +; Written by: Mark A. Law +; +; Copyright: © 1991-1993 by Apple Computer, Inc., all rights reserved. +; +; Change History (most recent first): +; +; 7/26/93 mal Changed vers to 1.0.1d1 for first bug fix after 1.0 release. +; 6/17/93 kc Roll in Ludwig. +; 6/14/93 mal Changed version to 1.0. +; 6/14/93 kc Roll in Ludwig. +; 5/22/93 mal Change vers to 1.0b7q1 since drvr did change since b6. +; 5/3/93 mal Updated to 1.0b6q4 +; 5/1/93 mal Changed name to 'Built-In Ethernet Driver' and vers to 1.0b6q1. +; 3/21/93 mal Updated to b3q2 +; 2/17/93 mal Updated to 1.0a10q4 +; <2> 1/27/93 mal Updated to 1.0a9q3 +; 12/4/92 mal Updated to 1.0a8q3. +; 11/19/92 mal Updated to 1.0a7. +; 11/10/92 mal Updated to 1.0a6q1. +; 10/30/92 mal Updated to 1.0a5 +; 10/26/92 mal Updated to 1.0a4q4 +; 10/13/92 mal changed to 1.0d10q4 +; <1> 10/6/92 GDW New location for ROMLink tool. +; 9/14/92 mal changed to 1.0d9q6 +; 7/25/92 mal Changed to 1.0d9q4 +; 6/22/92 mal Updated to 1.0d8q1. +; 4/30/92 mal +; 4/28/92 mal Chg to 1.0D5q1 +; 3/23/92 mal Chg to 1.0d3q4 for 1.0D3 ROM bld. +; +; To Do: +; + + PRINT PUSH, GEN, NOMDIR +; +; ••• DO NOT CHANGE parm 9, "MaceEnet", driver code depends on that string! +; + VERSION 'Built-In Ethernet Driver', 1, 0, 1, development, 1, '1992-1993', '', MaceEnet + + PRINT POP diff --git a/DeclData/DeclNet/Mace/VersionMaceEnet.a.idump b/DeclData/DeclNet/Mace/VersionMaceEnet.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Mace/VersionMaceEnet.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Mace/VersionMaceEnet.a.rdump b/DeclData/DeclNet/Mace/VersionMaceEnet.a.rdump new file mode 100644 index 0000000..d647e04 --- /dev/null +++ b/DeclData/DeclNet/Mace/VersionMaceEnet.a.rdump @@ -0,0 +1,28 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0069 6768 7473 2072" /* ..Monaco.ights r */ + $"6573 6572 7665 642E 0D3B 0D3B 0943 6861" /* eserved..;.;.Cha */ + $"6E67 0006 0004 00CE 0036 01BF 02EF 0055" /* ng.......6.....U */ + $"002F 0146 02E8 A879 725C 0000 0000 0000" /* ./.F...yr\...... */ + $"0000 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"00CE 0036 01BF 02EF 0055 002F 0146 02E8" /* ...6.....U./.F.. */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"AB77 FA68 3FE5 3230 0004 0000 0000 0000" /* .w.h?.20........ */ + $"0000 A933 739B A933 739B A6F7 B0C6 0078" /* ...3s..3s......x */ + $"BC36 0000 0005 0011 2553 7570 6572 4D61" /* .6......%SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA4D 6163 65BA 000E" /* .DeclNet.Mace... */ + $"4368 7269 7320 5065 7465 7273 656E 0002" /* Chris Petersen.. */ + $"3130 0011 5665 7273 696F 6E4D 6163 6545" /* 10..VersionMaceE */ + $"6E65 742E 6100 0000 003C 4368 616E 6765" /* net.a.... 10/26/92 mal Updated to ESD's latest version. +; 10/26/92 mal Updated SNMP statistic arrays to latest versions. +; <1> 10/6/92 GDW New location for ROMLink tool. +; + +LAPMIBStats RECORD 0,increment +ifVersion DS.L 1 ; Version of LinkStats we support +ifDescr DS.B 256 ; String with info about interface +ifType DS.L 1 ; <8> Change to a Long. Code with type of interface +ifMaxMTU DS.L 1 ; <8> Change to a Long. Largest size of IP datagram that can be tx/recv +ifSpeed DS.L 1 ; Bandwidth in bits/second +ifPhysAddress DS.B 32 ; Interface address +ifAdminStatus DS.L 1 ; <8> Change to a Long. Desired state (1 = up, 2 = down, 3 = testing) +ifOperStatus DS.L 1 ; <8> Change to a Long. Current state (1 = up, 2 = down, 3 = testing) +ifLastChange DS.L 1 ; SysTicks when interface entered current operation state +ifInOctets DS.L 1 ; Total nbr bytes received including framing chars +ifInUcastPkts DS.L 1 ; Nbr of unicast packets received +ifInNUcastPkts DS.L 1 ; Nbr of broad/multi cast packets received +ifInDiscards DS.L 1 ; Nbr of overwrites that occured (NOT USED) +ifInErrors DS.L 1 ; Nbr of pkts recv which contain error +ifInUnknownProtos DS.L 1 ; Nbr of pkts recv discarded cuz of unknown protocol +ifOutOctets DS.L 1 ; Total nbr bytes tx including framing chars +ifOutUcastPkts DS.L 1 ; Nbr of unicast packets tx +ifOutNUcastPkts DS.L 1 ; Nbr of broad/multi cast packets tx +ifOutDiscards DS.L 1 ; Nbr tx pkts discarded (NOT USED) +ifOutErrors DS.L 1 ; Nbr tx pkts not sent due to error +ifOutQLen DS.L 1 ; Current nbr of packets in output queue +LAPMIBStatsSz EQU * + ENDR + +; ifAdminStatus and ifOperStatus +ifStatusUp EQU 1 +ifStatusDown EQU 2 +ifStatusTesting EQU 3 + +; IfTypes +other EQU 1 ; none of the following +regular1822 EQU 2 +hdh1822 EQU 3 +ddn_x25 EQU 4 +rfc877_x25 EQU 5 +ethernet_csmacd EQU 6 +iso88023_csmacd EQU 7 +iso88024_tokenBus EQU 8 +iso88025_tokenRing EQU 9 +iso88026_man EQU 10 +starLan EQU 11 +proteon_10Mbit EQU 12 +proteon_80Mbit EQU 13 +hyperchannel EQU 14 +fddi EQU 15 +lapb EQU 16 +sdlc EQU 17 +ds1 EQU 18 ; T-1 +e1 EQU 19 ; european equivalent of T-1 +basicISDN EQU 20 +primaryISDN EQU 21 +propPointToPointSerial EQU 22 ; proprietary serial +ppp EQU 23 +softwareLoopback EQU 24 +eon EQU 25 ; CLNP over IP +ethernet_3Mbit EQU 26 +nsip EQU 27 ; XMS over IP +slip EQU 28 ; generic SLIP +ultra EQU 29 ; ULTRA technologies +ds3 EQU 30 ; T-3 +sip EQU 31 ; SMDS +frame_relay EQU 32 + +; +; EtherNet (802.3) SNMP equates +; +Dot3Entry Record 0,increment +dot3Version DS.l 1 ; Version of LapDot3 entry that we support +dot3Index DS.l 1 ; ifIndex for this driver +dot3InitializeMac DS.l 1 ; Init status (1 = inited, 2 = uninited) +dot3SubLayerStatus DS.l 1 ; Op status of the MAC sublayer (1 = enabled, 2 = disabled) +dot3MulticastReceiveStatus DS.l 1 ; Multicast receive status (1 = enabled, 2 = disabled) +dot3TxEnabled DS.l 1 ; MAC frame tx state (1 = enabled, 2 = disabled) +dot3TestTdrValue DS.l 1 ; Time between TDR start/end +Dot3EntrySz EQU * ; End of Dot3Entry + ENDR + +Dot3StatsEntry RECORD 0,increment +dot3StatsVersion DS.l 1 ; Version number +dot3StatsIndex DS.l 1 ; Same as ifIndex (to be left at zero) +dot3StatsAlignmentErrors DS.l 1 +dot3StatsFCSErrors DS.l 1 +dot3StatsSingleCollisionFrames DS.l 1 +dot3StatsMultipleCollisionFrames DS.l 1 +dot3StatsSQETestErrors DS.l 1 +dot3StatsDeferredTransmissions DS.l 1 +dot3StatsLateCollisions DS.l 1 +dot3StatsExcessiveCollisions DS.l 1 +dot3StatsInternalMacTransmitErrors DS.l 1 +dot3StatsCarrierSenseErrors DS.l 1 +dot3StatsExcessiveDeferrals DS.l 1 +dot3StatsFrameTooLongs DS.l 1 +dot3StatsInRangeLengthErrors DS.l 1 +dot3StatsOutOfRangeLengthFields DS.l 1 +dot3StatsInternalMacReceiveErrors DS.l 1 +Dot3StatsEntrySz EQU * + ENDR + +Dot3CollEntry RECORD 0,increment +dot3CollVersion DS.l 1 ; Version number +dot3CollIndex DS.l 1 ; Same as ifIndex (to be left at zero) +dot3CollCount DS.l 1 +dot3CollFrequencies DS.l 1 +Dot3CollEntrySz EQU * + ENDR + +; +; TokenRing (802.5) SNMP equates +; +Dot5Entry Record 0,increment +dot5Version DS.l 1 ; Version of LapDot5 entry that we support +dot5Index DS.l 1 ; ifIndex for this driver +dot5Commands DS.l 1 ; always reads as no_op (1) +dot5RingStatus DS.l 1 +dot5RingState DS.l 1 +dot5RingOpenStatus DS.l 1 +dot5RingSpeed DS.l 1 +dot5UpStream DS.l 1 +dot5ActMonParticipate DS.l 1 +dot5Functional DS.l 1 +Dot5EntrySz EQU * ; End of Dot5Entry + ENDR + +Dot5StatsEntry RECORD 0,increment ; •• +dot5StatsVersion DS.l 1 ; Version number +dot5StatsIndex DS.l 1 ; Same as ifIndex (to be left at zero) +dot5StatsLineErrors DS.l 1 +dot5StatsBurstErrors DS.l 1 +dot5StatsACErrors DS.l 1 +dot5StatsAbortTransErrors DS.l 1 +dot5StatsInternalErrors DS.l 1 +dot5StatsLostFrameErrors DS.l 1 +dot5StatsReceiveCongestions DS.l 1 +dot5StatsFrameCopiedErrors DS.l 1 +dot5StatsTokenErrors DS.l 1 +dot5StatsSoftErrors DS.l 1 +dot5StatsHardErrors DS.l 1 +dot5StatsSignalLoss DS.l 1 +dot5StatsTransmitBeacons DS.l 1 +dot5StatsRecoverys DS.l 1 +dot5StatsLobeWires DS.l 1 +dot5StatsRemoves DS.l 1 +dot5StatsSingles DS.l 1 +dot5StatsFreqErrors DS.l 1 +Dot5StatsEntrySz EQU * + ENDR + +Dot5TimerEntry RECORD 0,increment ; •• +dot5TimerVersion DS.l 1 ; Version number +dot5TimerIndex DS.l 1 ; Same as ifIndex (to be left at zero) +dot5TimerReturnRepeat DS.l 1 +dot5TimerHolding DS.l 1 +dot5TimerQueuePDU DS.l 1 +dot5TimerValidTransmit DS.l 1 +dot5TimerNoToken DS.l 1 +dot5TimerActiveMon DS.l 1 +dot5TimerStandbyMon DS.l 1 +dot5TimerErrorReport DS.l 1 +dot5TimerBeaconTransmit DS.l 1 +dot5TimerBeaconReceive DS.l 1 +Dot5TimerEntrySz EQU * + ENDR + +; dot3InitializeMac +dot3initialized EQU 1 +dot3uninitialized EQU 2 + +; dot3SubLayerStatus, dot3MulticastReceiveStatus +dot3enabled EQU 1 +dot3disabled EQU 2 + +; dot3TxEnabled, dot5ActMonParticipate +dot_true EQU 1 +dot_false EQU 2 + +; dot5Commands +dot5no_op EQU 1 +dot5open EQU 2 +dot5reset EQU 3 +dot5close EQU 4 + +; dot5RingState +opened EQU 1 +closed EQU 2 +opening EQU 3 +closing EQU 4 +openFailure EQU 5 +ringFailure EQU 6 + +; dot5RingOpenStatus +noOpen EQU 1 +badParam EQU 2 +lobeFailed EQU 3 +signalLoss EQU 4 +insertionTimeout EQU 5 +ringFailed EQU 6 +beaconing EQU 7 +duplicateMAC EQU 8 +requestFailed EQU 9 +removeReceived EQU 10 +ringopen EQU 11 + +; dot5RingSpeed +unknown EQU 1 +oneMegabit EQU 2 +fourMegabit EQU 3 +sixteenMegabit EQU 4 + +SNMPVersion EQU $100 ; used for LAPMIBStats, Dot3Stats, Dot3Entry diff --git a/DeclData/DeclNet/SNMPLAP.a.idump b/DeclData/DeclNet/SNMPLAP.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/SNMPLAP.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/SNMPLAP.a.rdump b/DeclData/DeclNet/SNMPLAP.a.rdump new file mode 100644 index 0000000..85a0335 --- /dev/null +++ b/DeclData/DeclNet/SNMPLAP.a.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"000C 4D6F 6E61 636F 006D 656E 7420 5072" /* ..Monaco.ment Pr */ + $"6F74 6F63 6F6C 2065 7175 6174 6573 2066" /* otocol equates f */ + $"6F72 0007 0004 0018 FBD1 025B FDD1 0018" /* or.........[.... */ + $"FBD1 025B FDD1 A711 CA40 0000 0107 0000" /* ...[.....@...... */ + $"0141 0000 0000 0100" /* .A...... */ +}; + +data 'MPSR' (1008) { + $"0018 FBD1 025B FDD1 0018 FBD1 025B FDD1" /* .....[.......[.. */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"C58C 8468 3FE5 3230 0004 0000 0000 0000" /* ...h?.20........ */ + $"0000 A933 7396 A933 7396 A6F7 AE5C 0078" /* ...3s..3s....\.x */ + $"2B21 0000 0005 0005 2053 7570 6572 4D61" /* +!...... SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA00 0E43 6872 6973" /* .DeclNet...Chris */ + $"2050 6574 6572 7365 6E00 0133 0009 534E" /* Petersen..3..SN */ + $"4D50 4C41 502E 6100 0000 0020 5570 6461" /* MPLAP.a.... Upda */ + $"7465 6420 746F 2045 5344 2773 206C 6174" /* ted to ESD's lat */ + $"6573 7420 7665 7273 696F 6E2E 00" /* est version.. */ +}; + diff --git a/DeclData/DeclNet/Sonic/Sonic.a b/DeclData/DeclNet/Sonic/Sonic.a new file mode 100644 index 0000000..316504b --- /dev/null +++ b/DeclData/DeclNet/Sonic/Sonic.a @@ -0,0 +1,1378 @@ +; +; File: Sonic.a +; +; Contains: Sonic-specific support routines +; +; Written by: Sean Findley +; +; Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved. +; +; Change History (most recent first): +; +; <1> 10/6/92 GDW New location for ROMLink tool. +; <1> 6/12/92 RLM first checked in +; 02/07/92 jmp (jmp,H2/BG/SJF,Z3) Modifications for passing in SonicPtr instead +; of storing it. +; <1> 2/4/92 mal first checked in +; ——————————————————————————————————————————————————————————————————————————————————————— +; Pre-Horror ROM comments begin here. +; ——————————————————————————————————————————————————————————————————————————————————————— +; <2> 4/21/91 CCH Rolled in Sean Findley's changes. +; <1> 12/14/90 JK Added to builds +; +; To Do: +; + +;•••••••••••••••• SONIC.a +; written by Sean J. Findley Jan. 1990 + + PRINT NOMDIR,NOMCALL + + MACRO + Set10 + SMOVE #(TalliesPerSec*10) MOD 65536,Timer0(A2) + ; set lower 16 bits of counter + SMOVE #(TalliesPerSec*10) DIV 65536,Timer1(A2) + ; set upper 16 bits of counter + MOVE.L #(1< SONIC registers. +Set10Seconds PROC ENTRY + WITH SONICRegs + Set10 ; set timer for 10 seconds + RTS + ENDPROC +;•••••••••••••••• +; Restart SONIC. Assumes A2-> SONIC registers. +RestartSONIC PROC EXPORT ; take SONIC out of reset + WITH SONICRegs + MOVEQ #0,D0 + SMOVE D0,Command(A2) ; take out of reset +@wait + SMOVE Command(A2),D0 + BTST #SoftReset,D0 + BNE.S @wait ; wait for it + + Set10 ; set timer for 10 seconds + + MOVEQ #(1< SONIC registers + +ResetSONIC PROC EXPORT ; + WITH SONICRegs + MOVEQ #(1<SONIC chip +; Uses D1 + +SONICSync PROC ENTRY + WITH SONICRegs + SUB.L D1,D1 ; clear 32 bits + BSET D0,D1 + SMOVE D1,Command(A2) +@waitloop + SMOVE Command(A2),D1 + BTST D0,D1 + BNE.S @waitloop ; wait for command to complete + RTS + ENDWITH + ENDPROC + +;•••••••••••••••• +; Link to the end of recv descriptor list. +; A1->new entry, uses A0 +LinkToRxList PROC ENTRY + + MOVE.L A2,-(SP) + + SUB.L D0,D0 + SMOVE D0,Rxpkt.status(A1) ; setup to receive + MOVEQ #(1<last descriptor ptr + MOVEA.L (A0),A2 ; A2->last descriptor + + MOVE.L A1,(A0) ; update last pointer + MOVE.L A1,D0 + + IF MMU THEN + SUB.L RDAptr+llg,D0 + ADD.L RDAptr+lph,D0 ; D0=physical address + ENDIF + + SMOVE D0,Rxpkt.link(A2) ; link us to the end of the list + + LEA NextRxDesc,A0 + TST.L (A0) ; were we out of buffers? + BNE.S @done ; no + + MOVE.L A1,(A0) ; set next recv desc to poll +@done + MOVEA.L (SP)+,A2 + RTS + ENDPROC + +;•••••••••••••••• SONIC Free Buffer +; void SONICFREEBUFF(desc) +SONICFREEBUFF PROC EXPORT + +parms RECORD 4 +RxDescriptor DS.L 1 ; ->to RDA descriptor to free + ENDR + + WITH parms + + MOVEA.L IntDRtn,A0 ; A0->proc to disable interrupts + JSR (A0) ; call it + + MOVEA.L RxDescriptor(SP),A1 ; A1->descriptor to be freed + + MOVE.L A2,-(SP) ; save reg + MOVE.L D0,-(SP) ; save SR returned by proc + + ST Rxpkt.isFree(A1) ; mark this desc to be freed + + LEA FreeQ,A2 ; A2->to be freed queue + CMPA.L (A2),A1 ; is this entry at the front? + BNE.S @xit ; that's all we can do now +; free as many descriptors as possible starting at the front of the queue +@FreeDesc + TST.B Rxpkt.isFree(A1) ; can we free this desc? + BEQ.S @done ; no, all done + + MOVE.L Rxpkt.nextRD(A1),(A2) ; set queue head to next desc if any + + BSR.S doFreeDesc ; give descriptor back to SONIC + + MOVE.L (A2),D0 ; any more to free? + BEQ.S @done ; all done + + MOVEA.L D0,A1 ; A1->next descriptor to free + BRA.S @FreeDesc ; try the next one +@done + TST.L (A2)+ ; see if queue has been emptied + BNE.S @xit ; is not + CLR.L (A2) ; clear tail pointer too +@xit + MOVEA.L IntERtn,A0 ; A0->proc to enable interrupts + JSR (A0) ; do it + ADDQ.W #4,SP ; strip SR parm + + MOVEA.L (SP)+,A2 ; get back reg + RTS +doFreeDesc + SMOVE Rxpkt.in_use(A1),D0 ; see if SONIC still using desc + TST.W D0 + BEQ LinkToRxList ; put desc on receive list +; put desc on hold list +; If the descriptor might still be in use by the SONIC. This can happen if no other descriptors +; have been freed prior to this one OR we have not received any packets since freeing other +; descriptors prior to this one. + LEA HoldDescHdr,A0 ; A0->hold list header + MOVE.L (A0),Rxpkt.nextRD(A1) ; link prev to our next + MOVE.L A1,(A0) ; put desc on head of list + RTS + + ENDWITH + ENDPROC + + +;•••••••••••••••• SONIC Interrupt Handler +SONICInterrupt PROC ENTRY + +OurStack RECORD {A6Link} ; +Sz EQU * ; +A6Link DS.L 2 ; +SONICPtr DS.L 1 ; + ENDR ; + +; void SONICInterrupt() + + WITH SONICRegs + LINK A6,#OurStack.Sz ; + MOVEM.L A2-A3, -(SP) ; save those we use +@more + MOVEA.L OurStack.SONICptr(A6),A2 ; A2->SONIC regs + + SMOVE Int_Status(A2),D0 ; get ISR from SONIC + MOVE.W D0,D1 ; save it + MOVE.W #(1< + RTS + +IntTable +; Each interrupt is called with its respective status bit set in D2. It has the option of +; when to clear it in the ISR. + + DC.W RFO-IntTable ; receive FIFO overrun + DC.W MP-IntTable ; MP tally counter rollover + DC.W FAE-IntTable ; FAE tally counter rollover + DC.W CRC-IntTable ; CRC tally counter rollover + DC.W RBAE-IntTable ; receive buffer overflow + DC.W RBE-IntTable ; receive buffers exhausted + DC.W RDE-IntTable ; receive descriptors exhausted + DC.W TC-IntTable ; timer complete + DC.W TXER-IntTable ; transmit error + DC.W TXDN-IntTable ; transmit complete + DC.W PKTRX-IntTable ; packet received + DC.W PINT-IntTable ; programmable interrupt + DC.W LCD-IntTable ; load CAM done + DC.W HBL-IntTable ; heartbeat lost + DC.W Reserved-IntTable ; reserved + DC.W Reserved-IntTable ; reserved +;________________ +RFO ; receive FIFO overrun +MACRxError + MOVEA.L NetStatp, A0 ; Get pointer to array + ADDQ.L #1, NetStats.MPerr(A0) ; Increment statistic + RTS +;________________ +MP ; MP tally counter rollover + RTS +;________________ +FAE ; FAE tally counter rollover + RTS +;________________ +CRC ; CRC tally counter rollover + RTS +;________________ +RBAE ; receive buffer overflow + BRA.S MACRxError ; report receive error +;________________ +RBE ; receive buffers exhausted + BRA.S MACRxError ; report receive error +;________________ +RDE ; receive descriptors exhausted + RTS +;________________ +TC ; timer complete +; This interrupt is used to fix a bug in the SONIC. If a packet has not been received in +; the last 10 seconds and there ARE receive descriptors available, AND the current RDA +; pointer is at the End Of List, reset the SONIC. + + + SMOVE Silicon_Rev(A2),D0 ; check SONIC version + CMPI.W #3,D0 + BHI.S @done ; do nothing if rev 4 or later + + MOVE.L NextRxDesc,D0 ; see if descriptors available + BEQ Set10Seconds ; none available, user is very slow to free buffers + SMOVE Current_RDA(A2),D0 + BTST #EOL_Bit,D0 + BEQ Set10Seconds ; SONIC is not stuck + SMOVE Int_Status(A2),D0 + BTST #RecdPkt,D0 ; make sure a packet did'nt arrive + BNE Set10Seconds ; process it if so +; SONIC is in a loop, reset it and get going again + SMOVE Command(A2),-(SP) ; save current command status + + MOVE.L #1<retry count + + SMOVE Int_Status(A2),D0 ; check for errors + ANDI.W #(1<xmitted TDA + MOVE.L TRANParms,-(SP) ; pointer to xmit complete parms + MOVEM.L A3,-(SP) ; pass ptr to xmit buffer descriptor + MOVE.L TRANProc,A0 ; xmit completion routine address + JSR (A0) ; call it + ADDQ.W #8,SP ; strip trans parms + + SMOVE TxPkt.status(A3),D0 ; get back status + ANDI.W #$F800, D0 + MOVEA.L NetStatp, A0 ; Get pointer to array + CMPI.W #$0800, D0 ; were there any? + BLO.S @ok ; none + BHI.S @many ; more than one + ADDQ.L #1, NetStats.sCollFrame(A0) ; Increment statistic + BRA.S @coll + +@many + ADDQ.L #1, NetStats.mCollFrame(A0) ; inc multiple collision frame + +@coll + ADDQ.L #1, NetStats.CollFrame(A0) ; inc collision count +@ok + SMOVE TxPkt.status(A3),D1 ; get back status + CMPI.W #(1<this TDA link field + + SMOVE (A3),D0 ; fetch link field + BTST #EOL_Bit,D0 + BNE.S @done ; this is the end..my friend + + SMOVE Upper_TDA(A2),D1 + SWAP D1 + MOVE.W D0,D1 + + IF MMU THEN + SUB.L TxTDAptr+lph,D1 + ADD.L TxTDAptr+llg,D1 ; D1=logical address + ENDIF + + MOVEA.L D1,A3 ; A3->next TDA in xmitted chain + + MOVEA.L IntERtn,A1 + JSR (A1) ; reenable interrupts + + BRA @doTxComp +@done + MOVEA.L IntERtn,A1 + JSR (A1) ; reenable interrupts + ADDQ.W #4,SP ; strip old SR + + RTS +;________________ +PKTRX ; packet received + MOVE.L HoldDescHdr,D0 ; any descriptors held? + BEQ.S checkDesc ; none to process + +; Free available receive descriptors from the hold list. + + LEA HoldDescHdr,A3 ; A3->prev link + MOVEA.L D0,A1 ; A1->held descriptor +@chk + MOVE.L Rxpkt.nextRD(A1),D1 ; save forward link + + SMOVE RxPkt.in_use(A1),D0 + TST.W D0 ; desc still in use by the SONIC? + BMI.S @nxt ; yes + + BSR LinkToRxList ; put on receive list + + MOVE.L D1,(A3) ; delete from hold list + MOVEA.L A3,A1 ; keep prev link +@nxt + MOVEA.L A1,A3 ; A3->prev link + MOVEA.L D1,A1 ; A1->next held desc maybe + TST.L D1 + BNE.S @chk ; more to do +checkDesc + MOVE.L NextRxDesc,D0 + BEQ @done + + MOVEA.L D0,A3 ; A3->next active descriptor + + SMOVE RxPkt.status(A3),D0 + TST.W D0 ; at logical end of list? + BEQ @done + + MOVE.L A3,-(SP) ; pass buffer descriptor + MOVE.L RECVparms,-(SP) ; parms ptr for user + SMOVE RxPkt.pkt_ptr1(A3),D0 + SWAP D0 + SMOVE RxPkt.pkt_ptr0(A3),D1 + MOVE.W D1,D0 + + IF MMU THEN + SUB.L RBAptr+lph,D0 + ADD.L RBAptr+llg,D0 ; D0=logical address + ENDIF + + MOVE.L D0,-(SP) ; pointer to packet data + SUB.L D0,D0 + SMOVE RxPkt.byte_count(A3),D0 + MOVE.L D0,-(SP) ; length of packet received + SUB.L D0,D0 + SMOVE RxPkt.status(A3),D0 + MOVE.L D0,-(SP) ; receive status + +; setup pointer to next descriptor + SUB.L D1,D1 + SMOVE Rxpkt.link(A3),D2 ; get lower part of link + BTST #EOL_Bit,D2 ; end of list? + BNE.S @FreeQueue ; yes + SMOVE Upper_RDA(A2),D1 + SWAP D1 ; setup upper part of address + MOVE.W D2,D1 ; setup lower part of address + + IF MMU THEN + SUB.L RDAptr+lph,D1 + ADD.L RDAptr+llg,D1 ; D1=logical address + ENDIF +@FreeQueue +; place descriptor on to-be-freed queue + LEA FreeQ,A1 ; A1->to be freed queue + CLR.L Rxpkt.nextRD(A3) ; clear this desc link field + CLR.B Rxpkt.isFree(A3) ; mark as not freed yet + TST.L (A1)+ ; check queue head + BNE.S @notEmpty ; has entries on it + MOVE.L A3,(A1) ; put this desc on the end of queue + MOVE.L A3,-(A1) ; and on the front as well + BRA.S @doneQueueing ; that's it +@notEmpty + MOVEA.L (A1),A0 ; A0->tail + MOVE.L A3,Rxpkt.nextRD(A0) ; link tail to this desc + MOVE.L A3,(A1) ; put this desc on the end of queue +@doneQueueing + MOVEA.L D1,A3 ; A3->next descriptor maybe + + LEA NextRxDesc,A0 + MOVE.L A3,(A0) ; update for next receive +@doRxCall + MOVEA.L RECVProc,A0 ; addr of receive routine + JSR (A0) ; call it + + MOVE.L (SP)+,D1 ; get back status + LEA 16(SP),SP ; strip other parms + + MOVEA.L NetStatp, A0 ; Get pointer to array + MOVE.W #(1<SONIC registers + + LEA RECVProc,A0 + MOVE.L RECVRtn(A6),(A0) + + LEA RECVParms,A0 + MOVE.L RECVPrms(A6),(A0) + + LEA TRANProc,A0 + MOVE.L TRANRtn(A6),(A0) + + LEA TRANParms,A0 + MOVE.L TRANPrms(A6),(A0) + + LEA IntDRtn,A0 + MOVE.L IntDisable(A6),(A0) + + LEA IntERtn,A0 + MOVE.L IntEnable(A6),(A0) + + LEA NetStatp,A0 + MOVE.L NetStatArray(A6),(A0) + + SUB.L D0,D0 ; clear 32 bits + SMOVE D0,Int_Mask(A2) ; disable SONIC interrupts + + BSET #SoftReset,D0 ; do a software reset on SONIC + SMOVE D0,Command(A2) + + PEA SONICInterrupt ; addr of our interrupt handler + MOVEA.L IntInstall(A6),A0 ; addr of installation proc + JSR (A0) ; install interrupt handler + ADDQ.W #4,SP + +; setup SONIC chip configuration + MOVE.L DataConfig(A6),D0 + SMOVE D0,Data_Config(A2) ; setup data configuration +; setup reception control + SUB.L D0,D0 ; clear 32 bits + BSET #RecvErrors,D0 ; receive CRC errors + + SMOVE Silicon_Rev(A2),D1 + CMPI.W #3,D1 + BLS.S @setBrd ; no runts for rev 3 or earlier + BSET #RecvRunts,D0 ; receive runt packets +@setBrd + BSET #RecvBroadCast,D0 ; receive broadcasts + SMOVE D0,Recv_Control(A2) +; Ensure that descriptors are in the same 64k page + MOVE.L NumRxBuffs(A6),D0 ; calculate control memory size + MULU #Rxpkt.RxRDAsize,D0 ; memory for recv descriptors + + ADDI.L #TxTDAsize * Max_Tx_Packets + RRArecSz + CAMDescSz,D0 + ; xmit descriptors, RRA and CAM + ADD.L MemStart(A6),D0 ; calc ending address + SUBQ.L #1,D0 ; make it inclusive + CLR.W D0 ; trash lower 16 bits + + MOVE.L MemStart(A6),D1 + CLR.W D1 ; get start address page + CMP.L D1,D0 ; see if boundry crossed + BEQ.S @AllocateMem ; proceed if not + + ADDI.L #$10000,D1 ; adjust to 64k boundry + SUB.L MemStart(A6),D1 ; calc adjustment amount + + ADD.L D1,MemStart(A6) ; update pointer + SUB.L D1,MemSize(A6) ; update size +@AllocateMem + +; get memory for TDA + MOVE.L #TxTDAsize * Max_Tx_Packets,D0 + ; mem for TDA (up to 16 packets) + LEA FreeTxTDA,A1 + MOVE.L MemStart(A6),(A1) ; save free txtda ptr + + IF MMU THEN + LEA TxTDAPtr,A1 + BSR @SetAddresses ; set current phys/log addrs + ENDIF + + MOVEA.L MemStart(A6),A1 ; A1->1st TDA + MOVE.L A1,D1 + + IF MMU THEN + SUB.L TxTDAPtr+llg,D1 + ADD.L TxTDAPtr+lph,D1 ; D1=physical address of TDA + ENDIF + + SWAP D1 + SMOVE D1,Upper_TDA(A2) ; set upper TDA + + ADD.L D0,MemStart(A6) ; update pointer + SUB.L D0,MemSize(A6) ; update size + MOVEQ #Max_Tx_Packets-2,D1 ; link together all free TDAs +@linkTDA + PEA TxTDAsize(A1) ; get link to next TDA + MOVE.L (SP),nextTD(A1) ; put in link field of TDA + MOVEA.L (SP)+,A1 ; point at next one + DBRA D1,@linkTDA ; do them all (last link = nil) + +; get memory for RRA + MOVEQ #RRArecSz+CAMDescSz,D0 ; mem for 1 RRA and 1 CAM descriptor + LEA RRAptr,A1 + MOVE.L MemStart(A6),(A1) ; save RRA ptr + + IF MMU THEN + BSR @SetAddresses ; set log/phys addresses + ENDIF + + MOVE.L MemStart(A6),D1 + + IF MMU THEN + SUB.L RRAptr+llg,D1 + ADD.L RRAptr+lph,D1 ; D1=physical address of RRA + ENDIF + + SWAP D1 + SMOVE D1,Upper_RRA(A2) ; set upper 16 bits of RRA addr + + ADD.L D0,MemStart(A6) ; update pointer + SUB.L D0,MemSize(A6) ; update size +; get memory for RBA + MOVE.L MemSize(A6),D0 + + DIVU #Max_Pkt_Size+RxRDAsize,D0 + EXT.L D0 + + CMP.L NumRxBuffs(A6),D0 ; more than requested? + BLS.S @usebuffs ; use number if less + + MOVE.L NumRxBuffs(A6),D0 +@usebuffs + LEA RxDescs,A1 + MOVE.L D0,(A1) ; save buffer/descriptor count +; get memory for RDA + LEA RDAptr,A1 + MOVE.L MemStart(A6),(A1) ; set RD list pointer + + IF MMU THEN + BSR @SetAddresses ; set log/phys addresses + ENDIF + + LEA NextRxDesc,A1 + MOVE.L MemStart(A6),(A1) ; set next poll address too + + MOVE.L RxDescs,D0 ; D0=# descriptors + MOVE.L D0,D1 + MULU #Rxpkt.RxRDAsize,D1 ; get actual allocated descriptor size + ADD.L D1,MemStart(A6) + SUB.L D1,MemSize(A6) + SUBQ.L #1,D0 ; convert desc count to base zero + MOVEA.L RDAptr,A0 ; A0->start of RDA +@setRD + TST.L D0 ; on last one? + BNE.S @notLast + + SUB.L D1,D1 ; nil pointer + BSET #EOL_Bit,D1 + BRA.S @setLink ; link last to first +@notLast + PEA RxRDAsize(A0) + MOVE.L (SP)+,D1 ; link to next + + IF MMU THEN + SUB.L RDAptr+llg,D1 + ADD.L RDAptr+lph,D1 ; D1=physical address + ENDIF +@setLink + SMOVE D1,RxPkt.link(A0) ; set link + MOVEQ #-1,D1 + SMOVE D1,RxPkt.in_use(A0) ; mark descriptor as in use by SONIC + LEA RxRDASize(A0),A0 + DBRA D0,@setRD + + PEA -RxRDASize(A0) + LEA LastDesc,A1 + MOVE.L (SP)+,(A1) ; save ptr to last one in list +; set pointer to buffer area + MOVE.L RxDescs,D0 + MULU #Max_Pkt_Size,D0 ; get actual memory used for buffers + + LEA RBAptr,A1 + MOVE.L MemStart(A6),(A1) ; save ptr to buffer area + + IF MMU THEN + BSR @SetAddresses ; set log/phys addresses + ENDIF + + ADD.L D0,MemStart(A6) ; update pointer + SUB.L D0,MemSize(A6) ; update size +; init RRA descriptors + MOVEA.L RRAPtr,A0 ; get pointer to RRA + LEA CAMDescSz(A0),A1 ; add in enough for CAM operations + + PEA (A1) ; save for later + MOVE.L A1,D0 + + IF MMU THEN + SUB.L RRAptr+llg,D0 + ADD.L RRAptr+lph,D0 ; A1=physical address + ENDIF + + SMOVE D0,RRA_Read(A2) ; set up RRP + SMOVE D0,RRA_Start(A2) ; save lower 16 bit of RRA addr + + ADDI.W #RRArecSz,D0 ; ONE descriptor + + SMOVE D0,RRA_End(A2) ; and set the end of RRA too + SUB.L D0,D0 ; clear 32 bits + SMOVE D0,RRA_Write(A2) ; force wrap-around RRA + + MOVE.L RBAptr,D0 + + IF MMU THEN + SUB.L RBAptr+llg,D0 + ADD.L RBAptr+lph,D0 ; D0=physical address + ENDIF + + MOVEA.L (SP)+,A1 ; get ptr to descriptor + + SMOVE D0,buff_ptr0(A1) ; setup resource descriptor + SWAP D0 + SMOVE D0,buff_ptr1(A1) + + MOVE.L RxDescs,D1 + MULU #Max_Pkt_Size/2,D1 ; D1=word count for buffer area + + SMOVE D1,buff_wc0(A1) ; setup buffer size + SWAP D1 + SMOVE D1,buff_wc1(A1) + + MOVEQ #-1,D0 ; reset all bits in ISR + SMOVE D0,Int_Status(A2) + BSR Set10Seconds ; init timer value + + SUB.L D0,D0 + SMOVE D0,Command(A2) ; start chip running +@wait + SMOVE Command(A2),D0 ; wait for SONIC to start up + BTST #SoftReset,D0 + BNE.S @wait + + MOVEQ #ReadRRA,D0 + BSR SONICSync ; read RRA descriptor +@loadRD + MOVE.L RDAptr,D0 + + IF MMU THEN + SUB.L RDAptr+llg,D0 + ADD.L RDAptr+lph,D0 ; D0= physical address + ENDIF + + SMOVE D0,Current_RDA(A2) ; setup RDA pointers + SWAP D0 + SMOVE D0,Upper_RDA(A2) + + BSR RestartSONIC ; enable reception and start timer + + MOVE.L #OurIntsMask,D0 ; setup for our interrupts + SMOVE D0,Int_Mask(A2) ; enable SONIC interrupts + MOVE.L MemSize(A6),D0 ; return # unused bytes in usage area +@IError + MOVEA.L (SP)+,A2 + UNLK A6 + RTS + + IF MMU THEN +@SetAddresses +; set lowest logical/physical addresses for pointer in A1 + MOVE.L D0,-(SP) ; save mem size, ptr + MOVE.L A1,-(SP) + MOVE.L D0,-(SP) ; pass logical size + MOVE.L MemStart(A6),-(SP) ; pass logical address + MOVEA.L TransAddr(A6),A0 + JSR (A0) ; D0=lowest physical addr + ADDQ.W #8,SP + MOVEA.L (SP)+,A1 + MOVE.L D0,lph(A1) ; set lowest physical address + MOVE.L MemStart(A6),llg(A1) ; set lowest logical address + MOVE.L (SP)+,D0 ; get back mem size + RTS + ENDIF + + ENDWITH + ENDPROC + +;•••••••••••••••• SONIC ShutDown +; void SONICHALT() + +SONICHALT PROC EXPORT +OurStack RECORD {A6Link} ; thru next +Sz EQU * +A6Link DS.L 2 +SONICPtr DS.L 1 + ENDR + + WITH SONICRegs + + LINK A6,#OurStack.Sz + MOVE.L A2,-(SP) + + MOVEA.L IntDRtn,A0 ; A0->proc to disable interrupts + JSR (A0) ; call it + MOVE.L D0,-(SP) ; save SR returned + + MOVEA.L OurStack.SONICptr(A6),A2 ; A2->sonic regs + BSR ResetSONIC ; disable packet reception + SUB.L D0,D0 + SMOVE D0,Int_Mask(A2) ; disable SONIC interrupts + SMOVE D0,CAM_Enable(A2) ; wipe out the CAM + + MOVEA.L IntERtn,A0 ; + JSR (A0) ; reenable interrupts + ADDQ.W #4,SP ; + + MOVEA.L (SP)+,A2 + UNLK A6 ; + RTS ; all done + ENDPROC + +;•••••••••••••••• SONIC Transmit +; void SONICXMIT(wdsPtr) + +parms RECORD {A6Link} +LocalSize EQU * +SaveA2 DS.L 1 +A6Link DS.L 2 +SONICPtr DS.L 1 ; +wdsPtr DS.L 1 ; write data structure pointer + ENDR + + PROC + EXPORT SONICXMIT + WITH SONICRegs,TxPkt,parms + +noTDA + MOVEA.L IntERtn,A0 + MOVE.L D0,-(SP) ; save SR returned by proc + JSR (A0) ; reenable interrupts + MOVEQ #-1,D0 + UNLK A6 + RTS +SONICXMIT + LINK A6,#LocalSize ; make some room + + MOVEA.L IntDRtn,A0 ; A0->proc to disable interrupts + JSR (A0) ; call it + + MOVE.L FreeTxTDA,D1 + BEQ.S noTDA ; If no TDA available +; it's always faster to not branch + MOVE.L A2,SaveA2(A6) ; save regs + MOVE.L D0,-(SP) ; save SR returned by IntDRtn proc + + LEA FreeTxTDA,A0 + MOVEA.L (A0),A1 ; A1->new TDA + MOVE.L nextTD(A1),(A0) ; unlink from free list + + EXG A1,A2 ; save TDA ptr + MOVEA.L IntERtn,A0 + JSR (A0) ; reenable interrupts maybe + EXG A1,A2 ; restore TDA ptr + + MOVEA.L wdsPtr(A6),A2 ; A2->wds, A1->this TDA + + SUB.L D0,D0 ; clear 32 bits + SMOVE D0,frag_count(A1) ; init Tx fields + SMOVE D0,pkt_size(A1) + SMOVE D0,status(A1) + SMOVE D0,config(A1) ; start timer after SFD, tx FCS, time + ; excessive deferrals + + LEA frag_start(A1),A0 ; A0->fragment fields +@fragloop + SUB.L D0,D0 ; clear 32 bits + MOVE.W (A2)+,D0 ; check wds segment len + BEQ.S @chkpkt ; see if everything is ok + + IF SONIC32 THEN + ADDQ.L #1,frag_count(A1) + ADD.L D0,pkt_size(A1) ; and total packet size + ELSE + ADDQ.W #1,frag_count(A1) ; bump count + ADD.W D0,pkt_size(A1) ; and total packet size + ENDIF + + MOVE.L D0,-(SP) ; save frag size from wds + MOVE.L (A2)+,D0 ; get wds ptr + SMOVE D0,(A0)+ ; set lower 16 of frag_ptr + SWAP D0 + SMOVE D0,(A0)+ ; set upper 16 + MOVE.L (SP)+,D0 + SMOVE D0,(A0)+ ; set frag size in TDA + BRA.S @fragloop ; keep going +@chkpkt + SMOVE pkt_size(A1),D0 + EXT.L D0 ; make a 32 bit quantity + + SUBI.L #Min_Pkt_Size,D0 ; calc pad size + BHS.S @sendit ; go do it if long enough + + NEG.L D0 ; convert to positive number + + IF SONIC32 THEN + + ADDQ.L #1,frag_count(A1) ; add another fragment for padding + ADD.L D0,pkt_size(A1) ; bump total too + + ELSE + + ADDQ.W #1,frag_count(A1) ; add another fragment for padding + ADD.W D0,pkt_size(A1) ; bump total too + + ENDIF + + MOVE.L RBAptr,D1 ; start of buffers + + IF MMU THEN + SUB.L RBAptr+llg,D1 + ADD.L RBAptr+lph,D1 ; convert to physical address + ENDIF + + SMOVE D1,(A0)+ ; set lower 16 of frag_ptr + SWAP D1 + SMOVE D1,(A0)+ ; set upper 16 + + SMOVE D0,(A0)+ ; set frag size in TDA +@sendit + MOVEQ #(1<proc to disable interrupts + JSR (A0) ; call it (SR already on stack from above) + + EXG A1,A2 ; restore curr frag ptr in A1 + MOVEA.L SONICptr(A6),A2 ; A2->sonic regs + + MOVE.L NextTxTDA,D0 ; check if we already have a chain + BNE.S @haveChain + + LEA NextTxTDA,A0 ; start a new chain + MOVE.L A1,(A0) + BRA.S @doxmit ; transmit new chain maybe +@haveChain + MOVEA.L D0,A0 ; A0->start of existing chain + SMOVE Upper_TDA(A2),D1 + SWAP D1 ; get upper TDA address +@chkTDA + SMOVE frag_count(A0),D0 ; D0=fragment count for this packet + FragMul D0 ; calc an offset to the link field + LEA frag_start(A0),A0 ; A0->start of fragments for this pkt + LEA (A0,D0.W),A0 ; A0->link field for this pkt + SMOVE (A0),D0 + BTST #EOL_Bit,D0 ; at the last pkt in chain? + BNE.S @setlink ; append to end if so + + MOVE.W D0,D1 ; D1=physical address of next TDA + + IF MMU THEN + SUB.L TxTDAPtr+lph,D1 + ADD.L TxTDAPtr+llg,D1 ; D1=logical addr (upper half) + ENDIF + + MOVEA.L D1,A0 ; A0->next TDA + BRA.S @chkTDA ; keep searching for last TDA +@setlink + MOVE.L A1,D0 ; D0=ptr to new TDA + + IF MMU THEN + SUB.L TxTDAPtr+llg,D0 + ADD.L TxTDAPtr+lph,D0 ; D0=physical address + ENDIF + + SMOVE D0,(A0) ; update link of last TDA +@doxmit + LEA TxTDAptr,A0 + TST.L (A0) + BNE.S @done ; transmit already in progress + + LEA NextTxTDA,A1 + MOVE.L (A1),(A0) ; start transmitting current chain + MOVEQ #0, D0 + MOVE.L D0, (A1) ; empty chain + + MOVE.L (A0),D0 + + IF MMU THEN + SUB.L TxTDAPtr+llg,D0 + ADD.L TxTDAPtr+lph,D0 ; D0=physical address of curr TDA + ENDIF + + SMOVE D0,Current_TDA(A2) ; set current SONIC TDA ptr + + MOVEQ #(1< +CAMentry DS.W 3 ; 48 bit address to set in CAM +Loadit DS.L 1 ; true if adding CAM entry + ENDR + + WITH parms,SONICRegs,CAMDesc + + LINK A6,#LocalSize ; save A6 + MOVEM.L A2/D3/D4,-(SP) ; save reg + + MOVEA.L IntDRtn,A0 ; A0->proc to disable interrupts + JSR (A0) ; call it + MOVE.L D0,-(SP) ; save SR returned + + MOVEA.L SONICptr(A6),A2 ; A2->SONIC + + MOVE.L CAMentry(A6),D1 ; D1=upper/middle of 48 bit addr + MOVE.W CAMentry+4(A6),D2 ; D2.W=lower " + + TST.L Loadit(A6) ; doing a load CAM? + BEQ.S @doClear ; no +; search for an empty CAM entry +@wait1 + SMOVE Command(A2),D0 + EORI.W #(1<RRA, D3=index to CAM cell + + ROR.W #8,D2 ; swap bytes in word + SMOVE D2,Port0(A0) ; set lower 16 bits + + ROR.W #8,D1 ; swap bytes in word + SMOVE D1,Port1(A0) ; set middle " + + SWAP D1 + ROR.W #8,D1 ; swap bytes in word + SMOVE D1,Port2(A0) ; set upper " + + SMOVE CAM_Enable(A2),D0 ; get current CAM map + BSET D3,D0 ; set the new one + SMOVE D0,enable(A0) ; set bit map for CAM + + BSR.S LoadCAMcells ; load descriptor and CAM enable reg + + MOVE.L D3,D0 ; set function result + BRA.S @Xit +@doClear + BSR ResetSONIC ; let transmits/receives complete + + MOVEQ #15,D3 + SMOVE CAM_Enable(A2),D0 ; get current CAM map +@compCAM + ASL.W #1,D0 ; check cell + DBCS D3,@compCAM ; until we have an active one + BCS.S @compareit +@notfound + BSR RestartSONIC ; get SONIC going again + MOVE.W D3,D0 + EXT.L D0 ; D0.L=-1 + BRA.S @Xit ; return error (did'nt find entry) +@more + SUBQ #1,D3 ; keep index straight + BMI.S @notfound + BRA.S @compCAM +@compareit ; compare CAM to addr in D1/D2 + SMOVE D3,CAM_EntryPtr(A2) ; select CAM cell to read + SMOVE CAM_Port1(A2),D4 ; get middle 16 bits + ROR.W #8,D4 ; normalize it + MOVE.W D4,-(SP) ; save it + SMOVE CAM_Port0(A2),D4 ; get upper 16 bits + ROR.W #8,D4 ; normalize it + MOVE.W D4,-(SP) ; save it + CMP.L (SP)+,D1 ; same as the one we want? + BNE.S @more ; no, keep checking + + SMOVE CAM_Port2(A2),D4 ; get lower 16 + ROR.W #8,D4 ; normalize it + CMP.W D4,D2 ; same? + BNE.S @more ; look again if not + + MOVEA.L RRAptr,A0 ; A0->CAM descriptor + + SUB.L D2,D2 + SMOVE D2,Port0(A0) ; put zero entry in cell + SMOVE D2,Port1(A0) + SMOVE D2,Port2(A0) + SMOVE CAM_Enable(A2),D0 ; get current CAM map + BCLR D3,D0 ; clear the one to delete + SMOVE D0,enable(A0) ; and do it + + BSR RestartSONIC ; get SONIC going again + BSR.S LoadCAMcells ; clear the entry now + SUB.L D0,D0 ; clear 32 bits +@Xit + MOVEA.L IntERtn,A0 ; + JSR (A0) ; reenable interrupts + ADDQ.W #4,SP ; + + MOVEM.L (SP)+,A2/D3/D4 + UNLK A6 + RTS + + +LoadCAMcells ; setup CAM cells and enable register +; D3=base zero index of CAM cell, A0->CAM load descriptor + SMOVE D3,Entry_ptr(A0) ; set base zero index to CAM cell + MOVE.L A0,D0 + + IF MMU THEN + SUB.L RRAptr+llg,D0 + ADD.L RRAptr+lph,D0 ; D0=physical address + ENDIF + + SMOVE D0,CAM_DescPtr(A2) ; set current descriptor ptr + MOVEQ #1, D0 + SMOVE D0,CAM_Count(A2) ; set one cell only + + MOVEQ #LoadCAM,D0 + BRA SONICSync ; do it now & return + ENDWITH + ENDPROC + + END + \ No newline at end of file diff --git a/DeclData/DeclNet/Sonic/Sonic.a.idump b/DeclData/DeclNet/Sonic/Sonic.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Sonic/Sonic.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Sonic/Sonic.a.rdump b/DeclData/DeclNet/Sonic/Sonic.a.rdump new file mode 100644 index 0000000..713ae70 --- /dev/null +++ b/DeclData/DeclNet/Sonic/Sonic.a.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 000C 0186 000D 0118" /* ..Monaco........ */ + $"000E 0168 000F 0000 001E 000F 0000 496E" /* ...h..........In */ + $"7661 0006 0004 003C 0024 02E8 02BD 003C" /* va.....<.$.....< */ + $"0024 02E8 02BD A678 8BDC 0000 0000 0000" /* .$.....x........ */ + $"0000 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"003C 0024 02E8 02BD 003C 0024 02E8 02BD" /* .<.$.....<.$.... */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"33F7 B43E 3FE5 3230 0004 0000 0000 0000" /* 3..>?.20........ */ + $"0000 A933 73AB A933 73AB A6F7 B0F2 0078" /* ...3s..3s......x */ + $"C6B2 0000 0001 0001 2653 7570 6572 4D61" /* ........&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA53 6F6E 6963 BA00" /* .DeclNet.Sonic.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0131 0007 536F 6E69 632E 6100 0000 001F" /* .1..Sonic.a..... */ + $"4E65 7720 6C6F 6361 7469 6F6E 2066 6F72" /* New location for */ + $"2052 4F4D 4C69 6E6B 2074 6F6F 6C2E 0D00" /* ROMLink tool... */ +}; + diff --git a/DeclData/DeclNet/Sonic/Sonic.make b/DeclData/DeclNet/Sonic/Sonic.make new file mode 100644 index 0000000..9f99ae8 --- /dev/null +++ b/DeclData/DeclNet/Sonic/Sonic.make @@ -0,0 +1,39 @@ +# +# File: Sonic.make +# +# Contains: Makefile for Sonic. +# +# Written by: Kurt Clark, Chas Spillar, and Tim Nichols +# +# Copyright: © 1992 by Apple Computer, Inc., all rights reserved. +# +# Change History (most recent first): +# + +"{RsrcDir}DeclDataSonic.rsrc" ƒ "{ObjDir}SonicEnet.a.o" ∂ + "{ObjDir}Sonic.a.o" ∂ + "{ObjDir}Loopback.c.o" ∂ + "{IfObjDir}interface.o" + Link {StdLOpts} {StdAlign} -rt decl=1 -o "{Targ}" "{ObjDir}SonicEnet.a.o" ∂ + "{ObjDir}Sonic.a.o" ∂ + "{ObjDir}Loopback.c.o" ∂ + "{IfObjDir}interface.o" + + +"{ObjDir}SonicEnet.a.o" ƒ "{SonicDir}SonicEnet.a" ∂ + "{SonicDir}SonicEqu.a" ∂ + "{SonicDir}VersionEclipse.a" ∂ + "{EthernetDir}AtalkMacros.a" ∂ + "{EthernetDir}ENETEqu.a" ∂ + "{AIncludes}GestaltEqu.a" ∂ + "{AIncludes}Slots.a" ∂ + "{AIncludes}SysEqu.a" ∂ + "{AIncludes}SysErr.a" ∂ + "{AIncludes}ToolUtils.a" ∂ + "{AIncludes}Traps.a" + Asm {StdAOpts} -d ForEclipseROM=0,sonic32=1,ctlpad=0,mmu=1 -i "{SonicDir}" -i "{EthernetDir}" -o "{Targ}" "{SonicDir}SonicEnet.a" + + +"{ObjDir}Sonic.a.o" ƒ "{SonicDir}Sonic.a" ∂ + "{SonicDir}SonicEqu.a" + Asm {StdAOpts} -d sonic32=1,mmu=1 -i "{SonicDir}" -i "{EthernetDir}" -o "{Targ}" "{SonicDir}Sonic.a" diff --git a/DeclData/DeclNet/Sonic/Sonic.make.idump b/DeclData/DeclNet/Sonic/Sonic.make.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Sonic/Sonic.make.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Sonic/Sonic.make.rdump b/DeclData/DeclNet/Sonic/Sonic.make.rdump new file mode 100644 index 0000000..332cf38 --- /dev/null +++ b/DeclData/DeclNet/Sonic/Sonic.make.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0047 656F 7267 6520" /* ..Monaco.George */ + $"442E 2057 696C 736F 6E20 4A72 2E0D 230D" /* D. Wilson Jr..#. */ + $"2309 0006 0004 0029 0007 035A 0238 0029" /* #......)...Z.8.) */ + $"0007 035A 0238 A71A 6851 0000 00E0 0000" /* ...Z.8..hQ...... */ + $"00E0 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"0029 0007 035A 0238 0029 0007 035A 0238" /* .)...Z.8.)...Z.8 */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"2B26 BAE5 3FE5 3230 0004 0000 0000 0000" /* +&..?.20........ */ + $"0000 A933 73AB A933 73AB A6F7 B0F2 0078" /* ...3s..3s......x */ + $"C6B2 0000 0006 0001 2653 7570 6572 4D61" /* ........&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA53 6F6E 6963 BA00" /* .DeclNet.Sonic.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0131 000A 536F 6E69 632E 6D61 6B65 0000" /* .1..Sonic.make.. */ + $"0000 144D 6F76 6564 2066 726F 6D20 6D61" /* ...Moved from ma */ + $"6B65 6669 6C65 2E00" /* kefile.. */ +}; + diff --git a/DeclData/DeclNet/Sonic/SonicEnet.a b/DeclData/DeclNet/Sonic/SonicEnet.a new file mode 100644 index 0000000..c478e81 --- /dev/null +++ b/DeclData/DeclNet/Sonic/SonicEnet.a @@ -0,0 +1,1825 @@ +; +; File: EtherNet.a -> SonicEnet.a +; +; Contains: Shell for Ethernet driver +; +; Written by: Sean Findley +; +; Copyright: © 1990-91 by Apple Computer, Inc., all rights reserved. +; +; +; Change History (most recent first): +; +; 1/29/93 RB Do not move #$2600 to the status register, always do an ORI.W +; with it so that NuKernel works and the stack is not changed. +; 10/28/92 SWC Changed the INCLUDEs to a LOAD of StandardEqu.d. +; 10/26/92 mal Updated controltable COMMENTS with correct snmp enet control +; codes, 238-242; note, these snmp enet control codes are still +; unimplemented and return controlerr. +; <1> 10/6/92 GDW New location for ROMLink tool. +; 6/22/92 mal Changed Open so ptr and size to data passed to LOOPBACKTEST; +; added SNMP control calls to control table but don't support yet. +; <1> 6/12/92 RLM first checked in +; 5/13/92 KW (JC,H5) Change driver to support configuration information +; obtained from ecfg resource rather than from using boxflag +; driven tables. +; (JC,H4) Add support for new machines to boxflag driven tables. +; 02/07/92 jmp (jmp,H3/BG/SJF,Z12) Added fixes for the possible loss of +; transmit buffers. Also turn off interrupts around processing +; the CAM. +; <1> 2/4/92 mal first checked in +; ——————————————————————————————————————————————————————————————————————————————————————— +; Pre-Pandora ROM comments begin here. +; ——————————————————————————————————————————————————————————————————————————————————————— +; <11> 10/22/91 SAM Added Sean Findley's changes to correct an interaction problem +; with VM/Ethernet. From Zydeco-Terror ROM. +; ——————————————————————————————————————————————————————————————————————————————————————— +; Pre-Zydeco ROM comments begin here. +; ——————————————————————————————————————————————————————————————————————————————————————— +; <10> 5/22/91 BG Removed a _DetachResource in the driver that Sean says shouldn't +; be there. Also changed a BEQ to a BEQ.S to LoopError in Open. +; <9> 4/21/91 CCH Rolled in Sean Findley's changes. +; <8> 4/2/91 CCH Added a cache flush after the blockmove to the write buffer. +; <7> 3/19/91 BG Enabled the _MemoryDispatch call for logical-to-physical +; translation in TranslateAddress. Previously, it was returning +; the logical address since it knew that logical=physical in the +; Eclipse/Spike cases. +; <6> 3/14/91 BG (for SJF) A number of changes: +; - Driver variables now allocated via _NewPtr to save +; space on disk. +; - When installing/removing a SlotMgr interrupt routine +; the slot number is not hard-coded to 9. +; - Removed all calls to _SwapMMUMode since the Sonic +; base address is accessible in both 24- and 32-bit modes. +; - Implement VM support +; - Activate the "extended Motorola mode" for the AVF +; SONIC parts. +; <5> 2/26/91 JK Added extended Motorola mode code, and GetPhysical call. +; <4> 2/1/91 JK Rolled in Ethernet code review changes. +; <3> 1/31/91 JK Hacked in call to LockMemoryContiguous. +; <2> 1/9/91 JK Fixed to use Ethernet address PROM on Eclipse motherboard. +; <1> 12/14/90 JK Added to build +; + + TITLE 'Ethernet Driver' +;___________________________________________________________________________ +; +; Ethernet Data Link Level Driver +; +; Sean Findley +; January 1990 + + PRINT OFF + LOAD 'StandardEqu.d' + INCLUDE 'Slots.a' ; Slot interrupt equates + INCLUDE 'GestaltEqu.a' + + INCLUDE 'ATalkMacros.a' ; Nifty Macros + + PRINT NOGEN,NOMDIR,ON + INCLUDE 'ENETEqu.a' ; Driver definitions + INCLUDE 'SonicEqu.a' ; SONIC chip definitions + EJECT + +RxParms RECORD {A6Link} ; stack frame for received packets thru next +Size EQU * +InUse EQU * ; in use flag (long) +A6Link DS.L 1 +Return DS.L 1 +Status DS.L 1 ; status of recv +Length DS.L 1 ; length of packet +Data DS.L 1 ; data pointer +DCE DS.L 1 ; DCE pointer +RxDesc DS.L 1 ; buffer descriptor pointer +ParmsSz EQU * - Status ; positive size of frame + ENDR + +NumBuffers EQU 8 ; "optimal" number of buffers + +; Sonic Configuration Record
+SCFG RECORD 0 ; Config values from config rsrc +SONICBase24 DS.L 1 ; Base address of SONIC in 24 bit mode +SONICBase32 DS.L 1 ; Base address of SONIC in 32 bit mode +EnetPROM DS.L 1 ; base address of Address Prom in 32 bit mode +DataCfgLpBk DS.L 1 ; DataConfig reg values during loopback tests +DataCfgRun DS.L 1 ; DataConfig reg values during normal operation +DataCfg2 DS.L 1 ; DataConfig 2 reg +SONICSlot DS.B 1 ; Logical slot of SONIC for the slot manager +SmartMMU DS.B 1 ; Non-zero if system has smart MMU code + ; The following are optional values; ignored if zero +EnetAddr DS.B 6 ; Alternate Ethernet Address, overrides Address PROM +NumRxBuffs DS.W 1 ; Alternate number of receive buffers +NumTxBuffs DS.W 1 ; Alternate number of transmit buffers +CfgSize EQU * + ENDR ;
+ +OurV RECORD 0 ; our variables +OurDCE DS.L 1 ; Offset to our DCE pointer in variables +InfoStart EQU * ; Start of returned info +OurAddr DS.B EAddrSz ; Our Ethernet address +OverWrtCnt DS.L 1 ; Count of number of overwrites (long) +TimeoutCnt DS.L 1 ; Count of timeouts on writes (long) +BadDestCnt DS.L 1 ; Count of packets received not to us (long) +InfoEnd EQU * ; End of returned info +MaxData DS.W 1 ; Max data size for write +RHA DS.B EHdrSize ; Read Header Area +;___________________________________________________________________________ +; +; The LAP protocol handler table starts here. Format: +; .BYTE InUseFlag1,..., InUseFlagN ; Entry in use flag +; .WORD ProtCode1, ..., ProtCodeN ; Protocol type codes +; .LONG PHAddr1, ..., PHAddrN ; Protocol handler addresses +; .LONG RdQueueHd1, ..., RdQueueHdN ; Read queue heads +;___________________________________________________________________________ +LAPTblSz EQU 16 ; Size of LAP protocol handler table (even) +InUseFlag DS.B LAPTblSz ; Entry in use flag +Protocols DS.W LAPTblSz ; List of active protocols +Handlers DS.L LAPTblSz ; List of handler addresses +RdQueueHd DS.L LAPTblSz ; Read queue heads +LAPTblEnd EQU * ; End of LAP table + +;___________________________________________________________________________ +; +; Multicast address table. Entry format: +; Ethernet address (6 bytes) +; Use count (1 byte). Zero means entry free. +; Unused (1 byte) +;___________________________________________________________________________ + +MTblSz EQU 8 ; Size (in entries) of multicast address table (???) +MEntrySz EQU 8 ; Size of an entry (power of 2) +MUseCount EQU EAddrSz ; Offset to use count in entry + +MultiCTbl DS.B MTblSz*MEntrySz ; A list of valid addresses +EtherStats DS NetStats ; SONIC network statistics +SONICmem DS.L 1 ; header to xmit buffer list +deferCtl DS.W 1 ; flag=true if deferring ctl call +VBLQEL DS.B 14 ; VBL for ctl call deferrals +AddrMask DS.L 1 ; 32 bit mask for addresses +BlockMove DS.L 1 ; trap address of block move +LastRxDesc DS.L 1 ; current rx descriptor address +WrBuffHdr DS.L 1 ; header to free xmit buffers +XmitWait DS.W 1 ; flag to indicate write waiting for buffers +XmitBuffs DS.L 1 ; # of xmit buffers +PLTable DS.L 1 ; ptr to address translation table +MachID DS.W 1 ; id of CPU (from Gestalt) +DataCache DS.L 1 ; stored value of data cache reg on LC 030 +CacheCount DS.L 1 ; use count for cache +SONICCfg DS SCFG ; SONIC config data from config rsrc
+; •••••••• WARNING ••••••••• +; The following array MUST be the LAST item in the vars list. It is used only if VM is +; running. If not, it is trimmed off the required memory for the driver. +RxDefBuffs DS.B RxParms.ParmsSz * NumBuffers ; if VM running, only Numbuffers max. allowed + +DataSize EQU * ; End of variables + ENDR + +;_______________________________________ +; +; Other definitions +;_______________________________________ + +OneWdsSz EQU 8 ; single fragment wds size + +PtoL RECORD 0 +Physical DS.L 1 ; physical address of xmit buffer +Logical DS.L 1 ; associated logical addr +Size EQU * + ENDR + +XmitRec RECORD 0 ; + DS.B Max_Pkt_Size+OneWdsSz+PtoL.Size ; memory for each xmit buffer + ALIGN 4 ; make sure MOD 4 size +Size EQU * ; + ENDR ; + +AMaxDataSz EQU 768-EHdrSize ; Maximum data size for AppleTalk mode + +IntLockOut EQU $400 ; SR value to lock interrupts rb + +BlockMoveTrap EQU $A02E ; trap value for _BlockMove + + +Configrsrc EQU 'ecfg' ; rsrc type for sonic config data rsrc
+ + +NeedDefer EQU 5 ; bit indicates VM is running
+ EJECT + +ENETDriver MAIN EXPORT + + STRING PASCAL + MACHINE MC68020 + + IMPORT SONICINIT,SONICXMIT,SONICCAMLOAD,SONICFREEBUFF,SONICHALT + IMPORT ResetSONIC,RestartSONIC + IMPORT LOOPBACKTEST + + WITH SONICRegs,OurV + +; ***************************************** +; * * +; * Start of ENET driver * +; * * +; ***************************************** +ENET +; +; Driver header +; + DC.W $4400 ; Control, Locked, no Goodbye + DC.W 0,0 ; No time, no events + DC.W 0 ; No menu + +; +; Entry points offset table +; + DC.W Open-ENET + DC.W AnRTS-ENET + DC.W Control-ENET + DC.W AnRTS-ENET + DC.W Close-ENET + + DC.W '.ENET' ; Driver name + ALIGN 2 + + INCLUDE 'VersionEclipse.a' + +;________________________________________________________________________ +; +; Open - initialize the ENET driver +; +; Called: +; D0 = 0 +; A0 -> queue element +; A1 -> DCE +;________________________________________________________________________ + + + +Open + LINK A6,#0 ; mark the stack for easy exit + + MOVE.L A1,-(SP) ; save DCE pointer + + MOVE.L #gestaltVMAttr,D0 ; see if VM is running + _Gestalt ; + BNE.S @noVM ; it isn't if call failed + MOVE.L A0,D0 ; + BEQ.S @noVM ; zero result means no VM running + + BSET #NeedDefer,dCtlStorage(A1) ; indicate VM is running + BSET #VMImmuneBit,dCtlFlags+1(A1) ; tell VM to leave our calls alone +@noVM ; + + LEA OurVarPtr,A3 ; A3 -> variable pointer +; +; Allocate our variables +; + MOVE.L #DataSize,D0 ; variables size + BTST #NeedDefer,dCtlStorage(A1) ; is VM running? + BNE.S @10 ; yes, get full memory + SUBI.L #RxParms.ParmsSz * NumBuffers,D0 + ; adjust memory requirement +@10 + _NewPtr ,SYS,CLEAR ; get memory + BNE OpenError + + MOVE.L A0,(A3) ; save variable pointer + MOVEA.L A0,A2 ; A2 -> variable space + + MOVE.B SonicEnet,DCtlQueue+1(A1) ; Version number goes here + + MOVE.L A1,D0 + _StripAddress + MOVE.L D0,OurDCE(A2) ; Save our DCE address
+ + MOVE.W #BlockMoveTrap,D0 + _GetTrapAddress + MOVE.L A0,BlockMove(A2) ; save trap address in our vars + + MOVE #EMaxDataSz,MaxData(A2) ; Set AppleTalk mode max data size +; +; Look for a SONIC configuration resource for this CPU
+; + MOVE.L #gestaltMachineType,D0 + _Gestalt ; get our machine type + MOVE.L A0,D0 + MOVE D0,MachID(A2) ; save our machine ID + + SUBQ #4,SP ; Make room for handle + MOVE.L #Configrsrc,-(SP) ; Push resource type + MOVE D0,-(SP) ; Set machine ID as resource ID + _GetResource ; Get it from system file + MOVE.L (SP)+,D0 ; D0 = handle to config resource + BNE.S @21 ; Bra if we found it + + SUBQ #4,SP ; Make room for handle + MOVE.L #Configrsrc,-(SP) ; Push resource type + MOVE MachID(A2),-(SP) ; Set machine ID as resource ID + MOVE #MapTrue,ROMMapInsert ; Look for resource in sys ROM + _GetResource ; Get it from ROM + MOVE.L (SP)+,D0 ; D0 = handle to config resource + BNE.S @21 + MOVEQ #-1,D0 ; return with generic error (D0=-1) + BRA OpenError ; return, config rsrc not found + +@21 MOVEA.L D0, A3 ; Save handle to resource + + MOVEA.L (A3), A0 ; A0-> config resource + LEA SONICCfg(A2), A1 ; A1-> space in our vars + MOVE.L #SCFG.CfgSize, D0 + _BlockMove ; Copy data from rsrc to our vars + + MOVE.L A3, -(SP) ; push handle + _ReleaseResource ; We're thru with config resource + + LEA SONICCfg.EnetAddr(A2), A0 ; A0-> alternate ethernet address + TST.L (A0) ; Check address + BNE.S @22 + TST 4(A0) + BEQ.S @23 ; Ignore if all zeros +@22 + BTST #0,(A0) ; Make sure it's not a multicast addr + BNE.S @23 ; Ignore it if it is + MOVE.L (A0)+,OurAddr(A2) ; Move four bytes to our address + MOVE (A0)+,OurAddr+4(A2) ; Move the last two bytes +@23 + MOVEQ #NumBuffers,D2 ; set desired # of buffers + MOVE.L D2,D3 ; D2=xmit,D3=recv + + MOVE SONICCfg.NumTxBuffs(A2),D0 ; get alternate # xmit buffers + BEQ.S @24 ; don't override if zero + MOVE D0, D2 ; override default # xmit buffers +@24 + BTST #NeedDefer,([OurDCE,A2],dCtlStorage) ; is VM running? + BNE.S @25 ; Yes, don't override # recv buffers + + MOVE SONICCfg.NumRxBuffs(A2),D0 ; get alternate # recv buffers + BEQ.S @25 ; don't override if zero + MOVE D0, D3 ; override default # recv buffers
+@25 + +; D2=# xmit buffers to allocate, D3=# recv buffers to allocate + +@GetMemory + CMPI.W #Min_Rx_Buffs,D3 ; have mininum number of buffers? + BLO.S @nomem ; no, get out + + MOVE.L #Ctl_Mem_Size,D0 ; add up memory needed + + MOVE.L #Rxpkt.RxRDAsize,D1 + MULU D3,D1 + ADD.L D1,D0 ; D0=memory for all descriptors + LSL.L #1,D0 ; times 2 + + MOVE.L #Max_Pkt_Size,D1 + MULU D3,D1 + ADD.L D1,D0 ; D0=memory for receive buffers + + MOVE.L D0,D4 ; save SONIC memory size for later + + MOVE.L D2,D1 ; D1=# xmit buffs + + MULU #XmitRec.Size,D1 ; D1=memory needed for xmit buffs + + ADD.L D1,D0 ; D0=memory for recv and xmit buffs + + MOVE.L D0,D5 ; remember size of Sonic memory + + _NewPtr ,SYS,CLEAR ; get the memory + BEQ.S @haveMem ; use it + + SUBQ.L #1,D2 ; adjust # xmit buffers first + BHI.S @GetMemory + MOVEQ #1,D2 ; set back to mininum of one + SUBQ.L #1,D3 ; adjust # recv buffers last + BHI.S @GetMemory +@nomem + MOVE.W #mFulErr,D0 + BRA OpenError ; get out with error +@haveMem + BTST #NeedDefer,([OurDCE,A2],dCtlStorage) + BNE.S @haveMemDispatch ; VM is running, ok to call _VM + + TST.B SONICCfg.SmartMMU(A2) ; no VM, do we have smart MMU code?
+ BEQ.S @nolock ; no, don't lock memory
+ +@haveMemDispatch + MOVE.L A1,-(SP) ; save a1 + MOVEA.L D5,A1 ; length of buffer + MOVEQ #4,D0 ; LockMemoryContiguous + _MemoryDispatch ; MemoryDispatch + MOVEA.L (SP)+,A1 ; restore a1 + BNE OpenError ; failed, so bail + +@nolock ;
+ MOVE.L D2,XmitBuffs(A2) ; save # of xmit buffers + + MOVE.L D1,D5 ; save xmit buffers size for later + + MOVE.L A0,D0 + _StripAddress + MOVEA.L D0,A0 + MOVE.L D0,SONICmem(A2) ; save ptr in our vars + MOVE.L A0,WrBuffHdr(A2) ; set header pointer + + MOVE.L D2,D0 + SUBQ.W #1,D0 ; adjust loop count + BRA.S @db1 +@setBufLink ; link together xmit buffers + PEA Max_Pkt_Size+OneWdsSz(A0) + MOVE.L (SP),(A0) ; set link to next buffer + MOVEA.L (SP)+,A0 ; point to next buffer +@db1 + DBRA D0,@setBufLink ; do them all + CLR.L (A0) ; clear the last one + + LEA Max_Pkt_Size+OneWdsSz(A0),A0 ; A0->Physical to Logical Table + + MOVE.L A0,PLTable(A2) ; save address of translation table + MOVEA.L WrBuffHdr(A2),A1 ; A1->1st buffer + + MOVE.L D2,D1 ; D1=# xmit buffs + BRA.S @db2 +@setupWDS + MOVEM.L A0/D1,-(SP) + MOVE.L #Max_Pkt_Size+OneWdsSz,-(SP) ; logical size + MOVE.L A1,-(SP) ; logical address + BSR TranslateAddress ; get physical address in D0 + MOVEA.L (SP)+,A1 ; get back buffer addr + ADDQ.W #4,SP ; trash length + MOVEM.L (SP)+,A0/D1 + MOVE.L A1,PtoL.Logical(A0) ; save logical address + MOVE.L D0,PtoL.Physical(A0) ; save physical address + MOVE.L D0,Max_Pkt_Size+2(A1) ; in WDS too + LEA PtoL.Size(A0),A0 ; next table entry + LEA Max_Pkt_Size+OneWdsSz(A1),A1 ; next buffer +@db2 + DBRA D1,@setupWDS ; translate all xmit buff addresses + + LEA OurAddr(A2),A1 + TST.L (A1) + BNE.S @45 ; already have an address + TST.W 4(A1) + BNE.S @45 ; already have an address +; Must be in 32 bit mode to examine Ethernet address PROM on an LC, doesn't matter for others + MOVEQ #true32b,D0 ; + _SwapMMUMode ; put us in 32-bit mode + MOVE.B D0,-(SP) ; save prior MMU status + + BSR AddrPromAddr ; A0->address prom + MOVEQ #0,D1 ; setup to checksum the PROM address + MOVEQ #7,D0 ; do 8 bytes +@Xor + MOVE.B (A0)+,D2 ; get byte to XOR + EOR.B D2,D1 + DBRA D0,@Xor ; do them all + SUBI.B #$FF,D1 ; end result should be $FF + BEQ.S @GetAddr ; keep going if it is + + MOVE.B (SP)+,D0 ; + _SwapMMUMode ; put back mmu + MOVEQ #-1,D0 ; + BRA OpenError ; return with generic error (D0=-1) +@GetAddr ; + ADDQ.W #EAddrSz,A1 ; go from last to first + + BSR AddrPromAddr ; A0->address prom + MOVEQ #EAddrSz-1,D2 ; get 6 addr bytes +@35 + MOVE.B (A0,D2.W),D0 ; D0=inverted address + BSR NormAddr ; normalize it + MOVE.B D0,-(A1) ; store in our vars + DBRA D2,@35 + + MOVE.B (SP)+,D0 ; + _SwapMMUMode ; put back mmu +@45 + + MOVEQ #-1,D0 + _StripAddress + MOVE.L D0,AddrMask(A2) ; save cached 32 bit address mask + + SUBA.W #SONICinitParms.ParmSize,SP ; make room for parms + PEA TranslateAddress ; addr of our log->phys addr translation + MOVE.L (SP)+,SONICinitParms.TransAddr(SP) + ; translation table proc address + BSR SONICAddr ; A0->SONIC + +; So far, only the Quadra's need this register set... + MOVE.L SONICCfg.DataCfg2(A2), D0 ; setup SONIC extended data config
+ SMOVE D0,Data_Config2(A0) ; set extended data config
+ + MOVE.L SONICCfg.DataCfgLpBk(A2), D0 ; setup SONIC data config for loopback tests
+ + MOVE.L D0,SONICinitParms.DataConfig(SP) + + PEA EtherStats(A2) ; ptr to stats array + MOVE.L (SP)+,SONICinitParms.NetStatArray(SP) + + PEA IntEnable ; interrupt enable routine + MOVE.L (SP)+,SONICinitParms.IntEnable(SP) + + PEA IntDisable + MOVE.L (SP)+,SONICinitParms.IntDisable(SP) + ; disable interrupts routine + + MOVE.L D3,SONICinitParms.NumRxBuffs(SP) + ; # of receive buffers + + MOVE.L D4,SONICinitParms.MemSize(SP) ; size of sonic mem + + MOVE.L SONICmem(A2),SONICinitParms.MemStart(SP) + ADD.L D5,SONICinitParms.MemStart(SP) ; ptr to sonic mem + + MOVE.L A2,SONICinitParms.TRANPrms(SP) ; trans complete parms + + PEA XmitDone + MOVE.L (SP)+,SONICinitParms.TRANRtn(SP) + ; proc to call for xmit complete + + MOVE.L OurDCE(A2),SONICinitParms.RECVPrms(SP) + ; recv complete parms + PEA EtherRecv + MOVE.L (SP)+,SONICinitParms.RECVRtn(SP) + ; proc to call for recvd packets + + PEA IntInstallation + MOVE.L (SP)+,SONICinitParms.IntInstall(SP) + ; interrupt proc installation routine + + BSR SONICAddr ; + MOVE.L A0,SONICinitParms.SONICbase(SP) ; + + BSR DataCacheOff ; turn off data cache on LC 030 + + BSR SONICINIT ; initialize sonic chip + ADDA.W #SONICinitParms.ParmSize,SP ; strip parms + + BSR DataCacheOn ; turn data cache back on + + BLT OpenError ; init failed + BEQ.S @loadCAM + + NEG.L D0 + MOVE.L D0,-(SP) ; memory not used + MOVEA.L SONICmem(A2),A0 ; addr of SONIC memory + _GetPtrSize ,SYS + ADD.L (SP)+,D0 ; adjust pointer size + _SetPtrSize ,SYS +@loadCAM + SUBA.W #CAMparms.ParmSize,SP ; make room for CAM parms + MOVE.L #-1,CAMparms.LoadorClear(SP) ; add an entry + MOVE.L OurAddr+2(A2),CAMparms.EAddr+2(SP) + MOVE.W OurAddr(A2),CAMparms.EAddr(SP) + BSR SONICAddr ; thru next + MOVE.L A0,CAMparms.SONICPtr(SP) ; pass SONIC base address + + BSR DataCacheOff ; turn off data cache on LC 030 + BSR SONICCAMLOAD ; put our address in CAM + ADDA.W #CAMparms.ParmSize,SP + BSR DataCacheOn ; turn data cache back on +; perform 3 SONIC loopback tests, if any fails, return an open error + + + Move.l #SonicEnetLongStrEnd-SonicEnetLongStr-1, -(SP) ; pass size of loopback + ; data, minus 1 since pascal string + Pea SonicEnetLongStr+1 ; pass ptr to loopback data + PEA OurAddr(A2) ; pass ptr to our address + MOVEA.L OurDCE(A2),A1 ; get ptr to DCE + MOVE.W dCtlRefNum(A1),D0 + MOVE.L D0,-(SP) ; pass our refnum for ctl calls + + BSR SONICAddr + MOVEA.L A0,A3 ; SONIC base address + + SMOVE Recv_Control(A3),D0 ; get recv_control reg + EORI.W #(1<SONIC Registers + BSR ResetSONIC ; get ready to change FIFO threshholds + SMOVE Data_Config(A2),D0 ; get current configuration data + MOVE.L SONICCfg.DataCfgLpBk(A3), D1 ; get loopback setup data configuration
+ ANDI.W #$000F,D1 ; access only FIFO settings + EOR.W D1,D0 ; clear initial FIFO threshholds + MOVE.L SONICCfg.DataCfgRun(A3), D1 ; get runtime setup data configuration
+ OR.W D1,D0 ; set runtime threshholds (requests bus less often) + SMOVE D0,Data_Config(A2) + BSR RestartSONIC ; start SONIC back up for loopback tests + EXG A2,A3 ; A3->SONIC Registers + + ADDQ.W #8,SP ; strip loopback test parms + + MOVEA.L (SP)+,A1 ; get back DCE + + LEA VBLQEL(A2),A0 + MOVE.W #vType,vblType(A0) + PEA ControlDefer + MOVE.L (SP)+,vblAddr(A0) + MOVE.W #32767,vblCount(A0) ; setup control call deferral timer + _VInstall + + MOVEQ #noErr,D0 ; Indicate no error + UNLK A6 + RTS ; And return + +LoopError ; failed one of 3 loopback tests + ADDQ.W #8,SP ; strip loopback test parms + BSR Close ; shut down SONIC + MOVEA.L (SP)+,A1 ; get back DCE + MOVEQ #-1,D0 + BRA.S OpenErrDone ; return with open error +; +; Open error - clear out variable pointer for next try +; +OpenError + MOVE.W D0,D3 ; save error code + + MOVEA.L (SP)+,A1 ; A1->DCE + TST.L SONICmem(A2) + BEQ.S @55 ; mem not allocated + MOVEA.L SONICmem(A2),A0 + _DisposPtr ; free it up +@55 + LEA OurVarPtr,A3 ; A3 -> our variable pointer + CLR.L (A3) ; Clear it out + MOVE.W D3,D0 +OpenErrDone + CMPI.W #-1,D0 ; translate generic error + BNE.S @60 + MOVEQ #openErr,D0 +@60 + TST.W D0 + UNLK A6 + RTS ; Return with error + +NormAddr ; convert IEEE address to normal format + MOVEM.L D2,-(SP) + CLR.B D1 + MOVEQ #7,D2 +@loop + LSL.B #1,D1 ; get ready for next bit + LSR.B #1,D0 ; get a bit from source + BCC.S @lb ; non there + ADDQ.B #1,D1 +@lb + DBRA D2,@loop + MOVE.B D1,D0 ; D0=converted value + MOVEM.L (SP)+,D2 + RTS + + +; Ptr TranslateAddress(laddr,lsize) ; translate logical to physical addrs +MemBlk RECORD 0 +address DS.L 1 +count DS.L 1 + ENDR + +TraAdd RECORD {A6Link} +LinkSz EQU * +logical DS MemBlk +physical DS MemBlk +A6Link DS.L 2 ; link and return addr +laddr DS.L 1 ; logical address +lsize DS.L 1 ; logical size + ENDR +TranslateAddress + WITH TraAdd + LINK A6,#LinkSz + MOVE.L laddr(A6),logical.address(A6) + MOVE.L laddr(A6),physical.address(A6) + + MOVEA.L OurVarPtr,A0 + BTST #NeedDefer,([OurDCE,A0],dCtlStorage) + BNE.S @haveMemDispatch ; VM is running, ok to call _VM + + TST.B SONICCfg.SmartMMU(A0) ; no VM, do we have smart MMU code?
+ BEQ.S @nophy ; no, no need to get physical address
+@haveMemDispatch + MOVE.L lsize(A6),logical.count(A6) + LEA logical(A6),A0 ; A0->translation table + LEA 1,A1 ; A1=count to translate + MOVEQ #5,D0 ; selector + + _MemoryDispatch ; MemoryDispatch +@nophy ;
+ MOVE.L physical.Address(A6),D0 ; return lowest physical address + + UNLK A6 + RTS + ENDWITH + +; SR IntDisable(); ; disable interrupts and return SR +IntDisable + MOVE SR,D0 + ORI.W #$600,SR ; rb + RTS + +; void IntEnable(SR) ; restore SR from prior disable call +IntEnable + MOVE.W 6(SP),SR ; do it + RTS + +; IntInstallation(SONIChandler) + +IntInstallation ; called by SONIC init + WITH SlotIntQElement + LEA SONIChandler,A0 + MOVE.L 4(SP),(A0) ; store SONIC interrupt handler + LEA SONICintQ,A0 ; interrupt queue element + MOVE.W #sIQType,SQType(A0) ; set type + PEA SONICInterrupt ; addr of handler + MOVE.L (SP)+,SQAddr(A0) + MOVE.W #200,SQPrio(A0) ; priority for now + MOVEA.L OurVarPtr,A1 + SUB.L D0,D0 + MOVE.B SONICCfg.SONICSlot(A1), D0 ; setup slot from config values
+ _SIntInstall ; install handler + RTS + ENDWITH +SONICInterrupt + MOVEM.L A0/D1-D3,-(SP) ; Mac OS assumes these are scratch + BSR SONICAddr ; get SONIC address in A0 + MOVE.L A0,-(SP) ; pass SONIC base address + BSR DataCacheOff ; turn off data cache on LC 030 + MOVEA.L SONIChandler,A1 ; + JSR (A1) ; + ADDQ.W #4,SP ; + BSR DataCacheOn ; turn data cache back on + MOVEM.L (SP)+,A0/D1-D3 ; + MOVEQ #-1,D0 ; indicate we processed this interrupt + RTS + +;________________________________________________________________________ +; +; Control - control requests to driver - all ENET calls come in here. +; +; Call: A0 -> I/O queue element +; A1 -> device control entry +;________________________________________________________________________ + +ControlDefer ; task to complete a deferred control call + MOVE.W #32767,vblCount(A0) ; next task is a long time maybe + _StackSpace ; D0 = avail. stack space + TST.L D0 + BMI.S @defer ; defer if negative space + CMPI.L #512,D0 ; is there a little room? + BHS.S @doControl ; yes +@defer + MOVE.W #1,VBLCount(A0) ; restart fast timer +@exit + RTS ; and get out +@doControl + LEA -VBLQEL(A0),A2 ; A2->our vars + BCLR #0,deferCtl(A2) + BEQ.S @exit ; return to VBL if not really deferring + + MOVEA.L OurDCE(A2),A1 ; A1->our DCE + MOVEA.L dCtlQHead(A1),A0 ; A0->param block in use + BRA.S doControl +Control + MOVE.W ioTrap(A0),D0 ; get trap word that called us + + BTST #asyncTrpBit,D0 ; is this a synchronous call? + BEQ.S doControl ; yes, bypass stack check + + _StackSpace ; D0 = avail. stack space + TST.L D0 + BMI.S @defer ; defer if negative space + CMPI.L #512,D0 ; is there a little room? + BHS.S doControl ; yes +@defer + MOVEA.L OurVarPtr,A2 ; A2->our vars + BSET #0,deferCtl(A2) ; indicate we are deferring + MOVE.W #1,vblCount+VBLQEL(A2) ; set next vbl to tick fast +CRTS + MOVEQ #noErr,D0 ; good return for now + RTS ; get out and get stack back +doControl + MOVE.W CSCode(A0),D2 ; Pickup control code + SUBQ #KillCode,D2 ; Check for OS kill I/O call + BEQ.S CRTS ; return if so + + MOVEQ #ControlErr,D0 ; Assume a control error + MOVE.L OurVarPtr,A2 ; A2 -> our variables + SUB #FirstENET-KillCode,D2 ; Subtract off lowest command + BLT ENETDone ; Return error if too low + CMP #LastENET-FirstENET,D2 ; Make sure not too high + BGT ENETDone ; Return error if too high + MOVE CSParam(A0),D1 ; D1 = 1st parameter word (protocol) + MOVE.L CSParam+2(A0),D3 ; D3 = 1st parameter longword (e.g. WDSP) +; +; Pick up routine address for this command and jump to routine +; + MOVE.W (ControlTable,D2.W*2),D2 ; get offset of routine + JMP (ControlTable,D2.W) ; go do the call + +;_________________________________________________________________________ +; +; Control dispatch table - must be in the same order as the ENET commands. +; Specifies offsets to the command-handling routines. +;_________________________________________________________________________ + +ControlTable + DC.w ENETDONE-ControlTable ; 238 LapGetDot3Entry + DC.w ENETDONE-ControlTable ; 239 LapSetDot3Entry + DC.w ENETDONE-ControlTable ; 240 LapDot3Stats + DC.w ENETDONE-ControlTable ; 241 LapDot3CollStats + DC.w ENETDONE-ControlTable ; 242 LapGetLinkStatus + DC.w ENETOK-ControlTable ; 243 CloseSAP + DC.w ENETOK-ControlTable ; 244 OpenSAP + DC.w DoDelMulti-ControlTable ; 245 + DC.w DoAddMulti-ControlTable ; 246 + DC.w DoAttachPH-ControlTable ; 247 + DC.w DoDetachPH-ControlTable ; 248 + DC.w DoWrite-ControlTable ; 249 + DC.w DoRead-ControlTable ; 250 + DC.w DoRdCancel-ControlTable ; 251 + DC.w DoGetInfo-ControlTable ; 252 + DC.w ENETOK-ControlTable ; 253 DoSetGeneral +;___________________________________________________________________________ +; +; DoAddMulti - add a multicast address to the list +; +; Call: +; A2 -> our variables +; D1 = first two bytes of address +; D3 = last four bytes of address +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoAddMulti + MOVEQ #eMultiErr,D0 ; Assume invalid address or table full + BTST #8,D1 ; Make sure multicast bit is set + BEQ ENETDone ; Return error if invalid multicast address + BSR FindMEntry ; D2 = entry number for this address + BPL.S @40 ; Branch if found it +; +; Look for the first free one +; + MOVEQ #MTblSz-1,D2 ; D2 = no. of entries in multicast table +@30 TST.B (MultiCTbl+MUseCount,A2,D2*MEntrySz) + ; This one free? + DBEQ D2,@30 ; Loop until checked them all or got one +@35 BNE ENETDone ; Error if none free + +; +; Set in table, then compute and set hash bit in appropriate multicast address register (MAR) +; +@40 MOVE.L D3,(MultiCTbl+2,A2,D2*MEntrySz) + ; Set second part of address + MOVE D1,(MultiCTbl,A2,D2*MEntrySz) + ; Set first part of address + ADDQ.B #1,(MultiCTbl+MUseCount,A2,D2*MEntrySz) + CMPI.B #1,(MultiCTbl+MUseCount,A2,D2*MEntrySz) + BHI ENETOK + + + SUBA.W #CAMparms.ParmSize,SP ; make room for CAM parms + MOVE.L #-1,CAMparms.LoadorClear(SP) ; we are adding a CAM entry + MOVE.L D3,CAMparms.EAddr+2(SP) ; lower 32 bits + MOVE.W D1,CAMparms.EAddr(SP) ; upper 16 bits + BSR SONICAddr ; + MOVE.L A0,CAMparms.SONICPtr(SP) ; pass SONIC base address + BSR DataCacheOff ; turn off data cache on LC 030 + BSR SONICCAMLOAD ; add this entry + ADDA.W #CAMparms.ParmSize,SP + BSR DataCacheOn ; turn data cache back on + + BRA ENETOK ; That's it + + + +;___________________________________________________________________________ +; +; DoDelMulti - delete a multicast address to the list +; +; Call: +; A2 -> our variables +; D1 = first two bytes of address +; D3 = last four bytes of address +; +; Return: +; D0 = error code +; +; Decrements the use count for the given address +;___________________________________________________________________________ + +DoDelMulti MOVEQ #eMultiErr,D0 ; Assume address not found + BSR.S FindMEntry ; D2 = entry number in table + BMI.S ENETDone ; Return error if not found + SUBQ.B #1,(MultiCTbl+MUseCount,A2,D2*MEntrySz) + ; Decrement use count + BNE.S ENETOK + + + SUBA.W #CAMparms.ParmSize,SP ; make room for CAM parms + CLR.L CAMparms.LoadorClear(SP) ; we are deleting a CAM entry + MOVE.L D3,CAMparms.EAddr+2(SP) ; lower 32 bits + MOVE.W D1,CAMparms.EAddr(SP) ; upper 16 bits + BSR SONICAddr ; + MOVE.L A0,CAMparms.SONICPtr(SP) ; pass SONIC base address + BSR DataCacheOff ; turn off data cache on LC 030 + BSR SONICCAMLOAD ; delete this entry + ADDA.W #CAMparms.ParmSize,SP + BSR DataCacheOn ; turn data cache back on + + BRA.S ENETOK ; Return no error +; +; FindMEntry - find this address's entry in the multicast table +; +; Call: +; D1 = high two bytes of address +; D3 = low four bytes of address +; A2 -> our variables +; +; Return: +; D2 = entry number within table (minus if not found). CCR set. +; + +FindMEntry MOVEQ #MTblSz-1,D2 ; D2 = no. of entries in multicast table +@10 TST.B (MultiCTbl+MUseCount,A2,D2*MEntrySz) + ; Is this entry in use? + BEQ.S @20 ; Branch if not + CMP (MultiCTbl,A2,D2*MEntrySz),D1 + ; This it? + BNE.S @20 ; Branch if not + CMP.L (MultiCTbl+2,A2,D2*MEntrySz),D3 + ; Is it? + BEQ.S @30 ; Branch if got it +@20 DBRA D2,@10 ; Loop until checked them all +@30 TST D2 ; Set CCR + RTS ; And return + + + +;___________________________________________________________________________ +; +; DoAttachPH - attach protocol handler control call +; +; Call: +; A2 -> our variables +; D3 = address of protocol handler's packet-receive code or zero +; D1 = protocol type code +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoAttachPH + AND.L AddrMask(A2),D3 ; 32 bit clean + + MOVEQ #LAPProtErr,D0 ; Assume an invalid protocol error +; +; Read down the active protocol table, searching for a match +; +@10 BSR.S GetProt ; See if it's there + BPL.S ENETDone ; Return error if protocol already active +; +; Now scan for the first free one . . . +; + MOVEQ #LAPTblSz-1,D2 ; Index into active protocols list +@20 TST.B InUseFlag(A2,D2) ; Check this entry + DBEQ D2,@20 ; Loop until get one or end + BNE.S ENETDone ; Error if none + MOVE.L D3,(Handlers,A2,D2*4) ; Fill Handlers in first (in case of interrupt) + CLR.L (RdQueueHd,A2,D2*4) ; Clear out read queue head + MOVE D1,Protocols(A2,D2*2) + ; Fill protocol type in + ST InUseFlag(A2,D2) ; Indicate in use +ENETOK CLR D0 ; Indicate no error +ENETDone + MOVE.L OurDCE(A2),A1 ; Make sure A1 has DCE address + MOVE.L JIODone,-(SP) ; This is how we exit (Prime, Control, Status) + RTS + +; +; Lookup D1 in the protocol table. Return D2 = index to protocol (negative = error). +; +GetProt MOVEQ #LAPTblSz-1,D2 ; Index into active protocols list +@10 TST.B InUseFlag(A2,D2) ; In use? + BEQ.S @20 ; Branch if not + CMP Protocols(A2,D2*2),D1 ; Match? + BEQ.S @30 ; Branch if so +@20 DBRA D2,@10 ; Keep going until got one +@30 TST D2 ; Set CCR to D2 + RTS ; Return (BPL for match) +;___________________________________________________________________________ +; +; DoDetachPH - detach protocol handler control call +; +; Call: +; A2 -> our variables +; D1 = protocol type code +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +; +; Find the requested protocol +; +DoDetachPH + MOVEQ #LAPProtErr,D0 ; Assume no such protocol active + + BSR.S GetProt ; D2 = index to protocol + BMI.S ENETDone ; Return error if at end of table + CLR.B InUseFlag(A2,D2) ; Indicate entry free + TST.L (Handlers,A2,D2*4) ; Default handler? + BNE.S @10 ; All done if not + BSR.S AbortAll ; Abort all active reads +@10 BRA.S ENETOK ; Complete this call + + +; +; AbortAll - abort all active read requests. +; +; A2 -> our variables +; D2 = flag offset into protocol table +; Uses D1,A0 +; +; Assumes InUseFlag(A2,D2) cleared out already so no interrupts +; + +AbortAll MOVE.L (RdQueueHd,A2,D2*4),D1 ; D1 -> first read, if any + BEQ.S @10 ; Branch if none + MOVE.L D1,A0 ; A0 -> queue element + MOVE.L (A0),(RdQueueHd,A2,D2*4) ; Remove from queue + MOVE #reqAborted,D0 ; Set error code + BSR CompleteReq ; Return error + BRA.S AbortAll ; And loop + +@10 RTS +;___________________________________________________________________________ +; +; DoWrite - write out a packet on Ethernet +; +; Call: +; A2 -> our variables +; D3 = WDS pointer +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoWrite +; D3=ptr to caller's wds + MOVE SR,-(SP) + ORI.W #IntLockOut,SR ; no interrupts rb + + MOVE.L WrBuffHdr(A2),D2 ; get a buffer pointer + BNE.S @haveBuff + + ST XmitWait(A2) ; set waiting flag + MOVE (SP)+,SR + MOVEQ #noErr,D0 + RTS ; return to caller +@haveBuff + CLR.B XmitWait(A2) ; no longer waiting + + MOVEA.L D2,A1 ; A1->buffer + MOVE.L QLink(A1),WrBuffHdr(A2) ; unlink from buffer list + MOVE (SP)+,SR + + MOVE.L A1,-(SP) ; save buffer pointer for later + + MOVE.L D3,A0 ; A0 -> WDS + CMP #EHdrSize,(A0) ; First entry must have whole header + BLO.S @30 ; Error if not + MOVE.L 2(A0),A0 ; A0 -> first WDS entry + MOVE.L OurAddr(A2),ESrcAddr(A0) ; Set our address in it + MOVE OurAddr+4(A2),ESrcAddr+4(A0) + ; (all six bytes) + + MOVE.L A4,-(SP) ; save non-interrupt scratch reg. + + LEA Max_Pkt_Size(A1),A3 ; A3->singe fragment wds (len field) + + MOVEQ #-EHdrSize,D2 ; setup for len check
+ + CLR.W (A3) ; init len
+ MOVE.L D3,A4 ; A4-> caller's WDS
+@x1 + MOVEQ #0,D0 + MOVE.W (A4)+,D0 ; get this frag length + BEQ.S @x2 ; all done + BMI.S @LenError ; negative values not allowed
+ + ADD.W D0,D2 ; accum length + CMP.W MaxData(A2),D2 ; check length so far + BHI.S @LenError ; bad, get out with error + + ADD.W D0,(A3) ; sum the length in WDS + MOVEA.L (A4)+,A0 ; get pointer to the data +;a0->source, a1->dest, d0=len + MOVEM.L A1/D0/D2,-(SP) ; save buff ptr and len + JSR ([BlockMove,A2]) ; move the data + MOVEM.L (SP)+,A1/D0/D2 ;
+ ADDA.L D0,A1 ; update buff ptr + BRA.S @x1 ; look for more +@x2 + MOVEA.L (SP)+,A4 ; restore non-interrupt scratch reg. + BRA.S @sendit ; go and send it now
+ +@LenError ; packet length is invalid + MOVEA.L (SP)+,A4 ; restore this reg.
+@30 + MOVE.L (SP)+,A3 ; A3->buffer + MOVE SR,-(SP) + ORI.W #IntLockOut,SR ; rb + + MOVE.L WrBuffHdr(A2),(A3) ; link buffer back to list + MOVE.L A3,WrBuffHdr(A2) + + MOVE (SP)+,SR + + MOVEQ #eLenErr,D0 ; Set length error + BRA ENETDone ; Return it + +@sendit + MOVE.L (SP),-(SP) ; dup TOS
+ ADDI.L #Max_Pkt_Size,(SP) ; pass wds pointer
+ BSR SONICAddr + MOVE.L A0,-(SP) ; pass base address of SONIC + + BSR DataCacheOff ; turn off data cache on LC 030 + BSR SONICXMIT ; send the packet + ADDQ.W #8,SP + BSR DataCacheOn ; turn data cache back on + + BEQ.S @TxOK ; SONIC was able to handle xmit + + MOVE.L (SP)+,A3 ; A3->buffer + MOVE SR,-(SP) + ORI.W #IntLockOut,SR ; rb + + MOVE.L WrBuffHdr(A2),(A3) ; link buffer back to list + MOVE.L A3,WrBuffHdr(A2) + + MOVE (SP)+,SR ; + + BSET #0,deferCtl(A2) ; indicate we are deferring + MOVE.W #1,vblCount+VBLQEL(A2) ; set next vbl to tick fast + MOVEQ #noErr,D0 + RTS +@TxOK + ADDQ.W #4,SP ; trash buffer pointer + + MOVEQ #noErr,D0 + MOVEA.L ourDCE(A2),A1 ; A1->DCE + MOVEA.L JIODone,A0 + JMP (A0) ; all done now + +; +; Tramsmit Complete routine (called from SONICInterrupt): + +TxPrm RECORD 4 +TxDesc DS.L 1 ; ptr to Xmit descriptor +TxParms DS.L 1 ; ptr to OurVars +TxPrmSz EQU * ; size of record + ENDR + +XmitDone + MOVEA.L OurVarPtr,A0 ; get ptr to our vars thru next + MOVEA.L OurDCE(A0),A1 ; get our DCE ptr + BTST #NeedDefer,dCtlStorage(A1) ; is VM running? + BEQ.S @noVM ; no, just proceed + + MOVE.L TxPrm.TxDesc(SP),A1 ; + BSR.S GetDescPhAddr ; get physical write buffer address in D0 + LEA @deferWrite,A0 ; routine to call when safe + _DeferUserFn ; defer the routine + RTS +@deferWrite + MOVEA.L A0,A1 ; A1->physical address of write buffer + MOVEA.L OurVarPtr,A0 ; + MOVEM.L A2/A3/D3,-(SP) ; save C regs + BRA.S @findXmitBuffer ; +@noVM ; + MOVE.L TxPrm.TxDesc(SP),A1 ; get ptr to descriptor + + MOVEM.L A2/A3/D3,-(SP) ; save C regs + + BSR.S GetDescPhAddr ; get physical write buffer address in D0 + MOVEA.L D0,A1 ; A1->xmit buffer (physical address) +@findXmitBuffer ; + MOVEA.L PLTable(A0),A2 ; A2->translation table + MOVE.L XmitBuffs(A0),D0 ; D0=#xmit buffers + SUBQ.W #1,D0 ; base zero +@cmp + CMPA.L PtoL.Physical(A2),A1 ; found it? + ADDQ.W #PtoL.Size,A2 + DBEQ D0,@cmp ; keep looking if not + + BNE.S @done ; safety, should not happen + + MOVEA.L PtoL.Logical-PtoL.Size(A2),A1 ; replace physical with logical address + + MOVE SR,-(SP) + ORI.W #IntLockOut,SR ; rb + + MOVE.L WrBuffHdr(A0),(A1) ; link buffer back into list + MOVE.L A1,WrBuffHdr(A0) + + MOVE (SP)+,SR + + TST.B XmitWait(A0) ; any pending xmits? + BEQ.S @done ; leave if not + + MOVEA.L A0,A2 ; A2->our vars + MOVEA.L OurDCE(A2),A1 ; A1->our DCE + MOVE.L dCtlQHead(A1),A0 ; A0->waiting write param blk + + MOVE.L CSParam+2(A0),D3 ; D3 = 1st parameter longword (e.g. WDSP) + + BSR DoWrite ; process the write +@done + MOVEM.L (SP)+,A2/A3/D3 ; restore C regs + RTS + +GetDescPhAddr ; get physical address of descriptor in D0
+ SMOVE TxPkt.frag_ptr1(A1),D0 ; get upper 16 bits of buffer address + SWAP D0 + SMOVE TxPkt.frag_ptr0(A1),D1 ; get lower 16 bits of buffer address + MOVE.W D1,D0 ; D0=xmit buffer (physical address)
+ RTS +;___________________________________________________________________________ +; +; DoRead - read a packet off the Ethernet +; +; Call: +; A0 -> queue element +; A1 -> our DCE +; A2 -> our variables +; D1 = protocol type code +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoRead MOVEQ #LAPProtErr,D0 ; Assume an error + BSR GetProt ; D2 = index into PH table + BMI ENETDone ; Error if not there + TST.L (Handlers,A2,D2*4) ; Is it the default? + BNE ENETDone ; Error if not + MOVE #buf2SmallErr,D0 ; Assume buffer not big enough + CMP #EHdrSize,EBuffSize(A0) ; Must hold at least header + BLO ENETDone ; Return error if not +; +; Dequeue the request from the system queue and queue it on ours (in order) +; + LEA (RdQueueHd,A2,D2*4),A3 ; A3 -> queue head + MOVE SR,-(SP) ; Save interrupt status + ORI.W #IntLockOut,SR ; Disable interrupts rb +@10 TST.L (A3) ; Is there a next element? + BEQ.S @20 ; Branch if not + MOVE.L (A3),A3 ; Point to it if so + BRA.S @10 ; And keep going until end + +@20 + EXG D0,A0 + AND.L AddrMask(A2),D0 + EXG D0,A0 ; 32 bit clean + + MOVE.L A0,(A3) ; Put queue element on our queue + BCLR #DrvrActive,DCtlFlags+1(A1) + ; Clear driver active flag + MOVE.L IOLink(A0),DCtlQHead(A1) ; Set next element addr in head + BNE.S @30 ; Branch if there is none + CLR.L DCtlQTail(A1) ; Clear tail if not +@30 CLR.L IOLink(A0) ; Indicate it's last one on our queue + MOVE.L DCtlQHead(A1),D0 ; Any more requests? + BEQ.S @40 ; Branch if not + BSET #DrvrActive,DCtlFlags+1(A1) + ; We're active again + MOVE (SP)+,SR ; Restore interrupt state + MOVE.L D0,A0 ; A0 -> new queue element + MOVEQ #0,D0 ; D0 should be clear + BSR Control ; Call ourselves + MOVEQ #0,D0 ; Return no error for previous call + RTS ; Return + +@40 MOVE (SP)+,SR ; Restore interrupt state + RTS ; Return +;___________________________________________________________________________ +; +; DoRdCancel - abort a pending read call +; +; Call: +; A2 -> our variables +; D3 = pointer to queue element to abort +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoRdCancel MOVE #CBNotFound,D0 ; Assume an error + AND.L AddrMask(A2),D3 ; 32 bit clean + MOVE.L D3,A1 ; A1 -> queue element + MOVE EProtType(A1),D1 ; D1 = protocol type + BSR GetProt ; D2 = index into PH table + BMI.S @60 ; Error if not there + TST.L (Handlers,A2,D2*4) ; Is it the default? + BNE.S @60 ; Error if not + LEA (RdQueueHd,A2,D2*4),A3 ; A3 -> queue head + MOVE SR,-(SP) ; Save interrupt status + ORI.W #IntLockOut,SR ; Disable interrupts rb +@30 MOVE.L (A3),D3 ; D3 -> next element in queue + AND.L AddrMask(A2),D3 ; 32 bit clean + BEQ.S @50 ; Error if no more + SUB.L A1,D3 ; Subtract out desired one + BEQ.S @40 ; Branch if it's the one + MOVE.L (A3),A3 ; A3 -> next in queue + BRA.S @30 ; Keep looking + +@40 MOVE.L (A1),(A3) ; Point previous to next + MOVE (SP)+,SR ; Restore interrupts +; +; Complete the ERead with an error, then the ERdCancel +; + MOVE.L A1,A0 ; A0 -> ERead queue element + MOVE #ReqAborted,D0 ; D0 = aborted error + BSR.S CompleteReq ; Complete it with error + BRA ENETOk ; Return no error for RdCancel + +@50 MOVE (SP)+,SR ; Restore interrupt state +@60 BRA ENETDone ; Return not found error + + +;________________________________________________________________________ +; +; CompleteReq - this code basically executes the parts of IODone necessary to +; complete the user's request (sets result code and executes the user's +; completion routine) +; +; Call: +; D0 = result code +; A0 -> I/O queue element +;________________________________________________________________________ + +CompleteReq MOVE.W D0,IOResult(A0) ; Set the result code + MOVEM.L D1-D3/A0-A3,-(SP) ; Save registers + MOVE.L IOCompletion(A0),D1 ; Check if there's a completion routine + BEQ.S @10 ; Branch if not - just return + MOVE.L D1,A1 ; Get it if so + TST.W D0 ; IODone does this + JSR (A1) ; Call completion routine +@10 MOVEM.L (SP)+,D1-D3/A0-A3 ; Restore registers + RTS ; Return +;___________________________________________________________________________ +; +; DoGetInfo - return our node address +; +; Call: +; A0 -> queue element +; A2 -> our variables +; D3 -> buffer for response +; +; Return: +; D0 = error code +;___________________________________________________________________________ + +DoGetInfo + AND.L AddrMask(A2),D3 ; 32 bit clean + + MOVEA.L A0,A3 ; save param blk ptr + MOVEQ #0,D0 ; Clear out D0 + MOVE EBuffSize(A3),D0 ; D0 = buffer size + CMP #InfoEnd-InfoStart,D0 ; Asking for more than we have? + BLS.S @10 ; Branch if not + MOVEQ #InfoEnd-InfoStart,D0 ; If so, just return what we have +@10 MOVE.L D3,A1 ; A1 -> where to move to + LEA InfoStart(A2),A0 ; A0 -> where to move from + PEA (A1,D0.L) ; next spot to move to + MOVE.L D0,-(SP) ; current move len + _BlockMove ; Move it + MOVE.W EBuffSize(A3),D0 + SUB.L (SP)+,D0 ; D0=len left in user buffer + MOVEA.L (SP)+,A1 ; A1->user buffer + BLS ENETOK ; no more user buffer + + CMPI.L #NetStats.Size,D0 + BLS.S @15 ; only move what is left + MOVE.L #NetStats.Size,D0 +@15 + LEA EtherStats(A2),A0 ; A0->stats + _BlockMove ; move them in + BRA ENETOK ; Return no error + + +;___________________________________________________________________________ +; +; EtherRecv - receive routine - called by slot manager +; +; Called: +; A1 = value passed in SIntInstall call (DCE pointer) +; +; Return: +; D0 <> 0 to indicate interrupt has been serviced +; A1 may be modified +; +; We disable AppleTalk interrupts, since incoming ATalk packet could cause a +; 20 msec hickup, whereas we'll generally take about 1/2 msec. +;___________________________________________________________________________ + +; EtherRecv(status,len,data,parms,buffdesc) + +EtherRecv ; thru next + MOVEA.L OurVarPtr,A1 + MOVEA.L OurDCE(A1),A1 ; A1->DCE + BTST #NeedDefer,dCtlStorage(A1) ; indicate VM is running + BEQ.S @noVM ; no, just continue + + MOVEA.L OurVarPtr,A0 ; A0->our vars + LEA RxDefBuffs-RxParms.ParmsSz(A0),A1 + ; point at parameter storage + MOVEQ #NumBuffers-1,D0 ; loop to find an empty one +@findRxDef + LEA RxParms.ParmsSz(A1),A1 ; bump pointer to next one + TST.L RxParms.InUse(A1) ; find an available storage area + DBEQ D0,@findRxDef ; keep searching + BNE.S @noVM ; safety, should not happen + + PEA (A1) ; save ptr to storage + LEA RxParms.Status(SP),A0 ; setup source addr (stack already aligned) + MOVEQ #RxParms.ParmsSz,D0 ; move size + _BlockMove ; save parameters + MOVE.L (SP)+,D0 ; param to pass to defer routine + LEA @deferRecv,A0 ; routine to defer + _DeferUserFn + RTS +@deferRecv + MOVE.L A0,-(SP) ; save frame storage ptr + SUBA.W #RxParms.ParmsSz,SP ; make param storage on stack + MOVEA.L SP,A1 ; A1->frame + MOVEQ #RxParms.ParmsSz,D0 + _BlockMove ; set frame data + + BSR.S @noVM ; now do the receive routine + + ADDA.W #RxParms.ParmsSz,SP ; strip param storage + MOVEA.L (SP)+,A0 ; get back storage ptr + CLR.L RxParms.InUse(A0) ; mark entry as free + RTS ; done +@noVM + LINK A6,#RxParms.Size + + MOVEM.L A2-A5/D3,-(SP) ; save C regs + + MOVE.L OurVarPtr,A2 ; A2 -> our variables + MOVE.L RxParms.RxDesc(A6),LastRxDesc(A2) + ; save descriptor pointer +; +; Process the receive interrupt +; + MOVEA.L RxParms.Data(A6),A0 ; A0->packet data + + MOVE.L RxParms.Status(A6),D1 ; get packet status + BTST #ReceivedOK,D1 ; was packet received OK? + BEQ.S @85 ; don't process if not + + MOVE.L RxParms.Length(A6),D1 ; d1=size of packet + SUBQ #4,D1 ; Subtract off FCS bytes +; +; Copy the Ethernet header from the packet into the RHA +; + LEA RHA(A2),A3 ; A3 -> RHA + MOVEQ #EHdrSize/2-1,D0 ; D0 = header count to move +@40 MOVE (A0)+,(A3)+ ; Move from card to RHA + DBRA D0,@40 ; Move them all + SUB #EHdrSize,D1 ; Subtract out header bytes from total +; +; Search the protocol handler table for this protocol +; + +@50 MOVE EType-EHdrSize(A3),D0 ; D0 = protocol type or 802.3 length + CMP.W #EMaxDataSz,D0 ; is it an 802.3? + BHI.S @110 ; if not, try other protocols + + CLR D0 ; Handler will be for type zero + EXG D0,D1 ; D1 = protocol type, D0 = old D1 + BSR GetProt ; D2 = offset in table + EXG D0,D1 ; Restore D0, D1 + BMI.S @85 ; Branch if not found + MOVE EType-EHdrSize(A3),D0 ; D0 = protocol type + +@70 LEA EReadPacket,A4 ; A4 -> our ReadPacket routine + LEA DefaultPH,A5 ; use default maybe + MOVE.L (Handlers,A2,D2*4),D3 ; call the protocol handler + BEQ.S @80 ; use default + MOVEA.L D3,A5 ; use table entry address +@80 + JSR (A5) +@85 + MOVEA.L OurVarPtr,A2 + MOVE.L LastRxDesc(A2),D0 + BEQ.S @90 ; descriptor already freed + MOVE.L D0,-(SP) + BSR SONICFREEBUFF + ADDQ.W #4,SP +@90 + MOVEM.L (SP)+,A2-A5/D3 ; Restore registers + UNLK A6 + RTS ; That's it +; +; Find Protocol handler for non 802.3 packet +; +@110 + EXG D0,D1 ; D1 = protocol type, D0 = old D1 + BSR GetProt ; D2 = offset in table + EXG D0,D1 ; Restore D0, D1 + BMI.S @85 ; Branch if not found + + BRA.S @70 ; Process it + +FreeDescriptor ; free current receive descriptor + MOVEM.L D0-D2/A2,-(SP) ; save regs + MOVEA.L OurVarPtr,A2 ; get our vars + MOVE.L LastRxDesc(A2),-(SP) ; pass descriptor pointer + CLR.L LastRxDesc(A2) ; inidicate it has been freed + BSR SONICFREEBUFF ; free this descriptor + ADDQ.W #4,SP + MOVEM.L (SP)+,D0-D2/A2 + TST.W D0 + RTS + +;___________________________________________________________________________ +; +; EReadPacket - read in the specified number of bytes into the specified +; buffer. Asking for more than there is is an error. +; +; EReadRest - read in the rest of the packet, putting the specified number +; of bytes into the specified buffer, and ignoring the rest. +; +; Call: +; A0 -> current location in card memory +; A1 -> card registers +; A3 -> buffer to read into +; A4 -> start of ReadPacket +; D1 = number of bytes left to come in (caller may decrease) +; D3 = byte count to read +; +; Return: +; D0 = error byte (Z bit set in CCR) +; D1 updated (ReadPacket) +; D2 saved +; D3 = 0 if exact number of bytes requested were read +; > 0 indicates number of bytes requested but not read +; (packet smaller than requested maximum) +; < 0 indicates number of extra bytes read but not returned +; (packet larger than requested maximum) +; A0,A1 preserved by ReadPacket, modified by ReadRest +; A2 saved +; A3 -> one past where last character went +; A4,A5 saved (until packet's all in or error) +;___________________________________________________________________________ + +EReadPacket BRA.S EDoRP ; Need this for two entry points + +EReadRest MOVE D3,D0 ; D0 = number of bytes to return + SUB D1,D0 ; D0 = remainder count + TST D3 ; Check for zero + BEQ.S @10 ; If so, don't waste our time + BSR.S MoveBytes ; Move the bytes in +@10 MOVE D0,D3 ; D3 = remainder count + MOVEQ #0,D0 ; No error no matter what + BRA.S FreeDescriptor ; let SONIC have descriptor back + +EDoRP + CMP.W D3,D1 + BLO.S @5 ; error in request + BSR.S MoveBytes ; Move in the bytes + TST D3 ; Moved them all? + BEQ.S @10 ; Branch if moved all ok +@5 + MOVEQ #eLenErr,D0 ; Set length error + BRA.S FreeDescriptor ; let SONIC have descriptor back +@10 RTS ; Return +;___________________________________________________________________________ +; +; DefaultPH - default protocol handler - complete an ERead call if there +; +; Called: +; A0,A1: preserve until ReadRest +; A2 -> local variables +; A4 -> EReadPacket +; A5 usable until ReadRest +; D0 = protocol type +; D2 = index into protocol table +; Interrupts are off +; +;___________________________________________________________________________ + +DefaultPH + MOVE.L (RdQueueHd,A2,D2*4),D0 ; D0 -> first ERead on queue + BEQ.S @20 ; Skip packet if none + MOVE.L D0,A5 ; A5 -> ERead queue element + MOVE.L (A5),(RdQueueHd,A2,D2*4) ; Remove from queue + MOVE.L D0,D2 ; D2 = queue element pointer + MOVE.L EBuffPtr(A5),A3 ; A3 -> buffer to read into + MOVE EBuffSize(A5),D3 ; D3 = maximum size to read + SUB #EHdrSize,D3 ; Adjust for header + LEA RHA(A2),A5 ; A5 -> header info + MOVE.L (A5)+,(A3)+ ; Move header into buffer + MOVE.L (A5)+,(A3)+ ; Hard code for speed + MOVE.L (A5)+,(A3)+ ; (AssumeEq?) + MOVE (A5)+,(A3)+ ; A3 -> buffer after header + JSR 2(A4) ; Read in the whole thing (D0=0) + MOVE.L D2,A0 ; A0 -> queue element again + MOVE EBuffSize(A0),D1 ; D1 = original request size + SUB D3,D1 ; D1 = total packet size + MOVE D1,EDataSize(A0) ; Set in queue element + TST D3 ; Check for buffer overflow + BPL.S @10 ; Branch if no overflow + MOVE #buf2SmallErr,D0 ; Set error +@10 BRA CompleteReq ; Complete request and return + +@20 MOVEQ #0,D3 ; Indicate no buffer + JMP 2(A4) ; Ignore packet and return + + +;___________________________________________________________________________ +; +; MoveBytes - move bytes from card memory to desired place +; +; Call: +; A0 -> current location in card memory +; A3 -> place to move bytes to +; D1 = number of bytes left in packet +; D3 = number of bytes to move +; +; Return: +; A0 adjusted +; A3 adjusted past bytes moved in +; D1 adjusted +; D3 = zero if all could be moved, remainder otherwise +;___________________________________________________________________________ + +MoveBytes + + MOVEM.L D0/D2/A1/A2,-(SP) ; Save registers + MOVE.L OurVarPtr,A2 ; A2 -> our variables + EXG D0,A3 + AND.L AddrMask(A2),D0 + EXG D0,A3 ; 32 bit clean + MOVE.L A3,A1 ; A1 -> where to move to + MOVEQ #0,D0 ; D0 = number of bytes to move + MOVE D3,D0 ; Assume we can move all asked for + CMP D1,D3 ; Can we move all asked for? + BLS.S @10 ; Branch if so + MOVE D1,D0 ; Else move all we can +@10 SUB D0,D1 ; Adjust count left to come in + SUB D0,D3 ; D3 = bytes not moved + ADDA.W D0,A3 + + MOVE.L D1,-(SP) ; save this one + MOVE.L A0,-(SP) + MOVE.L D0,-(SP) + JSR ([BlockMove,A2]) ; call block move routine + MOVEA.L (SP)+,A0 + ADDA.L (SP)+,A0 ; adjust pointer + MOVE.L (SP)+,D1 + +@30 MOVEM.L (SP)+,D0/D2/A1/A2 ; Restore registers + RTS ; That's it +;________________________________________________________________________ +; +; Close - close the ENET driver. +; +; A1 -> DCE +;________________________________________________________________________ + +Close +; This code is never really called because no use-count in implemented for the .ENET driver +; and multiple clients could be using it, e.g. MacTCP. + MOVE.L OurVarPtr,A2 ; A2 -> our variables + + BSR SONICAddr ; get SONIC base in A0 + MOVE.L A0,-(SP) ; pass SONIC base address + BSR.S DataCacheOff ; turn off data cache on LC 030 + BSR SONICHALT ; stop SONIC + ADDQ.W #4,SP ; + BSR DataCacheOn ; turn data cache back on + + MOVEA.L SONICmem(A2),A0 + _DisPosPtr ; get rid of storage + + MOVEQ #LAPTblSz-1,D2 ; D2 = Index into active protocols list +@10 TST.B InUseFlag(A2,D2) ; Active? + BEQ.S @20 ; Branch if not + TST.L (Handlers,A2,D2*4) ; Default handler + BNE.S @20 ; Branch if not + BSR AbortAll ; Abort all requests +@20 DBRA D2,@10 ; On to next + LEA SONICintQ,A0 ; interrupt queue element + MOVEQ #0,D0 ; Clear out D0 + MOVE.B SONICCfg.SONICSlot(A2), D0 ; setup slot from config values
+ _SIntRemove ; Remove us from interrupt queue + + LEA VBLQEL(A2),A0 + TST.L vblAddr(A0) ; did we launch ctl call VBL? + BEQ.S @50 + _VRemove ; remove VBL task if so +@50 + MOVEA.L OurVarPtr,A0 ; + _DisPosPtr ; + + LEA OurVarPtr,A2 ; A2 -> variable pointer + CLR.L (A2) ; Clear it out (no variables) + MOVEQ #0,D0 ; Indicate no error +AnRTS RTS ; And return + +; for LC 030 not running VM, turn data caching off so SONIC can DMA and we see it +DataCacheOff + MOVEA.L OurVarPtr,A0 + TST.B SONICCfg.SmartMMU(A0) ; do we have smart MMU code?
+ BNE.S @done ; yes, memory is locked and non-cacheable
+ BTST #NeedDefer,([OurDCE,A0],dCtlStorage) + BNE.S @done ; VM running, don't alter data cache + MOVE SR,-(SP) + ORI.W #IntLockOut,SR ; Disable interrupts rb + ADDQ.L #1,CacheCount(A0) ; bump use count + TST.L DataCache(A0) + BNE.S @done0 ; data cache already disabled + MOVEC CACR,D0 + MOVE.L D0,DataCache(A0) ; save current CACR + BSET #11,D0 ; purge data in data cache + BCLR #8,D0 ; disable data caching + MOVEC D0,CACR ; do it +@done0 + MOVE (SP)+,SR ; reenable interrupts +@done + RTS + +DataCacheOn ; reenable data caching on LC030 + MOVEM.L A0/D0,-(SP) + MOVE CCR,-(SP) ; save current condition flags + MOVEA.L OurVarPtr,A0 + TST.B SONICCfg.SmartMMU(A0) ; do we have smart MMU code?
+ BNE.S @done ; yes, memory is locked and non-cacheable
+ BTST #NeedDefer,([OurDCE,A0],dCtlStorage) + BNE.S @done ; VM running, don't alter data cache + MOVE SR,-(SP) + ORI.W #IntLockOut,SR ; Disable interrupts rb + SUBQ.L #1,CacheCount(A0) ; decrement use count + BNE.S @done0 ; not ready for reenable, nested disables + MOVE.L DataCache(A0),D0 + CLR.L DataCache(A0) + MOVEC D0,CACR ; reenable data caching +@done0 + MOVE (SP)+,SR ; reenable interrupts +@done + MOVE (SP)+,CCR ; restore condition flags + MOVEM.L (SP)+,A0/D0 + RTS + +AddrPromAddr ; return address of Ethernet PROM in A0 + MOVEA.L SONICCfg.EnetPROM(A2), A0 ; obtain address
+ RTS +SONICAddr + LEA ([OurVarPtr],SONICCfg), A0 ;
+ TST.B MMU32Bit + BEQ.S @setBase24 ; no adjustment for 24 bit + MOVEA.L SCFG.SONICbase32(A0), A0 ; obtain address for 32 bit + RTS +@setBase24 + MOVEA.L SCFG.SONICbase24(A0), A0 ; obtain address for 24 bit
+ RTS +; +; Variable storage +; +OurVarPtr DC.L 0 ; Pointer to our variables +SONICintQ DCB.B SlotIntQElement.sqHDSize,0 ; queue element for interrupts +SONIChandler DC.L 0 + END + + + diff --git a/DeclData/DeclNet/Sonic/SonicEnet.a.idump b/DeclData/DeclNet/Sonic/SonicEnet.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Sonic/SonicEnet.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Sonic/SonicEnet.a.rdump b/DeclData/DeclNet/Sonic/SonicEnet.a.rdump new file mode 100644 index 0000000..abd8025 --- /dev/null +++ b/DeclData/DeclNet/Sonic/SonicEnet.a.rdump @@ -0,0 +1,31 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0072 742B 2430 3034" /* ..Monaco.rt+$004 */ + $"3420 2D20 7468 6520 7374 6F72 7920 636F" /* 4 - the story co */ + $"6E74 0006 0004 0031 000B 023A 02EC 0031" /* nt.....1...:...1 */ + $"000B 023A 02EC A783 0EA8 0000 00DD 0000" /* ...:............ */ + $"017A 0000 0000 0100" /* .z...... */ +}; + +data 'MPSR' (1008) { + $"0031 000B 023A 02EC 0031 000B 023A 02EC" /* .1...:...1...:.. */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"58E5 6215 3FE5 3230 0004 0000 0000 0000" /* X.b.?.20........ */ + $"0000 A933 73AB A933 73AB A6F7 B0F2 0078" /* ...3s..3s......x */ + $"C6B2 0000 0003 0007 2653 7570 6572 4D61" /* ........&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA53 6F6E 6963 BA00" /* .DeclNet.Sonic.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0134 000B 536F 6E69 6345 6E65 742E 6100" /* .4..SonicEnet.a. */ + $"0000 007A 446F 206E 6F74 206D 6F76 6520" /* ...zDo not move */ + $"2324 3236 3030 2074 6F20 7468 6520 7374" /* #$2600 to the st */ + $"6174 7573 2072 6567 6973 7465 722C 2061" /* atus register, a */ + $"6C77 6179 7320 646F 2061 6E20 4F52 492E" /* lways do an ORI. */ + $"5720 7769 7468 2069 7420 736F 2074 6861" /* W with it so tha */ + $"7420 4E75 4B65 726E 656C 2077 6F72 6B73" /* t NuKernel works */ + $"2061 6E64 2074 6865 2073 7461 636B 2069" /* and the stack i */ + $"7320 6E6F 7420 6368 616E 6765 642E 00" /* s not changed.. */ +}; + diff --git a/DeclData/DeclNet/Sonic/SonicEqu.a b/DeclData/DeclNet/Sonic/SonicEqu.a new file mode 100644 index 0000000..b7e06ab --- /dev/null +++ b/DeclData/DeclNet/Sonic/SonicEqu.a @@ -0,0 +1,501 @@ +; +; File: SonicEqu.a +; +; Contains: Sonic-specific equates +; +; Written by: Sean Findley +; +; Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved. +; +; This file is used in these builds: Mac32 +; +; Change History (most recent first): +; +; <1> 10/6/92 GDW New location for ROMLink tool. +; <1> 6/12/92 RLM first checked in +; 02/07/92 jmp (jmp,H2/BG/SJF,Z4) Rolled in SMOVE macro def and SonicAddress +; def. +; <1> 2/4/92 mal first checked in +; ——————————————————————————————————————————————————————————————————————————————————————— +; Pre-Pandora ROM comments begin here. +; ——————————————————————————————————————————————————————————————————————————————————————— +; <3> 2/26/91 JK Added extended Motorola mode equates. +; <2> 1/30/91 JK Added code review changes. +; <1> 12/14/90 JK Added to build +; +; To Do: +; + +; SonicEqu.a - Equates for SONIC +; written by Sean J. Findley Jan. 1990 + +; Copyright (c) 1990 Apple Computer, Inc. + + MACRO + CtlRegPad + IF CTLPAD THEN + ORG *+2 + ENDIF + ENDM + + MACRO ; thru next + SMOVE &src,&dest + IF SONIC32 THEN + MOVE.L &src,&dest + ELSE + MOVE.W &src,&dest + ENDIF + ENDM ; + +;•••••••••••••••• SONIC Registers +SONICRegs RECORD 0 + IF SONIC32 THEN +Command DS.L 1 ; (CR) SONIC control +Data_Config DS.L 1 ; (DCR) packet configuration +Recv_Control DS.L 1 ; (RCR) pkt reception control +Trans_Control DS.L 1 ; (TCR) Transmission control +Int_Mask DS.L 1 ; (IMR) interrupt mask +Int_Status DS.L 1 ; (ISR) interrupts status bits +Upper_TDA DS.L 1 ; (UTDA) upper 16 bits of TDA address +Current_TDA DS.L 1 ; (CTDA) 16 bit ptr to current TDA +Trans_PktSize DS.L 1 ; (TPS) total size of outbound pkt +Trans_FragCount DS.L 1 ; (TFC) transmit fragment count +Trans_PktStart0 DS.L 1 ; (TSA0) lower 16 bit of pkt addr +Trans_PktStart1 DS.L 1 ; (TSA1) upper " +Trans_FragSize DS.L 1 ; (TFS) current fragment size +Upper_RDA DS.L 1 ; (URDA) upper 16 bits of RDA address +Current_RDA DS.L 1 ; (CRDA) 16 bit ptr to current RDA +Recv_RBA0 DS.L 1 ; (CRBA0) lower 16 bit receive addr in RBA +Recv_RBA1 DS.L 1 ; (CRBA1) upper 16 bit recive addr in RBA +Buff_Cnt0 DS.L 1 ; (RBWC0) lower 16 bit of word count in RBA +Buff_Cnt1 DS.L 1 ; (RBWC1) upper " +End_Buff DS.L 1 ; (EOBC) end of buffer word count +Upper_RRA DS.L 1 ; (URRA) upper 16 bits of RRA address +RRA_Start DS.L 1 ; (RSA) 16 bit ptr to RRA +RRA_End DS.L 1 ; (REA) 16 bit ptr to end of RRA +RRA_Read DS.L 1 ; (RRP) where SONIC gets next read resource +RRA_Write DS.L 1 ; (RWP) where host puts new read resources +TRBA0 DS.L 1 ; (TRBA0) used by SONIC +TRBA1 DS.L 1 ; (TRBA1) " +TBWC0 DS.L 1 ; (TBWC0) " +TBWC1 DS.L 1 ; (TBWC1) " +ADDR0 DS.L 1 ; (ADDR0) " +ADDR1 DS.L 1 ; (ADDR1) " +LLFA DS.L 1 ; (LLFA) " +TTDA DS.L 1 ; (TTDA) " +CAM_EntryPtr DS.L 1 ; (CEP) points to CAM cell +CAM_Port2 DS.L 1 ; (CAP2) selects upper 16 bits of CAM cell +CAM_Port1 DS.L 1 ; (CAP1) selects middle 16 bits of CAM cell +CAM_Port0 DS.L 1 ; (CAP0) selects lower 16 bits of CAM cell +CAM_Enable DS.L 1 ; (CE) CAM enable register turns cells on/off +CAM_DescPtr DS.L 1 ; (CDP) 16 bit ptr to current CAM descriptor +CAM_Count DS.L 1 ; (CDC) count of CAM descriptors +Silicon_Rev DS.L 1 ; (SR) rev info on SONIC chip +Timer0 DS.L 1 ; (WT0) lower 16 bits of SONCIC timer +Timer1 DS.L 1 ; (WT1) upper 16 " +Recv_SeqCnt DS.L 1 ; (RSC) receive sequence counter +CRC_Err DS.L 1 ; (CRCT) CRC error count +FAE_Err DS.L 1 ; (FAET) frame alignment error count +MissedPkt_Err DS.L 1 ; (MPT) missed packet error count +MDT DS.L 1 ; (MDT) max. deferral timer +RTC DS.L 1 ; (RTC) receive test control +TTC DS.L 1 ; (TTC) transmit test control +DTC DS.L 1 ; (DTC) DMA test control +CC0 DS.L 1 ; (CC0) CAM comparison 0 +CC1 DS.L 1 ; (CC1) CAM comparison 1 +CC2 DS.L 1 ; (CC2) CAM comparison 2 +CM DS.L 1 ; (CM) CAM match +res1 DS.L 2 ; reserved by National Semiconductor +RBC DS.L 1 ; (RBC) receiver byte count +res2 DS.L 1 ; reserved by National Semiconductor +TBO DS.L 1 ; (TBO) transmit backoff counter +TRC DS.L 1 ; (TRC) transmit random counter +TBM DS.L 1 ; (TBM) transmit backoff mask +res3 DS.L 1 ; reserved by National Semiconductor +Data_Config2 DS.L 1 ; extended data configiguration + ELSE +Command DS.W 1 ; (CR) SONIC control + CtlRegPad +Data_Config DS.W 1 ; (DCR) packet configuration + CtlRegPad +Recv_Control DS.W 1 ; (RCR) pkt reception control + CtlRegPad +Trans_Control DS.W 1 ; (TCR) Transmission control + CtlRegPad +Int_Mask DS.W 1 ; (IMR) interrupt mask + CtlRegPad +Int_Status DS.W 1 ; (ISR) interrupts status bits + CtlRegPad +Upper_TDA DS.W 1 ; (UTDA) upper 16 bits of TDA address + CtlRegPad +Current_TDA DS.W 1 ; (CTDA) 16 bit ptr to current TDA + CtlRegPad +Trans_PktSize DS.W 1 ; (TPS) total size of outbound pkt + CtlRegPad +Trans_FragCount DS.W 1 ; (TFC) transmit fragment count + CtlRegPad +Trans_PktStart0 DS.W 1 ; (TSA0) lower 16 bit of pkt addr + CtlRegPad +Trans_PktStart1 DS.W 1 ; (TSA1) upper " + CtlRegPad +Trans_FragSize DS.W 1 ; (TFS) current fragment size + CtlRegPad +Upper_RDA DS.W 1 ; (URDA) upper 16 bits of RDA address + CtlRegPad +Current_RDA DS.W 1 ; (CRDA) 16 bit ptr to current RDA + CtlRegPad +Recv_RBA0 DS.W 1 ; (CRBA0) lower 16 bit receive addr in RBA + CtlRegPad +Recv_RBA1 DS.W 1 ; (CRBA1) upper 16 bit recive addr in RBA + CtlRegPad +Buff_Cnt0 DS.W 1 ; (RBWC0) lower 16 bit of word count in RBA + CtlRegPad +Buff_Cnt1 DS.W 1 ; (RBWC1) upper " + CtlRegPad +End_Buff DS.W 1 ; (EOBC) end of buffer word count + CtlRegPad +Upper_RRA DS.W 1 ; (URRA) upper 16 bits of RRA address + CtlRegPad +RRA_Start DS.W 1 ; (RSA) 16 bit ptr to RRA + CtlRegPad +RRA_End DS.W 1 ; (REA) 16 bit ptr to end of RRA + CtlRegPad +RRA_Read DS.W 1 ; (RRP) where SONIC gets next read resource + CtlRegPad +RRA_Write DS.W 1 ; (RWP) where host puts new read resources + CtlRegPad +TRBA0 DS.W 1 ; (TRBA0) used by SONIC + CtlRegPad +TRBA1 DS.W 1 ; (TRBA1) " + CtlRegPad +TBWC0 DS.W 1 ; (TBWC0) " + CtlRegPad +TBWC1 DS.W 1 ; (TBWC1) " + CtlRegPad +ADDR0 DS.W 1 ; (ADDR0) " + CtlRegPad +ADDR1 DS.W 1 ; (ADDR1) " + CtlRegPad +LLFA DS.W 1 ; (LLFA) " + CtlRegPad +TTDA DS.W 1 ; (TTDA) " + CtlRegPad +CAM_EntryPtr DS.W 1 ; (CEP) points to CAM cell + CtlRegPad +CAM_Port2 DS.W 1 ; (CAP2) selects upper 16 bits of CAM cell + CtlRegPad +CAM_Port1 DS.W 1 ; (CAP1) selects middle 16 bits of CAM cell + CtlRegPad +CAM_Port0 DS.W 1 ; (CAP0) selects lower 16 bits of CAM cell + CtlRegPad +CAM_Enable DS.W 1 ; (CE) CAM enable register turns cells on/off + CtlRegPad +CAM_DescPtr DS.W 1 ; (CDP) 16 bit ptr to current CAM descriptor + CtlRegPad +CAM_Count DS.W 1 ; (CDC) count of CAM descriptors + CtlRegPad +Silicon_Rev DS.W 1 ; (SR) rev info on SONIC chip + CtlRegPad +Timer0 DS.W 1 ; (WT0) lower 16 bits of SONCIC timer + CtlRegPad +Timer1 DS.W 1 ; (WT1) upper 16 " + CtlRegPad +Recv_SeqCnt DS.W 1 ; (RSC) receive sequence counter + CtlRegPad +CRC_Err DS.W 1 ; (CRCT) CRC error count + CtlRegPad +FAE_Err DS.W 1 ; (FAET) frame alignment error count + CtlRegPad +MissedPkt_Err DS.W 1 ; (MPT) missed packet error count + CtlRegPad +MDT DS.W 1 ; (MDT) max. deferral timer + CtlRegPad +RTC DS.W 1 ; (RTC) receive test control + CtlRegPad +TTC DS.W 1 ; (TTC) transmit test control + CtlRegPad +DTC DS.W 1 ; (DTC) DMA test control + CtlRegPad +CC0 DS.W 1 ; (CC0) CAM comparison 0 + CtlRegPad +CC1 DS.W 1 ; (CC1) CAM comparison 1 + CtlRegPad +CC2 DS.W 1 ; (CC2) CAM comparison 2 + CtlRegPad +CM DS.W 1 ; (CM) CAM match + CtlRegPad +res1 DS.W 2 ; reserved by National Semiconductor + CtlRegPad +RBC DS.W 1 ; (RBC) receiver byte count + CtlRegPad +res2 DS.W 1 ; reserved by National Semiconductor + CtlRegPad +TBO DS.W 1 ; (TBO) transmit backoff counter + CtlRegPad +TRC DS.W 1 ; (TRC) transmit random counter + CtlRegPad +TBM DS.W 1 ; (TBM) transmit backoff mask + CtlRegPad +res3 DS.W 1 ; reserved by National Semiconductor + CtlRegPad +Data_Config2 DS.W 1 ; extended data configiguration + ENDIF + ENDR + +;•••••••••••••••• Content Addressable Memory (CAM) Descriptor Area CDA +CAMDesc RECORD 0 + IF SONIC32 THEN +Entry_ptr DS.L 1 ; base zero index to CAM cell +Port2 DS.L 1 ; lower 16 bits in cell +Port1 DS.L 1 ; middle 16 bits in cell +Port0 DS.L 1 ; upper 16 bits in cell +enable DS.L 1 ; CAM cell enable mask + ELSE +Entry_ptr DS.W 1 ; base zero index to CAM cell +Port2 DS.W 1 ; lower 16 bits in cell +Port1 DS.W 1 ; middle 16 bits in cell +Port0 DS.W 1 ; upper 16 bits in cell +enable DS.W 1 ; CAM cell enable mask + ENDIF +CAMDescSz EQU * + ENDR + +;•••••••••••••••• Receive Resource Descriptor Area RRA +RRArec RECORD 0 + IF SONIC32 THEN +buff_ptr0 DS.L 1 ; lower 16 bits of RBA address +buff_ptr1 DS.L 1 ; upper 16 bits of RBA address +buff_wc0 DS.L 1 ; lower 16 bits of RBA word count +buff_wc1 DS.L 1 ; upper 16 bits of RBA word count + ELSE +buff_ptr0 DS.W 1 ; lower 16 bits of RBA address +buff_ptr1 DS.W 1 ; upper 16 bits of RBA address +buff_wc0 DS.W 1 ; lower 16 bits of RBA word count +buff_wc1 DS.W 1 ; upper 16 bits of RBA word count + ENDIF +RRArecSz EQU * + ENDR + +;•••••••••••••••• Receive Descriptor Area RDA +Rxpkt RECORD 0 +; this link is used to keep rx descriptors on our own list(s) when SONIC is not using them +nextRD DS.L 1 ; internal ptr to next descriptor +isFree DS.B 1 ; = true if desc has been freed + ORG nextRD + IF SONIC32 THEN +status DS.L 1 ; receive status +byte_count DS.L 1 ; size of packet read +pkt_ptr0 DS.L 1 ; lower 16 bits of packet addr. in RBA +pkt_ptr1 DS.L 1 ; upper 16 bits of packet addr. in RBA +seq_no DS.L 1 ; sequence number +link DS.L 1 ; link to other RD +in_use DS.L 1 ; use flag + ELSE +status DS.W 1 ; receive status +byte_count DS.W 1 ; size of packet read +pkt_ptr0 DS.W 1 ; lower 16 bits of packet addr. in RBA +pkt_ptr1 DS.W 1 ; upper 16 bits of packet addr. in RBA +seq_no DS.W 1 ; sequence number +link DS.W 1 ; link to other RD +in_use DS.W 1 ; use flag + ENDIF +RxRDAsize EQU * + ENDR + +;•••••••••••••••• Transmit Descriptor Area TDA +Max_Tx_Frags EQU 16 ; maximum fragments supported for a transmit + +Txpkt RECORD 0 ; Transmit Descriptor +; this link is used to keep tx descriptors on our own list when SONIC is not using them +nextTD DS.L 1 ; internal ptr to next descriptor + ORG nextTD + IF SONIC32 THEN +status DS.L 1 ; status info written by SONIC +config DS.L 1 ; pre-transmit config data +pkt_size DS.L 1 ; size of packet +frag_count DS.L 1 ; fragment count +frag_start EQU * ; start of individual fragments +; the following 3 fields are repeated 1..frag_count +frag_ptr0 DS.L 1 ; lower 16 bits of address +frag_ptr1 DS.L 1 ; upper " +frag_size DS.L 1 ; fragment size +frag_esize EQU * - frag_start ; size of individual fragments + ORG * + (Max_Tx_Frags-1) * frag_esize + ; allocate rest of fragments +link DS.L 1 ; lower 16 bits of next TD (if any) + ELSE +status DS.W 1 ; status info written by SONIC +config DS.W 1 ; pre-transmit config data +pkt_size DS.W 1 ; size of packet +frag_count DS.W 1 ; fragment count +frag_start EQU * ; start of individual fragments +; the following 3 fields are repeated 1..frag_count +frag_ptr0 DS.W 1 ; lower 16 bits of address +frag_ptr1 DS.W 1 ; upper " +frag_size DS.W 1 ; fragment size +frag_esize EQU * - frag_start ; size of individual fragments + ORG * + (Max_Tx_Frags-1) * frag_esize + ; allocate rest of fragments +link DS.W 1 ; lower 16 bits of next TD (if any) + ENDIF +TxTDAsize EQU * ; size of a single frame TD + ENDR + +;•••••••••••••••• Initialization Parameters +SONICinitParms RECORD 0 +SONICbase DS.L 1 ; base address of SONIC registers +IntInstall DS.L 1 ; addr of proc that installs interrupt handler +RECVRtn DS.L 1 ; address of receive routine +RECVPrms DS.L 1 ; parms to pass @ receive +TRANRtn DS.L 1 ; address of xmit complete routine +TRANPrms DS.L 1 ; parms to pass @ xmit complete +MemStart DS.L 1 ; address of memory usage area +MemSize DS.L 1 ; size of memory usage area +NumRxBuffs DS.L 1 ; proposed # of receive buffers +IntDisable DS.L 1 ; proc to disable interrupts +IntEnable DS.L 1 ; proc to reenable interrupts +NetStatArray DS.L 1 ; ptr to network statistics array +DataConfig DS.L 1 ; data configuration value +TransAddr DS.L 1 ; ->proc to translate logical->physical address +ParmSize EQU * + ENDR +;•••••••••••••••• CAM Parameters +CAMparms RECORD 0 +SONICPtr DS.L 1 ; SONIC base address +EAddr DS.B 6 ; Ethernet address +LoadorClear DS.L 1 ; ≠ 0 if adding CAM entry +ParmSize EQU * + ENDR +;•••••••••••••••• (CR) Command Register Bits +LoadCAM EQU 9 ; load content addressable memory +ReadRRA EQU 8 ; read next read resource descriptor +SoftReset EQU 7 ; do a software reset +StartTimer EQU 5 ; start watchdog timer +StopTimer EQU 4 ; stop " +RxEnable EQU 3 ; receive packets +RxDisable EQU 2 ; stop receiving packets +TxEnable EQU 1 ; transmit packets +TxDisable EQU 0 ; stop transmitting packets + +;•••••••••••••••• (RCR) Receive Control/Status Register Bits +RecvErrors EQU 15 ; accept/reject packets with errors +RecvRunts EQU 14 ; accept/reject runt packets +RecvBroadCast EQU 13 ; accept/reject broadcasts +RecvAll EQU 12 ; turn on/off promiscuious mode +RecvMultiCast EQU 11 ; accept/reject multicasts +NoLoopBack EQU $0000 ; mask for no loopback +MACLoopBack EQU $0200 ; mask for MAC loopback +ENDECLoopBack EQU $0400 ; mask for ENDEC loopback +TxRxLoopBack EQU $0600 ; mask for Transceiver loopback +MultiRecd EQU 8 ; set when multicast is received +BroadRecd EQU 7 ; set when broadcast is received +RBAEmpty EQU 6 ; set when out of buffers in RBA +CarrierSense EQU 5 ; set when net busy and CRS is active +CollisionSense EQU 4 ; set when collision occurs if COL active +CRCErr EQU 3 ; set if packet has CRC error +FramAlignErr EQU 2 ; set if frame not aligned +LoopBackRecd EQU 1 ; set when loopback is received +ReceivedOK EQU 0 ; set upon successful packet reception + +;•••••••••••••••• (TCR) Transmit Control/Status Register Bits +TxProgInt EQU 15 ; generate a software interrupt +OWCTimer EQU 14 ; "out of window collision" timer control +CRCInhibit EQU 13 ; turn on/off FCS field +ExDeferTimer EQU 12 ; turn on/off excessive defer timer +ExcessDefer EQU 10 ; excessive deferrals detected +DeferredTx EQU 9 ; set when packet is being deferred +NoCRS EQU 8 ; CRS not present during transmission +CRSLost EQU 7 ; bad CRS during transmission +ExcessColl EQU 6 ; > 16 collisions detected +OutWindow EQU 5 ; "out of window" collision detected +PktMonitorBad EQU 3 ; packet monitored as bad +FIFOUnderRun EQU 2 ; Tx FIFO underrun +BCMismatch EQU 1 ; TxPkt_size ≠ sum(TxFrag_size) +TransmitOK EQU 0 ; packet transmitted successfuly + +;•••••••••••••••• (DCR) Data Configuration Register Bits +EXBUS EQU 15 ; extended bus mode +LatchBusRetry EQU 13 ; LBR +DConfig_Usr1 EQU 12 ; sets/resets pin USR1 +DConfig_Usr0 EQU 11 ; sets/resets pin USR0 +SynchTerm EQU 10 ; select sync/async input to DMA +WaitCtl0 EQU $0000 ; 0 bus cycles added to DMA +WaitCtl1 EQU $0040 ; 1 bus cycle added to DMA +WaitCtl2 EQU $0080 ; 2 bus cycles added to DMA +WaitCtl3 EQU $00C0 ; 3 bus cycles added to DMA +DataWidth EQU 5 ; 16/32 bit path width for DMA +BlockMode EQU 4 ; DMA block mode selection +RFT2 EQU $0000 ; 2 word recv FIFO threshold +RFT4 EQU $0004 ; 4 word recv FIFO threshold +RFT8 EQU $0008 ; 8 word recv FIFO threshold +RFT12 EQU $000C ; 12 word recv FIFO threshold +TFT4 EQU $0000 ; 4 word trans FIFO threshold +TFT8 EQU $0001 ; 8 word trans FIFO threshold +TFT12 EQU $0002 ; 12 word trans FIFO threshold +TFT14 EQU $0003 ; 14 word trans FIFO threshold + +;•••••••••••••••• (DCR2) Extended Data Configuration Register Bits +EXUSR3 EQU 15 ; extended user bits +EXUSR2 EQU 14 +EXUSR1 EQU 13 +EXUSR0 EQU 12 + +;•••••••••••••••• (ISR) Interrupt Status Register Bits +BusRetry EQU 14 ; set when bus needed retry +LostHeartBeat EQU 13 ; set when heartbeat is lost +DoneLoadCAM EQU 12 ; set when load CAM operation is done +GetProgInt EQU 11 ; set when programmable int. occurs +RecdPkt EQU 10 ; set when a packet has been recd. +TransDone EQU 9 ; set when trans is finished +TransError EQU 8 ; set when trans finished with an error +TimerElapsed EQU 7 ; set when timer reaches zero +EmptyRDA EQU 6 ; set when receive descriptors exhausted +EmptyRRA EQU 5 ; set when receive resources exhausted +RBAOverFLow EQU 4 ; set when buffer area is full +CRCRollover EQU 3 ; set when CRC tally has reached $FFFF +FAERollover EQU 2 ; set when FAE tally has reached $FFFF +MPRollover EQU 1 ; set when MP tally has reached $FFFF +RxFIFORollover EQU 0 ; set when Rx FIFO overflows + +OurIntsMask EQU (1 << BusRetry) + \ + (1 << RecdPkt) + \ + (1 << TransDone) + \ + (1 << TimerElapsed) + \ + (1 << RxFIFORollover) + \ + (1 << RBAOverFlow) + \ + (1 << EmptyRRA) + +;•••••••••••••••• Network Statistics +NetStats RECORD 0 ; network management stats. +TxOK DS.L 1 ; frames transmitted OK +sCollFrame DS.L 1 ; single collision frames +mCollFrame DS.L 1 ; multiple collision frames +CollFrame DS.L 1 ; collision frames +DefTx DS.L 1 ; deferred transmissions +LateColl DS.L 1 ; late collisions +ExcessColl DS.L 1 ; excessive collisions +ExcessDef DS.L 1 ; excessive defferals +InMACTxErr DS.L 1 ; internal MAC transmit errors +RxOK DS.L 1 ; frames received OK +MultiRxOK DS.L 1 ; multicast frames recd OK +BroadRxOK DS.L 1 ; broadcast frames recd OK +FCSerr DS.L 1 ; frame check sequence errors +FAerr DS.L 1 ; frame alignment errors +MPerr DS.L 1 ; missed packet errors +Size EQU * + ENDR + +;•••••••••••••••• General Equates +TalliesPerSec EQU 5000000 ; number of timer ticks/second +TxMaxRetries EQU 4 ; max attempts to retry aborted xmits +Max_Tx_Packets EQU 16 ; maximum # of chained Tx packets +Min_Pkt_Size EQU 60 ; minimum packet size +Min_Rx_Buffs EQU 2 ; minimum # of recv descriptors/buffers +Max_Pkt_Size EQU 1518 ; maximum packet size (inc. CRC) +EOL_Bit EQU 0 ; end-of-link bit +Ctl_Mem_Size EQU Txpkt.TxTDAsize*Max_Tx_Packets+ \; up to Max_Tx_Packets chained transmits + RRArec.RRArecSz+ \; 1 RRA descriptor + CAMDesc.CAMDescSz ; 1 CAM descriptor +Min_Mem_Size EQU Ctl_Mem_Size+ \ + Max_Pkt_Size*Min_Rx_Buffs+ \; max. size packets + Rxpkt.RxRDAsize*Min_Rx_Buffs; recv. descriptors diff --git a/DeclData/DeclNet/Sonic/SonicEqu.a.idump b/DeclData/DeclNet/Sonic/SonicEqu.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Sonic/SonicEqu.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Sonic/SonicEqu.a.rdump b/DeclData/DeclNet/Sonic/SonicEqu.a.rdump new file mode 100644 index 0000000..ea6528d --- /dev/null +++ b/DeclData/DeclNet/Sonic/SonicEqu.a.rdump @@ -0,0 +1,26 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0072 6F67 496E 7409" /* ..Monaco.rogInt. */ + $"0945 5155 0909 0931 3509 0909 0909 0909" /* .EQU...15....... */ + $"3B20 0006 0004 003C 0024 0363 023D 003C" /* ; .....<.$.c.=.< */ + $"0024 0363 023D A678 8BDC 0000 0000 0000" /* .$.c.=.x........ */ + $"0000 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"003C 0024 0363 023D 003C 0024 0363 023D" /* .<.$.c.=.<.$.c.= */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"EE56 7A55 3FE5 3230 0004 0000 0000 0000" /* .VzU?.20........ */ + $"0000 A933 73AB A933 73AB A6F7 B0F2 0078" /* ...3s..3s......x */ + $"C6B2 0000 0004 0001 2653 7570 6572 4D61" /* ........&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA53 6F6E 6963 BA00" /* .DeclNet.Sonic.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0131 000A 536F 6E69 6345 7175 2E61 0000" /* .1..SonicEqu.a.. */ + $"0000 1F4E 6577 206C 6F63 6174 696F 6E20" /* ...New location */ + $"666F 7220 524F 4D4C 696E 6B20 746F 6F6C" /* for ROMLink tool */ + $"2E0D 00" /* ... */ +}; + diff --git a/DeclData/DeclNet/Sonic/VersionEclipse.a b/DeclData/DeclNet/Sonic/VersionEclipse.a new file mode 100644 index 0000000..f3cefaa --- /dev/null +++ b/DeclData/DeclNet/Sonic/VersionEclipse.a @@ -0,0 +1,38 @@ +; +; File: VersionEclipse.a +; +; Contains: Version information for Eclipse +; +; Written by: Mike Quinn +; +; Copyright: © 1991-1992 by Apple Computer, Inc., all rights reserved. +; +; This file is used in these builds: Mac32 +; +; Change History (most recent first): +; +; 2/2/92 CSS Rollin Horror stuff: +;
10/17/92 BG Changed version to final release version. +; <1> 10/6/92 GDW New location for ROMLink tool. +; 6/22/92 mal Updated to 1.0.4d3. +; <1> 6/12/92 RLM first checked in +; 5/13/92 KW (JC,H4) Change driver to support configuration information +; obtained from ecfg resource rather than from using boxflag +; driven tables. +; 02/07/92 jmp (jmp,H3/BG,6) Updated version numbers for Zydeco. +; <1> 2/4/92 mal first checked in +; ——————————————————————————————————————————————————————————————————————————————————————— +; Pre-Pandora ROM comments begin here. +; ——————————————————————————————————————————————————————————————————————————————————————— +; <5> 10/22/91 BG/SAM Changed release version number. +; <4> 5/22/91 BG Updated version to reflect ROM beta. +; <3> 4/21/91 CCH Rolled in Sean Findley's changes. +; <2> 3/14/91 BG (actually sf) Updated driver version information. +; <1> 2/11/91 mjq first checked in +; + + PRINT PUSH, GEN, NOMDIR + + VERSION 'Quadra Ethernet Driver', 1, 0, 4, final, 1, '1990-1992', '', SonicEnet + + PRINT POP diff --git a/DeclData/DeclNet/Sonic/VersionEclipse.a.idump b/DeclData/DeclNet/Sonic/VersionEclipse.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclNet/Sonic/VersionEclipse.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclNet/Sonic/VersionEclipse.a.rdump b/DeclData/DeclNet/Sonic/VersionEclipse.a.rdump new file mode 100644 index 0000000..f1ac3c0 --- /dev/null +++ b/DeclData/DeclNet/Sonic/VersionEclipse.a.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0054 4571 752E 6100" /* ..Monaco.TEqu.a. */ + $"0000 0000 003E 0001 0000 4574 6865 724E" /* .....>....EtherN */ + $"6574 0006 0004 0029 0007 0230 02D4 0029" /* et.....)...0...) */ + $"0007 0230 02D4 A796 9FFB 0000 0109 0000" /* ...0............ */ + $"017D 0000 0000 0100" /* .}...... */ +}; + +data 'MPSR' (1008) { + $"0029 0007 0230 02D4 0029 0007 0230 02D4" /* .)...0...)...0.. */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"38F6 9052 3FE5 3230 0004 0000 0000 0000" /* 8..R?.20........ */ + $"0000 A933 73AB A933 73AB A6F7 B0F2 0078" /* ...3s..3s......x */ + $"C6B2 0000 0005 0002 2653 7570 6572 4D61" /* ........&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C4E 6574 BA53 6F6E 6963 BA00" /* .DeclNet.Sonic.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0132 0010 5665 7273 696F 6E45 636C 6970" /* .2..VersionEclip */ + $"7365 2E61 0000 0000 1355 7064 6174 6520" /* se.a.....Update */ + $"6672 6F6D 2048 6F72 726F 722E 00" /* from Horror.. */ +}; + diff --git a/DeclData/DeclVideo/ATI/ATIDeclGamma.r b/DeclData/DeclVideo/ATI/ATIDeclGamma.r new file mode 100644 index 0000000..cabb598 --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDeclGamma.r @@ -0,0 +1,247 @@ +/* + File: ATIDeclGamma.r + + Contains: xxx put contents here xxx + + Written by: xxx put writers here xxx + + Copyright: © 1993 by Apple Computer, Inc., all rights reserved. + + Change History (most recent first): + + <1> 11/5/93 fau first checked in + <1> 10/27/93 fau first checked in + <1> 10/19/93 fau first checked in + +*/ + +//-------------------------------------------------------------------------- +//start +// +//Name: ATIDeclGamma.r +//Creator: George D. Wilson Jr. +//Date: 5/19/92 +// +//Purpose: Gamma table declarations +// +//Category: Gamma Tables +//File: ATIDeclGamma.r +// +//Detailed: This file contains gamma table definitions for standard +// Apple monitors. +// +//Note: +// +//History: +// +// Date Programmer Modification +// -------- ---------- ----------------------------------------- +// +//stop +//------------------------------------------------------------------------*/ + +#include "ROMLink.r" +#include "Types.r" + +//===================================================================== +// Gamma resource tables +//===================================================================== +#define ColorGammaID 2000 +#define HiResGammaID 2001 +#define GrayGammaID 2002 +#define RubikGammaID 2003 + + +resource 'gdir' (700, "_GammaDirHiRes") {{ + 128, l{"HiResGamma"}; +}}; + + +resource 'gdir' (710, "_GammaDir_16") {{ + 128, l{"HiResGamma"}; + 129, l{"ColorGamma"}; +}}; + + + +resource 'node' (720, "ColorGamma") {{ + blocksize{}; + + word {ColorGammaID}; // gamma res ID + cstring{"Page-White Gamma"}; + align {2}; + + word {$0000}; // gVersion + word {$0000}; // gType + word {$0000}; // gFormulaSize + word {$0003}; // gChanCnt + word {$0100}; // gDataCnt + word {$0008}; // gChanWidth + + longs{{ + $00030609;$0C101012;$13151616;$181B1C1E; // red channel + $1F222326;$282B2C2F;$3234373A;$3C3F4041; + $42434445;$46474749;$4A4B4C4D;$4E4F5051; + $52535454;$56565758;$595A5B5C;$5D5E5F60; + $61626364;$65666768;$696A6B6C;$6D6E6F70; + $71727273;$74757677;$78797A7A;$7B7C7D7E; + $7F818283;$83848586;$8788898A;$8A8B8C8D; + $8E8F9091;$92939394;$95969798;$98999A9B; + $9C9D9E9F;$A0A1A1A2;$A3A4A4A5;$A6A7A8A8; + $A9AAABAC;$ADADAEAF;$B0B1B2B2;$B3B4B5B5; + $B6B7B8B8;$B9BABBBC;$BCBDBEBF;$C0C0C1C2; + $C3C3C4C5;$C6C6C7C8;$C9C9CACB;$CCCDCDCE; + $CFD0D1D1;$D2D3D4D4;$D5D6D7D7;$D8D9DADA; + $DBDCDDDE;$DEDFE0E1;$E1E2E3E4;$E4E5E6E7; + $E7E8E9EA;$EAEBECED;$EEEEEFF0;$F1F1F2F3; + $F4F4F5F6;$F7F8F8F9;$FAFBFBFC;$FDFEFFFF; + }}; + + longs{{ + $00030609;$0C101018;$20202223;$24252728; // green channel + $292C2D2E;$30323437;$383A3D3F;$40414242; + $43444445;$46474849;$4A4A4B4C;$4D4E4F50; + $51525354;$55565758;$595B5C5D;$5E5F6061; + $62636465;$65666768;$696A6B6C;$6D6E6F70; + $71717273;$74747576;$77787979;$7A7B7C7D; + $7E7F8081;$82838484;$85868788;$88898A8B; + $8C8D8E8E;$8F909192;$93939495;$96969798; + $999A9A9B;$9C9D9E9E;$9FA0A1A2;$A2A3A4A5; + $A5A6A7A8;$A8A9AAAB;$ABACADAE;$AFAFB0B1; + $B2B2B3B4;$B5B5B6B7;$B7B8B9BA;$BABBBCBD; + $BDBEBFC0;$C1C1C2C3;$C3C4C5C6;$C6C7C8C9; + $C9CACBCC;$CCCDCECF;$CFD0D1D2;$D2D3D4D4; + $D5D6D6D7;$D8D9D9DA;$DBDCDCDD;$DEDEDFE0; + $E1E1E2E3;$E4E4E5E6;$E6E7E8E9;$E9EAEBEC; + $ECEDEEEF;$EFF0F1F2;$F2F3F4F4;$F5F6F7F7; + }}; + + longs{{ + $00020508;$0A0D1010;$10202022;$23232425; // blue channel + $25272829;$2A2C2D2E;$2F303233;$34363738; + $3A3C3D3F;$40414142;$42434444;$45454647; + $4748494A;$4A4B4C4D;$4D4E4F4F;$51515253; + $54555656;$5758595A;$5B5C5D5E;$5F606061; + $62626364;$64656666;$67686969;$6A6B6C6C; + $6D6E6F6F;$70717272;$73747475;$76777778; + $79797A7B;$7C7C7D7E;$7F808182;$82838484; + $85868687;$8888898A;$8A8B8C8D;$8D8E8F90; + $90919192;$93939495;$95969797;$9899999A; + $9B9B9C9D;$9D9E9FA0;$A0A1A1A2;$A3A3A4A4; + $A5A6A6A7;$A7A8A9A9;$AAABABAC;$ADADAEAF; + $AFB0B0B1;$B2B2B3B3;$B4B5B5B6;$B6B7B8B8; + $B9BABABB;$BBBCBDBD;$BEBFBFC0;$C0C1C2C2; + $C3C3C4C5;$C5C6C6C7;$C8C8C9C9;$CACBCBCC; + $CCCDCECE;$CFD0D0D1;$D1D2D3D3;$D4D4D5D6; + }}; +}}; + + +resource 'node' (730, "HiResGamma") {{ + blocksize{}; + + word {HiResGammaID}; // gamma res ID + cstring{"Mac Std Gamma"}; + align {2}; + + word{$0000}; // gVersion + word{$0000}; // gType + word{$0000}; // gFormulaSize + word{$0001}; // gChanCnt + word{$0100}; // gDataCnt + word{$0008}; // gChanWidth + + longs{{ + $0005090B;$0E101315;$17191B1D;$1E202224; + $2527282A;$2C2D2F30;$31333436;$37383A3B; + $3C3E3F40;$42434445;$4748494A;$4B4D4E4F; + $50515254;$55565758;$595A5B5C;$5E5F6061; + $62636465;$66676869;$6A6B6C6D;$6E6F7071; + $72737475;$76777879;$7A7B7C7D;$7E7F8081; + $81828384;$85868788;$898A8B8C;$8C8D8E8F; + $90919293;$94959596;$9798999A;$9B9B9C9D; + $9E9FA0A1;$A1A2A3A4;$A5A6A6A7;$A8A9AAAB; + $ABACADAE;$AFB0B0B1;$B2B3B4B4;$B5B6B7B8; + $B8B9BABB;$BCBCBDBE;$BFC0C0C1;$C2C3C3C4; + $C5C6C7C7;$C8C9CACA;$CBCCCDCD;$CECFD0D0; + $D1D2D3D3;$D4D5D6D6;$D7D8D9D9;$DADBDCDC; + $DDDEDFDF;$E0E1E1E2;$E3E4E4E5;$E6E7E7E8; + $E9E9EAEB;$ECECEDEE;$EEEFF0F1;$F1F2F3F3; + $F4F5F5F6;$F7F8F8F9;$FAFAFBFC;$FCFDFEFF; + }}; +}}; + + + + +resource 'node' (740, "GrayGamma") {{ + blocksize{}; + + word {GrayGammaID}; // gamma res ID + cstring{"Mac Gray Gamma"}; + align {2}; + + word{$0000}; // gVersion + word{$0000}; // gType + word{$0000}; // gFormulaSize + word{$0001}; // gChanCnt + word{$0100}; // gDataCnt + word{$0008}; // gChanWidth + + longs{{ + $000A141D;$23262B2E;$30323437;$393B3C3E; + $40414244;$4547484A;$4B4D4E4F;$50515254; + $55565758;$5A5B5C5D;$5E5F6061;$63646566; + $6768696A;$6B6C6D6E;$6F707171;$72737475; + $76777879;$7A7B7C7D;$7E7F8080;$81828384; + $84858687;$88898A8A;$8B8C8D8E;$8F909091; + $92929394;$95969797;$98999A9A;$9B9C9D9E; + $9E9FA0A1;$A1A2A3A3;$A4A5A6A7;$A7A8A9AA; + $AAABACAD;$ADAEAFAF;$B0B1B2B2;$B3B4B4B5; + $B6B6B7B7;$B8B9B9BA;$BBBCBCBD;$BEBEBFC0; + $C0C1C2C2;$C3C4C5C5;$C6C6C7C8;$C8C9CACB; + $CCCDCDCE;$CFCFD0D0;$D1D2D2D3;$D3D4D5D6; + $D6D7D7D8;$D9D9DADA;$DBDCDDDD;$DEDFDFE0; + $E0E1E2E3;$E3E4E5E5;$E6E6E7E7;$E8E8E9EA; + $EAEBEBEC;$EDEDEEEF;$F0F0F1F2;$F2F3F4F4; + $F5F5F6F7;$F7F8F9FA;$FAFBFCFC;$FDFEFEFF; + }}; +}}; + + + + +resource 'node' (750, "RubikGamma") {{ + blocksize{}; + + word {RubikGammaID}; // gamma res ID + cstring{"Mac RGB Gamma"}; + align {2}; + + word{$0000}; // gVersion + word{$0000}; // gType + word{$0000}; // gFormulaSize + word{$0001}; // gChanCnt + word{$0100}; // gDataCnt + word{$0008}; // gChanWidth + + longs{{ + $05070809;$0B0C0D0F;$10111214;$15161819; + $1A1C1D1E;$20212223;$24262829;$2A2C2D2F; + $30313334;$36373839;$3A3C3D3E;$40414243; + $44454648;$494B4C4D;$4E4F5051;$52535455; + $5758595A;$5B5C5D5E;$5F606163;$63656567; + $67696A6B;$6C6D6E6F;$70717273;$74757677; + $78797A7A;$7B7C7D7E;$7F818283;$83848586; + $8788898A;$8B8C8D8E;$8E909091;$92939394; + $95969798;$999A9B9C;$9D9E9FA0;$A0A1A2A3; + $A4A4A5A6;$A7A8A9AA;$AAACADAD;$AEAEB0B1; + $B2B3B3B4;$B5B6B7B8;$B9B9BABB;$BCBDBEBF; + $BFC0C1C2;$C2C3C4C5;$C6C7C8C9;$CACBCCCD; + $CDCECECF;$D0D1D2D3;$D3D4D5D6;$D6D7D8D8; + $D9DADBDC;$DDDEDEDF;$E0E1E1E2;$E3E4E4E5; + $E6E7E7E8;$E9EAEBEC;$EDEEEEEF;$EFF0F1F2; + $F3F3F4F5;$F6F7F8F8;$F9F9FAFB;$FCFDFEFF; + }}; +}}; + diff --git a/DeclData/DeclVideo/ATI/ATIDeclGamma.r.idump b/DeclData/DeclVideo/ATI/ATIDeclGamma.r.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDeclGamma.r.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclVideo/ATI/ATIDeclGamma.r.rdump b/DeclData/DeclVideo/ATI/ATIDeclGamma.r.rdump new file mode 100644 index 0000000..73b0b30 --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDeclGamma.r.rdump @@ -0,0 +1,25 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 002D 2D2D 2D2D 2D2D" /* ..Monaco.------- */ + $"2D2D 2D2D 2D2D 2D2D 2D2D 2D2D 0D2F 2F73" /* ------------.//s */ + $"7461 0006 0004 00B6 004B 025F 0379 00B6" /* ta.......K._.y.. */ + $"004B 025F 0379 A8B6 4AB0 0000 019B 0000" /* .K._.y..J....... */ + $"019B 0000 0000 0100" /* ........ */ +}; + +data 'MPSR' (1008) { + $"00B6 004B 025F 0379 00B6 004B 025F 0379" /* ...K._.y...K._.y */ + $"0000 0000 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"AFBD 2474 3FE5 3230 0004 0000 0000 0000" /* ..$t?.20........ */ + $"0000 A933 73B5 A933 73B5 A900 0533 005C" /* ...3s..3s....3.\ */ + $"1376 0000 0002 0001 2653 7570 6572 4D61" /* .v......&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C56 6964 656F BA41 5449 BA00" /* .DeclVideo.ATI.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0131 000E 4154 4944 6563 6C47 616D 6D61" /* .1..ATIDeclGamma */ + $"2E72 0000 0000 1066 6972 7374 2063 6865" /* .r.....first che */ + $"636B 6564 2069 6E00" /* cked in. */ +}; + diff --git a/DeclData/DeclVideo/ATI/ATIDeclMonitors.r b/DeclData/DeclVideo/ATI/ATIDeclMonitors.r new file mode 100644 index 0000000..66e425c --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDeclMonitors.r @@ -0,0 +1,168 @@ +/* + File: ATIDeclMonitors.r + + Contains: xxx put contents here xxx + + Written by: xxx put writers here xxx + + Copyright: © 1993 by Apple Computer, Inc., all rights reserved. + + Change History (most recent first): + + <1> 11/5/93 fau first checked in + <1> 10/27/93 fau first checked in + <1> 10/19/93 fau first checked in + +*/ + +//-------------------------------------------------------------------------- +//start +// +//Name: ATIDeclMonitors.r +//Creator: George D. Wilson Jr. +//Date: 9/19/92 +// +//Purpose: Defintions for ATI monitors declaration ROM +// +//Category: Gamma Tables +//File: ATIDeclMonitors.r +// +//Detailed: This file contains definitions for video modes for the ATI +// VRAM PCI card. +// +//Note: +// +//History: +// +// Date Programmer Modification +// -------- ---------- ----------------------------------------- +// +//stop +//------------------------------------------------------------------------*/ + +#include "ROMLink.r" +#include "Types.r" + +#include "InternalOnlyEqu.r" //skanky stuff +#include "ATIDefROM.r" + +//===================================================================== +// _VideoType +//===================================================================== +resource 'styp' (520, "_VideoType") { + catDisplay, //Video sResource : + typVideo, // + drSwApple, // + drHwATI // +}; + +//===================================================================== +// _VideoName +//===================================================================== +resource 'cstr' (530, "_VideoName") { + "Display_Video_Apple_ATI" +}; + +//===================================================================== +// Driver directory +//===================================================================== +resource 'ddir' (530, "_VidDrvrDir") {{ + sMacOS68020, l{"_sATIDrvrDir"}; //References the Macintosh-OS 68020 driver. +}}; + +resource 'node' (535, "_sATIDrvrDir") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataVideo.rsrc"}; + type{'decl'}; + id{112};}}}; +}}; + +//===================================================================== +// _sRsrc_VideoHR_ATI for Hi-Res monitor +//===================================================================== +resource 'srsc' (500, "_sRsrc_VideoHR_ATI") {{ + sRsrcType, l{"_VideoType"}; //References the sResource Type. + sRsrcName, l{"_VideoName"}; //References the sResource Name. + sRsrcDrvrDir, l{"_VidDrvrDir"}; //References the driver directory. + sRsrcFlags, d{6}; + sRsrcHWDevId, d{1}; //The hardware device Id. + + minorBaseOS, long{defMinorBase}; //References the Minor Base Offset. + minorLength, long{defMinorLength}; //References the Minor Base Length. + sGammaDir, a{"_GammaDir_HR"}; //References the Gamma resource for 13" + + oneBitMode, l{"_EightBitModeHR1024"}; //References the first mode parameters. +}}; + +//===================================================================== +// _sRsrc_VideoHR_Diamond for Hi-Res monitor for Diamond +//===================================================================== +resource 'srsc' (505, "_sRsrc_VideoHR_Diamond") {{ + sRsrcType, l{"_VideoType"}; //References the sResource Type. + sRsrcName, l{"_VideoName"}; //References the sResource Name. + sRsrcDrvrDir, l{"_VidDrvrDir"}; //References the driver directory. + sRsrcFlags, d{6}; + sRsrcHWDevId, d{1}; //The hardware device Id. + + minorBaseOS, long{defMinorBase}; //References the Minor Base Offset. + minorLength, long{defMinorLength}; //References the Minor Base Length. + sGammaDir, a{"_GammaDir_HR"}; //References the Gamma resource for 13" + + oneBitMode, l{"_EightBitModeHR640"}; //References the first mode parameters. +}}; + + +//===================================================================== +//===================================================================== +// Hi-Res vidParms records +//===================================================================== +//===================================================================== + +//===================================================================== +// Eight-Bit per pixel parameter list for Hi-Res +//===================================================================== + +resource 'vmod' (550, "_EightBitModeHR1024") {{ + mVidParams, l{"_EightVidParamsHR1024"}; //References the eight-bit mode parameter record. + mPageCnt, d{1}; //The page count. + mDevType, d{clutType}; //The device type. +}}; + +resource 'vdev' (550, "_EightVidParamsHR1024") { + eightmBaseOffset, + 1024, //RowBytes + {eightmBounds_THR,eightmBounds_LHR,eightmBounds_BHR,eightmBounds_RHR}, + eightVersion, //bmVersion + 0, //packType not used + 0, //packSize not used + eightmHRes, //bmHRes + eightmVRes, //bmVRes + eightPixelType, //bmPixelType + eightPixelSize, //bmPixelSize + eightCmpCount, //bmCmpCount + eightCmpSize, //bmCmpSize + eightmPlaneBytes //bmPlaneBytes +}; + +resource 'vmod' (555, "_EightBitModeHR640") {{ + mVidParams, l{"_EightVidParamsHR640"}; //References the eight-bit mode parameter record. + mPageCnt, d{1}; //The page count. + mDevType, d{clutType}; //The device type. +}}; + +resource 'vdev' (555, "_EightVidParamsHR640") { + eightmBaseOffset, + 640, //RowBytes + {eightmBounds_THR,eightmBounds_LHR,eightmBounds_BHR,eightmBounds_RHR}, + eightVersion, //bmVersion + 0, //packType not used + 0, //packSize not used + eightmHRes, //bmHRes + eightmVRes, //bmVRes + eightPixelType, //bmPixelType + eightPixelSize, //bmPixelSize + eightCmpCount, //bmCmpCount + eightCmpSize, //bmCmpSize + eightmPlaneBytes //bmPlaneBytes +}; + diff --git a/DeclData/DeclVideo/ATI/ATIDeclMonitors.r.idump b/DeclData/DeclVideo/ATI/ATIDeclMonitors.r.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDeclMonitors.r.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclVideo/ATI/ATIDeclMonitors.r.rdump b/DeclData/DeclVideo/ATI/ATIDeclMonitors.r.rdump new file mode 100644 index 0000000..ffffc57 --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDeclMonitors.r.rdump @@ -0,0 +1,26 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 002D 2D2D 2D2D 2D2D" /* ..Monaco.------- */ + $"2D2D 2D2D 2D2D 2D2D 2D2D 2D2D 0D2F 2F73" /* ------------.//s */ + $"7461 0006 0004 0034 0085 02DE 0334 0034" /* ta.....4.....4.4 */ + $"0085 02DE 0334 A961 74AB 0000 1647 0000" /* .....4.at....G.. */ + $"1647 0000 0E84 0100" /* .G...... */ +}; + +data 'MPSR' (1008) { + $"0034 0085 02DE 0334 0034 0085 02DE 0334" /* .4.....4.4.....4 */ + $"0000 0E84 0000 0000 0000 0000 0000" /* .............. */ +}; + +data 'ckid' (128, "Projector") { + $"8EA8 853C 3FE5 3230 0004 0000 0000 0000" /* ... 11/5/93 fau first checked in + <1> 10/27/93 fau first checked in + <1> 10/19/93 fau first checked in + +*/ + +//-------------------------------------------------------------------------- +//start +// +//Name: ATIVideoROM.r +//Creator: George D. Wilson Jr. +//Date: 9/19/92 +// +//Purpose: Declaration ROM for ATI system +// +//Category: DeclROM +//File: ATIVideoROM.r +// +//Detailed: This file defines the declaration information for the ATI +// mother board. Currently this system defines only the video display +// portion of the system. +// +//Note: +// +//History: +// +// Date Programmer Modification +// -------- ---------- ----------------------------------------- +// 10/13/93 George W. Cleaned up some not used resources. +// +//stop +//------------------------------------------------------------------------*/ + +#include "ROMLink.r" +#include "Types.r" + +#include "InternalOnlyEqu.r" //skanky stuff +#include "DepVideoEqu.r" +#include "ATIDefROM.r" //Video driver equates + +// +//===================================================================== +// BEGIN Declaration ROM +//===================================================================== + + +//************************************************************* +//Constants +//************************************************************* + +#define TheBoardId $0575 //the Board Id (Special ATI Mother board) + +//----------- sResource Directory // +#define sRsrc_Board 1 //Board sResource {May be any number in [0..127]} +#define sRsrc_Video 128 //Video sResource {May be any number in [128..254]} + +//===================================================================== +// Directory +//===================================================================== + +resource 'sdir' (270, "_sRsrcATIDir") {{ + sRsrc_Board, l{"_sRsrc_BdATI"}; //References the board sResource. + sRsrc_VideoHR_ATI, a{"_sRsrc_VideoHR_ATI"}; //References the video sResource Hi-Res + sRsrc_VideoHR_Diamond, a{"_sRsrc_VideoHR_Diamond"}; //References the video sResource Hi-Res +}}; + +//============================================================= +// sRsrc_Board List - the Board sResource +//============================================================= + +resource 'boar' (280, "_sRsrc_BdATI") {{ + sRsrcType, l{"_BoardType"}; //References the sResource type + sRsrcName, c{"PCI Video"}; //Official product name + sRsrcIcon, a{"_VidICONCyclone"}; //A new icon + boardId, d{TheBoardId}; //The board Id. + primaryInit, l{"_sPInitRec"}; //References the Primary init record. + vendorInfo, l{"_VendorInfo"}; //References the OPTIONAL Vendor information list. +}}; + +//============================================================= +// _BoardType - Board type and category +//============================================================= +resource 'styp' (290, "_BoardType") { + catBoard, // CatBoard ALWAYS = $0001 for bd srsrc + typBoard, // TypBoard ALWAYS = $0000 for bd srsrc + 0, // CatBoard ALWAYS = $0000 for bd srsrc + 0 // CatBoard ALWAYS = $0000 for bd srsrc +}; + +//===================================================================== +// Primary Init Record +//===================================================================== + +resource 'node' (418, "_sPInitRec") {{ + blocksize{}; + include{match{{file{$$Shell("RsrcDir")"DeclDataVideo.rsrc"}; + type{'decl'}; + id{110};}}}; +}}; + +//===================================================================== +// Vendor Info record +//===================================================================== + +resource 'vend' (420, "_VendorInfo") {{ + vendorId, c{"Apple Computer, Inc."}; + revLevel, c{"1.0D1x02"}; + partNum, c{"0010"}; +}}; + +//===================================================================== +// Format/Header Block +//===================================================================== + +resource 'form' (128, "Root") { + l{"_sRsrcDir"}, + 1, // Should put "romRevision = 1" in ROMLink.r + appleFormat, + 0, + $0F +}; + diff --git a/DeclData/DeclVideo/ATI/ATIDeclVideo.r.idump b/DeclData/DeclVideo/ATI/ATIDeclVideo.r.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDeclVideo.r.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclVideo/ATI/ATIDeclVideo.r.rdump b/DeclData/DeclVideo/ATI/ATIDeclVideo.r.rdump new file mode 100644 index 0000000..6bc75a3 --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDeclVideo.r.rdump @@ -0,0 +1,26 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 003D 3D3D 3D3D 3D3D" /* ..Monaco.======= */ + $"3D3D 3D3D 3D3D 3D3D 3D3D 3D3D 3D3D 3D3D" /* ================ */ + $"3D3D 0006 0004 0041 0125 033E 036C 0041" /* ==.....A.%.>.l.A */ + $"0125 033E 036C A961 74BB 0000 0F5A 0000" /* .%.>.l.at....Z.. */ + $"0F5A 0000 0761 0100" /* .Z...a.. */ +}; + +data 'MPSR' (1008) { + $"0041 0125 033E 036C 0041 0125 033E 036C" /* .A.%.>.l.A.%.>.l */ + $"0000 0761 0000 0000 0000 0000 0000" /* ...a.......... */ +}; + +data 'ckid' (128, "Projector") { + $"B992 B7FE 3FE5 3230 0004 0000 0000 0000" /* ....?.20........ */ + $"0000 A961 C104 A961 74BB A900 0533 005C" /* ...a...at....3.\ */ + $"1376 0006 0004 0002 2653 7570 6572 4D61" /* .v......&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C56 6964 656F BA41 5449 BA00" /* .DeclVideo.ATI.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0132 000E 4154 4944 6563 6C56 6964 656F" /* .2..ATIDeclVideo */ + $"2E72 0000 0000 2470 7574 2069 6E20 6469" /* .r....$put in di */ + $"616D 6F6E 6420 6361 7264 2073 7570 706F" /* amond card suppo */ + $"7274 2066 6F72 2054 4E54 0D00" /* rt for TNT.. */ +}; + diff --git a/DeclData/DeclVideo/ATI/ATIDefROM.r b/DeclData/DeclVideo/ATI/ATIDefROM.r new file mode 100644 index 0000000..58db67b --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDefROM.r @@ -0,0 +1,238 @@ +/* + File: ATIDefROM.r + + Contains: xxx put contents here xxx + + Written by: xxx put writers here xxx + + Copyright: © 1993 by Apple Computer, Inc., all rights reserved. + + Change History (most recent first): + + <1> 11/5/93 fau first checked in + <1> 10/27/93 fau first checked in + <1> 10/19/93 fau first checked in + +*/ + +//-------------------------------------------------------------------------- +//start +// +//Name: ATIDefROM.r +//Creator: George D. Wilson Jr. +//Date: 9/19/92 +// +//Purpose: Defintions for ATI monitors declaration ROM. +// +//Category: Header File +//File: ATIDefROM.r +// +//Detailed: This file contains definitions for video modes for the Apple +// 13" and 16" monitors. +// +//Note: +// +//History: +// +// Date Programmer Modification +// -------- ---------- ----------------------------------------- +// +//stop +//------------------------------------------------------------------------*/ + +#define clutType 0 // 0 if lookup table +#define fixedType 1 // 1 if fixed table +#define directType 2 // 2 if direct values + +#define defPixelType 0 // pixeltype=chunky +#define ChunkyDirect 16 // pixelType=ChunkyDirect + +#define defmDevType clutType // clutType = 0 + +#define sRsrc_VideoHR_ATI $80 // Video parameter sResource id +#define sRsrc_Video16 $81 // Video parameter sResource id +#define sRsrc_VideoHR_Diamond $90 + +//************************************************************* +//Constants +//************************************************************* +// +// Parameter definitions {For Primary init} +// +#define defScrnRow $0080 //Bytes per pixel line +#define defMinorBase 0 //Video RAM Offset is 0 +#define defMinorLength $4B000 //Video RAM length is $40000 + +#define defBaseOffset $00000000 //Offset for ROM + +//============================================================================= +// Parameter definitions One bit-per-pixel Hi-Res 13" +//============================================================================= +#define onemBaseOffset defBaseOffset //Offset to base of video RAM +#define onemRowBytesHR $0050 //Rowbytes +#define onemBounds_THR 0 //Bounds.Top +#define onemBounds_LHR 0 //Bounds.Left +#define onemBounds_BHR 480 //Bounds.Bottom +#define onemBounds_RHR 640 //Bounds.Right +#define oneVersion 0 //Version = 0 +#define onemHRes $480000 //Horizontal Pixels/inch +#define onemVRes $480000 //Vertical pixels/inch +#define onePixelType clutType //0 = Chunky +#define onePixelSize 1 //Number of bits per pixel +#define oneCmpCount 1 //Number of components in pixel +#define oneCmpSize 1 //Number of bits per component +#define onemPlaneBytes 0 //Offset from one plane to the next. +#define onemPageCnt 1 //Total number of pages +#define onemVertRefRate 67 //Vert refresh rate + +#define onemDevType 0 //0 = CLUTType + +//============================================================================= +// Parameter definitions Two bit-per-pixel +//============================================================================= +#define twomBaseOffset defBaseOffset //Offset to base of video RAM +#define twomRowBytesHR $00A0 //Rowbytes +#define twomBounds_THR 0 //Bounds.Top +#define twomBounds_LHR 0 //Bounds.Left +#define twomBounds_BHR 480 //Bounds.Bottom +#define twomBounds_RHR 640 //Bounds.Right +#define twoVersion 0 //Version = 0 +#define twomHRes $480000 //Horizontal Pixels/inch +#define twomVRes $480000 //Vertical pixels/inch +#define twoPixelType clutType //0 = Chunky +#define twoPixelSize 2 //Number of bits per pixel +#define twoCmpCount 1 //Number of components in pixel +#define twoCmpSize 2 //Number of bits per component +#define twomPlaneBytes 0 //Offset from one plane to the next. +#define twomPageCnt 1 //Total number of pages +#define twomVertRefRate 67 //Vert refresh rate + +#define twomDevType 0 //0 = CLUTType + +//============================================================================= +// Parameter definitions Four bit-per-pixel +//============================================================================= +#define fourmBaseOffset defBaseOffset //Offset to base of video RAM +#define fourmRowBytesHR $0140 //Rowbytes +#define fourmBounds_THR 0 //Bounds.Top +#define fourmBounds_LHR 0 //Bounds.Left +#define fourmBounds_BHR 480 //Bounds.Bottom +#define fourmBounds_RHR 640 //Bounds.Right +#define fourVersion 0 //Version = 0 +#define fourmHRes $480000 //Horizontal Pixels/inch +#define fourmVRes $480000 //Vertical pixels/inch +#define fourPixelType clutType //0 = Chunky +#define fourPixelSize 4 //Number of bits per pixel +#define fourCmpCount 1 //Number of components in pixel +#define fourCmpSize 4 //Number of bits per component +#define fourmPlaneBytes 0 //Offset from one plane to the next. +#define fourmPageCnt 1 //Total number of pages +#define fourmVertRefRate 67 //Vert refresh rate + +#define onemDevType 0 //0 = CLUTType + +//============================================================================= +// Parameter definitions Eight bit-per-pixel +//============================================================================= +#define eightmBaseOffset defBaseOffset //Offset to base of video RAM +#define eightmRowBytesHR $0400 //Rowbytes +#define eightmBounds_THR 0 //Bounds.Top +#define eightmBounds_LHR 0 //Bounds.Left +#define eightmBounds_BHR 480 //Bounds.Bottom +#define eightmBounds_RHR 640 //Bounds.Right +#define eightVersion 0 //Version = 0 +#define eightmHRes $480000 //Horizontal Pixels/inch +#define eightmVRes $480000 //Vertical pixels/inch +#define eightPixelType clutType //0 = Chunky +#define eightPixelSize 8 //Number of bits per pixel +#define eightCmpCount 1 //Number of components in pixel +#define eightCmpSize 8 //Number of bits per component +#define eightmPlaneBytes 0 //Offset from one plane to the next. +#define eightmPageCnt 1 //Total number of pages +#define eightmVertRefRate 67 //Vert refresh rate + +#define onemDevType 0 //0 = CLUTType + +//============================================================================= +// Parameter definitions Sixteen bit-per-pixel +//============================================================================= +#define sixteenmBaseOffset defBaseOffset //Offset to base of video RAM +#define sixteenmRowBytesHR $0500 //Rowbytes +#define sixteenmBounds_THR 0 //Bounds.Top +#define sixteenmBounds_LHR 0 //Bounds.Left +#define sixteenmBounds_BHR 480 //Bounds.Bottom +#define sixteenmBounds_RHR 640 //Bounds.Right +#define sixteenVersion 0 //Version = 0 +#define sixteenmHRes $480000 //Horizontal Pixels/inch +#define sixteenmVRes $480000 //Vertical pixels/inch +#define sixteenPixelType $10 //0 = Chunky $10 = Direct +#define sixteenPixelSize 16 //Number of bits per in pixel +#define sixteenCmpCount 3 //Number of components in pixel +#define sixteenCmpSize 5 //Number of bits per component +#define sixteenmPlaneBytes 0 //Offset from one plane to the next. +#define sixteenmPageCnt 1 //Total number of pages +#define sixteenmVertRefRate 67 //Vert refresh rate + +#define sixteenmDevType ChunkyDirect //0 = CLUTType + +//============================================================================= +// Parameter definitions One bit-per-pixel +//============================================================================= +#define onemRowBytes16 104 //Rowbytes +#define onemBounds_T16 0 //Bounds.Top +#define onemBounds_L16 0 //Bounds.Left +#define onemBounds_B16 624 //Bounds.Bottom +#define onemBounds_R16 832 //Bounds.Right +//============================================================================= +// Parameter definitions Two bit-per-pixel +//============================================================================= +#define twomRowBytes16 208 //Rowbytes +#define twomBounds_T16 0 //Bounds.Top +#define twomBounds_L16 0 //Bounds.Left +#define twomBounds_B16 624 //Bounds.Bottom +#define twomBounds_R16 832 //Bounds.Right +//============================================================================= +// Parameter definitions Four bit-per-pixel +//============================================================================= +#define fourmRowBytes16 416 //Rowbytes +#define fourmBounds_T16 0 //Bounds.Top +#define fourmBounds_L16 0 //Bounds.Left +#define fourmBounds_B16 624 //Bounds.Bottom +#define fourmBounds_R16 832 //Bounds.Right +//============================================================================= +// Parameter definitions Eight bit-per-pixel +//============================================================================= +#define eightmRowBytes16 832 //Rowbytes +#define eightmBounds_T16 0 //Bounds.Top +#define eightmBounds_L16 0 //Bounds.Left +#define eightmBounds_B16 624 //Bounds.Bottom +#define eightmBounds_R16 832 //Bounds.Right + +//===================================================================== +// Video parameter sRsrc resource IDs +//===================================================================== + +#define sRsrcVidATIHR $80 // Hi-Res 1,2,4,8,16bpp +#define sRsrcVidATI16 $81 // 16" 1,2,4,8bpp +#define sRsrcVidATIFP $82 // 15" full page +#define sRsrcVidATI12 $83 // 12" monochrome????? + + + +//===================================================================== +// Special defines for SuperMario Build +//===================================================================== +//#define sRsrcUnknownDir 1 // sRsrc Directory for unknown CPUs. +//#define sRsrcUnknownBd 1 // Unknown board sRsrc. + +//#define sRsrcBFBasedDir $7F // CPUs supported (or thought about) in the Zydeco ROM. + +//#define sRsrc_Vid_DAFB_HRa $C8 // HiRes 8,16,32 +//#define sRsrc_Vid_DAFB_LPa $C6 // GoldFish 8,16,32 + + +//#define BoardspIDShift 1 // board spID shift value + + +//#define sRsrc_BdSpike boxQuadra700+BoardspIDShift // (16+BoardspIDShift) + diff --git a/DeclData/DeclVideo/ATI/ATIDefROM.r.idump b/DeclData/DeclVideo/ATI/ATIDefROM.r.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDefROM.r.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclVideo/ATI/ATIDefROM.r.rdump b/DeclData/DeclVideo/ATI/ATIDefROM.r.rdump new file mode 100644 index 0000000..edf69a4 --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDefROM.r.rdump @@ -0,0 +1,26 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 0078 7878 0D0D 0957" /* ..Monaco.xxx...W */ + $"7269 7474 656E 2062 793A 0978 7878 2070" /* ritten by:.xxx p */ + $"7574 0006 0004 002A 0275 0357 0471 01A4" /* ut.....*.u.W.q.. */ + $"0000 0363 043D A961 74CB 0000 27A8 0000" /* ...c.=.at...'... */ + $"27A8 0000 1B5A 0100" /* '....Z.. */ +}; + +data 'MPSR' (1008) { + $"002A 0275 0357 0471 01A4 0000 0363 043D" /* .*.u.W.q.....c.= */ + $"0000 1B5A 0000 0000 0000 0000 0000" /* ...Z.......... */ +}; + +data 'ckid' (128, "Projector") { + $"5E8E 812F 3FE5 3230 0004 0000 0000 0000" /* ^../?.20........ */ + $"0000 A961 C104 A961 74CB A900 0533 005C" /* ...a...at....3.\ */ + $"1376 0006 0005 0002 2653 7570 6572 4D61" /* .v......&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C56 6964 656F BA41 5449 BA00" /* .DeclVideo.ATI.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0132 000B 4154 4944 6566 524F 4D2E 7200" /* .2..ATIDefROM.r. */ + $"0000 0024 7075 7420 696E 2064 6961 6D6F" /* ...$put in diamo */ + $"6E64 2063 6172 6420 7375 7070 6F72 7420" /* nd card support */ + $"666F 7220 544E 540D 00" /* for TNT.. */ +}; + diff --git a/DeclData/DeclVideo/ATI/ATIDrvr.a b/DeclData/DeclVideo/ATI/ATIDrvr.a new file mode 100644 index 0000000..692a1c0 --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvr.a @@ -0,0 +1,464 @@ +; +; File: ATIDrvr.a +; +; Contains: xxx put contents here xxx +; +; Written by: xxx put writers here xxx +; +; Copyright: © 1993 by Apple Computer, Inc., all rights reserved. +; +; Change History (most recent first): +; +; <1> 11/5/93 fau first checked in +; <1> 10/27/93 fau first checked in +; <1> 10/19/93 fau first checked in +; +; + +;-------------------------------------------------------------------------- +;start +; +;Name: ATIDrvr.a +;Creator: George D. Wilson Jr. +;Date: 4/24/92 +; +;Purpose: Driver header for the ATI graphics driver. +; +;Category: Driver Header +;File: ATIDrvr.a +; +;Exports: Open - Driver open routine. +; Control - Driver control routine. +; Status - Driver status routine. +; Close - Driver close routine. +; intHandler - ATI VBL interrupt handler. +; +;Locals: done - Common driver exit routine. +; +;Detailed: This file is the assembly front end to the high level +; ATI driver routines. Most routines within this module +; simply setup a call to a high level routine of the same type. +; The only exception to this "Open". Open performs almost +; all the driver and variable initalization. +; +;Note: +; +;History: +; +; Date Programmer Modification +; -------- ---------- ----------------------------------------- +; +;stop +;------------------------------------------------------------------------*/ + +;-------------------------------------------------------------------------- +; +; Includes +; +;------------------------------------------------------------------------*/ + + include 'QuickDraw.a' + include 'Traps.a' + include 'SysEqu.a' + include 'ToolUtils.a' + include 'SysErr.a' + + include 'ATIHdr.a' + +;-------------------------------------------------------------------------- +; +; Imported Variables +; +;------------------------------------------------------------------------*/ + +globals RECORD 0,INCREMENT + ALIGN 2 +globalsSize EQU *-globals + ENDR + +Enable EQU 1 ; Turn ATI interrupts on +true EQU 1 ; Boolean true +false EQU 0 ; Boolean false + +;-------------------------------------------------------------------------- +; +; Imported Procedures +; +;------------------------------------------------------------------------*/ + + IMPORT OpenDRVR ; High level 'C' open routine + IMPORT ControlDRVR ; High level 'C' control routine + IMPORT StatusDRVR ; High level 'C' status routine + IMPORT CloseDRVR ; High level 'C' close routine + IMPORT DrvrSlotIntHandlerNuBus ; High level 'C' interrupt handler + +;-------------------------------------------------------------------------- +; +; Local Equates +; +;------------------------------------------------------------------------*/ + +rSave reg d1-d7/a0-a6 ; Saved registers + +;-------------------------------------------------------------------------- +; +; Exported Procedures +; +;------------------------------------------------------------------------*/ + +;-------------------------------------------------------------------------- +; +; Driver Headers +; +; *** WARNING: No code must be placed before these headers. *** +; +;------------------------------------------------------------------------*/ + +ATI MAIN EXPORT + + IMPORT Open + IMPORT Close + IMPORT Control + IMPORT Status + +ATIDrvr + dc.w $4C00 ; Flags: locked,bye,stat,ctl + dc.w 0 ; Periodic call interval + dc.w 0 ; Not an ornament + dc.w 0 ; No menu + + dc.w Open-ATIDrvr ; Open routine offset + dc.w 0 ; Prime routine offset + dc.w Control-ATIDrvr ; Control routine offset + dc.w Status-ATIDrvr ; Status routine offset + dc.w Close-ATIDrvr ; Close routine offset + + STRING PASCAL + _DCB_DriverNameATI ; Name of driver + ALIGN 2 + _DCW_Version ; Version number of driver + + ENDP + +;-------------------------------------------------------------------------- +; +; Beginning of Procedure Definitions +; +;------------------------------------------------------------------------*/ + + +;-------------------------------------------------------------------------- +;start +; +;Name: done +;Creator: George D. Wilson Jr. +;Date: 4/24/92 +; +;Purpose: Common exit routine. +; +;Category: Driver Done Handler +;File: ATIDrvr.a +; +;Calls: none +; +;Called By: Open, Close, Status, Control +; +;Entry: A0 - Parameter block pointer. +; A1 - Driver DCE pointer. +; +;Alters: ioResult - In parameter block will be altered. +; +;Exit: D0 - Result code (also copied into parameter block) +; +;Algorithm: If the "noQueueBit" bit is set in the ioTrap field of the +; parameter block, the I/O call is immediate, and exit via +; an RTS instruction. Immediate calls don't go through IODone, +; since the parameter block isn't queued. +; +; If ioResult is less than or equal to zero, return via a +; jump to the Device Manager's IODone routine. +; +; If ioResult is greater than zero, indicating that the I/O +; call is not yet done, return is via an RTS instruction. +; +;History: +; +; Date Programmer Modification +; -------- ---------- --------------------------------------- +; +;stop +;------------------------------------------------------------------------*/ + +done PROC + + bclr #drvrActive,dCtlFlags+1(a1) ; always clear busy bit + move.w ioResult(a0),d0 ; get ioResult + tst.w d0 ; is the call done? + bgt.s @byRts ; no - exit via RTS instr. + btst #noQueueBit-8,ioTrap(a0) ; is the call immediate? + bne.s @byRts ; br if so - exit via RTS instr. + move.l JIODone,-(sp) ; call is done; return to IODone + +@byRts +; _Debugger ; MacsBug + rts ; + ENDP + + +;-------------------------------------------------------------------------- +;start +; +;Name: IntHandlerNuBus +;Creator: George D. Wilson Jr. +;Date: 4/24/92 +; +;Purpose: ATI interrupt handler. +; +;Category: Slot Interrupt Handler +;File: ATIDrvr.a +; +;Called By: Mac exception handler +; +;Alters: +; +;Detailed: This is the low level entry point for the interrupt generated +; by the cursor VBL. +; +; Currently this routine is called by the 'intMeister' interrupt +; system. It determines which ATI interrupt generated the +; exception and calls the appropriate routine registered. +; +;Note: Keep a eye on this routine if the hardware or the 'intMeister' +; change. +; +;History: +; +; Date Programmer Modification +; -------- ---------- ---------------------------------------- +; +;stop +;------------------------------------------------------------------------*/ +IntHandlerNuBus PROC EXPORT + + +; _Debugger + moveq #kOurSlotNum,d0 + move.l JVBLTask,a0 ; Make the cursor move + jsr (a0) + moveq #1,d0 +@noVBL rts + + ENDP + + +;-------------------------------------------------------------------------- +;start +; +;Name: Open +;Creator: George D. Wilson Jr. +;Date: 4/24/92 +; +;Purpose: Performs low level driver open functions. +; +;Category: Driver Entry Point. +;File: ATIDrvr.c +; +;Calls: OpenDRVR, done +; +;Entry: a1 - Our driver DCE. +; +;Alters: dCtlStorage - Will be set to the global data storage +; for our driver if everything is OK. +; +; ioResult(a0) - The ioResult field of the parameter +; block will contain a driver error code +; or 'noErr' if everything went OK. +; +;Exit: d0 - Contains a driver error code or 'noErr' +; if everything went OK. +; +;Detailed: This routine leaves all the hard work to the high level routine. +; It expects the high level to indicate the success or failure by +; leaving a result code in D0. +; +;History: +; +; Date Programmer Modification +; -------- ---------- ----------------------------------------- +; +;stop +;------------------------------------------------------------------------*/ +Open PROC + + WITH globals + + movem.l rSave,-(sp) ; Save regs + move.l a1,-(sp) ; push DCE pointer + move.l a0,-(sp) ; push parm block pointrt + jsr OpenDRVR ; call C code + add #8,sp ; drop arguments + movem.l (sp)+,rSave ; Restore registers + move.w d0,ioResult(a0) ; Store the result code + bra done + ENDP + +;-------------------------------------------------------------------------- +;start +; +;Name: Close +;Creator: George D. Wilson Jr. +;Date: 4/24/92 +; +;Purpose: Performs driver close function. +; +;Category: Driver Entry Point. +;File: ATIDrvr.c +; +;Calls: close, done +; +;Entry: a0 - Pointer to callers parameter block. +; +; a1 - Pointer to our driver DCE. +; +;Alters: ioResult(a0) - The result field of the parameter block +; is set to the value returned from the +; high level call. The high level routine +; leaves its result in D0. +; +;Exit: d0 - Has a driver error code left by the high level routine. +; +;Detailed: When a driver close call is made this routine passes the +; callers parameter block in A0 and the driver DCE in A1 and +; calls the high level routine. The high routine handles everything. +; +; The high level routine should return a driver error code in D0. +; +;History: +; +; Date Programmer Modification +; -------- ---------- ----------------------------------------- +; +;stop +;------------------------------------------------------------------------*/ +Close PROC +; _Debugger ; MacsBug + movem.l rSave,-(sp) ; Save regs + move.l a1,-(sp) ; push DCE pointer + move.l a0,-(sp) ; push parm block pointer + jsr CloseDRVR ; call C code + add #8,sp ; drop arguments + movem.l (sp)+,rSave ; Restore registers + move.w d0,ioResult(a0) ; Store the result code + bra done + + ENDP +;-------------------------------------------------------------------------- +;start +; +;Name: Status +;Creator: George D. Wilson Jr. +;Date: 4/24/92 +; +;Purpose: Performs driver status functions. +; +;Category: Driver Entry Point. +;File: ATIDrvr.c +; +;Calls: status, done +; +;Entry: a0 - Pointer to callers parameter block. +; +; a1 - Pointer to our driver DCE. +; +;Alters: ioResult(a0) - The result field of the parameter block +; is set to the value returned from the +; high level call. The high level routine +; leaves its result in D0. +; +;Exit: d0 - Has a driver error code or 'noErr'. +; +;Detailed: This routine is simply an assembly language interface +; to the higher level status routine. It pushs a +; pointer to the callers parameter and then pushs +; a pointer to the driver DCE onto the stack. +; +; The high level routine should return a driver error +; code in D0. +; +;History: +; +; Date Programmer Modification +; -------- ---------- ----------------------------------------- +; +;stop +;------------------------------------------------------------------------*/ +Status PROC + movem.l rSave,-(sp) ; Save regs + move.l a1,-(sp) ; push DCE pointer + move.l a0,-(sp) ; push parm block pointer + jsr StatusDRVR ; call C code + add #8,sp ; drop arguments + movem.l (sp)+,rSave ; Restore registers + move.w d0,ioResult(a0) ; Store the result code + bra done + + ENDP +;-------------------------------------------------------------------------- +;start +; +;Name: Control +;Creator: George D. Wilson Jr. +;Date: 4/24/92 +; +;Purpose: Performs driver control functions. +; +;Category: Driver Entry Point. +;File: ATIDrvr.c +; +;Calls: control, done +; +;Entry: a0 - Pointer to callers parameter block. +; +; a1 - Pointer to our driver DCE. +; +;Alters: ioResult(a0) - The result field of the parameter block +; is set to the value returned from the +; high level call. The high level routine +; leaves its result in D0. +; +;Exit: d0 - Has a driver error code or 'noErr'. +; +;Detailed: This routine is simply an assembly language interface +; to the higher level control routine. It pushs a +; pointer to the callers parameter and then pushs +; a pointer to the driver DCE onto the stack. +; +; The high level routine should return a driver error +; code in D0. +; +;History: +; +; Date Programmer Modification +; -------- ---------- ----------------------------------------- +; +;stop +;------------------------------------------------------------------------*/ +Control PROC + + movem.l rSave,-(sp) ; Save regs + move.l a1,-(sp) ; push DCE pointer + move.l a0,-(sp) ; push parm block pointrt + jsr ControlDRVR ; call C code + add #8,sp ; drop arguments + movem.l (sp)+,rSave ; Restore registers + move.w d0,ioResult(a0) ; Store the result code + bra done + + ENDP + + END +;-------------------------------------------------------------------------- +; +; End of Module +; +;------------------------------------------------------------------------*/ diff --git a/DeclData/DeclVideo/ATI/ATIDrvr.a.idump b/DeclData/DeclVideo/ATI/ATIDrvr.a.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvr.a.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclVideo/ATI/ATIDrvr.a.rdump b/DeclData/DeclVideo/ATI/ATIDrvr.a.rdump new file mode 100644 index 0000000..941f75d --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvr.a.rdump @@ -0,0 +1,34 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 00BE 0009 0000 0014" /* ..Monaco........ */ + $"0001 2260 000A 0050 014A 00AC 02B6 0000" /* .."`...P.J...... */ + $"0000 0006 0004 005C 0099 0237 0347 005C" /* .......\...7.G.\ */ + $"0099 0237 0347 A933 73B5 0000 072C 0000" /* ...7.G.3s....,.. */ + $"0733 0000 2D92 0100" /* .3..-... */ +}; + +data 'MPSR' (1007) { + $"0006 0000 2384 0000 2389 0543 6C6F 7365" /* ....#...#..Close */ + $"0000 2ED8 0000 2EDF 0743 6F6E 7472 6F6C" /* .........Control */ + $"0000 1407 0000 140B 0564 6F6E 6500 0000" /* .........done... */ + $"1926 0000 1935 0B69 6E74 4861 6E64 6C65" /* .&...5.intHandle */ + $"7200 0000 1DDE 0000 1DE2 054F 7065 6E00" /* r..........Open. */ + $"0000 2939 0000 293F 0753 7461 7475 7300" /* ..)9..)?.Status. */ +}; + +data 'MPSR' (1008) { + $"005C 0099 0237 0347 005C 0099 0237 0347" /* .\...7.G.\...7.G */ + $"0000 2D92 0000 0000 0000 0000 0000" /* ..-........... */ +}; + +data 'ckid' (128, "Projector") { + $"C19B A15E 3FE5 3230 0004 0000 0000 0000" /* ...^?.20........ */ + $"0000 A933 73B5 A933 73B5 A900 0533 005C" /* ...3s..3s....3.\ */ + $"1376 0000 0006 0001 2653 7570 6572 4D61" /* .v......&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C56 6964 656F BA41 5449 BA00" /* .DeclVideo.ATI.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0131 0009 4154 4944 7276 722E 6100 0000" /* .1..ATIDrvr.a... */ + $"0010 6669 7273 7420 6368 6563 6B65 6420" /* ..first checked */ + $"696E 00" /* in. */ +}; + diff --git a/DeclData/DeclVideo/ATI/ATIDrvr.c b/DeclData/DeclVideo/ATI/ATIDrvr.c new file mode 100644 index 0000000..29659a0 --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvr.c @@ -0,0 +1,610 @@ +/* + File: ATIDrvr.c + + Contains: xxx put contents here xxx + + Written by: xxx put writers here xxx + + Copyright: © 1993 by Apple Computer, Inc., all rights reserved. + + Change History (most recent first): + + <1> 11/5/93 fau first checked in + <1> 10/27/93 fau first checked in + <1> 10/19/93 fau first checked in + +*/ + +/*------------------------------------------------------------------------- +*start +* +*Name: ATIDriver.c +*Creator: George D. Wilson Jr. +*Date: 8/15/93 +* +*Purpose: Main interface file for ATI video driver. +* +*Category: Macintosh driver +*File: ATIDrvr.c +* +*Exports: OpenDRVR - Handles initialization of driver. +* CloseDRVR - Handles shutdown of driver. +* ControlDRVR - Handles driver control calls. +* StatusDRVR - Handles driver status calls. +* WaitForVBL - Returns when vertical blanking is active. +* +*Locals: +* +*Detailed: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +* +* Includes +* +*-----------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ATIStdTypes.h" +#include "ATI.h" +#include "ATIDrvr.h" +#include "ATIVideo.h" + +#include "NubEqu.h" + +/*------------------------------------------------------------------------- +* +* Imported Procedures +* +*-----------------------------------------------------------------------*/ +extern UInt16 GetRowBytes(UInt8 monitorID, UInt8 videoMode, UInt8 theSlot); + +extern void IntHandlerNuBus(); + +/*------------------------------------------------------------------------- +* +* Exported Procedures +* +*-----------------------------------------------------------------------*/ +UInt16 OpenDRVR (CntrlParam *pb, AuxDCEPtr dce); +UInt16 CloseDRVR (CntrlParam *pb, DCtlPtr dce); +UInt16 ControlDRVR (CntrlParam *pb, DCtlPtr dce); +UInt16 StatusDRVR (CntrlParam *pb, DCtlPtr dce); + +/*------------------------------------------------------------------------- +* +* Beginning of Procedure Definitions +* +*-----------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +*start +* +*Name: WaitForVBL +*Creator: George D. Wilson Jr. +*Date: 3/20/92 +* +*Purpose: +* +*Category: +*File: +* +*Calls: +* +*Called By: +* +*Entry: +* +*Alters: +* +*Exit: +* +*Detailed: +* +*Algorithm: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ +void WaitForVBL() +{ + short i=0; + + i = i+1; +// DebugStr("\pWaitForVBL"); + + +} /* End of WaitForVBL */ + +/*------------------------------------------------------------------------- +*start +* +*Name: InstallInterruptRoutine +*Creator: George D. Wilson Jr. +*Date: 3/20/92 +* +*Purpose: +* +*Category: +*File: +* +*Calls: +* +*Called By: +* +*Entry: +* +*Alters: +* +*Exit: +* +*Detailed: +* +*Algorithm: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ +void InstallInterruptRoutine(DCtlPtr dce) +{ + +// OSErr err; + globalsPtr g; +// UInt32 intHi; + +// DebugStr("\pInstallInterruptRoutine"); + + g = (globalsPtr) *(dce->dCtlStorage); + +// RegisterNubInt(kVideoLineInt,(InterruptHdlr) IntHandlerNuBus,(long) dce); + + g->gInterruptsEnabled = kVBLInterruptEnabled; + +} /* End of InstallInterruptRoutine */ + + +/*------------------------------------------------------------------------- +*start +* +*Name: RemoveInterruptRoutine +*Creator: George D. Wilson Jr. +*Date: 3/20/92 +* +*Purpose: +* +*Category: +*File: +* +*Calls: +* +*Called By: +* +*Entry: +* +*Alters: +* +*Exit: +* +*Detailed: +* +*Algorithm: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ +void RemoveInterruptRoutine(DCtlPtr dce) +{ + +// OSErr err; + globalsPtr g; + +// DebugStr("\pRemoveInterruptRoutine"); + + g = (globalsPtr) *(dce->dCtlStorage); + if ( g->gInterruptsEnabled ) { + WaitForVBL(); + if ( *(long*)(kMySlot | kNMRQDisable) ); +// RemoveNubInt(kVideoLineInt); + g->gInterruptsEnabled = kVBLInterruptDisabled; + } + +} + +/*------------------------------------------------------------------------- +*start +* +*Name: OpenDRVR +*Creator: George D. Wilson Jr. +*Date: 3/20/92 +* +*Purpose: +* +*Category: +*File: +* +*Calls: +* +*Called By: +* +*Entry: +* +*Alters: +* +*Exit: +* +*Detailed: +* +*Algorithm: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ +UInt16 OpenDRVR (CntrlParam *pb, AuxDCEPtr dce) +{ + +#pragma unused(pb) + + globalsPtr g; + Handle globs; + UInt16 i; + SpBlock spPb; +// OSErr err; + SPRAMRecord sPRAM; + UInt8 videoMode; + +// DebugStr("\pOpenDRVR"); + + globs = nil; + ResrvMem(GLOBALSSIZE); + globs = NewHandleSysClear(GLOBALSSIZE); + if ( globs == nil ) return(openErr); + + dce->dCtlStorage = globs; + HLock(globs); + g = (globalsPtr) *(globs); + + //========================================================================== + // Zero all global data stuff + //========================================================================== + g->gGammaPtr = nil; + g->gCurrentPage = kOurVidPage; + g->gCurrentMode = kFirstVideoMode; // 8 bpp Fix this later ••• + g->gBaseAddr = (Ptr) (kATIVRAMAddr); + g->gFBBaseAddr = (Ptr) (kATIVRAMAddr); + g->gInterruptsEnabled = kVBLInterruptEnabled; + g->gMonoOnly = false; // Device supports color ••• + g->gLuminanceMode = false; // Current mode is color ••• + g->gDirectMode = false; + g->gNumLines = kNumLines480; // 13" is 480 ••• + g->gBigSlotNum = dce->dCtlSlot; + g->gSlotNum = dce->dCtlSlot; + + videoMode = kFirstVideoMode; + + spPb.spSlot = g->gSlotNum; + spPb.spResult = &sPRAM; +#if 0 + err = SReadPRAMRec(&spPb); + if ( err == noErr ) { // Did we get our PRAM? + g->gMonitorID = sPRAM.vendorUse4; // No save the monitor ID + g->gCurrentMode = sPRAM.vendorUse1; // Use the first video mode + if ( g->gCurrentMode > kFirstVideoMode ) { + g->gDirectMode = true; + } + } +#else + g->gDirectMode = false; + g->gMonitorID = kRGB1312; // No save the monitor ID + g->gCurrentMode = kFirstVideoMode; +#endif + g->gRowBytes = GetRowBytes(g->gMonitorID,g->gCurrentMode,g->gSlotNum); + + //========================================================================== + // Get or build gamma table + //========================================================================== + g->gGammaPtr = (GammaTablePtr) NewPtrSysClear(sizeof(GammaTable)); + if ( g->gGammaPtr ) { + g->gGammaPtr->gFormulaSize = 0; + g->gGammaPtr->gChanCnt = 1; + g->gGammaPtr->gDataCnt = 3; + g->gGammaPtr->gDataCnt = 256; + g->gGammaPtr->gDataWidth = 0x0008; + for ( i = 0; i < kNumCLUTEntries; i++ ) { + g->gGammaPtr->gFormulaData[i] = i; + } + } +#ifndef ROM +// InitNubInts(); +// InitNubIntMgr(); +#endif +// InstallInterruptRoutine(dce); + +#ifdef ROM +// err = AttachVBL(0x0E); +#endif + + return(noErr); // Say open was successful + +} + +/*------------------------------------------------------------------------- +*start +* +*Name: CloseDRVR +*Creator: George D. Wilson Jr. +*Date: 3/20/92 +* +*Purpose: +* +*Category: +*File: +* +*Calls: +* +*Called By: +* +*Entry: +* +*Alters: +* +*Exit: +* +*Detailed: +* +*Algorithm: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ +UInt16 CloseDRVR (CntrlParam *pb, DCtlPtr dce) +{ +#pragma unused(pb) + globalsPtr g; + UInt8 mmuMode; + +// DebugStr("\pCloseDRVR"); + + g = (globalsPtr) *(dce->dCtlStorage); + mmuMode = true32b; + SwapMMUMode(&mmuMode); + DoDisableVideo(g->gBigSlotNum); // Turn the video system off + if ( g->gGammaPtr ) { // If we have a gamma table + DisposPtr((Ptr) (g->gGammaPtr)); // Release the memory + } + + if ( g->gInterruptsEnabled ) { // If cursor interrupts are enabled +// RemoveInterruptRoutine(dce); // Disable them + } + + SwapMMUMode(&mmuMode); + DisposHandle(dce->dCtlStorage); // Release driver globals storage + return(noErr); // Say open was successful + +} + +/*------------------------------------------------------------------------- +*start +* +*Name: ControlDRVR +*Creator: George D. Wilson Jr. +*Date: 3/20/92 +* +*Purpose: +* +*Category: +*File: +* +*Calls: +* +*Called By: +* +*Entry: +* +*Alters: +* +*Exit: +* +*Detailed: +* +*Algorithm: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ +UInt16 ControlDRVR (CntrlParam *pb, DCtlPtr dce) +{ + Int16 message; // The control call being made + OSErr err; + globalsPtr g; + UInt8 mmuMode; + +// DebugStr("\pControlDRVR"); + + g = (globalsPtr) *(dce->dCtlStorage); + mmuMode = true32b; + SwapMMUMode(&mmuMode); + message = pb->csCode; + + switch ( message ) { + case cscReset: + err = DoVideoReset((VDPgInfoPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; +// case cscKillIO: +// err = DoKillIO((VDPgInfoPtr) *((UInt32 *) &(pb->csParam[0])), dce); +// break; + case cscSetMode: + err = DoSetVideoMode((VDPgInfoPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscSetEntries: + err = DoSetEntries((VDSetEntryPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscSetGamma: + err = DoSetGamma((VDGamRecPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscGrayScreen: + err = DoGrayPage((VDPgInfoPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscSetGray: + err = DoSetGray((VDGrayPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscSetInterrupt: + err = DoSetInterrupt((VDPgInfoPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscDirectSetEntries: + err = DoDirectSetEntries((VDSetEntryPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscSetDefaultMode: + err = DoSetDefaultMode((VDDefModePtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case 200: + err = noErr; + break; + default: err = controlErr; + + } // End switch + pb->ioResult = err; + SwapMMUMode(&mmuMode); + return(err); +} + +/*------------------------------------------------------------------------- +*start +* +*Name: StatusDRVR +*Creator: George D. Wilson Jr. +*Date: 3/20/92 +* +*Purpose: +* +*Category: +*File: +* +*Calls: +* +*Called By: +* +*Entry: +* +*Alters: +* +*Exit: +* +*Detailed: +* +*Algorithm: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ +UInt16 StatusDRVR (CntrlParam *pb, DCtlPtr dce) +{ + + Int16 message; // The control call being made + OSErr err; // Error code returned from routine + globalsPtr g; + UInt8 mmuMode; + +// DebugStr("\pStatusDRVR"); + + g = (globalsPtr) *(dce->dCtlStorage); + mmuMode = true32b; + SwapMMUMode(&mmuMode); + message = pb->csCode; + err = statusErr; // Standard error code + + switch ( message ) { + case cscGetMode: + err = DoGetMode((VDPgInfoPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscGetEntries: + err = DoGetEntries((VDSetEntryPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscGetPageCnt: + err = DoGetPages((VDPgInfoPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscGetBaseAddr: + err = DoGetBaseAddr((VDPgInfoPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscGetGray: + err = DoGetGray((VDGrayPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscGetInterrupt: + err = DoGetInterrupt((VDPgInfoPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscGetGamma: + err = DoGetGamma((VDGamRecPtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + case cscGetDefaultMode: + err = DoGetDefaultMode((VDDefModePtr) *((UInt32 *) &(pb->csParam[0])), dce); + break; + } // End switch + pb->ioResult = err; // Pass result code on + SwapMMUMode(&mmuMode); + return(err); + +} + +/*------------------------------------------------------------------------- +* +* End of Module +* +*-----------------------------------------------------------------------*/ diff --git a/DeclData/DeclVideo/ATI/ATIDrvr.c.idump b/DeclData/DeclVideo/ATI/ATIDrvr.c.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvr.c.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclVideo/ATI/ATIDrvr.c.rdump b/DeclData/DeclVideo/ATI/ATIDrvr.c.rdump new file mode 100644 index 0000000..7ee76dd --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvr.c.rdump @@ -0,0 +1,26 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 002D 2D2D 2D2D 2D2D" /* ..Monaco.------- */ + $"2D2D 2D2D 2D2D 2D2D 2D2D 2D0D 2A73 7461" /* -----------.*sta */ + $"7274 0006 0004 0070 00A3 0339 034F 0070" /* rt.....p...9.O.p */ + $"00A3 0339 034F A961 74E0 0000 31BA 0000" /* ...9.O.at...1... */ + $"31BA 0000 2AD5 0100" /* 1...*... */ +}; + +data 'MPSR' (1008) { + $"0070 00A3 0339 034F 0070 00A3 0339 034F" /* .p...9.O.p...9.O */ + $"0000 2AD5 0000 0000 0000 0000 0000" /* ..*........... */ +}; + +data 'ckid' (128, "Projector") { + $"AE13 AE73 3FE5 3230 0004 0000 0000 0000" /* ...s?.20........ */ + $"0000 A961 C104 A961 74E0 A900 0533 005C" /* ...a...at....3.\ */ + $"1376 0006 0007 0002 2653 7570 6572 4D61" /* .v......&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C56 6964 656F BA41 5449 BA00" /* .DeclVideo.ATI.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0132 0009 4154 4944 7276 722E 6300 0000" /* .2..ATIDrvr.c... */ + $"0024 7075 7420 696E 2064 6961 6D6F 6E64" /* .$put in diamond */ + $"2063 6172 6420 7375 7070 6F72 7420 666F" /* card support fo */ + $"7220 544E 540D 00" /* r TNT.. */ +}; + diff --git a/DeclData/DeclVideo/ATI/ATIDrvr.h b/DeclData/DeclVideo/ATI/ATIDrvr.h new file mode 100644 index 0000000..b27a85e --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvr.h @@ -0,0 +1,304 @@ +/* + File: ATIDrvr.h + + Contains: xxx put contents here xxx + + Written by: xxx put writers here xxx + + Copyright: © 1993 by Apple Computer, Inc., all rights reserved. + + Change History (most recent first): + + <1> 11/5/93 fau first checked in + <1> 10/27/93 fau first checked in + <1> 10/19/93 fau first checked in + +*/ + +/*------------------------------------------------------------------------- +*start +* +*Name: ATIDrvr.h +*Creator: George D. Wilson Jr. +*Date: 3/17/92 +* +*Purpose: Contains structures and defines for the RISC video driver. +* +*Category: Header File +*File: ATIDrvr.h +* +*Detailed: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ + +#define ATI 1 // Indicate we are for ATI hardware + +#define kNumPages 1 // Number of video pages +#define kOurVidPage 0 // The video page we use Always 0 on Quadra +#define kVBLInterruptEnabled 0 // VBL interrupts enabled return value +#define kVBLInterruptDisabled 1 // VBL interrupts disenabled return value +#define kDAFBHWID 0x001C // DAFB hardware device ID + +#define kRowBytes138bpp 0x400 // Apple 13" rowbytes 8bpp +// #define kRowBytes1316bpp 0x500 // Apple 13" rowbytes 16bpp +// #define kRowBytes1324bpp 0xA00 // Apple 13" rowbytes 24bpp + +#define kNumLines480 480 // + +#define kNumCLUTEntries 256 // Number of entries in the CLUT + +#define kSuper9 0x90000000 +#define kSuperA 0xA0000000 +#define kSuperB 0xB0000000 +#define kSuperC 0xC0000000 +#define kSuperD 0xD0000000 +#define kSuperE 0xE0200000 + +#define kSlot9 0x09000000 +#define kSlotA 0x0A000000 +#define kSlotB 0x0B000000 +#define kSlotC 0x0C000000 +#define kSlotD 0x0D000000 +#define kSlotE 0x0E000000 + +#define kMySlot kSlotE // Used to access ATI with Nub601 + +#ifdef ROM +#define kMySlot8 0x00 // Used to access ATI sResource structs +#else +#define kMySlot8 0x0E // Used to access ATI with Nub601 +#endif + +#define kMySuperSlot kSuperE // Used to access ATI with Nub601 + +#define kFirstVideoMode 0x80 +#define kSecondVideoMode 0x81 +#define kThirdVideoMode 0x82 +#define kFourthVideoMode 0x83 +#define kFifthVideoMode 0x84 +#define kSixthVideoMode 0x85 + +//=============================================================================== +// Below are the bit patterns to write into memory for each of the supported +// bit depths. +//=============================================================================== + +#define kOneBitPattern 0xAAAAAAAA +#define kTwoBitPattern 0xCCCCCCCC +#define kFourBitPattern 0xF0F0F0F0 +#define kEightBitPattern 0xFF00FF00 +#define kSixTeenBitPattern 0xFFFF0000 +#define kThirtyTwoBitPattern 0xFFFFFFFF + +#define kGrayCLUTValue 0x00808080 // Value to gray the CLUT + +#define kRedLumValue 0x4CCC +#define kGreenLumValue 0x970A +#define kBlueLumValue 0x1C29 + +//=============================================================================== +// The following definitions define the number of long word writes to +// to do to fill one line of video on the 13" monitor. +// This should be changed later to be monitor indepentent. +//=============================================================================== +#define kOneBitBytes 0x14 // Number of long writes for one bpp +#define kTwoBitBytes 0x28 // Number of long writes for two bpp +#define kFourBitBytes 0x50 // Number of long writes for four bpp +#define kEightBitBytes 0xA0 // Number of long writes for eight bpp +#define kSixTeenBitBytes 0x140 // Number of long writes for sixteen bpp +#define kThirtyTwoBitBytes 0x280 // Number of long writes for thirty two bpp + +#define kMonoDevice 0x01 // Monochrome device +#define kNonMonoDevice 0x00 // Non luminance mapping device + +// #define kNumLines 480 // Number of lines on a 13" + +//========================================================================== +// Sense line decode values +//========================================================================== +#define kSenseLineReset 0x00000007 // Drives all lines low +#define kSenseLineAMask 0x00000006 // Drives the A bit +#define kSenseLineBMask 0x00000005 // Drives the B bit +#define kSenseLineCMask 0x00000003 // Drives the C bit +#define kSenseLineMask 0x00000070 // Only the first three bits are used + +#define kMonitorNotConnected 0x07 // No monitor or extended value + +#define kRGB21 0x00 // 21" RGB display 1152x870 100.0 MHz +#define kFullPage 0x01 // Full page display 640x870 57.28 MHz +#define kRGB12 0x02 // 12" RGB display 512x384 15.67 MHz +#define kTwoPage 0x03 // Two page display 1152x870 100.0 MHz +#define kNTSC 0x04 // NTSC display varxvar 12.27 MHz +#define kRGB15 0x05 // 15" RGB display 640x870 57.28 MHz +#define kRGB1312 0x06 // Hi-Res 13" & 12" displays 30.24 MHz + +#define k16SenseACode 0x02 // Value received from A mask +#define k16SenseBCode 0x05 // Value received from B mask +#define k16SenseCCode 0x02 // Value received from C mask + +//========================================================================== +// Slot manager defines for the timing sResources +//========================================================================== +#define kATIVidParmSpId 0x7E // Resource id for the all ATI video systems + +#define kNoMonitorConnected 0xFF // No Monitor connected to system +#define kRGB1312Connected 0x80 // Hi-Res sRsrc ID +#define kRGB16Connected 0x81 // 16" sRsrc ID +#define kRGB21Connected 0x82 // sRsrc ID +#define kFullPageConnected 0x83 // sRsrc ID +#define kRGB12Connected 0x84 // sRsrc ID +#define kTwoPageConnected 0x85 // sRsrc ID +#define kNTSCConnected 0x86 // sRsrc ID +#define kRGB15Connected 0x87 // sRsrc ID + +#define kEndeavorParmSpId 0x80 // Resource id of Endeavor SBlock +#define kACDCParmSpId 0x81 // Resource id of ACDC SBlock +#define kSwatchParmSpId 0x82 // Resource id of Swatch SBlock + +//========================================================================== +// Definition of default mode data structure +//========================================================================== +struct VDDefMode { + UInt8 csID; +}; + +typedef struct VDDefMode VDDefMode; +typedef VDDefMode *VDDefModePtr, **VDDefModeHandle; + +#define kVDDefModeSize (sizeof(VDDefMode)) + +//========================================================================== +// Exported status routines +//========================================================================== +OSErr DoGetBaseAddr(VDPgInfoPtr pgPtr, DCtlPtr dce); +OSErr DoGetDefaultMode(VDDefModePtr dfPtr, DCtlPtr dce); +OSErr DoGetEntries(VDSetEntryPtr pgPtr, DCtlPtr dce); +OSErr DoGetGamma(VDGamRecPtr gPtr, DCtlPtr dce); +OSErr DoGetGray(VDGrayPtr pgPtr, DCtlPtr dce); +OSErr DoGetInterrupt(VDPgInfoPtr flgPtr, DCtlPtr dce); +OSErr DoGetMode(VDPgInfoPtr pgPtr, DCtlPtr dce); +OSErr DoGetPages(VDPgInfoPtr pgPtr, DCtlPtr dce); + +//========================================================================== +// Exported control routines +//========================================================================== +OSErr DoVideoReset(VDPgInfoPtr pgPtr, DCtlPtr dce); +OSErr DoSetVideoMode(VDPgInfoPtr pgPtr, DCtlPtr dce); +OSErr DoSetEntries(VDSetEntryPtr pgPtr, DCtlPtr dce); +OSErr DoSetGamma(VDGamRecPtr pgPtr, DCtlPtr dce); +OSErr DoGrayPage(VDPgInfoPtr pgPtr, DCtlPtr dce); +OSErr DoSetGray(VDGrayPtr pgPtr, DCtlPtr dce); +OSErr DoSetInterrupt(VDPgInfoPtr pgPtr, DCtlPtr dce); +OSErr DoDirectSetEntries(VDSetEntryPtr pgPtr, DCtlPtr dce); +OSErr DoSetDefaultMode(VDDefModePtr dfPtr, DCtlPtr dce); + +//========================================================================== +// Definition of slot manager vendor PRAM data structure +//========================================================================== +struct SPRAMRecord { + UInt16 boardID; + UInt8 vendorUse1; + UInt8 vendorUse2; + UInt8 vendorUse3; + UInt8 vendorUse4; + UInt8 vendorUse5; + UInt8 vendorUse6; +}; + +typedef struct SPRAMRecord SPRAMRecord; +typedef SPRAMRecord *SPRAMRecordPtr, **SPRAMRecordHandle; + +#define kSPRAMRecordSize (sizeof(SPRAMRecord)) + +//========================================================================== +// Definition of gamma table data structure +//========================================================================== +struct GammaTable { + short gVersion; // gamma version number + short gType; // gamma data type + short gFormulaSize; // Formula data size + short gChanCnt; // number of channels of data + short gDataCnt; // number of values/channel + short gDataWidth; // bits/corrected value (data packed to next larger byte size) + char gFormulaData[255*3]; // data for formulas followed by gamma values +}; + +typedef struct GammaTable GammaTable; +typedef GammaTable *GammaTablePtr, **GammaTableHandle; + +#define kGammaTableSize (sizeof(GammaTable)) + +struct ACDCVidParms { + UInt8 pbcr0ValueFirstMode; + UInt8 pbcr1ValueFirstMode; + UInt8 pbcr0ValueSecondMode; + UInt8 pbcr1ValueSecondMode; + UInt8 pbcr0ValueThirdMode; + UInt8 pbcr1ValueThirdMode; +}; + +typedef struct ACDCVidParms ACDCVidParms; +typedef struct ACDCVidParms *ACDCVidParmsPtr; +typedef struct ACDCVidParms **ACDCVidParmsHdl; + +#define ACDCVIDPARMSSIZE ((UInt32) sizeof(ACDCVidParms)) + + +struct endeavorVidParms { + UInt8 MRegValue; + UInt8 NRegValue; +}; + +typedef struct endeavorVidParms endeavorVidParms; +typedef struct endeavorVidParms *endeavorVidParmsPtr; +typedef struct endeavorVidParms **endeavorVidParmsHdl; + +#define ENDEAVORVIDPARMSSIZE ((UInt32) sizeof(endeavorVidParms)) + + +struct globals { + GammaTablePtr gGammaPtr; + Ptr gBaseAddr; + Ptr gFBBaseAddr; + Boolean gInterruptsEnabled; + Boolean gMonoOnly; + Boolean gLuminanceMode; + Boolean gDirectMode; + UInt16 gNumLines; + UInt16 gRowBytes; + UInt16 gCurrentPage; + UInt32 gBigSlotNum; + UInt8 gMonitorID; + UInt8 gSlotNum; + UInt8 gCurrentMode; + SlotIntQElement qElem; +}; + +typedef struct globals globals; +typedef struct globals *globalsPtr; +typedef struct globals **globalsH; + +#define GLOBALSSIZE ((UInt32) sizeof(globals)) + +//========================================================================== +// Utility routines +//========================================================================== +void RemoveInterruptRoutine(DCtlPtr dce); +void InstallInterruptRoutine(DCtlPtr dce); + +void DoDisableVideo(UInt32 theSlot); + + +/*------------------------------------------------------------------------- +* +* End of Module +* +*-----------------------------------------------------------------------*/ diff --git a/DeclData/DeclVideo/ATI/ATIDrvr.h.idump b/DeclData/DeclVideo/ATI/ATIDrvr.h.idump new file mode 100644 index 0000000..124c75a --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvr.h.idump @@ -0,0 +1 @@ +TEXTMPS \ No newline at end of file diff --git a/DeclData/DeclVideo/ATI/ATIDrvr.h.rdump b/DeclData/DeclVideo/ATI/ATIDrvr.h.rdump new file mode 100644 index 0000000..31fc095 --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvr.h.rdump @@ -0,0 +1,26 @@ +data 'MPSR' (1005) { + $"0009 4D6F 6E61 636F 002D 2D2D 2D2D 2D2D" /* ..Monaco.------- */ + $"2D2D 2D2D 2D2D 2D2D 2D2D 2D0D 2A73 7461" /* -----------.*sta */ + $"7274 0006 0004 003C 0024 026D 02FD 003C" /* rt.....<.$.m...< */ + $"0024 026D 02FD A961 74F1 0000 0A16 0000" /* .$.m...at....... */ + $"0AF8 0000 0878 0100" /* .....x.. */ +}; + +data 'MPSR' (1008) { + $"003C 0024 026D 02FD 003C 0024 026D 02FD" /* .<.$.m...<.$.m.. */ + $"0000 0878 0000 0000 0000 0000 0000" /* ...x.......... */ +}; + +data 'ckid' (128, "Projector") { + $"B325 AE73 3FE5 3230 0004 0000 0000 0000" /* .%.s?.20........ */ + $"0000 A961 C104 A961 74F1 A900 0533 005C" /* ...a...at....3.\ */ + $"1376 0006 0008 0002 2653 7570 6572 4D61" /* .v......&SuperMa */ + $"7269 6F50 726F 6ABA 4465 636C 4461 7461" /* rioProj.DeclData */ + $"BA44 6563 6C56 6964 656F BA41 5449 BA00" /* .DeclVideo.ATI.. */ + $"0E43 6872 6973 2050 6574 6572 7365 6E00" /* .Chris Petersen. */ + $"0132 0009 4154 4944 7276 722E 6800 0000" /* .2..ATIDrvr.h... */ + $"0024 7075 7420 696E 2064 6961 6D6F 6E64" /* .$put in diamond */ + $"2063 6172 6420 7375 7070 6F72 7420 666F" /* card support fo */ + $"7220 544E 540D 00" /* r TNT.. */ +}; + diff --git a/DeclData/DeclVideo/ATI/ATIDrvrImp.c b/DeclData/DeclVideo/ATI/ATIDrvrImp.c new file mode 100644 index 0000000..3a04410 --- /dev/null +++ b/DeclData/DeclVideo/ATI/ATIDrvrImp.c @@ -0,0 +1,1627 @@ +/* + File: ATIDrvrImp.c + + Contains: xxx put contents here xxx + + Written by: xxx put writers here xxx + + Copyright: © 1993 by Apple Computer, Inc., all rights reserved. + + Change History (most recent first): + + <1> 11/5/93 fau first checked in + <1> 10/27/93 fau first checked in + <1> 10/19/93 fau first checked in + +*/ + +/*------------------------------------------------------------------------- +*start +* +*Name: ATIDrvrImp +*Creator: George D. Wilson Jr. +*Date: 3/17/92 +* +*Purpose: Contains the implementations of the Quadra video driver routines. +* +*Category: +*File: ATIDrvrImp.c +* +*Exports: DoGetPages - Returns the number of video pages. +* DoGrayCLUT +* DoCheckMode +* DoGetMode +* DoGetEntries +* DoGetBaseAddr +* DoGetGray +* DoGetInterrupt +* DoGetGamma +* DoGetDefaultMode +* DoVideoReset +* DoSetEntries +* DoSetVideoMode +* DoSetGamma +* DoGrayPage +* DoSetGray +* DoSetInterrupt +* DoDirectSetEntries +* DoSetDefaultMode +* +*Locals: +* +*Detailed: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +* +* Includes +* +*-----------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include +#include + +#include "NubEqu.h" +#include "ATIStdTypes.h" +#include "ATI.h" +#include "ATIDrvr.h" +#include "ATIVideo.h" + +/*------------------------------------------------------------------------- +* +* Imported Variables +* +*-----------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +* +* Imported Procedures +* +*-----------------------------------------------------------------------*/ +extern UInt8 MonitorIDToSpID(UInt8 monitorId); +extern Ptr FindVideoTimingStruct(UInt8 monitorID, UInt8 theSlot); +extern Ptr GetTimingSBlock(UInt8 monitorID, UInt8 videoMode, UInt8 timingSelector, UInt8 ourSlot); +extern void PruneMonitors(UInt8 monitorID, UInt8 theSlot); +extern UInt16 od(UInt8 monitorID, UInt8 videoMode, UInt8 theSlot); +extern UInt16 GetNumLines(UInt8 monitorID, UInt8 videoMode, UInt8 theSlot); +extern UInt16 GetBitDepth(UInt8 monitorID, UInt8 videoMode, UInt8 theSlot); + +extern void DoProgramDAC(ColorSpecPtr ctPtr, UInt16 numEntries, UInt16 start, Boolean indexMode); +extern void DoProgramDACGamma(GammaTablePtr gammaPtr); +extern void DoBuildLinearRamp (ColorSpecPtr ctPtr); +extern void DoGammaCorrectCLUT(UInt16 numEntries, ColorSpecPtr orgCLUTPtr, + ColorSpecPtr corrCLUTPtr,GammaTablePtr gammaPtr); +extern void DoEnableVideo(UInt32 theSlot); +extern void DoDisableVideo(UInt32 theSlot); + +extern void DoProgramTiming (UInt32 slotNum, Ptr baseAddr, UInt8 monitorID, + UInt8 videoMode, UInt8 ourSlot, UInt16 rowBytes, + Boolean enableInterrupts); + +/*------------------------------------------------------------------------- +* +* Local Typedefs and Defines +* +*-----------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +* +* Exported Variables +* +*-----------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +* +* Exported Procedures +* +*-----------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +* +* Local Variables +* +*-----------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +* +* Beginning of Procedure Definitions +* +*-----------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +*start +* +*Name: DoGrayCLUT +*Creator: George D. Wilson Jr. +*Date: 4/14/92 +* +*Purpose: Fills the CLUT with a gray color. +* +*Category: +*File: ATIDrvrImp.c +* +*Calls: +* +*Called By: +* +*Entry: +* +*Alters: +* +*Exit: +* +*Detailed: +* +*Algorithm: +* +*Note: +* +*History: +* +* Date Programmer Modification +* -------- ---------- ----------------------------------------- +* +*stop +*-----------------------------------------------------------------------*/ +void DoGrayCLUT () +{ + + UInt32 i; + UInt8 *clutAddrReg = 0; + UInt8 *clutData; +// UInt8 dummy; + + unsigned long data; + +// DebugStr("\pDoGrayCLUT"); + + IOLongWrite(0xF2800000, (0x2 << 12) | 4); + *(unsigned char *)(0xF2C00000) = 0x3; + PerformPCIHack(); + + IOLongWrite(0xF2800000, (0x2 << 12)); + data = LByteSwap(*(unsigned long *)0xF2C00000); // Get Vendor ID + + if ( data == (0x1002 | (0x4158 << 16)) ) { // look for ATI + clutAddrReg = (UInt8 *) kDAC_W_INDEX; + clutData = (UInt8 *) kDAC_DATA; // Point to data register + *clutAddrReg = 0; // Point to first entry + WaitForVBL(); // Wait for blanking + for ( i = 0; i < kNumCLUTEntries; i++ ) { + *clutData = kGrayCLUTValue; + PerformPCIHack(); + *clutData = kGrayCLUTValue; + PerformPCIHack(); + *clutData = kGrayCLUTValue; + PerformPCIHack(); + } + } + else { +// if ( data == (0x100E | (0x9001 << 16)) ) { // look for Diamond + clutAddrReg = (UInt8 *)(0xF20003C8); // kRamWrite + clutData = (UInt8 *)(0xF20003C9); // kPaletteData + *clutAddrReg = 0; // Point to first entry + WaitForVBL(); // Wait for blanking + for ( i = 0; i < kNumCLUTEntries; i++ ) { + *clutData = (unsigned char)i; + PerformPCIHack(); + *clutData = (unsigned char)i; + PerformPCIHack(); + *clutData = (unsigned char)i; + PerformPCIHack(); + } + } + + IOLongWrite(0xF2800000, (0x2 << 12) | 4); + *(unsigned char *)(0xF2C00000) = 0x2; + PerformPCIHack(); + +} /* End of Do