; ; File: PSCEqu.a ; ; Contains: Equates for accessing the Peripheral Subsystem Controller (PSC) ; ; Written by: Mark A. Law ; ; Copyright: © 1992-1993 by Apple Computer, Inc. All rights reserved. ; ; Change History (most recent first): ; ; 6/14/93 kc Roll in Ludwig. ; 4/13/93 chp Cleaned up, reorganized, and generally munged to a greater ; degree than necessary. Unused fields of PSC_INT_TBL have been ; removed since the changes in were only to support the ; (defunct) DMA Manager. ; 3/16/93 chp Remove the definition of the PSCIntTbl lomem which has been ; superseded by an equivalent field in ExpandMem. ; 2/24/93 chp Updated UTSC offsets to reflect the correct values for the final ; PSC silicon and added a generic equate to the beginning of the ; 64-bit register. ; 1/23/93 mal Added DSP Level 2 interrupt handler & parm placeholders to PSC ; interrupt table. ; 11/19/92 mal Changed some MACE Enet DMA channel equs. ; 8/13/92 chp Added equates for SCCATX DMA channel number 6 (PSC2). ; 6/21/92 ejb Adding equate L5 ("Level 5") for the RTDrvr. ; 6/21/92 ejb Add equate DSPTOHOST as an alias for the equate DSP (PSC Lvl5 ; irq 0). The latter's name conflicts with RTDrvr equates. ; 5/24/92 RB Changed the DMA flush bit name to avoid a conflict with the ; Sound Manager equates. From FLUSH to DMAFLUSH. ; 4/2/92 mal Added ifdef to ensure we only included once per asm. ; 4/2/92 mal Updated PSCIntTbl to real lowmem location. ; 2/28/92 chp Modified structure of PSCIntTbl and changed “IRE” references to ; “IER” (interrupt enable register) for consistency with ; documentation and other parts of the source. ; 2/21/92 mal Removed sound equates. ; 2/14/92 mal Removed use of PSCBase, all registers defined as offsets. ; 1/24/92 mal Added temporary PSCIntTbl lowmem global. ; IF &TYPE('__IncludingPSCEqu__') = 'UNDEFINED' THEN __IncludingPSCEqu__ SET 1 ; PSC Interrupt Register and Interrupt Enable Register offsets ; level 2 registers - see HardwarePrivateEqu.a ; level 3 register offsets L3IR EQU $130 ; Level 3 Interrupt Register L3IER EQU $134 ; Level 3 Interrupt Enable Register ; level 3 bit offsets, both irq's and enable's MACE EQU 0 L3B7 EQU 7 ; "or" of all irq's, "sense" bit for enables ; level 4 register offsets L4IR EQU $140 ; Level 4 Interrupt Register L4IER EQU $144 ; Level 4 Interrupt Enable Register ; level 4 bit offsets, both irq's and enable's SNDSTAT EQU 0 L4SCCA EQU 1 L4SCCB EQU 2 DMA EQU 3 L4B7 EQU 7 ; "or" of all irq's, "sense" bit for enables ; level 5 register offsets L5 EQU 5 ; Level 5 interrupt L5IR EQU $150 ; Level 5 Interrupt Register L5IER EQU $154 ; Level 5 Interrupt Enable Register ; level 5 bit offsets, both irq's and enable's DSP EQU 0 DSPTOHOST EQU 0 FRMOVRN EQU 1 L5B7 EQU 7 ; "or" of all irq's, "sense" bit for enables ; level 6 register offsets L6IR EQU $160 ; Level 6 Interrupt Register L6IER EQU $164 ; Level 6 Interrupt Enable Register ; level 6 bit offsets, both irq's and enable's L660HZ EQU 0 L6SCCA EQU 1 L6SCCB EQU 2 L6B7 EQU 7 ; "or" of all irq's, "sense" bit for enables ; Universal Time Stamp Counter Register offsets UTSC EQU $300 LSUTSC EQU $300 ; least significant lword MSUTSC EQU $304 ; most significant lword PSCTEST EQU $400 PSC_BERRIE EQU $800 ; Bus Error Interrupt Enable (byte) BERRIE EQU 0 ; Bus Error Interrupt Enable bit offset PSC_ISR EQU $804 ; Interrupt Status Register (long) ; PSC DMA Control Register offsets SCSI_CNTL EQU $C00 ; Channel 0 control register (word) PSC_MACE_RECV_CNTL EQU $C10 ; Channel 1 control register PSC_MACE_XMIT_CNTL EQU $C20 ; Channel 2 control register FDC_CNTL EQU $C30 ; Channel 3 control register SCCA_CNTL EQU $C40 ; Channel 4 control register SCCB_CNTL EQU $C50 ; Channel 5 control register SCCATX_CNTL EQU $C60 ; Channel 6 control register ; PSC DMA Set Register offsets PSC_DMA_CHNL RECORD 0 ; PSC DMA Channel record for use Addr Addr0 DS.L 1 ; with Channel base equ's below, Cnt Cnt0 DS.L 1 ; SCSI_CHNL, MACE_RECV_CHNL, etc. CmdStat CmdStat0 DS.W 1 ORG *+6 Addr1 DS.L 1 ; 32 bits Cnt1 DS.L 1 ; 32 bits CmdStat1 DS.W 1 ; 16 bits ORG *+6 ENDR SCSI EQU $1000 ; Channel 0 base SCSI_ADDR0 EQU $1000 ; Register Set 0 address register SCSI_CNT0 EQU $1004 ; Register Set 0 count register SCSI_CMDSTAT0 EQU $1008 ; Register Set 0 command/status register SCSI_ADDR1 EQU $1010 ; Register Set 1 address register SCSI_CNT1 EQU $1014 ; Register Set 1 count register SCSI_CMDSTAT1 EQU $1018 ; Register Set 1 command/status register PSC_MACE_RECV EQU $1020 ; Channel 1 base MACE_RECV_ADDR0 EQU $1020 ; Register Set 0 address register MACE_RECV_CNT0 EQU $1024 ; Register Set 0 count register MACE_RECV_CMDSTAT0 EQU $1028 ; Register Set 0 command/status register MACE_RECV_ADDR1 EQU $1030 ; Register Set 1 address register MACE_RECV_CNT1 EQU $1034 ; Register Set 1 count register MACE_RECV_CMDSTAT1 EQU $1038 ; Register Set 1 command/status register PSC_MACE_XMIT EQU $1040 ; Channel 2 base MACE_XMIT_ADDR0 EQU $1040 ; Register Set 0 address register MACE_XMIT_CNT0 EQU $1044 ; Register Set 0 count register MACE_XMIT_CMDSTAT0 EQU $1048 ; Register Set 0 command/status register MACE_XMIT_ADDR1 EQU $1050 ; Register Set 1 address register MACE_XMIT_CNT1 EQU $1054 ; Register Set 1 count register MACE_XMIT_CMDSTAT1 EQU $1058 ; Register Set 1 command/status register FDC EQU $1060 ; Channel 3 base FDC_ADDR0 EQU $1060 ; Register Set 0 address register FDC_CNT0 EQU $1064 ; Register Set 0 count register FDC_CMDSTAT0 EQU $1068 ; Register Set 0 command/status register FDC_ADDR1 EQU $1070 ; Register Set 1 address register FDC_CNT1 EQU $1074 ; Register Set 1 count register FDC_CMDSTAT1 EQU $1078 ; Register Set 1 command/status register SCCA EQU $1080 ; Channel 4 base SCCA_ADDR0 EQU $1080 ; Register Set 0 address register SCCA_CNT0 EQU $1084 ; Register Set 0 count register SCCA_CMDSTAT0 EQU $1088 ; Register Set 0 command/status register SCCA_ADDR1 EQU $1090 ; Register Set 1 address register SCCA_CNT1 EQU $1094 ; Register Set 1 count register SCCA_CMDSTAT1 EQU $1098 ; Register Set 1 command/status register SCCB EQU $10A0 ; Channel 5 base SCCB_ADDR0 EQU $10A0 ; Register Set 0 address register SCCB_CNT0 EQU $10A4 ; Register Set 0 count register SCCB_CMDSTAT0 EQU $10A8 ; Register Set 0 command/status register SCCB_ADDR1 EQU $10B0 ; Register Set 1 address register SCCB_CNT1 EQU $10B4 ; Register Set 1 count register SCCB_CMDSTAT1 EQU $10B8 ; Register Set 1 command/status register SCCATX EQU $10C0 ; Channel 6 base SCCATX_ADDR0 EQU $10C0 ; Register Set 0 address register SCCATX_CNT0 EQU $10C4 ; Register Set 0 count register SCCATX_CMDSTAT0 EQU $10C8 ; Register Set 0 command/status register SCCATX_ADDR1 EQU $10D0 ; Register Set 1 address register SCCATX_CNT1 EQU $10D4 ; Register Set 1 count register SCCATX_CMDSTAT1 EQU $10D8 ; Register Set 1 command/status register ; PSC DMA Channel Register Bits ; DMA Channel Command/Status Register bit offsets IF EQU 8 DIR EQU 9 TERMCNT EQU 10 ENABLED EQU 11 IE EQU 12 ; DMA Channel Control Register bit offsets CIRQ EQU 8 DMAFLUSH EQU 9 PAUSE EQU 10 SWRESET EQU 11 CIE EQU 12 BERR EQU 13 FROZEN EQU 14 SENSE EQU 15 ; PSC Interrupt Handler Table Template (see InterruptHandlers.a) ; ; This table contains address, parm entries for the real handlers for ; interrupt levels 3, 4, 5, and 6. Individual drivers are responsible ; for installing themselves and an optional parameter into the table. ; ; An interrupt handler is dispatched with its parameter in A1. ; ; During Cyclone development, the PSCIntTbl lomem ($1FC0) pointed to this table. ; Now the pointer is in ExpandMem (emDMADispGlobs). PSC_INT_TBL record 0,increment ; device interrupt handlers - levels 3-6 ; MACEhndlr ds.l 1 ; MACE int. handler MACEparm ds.l 1 SNDSTAThndlr ds.l 1 ; Level 4 SNDSTAT int. handler SNDSTATparm ds.l 1 L4SCCAhndlr ds.l 1 ; Level 4 SCCA int. handler L4SCCAparm ds.l 1 L4SCCBhndlr ds.l 1 ; Level 4 SCCB int. handler L4SCCBparm ds.l 1 DSPhndlr ds.l 1 ; Level 5 DSP int. handler DSPparm ds.l 1 FRMOVRNhndlr ds.l 1 ; Level 5 FRMOVRN int. handler FRMOVRNparm ds.l 1 L660HZhndlr ds.l 1 ; Level 6 60 Hz int. handler L660HZparm ds.l 1 L6SCCAhndlr ds.l 1 ; Level 6 SCCA int. handler L6SCCAparm ds.l 1 ; (On Mac OS, SCC ints at Level 4) L6SCCBhndlr ds.l 1 ; Level 6 SCCB int. handler L6SCCBparm ds.l 1 ; (On Mac OS, SCC ints at Level 4) ; DMA interrupt handlers - level 4 ; DMA_hndlrs EQU * SCSIhndlr ds.l 1 ; SCSI DMA int. handler SCSIparm ds.l 1 MACE_RECVhndlr ds.l 1 ; Mace Receive DMA int. handler MACE_RECVparm ds.l 1 MACE_XMIThndlr ds.l 1 ; Mace Transmit Done DMA int. handler MACE_XMITparm ds.l 1 FDChndlr ds.l 1 ; FDC DMA int. handler FDCparm ds.l 1 SCCAhndlr ds.l 1 ; SCCA DMA int. handler SCCAparm ds.l 1 SCCBhndlr ds.l 1 ; SCCB DMA int. handler SCCBparm ds.l 1 SCCATXhndlr ds.l 1 ; SCCATX DMA int. handler SCCATXparm ds.l 1 ; For Sound compatibility with older systems, the Level 5 DSP Interrupt handler ; installs a “deferred” handler/parm here. PSCServiceInt will run this handler ; if one exists and it’s about to RTE to level 0 or 1. ; DSPL2hndlr ds.l 1 ; ptr to head of queue DSPL2parm ds.l 1 ; ptr to tail of queue PSC_INT_TBL_SZ equ * endr ENDIF ; including __IncludingPSCEqu__