sys7.1-doc-wip/Drivers/IOP/IOPDefs.aii
2019-07-27 22:37:48 +08:00

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;EASE$$$ READ ONLY COPY of file “IOPDefs.aii”
; 1.2 CCH 07/08/1989 Added EASE comments to file.
;•1.1 GGD 06/15/1989 Updated to use equates for the latest rev of the IOP chip,
; re-formated tab stops in source.
; 1.0 CCH 11/ 9/1988 Adding to EASE.
; END EASE MODIFICATION HISTORY
macro
assert &boolExpr
if not(&Eval(&boolExpr)) then
aerror &concat('Assertion Failed - ',&boolExpr)
endif
endm
; 65C02 definitions
pswC equ %00000001 ; carry bit
pswZ equ %00000010 ; zero bit
pswI equ %00000100 ; interrupt bit
pswD equ %00001000 ; decimal bit
pswB equ %00010000 ; break bit
psw5 equ %00100000 ; bit 5 unused
pswV equ %01000000 ; overflow bit
pswN equ %10000000 ; negative bit
StackPage equ $0100 ; page 1 is the stack
vNMI equ $FFFA ; non-maskable interrupt
vRESET equ $FFFC ; reset vector
vINT equ $FFFE ; interrupt vector
; IOP Hardware offsets
IOBase equ $F000 ; base of I/O space
; TIMER Hardware Control
TimerCounterL equ IOBase+$10 ; (RW) Timer low counter (latch on write)
TimerCounterH equ IOBase+$11 ; (RW) Timer high counter (load on write)
TimerLatchL equ IOBase+$12 ; (RW) Timer low latch
TimerLatchH equ IOBase+$13 ; (RW) Timer high latch
; DMA Hardware Control
DMA1Control equ IOBase+$20 ; (RW) DMA channel 1 control
DMAEN1 equ %00000001 ; enable DMA channel 1
DREQ1 equ %00000010 ; DMA request 1 active
DMADIR1 equ %00000100 ; transfer I/O to RAM
DEN1ON2 equ %00001000 ; start DMA 1 after DMA 2 complete
IOA1 equ %00010000 ; DMA I/O address
DMA1RAMAddressL equ IOBase+$21 ; (RW) DMA channel 1 RAM address low byte
DMA1RAMAddressH equ IOBase+$22 ; (RW) DMA channel 1 RAM address high byte
DMA1XferCountL equ IOBase+$23 ; (RW) DMA channel 1 transfer count low byte
DMA1XferCountH equ IOBase+$24 ; (RW) DMA channel 1 transfer count high byte
DMA2Control equ IOBase+$28 ; (RW) DMA channel 2 control
DMAEN2 equ %00000001 ; enable DMA channel 2
DREQ2 equ %00000010 ; DMA request 2 active
DMADIR2 equ %00000100 ; transfer I/O to RAM
DEN2ON1 equ %00001000 ; start DMA 2 after DMA 1 complete
IOA2 equ %00010000 ; DMA I/O address
DMA2RAMAddressL equ IOBase+$29 ; (RW) DMA channel 2 RAM address low byte
DMA2RAMAddressH equ IOBase+$2A ; (RW) DMA channel 2 RAM address high byte
DMA2XferCountL equ IOBase+$2B ; (RW) DMA channel 2 transfer count low byte
DMA2XferCountH equ IOBase+$2C ; (RW) DMA channel 2 transfer count high byte
; Miscelaneous Hardware Control
SCCControlReg equ IOBase+$30 ; (RW) SCC control register
BYPASS equ %00000001 ; Host processor controls SCC/ISM
SCCISM equ %00000010 ; ISM port
* equ %00000100 ; unused
RTXCA equ %00001000 ; selects SCC channel A clock source
RTXCB equ %00100000 ; selects SCC channel B clock source
GPOUT1 equ %10000000 ; general purpose output 1
RTXC3MHz equ %00 ; 3.6864MHz
RTXCDPCLK equ %01 ; DPCLK/10
RTXCDPLLOut equ %10 ; Digital phase locked loop output
RTXCGPI equ %11 ; GPIA or GPIB
IOControlReg equ IOBase+$31 ; (RW) I/O Control register
IODurationCount equ %00000001 ; I/O duration count
IODelayCount equ %00010000 ; I/O delay count
TimerDPLLctl equ IOBase+$32 ; (RW) Timer/DPLL control
CONT equ %00000001 ; timer continuous mode
GPOUT0 equ %00000010 ; general purpose output 0
GPIN0 equ %00000100 ; general purpose input 0
GPIN1 equ %00001000 ; general purpose input 1
DPLL1EN equ %00010000 ; DPLL 1 enabled
CRSNS1 equ %00100000 ; carrier present on RXDA
DPLL2EN equ %01000000 ; DPLL 2 enabled
CRSNS2 equ %10000000 ; carrier present on RXDB
InterruptMask equ IOBase+$33 ; (RW) Interrupt Mask Register
DMA1ENI equ %00000010 ; enable DMA channel 1 interrupts
DMA2ENI equ %00000100 ; enable DMA channel 2 interrupts
SCCENI equ %00001000 ; enable SCC interrupts
HSTENI equ %00010000 ; enable interrupts from the host processor
TMRENI equ %00100000 ; enable timer interrupts
InterruptReg equ IOBase+$34 ; (RW) Interrupt Register
DMA1INT equ %00000010 ; DMA channel 1 interrupt
DMA2INT equ %00000100 ; DMA channel 2 interrupt
SCCINT equ %00001000 ; SCC interrupt
HSTINT equ %00010000 ; interrupt from the host processor
TMRINT equ %00100000 ; timer interrupt
HostControl equ IOBase+$35 ; (RW) Host Register
INTHST0 equ %00000100 ; host interrupt 0 active
INTHST1 equ %00001000 ; host interrupt 1 active
MsgCompletedINT equ INTHST0 ; indicates message in MessageCompleted state
NewMsgSentINT equ INTHST1 ; indicates message in NewMessageSent state
; IOP Shared Memory Addresses
RCVMsgBase equ $0200 ; receive message page
RCVMsgMax equ RCVMsgBase+$00 ; Highest receive message number
RCVMsg1State equ RCVMsgBase+$01 ; receive message 1 state
RCVMsg2State equ RCVMsgBase+$02 ; receive message 2 state
RCVMsg3State equ RCVMsgBase+$03 ; receive message 3 state
RCVMsg4State equ RCVMsgBase+$04 ; receive message 4 state
RCVMsg5State equ RCVMsgBase+$05 ; receive message 5 state
RCVMsg6State equ RCVMsgBase+$06 ; receive message 6 state
RCVMsg7State equ RCVMsgBase+$07 ; receive message 7 state
PatchReq equ RCVMsgBase+$1F ; Host wants to patch IOP code
RCVMsg1Data equ RCVMsgBase+$20 ; receive message 1 data
RCVMsg2Data equ RCVMsgBase+$40 ; receive message 2 data
RCVMsg3Data equ RCVMsgBase+$60 ; receive message 3 data
RCVMsg4Data equ RCVMsgBase+$80 ; receive message 4 data
RCVMsg5Data equ RCVMsgBase+$A0 ; receive message 5 data
RCVMsg6Data equ RCVMsgBase+$C0 ; receive message 6 data
RCVMsg7Data equ RCVMsgBase+$E0 ; receive message 7 data
XMTMsgBase equ $0300 ; transmit message page
XMTMsgMax equ XMTMsgBase+$00 ; Highest transmit message number
XMTMsg1State equ XMTMsgBase+$01 ; transmit message 1 state
XMTMsg2State equ XMTMsgBase+$02 ; transmit message 2 state
XMTMsg3State equ XMTMsgBase+$03 ; transmit message 3 state
XMTMsg4State equ XMTMsgBase+$04 ; transmit message 4 state
XMTMsg5State equ XMTMsgBase+$05 ; transmit message 5 state
XMTMsg6State equ XMTMsgBase+$06 ; transmit message 6 state
XMTMsg7State equ XMTMsgBase+$07 ; transmit message 7 state
Alive equ XMTMsgBase+$1F ; IOP is alive flag
XMTMsg1Data equ XMTMsgBase+$20 ; transmit message 1 data
XMTMsg2Data equ XMTMsgBase+$40 ; transmit message 2 data
XMTMsg3Data equ XMTMsgBase+$60 ; transmit message 3 data
XMTMsg4Data equ XMTMsgBase+$80 ; transmit message 4 data
XMTMsg5Data equ XMTMsgBase+$A0 ; transmit message 5 data
XMTMsg6Data equ XMTMsgBase+$C0 ; transmit message 6 data
XMTMsg7Data equ XMTMsgBase+$E0 ; transmit message 7 data
; IOP Message States
Idle equ 0 ; message buffer idle
NewMessageSent equ 1 ; new message arrived
MessageReceived equ 2 ; message being processed
MessageCompleted equ 3 ; request completed
; Block Copy Message Assignments
BCxmtState equ XMTMsg1State
BCxmtData equ XMTMsg1Data
; Block Copy Driver request format
bcIOPtoHOST equ $00
bcHOSTtoIOP equ $01
bcCompare equ $02
bcReqCmd equ BCxmtData+$00 ; (byte) Request Kind
bcReqByteCount equ BCxmtData+$02 ; (word) transfer byte count
bcReqHostAddr equ BCxmtData+$04 ; (long) host RAM address
bcReqIopAddr equ BCxmtData+$08 ; (word) IOP RAM address
bcReqCompRel equ BCxmtData+$0A ; (byte) Compare Relation (output)
; TMPB Time constants (1 tick = 256 clocks @1.9584MHz = 130.71895 uSec)
TMPB1second equ 7650 ; 1 second
TMPB100ms equ TMPB1second/10 ; 100 milliseconds
TMPB10ms equ TMPB1second/100 ; 10 milliseconds
TMPB1ms equ TMPB1second/1000 ; 1 millisecond