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128 lines
3.7 KiB
Plaintext
128 lines
3.7 KiB
Plaintext
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; File: MC680x0.a
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;
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; Contains: Equates for dealing with the 680x0 chips
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;
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; Written by: Paul Wolf
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;
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; Copyright: © 1991 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <1> 10/24/91 SAM Rolled in Regatta file.
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; <0> 8/3/91 SAM (pdw) Created needed for BusErrHandler in SCSIMgrHW96.a.
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;
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;__________________________________________________________________________
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;****** 68040 *******
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; Transfer Type
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TT_Normal EQU $0 ; normal access
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TT_MOVE16 EQU $1 ; MOVE16 Access
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TT_Alternate EQU $2 ; Alternate access
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TT_Acknowledge EQU $3 ; Acknowledge access
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; Transfer Modifier
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TM_Data_Cache_Push EQU $0 ; Data cache push
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TM_User_Data EQU $1 ; User Data Access
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TM_User_Code EQU $2 ; User Code Access
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TM_MMU_DataTable EQU $3
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TM_MMU_CodeTable EQU $4
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TM_Sup_Data EQU $5 ; Supervisor Data Access
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TM_Sup_Code EQU $6 ; Supervisor Code Access
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; Transfer Type and Transfer Modifier combination
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NORMAL_USER_DATA EQU ((TT_Normal<<3) | TM_User_Data)
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NORMAL_USER_CODE EQU ((TT_Normal<<3) | TM_User_Code)
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MOVE16_USER_DATA EQU ((TT_MOVE16<<3) | TM_User_Data)
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MOVE16_SUPV_DATA EQU ((TT_MOVE16<<3) | TM_Sup_Data)
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NORMAL_SUPV_DATA EQU ((TT_Normal<<3) | TM_Sup_Data)
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NORMAL_SUPV_CODE EQU ((TT_Normal<<3) | TM_Sup_Code)
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; Transfer Size
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;WB_CHAR EQU $1 ; byte access
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;WB_SHORT EQU $2 ; word access
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;WB_LONG EQU $0 ; long word access
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;WB_LINE EQU $3 ; line access
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; MMUSR Bit Mask Definitions
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MMUSR_R EQU $00000001 ; page resident
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MMUSR_T EQU $00000002 ; TT hit
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MMUSR_W EQU $00000004 ; Write-Protect page
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MMUSR_M EQU $00000010 ; Modified Page
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MMUSR_CM EQU $00000060 ; Page Cache Mode
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MMUSR_S EQU $00000080 ; Supervisor Protection Page
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MMUSR_UPA EQU $00000300 ; User Page Attribute
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MMUSR_G EQU $00000400 ; Global Page
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MMUSR_B EQU $00000800 ; Physical Bus error Page
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MMUSR_PG EQU $fffff000 ; Page Base Address
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;
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; MC68040 Special Status Word (SSW)
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;
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bCP EQU 15 ; FP Post Exception Pending
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bCU EQU 14 ; Unimplemented FP Inst. Exception pending
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bCT EQU 13 ; Trace Exception pending
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bCM EQU 12 ; MOVEM Instruction Execution pending
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bMA EQU 11 ; Misaligned Access
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bATC EQU 10 ; ATC Fault
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bLK EQU 9 ; Locked Transfer
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bRW EQU 8 ; Read/Write
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SIZE_MSK EQU $60 ; transfer size
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TT_MSK EQU $18 ; transfer type
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TM_MSK EQU $07 ; transfer modifier
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TTTM_MSK EQU TT_MSK+TM_MSK ; transfer type/modifier
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; Transfer Size
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WB_BYTE EQU $1<<5 ; byte access
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WB_WORD EQU $2<<5 ; word access
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WB_LONG EQU $0<<5 ; long word access
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WB_LINE EQU $3<<5 ; line access
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;
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; MC68040 WriteBack Status Word (WBSW)
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;
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bVALID EQU 7 ; Valid
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;SIZE_MSK, TT_MSK, TM_MSK, TTTM_MSK same as SSW definitions
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AEXFrameType EQU $07 ; Access Error Exception Stack Frame type value
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shortBEXFrameType EQU $0A ; Short bus cycle fault stack frame (020/030)
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shortBEXFrameSize EQU 16*2 ; size
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;
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; Access Error Exception Stack Frame (7) Definition
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;
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AEXFrame RECORD 0, INCREMENT
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xSR ds.w 1 ; Status Register
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xPC ds.l 1 ; Program Counter
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FrameType ; =7 for Access Error Exception
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VectorOffset ds.w 1 ; Vector Offset
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EffAddr ds.l 1 ; Effective Address
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SSW ds.w 1 ; Special Status Word
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WB3S ds.w 1 ; Writeback 3 Status
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WB2S ds.w 1 ; Writeback 2 Status
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WB1S ds.w 1 ; Writeback 1 Status
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FaultAddr ds.l 1 ; Fault Address
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WB3A ds.l 1 ; Writeback 3 Address
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WB3D ds.l 1 ; Writeback 3 Data
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WB2A ds.l 1 ; Writeback 2 Address
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WB2D ds.l 1 ; Writeback 2 Data
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WB1A ds.l 1 ; Writeback 1 Address
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WB1D ; Writeback 1 Data
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PD0 ds.l 1 ; Push Data 0
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PD1 ds.l 1 ; Push Data 1
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PD2 ds.l 1 ; Push Data 2
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PD3 ds.l 1 ; Push Data 3
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AEXFrameSize EQU * ; size of 040 AE Exception Frame
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ENDR
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