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416 lines
16 KiB
Plaintext
416 lines
16 KiB
Plaintext
;
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; File: I2C.a
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;
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; Contains: Routines for reading and writing I-squared-C serial ROMS.
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;
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; Written by:
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;
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; Copyright: © 1993 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <K2> 5/20/93 EH Fixed up comments.
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; <1> 5/20/93 EH first checked in
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;
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;
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;———————————————————————————————————————————————————————————————————————————————————————— <5> HJR
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;
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; Routine: X24c01aGetID
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;
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; This routine talks to the X24c01a Xicor Serial ROM part to get the Ethernet ID
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; address stored therein. The X24c01a belongs to a class of parts whose interface
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; is the standard I-squared-C (I2C) inteface, consististing of two signals, a clock
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; and a bi-directional data signal.
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;
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; On Blackbird, the clock signal is hooked up to PB0 of the VIA 1 cell inside Whitney.
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; the clock signal is hooked up to PB1 of the VIA 1 cell inside Whitney.
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;
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; Since there are an increasing number of I2C ROMs in Macintosh products, we may
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; want to generalize this solution at some point. But for now...
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;
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;———————————————————————————————————————————————————————————————————————————————————————— <5> HJR
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print off
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load 'StandardEqu.d'
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include 'HardwarePrivateEqu.a'
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include 'i2cEqu.a'
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print on
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machine MC68040
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X24c01aGetID PROC EXPORT
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* bra.s BBirdGetENetID
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: BBirdGetENetID
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;
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; Inputs: a0.l - points to memory in which to place the ROM ID bytes
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;
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; Outputs: a0.l - points to valid ROM ID bytes
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; or points to zeroes
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;
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; Trashes:
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;
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; Function: Gets the EtherNet ID from the Serial EtherNet ID ROM.
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;————————————————————————————————————————————————————————————————————————————————————————
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BBirdGetENetID
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ENetregs REG d0-d7/a5
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movem.l ENetregs, -(sp)
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moveq #retryCnt, d3 ; set the retry count
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move.l VIA, a5 ; point to the via
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@ReadCmdStart
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bsr.w SendStart ; send Start Condition
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move.b #$A0, d4 ; send slave address for write
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bsr.w SendByte
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bsr.w ReceiveAck ; get Acknowledge
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beq.s @sendWordAddr ; Ack OK? then go on
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@error
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move.l a1, a0 ; restore our pointer
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cmpi.w #WereLosers, d0 ; are we totally dead?
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beq.s @exit ; totally dead, so exit with ID = 0
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dbra d3, @ReadCmdStart ; retry if non-zero retry count
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bra.s @exit ; retries exhausted, so punt with ID = 0
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@sendWordAddr
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moveq #0, d4 ; send read addr = 0
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bsr.w SendByte
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bsr.w ReceiveAck ; get Acknowledge
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bne.s @error ; Ack OK? then go on
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@sendSlaveAddr
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bsr.w SendStart ; send another Start Condition
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move.b #$A1, d4 ; send slave address for read
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bsr.w SendByte
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bsr.w ReceiveAck ; get Acknowledge
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bne.s @error
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@read
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move.l a0, a1 ; save our pointer
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moveq #8-1, d1 ; get 8 bytes
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@byteLoop
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bsr.w GetByte ; get a byte
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bsr.w SendAck ; send acknowledge
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move.b d4, (a0)+ ; save it
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dbra d1, @byteLoop
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move.l a1, a0 ; restore our pointer
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@exit bsr.w SendStop
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movem.l (sp)+, ENetregs
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rts
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: BBirdSetENetID
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;
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; Inputs: a0.l - points to ROM ID in memory to send to ROM
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;
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; Outputs:
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;
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; Trashes:
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;
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; Function: Sets the EtherNet ID for the Serial EtherNet ID ROM.
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;————————————————————————————————————————————————————————————————————————————————————————
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BBirdSetENetID
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movem.l ENetregs, -(sp)
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moveq #retryCnt, d3 ; set the retry count
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move.l VIA, a5 ; point to the via
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moveq #2-1, d6 ; page cnt: two pages = eight bytes
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moveq #0, d7 ; write address start
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@PageWriteStart
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move.l a0, a1 ; save our pointer
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bsr.s SendStart ; send Start Condition
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move.b #$A0, d4 ; send slave address for write
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bsr.w SendByte
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bsr.w ReceiveAck ; get Acknowledge
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beq.s @sendWordAddr ; Ack OK? then go on
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@error
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move.l a1, a0 ; restore our pointer
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bsr.s SendStop ; stop the music
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cmpi.w #WereLosers, d0 ; are we totally dead?
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beq.s @exit ; totally dead, so exit with ID = 0
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dbra d3, @PageWriteStart ; retry if non-zero retry count
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bra.s @exit ; retries exhausted, so punt with ID = 0
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@sendWordAddr
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move.l d7, d4 ; starting write addr for this page
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bsr.w SendByte
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bsr.w ReceiveAck ; get Acknowledge
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bne.s @error ; Ack OK? then go on
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@write
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moveq #4-1, d1 ; send 4 bytes
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@byteLoop move.b (a0)+, d4 ; get byte to send
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bsr.s SendByte ; send it
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bsr.w ReceiveAck ; wait for acknowledge
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bne.s @error ; punt on error
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dbra d1, @byteLoop ; loop thru page bytes
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bsr.s SendStop ; stop the music
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bsr.w Wait10ms ; wait for ROM's internal write cycle
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addq.w #4, d7 ; bump write addr to next page
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dbra d6, @PageWriteStart ; loop thru 2 pages = eight bytes
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move.l a1, a0 ; restore our pointer
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@exit movem.l (sp)+, ENetregs
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rts
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: SendStart
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;
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; Inputs: a5.l - points to VIA
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;
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; Outputs: None
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;
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; Trashes: d2
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;
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; Function: Sends Start condition for transaction to Ethernet ID ROM.
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; Start indicated by HIGH to LOW Data transition while Clock is HIGH.
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;————————————————————————————————————————————————————————————————————————————————————————
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SendStart
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bset.b #vENetIDData,vDIRB(a5) ; set Data direction OUT
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bset.b #vENetIDData, (a5) ; must init data ...
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bset.b #vENetIDClk, (a5) ; ... before clock
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bsr.w Wait10 ; wait start-setup time
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bclr.b #vENetIDData, (a5) ; set the start condition
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bsr.w Wait10 ; wait start-hold time
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bclr.b #vENetIDClk, (a5) ; and drop the clock
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rts
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: SendStop
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;
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; Inputs: a5.l - points to VIA
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;
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; Outputs: None
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;
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; Trashes: d2
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;
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; Function: Sends Start condition for transaction to Ethernet ID ROM.
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; Data must be LOW coming in (we have just ack'd).
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; Stop indicated by LOW to HIGH Data transition while Clock is HIGH.
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;————————————————————————————————————————————————————————————————————————————————————————
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SendStop
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bset.b #vENetIDData,vDIRB(a5) ; set Data direction OUT
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bset.b #vENetIDClk, (a5) ; set clock HIGH
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bsr.w Wait10 ; wait stop-setup time
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bset.b #vENetIDData, (a5) ; set the stop condition
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bsr.w Wait10 ; wait stop-hold time
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rts
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: ClockBit
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;
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; Inputs: a5.l - points to VIA
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;
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; Outputs: d5.b - level of rcv bit when clock is high
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;
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; Trashes: d2
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;
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; Function: Pulse high.
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; Turns off interrupts so we don't screw up.
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;————————————————————————————————————————————————————————————————————————————————————————
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ClockBit
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move sr, -(sp) ; save status register
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ori.w #hiIntMask, sr ; turn off interrupts
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bsr.w Wait10 ; wait some more
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bset.b #vENetIDClk, (a5) ; clock goes HIGH
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btst.b #vENetIDData, (a5) ; get the bit
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sne.b d5 ;
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bclr.b #vENetIDClk, (a5) ; clock goes LOW
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bsr.w Wait10 ; wait some more
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move (sp)+, sr ; restore interrupts
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rts
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: SendByte
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;
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; Inputs: d4.b - byte to send
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;
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; Outputs:
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;
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; Trashes:
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;
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; Function: Sends a byte to the EtherNet ID ROM
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;————————————————————————————————————————————————————————————————————————————————————————
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SendByte
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sendregs REG d0-d3/d5
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movem.l sendregs, -(sp)
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bset.b #vENetIDData,vDIRB(a5) ; set Data direction OUT
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moveq #1,d1 ; set send/rcv flag
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moveq #8-1, d3 ; loop thru 8 bits
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@loop rol.b #1,d4 ; get bit to send in the carry
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bcc.s @zero ;
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bset.b #vENetIDData, (a5) ; send a one
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bra.s @clockData
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@zero bclr.b #vENetIDData, (a5) ; send a zero
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@clockData bsr.s ClockBit ; send out a bit
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dbra d3, @loop
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movem.l (sp)+, sendregs
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rts
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: GetByte
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;
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; Inputs:
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;
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; Outputs: d4.b has the received byte
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;
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; Trashes:
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;
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; Function: Receives a byte from the EtherNet ID ROM
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;————————————————————————————————————————————————————————————————————————————————————————
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GetByte
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getByteRegs REG d0-d3/d5
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movem.l getByteRegs, -(sp)
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bclr.b #vENetIDData,vDIRB(a5) ; Data direction is IN
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moveq #0,d1 ; clear send/rcv flag
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moveq #8-1, d3 ; loop thru 8 bits
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moveq #0,d4 ; clear for incoming byte
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@loop bsr.s ClockBit ; clock in a bit
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roxl.b #1,d5 ; get incoming bit into extend bit
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roxl.b #1,d4 ; shift incoming bit receive byte
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dbra d3, @loop
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movem.l (sp)+, getByteRegs
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rts
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: ReceiveAck
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;
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; Inputs: a5.l - points to VIA
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;
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;
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; Outputs: d0.w - error indicator
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;
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; Trashes:
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;
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; Function: Waits for an acknowledge bit from the EtherNet ID ROM.
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; Data direction must be IN.
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;————————————————————————————————————————————————————————————————————————————————————————
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ReceiveAck
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ackregs REG d1-d3/d5
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movem.l ackregs, -(sp)
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bclr.b #vENetIDData,vDIRB(a5) ; Data direction is IN
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moveq #0, d1 ; clear the xmit/rcv flag
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bsr.s ClockBit ; get a bit
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tst.b d5 ; did we get the ACK?
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beq.s @ackOK
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moveq #badACK, d0 ; assume we get ACK late
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moveq #8-1-1, d3 ; lets try to get ACK for rest of byte
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@tryForAck
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bsr.s ClockBit ; get a bit
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tst.b d5 ; did we get the ACK?
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beq.s @getToKnownState ; yes, now get into a known state
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dbra d3, @tryForAck ; no, try for ACK again
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moveq #WereLosers, d0 ; never got an ACK, return PUNT error
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bra.s @exit
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@getToKnownState
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bsr.s GetByte ; read ROM just in case
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bclr.b #vENetIDData, (a5) ; send out ACK
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bsr.w SendStop ; send Stop
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bra.s @exit ; return bacACK error
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@ackOK moveq #0,d0 ; return happy-Ack
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@exit movem.l (sp)+, ackregs
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tst.w d0 ; set error condition
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rts
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: SendAck
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;
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; Inputs: a5.l - points to VIA
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;
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; Outputs:
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;
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; Trashes: d1, d4
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;
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; Function: Sends an acknowledge bit to the EtherNet ID ROM
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;————————————————————————————————————————————————————————————————————————————————————————
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SendAck
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@sendackregs REG d1/d4
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movem.l @sendackregs, -(sp)
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bset.b #vENetIDData,vDIRB(a5) ; Data direction is OUT
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moveq #1, d1 ; set xmit/rcv flag
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bclr.b #vENetIDData, (a5) ; clear for Ack
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bsr.w ClockBit ; send Ack bit
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movem.l (sp)+, @sendackregs
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rts
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;————————————————————————————————————————————————————————————————————————————————————————
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; Routine: Wait5, Wait10, Wait10ms
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;
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; Inputs:
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;
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; Outputs:
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;
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; Trashes: d2
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;
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; Function: Delays 5µs, 10µs, and 10ms
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;————————————————————————————————————————————————————————————————————————————————————————
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Wait10 move.w TimeVIAdb,d2 ; 1 ms delay
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lsl.w #2,d2 ; 4 ms delay
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add.w TimeVIAdb,d2 ; 5 ms delay
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lsr.w #8,d2 ; 9.76 µs delay
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lsr.w #1,d2
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@loop tst.b ([VIA])
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dbra d2,@loop
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rts
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Wait5 move.w TimeVIAdb,d2 ; 1 ms delay
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lsl.w #2,d2 ; 4 ms delay
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add.w TimeVIAdb,d2 ; 5 ms delay
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lsr.w #8,d2 ; 4.88 µs delay
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lsr.w #2,d2
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@loop tst.b ([VIA])
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dbra d2,@loop
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rts
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Wait10ms move.w TimeVIAdb,d2 ; 1 ms delay
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lsl.w #3,d2 ; 8 ms delay
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add.w TimeVIAdb,d2 ; 9 ms delay
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add.w TimeVIAdb,d2 ; 10 ms delay
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@loop tst.b ([VIA])
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dbra d2,@loop
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rts
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ENDPROC
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END |