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500 lines
17 KiB
Plaintext
500 lines
17 KiB
Plaintext
;
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; File: HALc96HWInit.a
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;
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; Contains: 53c96 Hardware Initialization routines
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;
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; Written by: Paul Wolf
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;
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; Copyright: © 1990-1994 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM31> 2/1/94 chp Add logic to set the clock conversion factor and select/reselect
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; timeout values for MacRISC-style CPUs.
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; <SM30> 11/22/93 pdw Rolling in from <MCxx>.
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; <MC6> 11/8/93 pdw Added support for new Cold Fusions with old parts!
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; <SM29> 11/19/93 chp Don’t call ClearSCSIIRQ for level-sensitive HBAs.
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; <SMG2> 9/29/93 chp Add a test and call to initialize Grand Central DMA hardware.
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; <SM27> 11/7/93 pdw Got rid of forPDMProto around DoWeHaveAMIC3B to help (but not
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; solve) build Bob's build problems.
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; <SM26> 10/29/93 DCB <MC> roll-in.
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; <MC5> 10/28/93 pdw I don't remember.
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; <SM25> 10/14/93 pdw <MC> roll-in.
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; <MC4> 10/12/93 pdw Added support for Synchronous data transfers, rewrote State
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; Machine, message handling etc.
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; <MC3> 10/6/93 pdw Fixed up the forPDMProto stuff.
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; <MC2> 10/4/93 RC Put forPDMProto around AMIC3/2 special code
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; <SM24> 9/9/93 pdw Lots of little changes. Name changes, temporary cache_bug
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; stuff.
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; <SM23> 8/13/93 pdw Cleaned up "that shit above".
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; <SM22> 8/12/93 KW conditionalizing smurf branches
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; <SM21> 8/11/93 KW added some branches based on new smurf boxes
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; <SM20> 7/20/93 pdw Pulled out DoWeHaveFastSCSI functionality into an independent
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; routine so that other routines can use it.
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; <SM19> 7/17/93 pdw Did I change something in here?
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; <SM18> 6/29/93 pdw Massive checkins: Change asynchronicity mechanism to CallMachine
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; stack switching mechanism. Adding support for Cold Fusion.
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; Rearranging HW/SW Init code. Some code optimizations.
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; <SM17> 5/25/93 DCB Changed some bsr.s to bsr.w to fix the build.
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; <SM16> 5/25/93 DCB Rollin from Ludwig (The item below)
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; <LW6> 5/21/93 PW Getting Mac's SCSI ID from PRAM instead of hard-coded. (This was
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; a BUG!)
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; <SM15> 5/5/93 PW Converted names to meanies-friendly names. Updated with latest
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; from Ludwig stuff.
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; <LW4> 3/26/93 PW Put explicit bit lists in the InitCFx code instead of using
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; constants from a header file for the whole combination of bits.
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; <LW3> 2/17/93 PW Removed some TERROR tags.
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; <SM14> 4/8/93 DCB Added Initialization code for Wombat class machines..
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; <SM13> 3/29/93 PW Changed handling of CF3: if threshold-8, setting it up here
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; without SaveResidual on, else setting only SaveResidual.
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; <SM12> 3/20/93 PW Unknown changes.
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; <SM11> 1/31/93 PW Update from the latest of Ludwig. Also changes required for PDM
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; (will update Ludwig with these as needed myself).
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; <LW2> 1/27/93 PW Added nonSerializedIO checks and NOPs for PDM support.
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; <SM9> 12/5/92 PW EXPORTed Init53c9xRegs for fix to Reset interrupt bug in Curio.
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; <SM8> 12/3/92 fau Added boxRiscQuadra to the previous DAFBExists change.
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; <SM7> 12/3/92 fau Changed the use of DAFBExists to check for the
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; Spike/Eclipse/Zydeco box flag. Those registers on DAFB are only
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; needed on those machines. Changed the check for BoxCyclone to a
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; TestFor PSCExists (this assumes that only Cyclone type machines
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; have a PSC).
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; <SM6> 10/30/92 DCB Various Interrupt Handling improvements (using the new macros)
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; <SM5> 8/31/92 PW Changed register and command definitions to reflect changes to
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; SCSIEqu53c96.
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; <SM4> 8/24/92 PN Take out CycloneboxEVT1 stuff
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; <SM3> 8/9/92 CCH Modified boxflag check for Quadras to include RISC Quadras.
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; <SM2> 7/28/92 PW Resolved differences in sources.
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; <SM2> 7/27/92 PW Got DMA working.
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; <SM1> 7/27/92 PW Virtually initial check-in.
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;
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;==========================================================================
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MACHINE MC68020 ; '020-level
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BLANKS ON ; assembler accepts spaces & tabs in operand field
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PRINT OFF ; do not send subsequent lines to the listing file
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; don't print includes
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PostNOP EQU 1 ;
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LOAD 'StandardEqu.d'
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INCLUDE 'HardwarePrivateEqu.a'
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INCLUDE 'UniversalEqu.a' ; for VIA bit and -TestFor- definitions
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INCLUDE 'Debug.a' ; for NAME macro
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INCLUDE 'SCSI.a'
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INCLUDE 'SCSIEqu53c96.a'
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INCLUDE 'HALc96equ.a'
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PRINT ON ; do send subsequent lines to the listing files
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CASE OBJECT
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IMPORT GetInitiatorID
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IMPORT RecordEvent ; Recorder.a
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IMPORT InitAMIC ; HALc96AMIC.a
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IMPORT InitHW_GC ; HALc96GC.c
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;==========================================================================
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;
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; Init53c9xHW
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;
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; C Calling convention:
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; long Init53c9xHW(HBADesc_53c9x *hwDesc)
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;
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;——————————————————————————————————————————————————————————————————————————
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Init53c9xHW PROC EXPORT
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IMPORT AsmInit53c9xHW
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move.l A5, -(sp) ; save
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move.l 8(sp), A5 ; get pointer to hwDesc
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bsr.w AsmInit53c9xHW
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move.l (sp)+, A5
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rts
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NAME 'Init53c9xHW'
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ENDP
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;--------------------------------------------------------------------------
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;
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; AsmInit53c9xHW - reset and initialize the 53C96 SCSI controller
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; This routine resets all functions in the chip and returns
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; it to a disconnected state.
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;
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; INPUTS
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; a3 -> pointer to SCSI port base address
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; a2 -> pointer to SCSI DAFB register
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; (NOTE - this routine assumes that we are in 32-bit mode!)
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;
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; OUTPUTS
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; none
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;
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; trashes: none
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AsmInit53c9xHW PROC EXPORT
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IMPORT InitHW_SCSI96_BIOS, DoWeHaveFastSCSI
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WITH HALc96GlobalRecord
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@trashedRegs REG A0/A2-A3
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movem.l @trashedRegs, -(sp)
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DisableSCSIIRQ ; make sure we don't accidentally generate ints
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move.l HALc96GlobalRecord.baseRegAddr(A5), a3 ; where the 53c96 is
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move.l A3, -(sp)
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bsr DoWeHaveFastSCSI ; see if we have a 53FC96
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beq.s @f96
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tst.b HALc96GlobalRecord.HBAisFast(A5) ; test the IsFast flag
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bne.s @f96 ; if it's not set already,...
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move.b #$40, HALc96GlobalRecord.HBAisFast(A5) ; ...set the IsFast flag
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@f96
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addq.l #4, sp
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;
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;………… Now we do our true reset to make sure everything's undone from that weird sequence above
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;
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move.b #cResetChip, rCMD(a3) ; send reset-scsi-chip cmd
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nop
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move.b #cNOP, rCMD(a3) ; NOP required after HW or SW reset
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move.b #cFlushFIFO, rCMD(a3) ; Flush FIFO
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nop
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;
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;………… Initialize c96 configuration registers
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;
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move.l A5, -(sp) ; HALg is only parameter to GetInitID
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bsr GetInitiatorID ; returns InitID in D0 (like a C fn!)
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addq.l #4, sp
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or.b #mCF1_ResetIntrpDisable, D0 ; plus we still want reset ints disabled
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move.b D0, rCF1(a3)
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; 0 = slow cable mode disabled
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; 1 = disable intrp to host on bus reset
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; 0 = parity test mode disabled
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; 0 = parity checking disable
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; (ie. do not check parity on incoming data)
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; 0 = chip mode test disabled
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; 7 = use 7 as default myBusID
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move.b #mCF2_SCSI2, rCF2(a3)
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; 0 = do not reserve FIFO byte during sync xfer
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; 0 = disable phase latch
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; (Ie. status regr is a live state indicator of SCSI phase lines)
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; for f96 part, this bit turns on 24bit xfer count as well
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; 0 = ignore byte control inputs
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; 0 = DACK* is enabled decr the xfer counter
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; 1 = do use SCSI-2 features
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; 0 = do not abort if parity error is detected (when target)
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; 0 = do not carry parity from DMA bus (i.e. generate parity on xmit)
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; 0 = do not flag outgoing parity errs (DMA-xfer)
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move.b #mCF3_SaveResidual, rCF3(A3)
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; 1 = do not assert DREQ on residual byte at end of xfer
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; 0 = disable alternate DMA mode
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; 0 = disable threshold 8 mode (we'll change it in Initc96Asm if need be)
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nop
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;………… Initialize the DAFB if we got one …………
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;
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tst.b HALc96GlobalRecord.needsDAFBinit(A5)
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beq.s @setupC96 ; only Spike/Eclipse have a VIA2 and DAFB
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move.l HALc96GlobalRecord.dafbAddr(A5), A2 ; get address of DAFB register
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; Check whether we're 25 or 33MHz and set SCSI chip speed values appropriately
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move.l VIA2, a0 ; get VIA2 so that we can check the speed bit
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move.b vBufB(a0), d0 ; read PBx values for 25/33MHz checks
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btst #v2Speed, d0 ; are we 25 MHz or 33 Mhz?
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beq.s @25MHzDAFB ; if Speed == 33MHz THEN
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@33MHzDAFB
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move.l #tsc_cf_stg_33, (a2) ; setup DAFB SCSI config register.
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bra.s @setupC96 ; ELSE // Speed == 25MHz
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@25MHzDAFB
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move.l #tsc_cf_stg_25, (a2) ; setup DAFB SCSI config register.
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; ENDIF
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;………… Set up Clock Conversion Factor and Select/Reselect Timeout registers …………
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;
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; CPU SCSI
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; Quadra700 25 25
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; Quadra900 25 15.6672
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; Zydeco 33 24.28416 (boxFlag=Eclipse)
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; Cyclone 33 25 or 24.576 (which?)
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; PDM-Curio xx 20
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; PDM-Fast xx 40
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; TNT-Curio xx 20
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; TNT-Fast xx 40
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;
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@setupC96
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cmp.b #pdmaTypeBIOS,HALc96GlobalRecord.dmaType(A5) ; Is this a Wombat or Primus/Optimus?
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bne.s @notBIOSbased
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bsr.l InitHW_SCSI96_BIOS ; initialize BIOS stuff
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bra.s @21to25MHz
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@notBIOSbased
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TestFor PSCExists ; Do we have a PSC? <SM7>
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bne.s @21to25MHz ; Yes -> Cyclone
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@notCyclone
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TestFor HMCDecoder ; Do we have a HMC (e.g. PDM)? <SM7>
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bnz.b @PDMorMacRISC
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TestFor GrandCentralExists ; Do we have Grand Central (e.g. TNT)?
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bz.b @PDMnorMacRISC
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@PDMorMacRISC
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tst.b HALc96GlobalRecord.HBAisFast(A5) ; are we talking to an CF96?
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bne.s @40MHz ; fast -> 40MHz
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bra.s @20MHz ; else (Curio) -> 20MHz
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@PDMnorMacRISC
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TestFor SCSI96_2Exists ; check for a Q700 versus Q9x0
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beq.s @21to25MHz ; 1 bus? yes-> it's a 700 with 25 CPU/25 SCSI
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; Either 900 or 950, Check for difference between 25 and 33MHz:
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btst #v2Speed,d0 ; are we running at 25 or 33 MHZ?
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bne.s @21to25MHz ; set -> 33MHz CPU = 25MHz SCSI clock
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@16Mhz ; clr -> 25MHz CPU = 16MHz SCSI clock
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move.b #ccf16to20MHz, rCKF(a3) ; load clock conversion factor (CCF) value
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move.b #SelTO16Mhz, rSTO(a3) ; load select/reselect timeout value
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bra.s @endClockSetup
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@21to25MHz ;
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move.b #ccf21to25MHz, rCKF(a3) ; load clock conversion factor (CCF) value
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move.b #SelTO25Mhz, rSTO(a3) ;
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bra.s @endClockSetup
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@20MHz
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move.b #ccf16to20MHz, rCKF(a3) ; Curio is running at 20MHz
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move.b #SelTO20Mhz, rSTO(a3) ;
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bra.s @endClockSetup
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@40MHz
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move.b #ccf36to40MHz, rCKF(a3) ; load clock conversion factor (CCF) value
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move.b #SelTO40Mhz, rSTO(a3) ;
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@endClockSetup
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nop
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move.b #initOp, rSyncOffset(a3) ; select sync or async operation; if sync then
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; sync offset value must be nonzero
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; Set synch xfer period and offset if using
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; synch data xfer
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nop
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move.b rINT(a3), d0 ; read & clear rFOS, rSTA & rINT into throwaway
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nop
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move.b rINT(a3), d0 ; read again just in case there was a stacked int
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cmp.b #LEVEL, intSensSCSI(A5) ; can’t really clear LEVEL-sensitive IRQ
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beq.b @1
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ClearSCSIIRQ
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@1
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;
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;………… Initialize DMA Hardware (if it exists) …………
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;
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tst.b HBAhasDMA(A5) ; does HBA have real DMA?
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beq.s @endDMAstuff ; ->
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@hasDMA
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cmp.b #dmaTypePSC, dmaType(A5) ; is it a PSC-type DMA?
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beq.s @hasPSC ; -> yes
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cmp.b #dmaTypeAMIC, dmaType(A5) ; is it an AMIC-type DMA?
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beq.s @hasAMIC ; -> yes
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cmp.b #dmaTypeGC, dmaType(A5) ; is it a Grand Central-type DMA?
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beq.s @hasGC ; -> yes
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DebugStr 'HWInit:Bad hwDesc - dmaType unknown'
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@hasPSC bra.s @endDMAstuff ; no PSC init here
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@hasAMIC bsr InitAMIC ; init the AMIC (turn off Run bit)
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bra.s @endDMAstuff
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@hasGC bsr InitHW_GC
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@endDMAstuff
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movem.l (sp)+, @trashedRegs
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moveq.l #0, D0
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rts
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ENDWITH
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NAME 'Init53x9xRegs'
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ENDP
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;——————————————————————————————————————————————————————————————————————————————————————————
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;
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; InitHW_SCSI96_BIOS - reset and initialize the 53C96 SCSI controller once the gibbly loads.
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; This routine resets all functions in the chip and returns
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; it to a disconnected state.
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;
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; INPUTS
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; a3 -> pointer to SCSI port base address
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;
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; trashes: d0, d1
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InitHW_SCSI96_BIOS PROC EXPORT
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WITH DecoderInfo, DecoderKinds, ProductInfo ;
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; Check whether or not we're 25 or 33MHz and set SCSI bus speed values appropriately
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; Get machine type + CPU speed information from VIA1
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;
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; Useful VIA1 PortA bits to read: PA6, PA4, PA2, PA1 ($56)
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;
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; PA6 = Lego (1), or Frigidaire (0) plastics for Wombat
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; PA4, PA2 = CPU Speed. 0=20MHz, 1=25MHz, 2=33MHz, 3=40MHz
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; PA1 = WLCD (0) or NOT! [Reserved] (1)
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;
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; Retrieve CPU Speed information from VIA1 Port A
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@trashedRegs REG D0/D2/D3/A0/A2
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movem.l @trashedRegs, -(sp) ; save stuff
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movea.l UnivInfoPtr,a0 ; point to the DecoderInfo table
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adda.l ProductInfo.DecoderInfoPtr(a0),a0
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movea.l VIA1Addr(a0),a2 ; get VIA1 address to get machine/cpu_speed info
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moveq #%00101000,d3 ; force VIA1 VDirA to have the correct directions
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move.b d3,VDirA(a2) ; ... so we can read the CPU ID extension info
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moveq #%00010100,d3 ; get VBufA, bits PA4, PA2 (dont need PA6, PA1)
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and.b VBufA(a2),d3 ; get plastics_type/cpu_speed information
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lea BIOSAddr,a2 ; get BIOS address for ConfigSonic_SCSI setup
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move.b BIOS_SONIC_SCSI(a2),d2 ; save Sonic bit but trash
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andi.b #BIOSSCSIFilter,d2 ; everything else
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lsr.b #2,d3 ; shift PA4,PA2 down to bits 2-0
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bne.s @25MHz ; 0=20MHz, otherwise check higher
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@20MHz
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ori.b #BIOScfg20MHz,d2 ; setup for and'ing the correct SCSI cfg bits
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bra.s @contSetup
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@25MHz
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subq.b #4,d3 ; split the rest of the values
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beq.s @33MHz
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bgt.s @40MHz
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ori.b #BIOScfg25MHz,d2 ; setup for and'ing the correct SCSI cfg bits
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bra.s @contSetup
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@33MHz
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ori.b #BIOScfg33MHz,d2 ; setup for and'ing the correct SCSI cfg bits
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bra.s @contSetup
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@40MHz
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ori.b #BIOScfg40MHz,d2 ; setup for and'ing the correct SCSI cfg bits
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@contSetup
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move.b d2,BIOS_SONIC_SCSI(a2) ;
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movem.l (sp)+, @trashedRegs ; restore stuff
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rts ;
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NAME 'InitHW_SCSI96_BIOS'
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ENDP
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;——————————————————————————————————————————————————————————————————————————————————————————
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DoWeHaveFastSCSI PROC EXPORT
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;
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;………… First we reset the chip and see if we can get the Chip ID (from the F96) by doing
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; the magic <Reset, NOP, FeaturesEnable, DMA+NOP, read ChipID> sequence
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;
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move.l A3, -(sp)
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move.l 8(sp), A3 ; get hardware address
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move.b #cResetChip, rCMD(a3) ; load reset-scsi-chip cmd, this cmd has
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; the same effect as a hw reset
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nop
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move.b #cNOP, rCMD(a3) ; NOP required after HW or SW reset
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move.b #mCF2_FeaturesEnable, rCF2(A3) ; turn on Features enable then,
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move.b #$80+cNOP, rCMD(A3) ; send a DMA NOP command then,
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nop
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move.b rChipID(A3), D0 ; get the chip ID
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cmp.b #$A2, D0 ; is it an FC96?
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seq D0
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move.l (sp)+, A3
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tst D0
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rts
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NAME 'DoWeHaveFastSCSI'
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ENDP
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;—————————————————————————————
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DoWeHaveAMIC3B PROC EXPORT
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;
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via2slotIER equ $50f26012
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amic3Bflag EQU $60<<24 ; $6 in high nibble
|
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move.w SR, -(sp)
|
||
or.w #$0700, SR ; block interrupts
|
||
|
||
move.l #amic3Bflag, D1
|
||
beq.s @ckSlotBit1
|
||
move.l D1, A0
|
||
add.w #$efe8, A0
|
||
move.l (A0), A0
|
||
move.l $f0(A0), D1
|
||
beq.s @ckSlotBit2
|
||
@ckSlotBit1
|
||
move.l D1, -(sp) ; save D1
|
||
move.b via2slotIER, D1
|
||
|
||
move.b #$82, via2slotIER
|
||
btst.b #1, via2slotIER
|
||
bne.s @notAMIC3
|
||
move.b #$02, via2slotIER
|
||
btst.b #1, via2slotIER
|
||
bra.s @exit
|
||
|
||
@ckSlotBit2
|
||
move.l D1, -(sp) ; save D1
|
||
move.b via2slotIER, D1 ; get current Interrupt Enable flags
|
||
|
||
move.b #$84, via2slotIER ; try to set new NuBus slot flag
|
||
btst.b #2, via2slotIER ; does it stick?
|
||
beq.s @notAMIC3 ; nope -> not AMIC3
|
||
move.b #$04, via2slotIER ; try to clear new NuBus slot flag
|
||
btst.b #2, via2slotIER ; does it stick?
|
||
beq.s @isAMIC3 ; yup -> is AMIC3
|
||
@notAMIC3
|
||
move.l (sp)+, D1
|
||
move.w (sp)+, SR ; reenable interrupts
|
||
cmp.b D0, D0 ; set Z
|
||
rts
|
||
|
||
@isAMIC3
|
||
lsl.b #7-2, D1 ; get the old value of bit 2 into bit 7 (set/clr bit)
|
||
or.b #4, D1 ; tell it which bit we want to set/clear
|
||
move.b D1, via2slotIER ; restore old value of bit
|
||
move.l (sp)+, D1
|
||
move.w (sp)+, SR ; reenable interrupts
|
||
@exit
|
||
cmp.w #0, A7 ; clear Z
|
||
rts
|
||
;
|
||
ENDP
|
||
|
||
END |