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560 lines
21 KiB
Plaintext
560 lines
21 KiB
Plaintext
;__________________________________________________________________________________________________
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;
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; File: HALc96equ.a
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;
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; Contains: HALc96 private equates, variables and data structures
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;
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; Written by: Paul Wolf
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;
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; Copyright © 1989-1994 by Apple Computer, Inc. All rights reserved.
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;
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; This file is used in these builds:
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;
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; Change History (most recent first):
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;
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; <SM34> 1/25/94 DCB Added another deferred task record for use by pseudo DMA
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; machines.
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; <SM33> 12/19/93 DCB Added the pendingDTask flag.
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; <SM32> 11/22/93 pdw Rolling in from <MCxx>.
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; <MC10> 11/11/93 pdw Rearranged globals to accomodate dynamic supported-flags.
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; <SM31> 11/19/93 chp Add IRQ primitive vectors to HBADesc_53c9x record. Add constants
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; for intTypeSCSI and intTypeDMA. Modify IRQ macros to use the
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; newly defined primitive vectors.
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; <SM30> 11/16/93 SAM Removed eieio macro definition.
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; <MC6> 10/29/93 pdw Added dmaAlignmentSize and dmaAlignMask.
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; <SMG3> 9/29/93 chp Add HAL fields to the HAL globals to represent a DB-DMA channel
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; command list buffer, with both logical and physical addresses.
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; Clean up changes in <SMG2>. Fix some potentially case-sensitive
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; stuff.
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; <SMG2> 9/22/93 chp Add TNT support.
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; <SM28> 10/29/93 DCB Added a deferred task element to the globals so we can reduce
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; the interrupt level in the pseudo DMA data xfer routines.
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; <MC5> 10/28/93 pdw Just the usual - new vectors, new globals etc.
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; <SM27> 10/14/93 pdw <MC> roll-in.
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; <MC4> 10/12/93 pdw Added support for Synchronous data transfers, rewrote State
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; Machine, message handling etc.
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; <MC3> 10/6/93 pdw Added forPDMProto around bit defines that are only used on
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; prototypes.
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; <MC2> 9/26/93 pdw Changes to G_State usage from bit flags to enumeration.
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; <SM26> 9/16/93 DCB Got rid of YeOldeBusErrVect since it isn't used anymore.
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; <SM25> 9/12/93 pdw Getting rid of jvTransfer.
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; <SM24> 9/9/93 pdw Lots of little changes. Name changes, temporary cache_bug
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; stuff.
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; <SM23> 8/19/93 DCB Improving the bus error handler so that disconnects at
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; non-polled bytes will work properly.
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; <SM22> 8/13/93 pdw Got rid of some unused bits. Added eieio macro.
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; <SM21> 7/20/93 pdw Added intIRQbitNum and changed intDREQbitNum to a uchar.
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; <SM20> 7/17/93 pdw A few little things.
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; <SM19> 6/29/93 pdw Massive checkins: Change asynchronicity mechanism to CallMachine
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; stack switching mechanism. Adding support for Cold Fusion.
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; Rearranging HW/SW Init code. Some code optimizations. Resolving
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; with my Ludwig sources.
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; <SM18> 5/26/93 PW Separating...
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; <SM18> 5/26/93 PW Separating the nonSerializedIO from the PDM debug stuff.
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; <SM17> 5/25/93 DCB Rollin from Ludwig. (The next item below)
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; <LW12> 5/21/93 PW Adding PRAM selectable Initiator ID stuff.
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; <SM16> 5/6/93 PW Adding NOP to keep stop asm warnings.
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; <SM15> 5/5/93 PW Converted names to meanies-friendly names. Updated with latest
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; from Ludwig stuff.
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; <SM14> 3/29/93 PW Temp: Added 2 flags to selectively enable real DMA on AMIC/Curio
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; (PDM). These are set by PRAM values in HALc96Init.a.
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; <SM13> 3/29/93 DCB Adding pdmaTypeBIOS type to the dma type enum.
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; <LW11> 5/1/93 PW Got rid of RECORD_ON definition (should only be in Debug.a now.
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; <LW10> 4/30/93 DCB Getting rid of Info HalAction vector. It is getting its own
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; entry point into the HAL to prevent deadlocks.
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; <LW9> 4/30/93 PW Added fields needed for 1,511 TIB optimization as well as some
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; extra fields in jump table for future use.
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; <LW8> 4/30/93 DCB Changing default RECORD_ON to 0 for final Candiatate
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; <LW6> 4/14/93 DCB Added jump table vector for SetParity
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; <LW5> 3/26/93 PW Added savedCF2 byte and rearranged vectors for some reason.
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; <SM12> 3/20/93 PW Introducing noSCSIInts.
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; <LW4> 2/17/93 PW Moved otherHALg up into C-accessible area of globals.
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; <SM11> 1/31/93 PW Update from the latest of Ludwig. Also changes required for PDM
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; (will update Ludwig with these as needed myself).
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; <LW3> 1/27/93 PW Added dispatched InitDataStuff and DoData routines.
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; <LW2> 1/8/93 PW Added inISR semaphore to check for a re-entrant ISR.
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; <SM10> 12/9/92 PW Deleted unused field.
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; <SM9> 12/5/92 PW Minor rearrangement to be more logical.
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; <SM8> 11/20/92 DCB Removed an include and put a conditional around deferred task
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; manager stuff to save a few bytes of global space.
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; <SM7> 11/12/92 PN Get rid of ≥ 020 conditionals
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; <SM6> 10/30/92 DCB Added some flags to control direct DMA operations. Also added
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; some macros to improve interrupt handlinbg
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; <SM5> 10/8/92 PW Aligned some fields and rearranged some others. Eliminated
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; unused third transfer vectors.
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; <SM4> 8/30/92 PW Added kAssertATN to dispatch vectors.
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; <SM3> 8/20/92 DCB Fixed SCSI Bus Reset
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; <SM2> 7/28/92 PW Resolved differences in sources.
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; <SM1> 7/27/92 PW Initial check-in.
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;
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;__________________________________________________________________________________________________
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BLANKS ON
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STRING ASIS
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IF CPU ≥ 020 THEN ;
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MACHINE MC68020 ; for '020 instructions
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ENDIF
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IF (&TYPE('__INCLUDINGDEFERREDTASKEQU__') = 'UNDEFINED') THEN
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INCLUDE 'DeferredTaskEqu.a'
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ENDIF
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IF (&TYPE('__INCLUDINGGRANDCENTRALPRIV__') = 'UNDEFINED') THEN
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INCLUDE 'GrandCentralPriv.a'
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ENDIF
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;
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; Version number of the SCSI Mgr
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;
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mgrVersion2 EQU 2 ; brand new SCSI Mgr 2
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; SCSI Manager "G_State" flags
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scPending EQU 7 ; bit in G_State -- an old request is spinning in SCSIGet
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scBusy EQU 0 ; bit in G_State -- an old request is pending/in progress
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MAXSTACK EQU 256
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; Declaration of HALc96 globals
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;
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HALc96GlobalRecord RECORD 0, INCREMENT
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;
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;====== Accessible from C and Asm ===== UPDATE HALc96.h FILE AS WELL!
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; NOTE: hwDesc (and the elements of that structure following) must remain at the top
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; of the globals so that the HW init code can use the same routines as the mainline
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; HAL code (i.e. ClearSCSIIRQ). See HALc96HWInit.a for more details.
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;
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hwDesc ; HBADesc_53c9x …
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baseRegAddr ds.l 1 ; base addr of c9x registers (offset of $10 between regs
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pdmaAddr ds.l 1 ; addr of Pseudo-dma access
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pdmaNonSerlzdAddr ds.l 1 ; addr of Pseudo-dma in non-serialized space access
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dreqAddr ds.l 1 ; addr of DAFB register with DREQ bit (SCSI DREQ base address)
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intEnableSCSIAddr ds.l 1 ; addr of control register for SCSI interrupt
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intFlagSCSIAddr ds.l 1 ; addr of status register for SCSI interrupt
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dafbAddr ds.l 1 ; addr of DAFB that needs initialization
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hbaUnusedL1 ds.l 1 ; addr of
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dmaCntrlAddr ds.l 1 ; addr of true DMA control register(s)
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dmaBaseAddr ds.l 1 ; addr of true DMA base register(s)
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jvClearSCSIIRQ ds.l 1 ; hardware-specific primitive routine
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jvEnableSCSIIRQ ds.l 1 ; hardware-specific primitive routine
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jvDisableSCSIIRQ ds.l 1 ; hardware-specific primitive routine
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jvTestSCSIIE ds.l 1 ; hardware-specific primitive routine
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dreqNeedsSwapMMU ds.b 1 ; Boolean: set if dreq status bit is in 32-bit space
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HBAisFast ds.b 1 ; Boolean: set if c9x part capable of Fast Synchronous (10MB/S)
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HBAisDiff ds.b 1 ; Boolean: set if c9x part capable of differential
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usesThreshold8 ds.b 1 ; Boolean: set if DMA/interface can use c96's threshold8 mode
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needsDAFBinit ds.b 1 ; Boolean: set if there's a DAFB that needs to be inited
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hbaUnusedB1 ds.b 1 ; Boolean: set if
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hbaUnusedB2 ds.b 1 ; Boolean: set if
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hbaUnusedB3 ds.b 1 ; Boolean: set if
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HBAhasDMA ds.b 1 ; Boolean: set if true DMA available
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HBAhasPseudoDMA ds.b 1 ; Boolean: set if Pseudo-DMA available
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HBAhasHskPseudoDMA ds.b 1 ; Boolean: set if handshaked Pseudo-DMA available
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dmaCacheCoherent ds.b 1 ; Boolean: set if DMA is fully cache coherent (no flushing needed)
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hbaUnusedB4 ds.b 1 ; Boolean: set if
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hbaUnusedB5 ds.b 1 ; Boolean: set if
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hbaUnusedB6 ds.b 1 ; Boolean: set if
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initiatorID ds.b 1 ; Char: ID of Macintosh (Initiator) on this bus
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testIRQenableValue ds.b 1 ; Char: value to mask with to test SCSI IRQ enable
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enableIRQvalue ds.b 1 ; Char: value to write to enable SCSI IRQ
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disableIRQvalue ds.b 1 ; Char: value to write to disable SCSI IRQ
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clearIRQvalue ds.b 1 ; Char: value to write to clear SCSI IRQ
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intIRQbitNum ds.b 1 ; bit to test for IRQ
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intDREQbitNum ds.b 1 ; bit to test for DREQ
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hbaUnusedC1 ds.b 1 ;
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hbaUnusedC2 ds.b 1 ;
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intTypeSCSI ds.b 1 ; type of interrupt control (shared VIA bit, etc.)
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intSensSCSI ds.b 1 ; type of sensitivity (LEVEL, EDGE, STICKYBIT)
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intTypeDMA ds.b 1 ; type of interrupt control (shared VIA bit, etc.)
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intSensDMA ds.b 1 ; type of sensitivity (LEVEL, EDGE, STICKYBIT)
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dmaType ds.b 1 ; type of programming model for DMA (PSC, AMIC,…)
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dmaAlignmentSize ds.b 1 ; alignment requirements (i.e. 8, 16 etc)
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hbaUnusedC4 ds.b 1 ;
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hbaUnusedC5 ds.b 1 ;
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intOSNumberSCSI ds.w 1 ; OS registration number for the SCSI interrupt
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intOSNumberDMA ds.w 1 ; OS registration number for the DMA interrupt
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hbaUnusedS1 ds.w 1 ;
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hbaUnusedS2 ds.w 1 ;
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;
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; …end of hwDesc
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;…0
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SIMstaticPtr ds.l 1 ; ptr to SIM's globals (for SSM callbacks)
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XPT_ISRptr ds.l 1 ; ptr to XPT's ISR (so HAL can install it)
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unusedRPtr ds.l 1 ; ptr to
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ReconnectISRptr ds.l 1 ; ptr to SIM's Reconnect ISR for us to call
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busID ds.w 1 ; bus ID of this HAL's bus
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rsrvdS2 ds.w 1 ; <SM5> pdw
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cclPhysicalAddr ds.l 1 ; addr of DB-DMA channel command list buffer (physical)
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cclLogicalAddr ds.l 1 ; addr of DB-DMA channel command list buffer (logical)
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physicalCopyBuffer ds.l 1 ; physical address of locked/noncachable copy buffer
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logicalCopyBuffer ds.l 1 ; logical address of copy buffer to DMA into/out of
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otherHALg ds.l 1 ; globals ptr to other HAL on dual bus machine
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privStackTop ds.l 1 ;
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minDMAsize ds.l 1 ;
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supported_scFlags ds.l 1
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supported_scIOFlags ds.w 1
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supported_scDataTypes ds.w 1
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unusedCA1 ds.l 4
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;
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;======= Accessible from Asm only ======
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;
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G_JmpTbl ;—————— Jump Table ————————
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;———— entry point jump table vectors
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; must correspond to HALaction record shown below
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jvInitiate ds.l 1 ; 0
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jvBitBucket ds.l 1
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jvDataIn ds.l 1
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jvDataOut ds.l 1
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jvAcceptMsg ds.l 1 ; 4
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jvRejectMsg ds.l 1
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jvMsgIn ds.l 1
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jvMsgOut ds.l 1
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jvStatus ds.l 1 ; 8
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jvComplete ds.l 1
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jvSaveDataPointer ds.l 1
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jvModifyDataPointer ds.l 1
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jvRestorePointers ds.l 1 ; 12
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jvGetReconnectInfo ds.l 1
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jvGetSelectInfo ds.l 1
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jvSelect ds.l 1
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jvSelectWAtn ds.l 1 ; $10
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jvCommand ds.l 1
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jvSetParity ds.l 1 ; <LW6> DCB
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jvHandleSelected ds.l 1 ; $13
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jvSetupIO ds.l 1 ; $14
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jvResetBus ds.l 1
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jvAssertATN ds.l 1
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jvTeardownIO ds.l 1
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jvUnused18 DS.L 1 ;$18
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jvUnused19 DS.L 1
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jvUnused1a DS.L 1
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jvUnused1b DS.L 1
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jvUnused1c DS.L 1
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jvUnused1d DS.L 1
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jvUnused1e DS.L 1
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jvUnused1f DS.L 1
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;———— non-entry point jump table vectors
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;—— Data Routines
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initDataRoutines ds.l 4 ; jump table for data-transfer routines ; $20
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dataRoutines ds.l 4 ; jump table for data-transfer routines ; $24
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xferRoutines equ * ; jump table for data-transfer routines ; $28
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readOffset equ (* - xferRoutines)/4
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scsiReadFast equ (* - xferRoutines)/4
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jvReadFast DS.L 1 ; fast reads
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scsiReadSlow equ (* - xferRoutines)/4
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jvReadSlow DS.L 1 ; slow reads
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writeOffset equ (* - xferRoutines)/4
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scsiWriteFast equ (* - xferRoutines)/4
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jvWriteFast DS.L 1 ; fast writes
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scsiWriteSlow equ (* - xferRoutines)/4
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jvWriteSlow DS.L 1 ; slow writes
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numTransferTypes equ (*-xferRoutines)/4/2 ; <SM5> pdw
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;———— assorted other non-entry vectors
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jvUnused2c DS.L 1 ;$2c:
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jvCyclePhase DS.L 1 ; Bitbuckets or fills bytes to get target to Status phase
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jvBusErr DS.L 1 ;
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jvUnusedX DS.L 1 ;
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jvStartDMA DS.L 1 ;$30: starts either DMA read or write
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jvStopReadDMA DS.L 1 ; stops a DMA read
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jvStopWriteDMA DS.L 1 ; stops a DMA write
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jvWt4DMAComplete DS.L 1 ; waits until a DMA is complete (only used by initate)
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jvAutoMsgIn DS.L 1
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jvWt4SelectComplete DS.L 1
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jvHandleBusInt DS.L 1
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jvUnused37 DS.L 1
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jvUnused38 DS.L 1
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jvUnused39 DS.L 1
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jvUnused3a DS.L 1
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jvUnused3b DS.L 1
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jvUnused3c DS.L 1
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jvUnused3d DS.L 1
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jvUnused3e DS.L 1
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jvUnused3f DS.L 1
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;———— end of jump vectors
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numSelectors equ (*-G_JmpTbl)/4 ;$38
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transferType DS.W 1 ; Type of data transfer to perform (used in Transfer_96, BusError)
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rCF3NormalVal DS.B 1 ; value of rCF3 during normal operation
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rCF3DMAVal DS.B 1 ; value of rCF3 during DMA operation
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unused1 DS.B 1 ; LUDWIG : rCF3DataVal
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optimTIB DS.B 1 ; set if we're optimizing the TIB
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currentPhase DS.B 1 ; current SCSI bus phase
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dataDeferStuff DS.B 1 ; semaphore for the null deferred task
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G_State96 DS.B 1 ; Bits to follow c96 internal state
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gotInt DS.B 1 ; flag = we've got an int
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intFlags DS.B 1 ; some flags for things
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dmaFlags DS.B 1 ; some more flags for things (DMA and LockMemory Control) <SM6>
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chanlControl DS.L 1 ; used by PSC code only - saved between Start and StopPSC
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setRegs DS.L 1 ; used by PSC code only
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intRegsRead equ *
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int_rSQS DS.B 1 ; Value of rSQS at last valid interrupt read (required)
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int_rSTA DS.B 1 ; Value of rSTA at last valid interrupt read (required)
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int_rFIFOflags DS.B 1 ; Value of rFOS at last valid interrupt read (useless)
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int_rINT DS.B 1 ; Value of rINT at last valid interrupt read (required)
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illCmdRegsRead DS.B 1 ;
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DS.B 1 ;
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DS.B 1 ;
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DS.B 1 ;
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r_selectingID DS.B 1 ; ID of target (re)selecting c96
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r_selectingMsg1 DS.B 1 ; msg byte received (Identify) after reselected
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r_selMsgLen DS.B 1 ;
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r_selPhase DS.B 1 ;
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newRegsRead DS.L 1 ; Value of regs at previous interrupt read (useless)
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oldRegsRead DS.L 1 ; Value of regs at previous interrupt read (useless)
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olderRegsRead DS.L 1 ; Value of regs at previous interrupt read (useless)
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oldestRegsRead DS.L 1 ; Value of regs at previous interrupt read (useless)
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dbug0 DS.L 1 ;
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firstIncCount DS.L 1 ; transfer count from first scInc (before optimization)
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secondIncCount DS.L 1 ; same but from second scInc of optimized TIB
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logBuffer DS.L 1 ; a place to remember where the real (logical) buffer is while
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; we use the physical one to DMA into
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getPhysLen DS.L 1 ; a spot for the count of a logical-physical table
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publicSP DS.L 1 ; stack pointer upon arrival into RealHALaction
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suspendedSP DS.L 1 ; suspended SCSI thread stack pointer
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rcvdIDBits DS.B 1 ; mask of bits on bus during selection
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selectedRegSQS DS.B 1 ; rSQS after selection
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rcvdMessageLen DS.B 1 ; # of message out bytes received after being selected as target
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rcvdMessage DS.B 13 ; message out bytes received after being selected as target
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rcvdCommandLen DS.B 1 ; # of command bytes received after being selected as target
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rcvdCommand DS.B 15 ; command bytes received after being selected as target
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publicStkLowPt DS.L 1
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privStackState DS.B 1
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dataDTFlags DS.B 1 ; Used to keep track of whether we are in our data xfer deferred task
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savedSR DS.W 1 ; saved SR for use in BERR handler
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intrpStackFrame DS.L 1
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dmaAlignMask DS.L 1 ; mask that corresponds with alignment
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dataDT DS DeferredTask ; The deferred task record which allows us to
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; defer pseudoDMA data transfers until after
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; we are out of our interrupt handler.
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dataDT_Null DS DeferredTask ; A deferred task that just points to null. Since
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; the real deferred task manager doesn't run when
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; VM is disabled we needed to write our own. jDisptch
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; only gets called when there is something in the real
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; deferred task queue so we just stuff this in there
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; to trigger interrupthandlers.a to call jDisptch which
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; calls our own deferred task manager
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extras DS.L 8 ; unused
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;
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;---- End Of Globals ----
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GlobalSize EQU *-HALc96GlobalRecord ; size of HALc96 globals
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ENDR
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;————————————————————————————————————————————————————————————————————————————————————
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; If we were smart, we'd make this page size independent
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PageSize601 EQU $1000 ; 4K (for now)
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PageMask601 EQU $0FFF ; inverse
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;—————————————————————————————————————————————————————————
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; Bit definitions for flag bytes in globals
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; bytes! i.e. no bit higher than 7
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;————————————————————————————————————————————————————————
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;———— G_State96 Value defs —— keeps track of where old-API is in a c96 Select(w/Atn) cmd
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;
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; We need to keep track of what state the c96 is in during it's handling of a DMA Select
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; or Select W/Atn command because we hand control back to the SIM (and then to the client
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; during the processing of an old API transaction right in the middle of the c96's
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; processing of this command.
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;
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NeedMsgOut EQU 3 ; expect a msg_out phase next as part of $C1 cmd to c96
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|
NeedCmdSent EQU 2 ; expect a command phase that we need to complete the select
|
|
FCIntPend EQU 1 ; Function Complete Intrp pending bit (from $C1 cmd)
|
|
|
|
|
|
;——— Bit Definitions for intFlags byte —————
|
|
|
|
waiting4int EQU 3 ; Wt4SCSIInt has been called but ISR hasn't happened yet
|
|
intRegsValid EQU 6 ; set when we get an int and cleared before issuing a command
|
|
r_selRegsValid EQU 7 ; set when we get a sel/resel int and clrd at issue of Enable R_Sel cmd
|
|
|
|
;——— Bit Definitions for dataDTFlags byte —————
|
|
|
|
inDataDT EQU 0 ; Set if we are doing DMA straight to the user's buffer
|
|
fromRealInt EQU 1 ; Set if we have are executing code from our ISR as a result of
|
|
; a real (as opposed to polled for) interrupt. This means that it
|
|
; is safe to defer our data transfer
|
|
pendingDTask EQU 2 ; Set if we are expecting the deferred task to execute.
|
|
|
|
|
|
;——— Bit Definitions for dmaFlags byte —————
|
|
|
|
noBlockMove EQU 0 ; Set if we are doing DMA straight to the user's buffer <SM6>
|
|
|
|
; forPDMProto
|
|
doRealDMAWrite EQU 4
|
|
doRealDMARead EQU 5
|
|
; end
|
|
;
|
|
;———— Register saving convention ————
|
|
;
|
|
scsiRegs REG a0-a5/d1-d7 ; standard register saving convention (result in d0)
|
|
intrRegs REG a0-a5/d0-d7 ; interrupt handler register saving convention
|
|
|
|
;
|
|
; Old SCSI Mgr equates -- temporary, since SCSI.a has the public portion of the PB
|
|
;
|
|
|
|
;maxOpcode EQU 8 ; highest numbered TIB opcode (from rom78fix.a)
|
|
|
|
|
|
;---------------------------------------------------
|
|
; For intTypeSCSI and intTypeDMA HW descriptors
|
|
;---------------------------------------------------
|
|
SHARED_VIA EQU 0
|
|
INDEPENDENT_VIA EQU 1
|
|
SECOND_SHARED_VIA EQU 2
|
|
GRAND_CENTRAL EQU 3
|
|
|
|
|
|
;---------------------------------------------------
|
|
; For intSensSCSI and intSensDMA HW descriptors
|
|
;---------------------------------------------------
|
|
EDGE EQU 0
|
|
LEVEL EQU 1 ; no clear necessary
|
|
STICKYBIT EQU 2
|
|
|
|
|
|
;---------------------------------------------------
|
|
; For dmaType HW descriptor
|
|
;---------------------------------------------------
|
|
dmaTypeNone EQU 0
|
|
dmaTypePSC EQU 1
|
|
dmaTypeAMIC EQU 2
|
|
pdmaTypeBIOS EQU 3
|
|
dmaTypeGC EQU 4
|
|
|
|
|
|
;---------------------------------------------------
|
|
; Debug Defs
|
|
;---------------------------------------------------
|
|
|
|
overFlow EQU $0 ;
|
|
|
|
|
|
;——————————————————————————————————————————————————————————
|
|
MACRO
|
|
ClearSCSIIRQ ; clear latched VIA SCSI interrupt bit <SM6> pdw
|
|
;—————————————————————————————
|
|
IF 0 AND RECORD_ON THEN
|
|
pea 'It=0'
|
|
move.l sp, -(sp)
|
|
bsr RecordEvent
|
|
addq.l #8, sp
|
|
ENDIF
|
|
if noSCSIInts then
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
else
|
|
jsr ([HALc96GlobalRecord.jvClearSCSIIRQ,A5])
|
|
endif
|
|
eieio
|
|
ENDM
|
|
|
|
;——————————————————————————————————————————————————————————
|
|
MACRO
|
|
EnableSCSIIRQ ; Enable SCSI interrupt <SM6> pdw
|
|
;—————————————————————————————
|
|
IF 0 AND RECORD_ON THEN
|
|
pea 'It++'
|
|
move.l sp, -(sp)
|
|
bsr RecordEvent
|
|
addq.l #8, sp
|
|
ENDIF
|
|
if noSCSIInts then
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
else
|
|
jsr ([HALc96GlobalRecord.jvEnableSCSIIRQ,A5])
|
|
endif
|
|
eieio
|
|
ENDM
|
|
|
|
|
|
;——————————————————————————————————————————————————————————
|
|
MACRO
|
|
DisableSCSIIRQ ; Disable SCSI interrupt <SM6> pdw
|
|
;—————————————————————————————
|
|
IF 0 AND RECORD_ON THEN
|
|
pea 'It--'
|
|
move.l sp, -(sp)
|
|
bsr RecordEvent
|
|
addq.l #8, sp
|
|
ENDIF
|
|
if noSCSIInts then
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
else
|
|
jsr ([HALc96GlobalRecord.jvDisableSCSIIRQ,A5])
|
|
endif
|
|
eieio
|
|
ENDM
|
|
|
|
|
|
;——————————————————————————————————————————————————————————
|
|
MACRO
|
|
jsrv &jv, &areg ; jsr to A5-vectored routine
|
|
;—————————————————————————————
|
|
IF INDEXED_IS_FASTER THEN
|
|
jsr ([&jv, A5])
|
|
ELSE
|
|
move.l &jv(A5), &areg
|
|
jsr (&areg)
|
|
ENDIF
|
|
ENDM |