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sys7.1-doc-wip/OS/StartMgr/USTPostProc.a
Horst Beepmanh 33cd9271f4 SuperMarioProj.1994-02-09
2019-07-27 22:37:48 +08:00

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;
; File: USTPostProc.a
;
; Contains: This file includes the error handling routines and the ram testing routine called
; by StartInit.
;
;
; Copyright: © 1983-1990, 1992 by Apple Computer, Inc., all rights reserved.
;
; Change History (most recent first):
;
; <SM3> 11/18/92 fau Modified the Error1-4Handlers to check whether they are running
; on a YMCADecoder-based machine (A Cyclone). If so, then we will
; call the correct "death chimes" for Cyclone, using the DSP and
; not the non-existent ASC.
; <SM2> 5/1/92 kc Roll in Horror. Comments Follow:
; <H3> 3/6/92 AL Made a couple of branches and BSR6 branches to long branches
; because they reference routines in the file USTTestMgr.a, which
; was moved into USTStartTest1.a after the PROC parts were
; conditionalized (the UST files outgrew their space, so a couple
; of them had to be moved elsewhere).
; <H2> 01/27/92 jmp Conditionalized the PROC parts of this file for use in lining up
; the UST part of HORROR with that of TERROR/Zydeco.
; ———————————————————————————————————————————————————————————————————————————————————————
; Pre-Horror ROM comments begin here.
; ———————————————————————————————————————————————————————————————————————————————————————
; <T3> 12/14/90 HJR Changed how non critical tests are reported in PRAM.
; <T2> 9/17/90 CCH Modified a cache flush routine to b e 68040-friendly.
; ———————————————————————————————————————————————————————————————————————————————————————
; Pre-Terror ROM comments begin here.
; ———————————————————————————————————————————————————————————————————————————————————————
; <6> 5/18/90 CV Rolling in changes from mainproj. Original comments below.
; {7} 5/7/90 SS Removed IMPORT of TMVectors because it wasn't used in here
; anyway.
; {6} 4/26/90 SS At Error1Handler, set up the stack first thing because if we got
; there from a failure of SizeMemory, a7 will not be set to
; anything meaningful.
; <5> 4/2/90 CV Rolling in changes from mainproj. Original comments below.
; {5} 3/27/90 SS In the non-critical test error handler I no longer clear the
; error register (d6) upon exit. I need that result later if I'm
; in test, so I can't clear it.
; <4> 3/2/90 CV Replacing file with file from mainproj.
; {4} 2/27/90 SS Changed the error handler so that if you're in test mode (with
; burn-in jumper installed) it checks for diagnostic ROMs and
; returns to them if present. If there are no diagnostic ROMs,
; operation is the same as before.
; {3} 2/16/90 SS Added flags to statements which were changed to support Ericson.
; {2} 2/12/90 MA Writes to PRAM used to use D5 as index into PRAM. Now uses D4.
; D5 would be destroyed by quasi-power manager or EGRET.
; <1.7> 11/22/89 rle needed for ZoneV: fix parameters for StartTimer within
; <1.6> 11/13/89 rle fixed bug in error1handler to enable instruction burst mode
; <1.5> 11/12/89 CCH Fixed comment in version 1.4 (: instead of a ;)
; <1.4> 11/11/89 rle needed for ZoneV: corrected bugs inadvertantly introduced when
; <1.3> 8/22/89 GMR Made Error1Handler jmp directly to test manager, instead of
; falling
; <1.2> 6/13/89 GGD Modified to work with latest version of Beep.a, leave cache on,
; pass
; <1.1> 6/11/89 GMR Removed INCLUDES, now in header file which includes all others.
; <1.0> 6/11/89 GMR Added new universal StartTest files for first time to EASE.
; <1.9> 5/26/89 rle cleaned up file (removed obsolete code); doRAMTest no longer
; exists
; <1.8> 5/16/89 rle turn off cache when calling error beeps; don't need RAMTest
; anymore!
; <1.7> 4/28/89 rle save/restore register d7 upon calls to error beep within
; error2handler
; <1.6> 4/11/89 rle clear results register upon exit from NCErrorHandler
; <1.5> 3/28/89 rle updated RAMTest for use on all MMU-based machines, in keeping
; with the new, consistent memory test model
; <1.4> 2/14/89 RLE test results register when control returned from mod3test for
; MMU machines
; <1.3> 2/10/89 RLE update equates to support minimal f-19 build
; <1.2> 2/6/89 RLE replaced NuMac conditionals with more generic identifiers
; <1.1> 2/2/89 RLE STPostProc.a is now an independent file, responsible for
; importting and exportting the procedures it needs and others
; need; fixed a lot of conditional statements to make them more
; generic and less CPU-specific; changed NCErrorHandler to log d6
; and d7 to parameter ram, implementation depending upon the CPU
; in question; fixed NCErrorHandler to turn off clock chip write
; protect; changed doRAMTest to handle MMU systems--StartInit
; still passes in physical addresses and we just turn the MMU off
; temporarily
; <1.0> 1/11/89 RLE derived from version 1.4 of StartTest.a modified version history
; markers for all old versions to start with "[" instead of
; "<"--this allows changes in STPostProc to be tracked separately
; changed NCErrorHandler to indicate an error by setting LSB in
; byte 0 of test parameter ram ($70 on Harpo); d6 and d7 are
; logged by NCErrorHandler to the bottom eight bytes of test
; parameter ram ($78 on Harpo) in the event of an error
;
; To Do:
;
;------------------------------------------------------------------------------
PostProc PROC ; <v1.1>
WITH DecoderInfo
INCLUDE 'UniversalEqu.a' ; <7> rb
EXPORT goTM
EXPORT Error1Handler
EXPORT Error2Handler
EXPORT Error3Handler
EXPORT Error4Handler
EXPORT NCErrorHandler
IMPORT ErrorBeep1
IMPORT ErrorBeep2
IMPORT ErrorBeep3
IMPORT CritErr
IMPORT RdXByte
IMPORT WrXByte
IMPORT TMEntry1
IMPORT StartTimer
IMPORT CycloneBeep ; <SM3> fau
IMPORT QuasiPwrMgr
IMPORT Mod3Test
IMPORT JGetHardwareInfo ; [C43>
IMPORT ClkWpOff ; <v1.1>
;-----------**If here, then in board burn in or Service**-------------------
; We in board burn in (or board tester) because of loopback on VIA SV0-SV1, and/or failure.
; If no failure, set d6 to reflect good power on tests.
goTM tst.w d7 ;was any error during tests? [C660>
bne.s @710 ;yes, d6 has minor code [C660>
move.l #$87654321,d6 ;no, set good result code
@710
; bra Error1Handler ;vector through error handler <v1.9>
;---------------------------------------------------------------------------
; Entry to Error1Handler indicates a fatal error on StartTest1 tests. We
; must assume the screen wasn't cleared or anything. We don't even know
; where the video card is, so for now lets not do any error display. Leave
; the screen garbaged.....
;
; Entry to Error2Handler indicates a fatal error on StartTest2 tests. The
; screen should be cleared and the low memory screen globals should be ok.
; This means we can display some error data on the screen, then continue
; on to the Test Manager and wait for possible further instructions via
; the serial port. CritError routine will verify that the video is inited
; with the "VideoMagic" global.
;
; On entry, d6 = minor fail code or failed bit mask for RAM failures.
; d7.lw = major fail code as per equates and exceptions above.
; d7.hw = current flag bits, perhaps of minor interest.
;
; Registers d7 and d6 are displayed on the screen as follows:
;
;
; Sad "Mac"
; Icon
;
; XXXXXXXX X = D7 contents
; YYYYYYYY Y = D6 contents
;
; We must also check the flag bits in d7 to make sure we aren't in board
; burn in or service.
;
; ErrorBeep1 is called for any error that comes through Error1Handler. That
; includes the early failures, low RAM, ROM, or an NMI hit while testing.
;---------------------------------------------------------------------------
;
WITH ProductInfo, DecoderInfo, DecoderKinds ; <SM??> fau
Error1Handler ;first check if we are running on a board tester (burn-in flag set and diag ROM response)
move.l #aStack,a7 ;set stack pointer value <6>
moveq #0,d2 ; <4>
BSR6 JGetHardwareInfo ;Get info on this machine (This sets up A1 - among other things -- to point to product info)
btst #test,d7 ;burn-in flag set? <4>
bne.s @OnTester ;yes,we're on a tester so perform the diagRom check<4>
; If not in test, we want to make a squawk here, so set up regs for Error Beep. <4>
cmp.b #YMCADecoder,DecoderKind(a1) ; Do we have a YMCA (can't test for DSP 'cause we have no memory and it's in the ; <SM3> fau
bne.s @DoASC ; no, assume it's an ASC <SM3> fau
movea.l #1,a1 ; Tell CycloneBeep to play sound #1 <SM3> fau
BigBSR6 CycloneBeep,a0 ; And go play it... <SM3> fau
bra.l TMEntry1 ; then go to Test Manager <4>
@DoASC
movea.l ASCAddr(a0),a3 ;setup ASC address for BootBeep6 <4>
movea.l VIA1Addr(a0),a5 ;setup VIA1 address for Beep <1.2><4>
BigBSR6 ErrorBeep1,a0 ;the first of several squawks... <4>
bra.l TMEntry1 ;then go to Test Manager <4>
@OnTester ; <4>
btst.l #DiagROMExists,d0 ;do we support a diagnostic rom? <9><4>
beq.s @noDiagRom ;no, continue <4>
lea @noDiagRom,a6 ;yes, load up return address <4>
bset #beok,d7 ;then tell the handler its ok <4>
move.l DiagROMAddr(a0),a1 ;get start of diagnostic ROM <4>
movem.l (a1)+,d0/a0 ;getting the vector....bus error to @noDiagRom <4>
cmpi.l #TROMCode,d0 ;didn't bus error, see if codes match <4>
bne.s @noDiagRom ;don't match,we're not on a tester continue <4>
lea @noDiagRom,a1 ;in case we're returning via A1... <4>
jmp (a0) ;jump into diagnostic rom <4>
@noDiagRom ; <4>
bclr #beok,d7 ;clear the BusError is OK flag <4>
;removed conditionals for HcMac (laguna) since laguna is not meant to run this code [v1.2>
;i.e. the error1handler for laguna and 68000 based macs is in reality error2handler [v1.2>
; Now if we got here and we are testing (VIA looped) then lets queue
; up the boot message for the host.
bset #MsgQ,d7 ;queue up the message
bset #timer,d7 ;use timer for message timing
; The VIA 1 timer must be started up with extended count in d4.hw
move.w #sec,d4 ;set extended timer count
BigBSR6 StartTimer,a0 ;start timer <v1.4>
; Flush and enable the appropriate I-Cache
movec CACR,d0 ; retrieve current CACR <T2>|
bset #15,d0 ; set 040 "enable I-Cache" bit to see if we're on an 040 V
movec d0,CACR ; set the bit to see if it sticks
movec CACR,d0 ;
btst #15,d0 ; are we on an 040?
beq.s @notAn040 ; IF we're on an 040 THEN
MACHINE MC68040 ; perform 040 cache flush, I-cache is already enabled
cinva ic ; invalidate (flush) the instruction cache
bra.s @go ; continue
MACHINE MC68030 ;
@notAn040 ; ELSE
movec CACR,d0 ; examine cache control register
bset #3,d0 ; flush instruction cache
movec d0,CACR ; execute flush
movec CACR,d0 ; read new cache control register
ori.b #$11,d0 ; enable i-cache and burst mode
movec d0,CACR ; do it
@go ; ENDIF <T2>
bra.l TMEntry1 ;then go to Test Manager
;-----------------
; Handle an error that occurred after the video was initialized, unless
; we happen to be in service, then just continue to Test Manager.
Error2Handler
moveq #0,d2
BSR6 JGetHardwareInfo ;Get info on this machine (This sets up A1 - among other things -- to point to product info)
movea.l ASCAddr(a0),a3 ;setup ASC address for BootBeep6
movea.l VIA1Addr(a0),a2 ;setup VIA1 address for quasi call <1.2>
btst #test,d7 ;in service? [C202>
bne.s @10 ;yes, go to Test Manager [C202>
cmp.b #YMCADecoder,DecoderKind(a1) ; Do we have a YMCA (can't test for DSP 'cause we have no memory and it's in the <SM3> fau
bne.s @DoASC ; no, assume it's an ASC <SM3> fau
movea.l #2,a1 ; Tell CycloneBeep to play sound #1 <SM3> fau
BigBSR6 CycloneBeep,a0 ; And go play it... <SM3> fau
BigJmp CritErr,a0 ;display the error data if possible,
@DoASC
movea.l a2,a5 ;get VIA1 base in a5 now
BigBSR6 ErrorBeep1,a0 ;the first of several squawks...
BigJmp CritErr,a0 ;display the error data if possible,
;CritErr will return to Test Manager
@10
@20 bra.l TMEntry1 ;go to Test Manager
;-----------------
; An error occurred during RAMTest call, beep appropriately and display error
Error3Handler
moveq #0,d2
BSR6 JGetHardwareInfo ;Get info on this machine (This sets up A1 - among other things -- to point to product info)
movea.l ASCAddr(a0),a3 ;setup ASC address for BootBeep6
movea.l VIA1Addr(a0),a5 ;setup VIA1 address for Beep <1.2>
cmp.b #YMCADecoder,DecoderKind(a1) ; Do we have a YMCA (can't test for DSP 'cause we have no memory and it's in the <SM3> fau
bne.s @DoASC ; no, assume it's an ASC <SM3> fau
movea.l #3,a1 ; Tell CycloneBeep to play sound #1 <SM3> fau
BigBSR6 CycloneBeep,a0 ; And go play it... <SM3> fau
BigJmp CritErr,a0 ; display the error data if possible,
@DoASC
BigBSR6 ErrorBeep2,a0 ;the second of several squawks...
BigJmp CritErr,a0 ;display the error data if possible,
;CritErr will return to Test Manager
Error4Handler
moveq #0,d2
BSR6 JGetHardwareInfo ;Get info on this machine (This sets up A1 - among other things -- to point to product info)
movea.l ASCAddr(a0),a3 ;setup ASC address for BootBeep6
movea.l VIA1Addr(a0),a5 ;setup VIA1 address for Beep <1.2>
cmp.b #YMCADecoder,DecoderKind(a1) ; Do we have a YMCA (can't test for DSP 'cause we have no memory and it's in the <SM3> fau
bne.s @DoASC ; no, assume it's an ASC <SM3> fau
movea.l #4,a1 ; Tell CycloneBeep to play sound #1 <SM3> fau
BigBSR6 CycloneBeep,a0 ; And go play it... <SM3> fau
BigJmp CritErr,a0 ; display the error data if possible,
@DoASC
BigBSR6 ErrorBeep3,a0 ;the third of several squawks...
BigJmp CritErr,a0 ;display the error data if possible,
;CritErr will return to Test Manager
ENDWITH
;--------------------------------------- [v1.5>
; Entry to NCErrorHandler indicates that a non-critical error has occurred [v1.5>
; sometime while running a "nonessential" subsystem like the SCC or Sound [v1.5>
; results are logged to the last 8 bytes of parameter ram as follows: <v1.0>
; byte 120 (240) - d6.uub <v1.1>
; 121 (241) - d6.mub <v1.1>
; 122 (242) - d6.mlb <v1.1>
; 123 (243) - d6.llb <v1.1>
; 124 (---) - d7.uub <v1.1>
; 125 (---) - d7.mub <v1.1>
; 126 (250) - d7.mlb <v1.1>
; 127 (251) - d7.llb <v1.1>
; <v1.1>
; In addition, the flag byte (112 for PowerMgr systems, 249 for 030 systems) <v1.1>
; has its lsbit set to indicate that parameter ram contains non-critical error <v1.1>
; information. <v1.1>
;
NCErrorHandler ; <v1.5>
cmpi.l #-1,d6 ;is this a fail/no-log? <v1.5>
beq.w @finish ;yes, return immediately
move.l DecoderInfo.VIA1Addr(a0),a2 ;else, get VIA1 base address
@log
; <v1.1>
BSR6 ClkWpOff ;turn off write protect to clock chip <v1.1>
move.w #NCFailFlag,d1 ;read flag byte <v1.1>
BSR6 RdXbyte ;read parameter ram <v1.1>
bset.l #0,d1 ;set lsb of flag to indicate non-crit data <v1.1>
bne.s @not1st ;if this is not the first error, continue
move.b d1,d2 ;move new flag into data byte <v1.1>
move.w #NCFailFlag,d1 ;get address byte to send <v1.1>
BSR6 WrXByte ;write parameter ram <v1.1>
move.l #(NCFailHist<<16 | NCHistBytes-1),d4 ;prepare to zero history
@zero swap d4 ;get the PRAM address
move.w d4,d1 ;put it in the proper register
addq.w #1,d4 ;go to next location
moveq.l #0,d2 ;value to write (zero)
BSR6 WrXByte ;go write it
swap d4 ;see if we're done
dbra.w d4,@zero ;continue until done
@not1st
move.l #((NCFailHist+NCHistBytes)<<16 | NCHistBytes-2),d4 ;prepare to roll history
@roll swap d4 ;get source address
subq.w #2,d4 ;adjust it
move.w d4,d1 ;read from this address
BSR6 RdXByte ;perform the read
move.b d1,d2 ;take the result
addq.w #1,d4 ;and write it to the next location
move.w d4,d1 ;modified address goes here
BSR6 WrXByte ;perform the write
swap d4 ;retrieve the count
dbra.w d4,@roll ;and keep going until we're done
move.w #NCFailHist,d1 ;now store the new failed test #
move.b d7,d2 ;here's the test number
BSR6 WrXByte ;write it
move.l #(NCLastFailure<<16 | NCLstFailBytes-1),d4 ;prepare to store the error code
@result
swap d4 ;get the destination address
move.w d4,d1 ;prepare it for the PRAM write
addq.l #1,d4 ;increment it
rol.l #8,d6 ;get the next byte of d6
move.b d6,d2 ;prepare to write it
BSR6 WrXByte ;perform the write
swap d4 ;now retrieve the byte count
dbra.w d4,@result ;and keep going until done
@finish
rts ;return to caller <v1.1>
EndProc
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