502 lines
21 KiB
Plaintext
502 lines
21 KiB
Plaintext
;
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; File: SonicEqu.a
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;
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; Contains: Sonic-specific equates
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;
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; Written by: Sean Findley
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;
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; Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved.
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;
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; This file is used in these builds: Mac32
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;
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; Change History (most recent first):
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;
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; <1> 10/6/92 GDW New location for ROMLink tool.
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; <1> 6/12/92 RLM first checked in
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; <P2> 02/07/92 jmp (jmp,H2/BG/SJF,Z4) Rolled in SMOVE macro def and SonicAddress
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; def.
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; <1> 2/4/92 mal first checked in
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; ———————————————————————————————————————————————————————————————————————————————————————
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; Pre-Pandora ROM comments begin here.
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; ———————————————————————————————————————————————————————————————————————————————————————
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; <3> 2/26/91 JK Added extended Motorola mode equates.
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; <2> 1/30/91 JK Added code review changes.
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; <1> 12/14/90 JK Added to build
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;
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; To Do:
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;
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; SonicEqu.a - Equates for SONIC
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; written by Sean J. Findley Jan. 1990
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; Copyright (c) 1990 Apple Computer, Inc.
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MACRO
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CtlRegPad
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IF CTLPAD THEN
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ORG *+2
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ENDIF
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ENDM
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MACRO ; <Z4> thru next <Z4>
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SMOVE &src,&dest
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IF SONIC32 THEN
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MOVE.L &src,&dest
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ELSE
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MOVE.W &src,&dest
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ENDIF
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ENDM ; <Z4>
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;•••••••••••••••• SONIC Registers
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SONICRegs RECORD 0
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IF SONIC32 THEN
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Command DS.L 1 ; (CR) SONIC control
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Data_Config DS.L 1 ; (DCR) packet configuration
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Recv_Control DS.L 1 ; (RCR) pkt reception control
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Trans_Control DS.L 1 ; (TCR) Transmission control
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Int_Mask DS.L 1 ; (IMR) interrupt mask
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Int_Status DS.L 1 ; (ISR) interrupts status bits
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Upper_TDA DS.L 1 ; (UTDA) upper 16 bits of TDA address
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Current_TDA DS.L 1 ; (CTDA) 16 bit ptr to current TDA
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Trans_PktSize DS.L 1 ; (TPS) total size of outbound pkt
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Trans_FragCount DS.L 1 ; (TFC) transmit fragment count
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Trans_PktStart0 DS.L 1 ; (TSA0) lower 16 bit of pkt addr
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Trans_PktStart1 DS.L 1 ; (TSA1) upper "
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Trans_FragSize DS.L 1 ; (TFS) current fragment size
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Upper_RDA DS.L 1 ; (URDA) upper 16 bits of RDA address
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Current_RDA DS.L 1 ; (CRDA) 16 bit ptr to current RDA
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Recv_RBA0 DS.L 1 ; (CRBA0) lower 16 bit receive addr in RBA
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Recv_RBA1 DS.L 1 ; (CRBA1) upper 16 bit recive addr in RBA
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Buff_Cnt0 DS.L 1 ; (RBWC0) lower 16 bit of word count in RBA
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Buff_Cnt1 DS.L 1 ; (RBWC1) upper "
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End_Buff DS.L 1 ; (EOBC) end of buffer word count
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Upper_RRA DS.L 1 ; (URRA) upper 16 bits of RRA address
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RRA_Start DS.L 1 ; (RSA) 16 bit ptr to RRA
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RRA_End DS.L 1 ; (REA) 16 bit ptr to end of RRA
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RRA_Read DS.L 1 ; (RRP) where SONIC gets next read resource
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RRA_Write DS.L 1 ; (RWP) where host puts new read resources
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TRBA0 DS.L 1 ; (TRBA0) used by SONIC
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TRBA1 DS.L 1 ; (TRBA1) "
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TBWC0 DS.L 1 ; (TBWC0) "
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TBWC1 DS.L 1 ; (TBWC1) "
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ADDR0 DS.L 1 ; (ADDR0) "
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ADDR1 DS.L 1 ; (ADDR1) "
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LLFA DS.L 1 ; (LLFA) "
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TTDA DS.L 1 ; (TTDA) "
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CAM_EntryPtr DS.L 1 ; (CEP) points to CAM cell
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CAM_Port2 DS.L 1 ; (CAP2) selects upper 16 bits of CAM cell
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CAM_Port1 DS.L 1 ; (CAP1) selects middle 16 bits of CAM cell
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CAM_Port0 DS.L 1 ; (CAP0) selects lower 16 bits of CAM cell
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CAM_Enable DS.L 1 ; (CE) CAM enable register turns cells on/off
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CAM_DescPtr DS.L 1 ; (CDP) 16 bit ptr to current CAM descriptor
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CAM_Count DS.L 1 ; (CDC) count of CAM descriptors
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Silicon_Rev DS.L 1 ; (SR) rev info on SONIC chip
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Timer0 DS.L 1 ; (WT0) lower 16 bits of SONCIC timer
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Timer1 DS.L 1 ; (WT1) upper 16 "
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Recv_SeqCnt DS.L 1 ; (RSC) receive sequence counter
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CRC_Err DS.L 1 ; (CRCT) CRC error count
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FAE_Err DS.L 1 ; (FAET) frame alignment error count
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MissedPkt_Err DS.L 1 ; (MPT) missed packet error count
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MDT DS.L 1 ; (MDT) max. deferral timer
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RTC DS.L 1 ; (RTC) receive test control
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TTC DS.L 1 ; (TTC) transmit test control
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DTC DS.L 1 ; (DTC) DMA test control
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CC0 DS.L 1 ; (CC0) CAM comparison 0
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CC1 DS.L 1 ; (CC1) CAM comparison 1
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CC2 DS.L 1 ; (CC2) CAM comparison 2
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CM DS.L 1 ; (CM) CAM match
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res1 DS.L 2 ; reserved by National Semiconductor
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RBC DS.L 1 ; (RBC) receiver byte count
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res2 DS.L 1 ; reserved by National Semiconductor
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TBO DS.L 1 ; (TBO) transmit backoff counter
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TRC DS.L 1 ; (TRC) transmit random counter
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TBM DS.L 1 ; (TBM) transmit backoff mask
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res3 DS.L 1 ; reserved by National Semiconductor
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Data_Config2 DS.L 1 ; extended data configiguration
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ELSE
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Command DS.W 1 ; (CR) SONIC control
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CtlRegPad
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Data_Config DS.W 1 ; (DCR) packet configuration
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CtlRegPad
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Recv_Control DS.W 1 ; (RCR) pkt reception control
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CtlRegPad
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Trans_Control DS.W 1 ; (TCR) Transmission control
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CtlRegPad
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Int_Mask DS.W 1 ; (IMR) interrupt mask
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CtlRegPad
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Int_Status DS.W 1 ; (ISR) interrupts status bits
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CtlRegPad
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Upper_TDA DS.W 1 ; (UTDA) upper 16 bits of TDA address
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CtlRegPad
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Current_TDA DS.W 1 ; (CTDA) 16 bit ptr to current TDA
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CtlRegPad
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Trans_PktSize DS.W 1 ; (TPS) total size of outbound pkt
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CtlRegPad
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Trans_FragCount DS.W 1 ; (TFC) transmit fragment count
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CtlRegPad
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Trans_PktStart0 DS.W 1 ; (TSA0) lower 16 bit of pkt addr
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CtlRegPad
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Trans_PktStart1 DS.W 1 ; (TSA1) upper "
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CtlRegPad
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Trans_FragSize DS.W 1 ; (TFS) current fragment size
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CtlRegPad
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Upper_RDA DS.W 1 ; (URDA) upper 16 bits of RDA address
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CtlRegPad
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Current_RDA DS.W 1 ; (CRDA) 16 bit ptr to current RDA
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CtlRegPad
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Recv_RBA0 DS.W 1 ; (CRBA0) lower 16 bit receive addr in RBA
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CtlRegPad
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Recv_RBA1 DS.W 1 ; (CRBA1) upper 16 bit recive addr in RBA
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CtlRegPad
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Buff_Cnt0 DS.W 1 ; (RBWC0) lower 16 bit of word count in RBA
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CtlRegPad
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Buff_Cnt1 DS.W 1 ; (RBWC1) upper "
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CtlRegPad
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End_Buff DS.W 1 ; (EOBC) end of buffer word count
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CtlRegPad
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Upper_RRA DS.W 1 ; (URRA) upper 16 bits of RRA address
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CtlRegPad
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RRA_Start DS.W 1 ; (RSA) 16 bit ptr to RRA
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CtlRegPad
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RRA_End DS.W 1 ; (REA) 16 bit ptr to end of RRA
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CtlRegPad
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RRA_Read DS.W 1 ; (RRP) where SONIC gets next read resource
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CtlRegPad
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RRA_Write DS.W 1 ; (RWP) where host puts new read resources
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CtlRegPad
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TRBA0 DS.W 1 ; (TRBA0) used by SONIC
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CtlRegPad
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TRBA1 DS.W 1 ; (TRBA1) "
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CtlRegPad
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TBWC0 DS.W 1 ; (TBWC0) "
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CtlRegPad
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TBWC1 DS.W 1 ; (TBWC1) "
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CtlRegPad
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ADDR0 DS.W 1 ; (ADDR0) "
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CtlRegPad
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ADDR1 DS.W 1 ; (ADDR1) "
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CtlRegPad
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LLFA DS.W 1 ; (LLFA) "
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CtlRegPad
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TTDA DS.W 1 ; (TTDA) "
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CtlRegPad
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CAM_EntryPtr DS.W 1 ; (CEP) points to CAM cell
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CtlRegPad
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CAM_Port2 DS.W 1 ; (CAP2) selects upper 16 bits of CAM cell
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CtlRegPad
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CAM_Port1 DS.W 1 ; (CAP1) selects middle 16 bits of CAM cell
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CtlRegPad
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CAM_Port0 DS.W 1 ; (CAP0) selects lower 16 bits of CAM cell
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CtlRegPad
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CAM_Enable DS.W 1 ; (CE) CAM enable register turns cells on/off
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CtlRegPad
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CAM_DescPtr DS.W 1 ; (CDP) 16 bit ptr to current CAM descriptor
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CtlRegPad
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CAM_Count DS.W 1 ; (CDC) count of CAM descriptors
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CtlRegPad
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Silicon_Rev DS.W 1 ; (SR) rev info on SONIC chip
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CtlRegPad
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Timer0 DS.W 1 ; (WT0) lower 16 bits of SONCIC timer
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CtlRegPad
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Timer1 DS.W 1 ; (WT1) upper 16 "
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CtlRegPad
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Recv_SeqCnt DS.W 1 ; (RSC) receive sequence counter
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CtlRegPad
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CRC_Err DS.W 1 ; (CRCT) CRC error count
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CtlRegPad
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FAE_Err DS.W 1 ; (FAET) frame alignment error count
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CtlRegPad
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MissedPkt_Err DS.W 1 ; (MPT) missed packet error count
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CtlRegPad
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MDT DS.W 1 ; (MDT) max. deferral timer
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CtlRegPad
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RTC DS.W 1 ; (RTC) receive test control
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CtlRegPad
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TTC DS.W 1 ; (TTC) transmit test control
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CtlRegPad
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DTC DS.W 1 ; (DTC) DMA test control
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CtlRegPad
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CC0 DS.W 1 ; (CC0) CAM comparison 0
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CtlRegPad
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CC1 DS.W 1 ; (CC1) CAM comparison 1
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CtlRegPad
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CC2 DS.W 1 ; (CC2) CAM comparison 2
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CtlRegPad
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CM DS.W 1 ; (CM) CAM match
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CtlRegPad
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res1 DS.W 2 ; reserved by National Semiconductor
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CtlRegPad
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RBC DS.W 1 ; (RBC) receiver byte count
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CtlRegPad
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res2 DS.W 1 ; reserved by National Semiconductor
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CtlRegPad
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TBO DS.W 1 ; (TBO) transmit backoff counter
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CtlRegPad
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TRC DS.W 1 ; (TRC) transmit random counter
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CtlRegPad
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TBM DS.W 1 ; (TBM) transmit backoff mask
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CtlRegPad
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res3 DS.W 1 ; reserved by National Semiconductor
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CtlRegPad
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Data_Config2 DS.W 1 ; extended data configiguration
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ENDIF
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ENDR
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;•••••••••••••••• Content Addressable Memory (CAM) Descriptor Area CDA
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CAMDesc RECORD 0
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IF SONIC32 THEN
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Entry_ptr DS.L 1 ; base zero index to CAM cell
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Port2 DS.L 1 ; lower 16 bits in cell
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Port1 DS.L 1 ; middle 16 bits in cell
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Port0 DS.L 1 ; upper 16 bits in cell
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enable DS.L 1 ; CAM cell enable mask
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ELSE
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Entry_ptr DS.W 1 ; base zero index to CAM cell
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Port2 DS.W 1 ; lower 16 bits in cell
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Port1 DS.W 1 ; middle 16 bits in cell
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Port0 DS.W 1 ; upper 16 bits in cell
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enable DS.W 1 ; CAM cell enable mask
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ENDIF
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CAMDescSz EQU *
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ENDR
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;•••••••••••••••• Receive Resource Descriptor Area RRA
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RRArec RECORD 0
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IF SONIC32 THEN
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buff_ptr0 DS.L 1 ; lower 16 bits of RBA address
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buff_ptr1 DS.L 1 ; upper 16 bits of RBA address
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buff_wc0 DS.L 1 ; lower 16 bits of RBA word count
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buff_wc1 DS.L 1 ; upper 16 bits of RBA word count
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ELSE
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buff_ptr0 DS.W 1 ; lower 16 bits of RBA address
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buff_ptr1 DS.W 1 ; upper 16 bits of RBA address
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buff_wc0 DS.W 1 ; lower 16 bits of RBA word count
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buff_wc1 DS.W 1 ; upper 16 bits of RBA word count
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ENDIF
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RRArecSz EQU *
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ENDR
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;•••••••••••••••• Receive Descriptor Area RDA
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Rxpkt RECORD 0
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; this link is used to keep rx descriptors on our own list(s) when SONIC is not using them
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nextRD DS.L 1 ; internal ptr to next descriptor
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isFree DS.B 1 ; = true if desc has been freed
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ORG nextRD
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IF SONIC32 THEN
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status DS.L 1 ; receive status
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byte_count DS.L 1 ; size of packet read
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pkt_ptr0 DS.L 1 ; lower 16 bits of packet addr. in RBA
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pkt_ptr1 DS.L 1 ; upper 16 bits of packet addr. in RBA
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seq_no DS.L 1 ; sequence number
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link DS.L 1 ; link to other RD
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in_use DS.L 1 ; use flag
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ELSE
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status DS.W 1 ; receive status
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byte_count DS.W 1 ; size of packet read
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pkt_ptr0 DS.W 1 ; lower 16 bits of packet addr. in RBA
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pkt_ptr1 DS.W 1 ; upper 16 bits of packet addr. in RBA
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seq_no DS.W 1 ; sequence number
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link DS.W 1 ; link to other RD
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in_use DS.W 1 ; use flag
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ENDIF
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RxRDAsize EQU *
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ENDR
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;•••••••••••••••• Transmit Descriptor Area TDA
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Max_Tx_Frags EQU 16 ; maximum fragments supported for a transmit
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Txpkt RECORD 0 ; Transmit Descriptor
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; this link is used to keep tx descriptors on our own list when SONIC is not using them
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nextTD DS.L 1 ; internal ptr to next descriptor
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ORG nextTD
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IF SONIC32 THEN
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status DS.L 1 ; status info written by SONIC
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config DS.L 1 ; pre-transmit config data
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pkt_size DS.L 1 ; size of packet
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frag_count DS.L 1 ; fragment count
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frag_start EQU * ; start of individual fragments
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; the following 3 fields are repeated 1..frag_count
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frag_ptr0 DS.L 1 ; lower 16 bits of address
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frag_ptr1 DS.L 1 ; upper "
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frag_size DS.L 1 ; fragment size
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frag_esize EQU * - frag_start ; size of individual fragments
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ORG * + (Max_Tx_Frags-1) * frag_esize
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; allocate rest of fragments
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link DS.L 1 ; lower 16 bits of next TD (if any)
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ELSE
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status DS.W 1 ; status info written by SONIC
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config DS.W 1 ; pre-transmit config data
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pkt_size DS.W 1 ; size of packet
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frag_count DS.W 1 ; fragment count
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frag_start EQU * ; start of individual fragments
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; the following 3 fields are repeated 1..frag_count
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frag_ptr0 DS.W 1 ; lower 16 bits of address
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frag_ptr1 DS.W 1 ; upper "
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frag_size DS.W 1 ; fragment size
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frag_esize EQU * - frag_start ; size of individual fragments
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ORG * + (Max_Tx_Frags-1) * frag_esize
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; allocate rest of fragments
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link DS.W 1 ; lower 16 bits of next TD (if any)
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ENDIF
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TxTDAsize EQU * ; size of a single frame TD
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ENDR
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;•••••••••••••••• Initialization Parameters
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SONICinitParms RECORD 0
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SONICbase DS.L 1 ; base address of SONIC registers
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IntInstall DS.L 1 ; addr of proc that installs interrupt handler
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RECVRtn DS.L 1 ; address of receive routine
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RECVPrms DS.L 1 ; parms to pass @ receive
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TRANRtn DS.L 1 ; address of xmit complete routine
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TRANPrms DS.L 1 ; parms to pass @ xmit complete
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MemStart DS.L 1 ; address of memory usage area
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MemSize DS.L 1 ; size of memory usage area
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NumRxBuffs DS.L 1 ; proposed # of receive buffers
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IntDisable DS.L 1 ; proc to disable interrupts
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IntEnable DS.L 1 ; proc to reenable interrupts
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NetStatArray DS.L 1 ; ptr to network statistics array
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DataConfig DS.L 1 ; data configuration value
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TransAddr DS.L 1 ; ->proc to translate logical->physical address
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ParmSize EQU *
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ENDR
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;•••••••••••••••• CAM Parameters
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CAMparms RECORD 0
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SONICPtr DS.L 1 ; SONIC base address <Z4>
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EAddr DS.B 6 ; Ethernet address
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LoadorClear DS.L 1 ; ≠ 0 if adding CAM entry
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ParmSize EQU *
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ENDR
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;•••••••••••••••• (CR) Command Register Bits
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LoadCAM EQU 9 ; load content addressable memory
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ReadRRA EQU 8 ; read next read resource descriptor
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SoftReset EQU 7 ; do a software reset
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StartTimer EQU 5 ; start watchdog timer
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StopTimer EQU 4 ; stop "
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RxEnable EQU 3 ; receive packets
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RxDisable EQU 2 ; stop receiving packets
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TxEnable EQU 1 ; transmit packets
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TxDisable EQU 0 ; stop transmitting packets
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;•••••••••••••••• (RCR) Receive Control/Status Register Bits
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RecvErrors EQU 15 ; accept/reject packets with errors
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RecvRunts EQU 14 ; accept/reject runt packets
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RecvBroadCast EQU 13 ; accept/reject broadcasts
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RecvAll EQU 12 ; turn on/off promiscuious mode
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RecvMultiCast EQU 11 ; accept/reject multicasts
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NoLoopBack EQU $0000 ; mask for no loopback
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MACLoopBack EQU $0200 ; mask for MAC loopback
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ENDECLoopBack EQU $0400 ; mask for ENDEC loopback
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TxRxLoopBack EQU $0600 ; mask for Transceiver loopback
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MultiRecd EQU 8 ; set when multicast is received
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BroadRecd EQU 7 ; set when broadcast is received
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RBAEmpty EQU 6 ; set when out of buffers in RBA
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CarrierSense EQU 5 ; set when net busy and CRS is active
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CollisionSense EQU 4 ; set when collision occurs if COL active
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CRCErr EQU 3 ; set if packet has CRC error
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FramAlignErr EQU 2 ; set if frame not aligned
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LoopBackRecd EQU 1 ; set when loopback is received
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ReceivedOK EQU 0 ; set upon successful packet reception
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;•••••••••••••••• (TCR) Transmit Control/Status Register Bits
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TxProgInt EQU 15 ; generate a software interrupt
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OWCTimer EQU 14 ; "out of window collision" timer control
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CRCInhibit EQU 13 ; turn on/off FCS field
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ExDeferTimer EQU 12 ; turn on/off excessive defer timer
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ExcessDefer EQU 10 ; excessive deferrals detected
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DeferredTx EQU 9 ; set when packet is being deferred
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NoCRS EQU 8 ; CRS not present during transmission
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CRSLost EQU 7 ; bad CRS during transmission
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ExcessColl EQU 6 ; > 16 collisions detected
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OutWindow EQU 5 ; "out of window" collision detected
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PktMonitorBad EQU 3 ; packet monitored as bad
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FIFOUnderRun EQU 2 ; Tx FIFO underrun
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BCMismatch EQU 1 ; TxPkt_size ≠ sum(TxFrag_size)
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TransmitOK EQU 0 ; packet transmitted successfuly
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;•••••••••••••••• (DCR) Data Configuration Register Bits
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EXBUS EQU 15 ; extended bus mode
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LatchBusRetry EQU 13 ; LBR
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DConfig_Usr1 EQU 12 ; sets/resets pin USR1
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DConfig_Usr0 EQU 11 ; sets/resets pin USR0
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SynchTerm EQU 10 ; select sync/async input to DMA
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WaitCtl0 EQU $0000 ; 0 bus cycles added to DMA
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WaitCtl1 EQU $0040 ; 1 bus cycle added to DMA
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WaitCtl2 EQU $0080 ; 2 bus cycles added to DMA
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WaitCtl3 EQU $00C0 ; 3 bus cycles added to DMA
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DataWidth EQU 5 ; 16/32 bit path width for DMA
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BlockMode EQU 4 ; DMA block mode selection
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RFT2 EQU $0000 ; 2 word recv FIFO threshold
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RFT4 EQU $0004 ; 4 word recv FIFO threshold
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RFT8 EQU $0008 ; 8 word recv FIFO threshold
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RFT12 EQU $000C ; 12 word recv FIFO threshold
|
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TFT4 EQU $0000 ; 4 word trans FIFO threshold
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TFT8 EQU $0001 ; 8 word trans FIFO threshold
|
|
TFT12 EQU $0002 ; 12 word trans FIFO threshold
|
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TFT14 EQU $0003 ; 14 word trans FIFO threshold
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|
|
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;•••••••••••••••• (DCR2) Extended Data Configuration Register Bits
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|
EXUSR3 EQU 15 ; extended user bits
|
|
EXUSR2 EQU 14
|
|
EXUSR1 EQU 13
|
|
EXUSR0 EQU 12
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|
|
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;•••••••••••••••• (ISR) Interrupt Status Register Bits
|
|
BusRetry EQU 14 ; set when bus needed retry
|
|
LostHeartBeat EQU 13 ; set when heartbeat is lost
|
|
DoneLoadCAM EQU 12 ; set when load CAM operation is done
|
|
GetProgInt EQU 11 ; set when programmable int. occurs
|
|
RecdPkt EQU 10 ; set when a packet has been recd.
|
|
TransDone EQU 9 ; set when trans is finished
|
|
TransError EQU 8 ; set when trans finished with an error
|
|
TimerElapsed EQU 7 ; set when timer reaches zero
|
|
EmptyRDA EQU 6 ; set when receive descriptors exhausted
|
|
EmptyRRA EQU 5 ; set when receive resources exhausted
|
|
RBAOverFLow EQU 4 ; set when buffer area is full
|
|
CRCRollover EQU 3 ; set when CRC tally has reached $FFFF
|
|
FAERollover EQU 2 ; set when FAE tally has reached $FFFF
|
|
MPRollover EQU 1 ; set when MP tally has reached $FFFF
|
|
RxFIFORollover EQU 0 ; set when Rx FIFO overflows
|
|
|
|
OurIntsMask EQU (1 << BusRetry) + \
|
|
(1 << RecdPkt) + \
|
|
(1 << TransDone) + \
|
|
(1 << TimerElapsed) + \
|
|
(1 << RxFIFORollover) + \
|
|
(1 << RBAOverFlow) + \
|
|
(1 << EmptyRRA)
|
|
|
|
;•••••••••••••••• Network Statistics
|
|
NetStats RECORD 0 ; network management stats.
|
|
TxOK DS.L 1 ; frames transmitted OK
|
|
sCollFrame DS.L 1 ; single collision frames
|
|
mCollFrame DS.L 1 ; multiple collision frames
|
|
CollFrame DS.L 1 ; collision frames
|
|
DefTx DS.L 1 ; deferred transmissions
|
|
LateColl DS.L 1 ; late collisions
|
|
ExcessColl DS.L 1 ; excessive collisions
|
|
ExcessDef DS.L 1 ; excessive defferals
|
|
InMACTxErr DS.L 1 ; internal MAC transmit errors
|
|
RxOK DS.L 1 ; frames received OK
|
|
MultiRxOK DS.L 1 ; multicast frames recd OK
|
|
BroadRxOK DS.L 1 ; broadcast frames recd OK
|
|
FCSerr DS.L 1 ; frame check sequence errors
|
|
FAerr DS.L 1 ; frame alignment errors
|
|
MPerr DS.L 1 ; missed packet errors
|
|
Size EQU *
|
|
ENDR
|
|
|
|
;•••••••••••••••• General Equates
|
|
TalliesPerSec EQU 5000000 ; number of timer ticks/second
|
|
TxMaxRetries EQU 4 ; max attempts to retry aborted xmits
|
|
Max_Tx_Packets EQU 16 ; maximum # of chained Tx packets
|
|
Min_Pkt_Size EQU 60 ; minimum packet size
|
|
Min_Rx_Buffs EQU 2 ; minimum # of recv descriptors/buffers
|
|
Max_Pkt_Size EQU 1518 ; maximum packet size (inc. CRC)
|
|
EOL_Bit EQU 0 ; end-of-link bit
|
|
Ctl_Mem_Size EQU Txpkt.TxTDAsize*Max_Tx_Packets+ \; up to Max_Tx_Packets chained transmits
|
|
RRArec.RRArecSz+ \; 1 RRA descriptor
|
|
CAMDesc.CAMDescSz ; 1 CAM descriptor
|
|
Min_Mem_Size EQU Ctl_Mem_Size+ \
|
|
Max_Pkt_Size*Min_Rx_Buffs+ \; max. size packets
|
|
Rxpkt.RxRDAsize*Min_Rx_Buffs; recv. descriptors
|