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361 lines
11 KiB
C++
361 lines
11 KiB
C++
// Copyright 2014 The Chromium Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// This file is an internal atomic implementation, use base/atomicops.h instead.
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// TODO(rmcilroy): Investigate whether we can use __sync__ intrinsics instead of
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// the hand coded assembly without introducing perf regressions.
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// TODO(rmcilroy): Investigate whether we can use acquire / release versions of
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// exclusive load / store assembly instructions and do away with
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// the barriers.
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#ifndef BASE_ATOMICOPS_INTERNALS_ARM64_GCC_H_
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#define BASE_ATOMICOPS_INTERNALS_ARM64_GCC_H_
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#if defined(OS_QNX)
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#include <sys/cpuinline.h>
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#endif
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namespace base {
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namespace subtle {
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inline void MemoryBarrier() {
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__asm__ __volatile__ ( // NOLINT
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"dmb ish \n\t" // Data memory barrier.
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::: "memory"
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); // NOLINT
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}
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[prev], %[ptr] \n\t" // Load the previous value.
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"cmp %w[prev], %w[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %w[new_value], %[ptr] \n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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"1: \n\t"
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"clrex \n\t" // In case we didn't swap.
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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Atomic32 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[result], %[ptr] \n\t" // Load the previous value.
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"stxr %w[temp], %w[new_value], %[ptr] \n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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: [result]"=&r" (result),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [new_value]"r" (new_value)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[result], %[ptr] \n\t" // Load the previous value.
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"add %w[result], %w[result], %w[increment]\n\t"
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"stxr %w[temp], %w[result], %[ptr] \n\t" // Try to store the result.
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"cbnz %w[temp], 0b \n\t" // Retry on failure.
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: [result]"=&r" (result),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [increment]"r" (increment)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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MemoryBarrier();
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Atomic32 result = NoBarrier_AtomicIncrement(ptr, increment);
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MemoryBarrier();
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return result;
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}
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[prev], %[ptr] \n\t" // Load the previous value.
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"cmp %w[prev], %w[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %w[new_value], %[ptr] \n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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"dmb ish \n\t" // Data memory barrier.
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"1: \n\t"
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// If the compare failed the 'dmb' is unnecessary, but we still need a
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// 'clrex'.
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"clrex \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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int32_t temp;
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MemoryBarrier();
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[prev], %[ptr] \n\t" // Load the previous value.
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"cmp %w[prev], %w[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %w[new_value], %[ptr] \n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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"1: \n\t"
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// If the compare failed the we still need a 'clrex'.
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"clrex \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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MemoryBarrier();
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}
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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MemoryBarrier();
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*ptr = value;
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}
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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return *ptr;
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}
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inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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Atomic32 value = *ptr;
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MemoryBarrier();
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return value;
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}
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inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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MemoryBarrier();
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return *ptr;
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}
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// 64-bit versions of the operations.
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// See the 32-bit versions for comments.
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inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[prev], %[ptr] \n\t"
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"cmp %[prev], %[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %[new_value], %[ptr] \n\t"
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"cbnz %w[temp], 0b \n\t"
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"1: \n\t"
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"clrex \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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Atomic64 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[result], %[ptr] \n\t"
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"stxr %w[temp], %[new_value], %[ptr] \n\t"
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"cbnz %w[temp], 0b \n\t"
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: [result]"=&r" (result),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [new_value]"r" (new_value)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[result], %[ptr] \n\t"
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"add %[result], %[result], %[increment] \n\t"
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"stxr %w[temp], %[result], %[ptr] \n\t"
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"cbnz %w[temp], 0b \n\t"
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: [result]"=&r" (result),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [increment]"r" (increment)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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MemoryBarrier();
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Atomic64 result = NoBarrier_AtomicIncrement(ptr, increment);
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MemoryBarrier();
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return result;
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}
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inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[prev], %[ptr] \n\t"
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"cmp %[prev], %[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %[new_value], %[ptr] \n\t"
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"cbnz %w[temp], 0b \n\t"
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"dmb ish \n\t"
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"1: \n\t"
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"clrex \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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int32_t temp;
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MemoryBarrier();
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[prev], %[ptr] \n\t"
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"cmp %[prev], %[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %[new_value], %[ptr] \n\t"
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"cbnz %w[temp], 0b \n\t"
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"1: \n\t"
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"clrex \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [old_value]"r" (old_value),
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[new_value]"r" (new_value)
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: "memory", "cc"
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); // NOLINT
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return prev;
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}
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inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value;
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MemoryBarrier();
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}
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inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
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MemoryBarrier();
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*ptr = value;
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}
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inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
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return *ptr;
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}
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inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
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Atomic64 value = *ptr;
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MemoryBarrier();
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return value;
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}
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inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
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MemoryBarrier();
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return *ptr;
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}
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} // namespace base::subtle
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} // namespace base
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#endif // BASE_ATOMICOPS_INTERNALS_ARM64_GCC_H_
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