mirror of
https://github.com/classilla/tenfourfox.git
synced 2024-06-04 23:29:33 +00:00
e4c0873499
* fix non-PPC codepath: branch32 to branchPtr * fix register structure access on x86 * save graphic context, tweak calculation * M1499198 * M1499198 * use old SSE Int32x4 load instead of missing Simd which were too difficult to backport, remove error
169 lines
5.0 KiB
C++
169 lines
5.0 KiB
C++
/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
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* vim: set ts=8 sts=4 et sw=4 tw=99:
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef jit_x86_BaseAssembler_x86_h
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#define jit_x86_BaseAssembler_x86_h
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#include "jit/x86-shared/BaseAssembler-x86-shared.h"
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namespace js {
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namespace jit {
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namespace X86Encoding {
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class BaseAssemblerX86 : public BaseAssembler
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{
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public:
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// Arithmetic operations:
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void adcl_ir(int32_t imm, RegisterID dst)
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{
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spew("adcl $%d, %s", imm, GPReg32Name(dst));
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MOZ_ASSERT(CAN_SIGN_EXTEND_8_32(imm));
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m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_ADC);
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m_formatter.immediate8s(imm);
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}
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void adcl_im(int32_t imm, const void* addr)
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{
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spew("adcl %d, %p", imm, addr);
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if (CAN_SIGN_EXTEND_8_32(imm)) {
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m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_ADC);
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m_formatter.immediate8s(imm);
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} else {
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m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_ADC);
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m_formatter.immediate32(imm);
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}
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}
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void adcl_rr(RegisterID src, RegisterID dst)
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{
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spew("adcl %s, %s", GPReg32Name(src), GPReg32Name(dst));
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m_formatter.oneByteOp(OP_ADC_GvEv, src, dst);
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}
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using BaseAssembler::andl_im;
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void andl_im(int32_t imm, const void* addr)
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{
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spew("andl $0x%x, %p", imm, addr);
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if (CAN_SIGN_EXTEND_8_32(imm)) {
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m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_AND);
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m_formatter.immediate8s(imm);
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} else {
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m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_AND);
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m_formatter.immediate32(imm);
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}
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}
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using BaseAssembler::orl_im;
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void orl_im(int32_t imm, const void* addr)
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{
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spew("orl $0x%x, %p", imm, addr);
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if (CAN_SIGN_EXTEND_8_32(imm)) {
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m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_OR);
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m_formatter.immediate8s(imm);
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} else {
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m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_OR);
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m_formatter.immediate32(imm);
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}
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}
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using BaseAssembler::subl_im;
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void subl_im(int32_t imm, const void* addr)
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{
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spew("subl $%d, %p", imm, addr);
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if (CAN_SIGN_EXTEND_8_32(imm)) {
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m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_SUB);
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m_formatter.immediate8s(imm);
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} else {
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m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_SUB);
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m_formatter.immediate32(imm);
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}
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}
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void shldl_irr(int32_t imm, RegisterID src, RegisterID dst)
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{
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MOZ_ASSERT(imm < 32);
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spew("shldl $%d, %s, %s", imm, GPReg32Name(src), GPReg32Name(dst));
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m_formatter.twoByteOp8(OP2_SHLD, dst, src);
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m_formatter.immediate8u(imm);
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}
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void shrdl_irr(int32_t imm, RegisterID src, RegisterID dst)
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{
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MOZ_ASSERT(imm < 32);
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spew("shrdl $%d, %s, %s", imm, GPReg32Name(src), GPReg32Name(dst));
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m_formatter.twoByteOp8(OP2_SHRD, dst, src);
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m_formatter.immediate8u(imm);
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}
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// SSE operations:
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using BaseAssembler::vcvtsi2sd_mr;
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void vcvtsi2sd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
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{
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twoByteOpSimd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, address, src0, dst);
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}
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using BaseAssembler::vmovaps_mr;
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void vmovaps_mr(const void* address, XMMRegisterID dst)
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{
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twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, address, invalid_xmm, dst);
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}
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using BaseAssembler::vmovdqa_mr;
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void vmovdqa_mr(const void* address, XMMRegisterID dst)
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{
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twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, address, invalid_xmm, dst);
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}
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void vhaddpd_rr(XMMRegisterID src, XMMRegisterID dst)
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{
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twoByteOpSimdFlags("vhaddpd", VEX_PD, OP2_HADDPD, src, dst);
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}
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void vsubpd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
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{
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twoByteOpSimd("vsubpd", VEX_PD, OP2_SUBPS_VpsWps, src1, src0, dst);
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}
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void vpunpckldq_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) {
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twoByteOpSimd("vpunpckldq", VEX_PD, OP2_PUNPCKLDQ, src1, src0, dst);
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}
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void vpunpckldq_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
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{
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twoByteOpSimd("vpunpckldq", VEX_PD, OP2_PUNPCKLDQ, offset, base, src0, dst);
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}
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void vpunpckldq_mr(const void* addr, XMMRegisterID src0, XMMRegisterID dst)
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{
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twoByteOpSimd("vpunpckldq", VEX_PD, OP2_PUNPCKLDQ, addr, src0, dst);
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}
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// Misc instructions:
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void pusha()
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{
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spew("pusha");
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m_formatter.oneByteOp(OP_PUSHA);
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}
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void popa()
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{
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spew("popa");
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m_formatter.oneByteOp(OP_POPA);
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}
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};
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typedef BaseAssemblerX86 BaseAssemblerSpecific;
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} // namespace X86Encoding
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} // namespace jit
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} // namespace js
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#endif /* jit_x86_BaseAssembler_x86_h */
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