2017-04-10 11:32:00 +00:00
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/* tc-ft32.c -- Assemble code for ft32
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2022-10-27 18:45:45 +00:00
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Copyright (C) 2008-2022 Free Software Foundation, Inc.
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2017-04-10 11:32:00 +00:00
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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/* Contributed by Anthony Green <green@spindazzle.org>. */
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#include "as.h"
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#include "safe-ctype.h"
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#include "opcode/ft32.h"
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extern const ft32_opc_info_t ft32_opc_info[128];
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2018-12-28 15:25:28 +00:00
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/* See md_parse_option() for meanings of these options. */
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static char norelax; /* True if -norelax switch seen. */
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2017-04-10 11:32:00 +00:00
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const char comment_chars[] = "#";
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const char line_separator_chars[] = ";";
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const char line_comment_chars[] = "#";
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static int pending_reloc;
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2022-10-27 18:45:45 +00:00
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static htab_t opcode_hash_control;
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2017-04-10 11:32:00 +00:00
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static valueT md_chars_to_number (char * buf, int n);
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const pseudo_typeS md_pseudo_table[] =
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{
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{0, 0, 0}
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};
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const char FLT_CHARS[] = "rRsSfFdDxXpP";
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const char EXP_CHARS[] = "eE";
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/* This function is called once, at assembler startup time. It sets
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up the hash table with all the opcodes in it, and also initializes
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some aliases for compatibility with other assemblers. */
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void
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md_begin (void)
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{
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const ft32_opc_info_t *opcode;
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2022-10-27 18:45:45 +00:00
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opcode_hash_control = str_htab_create ();
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2017-04-10 11:32:00 +00:00
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/* Insert names into hash table. */
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for (opcode = ft32_opc_info; opcode->name; opcode++)
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2022-10-27 18:45:45 +00:00
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str_hash_insert (opcode_hash_control, opcode->name, opcode, 0);
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2017-04-10 11:32:00 +00:00
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bfd_set_arch_mach (stdoutput, TARGET_ARCH, 0);
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2018-12-28 15:25:28 +00:00
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if (!norelax)
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linkrelax = 1;
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2017-04-10 11:32:00 +00:00
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}
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/* Parse an expression and then restore the input line pointer. */
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static char *
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parse_exp_save_ilp (char *s, expressionS *op)
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{
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char *save = input_line_pointer;
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input_line_pointer = s;
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expression (op);
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s = input_line_pointer;
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input_line_pointer = save;
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return s;
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}
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static int
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parse_condition (char **ptr)
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{
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char *s = *ptr;
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2018-12-28 15:25:28 +00:00
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static const struct
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{
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2017-04-10 11:32:00 +00:00
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const char *name;
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int bits;
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2018-12-28 15:25:28 +00:00
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}
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ccs[] =
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{
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2017-04-10 11:32:00 +00:00
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{ "gt," , (2 << FT32_FLD_CR_BIT) | (5 << FT32_FLD_CB_BIT) | (1 << FT32_FLD_CV_BIT)},
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{ "gte," , (2 << FT32_FLD_CR_BIT) | (4 << FT32_FLD_CB_BIT) | (1 << FT32_FLD_CV_BIT)},
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{ "lt," , (2 << FT32_FLD_CR_BIT) | (4 << FT32_FLD_CB_BIT) | (0 << FT32_FLD_CV_BIT)},
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{ "lte," , (2 << FT32_FLD_CR_BIT) | (5 << FT32_FLD_CB_BIT) | (0 << FT32_FLD_CV_BIT)},
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{ "a," , (2 << FT32_FLD_CR_BIT) | (6 << FT32_FLD_CB_BIT) | (1 << FT32_FLD_CV_BIT)},
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{ "ae," , (2 << FT32_FLD_CR_BIT) | (1 << FT32_FLD_CB_BIT) | (0 << FT32_FLD_CV_BIT)},
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{ "be," , (2 << FT32_FLD_CR_BIT) | (6 << FT32_FLD_CB_BIT) | (0 << FT32_FLD_CV_BIT)},
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{ "b," , (2 << FT32_FLD_CR_BIT) | (1 << FT32_FLD_CB_BIT) | (1 << FT32_FLD_CV_BIT)},
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{ "nz," , (2 << FT32_FLD_CR_BIT) | (0 << FT32_FLD_CB_BIT) | (0 << FT32_FLD_CV_BIT)},
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{ "z," , (2 << FT32_FLD_CR_BIT) | (0 << FT32_FLD_CB_BIT) | (1 << FT32_FLD_CV_BIT)},
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{ "nc," , (2 << FT32_FLD_CR_BIT) | (1 << FT32_FLD_CB_BIT) | (0 << FT32_FLD_CV_BIT)},
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{ "c," , (2 << FT32_FLD_CR_BIT) | (1 << FT32_FLD_CB_BIT) | (1 << FT32_FLD_CV_BIT)},
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{ "no," , (2 << FT32_FLD_CR_BIT) | (2 << FT32_FLD_CB_BIT) | (0 << FT32_FLD_CV_BIT)},
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{ "o," , (2 << FT32_FLD_CR_BIT) | (2 << FT32_FLD_CB_BIT) | (1 << FT32_FLD_CV_BIT)},
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{ "ns," , (2 << FT32_FLD_CR_BIT) | (3 << FT32_FLD_CB_BIT) | (0 << FT32_FLD_CV_BIT)},
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{ "s," , (2 << FT32_FLD_CR_BIT) | (3 << FT32_FLD_CB_BIT) | (1 << FT32_FLD_CV_BIT)},
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{ NULL, 0}
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}, *pc;
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for (pc = ccs; pc->name; pc++)
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{
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if (memcmp(pc->name, s, strlen(pc->name)) == 0)
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{
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*ptr += strlen(pc->name) - 1;
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return pc->bits;
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}
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}
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return -1;
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}
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static int
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parse_decimal (char **ptr)
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{
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int r = 0;
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char *s = *ptr;
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while (('0' <= *s) && (*s <= '9'))
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{
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r *= 10;
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r += (*s++ - '0');
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}
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*ptr = s;
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return r;
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}
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static int
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parse_register_operand (char **ptr)
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{
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int reg;
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char *s = *ptr;
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if (*s != '$')
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{
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as_bad (_("expecting register"));
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ignore_rest_of_line ();
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return -1;
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}
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if ((s[1] == 's') && (s[2] == 'p'))
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{
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reg = 31;
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}
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else if ((s[1] == 'c') && (s[2] == 'c'))
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{
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reg = 30;
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}
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else if ((s[1] == 'f') && (s[2] == 'p'))
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{
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reg = 29;
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}
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else if (s[1] == 'r')
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{
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reg = s[2] - '0';
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if ((reg < 0) || (reg > 9))
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{
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as_bad (_("illegal register number"));
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ignore_rest_of_line ();
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return -1;
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}
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if ((reg == 1) || (reg == 2) || (reg == 3))
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{
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int r2 = s[3] - '0';
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if ((r2 >= 0) && (r2 <= 9))
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{
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reg = (reg * 10) + r2;
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*ptr += 1;
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}
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}
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}
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else
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{
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as_bad (_("illegal register number"));
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ignore_rest_of_line ();
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return -1;
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}
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*ptr += 3;
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return reg;
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}
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/* This is the guts of the machine-dependent assembler. STR points to
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a machine dependent instruction. This function is supposed to emit
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the frags/bytes it assembles to. */
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void
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md_assemble (char *str)
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{
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char *op_start;
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char *op_end;
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ft32_opc_info_t *opcode;
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char *output;
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int idx = 0;
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char pend;
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int nlen = 0;
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unsigned int b;
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int f;
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expressionS arg;
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2022-10-27 18:45:45 +00:00
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bool fixed = false;
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2018-12-28 15:25:28 +00:00
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unsigned int sc;
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2022-10-27 18:45:45 +00:00
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bool can_sc;
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2017-04-10 11:32:00 +00:00
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/* Drop leading whitespace. */
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while (*str == ' ')
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str++;
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/* Find the op code end. */
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op_start = str;
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for (op_end = str;
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2018-12-28 15:25:28 +00:00
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*op_end
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&& !is_end_of_line[*op_end & 0xff]
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&& *op_end != ' '
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&& *op_end != '.';
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2017-04-10 11:32:00 +00:00
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op_end++)
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nlen++;
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pend = *op_end;
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*op_end = 0;
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if (nlen == 0)
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as_bad (_("can't find opcode "));
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2022-10-27 18:45:45 +00:00
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opcode = (ft32_opc_info_t *) str_hash_find (opcode_hash_control, op_start);
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2017-04-10 11:32:00 +00:00
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*op_end = pend;
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if (opcode == NULL)
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{
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as_bad (_("unknown opcode %s"), op_start);
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return;
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}
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b = opcode->bits;
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f = opcode->fields;
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if (opcode->dw)
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{
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int dw;
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2018-12-28 15:25:28 +00:00
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2017-04-10 11:32:00 +00:00
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if (*op_end == '.')
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{
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switch (op_end[1])
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{
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case 'b':
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dw = 0;
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break;
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case 's':
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dw = 1;
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break;
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case 'l':
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dw = 2;
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break;
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default:
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as_bad (_("unknown width specifier '.%c'"), op_end[1]);
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return;
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}
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op_end += 2;
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}
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else
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{
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dw = 2; /* default is ".l" */
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}
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b |= dw << FT32_FLD_DW_BIT;
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}
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while (ISSPACE (*op_end))
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op_end++;
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output = frag_more (4);
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while (f)
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{
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int lobit = f & -f;
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2018-12-28 15:25:28 +00:00
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2017-04-10 11:32:00 +00:00
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if (f & lobit)
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{
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switch (lobit)
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2018-12-28 15:25:28 +00:00
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{
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case FT32_FLD_CBCRCV:
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b |= parse_condition( &op_end);
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break;
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case FT32_FLD_CB:
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b |= parse_decimal (&op_end) << FT32_FLD_CB_BIT;
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break;
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case FT32_FLD_R_D:
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b |= parse_register_operand (&op_end) << FT32_FLD_R_D_BIT;
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break;
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case FT32_FLD_CR:
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b |= (parse_register_operand (&op_end) - 28) << FT32_FLD_CR_BIT;
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break;
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case FT32_FLD_CV:
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b |= parse_decimal (&op_end) << FT32_FLD_CV_BIT;
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break;
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case FT32_FLD_R_1:
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b |= parse_register_operand (&op_end) << FT32_FLD_R_1_BIT;
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break;
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case FT32_FLD_RIMM:
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if (*op_end == '$')
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{
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b |= parse_register_operand (&op_end) << FT32_FLD_RIMM_BIT;
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|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
b |= 0x400 << FT32_FLD_RIMM_BIT;
|
|
|
|
|
op_end = parse_exp_save_ilp (op_end, &arg);
|
2022-10-27 18:45:45 +00:00
|
|
|
|
fixed = true;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
fix_new_exp (frag_now,
|
|
|
|
|
(output - frag_now->fr_literal),
|
|
|
|
|
2,
|
|
|
|
|
&arg,
|
|
|
|
|
0,
|
|
|
|
|
BFD_RELOC_FT32_10);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case FT32_FLD_R_2:
|
|
|
|
|
b |= parse_register_operand (&op_end) << FT32_FLD_R_2_BIT;
|
|
|
|
|
break;
|
|
|
|
|
case FT32_FLD_K20:
|
|
|
|
|
op_end = parse_exp_save_ilp (op_end, &arg);
|
2022-10-27 18:45:45 +00:00
|
|
|
|
fixed = true;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
fix_new_exp (frag_now,
|
|
|
|
|
(output - frag_now->fr_literal),
|
|
|
|
|
3,
|
|
|
|
|
&arg,
|
|
|
|
|
0,
|
|
|
|
|
BFD_RELOC_FT32_20);
|
|
|
|
|
break;
|
|
|
|
|
case FT32_FLD_PA:
|
|
|
|
|
op_end = parse_exp_save_ilp (op_end, &arg);
|
2022-10-27 18:45:45 +00:00
|
|
|
|
fixed = true;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
fix_new_exp (frag_now,
|
|
|
|
|
(output - frag_now->fr_literal),
|
|
|
|
|
3,
|
|
|
|
|
&arg,
|
|
|
|
|
0,
|
|
|
|
|
BFD_RELOC_FT32_18);
|
|
|
|
|
break;
|
|
|
|
|
case FT32_FLD_AA:
|
|
|
|
|
op_end = parse_exp_save_ilp (op_end, &arg);
|
2022-10-27 18:45:45 +00:00
|
|
|
|
fixed = true;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
fix_new_exp (frag_now,
|
|
|
|
|
(output - frag_now->fr_literal),
|
|
|
|
|
3,
|
|
|
|
|
&arg,
|
|
|
|
|
0,
|
|
|
|
|
BFD_RELOC_FT32_17);
|
|
|
|
|
break;
|
|
|
|
|
case FT32_FLD_K16:
|
|
|
|
|
op_end = parse_exp_save_ilp (op_end, &arg);
|
2022-10-27 18:45:45 +00:00
|
|
|
|
fixed = true;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
fix_new_exp (frag_now,
|
|
|
|
|
(output - frag_now->fr_literal),
|
|
|
|
|
2,
|
|
|
|
|
&arg,
|
|
|
|
|
0,
|
|
|
|
|
BFD_RELOC_16);
|
|
|
|
|
break;
|
|
|
|
|
case FT32_FLD_K15:
|
|
|
|
|
op_end = parse_exp_save_ilp (op_end, &arg);
|
|
|
|
|
if (arg.X_add_number & 0x80)
|
|
|
|
|
arg.X_add_number ^= 0x7f00;
|
2022-10-27 18:45:45 +00:00
|
|
|
|
fixed = true;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
fix_new_exp (frag_now,
|
|
|
|
|
(output - frag_now->fr_literal),
|
|
|
|
|
2,
|
|
|
|
|
&arg,
|
|
|
|
|
0,
|
|
|
|
|
BFD_RELOC_FT32_15);
|
|
|
|
|
break;
|
|
|
|
|
case FT32_FLD_R_D_POST:
|
|
|
|
|
b |= parse_register_operand (&op_end) << FT32_FLD_R_D_BIT;
|
|
|
|
|
break;
|
|
|
|
|
case FT32_FLD_R_1_POST:
|
|
|
|
|
b |= parse_register_operand (&op_end) << FT32_FLD_R_1_BIT;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
as_bad (_("internal error in argument parsing"));
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
f &= ~lobit;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
if (f)
|
|
|
|
|
{
|
|
|
|
|
while (ISSPACE (*op_end))
|
|
|
|
|
op_end++;
|
|
|
|
|
|
|
|
|
|
if (*op_end != ',')
|
|
|
|
|
{
|
|
|
|
|
as_bad (_("expected comma separator"));
|
|
|
|
|
ignore_rest_of_line ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
op_end++;
|
|
|
|
|
while (ISSPACE (*op_end))
|
|
|
|
|
op_end++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2018-12-28 15:25:28 +00:00
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
if (*op_end != 0)
|
|
|
|
|
as_warn (_("extra stuff on line ignored"));
|
|
|
|
|
|
2018-12-28 15:25:28 +00:00
|
|
|
|
can_sc = ft32_shortcode (b, &sc);
|
|
|
|
|
|
|
|
|
|
if (!fixed && can_sc)
|
|
|
|
|
{
|
|
|
|
|
arg.X_op = O_constant;
|
|
|
|
|
arg.X_add_number = 0;
|
|
|
|
|
arg.X_add_symbol = NULL;
|
|
|
|
|
arg.X_op_symbol = NULL;
|
|
|
|
|
fix_new_exp (frag_now,
|
|
|
|
|
(output - frag_now->fr_literal),
|
|
|
|
|
2,
|
|
|
|
|
&arg,
|
|
|
|
|
0,
|
|
|
|
|
BFD_RELOC_FT32_RELAX);
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
output[idx++] = 0xff & (b >> 0);
|
|
|
|
|
output[idx++] = 0xff & (b >> 8);
|
|
|
|
|
output[idx++] = 0xff & (b >> 16);
|
|
|
|
|
output[idx++] = 0xff & (b >> 24);
|
|
|
|
|
|
|
|
|
|
dwarf2_emit_insn (4);
|
|
|
|
|
|
|
|
|
|
while (ISSPACE (*op_end))
|
|
|
|
|
op_end++;
|
|
|
|
|
|
|
|
|
|
if (*op_end != 0)
|
|
|
|
|
as_warn ("extra stuff on line ignored");
|
|
|
|
|
|
|
|
|
|
if (pending_reloc)
|
|
|
|
|
as_bad ("Something forgot to clean up\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Turn a string in input_line_pointer into a floating point constant
|
|
|
|
|
of type type, and store the appropriate bytes in *LITP. The number
|
|
|
|
|
of LITTLENUMS emitted is stored in *SIZEP . An error message is
|
|
|
|
|
returned, or NULL on OK. */
|
|
|
|
|
|
|
|
|
|
const char *
|
|
|
|
|
md_atof (int type, char *litP, int *sizeP)
|
|
|
|
|
{
|
|
|
|
|
int prec;
|
|
|
|
|
LITTLENUM_TYPE words[4];
|
|
|
|
|
char *t;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
switch (type)
|
|
|
|
|
{
|
|
|
|
|
case 'f':
|
|
|
|
|
prec = 2;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 'd':
|
|
|
|
|
prec = 4;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
*sizeP = 0;
|
|
|
|
|
return _("bad call to md_atof");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
t = atof_ieee (input_line_pointer, type, words);
|
|
|
|
|
if (t)
|
|
|
|
|
input_line_pointer = t;
|
|
|
|
|
|
|
|
|
|
*sizeP = prec * 2;
|
|
|
|
|
|
|
|
|
|
for (i = prec - 1; i >= 0; i--)
|
|
|
|
|
{
|
|
|
|
|
md_number_to_chars (litP, (valueT) words[i], 2);
|
|
|
|
|
litP += 2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const char *md_shortopts = "";
|
|
|
|
|
|
|
|
|
|
struct option md_longopts[] =
|
|
|
|
|
{
|
2018-12-28 15:25:28 +00:00
|
|
|
|
#define OPTION_NORELAX (OPTION_MD_BASE)
|
|
|
|
|
{"norelax", no_argument, NULL, OPTION_NORELAX},
|
|
|
|
|
{"no-relax", no_argument, NULL, OPTION_NORELAX},
|
2017-04-10 11:32:00 +00:00
|
|
|
|
{NULL, no_argument, NULL, 0}
|
|
|
|
|
};
|
|
|
|
|
size_t md_longopts_size = sizeof (md_longopts);
|
|
|
|
|
|
|
|
|
|
/* We have no target specific options yet, so these next
|
|
|
|
|
two functions are empty. */
|
|
|
|
|
int
|
|
|
|
|
md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED)
|
|
|
|
|
{
|
2018-12-28 15:25:28 +00:00
|
|
|
|
switch (c)
|
|
|
|
|
{
|
|
|
|
|
case OPTION_NORELAX:
|
|
|
|
|
norelax = 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 1;
|
2017-04-10 11:32:00 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
|
|
|
|
|
{
|
2018-12-28 15:25:28 +00:00
|
|
|
|
fprintf (stream, _("FT32 options:\n"));
|
|
|
|
|
fprintf (stream, _("\n\
|
|
|
|
|
-no-relax don't relax relocations\n\
|
|
|
|
|
\n"));
|
2017-04-10 11:32:00 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Convert from target byte order to host byte order. */
|
|
|
|
|
|
|
|
|
|
static valueT
|
|
|
|
|
md_chars_to_number (char * buf, int n)
|
|
|
|
|
{
|
|
|
|
|
valueT result = 0;
|
|
|
|
|
unsigned char * where = (unsigned char *) buf;
|
|
|
|
|
|
|
|
|
|
while (n--)
|
|
|
|
|
{
|
|
|
|
|
result <<= 8;
|
|
|
|
|
result |= (where[n] & 255);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return result;
|
|
|
|
|
}
|
2018-12-28 15:25:28 +00:00
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
/* Apply a fixup to the object file. */
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
md_apply_fix (fixS *fixP ATTRIBUTE_UNUSED,
|
|
|
|
|
valueT * valP ATTRIBUTE_UNUSED, segT seg ATTRIBUTE_UNUSED)
|
|
|
|
|
{
|
|
|
|
|
char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
|
|
|
|
|
long val = *valP;
|
|
|
|
|
long newval;
|
|
|
|
|
|
2018-12-28 15:25:28 +00:00
|
|
|
|
if (linkrelax && fixP->fx_subsy)
|
|
|
|
|
{
|
|
|
|
|
/* For a subtraction relocation expression, generate one
|
|
|
|
|
of the DIFF relocs, with the value being the difference.
|
|
|
|
|
Note that a sym1 - sym2 expression is adjusted into a
|
|
|
|
|
section_start_sym + sym4_offset_from_section_start - sym1
|
|
|
|
|
expression. fixP->fx_addsy holds the section start symbol,
|
|
|
|
|
fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
|
|
|
|
|
holds sym1. Calculate the current difference and write value,
|
|
|
|
|
but leave fx_offset as is - during relaxation,
|
|
|
|
|
fx_offset - value gives sym1's value. */
|
|
|
|
|
|
|
|
|
|
switch (fixP->fx_r_type)
|
|
|
|
|
{
|
|
|
|
|
case BFD_RELOC_32:
|
|
|
|
|
fixP->fx_r_type = BFD_RELOC_FT32_DIFF32;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2022-10-27 18:45:45 +00:00
|
|
|
|
as_bad_subtract (fixP);
|
2018-12-28 15:25:28 +00:00
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val = S_GET_VALUE (fixP->fx_addsy) +
|
|
|
|
|
fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy);
|
|
|
|
|
*valP = val;
|
|
|
|
|
|
|
|
|
|
fixP->fx_subsy = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* We don't actually support subtracting a symbol. */
|
|
|
|
|
if (fixP->fx_subsy != (symbolS *) NULL)
|
2022-10-27 18:45:45 +00:00
|
|
|
|
as_bad_subtract (fixP);
|
2018-12-28 15:25:28 +00:00
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
switch (fixP->fx_r_type)
|
|
|
|
|
{
|
2018-12-28 15:25:28 +00:00
|
|
|
|
case BFD_RELOC_FT32_DIFF32:
|
2017-04-10 11:32:00 +00:00
|
|
|
|
case BFD_RELOC_32:
|
|
|
|
|
buf[3] = val >> 24;
|
|
|
|
|
buf[2] = val >> 16;
|
|
|
|
|
buf[1] = val >> 8;
|
|
|
|
|
buf[0] = val >> 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_16:
|
|
|
|
|
buf[1] = val >> 8;
|
|
|
|
|
buf[0] = val >> 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_8:
|
|
|
|
|
*buf = val;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_FT32_10:
|
|
|
|
|
if (!val)
|
|
|
|
|
break;
|
|
|
|
|
newval = md_chars_to_number (buf, 2);
|
|
|
|
|
newval |= (val & ((1 << 10) - 1)) << FT32_FLD_RIMM_BIT;
|
|
|
|
|
md_number_to_chars (buf, newval, 2);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_FT32_20:
|
|
|
|
|
if (!val)
|
|
|
|
|
break;
|
|
|
|
|
newval = md_chars_to_number (buf, 3);
|
|
|
|
|
newval |= val & ((1 << 20) - 1);
|
|
|
|
|
md_number_to_chars (buf, newval, 3);
|
|
|
|
|
break;
|
|
|
|
|
|
2018-12-28 15:25:28 +00:00
|
|
|
|
case BFD_RELOC_FT32_15:
|
|
|
|
|
if (!val)
|
|
|
|
|
break;
|
|
|
|
|
newval = md_chars_to_number (buf, 2);
|
|
|
|
|
newval |= val & ((1 << 15) - 1);
|
|
|
|
|
md_number_to_chars (buf, newval, 2);
|
|
|
|
|
break;
|
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
case BFD_RELOC_FT32_17:
|
|
|
|
|
if (!val)
|
|
|
|
|
break;
|
|
|
|
|
newval = md_chars_to_number (buf, 3);
|
|
|
|
|
newval |= val & ((1 << 17) - 1);
|
|
|
|
|
md_number_to_chars (buf, newval, 3);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BFD_RELOC_FT32_18:
|
|
|
|
|
if (!val)
|
|
|
|
|
break;
|
|
|
|
|
newval = md_chars_to_number (buf, 4);
|
|
|
|
|
newval |= (val >> 2) & ((1 << 18) - 1);
|
|
|
|
|
md_number_to_chars (buf, newval, 4);
|
|
|
|
|
break;
|
|
|
|
|
|
2018-12-28 15:25:28 +00:00
|
|
|
|
case BFD_RELOC_FT32_RELAX:
|
|
|
|
|
break;
|
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
default:
|
|
|
|
|
abort ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
|
|
|
|
|
fixP->fx_done = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
md_number_to_chars (char *ptr, valueT use, int nbytes)
|
|
|
|
|
{
|
|
|
|
|
number_to_chars_littleendian (ptr, use, nbytes);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate a machine-dependent relocation. */
|
2018-12-28 15:25:28 +00:00
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
arelent *
|
|
|
|
|
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
|
|
|
|
|
{
|
|
|
|
|
arelent *relP;
|
|
|
|
|
bfd_reloc_code_real_type code;
|
|
|
|
|
|
|
|
|
|
switch (fixP->fx_r_type)
|
|
|
|
|
{
|
|
|
|
|
case BFD_RELOC_32:
|
|
|
|
|
case BFD_RELOC_16:
|
|
|
|
|
case BFD_RELOC_8:
|
|
|
|
|
case BFD_RELOC_FT32_10:
|
|
|
|
|
case BFD_RELOC_FT32_20:
|
2018-12-28 15:25:28 +00:00
|
|
|
|
case BFD_RELOC_FT32_15:
|
2017-04-10 11:32:00 +00:00
|
|
|
|
case BFD_RELOC_FT32_17:
|
|
|
|
|
case BFD_RELOC_FT32_18:
|
2018-12-28 15:25:28 +00:00
|
|
|
|
case BFD_RELOC_FT32_RELAX:
|
|
|
|
|
case BFD_RELOC_FT32_DIFF32:
|
2017-04-10 11:32:00 +00:00
|
|
|
|
code = fixP->fx_r_type;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
2018-12-28 15:25:28 +00:00
|
|
|
|
_("Semantics error. This type of operand can not be "
|
|
|
|
|
"relocated, it must be an assembly-time constant"));
|
|
|
|
|
return NULL;
|
2017-04-10 11:32:00 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
relP = XNEW (arelent);
|
|
|
|
|
gas_assert (relP != 0);
|
|
|
|
|
relP->sym_ptr_ptr = XNEW (asymbol *);
|
|
|
|
|
*relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
|
|
|
|
|
relP->address = fixP->fx_frag->fr_address + fixP->fx_where;
|
|
|
|
|
|
|
|
|
|
relP->addend = fixP->fx_offset;
|
|
|
|
|
|
|
|
|
|
relP->howto = bfd_reloc_type_lookup (stdoutput, code);
|
|
|
|
|
if (! relP->howto)
|
|
|
|
|
{
|
|
|
|
|
const char *name;
|
|
|
|
|
|
|
|
|
|
name = S_GET_NAME (fixP->fx_addsy);
|
|
|
|
|
if (name == NULL)
|
|
|
|
|
name = _("<unknown>");
|
|
|
|
|
as_fatal (_("Cannot generate relocation type for symbol %s, code %s"),
|
|
|
|
|
name, bfd_get_reloc_code_name (code));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return relP;
|
|
|
|
|
}
|
2018-12-28 15:25:28 +00:00
|
|
|
|
|
|
|
|
|
/* TC_FORCE_RELOCATION hook */
|
|
|
|
|
|
2022-10-27 18:45:45 +00:00
|
|
|
|
static bool
|
2018-12-28 15:25:28 +00:00
|
|
|
|
relaxable_section (asection *sec)
|
|
|
|
|
{
|
|
|
|
|
return ((sec->flags & SEC_DEBUGGING) == 0
|
|
|
|
|
&& (sec->flags & SEC_CODE) != 0
|
|
|
|
|
&& (sec->flags & SEC_ALLOC) != 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Does whatever the xtensa port does. */
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
ft32_validate_fix_sub (fixS *fix)
|
|
|
|
|
{
|
|
|
|
|
segT add_symbol_segment, sub_symbol_segment;
|
|
|
|
|
|
|
|
|
|
/* The difference of two symbols should be resolved by the assembler when
|
|
|
|
|
linkrelax is not set. If the linker may relax the section containing
|
|
|
|
|
the symbols, then an Xtensa DIFF relocation must be generated so that
|
|
|
|
|
the linker knows to adjust the difference value. */
|
|
|
|
|
if (!linkrelax || fix->fx_addsy == NULL)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
/* Make sure both symbols are in the same segment, and that segment is
|
|
|
|
|
"normal" and relaxable. If the segment is not "normal", then the
|
|
|
|
|
fix is not valid. If the segment is not "relaxable", then the fix
|
|
|
|
|
should have been handled earlier. */
|
|
|
|
|
add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
|
|
|
|
|
if (! SEG_NORMAL (add_symbol_segment) ||
|
|
|
|
|
! relaxable_section (add_symbol_segment))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
|
|
|
|
|
return (sub_symbol_segment == add_symbol_segment);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* TC_FORCE_RELOCATION hook */
|
|
|
|
|
|
|
|
|
|
/* If linkrelax is turned on, and the symbol to relocate
|
|
|
|
|
against is in a relaxable segment, don't compute the value -
|
|
|
|
|
generate a relocation instead. */
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
ft32_force_relocation (fixS *fix)
|
|
|
|
|
{
|
|
|
|
|
if (linkrelax && fix->fx_addsy
|
|
|
|
|
&& relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
|
|
|
|
|
{
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return generic_force_reloc (fix);
|
|
|
|
|
}
|
|
|
|
|
|
2022-10-27 18:45:45 +00:00
|
|
|
|
bool
|
2018-12-28 15:25:28 +00:00
|
|
|
|
ft32_allow_local_subtract (expressionS * left,
|
|
|
|
|
expressionS * right,
|
|
|
|
|
segT section)
|
|
|
|
|
{
|
|
|
|
|
/* If we are not in relaxation mode, subtraction is OK. */
|
|
|
|
|
if (!linkrelax)
|
2022-10-27 18:45:45 +00:00
|
|
|
|
return true;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
|
|
|
|
|
/* If the symbols are not in a code section then they are OK. */
|
|
|
|
|
if ((section->flags & SEC_CODE) == 0)
|
2022-10-27 18:45:45 +00:00
|
|
|
|
return true;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
|
|
|
|
|
if (left->X_add_symbol == right->X_add_symbol)
|
2022-10-27 18:45:45 +00:00
|
|
|
|
return true;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
|
|
|
|
|
/* We have to assume that there may be instructions between the
|
|
|
|
|
two symbols and that relaxation may increase the distance between
|
|
|
|
|
them. */
|
2022-10-27 18:45:45 +00:00
|
|
|
|
return false;
|
2018-12-28 15:25:28 +00:00
|
|
|
|
}
|