{AARCH64_OPND_CLASS_IMMEDIATE,"NZCV",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_nzcv},"a flag bit specifier giving an alternative value for each flag"},
{AARCH64_OPND_CLASS_IMMEDIATE,"AIMM",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_shift,FLD_imm12},"a 12-bit unsigned immediate with optional left shift of 12 bits"},
{AARCH64_OPND_CLASS_IMMEDIATE,"HALF",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_imm16},"a 16-bit immediate with optional left shift"},
{AARCH64_OPND_CLASS_IMMEDIATE,"FBITS",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_scale},"the number of bits after the binary point in the fixed-point value"},
{AARCH64_OPND_CLASS_ADDRESS,"ADDR_SIMPLE",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{},"an address with base register (no offset)"},
{AARCH64_OPND_CLASS_ADDRESS,"ADDR_REGOFF",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{},"an address with register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"ADDR_SIMM7",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_imm7,FLD_index2},"an address with 7-bit signed immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS,"ADDR_SIMM9",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_imm9,FLD_index},"an address with 9-bit signed immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS,"ADDR_SIMM9_2",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_imm9,FLD_index},"an address with 9-bit negative or unaligned immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS,"ADDR_SIMM10",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index},"an address with an optional 10-bit scaled, signed immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS,"ADDR_SIMM11",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_imm7,FLD_index2},"an address with 11-bit signed immediate (multiple of 16) offset"},
{AARCH64_OPND_CLASS_ADDRESS,"ADDR_SIMM13",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_imm9,FLD_index},"an address with 13-bit signed immediate (multiple of 16) offset"},
{AARCH64_OPND_CLASS_ADDRESS,"ADDR_OFFSET",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_imm9,FLD_index},"an address with an optional 8-bit signed immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_S4x16",4<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 4-bit signed offset, multiplied by 16"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_S4x32",5<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 4-bit signed offset, multiplied by 32"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_S4xVL",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 4-bit signed offset, multiplied by VL"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_S4x2xVL",1<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 4-bit signed offset, multiplied by 2*VL"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_S4x3xVL",2<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 4-bit signed offset, multiplied by 3*VL"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_S4x4xVL",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 4-bit signed offset, multiplied by 4*VL"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_S6xVL",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 6-bit signed offset, multiplied by VL"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_S9xVL",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 9-bit signed offset, multiplied by VL"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_U6",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 6-bit unsigned offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_U6x2",1<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 6-bit unsigned offset, multiplied by 2"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_U6x4",2<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 6-bit unsigned offset, multiplied by 4"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RI_U6x8",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn},"an address with a 6-bit unsigned offset, multiplied by 8"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RR",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_Rm},"an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RR_LSL1",1<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_Rm},"an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RR_LSL2",2<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_Rm},"an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RR_LSL3",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_Rm},"an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RR_LSL4",4<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_Rm},"an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RX",(0<<OPD_F_OD_LSB)|OPD_F_NO_ZR|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_Rm},"an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RX_LSL1",(1<<OPD_F_OD_LSB)|OPD_F_NO_ZR|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_Rm},"an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RX_LSL2",(2<<OPD_F_OD_LSB)|OPD_F_NO_ZR|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_Rm},"an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RX_LSL3",(3<<OPD_F_OD_LSB)|OPD_F_NO_ZR|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_Rm},"an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_ZX",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zn,FLD_Rm},"vector of address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_LSL1",1<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_LSL2",2<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_LSL3",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_XTW_14",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_XTW_22",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_XTW1_14",1<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_XTW1_22",1<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_XTW2_14",2<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_XTW2_22",2<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_XTW3_14",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_RZ_XTW3_22",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_ZI_U5",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zn},"an address with a 5-bit unsigned offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_ZI_U5x2",1<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zn},"an address with a 5-bit unsigned offset, multiplied by 2"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_ZI_U5x4",2<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zn},"an address with a 5-bit unsigned offset, multiplied by 4"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_ZI_U5x8",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zn},"an address with a 5-bit unsigned offset, multiplied by 8"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_ZZ_LSL",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zn,FLD_SVE_Zm_16},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_ZZ_SXTW",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zn,FLD_SVE_Zm_16},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS,"SVE_ADDR_ZZ_UXTW",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zn,FLD_SVE_Zm_16},"an address with a vector register offset"},
{AARCH64_OPND_CLASS_SVE_REG,"SVE_Za_5",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Za_5},"an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG,"SVE_Za_16",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Za_16},"an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG,"SVE_Zd",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zd},"an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG,"SVE_Zm_5",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zm_5},"an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG,"SVE_Zm_16",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zm_16},"an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG,"SVE_Zm3_INDEX",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_Zm_16},"an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG,"SVE_Zm3_22_INDEX",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_i3h,FLD_SVE_Zm_16},"an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG,"SVE_Zm3_11_INDEX",3<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_i3h2,FLD_SVE_i3l,FLD_SVE_imm3},"an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG,"SVE_Zm4_11_INDEX",4<<OPD_F_OD_LSB|OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SVE_i2h,FLD_SVE_i3l,FLD_SVE_imm4},"an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG,"SME_ZAda_2b",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SME_ZAda_2b},"an SME ZA tile ZA0-ZA3"},
{AARCH64_OPND_CLASS_SVE_REG,"SME_ZAda_3b",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SME_ZAda_3b},"an SME ZA tile ZA0-ZA7"},
{AARCH64_OPND_CLASS_SVE_REG,"SME_ZA_HV_idx_src",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5},"an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_SVE_REG,"SME_ZA_HV_idx_dest",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2},"an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_PRED_REG,"SME_Pm",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SME_Pm},"an SVE predicate register"},
{AARCH64_OPND_CLASS_SVE_REG,"SME_list_of_64bit_tiles",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SME_zero_mask},"list of 64-bit ZA element tiles"},
{AARCH64_OPND_CLASS_SVE_REG,"SME_ZA_HV_idx_ldstr",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2},"an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_SVE_REG,"SME_PnT_Wm_imm",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl},"Source scalable predicate register with index "},
{AARCH64_OPND_CLASS_IMMEDIATE,"TME_UIMM16",OPD_F_HAS_INSERTER|OPD_F_HAS_EXTRACTOR,{FLD_imm16},"a 16-bit unsigned immediate for TME tcancel"},