mirror of
https://github.com/autc04/Retro68.git
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343 lines
12 KiB
Plaintext
343 lines
12 KiB
Plaintext
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; Copyright 2011 Free Software Foundation, Inc.
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;
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; Contributed by Red Hat Inc;
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;
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; This file is part of the GNU Binutils.
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, write to the Free Software
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; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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; MA 02110-1301, USA.
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;; This coprocessor definition is being used to verify vliw mode behaviour.
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;; This is a mock-up done by Red Hat and is in no way supposed to represent
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;; a real coprocessor. The hardware is defined in mep-core.cpu.
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; Coprocessor registers
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(define-pmacro rh-isa-1 () (ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))
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(define-hardware
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(name h-cr64-rh-1)
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(comment "64-bit coprocessor registers for rh coprocessor for core 1")
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(attrs VIRTUAL rh-isa-1)
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(type register DI (32))
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(set (index newval) (c-call VOID "h_cr64_set" index newval))
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(get (index) (c-call DI "h_cr64_get" index))
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(indices keyword "$c" (.map -reg-pair (.iota 32)))
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)
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(define-hardware
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(name h-cr-rh-1)
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(comment "32-bit coprocessor registers for rh coprocessor for core 1")
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(attrs VIRTUAL rh-isa-1)
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(type register SI (32))
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(set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
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(get (index) (trunc SI (c-call DI "h_cr64_get" index)))
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(indices keyword "$c" (.map -reg-pair (.iota 32)))
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)
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(define-hardware
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(name h-ccr-rh-1)
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(comment "Coprocessor control registers for rh coprocessor for core 1")
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(attrs VIRTUAL rh-isa-1)
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(type register SI (64))
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(set (index newval) (c-call VOID "h_ccr_set" index newval))
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(get (index) (c-call DI "h_ccr_get" index))
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(indices keyword "" (.map -ccr-reg-pair (.iota 64)))
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)
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; ifields For 16-bit insns
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(dnf f-cphigh4 "High 4 bits" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 0 4)
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(dnf f-cpcrn "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 4 5)
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(dnf f-cpcrm "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 11 5)
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(dnf f-uu2 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 2)
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(dnf f-uu3 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 3)
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(dnf f-cprm "Core GPR" ((ISA ext_cop1_16)) 12 4)
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; ifields For 32-bit insns (some of the above are used too)
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; Notes:
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;
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; f-alone: A value of 0111 means that the insn can run alone in
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; one of the vliw modes.
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;
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; f-seg32: Together f-seg32 and f-seg32-a allow 64 different 32-bit
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; f-seg32-a: insns to be defined.
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(dnf f-seg32 "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 9 3)
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(dnf f-alone "Run-alone indicator" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_64)) 12 4)
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(dnf f-seg32-a "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 21 3)
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(dnf f-code8 "8 bit unsigned immediate" ((ISA ext_cop1_32)) 24 8)
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(dnf f-cpcrm-32 "Corpocessor Reg" ((ISA ext_cop1_32)) 16 5)
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; ifields for 48-bit insns
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; Note: Part of f-uu12 can be broken off later to enumerate
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; any 48-bit insns that may be added.
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(dnf f-uu12 "Unusued 12 bits" ((ISA ext_cop1_48)) 4 12)
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(dnf f-code16a "Unsigned immediate" ((ISA ext_cop1_48)) 16 16)
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(dnf f-code16b "Unsigned immediate" ((ISA ext_cop1_48,ext_cop1_64)) 32 16)
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; ifields for 64-bit insns
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(dnf f-uu8 "Unsused 8 bits" ((ISA ext_cop1_64)) 4 8)
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(dnf f-uu8a "Unused 13 bits" ((ISA ext_cop1_64)) 16 8)
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(dnf f-seg64 "Enumerate 64-bit insns" ((ISA ext_cop1_64)) 24 8)
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(dnf f-code16c "Unsigned immediate" ((ISA ext_cop1_64)) 48 16)
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(dnf f-cpcrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 5)
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(dnf f-cpcrm-64 "Coprocessor Register" ((ISA ext_cop1_64)) 37 4)
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(dnf f-code23 "23 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 41 23)
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(dnf f-cpccrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 4)
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(dnf f-cpccrm-64 "Core GPR" ((ISA ext_cop1_64)) 36 4)
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(dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 40 24)
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; Operands for 16-bit insns
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(dnop cpcrn "cpcrn" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn)
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(dnop cpcrm "cpcrm" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm)
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(dnop cprm "cprm" ((ISA ext_cop1_16)) h-gpr f-cprm)
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; Additional operands for 32-bit insns
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(dnop code8 "imm8" ((ISA ext_cop1_32)) h-uint f-code8)
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; Operands for 48-bit insns
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(dnop code16a "code16a" ((ISA ext_cop1_48)) h-uint f-code16a)
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(dnop code16b "code16b" ((ISA ext_cop1_48,ext_cop1_64)) h-uint f-code16b)
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; Additional operands for 64-bit insns
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(dnop code16c "code16c" ((ISA ext_cop1_64)) h-uint f-code16c)
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(dnop cpcrn64 "cpcrn64" ((ISA ext_cop1_64)) h-cr64-rh-1 f-cpcrn-64)
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(dnop cpcrm64 "crm64" ((ISA ext_cop1_64)) h-gpr f-cpcrm-64)
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(dnop cpccrn64 "cpccrn64" ((ISA ext_cop1_64)) h-ccr-rh-1 f-cpccrn-64)
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(dnop cpccrm64 "cpccrm64" ((ISA ext_cop1_64)) h-gpr f-cpccrm-64)
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(dnop cpcode23 "cpcode23" ((ISA ext_cop1_64)) h-uint f-code23)
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(dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24)
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; 16- and 32-bit nops can be defined as normal instructions without
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; any problems. nops take no operands, so nops longer than 32
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; bits cannot be defined as normal insns since that would result in
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; decodable bits beyond cgen's 32-bit boundary. As a result, we
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; have to use macros and other real insns to create 48- and 64-bit nops.
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;
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; In addition, since the names of the nops that will be created as part
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; of future insn sets are not known at this time, the assembler needs a
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; fixed set of nop names that it can use for automatic nop insertion.
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; The idea is that no matter what those insns are called, we don't want
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; to have to change the C code in the assemblers vliw grouping validation
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; and nop insertion routines. We therefore have to create macros for
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; all nops to map the macro names which are known to the assembler to the
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; names of the real nop insns.
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;
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; These emitted insns in these macros will need to be modified when
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; new nops are defined in new coprocessor insn sets.
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; A real 16-bit nop insn exists
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(dnmi cpnop16 "cpnop16"
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((ISA ext_cop1_16))
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"cpnop16"
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(emit cp16nop)
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)
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; A real 32-bit nop insn exists
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(dnmi cpnop32 "cpnop32"
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((ISA ext_cop1_32))
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"cpnop32"
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(emit cp32nop)
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)
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; There is no 48-bit nop insn so we use a real "dummy" insn to enable the nop.
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(dnmi cpnop48 "cpnop48"
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((ISA ext_cop1_48))
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"cpnop48"
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(emit cpf1nop (code16a 0) (code16b 0))
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)
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; There is no 64-bit nop insn so we use a real "dummy" insn to enable the nop.
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(dnmi cpnop64 "cpnop64"
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((ISA ext_cop1_64))
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"cpnop64"
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(emit cpf3nop (code16b 0) (code16c 0))
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)
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(define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16))
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(define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32))
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(define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48))
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(define-pmacro (dncp164i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_64))
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; 16-Bit Insns
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(dncp116i movcp16 "16-bit coprocessor move insn"
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(VLIW64_NO_MATCHING_NOP)
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"movcp16 $cpcrn,$cpcrm"
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(+ (f-cphigh4 1) cpcrn (f-uu2 0) cpcrm)
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(set cpcrn cpcrm)
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()
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)
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(dncp116i movcp16a "16-bit coprocessor move insn"
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(VLIW64_NO_MATCHING_NOP)
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"movcp16a $cpcrn,$cprm"
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(+ (f-cphigh4 2) cpcrn (f-uu3 0) cprm)
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(set cpcrn (zext DI cprm))
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()
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)
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(dncp116i movcp16b "16-bit coprocessor move insn"
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(VLIW64_NO_MATCHING_NOP)
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"movcp16b $cprm,$cpcrn"
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(+ (f-cphigh4 3) cpcrn (f-uu3 0) cprm)
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(set cprm (subword SI cpcrn 1))
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()
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)
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(dncp116i cp16nop "16-bit coprocessor nop"
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(VLIW64_NO_MATCHING_NOP)
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"cp16nop"
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(+ (f-cphigh4 0) (f-cpcrn 0) (f-uu2 0) (f-cpcrm 0))
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(unimp "cp16nop")
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()
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)
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; 32-Bit Insns
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(dncp132i cp32nop "32-bit coprocessor nop"
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(VLIW64_NO_MATCHING_NOP)
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"cp32nop"
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(+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7)
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(f-cpcrm-32 0) (f-seg32-a 0) (f-code8 0))
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(unimp "cpnop32")
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()
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)
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(dncp132i cpf2 "General 32-bit insn for compatibility with toshiba's tests "
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(VLIW64_NO_MATCHING_NOP)
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"cpf2 $code8"
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(+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7)
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(f-cpcrm-32 0) (f-seg32-a 1) code8)
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(unimp "cpf2")
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()
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)
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; 48-Bit Insns
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(dncp148i cpf1 "48-bit coprocessor helper insn"
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()
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"cpf1 $code16a,$code16b"
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(+ (f-cphigh4 4) (f-uu12 0) code16a code16b)
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(sequence ((HI result))
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(if (eq code16a 0)
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(set pc (c-call USI "cop_exception" pc))
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; Set branch condition flags to value of code16a[0:3]
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; Branch condition flags do not exist yet.
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(nop)
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)
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)
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()
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)
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(dncp148i cpf1nop "48-bit coprocessor nop insn"
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()
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"cpf1nop $code16a,$code16b"
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(+ (f-cphigh4 5) (f-uu12 0) code16a code16b)
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(sequence ((HI result))
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(set result (add code16a code16b))
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)
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()
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)
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; 64-Bit Insns
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(dncp164i cpf3 "64-bit coprocessor helper insn"
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()
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"cpf3 $code16b,$code16c"
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(+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0)
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(f-seg64 0) code16b code16c)
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(sequence ((HI result))
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(set result (add code16b code16c))
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)
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()
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)
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(dncp164i cpf3nop "64-bit coprocessor helper insn"
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()
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"cpf3nop $code16b,$code16c"
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(+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0)
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(f-seg64 7) code16b code16c)
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(sequence ((HI result))
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(set result (add code16b code16c))
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)
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()
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)
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(dncp164i cmov64a "64-bit cmov"
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()
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"cmov64a $cpcrn64,$cpcrm64,$cpcode23"
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(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
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(f-seg64 1) cpcrn64 cpcrm64 cpcode23)
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(sequence ((SI dummy))
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(set dummy cpcode23)
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(set cpcrn64 (zext DI cpcrm64)))
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()
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)
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(dncp164i cmov64b "64-bit cmov"
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()
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"cmov64b $cpcrm64,$cpcrn64,$cpcode23"
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|||
|
|
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
|
|||
|
|
(f-seg64 2) cpcrn64 cpcrm64 cpcode23)
|
|||
|
|
(sequence ((SI dummy))
|
|||
|
|
(set dummy cpcode23)
|
|||
|
|
(set cpcrm64 (subword SI cpcrn64 1)))
|
|||
|
|
()
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
(dncp164i cmovh64a "64-bit cmovh"
|
|||
|
|
()
|
|||
|
|
"cmovh64a $cpcrn64,$cpcrm64,$cpcode23"
|
|||
|
|
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
|
|||
|
|
(f-seg64 3) cpcrn64 cpcrm64 cpcode23)
|
|||
|
|
(sequence ((SI dummy))
|
|||
|
|
(set dummy cpcode23)
|
|||
|
|
(set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1)))))
|
|||
|
|
()
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
(dncp164i cmovh64b "64-bit cmovh"
|
|||
|
|
()
|
|||
|
|
"cmovh64b $cpcrm64,$cpcrn64,$cpcode23"
|
|||
|
|
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
|
|||
|
|
(f-seg64 4) cpcrn64 cpcrm64 cpcode23)
|
|||
|
|
(sequence ((SI dummy))
|
|||
|
|
(set dummy cpcode23)
|
|||
|
|
(set cpcrm64 (subword SI cpcrn64 0)))
|
|||
|
|
()
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
(dncp164i cmovc64a "64-bit cmovc"
|
|||
|
|
()
|
|||
|
|
"cmovc64a $cpccrn64,$cpccrm64,$cpcode24"
|
|||
|
|
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
|
|||
|
|
(f-seg64 5) cpccrn64 cpccrm64 cpcode24)
|
|||
|
|
(sequence ((SI dummy))
|
|||
|
|
(set dummy cpcode24)
|
|||
|
|
(set cpccrn64 cpccrm64))
|
|||
|
|
()
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
(dncp164i cmovc64b "64-bit cmovc"
|
|||
|
|
()
|
|||
|
|
"cmovc64b $cpccrm64,$cpccrn64,$cpcode24"
|
|||
|
|
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
|
|||
|
|
(f-seg64 6) cpccrn64 cpccrm64 cpcode24)
|
|||
|
|
(sequence ((SI dummy))
|
|||
|
|
(set dummy cpcode24)
|
|||
|
|
(set cpccrm64 cpccrn64))
|
|||
|
|
()
|
|||
|
|
)
|
|||
|
|
|