2012-03-26 19:18:29 +00:00
/* microblaze-opc.h -- MicroBlaze Opcodes
2017-04-10 11:32:00 +00:00
Copyright ( C ) 2009 - 2017 Free Software Foundation , Inc .
2012-03-26 19:18:29 +00:00
This file is part of the GNU opcodes library .
This library is free software ; you can redistribute it and / or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation ; either version 3 , or ( at your option )
any later version .
It is distributed in the hope that it will be useful , but WITHOUT
ANY WARRANTY ; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE . See the GNU General Public
License for more details .
You should have received a copy of the GNU General Public License
along with this file ; see the file COPYING . If not , write to the
Free Software Foundation , 51 Franklin Street - Fifth Floor , Boston ,
MA 02110 - 1301 , USA . */
# ifndef MICROBLAZE_OPC
# define MICROBLAZE_OPC
# include "microblaze-opcm.h"
# define INST_TYPE_RD_R1_R2 0
# define INST_TYPE_RD_R1_IMM 1
# define INST_TYPE_RD_R1_UNSIGNED_IMM 2
# define INST_TYPE_RD_R1 3
# define INST_TYPE_RD_R2 4
# define INST_TYPE_RD_IMM 5
# define INST_TYPE_R2 6
# define INST_TYPE_R1_R2 7
# define INST_TYPE_R1_IMM 8
# define INST_TYPE_IMM 9
# define INST_TYPE_SPECIAL_R1 10
# define INST_TYPE_RD_SPECIAL 11
# define INST_TYPE_R1 12
/* New instn type for barrel shift imms. */
# define INST_TYPE_RD_R1_IMM5 13
# define INST_TYPE_RD_RFSL 14
# define INST_TYPE_R1_RFSL 15
/* New insn type for insn cache. */
2014-09-12 22:14:23 +00:00
# define INST_TYPE_R1_R2_SPECIAL 16
2012-03-26 19:18:29 +00:00
/* New insn type for msrclr, msrset insns. */
# define INST_TYPE_RD_IMM15 17
/* New insn type for tuqula rd - addik rd, r0, 42. */
# define INST_TYPE_RD 18
/* New insn type for t*put. */
# define INST_TYPE_RFSL 19
2014-09-12 22:14:23 +00:00
/* For mbar. */
# define INST_TYPE_IMM5 20
2012-03-26 19:18:29 +00:00
# define INST_TYPE_NONE 25
2017-04-10 11:32:00 +00:00
/* Instructions where the label address is resolved as a PC offset
2012-03-26 19:18:29 +00:00
( for branch label ) . */
2017-04-10 11:32:00 +00:00
# define INST_PC_OFFSET 1
/* Instructions where the label address is resolved as an absolute
2012-03-26 19:18:29 +00:00
value ( for data mem or abs address ) . */
2017-04-10 11:32:00 +00:00
# define INST_NO_OFFSET 0
2012-03-26 19:18:29 +00:00
# define IMMVAL_MASK_NON_SPECIAL 0x0000
# define IMMVAL_MASK_MTS 0x4000
# define IMMVAL_MASK_MFS 0x0000
# define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */
# define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */
# define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */
# define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */
# define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */
2014-09-12 22:14:23 +00:00
# define OPCODE_MASK_H13S 0xFFE0E7F0 / * High 11 16:18 21:27 bits, 19:20 bits
and last nibble of last byte for spr . */
2017-04-10 11:32:00 +00:00
# define OPCODE_MASK_H23S 0xFC1FC000 / * High 6, 20-16 and 15:1 bits and last
2012-03-26 19:18:29 +00:00
nibble of last byte for spr . */
# define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */
# define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits. */
# define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */
# define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
# define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
2017-04-10 11:32:00 +00:00
# define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
2012-03-26 19:18:29 +00:00
# define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
# define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
# define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
/* New Mask for msrset, msrclr insns. */
# define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
2014-09-12 22:14:23 +00:00
/* Mask for mbar insn. */
# define OPCODE_MASK_HN 0xFF020004 /* High 16 bits and bits 14, 29. */
2012-03-26 19:18:29 +00:00
# define DELAY_SLOT 1
# define NO_DELAY_SLOT 0
2014-09-12 22:14:23 +00:00
# define MAX_OPCODES 289
2012-03-26 19:18:29 +00:00
struct op_code_struct
{
2017-04-10 11:32:00 +00:00
const char * name ;
2012-03-26 19:18:29 +00:00
short inst_type ; /* Registers and immediate values involved. */
short inst_offset_type ; /* Immediate vals offset from PC? (= 1 for branches). */
short delay_slots ; /* Info about delay slots needed after this instr. */
short immval_mask ;
2017-04-10 11:32:00 +00:00
unsigned long bit_sequence ; /* All the fixed bits for the op are set and
all the variable bits ( reg names , imm vals )
are set to 0. */
2012-03-26 19:18:29 +00:00
unsigned long opcode_mask ; /* Which bits define the opcode. */
enum microblaze_instr instr ;
enum microblaze_instr_type instr_type ;
/* More info about output format here. */
2017-04-10 11:32:00 +00:00
} opcodes [ MAX_OPCODES ] =
{
2012-03-26 19:18:29 +00:00
{ " add " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x00000000 , OPCODE_MASK_H4 , add , arithmetic_inst } ,
{ " rsub " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x04000000 , OPCODE_MASK_H4 , rsub , arithmetic_inst } ,
{ " addc " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x08000000 , OPCODE_MASK_H4 , addc , arithmetic_inst } ,
{ " rsubc " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x0C000000 , OPCODE_MASK_H4 , rsubc , arithmetic_inst } ,
{ " addk " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x10000000 , OPCODE_MASK_H4 , addk , arithmetic_inst } ,
{ " rsubk " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x14000000 , OPCODE_MASK_H4 , rsubk , arithmetic_inst } ,
{ " cmp " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x14000001 , OPCODE_MASK_H4 , cmp , arithmetic_inst } ,
{ " cmpu " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x14000003 , OPCODE_MASK_H4 , cmpu , arithmetic_inst } ,
{ " addkc " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x18000000 , OPCODE_MASK_H4 , addkc , arithmetic_inst } ,
{ " rsubkc " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x1C000000 , OPCODE_MASK_H4 , rsubkc , arithmetic_inst } ,
{ " addi " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x20000000 , OPCODE_MASK_H , addi , arithmetic_inst } ,
{ " rsubi " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x24000000 , OPCODE_MASK_H , rsubi , arithmetic_inst } ,
{ " addic " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x28000000 , OPCODE_MASK_H , addic , arithmetic_inst } ,
{ " rsubic " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x2C000000 , OPCODE_MASK_H , rsubic , arithmetic_inst } ,
{ " addik " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x30000000 , OPCODE_MASK_H , addik , arithmetic_inst } ,
{ " rsubik " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x34000000 , OPCODE_MASK_H , rsubik , arithmetic_inst } ,
{ " addikc " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x38000000 , OPCODE_MASK_H , addikc , arithmetic_inst } ,
{ " rsubikc " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x3C000000 , OPCODE_MASK_H , rsubikc , arithmetic_inst } ,
{ " mul " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x40000000 , OPCODE_MASK_H4 , mul , mult_inst } ,
{ " mulh " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x40000001 , OPCODE_MASK_H4 , mulh , mult_inst } ,
{ " mulhu " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x40000003 , OPCODE_MASK_H4 , mulhu , mult_inst } ,
{ " mulhsu " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x40000002 , OPCODE_MASK_H4 , mulhsu , mult_inst } ,
{ " idiv " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x48000000 , OPCODE_MASK_H4 , idiv , div_inst } ,
{ " idivu " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x48000002 , OPCODE_MASK_H4 , idivu , div_inst } ,
{ " bsll " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x44000400 , OPCODE_MASK_H3 , bsll , barrel_shift_inst } ,
{ " bsra " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x44000200 , OPCODE_MASK_H3 , bsra , barrel_shift_inst } ,
{ " bsrl " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x44000000 , OPCODE_MASK_H3 , bsrl , barrel_shift_inst } ,
{ " get " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C000000 , OPCODE_MASK_H32 , get , anyware_inst } ,
{ " put " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C008000 , OPCODE_MASK_H32 , put , anyware_inst } ,
{ " nget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C004000 , OPCODE_MASK_H32 , nget , anyware_inst } ,
{ " nput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00C000 , OPCODE_MASK_H32 , nput , anyware_inst } ,
{ " cget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C002000 , OPCODE_MASK_H32 , cget , anyware_inst } ,
{ " cput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00A000 , OPCODE_MASK_H32 , cput , anyware_inst } ,
{ " ncget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C006000 , OPCODE_MASK_H32 , ncget , anyware_inst } ,
{ " ncput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00E000 , OPCODE_MASK_H32 , ncput , anyware_inst } ,
{ " muli " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x60000000 , OPCODE_MASK_H , muli , mult_inst } ,
{ " bslli " , INST_TYPE_RD_R1_IMM5 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x64000400 , OPCODE_MASK_H3 , bslli , barrel_shift_inst } ,
{ " bsrai " , INST_TYPE_RD_R1_IMM5 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x64000200 , OPCODE_MASK_H3 , bsrai , barrel_shift_inst } ,
{ " bsrli " , INST_TYPE_RD_R1_IMM5 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x64000000 , OPCODE_MASK_H3 , bsrli , barrel_shift_inst } ,
2017-04-10 11:32:00 +00:00
{ " or " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x80000000 , OPCODE_MASK_H4 , microblaze_or , logical_inst } ,
{ " and " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x84000000 , OPCODE_MASK_H4 , microblaze_and , logical_inst } ,
{ " xor " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x88000000 , OPCODE_MASK_H4 , microblaze_xor , logical_inst } ,
2012-03-26 19:18:29 +00:00
{ " andn " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x8C000000 , OPCODE_MASK_H4 , andn , logical_inst } ,
{ " pcmpbf " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x80000400 , OPCODE_MASK_H4 , pcmpbf , logical_inst } ,
{ " pcmpbc " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x84000400 , OPCODE_MASK_H4 , pcmpbc , logical_inst } ,
{ " pcmpeq " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x88000400 , OPCODE_MASK_H4 , pcmpeq , logical_inst } ,
{ " pcmpne " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x8C000400 , OPCODE_MASK_H4 , pcmpne , logical_inst } ,
{ " sra " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x90000001 , OPCODE_MASK_H34 , sra , logical_inst } ,
{ " src " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x90000021 , OPCODE_MASK_H34 , src , logical_inst } ,
{ " srl " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x90000041 , OPCODE_MASK_H34 , srl , logical_inst } ,
{ " sext8 " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x90000060 , OPCODE_MASK_H34 , sext8 , logical_inst } ,
{ " sext16 " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x90000061 , OPCODE_MASK_H34 , sext16 , logical_inst } ,
2014-09-12 22:14:23 +00:00
{ " wic " , INST_TYPE_R1_R2_SPECIAL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x90000068 , OPCODE_MASK_H34B , wic , special_inst } ,
{ " wdc " , INST_TYPE_R1_R2_SPECIAL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x90000064 , OPCODE_MASK_H34B , wdc , special_inst } ,
{ " wdc.clear " , INST_TYPE_R1_R2_SPECIAL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x90000066 , OPCODE_MASK_H34B , wdcclear , special_inst } ,
{ " wdc.flush " , INST_TYPE_R1_R2_SPECIAL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x90000074 , OPCODE_MASK_H34B , wdcflush , special_inst } ,
2012-03-26 19:18:29 +00:00
{ " mts " , INST_TYPE_SPECIAL_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_MTS , 0x9400C000 , OPCODE_MASK_H13S , mts , special_inst } ,
{ " mfs " , INST_TYPE_RD_SPECIAL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_MFS , 0x94008000 , OPCODE_MASK_H23S , mfs , special_inst } ,
{ " br " , INST_TYPE_R2 , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x98000000 , OPCODE_MASK_H124 , br , branch_inst } ,
{ " brd " , INST_TYPE_R2 , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x98100000 , OPCODE_MASK_H124 , brd , branch_inst } ,
{ " brld " , INST_TYPE_RD_R2 , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x98140000 , OPCODE_MASK_H24 , brld , branch_inst } ,
{ " bra " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x98080000 , OPCODE_MASK_H124 , bra , branch_inst } ,
{ " brad " , INST_TYPE_R2 , INST_NO_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x98180000 , OPCODE_MASK_H124 , brad , branch_inst } ,
{ " brald " , INST_TYPE_RD_R2 , INST_NO_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x981C0000 , OPCODE_MASK_H24 , brald , branch_inst } ,
{ " brk " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x980C0000 , OPCODE_MASK_H24 , microblaze_brk , branch_inst } ,
{ " beq " , INST_TYPE_R1_R2 , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9C000000 , OPCODE_MASK_H14 , beq , branch_inst } ,
{ " beqd " , INST_TYPE_R1_R2 , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9E000000 , OPCODE_MASK_H14 , beqd , branch_inst } ,
{ " bne " , INST_TYPE_R1_R2 , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9C200000 , OPCODE_MASK_H14 , bne , branch_inst } ,
{ " bned " , INST_TYPE_R1_R2 , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9E200000 , OPCODE_MASK_H14 , bned , branch_inst } ,
{ " blt " , INST_TYPE_R1_R2 , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9C400000 , OPCODE_MASK_H14 , blt , branch_inst } ,
{ " bltd " , INST_TYPE_R1_R2 , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9E400000 , OPCODE_MASK_H14 , bltd , branch_inst } ,
{ " ble " , INST_TYPE_R1_R2 , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9C600000 , OPCODE_MASK_H14 , ble , branch_inst } ,
{ " bled " , INST_TYPE_R1_R2 , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9E600000 , OPCODE_MASK_H14 , bled , branch_inst } ,
{ " bgt " , INST_TYPE_R1_R2 , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9C800000 , OPCODE_MASK_H14 , bgt , branch_inst } ,
{ " bgtd " , INST_TYPE_R1_R2 , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9E800000 , OPCODE_MASK_H14 , bgtd , branch_inst } ,
{ " bge " , INST_TYPE_R1_R2 , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9CA00000 , OPCODE_MASK_H14 , bge , branch_inst } ,
{ " bged " , INST_TYPE_R1_R2 , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x9EA00000 , OPCODE_MASK_H14 , bged , branch_inst } ,
{ " ori " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xA0000000 , OPCODE_MASK_H , ori , logical_inst } ,
{ " andi " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xA4000000 , OPCODE_MASK_H , andi , logical_inst } ,
{ " xori " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xA8000000 , OPCODE_MASK_H , xori , logical_inst } ,
{ " andni " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xAC000000 , OPCODE_MASK_H , andni , logical_inst } ,
{ " imm " , INST_TYPE_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB0000000 , OPCODE_MASK_H12 , imm , immediate_inst } ,
{ " rtsd " , INST_TYPE_R1_IMM , INST_NO_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB6000000 , OPCODE_MASK_H1 , rtsd , return_inst } ,
{ " rtid " , INST_TYPE_R1_IMM , INST_NO_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB6200000 , OPCODE_MASK_H1 , rtid , return_inst } ,
{ " rtbd " , INST_TYPE_R1_IMM , INST_NO_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB6400000 , OPCODE_MASK_H1 , rtbd , return_inst } ,
{ " rted " , INST_TYPE_R1_IMM , INST_NO_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB6800000 , OPCODE_MASK_H1 , rted , return_inst } ,
{ " bri " , INST_TYPE_IMM , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB8000000 , OPCODE_MASK_H12 , bri , branch_inst } ,
{ " brid " , INST_TYPE_IMM , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB8100000 , OPCODE_MASK_H12 , brid , branch_inst } ,
{ " brlid " , INST_TYPE_RD_IMM , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB8140000 , OPCODE_MASK_H2 , brlid , branch_inst } ,
{ " brai " , INST_TYPE_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB8080000 , OPCODE_MASK_H12 , brai , branch_inst } ,
{ " braid " , INST_TYPE_IMM , INST_NO_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB8180000 , OPCODE_MASK_H12 , braid , branch_inst } ,
{ " bralid " , INST_TYPE_RD_IMM , INST_NO_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB81C0000 , OPCODE_MASK_H2 , bralid , branch_inst } ,
{ " brki " , INST_TYPE_RD_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB80C0000 , OPCODE_MASK_H2 , brki , branch_inst } ,
{ " beqi " , INST_TYPE_R1_IMM , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBC000000 , OPCODE_MASK_H1 , beqi , branch_inst } ,
{ " beqid " , INST_TYPE_R1_IMM , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBE000000 , OPCODE_MASK_H1 , beqid , branch_inst } ,
{ " bnei " , INST_TYPE_R1_IMM , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBC200000 , OPCODE_MASK_H1 , bnei , branch_inst } ,
{ " bneid " , INST_TYPE_R1_IMM , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBE200000 , OPCODE_MASK_H1 , bneid , branch_inst } ,
{ " blti " , INST_TYPE_R1_IMM , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBC400000 , OPCODE_MASK_H1 , blti , branch_inst } ,
{ " bltid " , INST_TYPE_R1_IMM , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBE400000 , OPCODE_MASK_H1 , bltid , branch_inst } ,
{ " blei " , INST_TYPE_R1_IMM , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBC600000 , OPCODE_MASK_H1 , blei , branch_inst } ,
{ " bleid " , INST_TYPE_R1_IMM , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBE600000 , OPCODE_MASK_H1 , bleid , branch_inst } ,
{ " bgti " , INST_TYPE_R1_IMM , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBC800000 , OPCODE_MASK_H1 , bgti , branch_inst } ,
{ " bgtid " , INST_TYPE_R1_IMM , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBE800000 , OPCODE_MASK_H1 , bgtid , branch_inst } ,
{ " bgei " , INST_TYPE_R1_IMM , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBCA00000 , OPCODE_MASK_H1 , bgei , branch_inst } ,
{ " bgeid " , INST_TYPE_R1_IMM , INST_PC_OFFSET , DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBEA00000 , OPCODE_MASK_H1 , bgeid , branch_inst } ,
{ " lbu " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xC0000000 , OPCODE_MASK_H4 , lbu , memory_load_inst } ,
2014-09-12 22:14:23 +00:00
{ " lbur " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xC0000200 , OPCODE_MASK_H4 , lbur , memory_load_inst } ,
2012-03-26 19:18:29 +00:00
{ " lhu " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xC4000000 , OPCODE_MASK_H4 , lhu , memory_load_inst } ,
2014-09-12 22:14:23 +00:00
{ " lhur " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xC4000200 , OPCODE_MASK_H4 , lhur , memory_load_inst } ,
2012-03-26 19:18:29 +00:00
{ " lw " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xC8000000 , OPCODE_MASK_H4 , lw , memory_load_inst } ,
2014-09-12 22:14:23 +00:00
{ " lwr " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xC8000200 , OPCODE_MASK_H4 , lwr , memory_load_inst } ,
2012-03-26 19:18:29 +00:00
{ " lwx " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xC8000400 , OPCODE_MASK_H4 , lwx , memory_load_inst } ,
{ " sb " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xD0000000 , OPCODE_MASK_H4 , sb , memory_store_inst } ,
2014-09-12 22:14:23 +00:00
{ " sbr " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xD0000200 , OPCODE_MASK_H4 , sbr , memory_store_inst } ,
2012-03-26 19:18:29 +00:00
{ " sh " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xD4000000 , OPCODE_MASK_H4 , sh , memory_store_inst } ,
2014-09-12 22:14:23 +00:00
{ " shr " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xD4000200 , OPCODE_MASK_H4 , shr , memory_store_inst } ,
2012-03-26 19:18:29 +00:00
{ " sw " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xD8000000 , OPCODE_MASK_H4 , sw , memory_store_inst } ,
2014-09-12 22:14:23 +00:00
{ " swr " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xD8000200 , OPCODE_MASK_H4 , swr , memory_store_inst } ,
2012-03-26 19:18:29 +00:00
{ " swx " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xD8000400 , OPCODE_MASK_H4 , swx , memory_store_inst } ,
{ " lbui " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xE0000000 , OPCODE_MASK_H , lbui , memory_load_inst } ,
{ " lhui " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xE4000000 , OPCODE_MASK_H , lhui , memory_load_inst } ,
{ " lwi " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xE8000000 , OPCODE_MASK_H , lwi , memory_load_inst } ,
{ " sbi " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xF0000000 , OPCODE_MASK_H , sbi , memory_store_inst } ,
{ " shi " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xF4000000 , OPCODE_MASK_H , shi , memory_store_inst } ,
{ " swi " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xF8000000 , OPCODE_MASK_H , swi , memory_store_inst } ,
{ " nop " , INST_TYPE_NONE , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x80000000 , OPCODE_MASK_H1234 , invalid_inst , logical_inst } , /* translates to or r0, r0, r0. */
{ " la " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x30000000 , OPCODE_MASK_H , invalid_inst , arithmetic_inst } , /* la translates to addik. */
{ " tuqula " , INST_TYPE_RD , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x3000002A , OPCODE_MASK_H , invalid_inst , arithmetic_inst } , /* tuqula rd translates to addik rd, r0, 42. */
{ " not " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xA800FFFF , OPCODE_MASK_H34 , invalid_inst , logical_inst } , /* not translates to xori rd,ra,-1. */
{ " neg " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x04000000 , OPCODE_MASK_H , invalid_inst , arithmetic_inst } , /* neg translates to rsub rd, ra, r0. */
{ " rtb " , INST_TYPE_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB6000004 , OPCODE_MASK_H1 , invalid_inst , return_inst } , /* rtb translates to rts rd, 4. */
{ " sub " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x04000000 , OPCODE_MASK_H , invalid_inst , arithmetic_inst } , /* sub translates to rsub rd, rb, ra. */
{ " lmi " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xE8000000 , OPCODE_MASK_H , invalid_inst , memory_load_inst } ,
{ " smi " , INST_TYPE_RD_R1_IMM , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xF8000000 , OPCODE_MASK_H , invalid_inst , memory_store_inst } ,
{ " msrset " , INST_TYPE_RD_IMM15 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x94100000 , OPCODE_MASK_H23N , msrset , special_inst } ,
{ " msrclr " , INST_TYPE_RD_IMM15 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x94110000 , OPCODE_MASK_H23N , msrclr , special_inst } ,
{ " fadd " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000000 , OPCODE_MASK_H4 , fadd , arithmetic_inst } ,
{ " frsub " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000080 , OPCODE_MASK_H4 , frsub , arithmetic_inst } ,
{ " fmul " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000100 , OPCODE_MASK_H4 , fmul , arithmetic_inst } ,
{ " fdiv " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000180 , OPCODE_MASK_H4 , fdiv , arithmetic_inst } ,
{ " fcmp.lt " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000210 , OPCODE_MASK_H4 , fcmp_lt , arithmetic_inst } ,
{ " fcmp.eq " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000220 , OPCODE_MASK_H4 , fcmp_eq , arithmetic_inst } ,
{ " fcmp.le " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000230 , OPCODE_MASK_H4 , fcmp_le , arithmetic_inst } ,
{ " fcmp.gt " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000240 , OPCODE_MASK_H4 , fcmp_gt , arithmetic_inst } ,
{ " fcmp.ne " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000250 , OPCODE_MASK_H4 , fcmp_ne , arithmetic_inst } ,
{ " fcmp.ge " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000260 , OPCODE_MASK_H4 , fcmp_ge , arithmetic_inst } ,
{ " fcmp.un " , INST_TYPE_RD_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000200 , OPCODE_MASK_H4 , fcmp_un , arithmetic_inst } ,
{ " flt " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000280 , OPCODE_MASK_H4 , flt , arithmetic_inst } ,
{ " fint " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000300 , OPCODE_MASK_H4 , fint , arithmetic_inst } ,
{ " fsqrt " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x58000380 , OPCODE_MASK_H4 , fsqrt , arithmetic_inst } ,
{ " tget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C001000 , OPCODE_MASK_H32 , tget , anyware_inst } ,
{ " tcget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C003000 , OPCODE_MASK_H32 , tcget , anyware_inst } ,
{ " tnget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C005000 , OPCODE_MASK_H32 , tnget , anyware_inst } ,
{ " tncget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C007000 , OPCODE_MASK_H32 , tncget , anyware_inst } ,
{ " tput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C009000 , OPCODE_MASK_H32 , tput , anyware_inst } ,
{ " tcput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00B000 , OPCODE_MASK_H32 , tcput , anyware_inst } ,
{ " tnput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00D000 , OPCODE_MASK_H32 , tnput , anyware_inst } ,
{ " tncput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00F000 , OPCODE_MASK_H32 , tncput , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " eget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C000400 , OPCODE_MASK_H32 , eget , anyware_inst } ,
{ " ecget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C002400 , OPCODE_MASK_H32 , ecget , anyware_inst } ,
{ " neget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C004400 , OPCODE_MASK_H32 , neget , anyware_inst } ,
{ " necget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C006400 , OPCODE_MASK_H32 , necget , anyware_inst } ,
{ " eput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C008400 , OPCODE_MASK_H32 , eput , anyware_inst } ,
{ " ecput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00A400 , OPCODE_MASK_H32 , ecput , anyware_inst } ,
{ " neput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00C400 , OPCODE_MASK_H32 , neput , anyware_inst } ,
{ " necput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00E400 , OPCODE_MASK_H32 , necput , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " teget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C001400 , OPCODE_MASK_H32 , teget , anyware_inst } ,
{ " tecget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C003400 , OPCODE_MASK_H32 , tecget , anyware_inst } ,
{ " tneget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C005400 , OPCODE_MASK_H32 , tneget , anyware_inst } ,
{ " tnecget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C007400 , OPCODE_MASK_H32 , tnecget , anyware_inst } ,
{ " teput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C009400 , OPCODE_MASK_H32 , teput , anyware_inst } ,
{ " tecput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00B400 , OPCODE_MASK_H32 , tecput , anyware_inst } ,
{ " tneput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00D400 , OPCODE_MASK_H32 , tneput , anyware_inst } ,
{ " tnecput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00F400 , OPCODE_MASK_H32 , tnecput , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " aget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C000800 , OPCODE_MASK_H32 , aget , anyware_inst } ,
{ " caget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C002800 , OPCODE_MASK_H32 , caget , anyware_inst } ,
{ " naget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C004800 , OPCODE_MASK_H32 , naget , anyware_inst } ,
{ " ncaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C006800 , OPCODE_MASK_H32 , ncaget , anyware_inst } ,
{ " aput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C008800 , OPCODE_MASK_H32 , aput , anyware_inst } ,
{ " caput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00A800 , OPCODE_MASK_H32 , caput , anyware_inst } ,
{ " naput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00C800 , OPCODE_MASK_H32 , naput , anyware_inst } ,
{ " ncaput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00E800 , OPCODE_MASK_H32 , ncaput , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " taget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C001800 , OPCODE_MASK_H32 , taget , anyware_inst } ,
{ " tcaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C003800 , OPCODE_MASK_H32 , tcaget , anyware_inst } ,
{ " tnaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C005800 , OPCODE_MASK_H32 , tnaget , anyware_inst } ,
{ " tncaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C007800 , OPCODE_MASK_H32 , tncaget , anyware_inst } ,
{ " taput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C009800 , OPCODE_MASK_H32 , taput , anyware_inst } ,
{ " tcaput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00B800 , OPCODE_MASK_H32 , tcaput , anyware_inst } ,
{ " tnaput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00D800 , OPCODE_MASK_H32 , tnaput , anyware_inst } ,
{ " tncaput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00F800 , OPCODE_MASK_H32 , tncaput , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " eaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C000C00 , OPCODE_MASK_H32 , eget , anyware_inst } ,
{ " ecaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C002C00 , OPCODE_MASK_H32 , ecget , anyware_inst } ,
{ " neaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C004C00 , OPCODE_MASK_H32 , neget , anyware_inst } ,
{ " necaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C006C00 , OPCODE_MASK_H32 , necget , anyware_inst } ,
{ " eaput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C008C00 , OPCODE_MASK_H32 , eput , anyware_inst } ,
{ " ecaput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00AC00 , OPCODE_MASK_H32 , ecput , anyware_inst } ,
{ " neaput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00CC00 , OPCODE_MASK_H32 , neput , anyware_inst } ,
{ " necaput " , INST_TYPE_R1_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00EC00 , OPCODE_MASK_H32 , necput , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " teaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C001C00 , OPCODE_MASK_H32 , teaget , anyware_inst } ,
{ " tecaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C003C00 , OPCODE_MASK_H32 , tecaget , anyware_inst } ,
{ " tneaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C005C00 , OPCODE_MASK_H32 , tneaget , anyware_inst } ,
{ " tnecaget " , INST_TYPE_RD_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C007C00 , OPCODE_MASK_H32 , tnecaget , anyware_inst } ,
{ " teaput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C009C00 , OPCODE_MASK_H32 , teaput , anyware_inst } ,
{ " tecaput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00BC00 , OPCODE_MASK_H32 , tecaput , anyware_inst } ,
{ " tneaput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00DC00 , OPCODE_MASK_H32 , tneaput , anyware_inst } ,
{ " tnecaput " , INST_TYPE_RFSL , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x6C00FC00 , OPCODE_MASK_H32 , tnecaput , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " getd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000000 , OPCODE_MASK_H34C , getd , anyware_inst } ,
{ " tgetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000080 , OPCODE_MASK_H34C , tgetd , anyware_inst } ,
{ " cgetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000100 , OPCODE_MASK_H34C , cgetd , anyware_inst } ,
{ " tcgetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000180 , OPCODE_MASK_H34C , tcgetd , anyware_inst } ,
{ " ngetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000200 , OPCODE_MASK_H34C , ngetd , anyware_inst } ,
{ " tngetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000280 , OPCODE_MASK_H34C , tngetd , anyware_inst } ,
{ " ncgetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000300 , OPCODE_MASK_H34C , ncgetd , anyware_inst } ,
{ " tncgetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000380 , OPCODE_MASK_H34C , tncgetd , anyware_inst } ,
{ " putd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000400 , OPCODE_MASK_H34C , putd , anyware_inst } ,
{ " tputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000480 , OPCODE_MASK_H34C , tputd , anyware_inst } ,
{ " cputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000500 , OPCODE_MASK_H34C , cputd , anyware_inst } ,
{ " tcputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000580 , OPCODE_MASK_H34C , tcputd , anyware_inst } ,
{ " nputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000600 , OPCODE_MASK_H34C , nputd , anyware_inst } ,
{ " tnputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000680 , OPCODE_MASK_H34C , tnputd , anyware_inst } ,
{ " ncputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000700 , OPCODE_MASK_H34C , ncputd , anyware_inst } ,
{ " tncputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000780 , OPCODE_MASK_H34C , tncputd , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " egetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000020 , OPCODE_MASK_H34C , egetd , anyware_inst } ,
{ " tegetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0000A0 , OPCODE_MASK_H34C , tegetd , anyware_inst } ,
{ " ecgetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000120 , OPCODE_MASK_H34C , ecgetd , anyware_inst } ,
{ " tecgetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0001A0 , OPCODE_MASK_H34C , tecgetd , anyware_inst } ,
{ " negetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000220 , OPCODE_MASK_H34C , negetd , anyware_inst } ,
{ " tnegetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0002A0 , OPCODE_MASK_H34C , tnegetd , anyware_inst } ,
{ " necgetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000320 , OPCODE_MASK_H34C , necgetd , anyware_inst } ,
{ " tnecgetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0003A0 , OPCODE_MASK_H34C , tnecgetd , anyware_inst } ,
{ " eputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000420 , OPCODE_MASK_H34C , eputd , anyware_inst } ,
{ " teputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0004A0 , OPCODE_MASK_H34C , teputd , anyware_inst } ,
{ " ecputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000520 , OPCODE_MASK_H34C , ecputd , anyware_inst } ,
{ " tecputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0005A0 , OPCODE_MASK_H34C , tecputd , anyware_inst } ,
{ " neputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000620 , OPCODE_MASK_H34C , neputd , anyware_inst } ,
{ " tneputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0006A0 , OPCODE_MASK_H34C , tneputd , anyware_inst } ,
{ " necputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000720 , OPCODE_MASK_H34C , necputd , anyware_inst } ,
{ " tnecputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0007A0 , OPCODE_MASK_H34C , tnecputd , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " agetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000040 , OPCODE_MASK_H34C , agetd , anyware_inst } ,
{ " tagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0000C0 , OPCODE_MASK_H34C , tagetd , anyware_inst } ,
{ " cagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000140 , OPCODE_MASK_H34C , cagetd , anyware_inst } ,
{ " tcagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0001C0 , OPCODE_MASK_H34C , tcagetd , anyware_inst } ,
{ " nagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000240 , OPCODE_MASK_H34C , nagetd , anyware_inst } ,
{ " tnagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0002C0 , OPCODE_MASK_H34C , tnagetd , anyware_inst } ,
{ " ncagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000340 , OPCODE_MASK_H34C , ncagetd , anyware_inst } ,
{ " tncagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0003C0 , OPCODE_MASK_H34C , tncagetd , anyware_inst } ,
{ " aputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000440 , OPCODE_MASK_H34C , aputd , anyware_inst } ,
{ " taputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0004C0 , OPCODE_MASK_H34C , taputd , anyware_inst } ,
{ " caputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000540 , OPCODE_MASK_H34C , caputd , anyware_inst } ,
{ " tcaputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0005C0 , OPCODE_MASK_H34C , tcaputd , anyware_inst } ,
{ " naputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000640 , OPCODE_MASK_H34C , naputd , anyware_inst } ,
{ " tnaputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0006C0 , OPCODE_MASK_H34C , tnaputd , anyware_inst } ,
{ " ncaputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000740 , OPCODE_MASK_H34C , ncaputd , anyware_inst } ,
{ " tncaputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0007C0 , OPCODE_MASK_H34C , tncaputd , anyware_inst } ,
2017-04-10 11:32:00 +00:00
2012-03-26 19:18:29 +00:00
{ " eagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000060 , OPCODE_MASK_H34C , eagetd , anyware_inst } ,
{ " teagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0000E0 , OPCODE_MASK_H34C , teagetd , anyware_inst } ,
{ " ecagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000160 , OPCODE_MASK_H34C , ecagetd , anyware_inst } ,
{ " tecagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0001E0 , OPCODE_MASK_H34C , tecagetd , anyware_inst } ,
{ " neagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000260 , OPCODE_MASK_H34C , neagetd , anyware_inst } ,
{ " tneagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0002E0 , OPCODE_MASK_H34C , tneagetd , anyware_inst } ,
{ " necagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000360 , OPCODE_MASK_H34C , necagetd , anyware_inst } ,
{ " tnecagetd " , INST_TYPE_RD_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0003E0 , OPCODE_MASK_H34C , tnecagetd , anyware_inst } ,
{ " eaputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000460 , OPCODE_MASK_H34C , eaputd , anyware_inst } ,
{ " teaputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0004E0 , OPCODE_MASK_H34C , teaputd , anyware_inst } ,
{ " ecaputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000560 , OPCODE_MASK_H34C , ecaputd , anyware_inst } ,
{ " tecaputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0005E0 , OPCODE_MASK_H34C , tecaputd , anyware_inst } ,
{ " neaputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000660 , OPCODE_MASK_H34C , neaputd , anyware_inst } ,
{ " tneaputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0006E0 , OPCODE_MASK_H34C , tneaputd , anyware_inst } ,
{ " necaputd " , INST_TYPE_R1_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C000760 , OPCODE_MASK_H34C , necaputd , anyware_inst } ,
{ " tnecaputd " , INST_TYPE_R2 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x4C0007E0 , OPCODE_MASK_H34C , tnecaputd , anyware_inst } ,
2014-09-12 22:14:23 +00:00
{ " clz " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x900000E0 , OPCODE_MASK_H34 , clz , special_inst } ,
{ " mbar " , INST_TYPE_IMM5 , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xB8020004 , OPCODE_MASK_HN , mbar , special_inst } ,
{ " sleep " , INST_TYPE_NONE , INST_PC_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0xBA020004 , OPCODE_MASK_HN , invalid_inst , special_inst } , /* translates to mbar 16. */
{ " swapb " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x900001E0 , OPCODE_MASK_H4 , swapb , arithmetic_inst } ,
{ " swaph " , INST_TYPE_RD_R1 , INST_NO_OFFSET , NO_DELAY_SLOT , IMMVAL_MASK_NON_SPECIAL , 0x900001E2 , OPCODE_MASK_H4 , swaph , arithmetic_inst } ,
2012-03-26 19:18:29 +00:00
{ " " , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 } ,
} ;
/* Prefix for register names. */
char register_prefix [ ] = " r " ;
char special_register_prefix [ ] = " spr " ;
char fsl_register_prefix [ ] = " rfsl " ;
char pvr_register_prefix [ ] = " rpvr " ;
/* #defines for valid immediate range. */
# define MIN_IMM ((int) 0x80000000)
# define MAX_IMM ((int) 0x7fffffff)
# define MIN_IMM15 ((int) 0x0000)
# define MAX_IMM15 ((int) 0x7fff)
2014-09-12 22:14:23 +00:00
# define MIN_IMM5 ((int) 0x00000000)
# define MAX_IMM5 ((int) 0x0000001f)
2012-03-26 19:18:29 +00:00
# endif /* MICROBLAZE_OPC */