2014-09-12 22:14:23 +00:00
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#source: elfv2.s
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#as: -a64
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#ld: -melf64ppc --defsym f2=0x1234 --defsym f3=0x10008888 --defsym f4=0x1200000 --defsym _start=f1
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#objdump: -dr
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.*
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Disassembly of section \.text:
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0+100000c0 <.*\.plt_branch\.f2>:
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2015-08-28 15:32:19 +00:00
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.*: (3d 82 ff ff|ff ff 82 3d) addis r12,r2,-1
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2017-04-10 11:32:00 +00:00
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.*: (e9 8c 7f 28|28 7f 8c e9) ld r12,32552\(r12\)
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2015-08-28 15:32:19 +00:00
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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2014-09-12 22:14:23 +00:00
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0+100000d0 <.*\.plt_branch\.f4>:
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2015-08-28 15:32:19 +00:00
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.*: (3d 82 ff ff|ff ff 82 3d) addis r12,r2,-1
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2017-04-10 11:32:00 +00:00
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.*: (e9 8c 7f 30|30 7f 8c e9) ld r12,32560\(r12\)
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2015-08-28 15:32:19 +00:00
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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2014-09-12 22:14:23 +00:00
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2017-04-10 11:32:00 +00:00
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0+100000e0 <(f1|_start)>:
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2015-08-28 15:32:19 +00:00
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.*: (3c 40 10 02|02 10 40 3c) lis r2,4098
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.*: (38 42 82 00|00 82 42 38) addi r2,r2,-32256
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.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
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.*: (f8 21 ff e1|e1 ff 21 f8) stdu r1,-32\(r1\)
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.*: (f8 01 00 30|30 00 01 f8) std r0,48\(r1\)
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2017-04-10 11:32:00 +00:00
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.*: (4b ff ff f5|f5 ff ff 4b) bl .* <(f1|_start)\+0x8>
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2015-08-28 15:32:19 +00:00
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.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
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.*: (4b ff ff c5|c5 ff ff 4b) bl .*\.plt_branch\.f2>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (e8 62 80 10|10 80 62 e8) ld r3,-32752\(r2\)
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.*: (48 00 87 81|81 87 00 48) bl 10008888 <f3>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (4b ff ff c1|c1 ff ff 4b) bl .*\.plt_branch\.f4>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (e8 01 00 30|30 00 01 e8) ld r0,48\(r1\)
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.*: (38 21 00 20|20 00 21 38) addi r1,r1,32
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.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
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.*: (4e 80 00 20|20 00 80 4e) blr
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