2014-09-21 17:33:12 +00:00
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/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
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2017-10-07 00:16:47 +00:00
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Copyright (C) 2012-2017 Free Software Foundation, Inc.
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2014-09-21 17:33:12 +00:00
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Contributed by Andes Technology Corporation.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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.macro SAVE_ALL_4B
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#ifdef __NDS32_REDUCED_REGS__
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smw.adm $r15, [$sp], $r15, #0xf
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smw.adm $r0, [$sp], $r10, #0x0
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#else /* not __NDS32_REDUCED_REGS__ */
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smw.adm $r0, [$sp], $r27, #0xf
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#endif /* not __NDS32_REDUCED_REGS__ */
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#ifdef NDS32_EXT_IFC
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mfusr $r1, $IFC_LP
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smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
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stack 8-byte alignment. */
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#endif
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SAVE_MAC_REGS
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SAVE_FPU_REGS
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mfsr $r1, $IPC /* Get IPC. */
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mfsr $r2, $IPSW /* Get IPSW. */
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smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
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move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
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mfsr $r0, $ITYPE /* Get VID to $r0. */
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srli $r0, $r0, #5
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#ifdef __NDS32_ISA_V2__
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andi $r0, $r0, #127
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#else
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fexti33 $r0, #6
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#endif
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.endm
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.macro SAVE_ALL
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/* SAVE_REG_TBL code has been moved to
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vector table generated by compiler. */
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#ifdef NDS32_EXT_IFC
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mfusr $r1, $IFC_LP
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smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
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stack 8-byte alignment. */
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#endif
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SAVE_MAC_REGS
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SAVE_FPU_REGS
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mfsr $r1, $IPC /* Get IPC. */
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mfsr $r2, $IPSW /* Get IPSW. */
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smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
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move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
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.endm
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