2014-09-12 22:14:23 +00:00
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/* Assembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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- the resultant file is machine generated, cgen-asm.in isn't
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2017-04-10 11:32:00 +00:00
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Copyright (C) 1996-2017 Free Software Foundation, Inc.
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2014-09-12 22:14:23 +00:00
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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Keep that in mind. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "epiphany-desc.h"
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#include "epiphany-opc.h"
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#include "opintl.h"
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#include "xregex.h"
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#include "libiberty.h"
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#include "safe-ctype.h"
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#undef min
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#define min(a,b) ((a) < (b) ? (a) : (b))
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#undef max
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#define max(a,b) ((a) > (b) ? (a) : (b))
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static const char * parse_insn_normal
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(CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
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/* -- assembler routines inserted here. */
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/* -- asm.c */
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const char *
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parse_shortregs (CGEN_CPU_DESC cd,
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const char ** strp,
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CGEN_KEYWORD * keywords,
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long * regno)
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{
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const char * errmsg;
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/* Parse register. */
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errmsg = cgen_parse_keyword (cd, strp, keywords, regno);
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if (errmsg)
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return errmsg;
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if (*regno > 7)
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errmsg = _("register unavailable for short instructions");
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return errmsg;
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}
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static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int,
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long *);
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static const char *
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parse_uimm_not_reg (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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unsigned long * valuep)
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{
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long * svalp = (void *) valuep;
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return parse_simm_not_reg (cd, strp, opindex, svalp);
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}
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/* Handle simm3/simm11/imm3/imm12. */
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static const char *
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parse_simm_not_reg (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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long * valuep)
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{
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const char * errmsg;
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int sign = 0;
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int bits = 0;
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switch (opindex)
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{
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case EPIPHANY_OPERAND_SIMM3:
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sign = 1; bits = 3; break;
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case EPIPHANY_OPERAND_SIMM11:
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sign = 1; bits = 11; break;
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case EPIPHANY_OPERAND_DISP3:
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sign = 0; bits = 3; break;
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case EPIPHANY_OPERAND_DISP11:
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/* Load/store displacement is a sign-magnitude 12 bit value. */
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sign = 0; bits = 11; break;
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}
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/* First try to parse as a register name and reject the operand. */
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errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep);
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if (!errmsg)
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return _("register name used as immediate value");
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errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep)
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: cgen_parse_unsigned_integer (cd, strp, opindex,
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(unsigned long *) valuep));
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if (errmsg)
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return errmsg;
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if (sign)
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errmsg = cgen_validate_signed_integer (*valuep,
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-((1L << bits) - 1), (1 << (bits - 1)) - 1);
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else
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errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1);
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return errmsg;
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}
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static const char *
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parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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const char ** strp,
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int opindex ATTRIBUTE_UNUSED,
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unsigned long *valuep)
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{
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if (**strp == '#')
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++*strp; /* Skip leading hashes. */
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if (**strp == '-')
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{
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*valuep = 1;
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++*strp;
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}
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else if (**strp == '+')
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{
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*valuep = 0;
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++*strp;
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}
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else
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*valuep = 0;
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return NULL;
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}
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static const char *
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parse_imm8 (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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bfd_reloc_code_real_type code,
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enum cgen_parse_operand_result * result_type,
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bfd_vma * valuep)
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{
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const char * errmsg;
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enum cgen_parse_operand_result rt;
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long dummyval;
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if (!result_type)
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result_type = &rt;
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code = BFD_RELOC_NONE;
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if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval)
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|| !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
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&dummyval))
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/* Don't treat "mov ip,ip" as a move-immediate. */
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return _("register source in immediate move");
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errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep);
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if (errmsg)
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return errmsg;
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if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff);
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else
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errmsg = _("byte relocation unsupported");
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*valuep &= 0xff;
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return errmsg;
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}
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static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'");
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static const char *
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parse_imm16 (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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bfd_reloc_code_real_type code ATTRIBUTE_UNUSED,
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enum cgen_parse_operand_result * result_type,
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bfd_vma * valuep)
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{
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const char * errmsg;
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enum cgen_parse_operand_result rt;
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long dummyval;
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if (!result_type)
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result_type = &rt;
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if (strncasecmp (*strp, "%high(", 6) == 0)
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{
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*strp += 6;
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH,
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result_type, valuep);
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if (**strp != ')')
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return MISSING_CLOSE_PARENTHESIS;
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++*strp;
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*valuep >>= 16;
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}
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else if (strncasecmp (*strp, "%low(", 5) == 0)
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{
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*strp += 5;
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW,
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result_type, valuep);
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if (**strp != ')')
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return MISSING_CLOSE_PARENTHESIS;
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++*strp;
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}
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else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names,
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&dummyval)
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|| !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
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&dummyval))
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/* Don't treat "mov ip,ip" as a move-immediate. */
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return _("register source in immediate move");
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else
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
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result_type, valuep);
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if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff);
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*valuep &= 0xffff;
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return errmsg;
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}
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const char *
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parse_branch_addr (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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int opinfo ATTRIBUTE_UNUSED,
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enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED,
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bfd_vma *valuep ATTRIBUTE_UNUSED)
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{
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const char * errmsg;
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enum cgen_parse_operand_result result_type;
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bfd_reloc_code_real_type code = BFD_RELOC_NONE;
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bfd_vma value;
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switch (opindex)
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{
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case EPIPHANY_OPERAND_SIMM24:
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code = BFD_RELOC_EPIPHANY_SIMM24;
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break;
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case EPIPHANY_OPERAND_SIMM8:
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code = BFD_RELOC_EPIPHANY_SIMM8;
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break;
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default:
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errmsg = _("ABORT: unknown operand");
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return errmsg;
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}
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errmsg = cgen_parse_address (cd, strp, opindex, code,
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&result_type, &value);
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if (errmsg == NULL)
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{
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if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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{
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/* Act as if we had done a PC-relative branch, ala .+num. */
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char buf[20];
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const char * bufp = (const char *) buf;
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sprintf (buf, ".+%ld", (long) value);
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errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type,
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&value);
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}
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if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED)
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{
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/* This will happen for things like (s2-s1) where s2 and s1
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are labels. */
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/* Nothing further to be done. */
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}
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else
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errmsg = _("Not a pc-relative address.");
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}
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return errmsg;
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}
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/* -- dis.c */
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const char * epiphany_cgen_parse_operand
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(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
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/* Main entry point for operand parsing.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `parse_insn_normal', but keeping it
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separate makes clear the interface between `parse_insn_normal' and each of
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the handlers. */
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const char *
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epiphany_cgen_parse_operand (CGEN_CPU_DESC cd,
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int opindex,
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const char ** strp,
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CGEN_FIELDS * fields)
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{
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const char * errmsg = NULL;
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/* Used by scalar operands that still need to be parsed. */
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long junk ATTRIBUTE_UNUSED;
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switch (opindex)
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{
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case EPIPHANY_OPERAND_DIRECTION :
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|
|
errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DIRECTION, (unsigned long *) (& fields->f_addsubx));
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_DISP11 :
|
|
|
|
|
errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_DISP11, (unsigned long *) (& fields->f_disp11));
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_DISP3 :
|
|
|
|
|
errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_DISP3, (unsigned long *) (& fields->f_disp3));
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_DPMI :
|
|
|
|
|
errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DPMI, (unsigned long *) (& fields->f_subd));
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_FRD :
|
|
|
|
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_FRD6 :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_FRM :
|
|
|
|
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_FRM6 :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_FRN :
|
|
|
|
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_FRN6 :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_IMM16 :
|
|
|
|
|
{
|
|
|
|
|
bfd_vma value = 0;
|
|
|
|
|
errmsg = parse_imm16 (cd, strp, EPIPHANY_OPERAND_IMM16, 0, NULL, & value);
|
|
|
|
|
fields->f_imm16 = value;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_IMM8 :
|
|
|
|
|
{
|
|
|
|
|
bfd_vma value = 0;
|
|
|
|
|
errmsg = parse_imm8 (cd, strp, EPIPHANY_OPERAND_IMM8, 0, NULL, & value);
|
|
|
|
|
fields->f_imm8 = value;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_RD :
|
|
|
|
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_RD6 :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_RM :
|
|
|
|
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_RM6 :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_RN :
|
|
|
|
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_RN6 :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SD :
|
|
|
|
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SD6 :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SDDMA :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sd6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SDMEM :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sd6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SDMESH :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sd6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SHIFT :
|
|
|
|
|
errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_SHIFT, (unsigned long *) (& fields->f_shift));
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SIMM11 :
|
|
|
|
|
errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM11, (long *) (& fields->f_sdisp11));
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SIMM24 :
|
|
|
|
|
{
|
|
|
|
|
bfd_vma value = 0;
|
|
|
|
|
errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM24, 0, NULL, & value);
|
|
|
|
|
fields->f_simm24 = value;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SIMM3 :
|
|
|
|
|
errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM3, (long *) (& fields->f_sdisp3));
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SIMM8 :
|
|
|
|
|
{
|
|
|
|
|
bfd_vma value = 0;
|
|
|
|
|
errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM8, 0, NULL, & value);
|
|
|
|
|
fields->f_simm8 = value;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SN :
|
|
|
|
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SN6 :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SNDMA :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sn6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SNMEM :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sn6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SNMESH :
|
|
|
|
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sn6);
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_SWI_NUM :
|
|
|
|
|
errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_SWI_NUM, (unsigned long *) (& fields->f_trap_num));
|
|
|
|
|
break;
|
|
|
|
|
case EPIPHANY_OPERAND_TRAPNUM6 :
|
|
|
|
|
errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_TRAPNUM6, (unsigned long *) (& fields->f_trap_num));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default :
|
|
|
|
|
/* xgettext:c-format */
|
|
|
|
|
fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
|
|
|
|
|
abort ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return errmsg;
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
cgen_parse_fn * const epiphany_cgen_parse_handlers[] =
|
2014-09-12 22:14:23 +00:00
|
|
|
|
{
|
|
|
|
|
parse_insn_normal,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
epiphany_cgen_init_asm (CGEN_CPU_DESC cd)
|
|
|
|
|
{
|
|
|
|
|
epiphany_cgen_init_opcode_table (cd);
|
|
|
|
|
epiphany_cgen_init_ibld_table (cd);
|
|
|
|
|
cd->parse_handlers = & epiphany_cgen_parse_handlers[0];
|
|
|
|
|
cd->parse_operand = epiphany_cgen_parse_operand;
|
|
|
|
|
#ifdef CGEN_ASM_INIT_HOOK
|
|
|
|
|
CGEN_ASM_INIT_HOOK
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Regex construction routine.
|
|
|
|
|
|
|
|
|
|
This translates an opcode syntax string into a regex string,
|
|
|
|
|
by replacing any non-character syntax element (such as an
|
|
|
|
|
opcode) with the pattern '.*'
|
|
|
|
|
|
|
|
|
|
It then compiles the regex and stores it in the opcode, for
|
|
|
|
|
later use by epiphany_cgen_assemble_insn
|
|
|
|
|
|
|
|
|
|
Returns NULL for success, an error message for failure. */
|
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
char *
|
2014-09-12 22:14:23 +00:00
|
|
|
|
epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
|
2017-04-10 11:32:00 +00:00
|
|
|
|
{
|
2014-09-12 22:14:23 +00:00
|
|
|
|
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
|
|
|
|
|
const char *mnem = CGEN_INSN_MNEMONIC (insn);
|
|
|
|
|
char rxbuf[CGEN_MAX_RX_ELEMENTS];
|
|
|
|
|
char *rx = rxbuf;
|
|
|
|
|
const CGEN_SYNTAX_CHAR_TYPE *syn;
|
|
|
|
|
int reg_err;
|
|
|
|
|
|
|
|
|
|
syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
|
|
|
|
|
|
|
|
|
|
/* Mnemonics come first in the syntax string. */
|
|
|
|
|
if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
|
|
|
|
|
return _("missing mnemonic in syntax string");
|
|
|
|
|
++syn;
|
|
|
|
|
|
|
|
|
|
/* Generate a case sensitive regular expression that emulates case
|
|
|
|
|
insensitive matching in the "C" locale. We cannot generate a case
|
|
|
|
|
insensitive regular expression because in Turkish locales, 'i' and 'I'
|
|
|
|
|
are not equal modulo case conversion. */
|
|
|
|
|
|
|
|
|
|
/* Copy the literal mnemonic out of the insn. */
|
|
|
|
|
for (; *mnem; mnem++)
|
|
|
|
|
{
|
|
|
|
|
char c = *mnem;
|
|
|
|
|
|
|
|
|
|
if (ISALPHA (c))
|
|
|
|
|
{
|
|
|
|
|
*rx++ = '[';
|
|
|
|
|
*rx++ = TOLOWER (c);
|
|
|
|
|
*rx++ = TOUPPER (c);
|
|
|
|
|
*rx++ = ']';
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
*rx++ = c;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Copy any remaining literals from the syntax string into the rx. */
|
|
|
|
|
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
|
|
|
|
|
{
|
2017-04-10 11:32:00 +00:00
|
|
|
|
if (CGEN_SYNTAX_CHAR_P (* syn))
|
2014-09-12 22:14:23 +00:00
|
|
|
|
{
|
|
|
|
|
char c = CGEN_SYNTAX_CHAR (* syn);
|
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
switch (c)
|
2014-09-12 22:14:23 +00:00
|
|
|
|
{
|
|
|
|
|
/* Escape any regex metacharacters in the syntax. */
|
2017-04-10 11:32:00 +00:00
|
|
|
|
case '.': case '[': case '\\':
|
|
|
|
|
case '*': case '^': case '$':
|
2014-09-12 22:14:23 +00:00
|
|
|
|
|
|
|
|
|
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
|
2017-04-10 11:32:00 +00:00
|
|
|
|
case '?': case '{': case '}':
|
2014-09-12 22:14:23 +00:00
|
|
|
|
case '(': case ')': case '*':
|
|
|
|
|
case '|': case '+': case ']':
|
|
|
|
|
#endif
|
|
|
|
|
*rx++ = '\\';
|
|
|
|
|
*rx++ = c;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
if (ISALPHA (c))
|
|
|
|
|
{
|
|
|
|
|
*rx++ = '[';
|
|
|
|
|
*rx++ = TOLOWER (c);
|
|
|
|
|
*rx++ = TOUPPER (c);
|
|
|
|
|
*rx++ = ']';
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
*rx++ = c;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Replace non-syntax fields with globs. */
|
|
|
|
|
*rx++ = '.';
|
|
|
|
|
*rx++ = '*';
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Trailing whitespace ok. */
|
2017-04-10 11:32:00 +00:00
|
|
|
|
* rx++ = '[';
|
|
|
|
|
* rx++ = ' ';
|
|
|
|
|
* rx++ = '\t';
|
|
|
|
|
* rx++ = ']';
|
|
|
|
|
* rx++ = '*';
|
2014-09-12 22:14:23 +00:00
|
|
|
|
|
|
|
|
|
/* But anchor it after that. */
|
2017-04-10 11:32:00 +00:00
|
|
|
|
* rx++ = '$';
|
2014-09-12 22:14:23 +00:00
|
|
|
|
* rx = '\0';
|
|
|
|
|
|
|
|
|
|
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
|
|
|
|
|
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
|
|
|
|
|
|
2017-04-10 11:32:00 +00:00
|
|
|
|
if (reg_err == 0)
|
2014-09-12 22:14:23 +00:00
|
|
|
|
return NULL;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
static char msg[80];
|
|
|
|
|
|
|
|
|
|
regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
|
|
|
|
|
regfree ((regex_t *) CGEN_INSN_RX (insn));
|
|
|
|
|
free (CGEN_INSN_RX (insn));
|
|
|
|
|
(CGEN_INSN_RX (insn)) = NULL;
|
|
|
|
|
return msg;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Default insn parser.
|
|
|
|
|
|
|
|
|
|
The syntax string is scanned and operands are parsed and stored in FIELDS.
|
|
|
|
|
Relocs are queued as we go via other callbacks.
|
|
|
|
|
|
|
|
|
|
??? Note that this is currently an all-or-nothing parser. If we fail to
|
|
|
|
|
parse the instruction, we return 0 and the caller will start over from
|
|
|
|
|
the beginning. Backtracking will be necessary in parsing subexpressions,
|
|
|
|
|
but that can be handled there. Not handling backtracking here may get
|
|
|
|
|
expensive in the case of the m68k. Deal with later.
|
|
|
|
|
|
|
|
|
|
Returns NULL for success, an error message for failure. */
|
|
|
|
|
|
|
|
|
|
static const char *
|
|
|
|
|
parse_insn_normal (CGEN_CPU_DESC cd,
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const CGEN_INSN *insn,
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const char **strp,
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CGEN_FIELDS *fields)
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{
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/* ??? Runtime added insns not handled yet. */
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const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
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const char *str = *strp;
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const char *errmsg;
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const char *p;
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const CGEN_SYNTAX_CHAR_TYPE * syn;
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#ifdef CGEN_MNEMONIC_OPERANDS
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/* FIXME: wip */
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int past_opcode_p;
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#endif
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/* For now we assume the mnemonic is first (there are no leading operands).
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We can parse it without needing to set up operand parsing.
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GAS's input scrubber will ensure mnemonics are lowercase, but we may
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not be called from GAS. */
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p = CGEN_INSN_MNEMONIC (insn);
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while (*p && TOLOWER (*p) == TOLOWER (*str))
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++p, ++str;
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if (* p)
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return _("unrecognized instruction");
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#ifndef CGEN_MNEMONIC_OPERANDS
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if (* str && ! ISSPACE (* str))
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return _("unrecognized instruction");
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#endif
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CGEN_INIT_PARSE (cd);
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cgen_init_parse_operand (cd);
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#ifdef CGEN_MNEMONIC_OPERANDS
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past_opcode_p = 0;
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#endif
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/* We don't check for (*str != '\0') here because we want to parse
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any trailing fake arguments in the syntax string. */
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syn = CGEN_SYNTAX_STRING (syntax);
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/* Mnemonics come first for now, ensure valid string. */
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if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
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abort ();
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++syn;
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while (* syn != 0)
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{
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/* Non operand chars must match exactly. */
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if (CGEN_SYNTAX_CHAR_P (* syn))
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{
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/* FIXME: While we allow for non-GAS callers above, we assume the
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first char after the mnemonic part is a space. */
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/* FIXME: We also take inappropriate advantage of the fact that
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GAS's input scrubber will remove extraneous blanks. */
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if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
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{
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#ifdef CGEN_MNEMONIC_OPERANDS
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if (CGEN_SYNTAX_CHAR(* syn) == ' ')
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past_opcode_p = 1;
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#endif
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++ syn;
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++ str;
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}
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else if (*str)
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{
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/* Syntax char didn't match. Can't be this insn. */
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static char msg [80];
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/* xgettext:c-format */
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sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
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CGEN_SYNTAX_CHAR(*syn), *str);
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return msg;
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}
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else
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{
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/* Ran out of input. */
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static char msg [80];
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/* xgettext:c-format */
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sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
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CGEN_SYNTAX_CHAR(*syn));
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return msg;
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}
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continue;
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}
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#ifdef CGEN_MNEMONIC_OPERANDS
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(void) past_opcode_p;
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#endif
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/* We have an operand of some sort. */
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errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
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if (errmsg)
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return errmsg;
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/* Done with this operand, continue with next one. */
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++ syn;
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}
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/* If we're at the end of the syntax string, we're done. */
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if (* syn == 0)
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{
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/* FIXME: For the moment we assume a valid `str' can only contain
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blanks now. IE: We needn't try again with a longer version of
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the insn and it is assumed that longer versions of insns appear
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before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
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while (ISSPACE (* str))
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++ str;
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if (* str != '\0')
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return _("junk at end of line"); /* FIXME: would like to include `str' */
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return NULL;
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}
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/* We couldn't parse it. */
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return _("unrecognized instruction");
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}
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/* Main entry point.
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This routine is called for each instruction to be assembled.
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STR points to the insn to be assembled.
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We assume all necessary tables have been initialized.
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The assembled instruction, less any fixups, is stored in BUF.
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Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
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still needs to be converted to target byte order, otherwise BUF is an array
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of bytes in target byte order.
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The result is a pointer to the insn's entry in the opcode table,
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or NULL if an error occured (an error message will have already been
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printed).
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Note that when processing (non-alias) macro-insns,
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this function recurses.
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??? It's possible to make this cpu-independent.
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One would have to deal with a few minor things.
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At this point in time doing so would be more of a curiosity than useful
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[for example this file isn't _that_ big], but keeping the possibility in
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mind helps keep the design clean. */
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const CGEN_INSN *
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epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
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const char *str,
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CGEN_FIELDS *fields,
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CGEN_INSN_BYTES_PTR buf,
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char **errmsg)
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{
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const char *start;
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CGEN_INSN_LIST *ilist;
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const char *parse_errmsg = NULL;
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const char *insert_errmsg = NULL;
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int recognized_mnemonic = 0;
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/* Skip leading white space. */
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while (ISSPACE (* str))
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++ str;
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/* The instructions are stored in hashed lists.
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Get the first in the list. */
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ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
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/* Keep looking until we find a match. */
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start = str;
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for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
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{
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const CGEN_INSN *insn = ilist->insn;
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recognized_mnemonic = 1;
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2017-04-10 11:32:00 +00:00
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#ifdef CGEN_VALIDATE_INSN_SUPPORTED
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2014-09-12 22:14:23 +00:00
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/* Not usually needed as unsupported opcodes
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shouldn't be in the hash lists. */
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/* Is this insn supported by the selected cpu? */
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if (! epiphany_cgen_insn_supported (cd, insn))
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continue;
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#endif
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/* If the RELAXED attribute is set, this is an insn that shouldn't be
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chosen immediately. Instead, it is used during assembler/linker
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relaxation if possible. */
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if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
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continue;
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str = start;
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/* Skip this insn if str doesn't look right lexically. */
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if (CGEN_INSN_RX (insn) != NULL &&
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regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
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continue;
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/* Allow parse/insert handlers to obtain length of insn. */
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CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
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parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
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if (parse_errmsg != NULL)
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continue;
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/* ??? 0 is passed for `pc'. */
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insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
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(bfd_vma) 0);
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if (insert_errmsg != NULL)
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continue;
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/* It is up to the caller to actually output the insn and any
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queued relocs. */
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return insn;
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}
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{
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static char errbuf[150];
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const char *tmp_errmsg;
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#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
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#define be_verbose 1
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#else
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#define be_verbose 0
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#endif
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if (be_verbose)
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{
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/* If requesting verbose error messages, use insert_errmsg.
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Failing that, use parse_errmsg. */
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tmp_errmsg = (insert_errmsg ? insert_errmsg :
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parse_errmsg ? parse_errmsg :
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recognized_mnemonic ?
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_("unrecognized form of instruction") :
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_("unrecognized instruction"));
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if (strlen (start) > 50)
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/* xgettext:c-format */
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sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
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2017-04-10 11:32:00 +00:00
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else
|
2014-09-12 22:14:23 +00:00
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/* xgettext:c-format */
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sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
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}
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else
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{
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if (strlen (start) > 50)
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/* xgettext:c-format */
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sprintf (errbuf, _("bad instruction `%.50s...'"), start);
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2017-04-10 11:32:00 +00:00
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else
|
2014-09-12 22:14:23 +00:00
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/* xgettext:c-format */
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sprintf (errbuf, _("bad instruction `%.50s'"), start);
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}
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2017-04-10 11:32:00 +00:00
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2014-09-12 22:14:23 +00:00
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*errmsg = errbuf;
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return NULL;
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}
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}
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